2005-03-30 03:30:46 +08:00
|
|
|
|
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Don't allow the `l' suffix for moving
|
|
|
|
|
|
moving between memory and segment register. Allow movq for
|
|
|
|
|
|
moving between general-purpose register and segment register.
|
|
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|
2005-02-09 16:05:43 +08:00
|
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|
|
2005-02-09 Jan Beulich <jbeulich@novell.com>
|
|
|
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|
|
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|
|
PR gas/707
|
|
|
|
|
|
* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
|
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|
|
|
|
FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
|
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|
|
|
fnstsw.
|
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|
2005-01-26 04:22:35 +08:00
|
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|
2005-01-25 Alexandre Oliva <aoliva@redhat.com>
|
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|
|
|
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|
|
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
* cgen.h (enum cgen_parse_operand_type): Add
|
|
|
|
|
|
CGEN_PARSE_OPERAND_SYMBOLIC.
|
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|
|
2005-01-22 03:42:08 +08:00
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|
2005-01-21 Fred Fish <fnf@specifixinc.com>
|
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|
|
|
* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
|
|
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|
|
Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
|
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|
|
Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
|
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|
2005-01-20 07:29:12 +08:00
|
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|
|
2005-01-19 Fred Fish <fnf@specifixinc.com>
|
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|
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|
|
|
* mips.h (struct mips_opcode): Add new pinfo2 member.
|
|
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|
|
(INSN_ALIAS): New define for opcode table entries that are
|
|
|
|
|
|
specific instances of another entry, such as 'move' for an 'or'
|
|
|
|
|
|
with a zero operand.
|
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|
|
(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
|
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|
(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
|
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|
|
2004-12-09 14:13:44 +08:00
|
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|
2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
|
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|
|
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|
|
|
* mips.h (CPU_RM9000): Define.
|
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|
|
(OPCODE_IS_MEMBER): Handle CPU_RM9000.
|
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|
2004-11-25 16:42:54 +08:00
|
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|
2004-11-25 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
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|
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|
|
|
* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
|
|
|
|
|
|
to/from test registers are illegal in 64-bit mode. Add missing
|
|
|
|
|
|
NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
|
|
|
|
|
|
(previously one had to explicitly encode a rex64 prefix). Re-enable
|
|
|
|
|
|
lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
|
|
|
|
|
|
support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
|
|
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|
|
2004-11-23 Jan Beulich <jbeulich@novell.com>
|
2004-11-23 15:55:12 +08:00
|
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|
|
|
* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
|
|
|
|
|
|
available only with SSE2. Change the MMX additions introduced by SSE
|
|
|
|
|
|
and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
|
|
|
|
|
|
instructions by their now designated identifier (since combining i686
|
|
|
|
|
|
and 3DNow! does not really imply 3DNow!A).
|
|
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|
|
|
2004-11-19 20:28:01 +08:00
|
|
|
|
2004-11-19 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
|
|
|
|
|
|
struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
|
|
|
|
|
|
|
2004-11-08 21:17:39 +08:00
|
|
|
|
2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
|
|
|
|
|
|
Vineet Sharma <vineets@noida.hcltech.com>
|
|
|
|
|
|
|
|
|
|
|
|
* maxq.h: New file: Disassembly information for the maxq port.
|
|
|
|
|
|
|
2004-11-06 07:14:30 +08:00
|
|
|
|
2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Put back "movzb".
|
|
|
|
|
|
|
* cris.h (enum cris_insn_version_usage): Tweak formatting and
comments. Remove member cris_ver_sim. Add members
cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
(struct cris_support_reg, struct cris_cond15): New types.
(cris_conds15): Declare.
(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
(NOP_Z_BITS): Define in terms of NOP_OPCODE.
(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
SIZE_FIELD_UNSIGNED.
2004-11-04 22:53:41 +08:00
|
|
|
|
2004-11-04 Hans-Peter Nilsson <hp@axis.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cris.h (enum cris_insn_version_usage): Tweak formatting and
|
|
|
|
|
|
comments. Remove member cris_ver_sim. Add members
|
|
|
|
|
|
cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
|
|
|
|
|
|
cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
|
|
|
|
|
|
(struct cris_support_reg, struct cris_cond15): New types.
|
|
|
|
|
|
(cris_conds15): Declare.
|
|
|
|
|
|
(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
|
|
|
|
|
|
(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
|
|
|
|
|
|
(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
|
|
|
|
|
|
(NOP_Z_BITS): Define in terms of NOP_OPCODE.
|
|
|
|
|
|
(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
|
|
|
|
|
|
SIZE_FIELD_UNSIGNED.
|
|
|
|
|
|
|
2004-11-25 16:42:54 +08:00
|
|
|
|
2004-11-04 Jan Beulich <jbeulich@novell.com>
|
gas/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (set_intel_syntax): Allow % in symbol names when
intel syntax and no register prefix, allow $ in symbol names when
intel syntax.
(set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX.
(intel_float_operand): Add fourth return value indicating math control
operations. Make classification more precise.
(md_assemble): Complain if memory operand of mov[sz]x has no size
specified.
(parse_insn): Translate word operands to floating point instructions
operating on integers as well as control instructions to short ones
as expected by AT&T syntax. Translate 'd' suffix to short one only for
floating point instructions operating on non-integer operands.
(match_template): Remove fldcw special case. Adjust q-suffix handling
to permit it on fild/fistp/fisttp in AT&T mode.
(process_suffix): Don't guess DefaultSize insns' suffix from
stackop_size for certain floating point control instructions. Guess
suffix for branch and [ls][gi]dt based on flag_code. Split error
messages for Intel and AT&T syntax, and make the condition more strict
for the former. Adjust suppressing of generation of operand size
overrides.
(intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE,
OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add
more error checking.
* config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR
SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines.
gas/testsuite/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* gas/i386/i386.exp: Execute new tests intelbad and intelok.
* gas/i386/intelbad.[sl]: New test to check for various things not
permitted in Intel mode.
* gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d:
Adjust for change to segment register store.
* gas/i386/intelok.[sd]: New test to check various Intel mode specific
things get handled correctly.
* gas/i386/x86_64.[sd]: Remove unsupported constructs referring to
'high' and 'low' parts of an operand, which the parser previously
accepted while neither telling that it's not supported nor that it
ignored the remainder of the line following these supposed keywords.
include/opcode/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386.h (sldx_Suf): Remove.
(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
(q_FP): Define, implying no REX64.
(x_FP, sl_FP): Imply FloatMF.
(i386_optab): Split reg and mem forms of moving from segment registers
so that the memory forms can ignore the 16-/32-bit operand size
distinction. Adjust a few others for Intel mode. Remove *FP uses from
all non-floating-point instructions. Unite 32- and 64-bit forms of
movsx, movzx, and movd. Adjust floating point operations for the above
changes to the *FP macros. Add DefaultSize to floating point control
insns operating on larger memory ranges. Remove left over comments
hinting at certain insns being Intel-syntax ones where the ones
actually meant are already gone.
opcodes/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
(indirEb): Remove.
(Mp): Use f_mode rather than none at all.
(t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
replaces what previously was x_mode; x_mode now means 128-bit SSE
operands.
(dis386): Make far jumps and calls have an 'l' prefix only in AT&T
mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
pinsrw's second operand is Edqw.
(grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
mode when an operand size override is present or always suffixing.
More instructions will need to be added to this group.
(putop): Handle new macro chars 'C' (short/long suffix selector),
'I' (Intel mode override for following macro char), and 'J' (for
adding the 'l' prefix to far branches in AT&T mode). When an
alternative was specified in the template, honor macro character when
specified for Intel mode.
(OP_E): Handle new *_mode values. Correct pointer specifications for
memory operands. Consolidate output of index register.
(OP_G): Handle new *_mode values.
(OP_I): Handle const_1_mode.
(OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
respective opcode prefix bits have been consumed.
(OP_EM, OP_EX): Provide some default handling for generating pointer
specifications.
2004-11-04 17:16:08 +08:00
|
|
|
|
|
|
|
|
|
|
* i386.h (sldx_Suf): Remove.
|
|
|
|
|
|
(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
|
|
|
|
|
|
(q_FP): Define, implying no REX64.
|
|
|
|
|
|
(x_FP, sl_FP): Imply FloatMF.
|
|
|
|
|
|
(i386_optab): Split reg and mem forms of moving from segment registers
|
|
|
|
|
|
so that the memory forms can ignore the 16-/32-bit operand size
|
|
|
|
|
|
distinction. Adjust a few others for Intel mode. Remove *FP uses from
|
|
|
|
|
|
all non-floating-point instructions. Unite 32- and 64-bit forms of
|
|
|
|
|
|
movsx, movzx, and movd. Adjust floating point operations for the above
|
|
|
|
|
|
changes to the *FP macros. Add DefaultSize to floating point control
|
|
|
|
|
|
insns operating on larger memory ranges. Remove left over comments
|
|
|
|
|
|
hinting at certain insns being Intel-syntax ones where the ones
|
|
|
|
|
|
actually meant are already gone.
|
|
|
|
|
|
|
2004-10-07 22:18:17 +08:00
|
|
|
|
2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx.h: Add COPS_REG_INS - Coprocessor Special register
|
|
|
|
|
|
instruction type.
|
|
|
|
|
|
|
2004-10-01 00:21:43 +08:00
|
|
|
|
2004-09-30 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
|
|
|
|
|
|
(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
|
|
|
|
|
|
|
* gas/config/tc-avr.c: Add support for
atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
* include/opcode/avr.h: Add support for
atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2004-09-11 21:15:05 +08:00
|
|
|
|
2004-09-11 Theodore A. Roth <troth@openavr.org>
|
|
|
|
|
|
|
|
|
|
|
|
* avr.h: Add support for
|
|
|
|
|
|
atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
|
|
|
|
|
|
|
2004-09-09 20:42:37 +08:00
|
|
|
|
2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
|
|
|
|
|
|
|
2004-08-25 20:54:15 +08:00
|
|
|
|
2004-08-24 Dmitry Diky <diwil@spec.ru>
|
|
|
|
|
|
|
|
|
|
|
|
* msp430.h (msp430_opc): Add new instructions.
|
|
|
|
|
|
(msp430_rcodes): Declare new instructions.
|
|
|
|
|
|
(msp430_hcodes): Likewise..
|
|
|
|
|
|
|
2004-08-13 16:14:02 +08:00
|
|
|
|
2004-08-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR/301
|
|
|
|
|
|
* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
|
|
|
|
|
|
processors.
|
|
|
|
|
|
|
2004-07-30 20:36:37 +08:00
|
|
|
|
2004-08-30 Michal Ludvig <mludvig@suse.cz>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
|
|
|
|
|
|
|
2004-07-23 03:10:49 +08:00
|
|
|
|
2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
|
|
|
|
|
|
|
2004-07-22 02:18:04 +08:00
|
|
|
|
2004-07-21 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h: Adjust instruction descriptions to better match the
|
|
|
|
|
|
specification.
|
|
|
|
|
|
|
2004-07-17 05:59:35 +08:00
|
|
|
|
2004-07-16 Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm.h: Remove all old content. Replace with architecture defines
|
|
|
|
|
|
from gas/config/tc-arm.c.
|
|
|
|
|
|
|
2004-07-10 02:42:14 +08:00
|
|
|
|
2004-07-09 Andreas Schwab <schwab@suse.de>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k.h: Fix comment.
|
|
|
|
|
|
|
2004-07-08 01:28:50 +08:00
|
|
|
|
2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx.h: New file.
|
|
|
|
|
|
|
2004-06-23 23:06:53 +08:00
|
|
|
|
2004-06-24 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
|
|
|
|
|
|
|
2004-05-24 22:33:21 +08:00
|
|
|
|
2004-05-24 Peter Barada <peter@the-baradas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k.h: Add 'size' to m68k_opcode.
|
|
|
|
|
|
|
2004-05-05 22:33:14 +08:00
|
|
|
|
2004-05-05 Peter Barada <peter@the-baradas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k.h: Switch from ColdFire chip name to core variant.
|
|
|
|
|
|
|
|
|
|
|
|
2004-04-22 Peter Barada <peter@the-baradas.com>
|
2004-04-22 18:33:16 +08:00
|
|
|
|
|
|
|
|
|
|
* m68k.h: Add mcfmac/mcfemac definitions. Update operand
|
|
|
|
|
|
descriptions for new EMAC cases.
|
|
|
|
|
|
Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
|
|
|
|
|
|
handle Motorola MAC syntax.
|
|
|
|
|
|
Allow disassembly of ColdFire V4e object files.
|
|
|
|
|
|
|
opcodes/
* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
PPC_OPERANDS_GPR_0.
* ppc-opc.c (RA0): Define.
(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
(RAOPT): Rename from RAO. Update all uses.
(powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi",
"stsdx", "stsdi", "lmd" and "stmd" insns.
include/opcode/
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
gas/testsuite/
Update gas/ppc/.
ld/testsuite/
Update ld-powerpc/.
2004-03-16 08:58:42 +08:00
|
|
|
|
2004-03-16 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
|
|
|
|
|
|
|
2004-03-21 07:44:18 +08:00
|
|
|
|
2004-03-12 Jakub Jelinek <jakub@redhat.com>
|
|
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* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
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2004-03-12 21:38:46 +08:00
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2004-03-12 Michal Ludvig <mludvig@suse.cz>
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* i386.h (i386_optab): Added xstore as an alias for xstorerng.
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2004-03-12 18:14:29 +08:00
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2004-03-12 Michal Ludvig <mludvig@suse.cz>
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* i386.h (i386_optab): Added xstore/xcrypt insns.
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2004-02-09 20:15:57 +08:00
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2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
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* h8300.h (32bit ldc/stc): Add relaxing support.
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2004-01-12 23:02:20 +08:00
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2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
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opcodes/
* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
PPC_OPERANDS_GPR_0.
* ppc-opc.c (RA0): Define.
(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
(RAOPT): Rename from RAO. Update all uses.
(powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi",
"stsdx", "stsdi", "lmd" and "stmd" insns.
include/opcode/
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
gas/testsuite/
Update gas/ppc/.
ld/testsuite/
Update ld-powerpc/.
2004-03-16 08:58:42 +08:00
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2004-01-12 23:02:20 +08:00
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* h8300.h (BITOP): Pass MEMRELAX flag.
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2004-01-10 01:47:17 +08:00
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2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
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* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
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except for the H8S.
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1999-05-03 15:29:06 +08:00
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2004-01-02 19:16:20 +08:00
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For older changes see ChangeLog-9103
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1999-05-03 15:29:06 +08:00
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Local Variables:
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2004-01-02 19:16:20 +08:00
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mode: change-log
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left-margin: 8
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fill-column: 74
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1999-05-03 15:29:06 +08:00
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version-control: never
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End:
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