2015-10-24 02:24:50 +08:00
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/*
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Copyright (c) 2015, Synopsys, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1) Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2) Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3) Neither the name of the Synopsys, Inc., nor the names of its contributors
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may be used to endorse or promote products derived from this software
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without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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/* This implementation is optimized for performance. For code size a generic
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implementation of this function from newlib/libc/string/memcmp.c will be
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used. */
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#if !defined (__OPTIMIZE_SIZE__) && !defined (PREFER_SIZE_OVER_SPEED)
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#include "asm.h"
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2015-12-16 01:54:58 +08:00
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#if !defined (__ARC601__) && defined (__ARC_NORM__) \
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&& defined (__ARC_BARREL_SHIFTER__)
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2015-10-24 02:24:50 +08:00
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#ifdef __LITTLE_ENDIAN__
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#define WORD2 r2
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#define SHIFT r3
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#else /* BIG ENDIAN */
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#define WORD2 r3
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#define SHIFT r2
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#endif
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ENTRY (memcmp)
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or r12,r0,r1
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asl_s r12,r12,30
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2015-12-16 01:54:58 +08:00
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#if defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__)
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2015-10-24 02:24:50 +08:00
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sub_l r3,r2,1
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brls r2,r12,.Lbytewise
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#else
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brls.d r2,r12,.Lbytewise
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sub_s r3,r2,1
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#endif
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ld r4,[r0,0]
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ld r5,[r1,0]
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lsr.f lp_count,r3,3
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2015-12-16 01:54:58 +08:00
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#ifdef __ARCEM__
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2015-10-24 02:24:50 +08:00
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/* A branch can't be the last instruction in a zero overhead loop.
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So we move the branch to the start of the loop, duplicate it
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after the end, and set up r12 so that the branch isn't taken
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initially. */
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mov_s r12,WORD2
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lpne .Loop_end
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brne WORD2,r12,.Lodd
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ld WORD2,[r0,4]
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#else
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lpne .Loop_end
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ld_s WORD2,[r0,4]
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#endif
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ld_s r12,[r1,4]
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brne r4,r5,.Leven
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ld.a r4,[r0,8]
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ld.a r5,[r1,8]
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2015-12-16 01:54:58 +08:00
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#ifdef __ARCEM__
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2015-10-24 02:24:50 +08:00
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.Loop_end:
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brne WORD2,r12,.Lodd
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#else
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brne WORD2,r12,.Lodd
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2015-12-16 01:54:58 +08:00
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#ifdef __ARCHS__
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2015-10-24 02:24:50 +08:00
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nop
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#endif
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.Loop_end:
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#endif
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asl_s SHIFT,SHIFT,3
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bcc_s .Last_cmp
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brne r4,r5,.Leven
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ld r4,[r0,4]
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ld r5,[r1,4]
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#ifdef __LITTLE_ENDIAN__
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2015-12-16 01:54:58 +08:00
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#if defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__)
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2015-10-24 02:24:50 +08:00
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nop_s
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; one more load latency cycle
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.Last_cmp:
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xor r0,r4,r5
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bset r0,r0,SHIFT
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sub_s r1,r0,1
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bic_s r1,r1,r0
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norm r1,r1
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b.d .Leven_cmp
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and r1,r1,24
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.Leven:
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xor r0,r4,r5
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sub_s r1,r0,1
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bic_s r1,r1,r0
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norm r1,r1
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; slow track insn
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and r1,r1,24
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.Leven_cmp:
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asl r2,r4,r1
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asl r12,r5,r1
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lsr_s r2,r2,1
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lsr_s r12,r12,1
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j_s.d [blink]
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sub r0,r2,r12
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.balign 4
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.Lodd:
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xor r0,WORD2,r12
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sub_s r1,r0,1
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bic_s r1,r1,r0
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norm r1,r1
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; slow track insn
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and r1,r1,24
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asl_s r2,r2,r1
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asl_s r12,r12,r1
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lsr_s r2,r2,1
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lsr_s r12,r12,1
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j_s.d [blink]
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sub r0,r2,r12
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#else /* !__ARC700__ */
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.balign 4
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.Last_cmp:
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xor r0,r4,r5
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b.d .Leven_cmp
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bset r0,r0,SHIFT
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.Lodd:
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mov_s r4,WORD2
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mov_s r5,r12
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.Leven:
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xor r0,r4,r5
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.Leven_cmp:
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mov_s r1,0x80808080
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; uses long immediate
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sub_s r12,r0,1
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bic_s r0,r0,r12
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sub r0,r1,r0
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xor_s r0,r0,r1
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and r1,r5,r0
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and r0,r4,r0
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xor.f 0,r0,r1
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sub_s r0,r0,r1
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j_s.d [blink]
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mov.mi r0,r1
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#endif /* !__ARC700__ */
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#else /* BIG ENDIAN */
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.Last_cmp:
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neg_s SHIFT,SHIFT
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lsr r4,r4,SHIFT
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lsr r5,r5,SHIFT
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; slow track insn
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.Leven:
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sub.f r0,r4,r5
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mov.ne r0,1
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j_s.d [blink]
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bset.cs r0,r0,31
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.Lodd:
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cmp_s WORD2,r12
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2015-12-16 01:54:58 +08:00
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#if defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__)
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2015-10-24 02:24:50 +08:00
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mov_s r0,1
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j_s.d [blink]
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bset.cs r0,r0,31
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2015-12-16 01:54:58 +08:00
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#else
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2015-10-24 02:24:50 +08:00
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j_s.d [blink]
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rrc r0,2
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2015-12-16 01:54:58 +08:00
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#endif /* __ARC700__ || __ARCEM__ || __ARCHS__ */
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2015-10-24 02:24:50 +08:00
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#endif /* ENDIAN */
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.balign 4
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.Lbytewise:
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breq r2,0,.Lnil
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ldb r4,[r0,0]
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ldb r5,[r1,0]
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lsr.f lp_count,r3
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2015-12-16 01:54:58 +08:00
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#ifdef __ARCEM__
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2015-10-24 02:24:50 +08:00
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mov r12,r3
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lpne .Lbyte_end
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brne r3,r12,.Lbyte_odd
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#else
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lpne .Lbyte_end
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#endif
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ldb_s r3,[r0,1]
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ldb_l r12,[r1,1]
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brne r4,r5,.Lbyte_even
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ldb.a r4,[r0,2]
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ldb.a r5,[r1,2]
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2015-12-16 01:54:58 +08:00
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#ifdef __ARCEM__
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2015-10-24 02:24:50 +08:00
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.Lbyte_end:
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brne r3,r12,.Lbyte_odd
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#else
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brne r3,r12,.Lbyte_odd
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2015-12-16 01:54:58 +08:00
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#ifdef __ARCHS__
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2015-10-24 02:24:50 +08:00
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nop
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#endif
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.Lbyte_end:
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#endif
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bcc_l .Lbyte_even
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brne r4,r5,.Lbyte_even
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ldb_s r3,[r0,1]
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ldb_s r12,[r1,1]
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.Lbyte_odd:
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j_s.d [blink]
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sub r0,r3,r12
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.Lbyte_even:
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j_s.d [blink]
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sub r0,r4,r5
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.Lnil:
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j_s.d [blink]
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mov_l r0,0
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ENDFUNC (memcmp)
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2015-12-16 01:54:58 +08:00
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#endif /* !__ARC601__ && __ARC_NORM__ && __ARC_BARREL_SHIFTER__ */
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2015-10-24 02:24:50 +08:00
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#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
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