82 lines
2.9 KiB
C
82 lines
2.9 KiB
C
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/*
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(c) Copyright 2017 Michael R. Neilly
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the names of the copyright holders nor the names of their
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <fenv.h>
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#include <stddef.h>
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/* This implementation is intended to comply with the following
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* specification:
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*
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* http://pubs.opengroup.org/onlinepubs/009695399/functions/feclearexcept.html
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* Referred to as 'feclearexcept.html below.
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*
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* "The feclearexcept() function shall attempt to clear the supported
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* floating-point exceptions represented by excepts."
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*/
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int feclearexcept(int excepts)
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{
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#if __riscv_flen
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/* Mask excepts to be sure only supported flag bits are set */
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excepts &= FE_ALL_EXCEPT;
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/* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA:
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* Version 2.1":
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*
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* "The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads
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* the value of the CSR, zeroextends the value to XLEN bits, and
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* writes it to integer register rd. The initial value in integer
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* register rs1 is treated as a bit mask that specifies bit
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* positions to be cleared in the CSR. Any bit that is high in rs1
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* will cause the corresponding bit to be cleared in the CSR, if
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* that CSR bit is writable. Other bits in the CSR are unaffected."
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*/
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/* Clear the requested flags */
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asm volatile("csrrc zero, fflags, %0" : : "r"(excepts));
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/* Per 'feclearexcept.html
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* "If the argument is zero or if all the specified exceptions were
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* successfully cleared, feclearexcept() shall return zero. Otherwise,
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* it shall return a non-zero value."
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*/
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#endif
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return 0;
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}
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