424 lines
15 KiB
C
424 lines
15 KiB
C
/******************************************************************************
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* * *** ***
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* *** *** ***
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* *** **** ********** *** ***** *** **** *****
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* ********* ********** *** ********* ************ *********
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* **** *** *** *** *** **** ***
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* *** *** ****** *** *********** *** **** *****
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* *** *** ****** *** ************* *** **** *****
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* *** **** **** *** *** *** **** ***
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* *** ******* ***** ************** ************* *********
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* *** ***** *** ******* ** ** ****** *****
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* t h e r e a l t i m e t a r g e t e x p e r t s
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*
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* http://www.rt-labs.com
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* Copyright (C) 2006. rt-labs AB, Sweden. All rights reserved.
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*------------------------------------------------------------------------------
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* $Id: lw_emac.c 348 2012-10-18 16:41:14Z rtlfrm $
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*
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*
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*------------------------------------------------------------------------------
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*/
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#include <bsp.h>
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#include <kern.h>
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#include <config.h>
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#include <bfin_dma.h>
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#include <string.h>
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#include "lw_emac.h"
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/* MII standard registers.
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See IEEE Std 802.3-2005 clause 22:
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"Reconciliation Sublayer (RS) and Media Independent Interface (MII)",
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section 2.4.1 to 3.
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http://standards.ieee.org/getieee802/download/802.3-2005_section2.pdf */
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#define MII_BMCR 0x00 /* Basic Mode Control Register */
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#define MII_BMSR 0x01 /* Basic Mode Status Register */
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#define MII_PHYIDR1 0x02 /* PHY Identifier Register 1 */
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#define MII_PHYIDR2 0x03 /* PHY Identifier Register 2 */
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#define MII_LPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */
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/* MII basic mode control register */
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#define MII_BMCR_RST BIT (15)
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#define MII_BMCR_ANEG_EN BIT (12)
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#define MII_BMCR_ANEG_RST BIT (9)
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/* MII basic mode status register */
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#define MII_BMSR_ANEGACK BIT (5)
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#define MII_BMSR_LINK BIT (2)
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/* MII auto-negotiation advertisement register */
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#define MII_ANAR_100_FD BIT (8) /* Can do 100BASE-TX full duplex */
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#define MII_ANAR_10_FD BIT (6) /* Can do 10BASE-T full duplex */
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/* Management Data Clock (MDC) frequency.
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* 2.5Mz corresponds to the minimum period for MDC as defined by the standard.
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* This is independent of whether the PHY is in 10Mbit/s or 100Mbit/s mode.
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* See Std. IEEE 802.3 (Ethernet) Clause 22.2.2.11 ("management data clock"). */
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#define PHY_MDC_Hz 2500000
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#define PHY_RETRIES 3000
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/* TODO: This might need changing for different boards. Fix? */
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#define PHY_ADDR 0
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#define ETH_RX_BUF_SIZE 2
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#define ETH_TX_BUF_SIZE 1
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#define ETH_FRAME_SIZE 0x614
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/* Ethernet MAC register structure */
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typedef struct bfin_emac_regs
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{
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/* Control-Status Register Group */
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uint32_t opmode; /* operating mode */
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uint32_t addrlo; /* address low */
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uint32_t addrhi; /* address high */
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uint32_t hashlo; /* multicast hash table low */
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uint32_t hashhi; /* multicast hash table high */
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uint32_t staadd; /* station management address */
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uint32_t stadat; /* station management data */
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uint32_t flc; /* flow control */
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uint32_t vlan1; /* VLAN1 tag */
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uint32_t vlan2; /* VLAN2 tag */
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uint32_t _reserved1;
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uint32_t wkup_ctl; /* wakeup frame control and status */
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uint32_t wkup_ffmsk[4]; /* wakeup frame n byte mask (n == 0,..,3) */
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uint32_t wkup_ffcmd; /* wakeup frame filter commands */
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uint32_t wkup_ffoff; /* wakeup frame filter offsets */
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uint32_t wkup_ffcrc0; /* wakeup frame filter CRC0/1 */
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uint32_t wkup_ffcrc1; /* wakeup frame filter CRC2/3 */
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uint32_t _reserved2[4];
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/* System Interface Register Group */
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uint32_t sysctl; /* system control */
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uint32_t systat; /* system status */
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/* Ethernet Frame Status Register Group */
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uint32_t rx_stat; /* RX Current Frame Status */
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uint32_t rx_stky; /* RX Sticky Frame Status */
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uint32_t rx_irqe; /* RX Frame Status Interrupt Enable */
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uint32_t tx_stat; /* TX Current Frame Status Register */
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uint32_t tx_stky; /* TT Sticky Frame Status */
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uint32_t tx_irqe; /* TX Frame Status Interrupt Enable */
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/* MAC Management Counter Register Group */
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uint32_t mmc_ctl; /* Management Counters Control */
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uint32_t mmc_rirqs; /* MMC RX Interrupt Status */
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uint32_t mmc_rirqe; /* MMC RX Interrupt Enable */
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uint32_t mmc_tirqs; /* MMC TX Interrupt Status */
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uint32_t mmc_tirqe; /* MMC TX Interrupt Enable */
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uint32_t _reserved3[27];
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uint32_t mmc_rxc_ok; /* FramesReceivedOK */
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uint32_t mmc_rxc_fcs; /* FrameCheckSequenceErrors */
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uint32_t mmc_rxc_align; /* AlignmentErrors */
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uint32_t mmc_rxc_octet; /* OctetsReceivedOK */
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uint32_t mmc_rxc_dmaovf; /* FramesLostDueToIntMACRcvError */
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uint32_t mmc_rxc_unicst; /* UnicastFramesReceivedOK */
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uint32_t mmc_rxc_multi; /* MulticastFramesReceivedOK */
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uint32_t mmc_rxc_broad; /* BroadcastFramesReceivedOK */
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uint32_t mmc_rxc_lnerri; /* InRangeLengthErrors */
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uint32_t mmc_rxc_lnerro; /* OutOfRangeLengthField */
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uint32_t mmc_rxc_long; /* FrameTooLongErrors */
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uint32_t mmc_rxc_macctl; /* MACControlFramesReceived */
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uint32_t mmc_rxc_opcode; /* UnsupportedOpcodesReceived */
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uint32_t mmc_rxc_pause; /* PAUSEMACCtrlFramesReceived */
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uint32_t mmc_rxc_allfrm; /* FramesReceivedAll */
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uint32_t mmc_rxc_alloct; /* OctetsReceivedAll */
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uint32_t mmc_rxc_typed; /* TypedFramesReceived */
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uint32_t mmc_rxc_short; /* FramesLenLt64Received */
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uint32_t mmc_rxc_eq64; /* FramesLenEq64Received */
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uint32_t mmc_rxc_lt128; /* FramesLen65_127Received */
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uint32_t mmc_rxc_lt256; /* FramesLen128_255Received */
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uint32_t mmc_rxc_lt512; /* FramesLen256_511Received */
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uint32_t mmc_rxc_lt1024; /* FramesLen512_1023Received */
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uint32_t mmc_rxc_ge1024; /* FramesLen1024_MaxReceived */
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/* TODO: add all registers */
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} bfin_emac_regs_t;
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COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, opmode) == 0x0);
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COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, staadd) == 0x14);
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COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, wkup_ctl) == 0x2c);
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COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, wkup_ffcrc1) == 0x4c);
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COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, sysctl) == 0x60);
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COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, rx_stat) == 0x68);
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COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, mmc_ctl) == 0x80);
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COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, mmc_tirqe) == 0x90);
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COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, mmc_rxc_ok) == 0x100);
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COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, mmc_rxc_dmaovf) == 0x110);
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COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, mmc_rxc_ge1024) == 0x15c);
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/* 32-bit aligned struct for ethernet data */
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typedef struct ethernet_data {
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uint16_t length; /* When TX = frame data length in bytes, not including 'length'
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* When RX = 0x0000 padding when using RXDWA
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*/
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uint8_t data[ETH_FRAME_SIZE]; /* Hold the ethernet frame */
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uint16_t padding; /* To make the struct 32-bit aligned */
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} ethernet_data_t;
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COMPILETIME_ASSERT (sizeof (ethernet_data_t) == 0x618) ;
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static volatile bfin_emac_regs_t * pEth = (bfin_emac_regs_t *) EMAC_OPMODE;
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/* Buffers for rx and tx DMA operations */
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static ethernet_data_t rxBuffer[ETH_RX_BUF_SIZE] __attribute__((section(".dma")));
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static ethernet_data_t txBuffer[ETH_TX_BUF_SIZE] __attribute__((section(".dma")));
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static volatile uint32_t rxStatusWord[ETH_RX_BUF_SIZE] __attribute__((section(".dma")));
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static volatile uint32_t txStatusWord[ETH_TX_BUF_SIZE] __attribute__((section(".dma")));
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static bfin_dma_descriptor_t rxDMADesc[ETH_RX_BUF_SIZE * 2] __attribute__((section(".dma")));
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static bfin_dma_descriptor_t txDMADesc[ETH_TX_BUF_SIZE * 2] __attribute__((section(".dma")));
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/* Hold the current index of rx and tx buffers */
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static uint8_t rxIdx, txIdx;
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/* Internal function that writes to a PHY register */
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static void lw_emac_write_phy_reg(uint8_t phy_addr, uint8_t reg_addr, uint32_t data) {
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/* Set the flags that should be set reg_addr on PHY */
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pEth->stadat = data;
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/* Wait for our turn then initiate writing of stadat to PHY register */
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pEth->staadd = SET_PHYAD(phy_addr) | SET_REGAD(reg_addr) | STAOP | STABUSY;
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while (pEth->staadd & STABUSY) ;
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}
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/* Internal function that reads from; and returns a PHY register */
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static uint32_t lw_emac_read_phy_reg(uint8_t phy_addr, uint8_t reg_addr) {
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pEth->staadd = SET_PHYAD(phy_addr) | SET_REGAD(reg_addr) | STABUSY;
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while (pEth->staadd & STABUSY) ;
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return pEth->stadat;
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}
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/* Internal function that sets the MAC address */
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static void lw_emac_set_mac_addr(uint8_t * ethAddr)
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{
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pEth->addrlo =
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ethAddr[0] |
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ethAddr[1] << 8 |
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ethAddr[2] << 16 |
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ethAddr[3] << 24;
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pEth->addrhi =
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ethAddr[4] |
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ethAddr[5] << 8;
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}
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static uint8_t lw_emac_init_registers(uint8_t * ethAddr) {
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uint32_t clock_divisor, sysctl_mdcdiv, phy_stadat, counter;
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/* CONFIGURE MAC MII PINS */
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/* Enable PHY Clock Output */
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*(volatile uint16_t *) VR_CTL |= PHYCLKOE;
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/* Set all bits to 1 to use MII mode */
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*(uint16_t *) PORTH_FER = 0xFFFF;
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/* CONFIGURE MAC REGISTERS */
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/*
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* Set the MMC (MAC Management Counter) control register
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* RTSC = Clear all counters
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*
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* Note that counters are not enabled at this time
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*/
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pEth->mmc_ctl = RSTC;
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/* Set MAC address */
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lw_emac_set_mac_addr (ethAddr);
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clock_divisor = SCLK / PHY_MDC_Hz;
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sysctl_mdcdiv = clock_divisor / 2 - 1;
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ASSERT (sysctl_mdcdiv <= 0x3f);
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rprintp ("PHY ID: %04x %04x\n",
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lw_emac_read_phy_reg (PHY_ADDR, MII_PHYIDR1),
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lw_emac_read_phy_reg (PHY_ADDR, MII_PHYIDR2)
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);
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/*
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* Set the system control register
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* SET_MDCDIV(x) = Set MDC to 2.5 MHz
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* RXDWA = Pad incoming frame with 0x0000 as to make the data-part 32-bit aligned
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* RXCKS = Enable Receive Frame TCP/UDP Checksum Computation
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*/
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pEth->sysctl = SET_MDCDIV(sysctl_mdcdiv) | RXDWA ;
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/* CONFIGURE PHY */
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/*
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* Set the PHY basic control register
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* MII_BMCR_ANEG_EN = Auto negotiation on
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* MII_BMCR_ANEG_RST = Restart the auto-neg process by setting
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* Speed handled by auto negotiation
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*/
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phy_stadat = MII_BMCR_ANEG_EN | MII_BMCR_ANEG_RST;
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lw_emac_write_phy_reg(PHY_ADDR, MII_BMCR, phy_stadat);
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/* Loop until link is up or time out after PHY_RETRIES */
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counter = 0;
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do {
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if (counter > PHY_RETRIES) {
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rprintp("Ethernet link is down\n");
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return -1;
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}
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task_delay (tick_from_ms (10));
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phy_stadat = lw_emac_read_phy_reg(PHY_ADDR, MII_BMSR);
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++counter;
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} while (!(phy_stadat & MII_BMSR_LINK)) ;
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/* Check whether link partner can do full duplex or not */
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phy_stadat = lw_emac_read_phy_reg(PHY_ADDR, MII_LPAR);
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if (phy_stadat & (MII_ANAR_100_FD | MII_ANAR_10_FD) ) {
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pEth->opmode = FDMODE;
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}
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else {
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pEth->opmode = 0;
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}
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/*
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* Setup DMA MAC receive/transfer channels with XCOUNT 0 (which we use
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* together with description based DMA) and XMODIFY 4 (bytes per transfer)
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*/
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bfin_dma_channel_init(DMA_CHANNEL_EMAC_RX, 0, 4);
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bfin_dma_channel_init(DMA_CHANNEL_EMAC_TX, 0, 4);
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return 0;
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}
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int bfin_EMAC_init (uint8_t *ethAddr)
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{
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rxIdx = txIdx = 0;
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if (lw_emac_init_registers(ethAddr) != 0) {
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return -1;
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}
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// Reset status words
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memset ((uint8_t *)rxStatusWord, 0, sizeof(rxStatusWord));
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memset ((uint8_t *)txStatusWord, 0, sizeof(txStatusWord));
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txDMADesc[0].next = &txDMADesc[1];
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txDMADesc[0].start_addr = &txBuffer[0];
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txDMADesc[0].config = DMA_CONFIG_DMA_EN |
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DMA_CONFIG_WDSIZE(DMA_WDSIZE_32BIT) |
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DMA_CONFIG_NDSIZE(5) |
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DMA_CONFIG_FLOW(DMA_FLOW_DESCRIPTOR_LIST_LARGE);
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txDMADesc[1].next = &txDMADesc[0];
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txDMADesc[1].start_addr = &txStatusWord[0];
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txDMADesc[1].config = DMA_CONFIG_DMA_EN |
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DMA_CONFIG_WNR |
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DMA_CONFIG_WDSIZE(DMA_WDSIZE_32BIT) |
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DMA_CONFIG_NDSIZE(0) |
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DMA_CONFIG_FLOW(DMA_FLOW_STOP);
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rxDMADesc[0].next = &rxDMADesc[1];
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rxDMADesc[0].start_addr = &rxBuffer[0];
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rxDMADesc[0].config = DMA_CONFIG_DMA_EN |
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DMA_CONFIG_WNR |
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DMA_CONFIG_WDSIZE(DMA_WDSIZE_32BIT) |
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DMA_CONFIG_NDSIZE(5) |
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DMA_CONFIG_FLOW(DMA_FLOW_DESCRIPTOR_LIST_LARGE);
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rxDMADesc[1].next = &rxDMADesc[2];
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rxDMADesc[1].start_addr = &rxStatusWord[0];
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rxDMADesc[1].config = DMA_CONFIG_DMA_EN |
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DMA_CONFIG_WNR |
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DMA_CONFIG_WDSIZE(DMA_WDSIZE_32BIT) |
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DMA_CONFIG_NDSIZE(5) |
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DMA_CONFIG_FLOW(DMA_FLOW_DESCRIPTOR_LIST_LARGE);
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rxDMADesc[2].next = &rxDMADesc[3];
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rxDMADesc[2].start_addr = &rxBuffer[1];
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rxDMADesc[2].config = DMA_CONFIG_DMA_EN |
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DMA_CONFIG_WNR |
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DMA_CONFIG_WDSIZE(DMA_WDSIZE_32BIT) |
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DMA_CONFIG_NDSIZE(5) |
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DMA_CONFIG_FLOW(DMA_FLOW_DESCRIPTOR_LIST_LARGE);
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rxDMADesc[3].next = &rxDMADesc[0];
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rxDMADesc[3].start_addr = &rxStatusWord[1];
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rxDMADesc[3].config = DMA_CONFIG_DMA_EN |
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DMA_CONFIG_WNR |
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DMA_CONFIG_WDSIZE(DMA_WDSIZE_32BIT) |
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DMA_CONFIG_NDSIZE(5) |
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DMA_CONFIG_FLOW(DMA_FLOW_DESCRIPTOR_LIST_LARGE);
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bfin_dma_channel_enable(DMA_CHANNEL_EMAC_RX, &rxDMADesc[0]);
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/* Enable Receiving, Automatic Pad Stripping and receiving of frames with length < 64 butes */
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pEth->opmode |= ASTP | PSF | RE;
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return 0;
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}
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int bfin_EMAC_send (void *packet, int length)
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{
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UASSERT(length > 0, EARG);
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UASSERT(length < ETH_FRAME_SIZE, EARG);
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/* TODO: Check DMA Error in IRQ status */
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while (bfin_dma_channel_interrupt_is_active (DMA_CHANNEL_EMAC_TX));
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txBuffer[txIdx].length = length;
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memcpy(txBuffer[txIdx].data, packet, length);
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bfin_dma_channel_enable(DMA_CHANNEL_EMAC_TX, txDMADesc);
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pEth->opmode |= TE;
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while ((txStatusWord[txIdx] & TX_COMP) == 0);
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ASSERT(txStatusWord[txIdx] & TX_OK);
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txStatusWord[txIdx] = 0;
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++txIdx;
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if (txIdx == ETH_TX_BUF_SIZE) {
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txIdx = 0;
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}
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return 0;
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}
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int bfin_EMAC_recv (uint8_t * packet, size_t size)
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{
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uint32_t length;
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uint32_t status = rxStatusWord[rxIdx];
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/* Check if rx frame is completed */
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if ((status & RX_COMP) == 0) {
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return -1;
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}
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else if ((status & RX_OK) == 0) {
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ASSERT(0);
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/* TODO: Handle error */
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return -1;
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}
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else if (status & RX_DMAO) {
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ASSERT(0);
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/* TODO: Handle overrun */
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return -1;
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}
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length = status & RX_FRLEN;
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if (size < length) {
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length = size;
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}
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memcpy(packet, rxBuffer[rxIdx].data, length);
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bfin_dma_channel_interrupt_clear (DMA_CHANNEL_EMAC_RX);
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rxStatusWord[rxIdx] = 0;
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++rxIdx;
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if (rxIdx == ETH_RX_BUF_SIZE) {
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rxIdx = 0;
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}
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return length;
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}
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