diff --git a/BSP/inc/bsp.h b/BSP/inc/bsp.h index f2b4de0..2d57885 100644 --- a/BSP/inc/bsp.h +++ b/BSP/inc/bsp.h @@ -43,7 +43,7 @@ // Internal SRAM memory size[Kbytes] <8-64> // Default: 64 -#define STM32_SRAM_SIZE 64 +#define STM32_SRAM_SIZE 20 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) diff --git a/FreeModbus/modbus/rtu/mbrtu_m.c b/FreeModbus/modbus/rtu/mbrtu_m.c index 1629f39..0460b37 100644 --- a/FreeModbus/modbus/rtu/mbrtu_m.c +++ b/FreeModbus/modbus/rtu/mbrtu_m.c @@ -160,7 +160,7 @@ eMBMasterRTUReceive( UCHAR * pucRcvAddress, UCHAR ** pucFrame, USHORT * pusLengt eMBErrorCode eStatus = MB_ENOERR; ENTER_CRITICAL_SECTION( ); - assert_param( usRcvBufferPos < MB_SER_PDU_SIZE_MAX ); + assert_param( usMasterRcvBufferPos < MB_SER_PDU_SIZE_MAX ); /* Length and CRC check */ if( ( usMasterRcvBufferPos >= MB_SER_PDU_SIZE_MIN ) @@ -235,7 +235,7 @@ xMBMasterRTUReceiveFSM( void ) BOOL xTaskNeedSwitch = FALSE; UCHAR ucByte; - assert_param( eSndState == STATE_TX_IDLE ); + assert_param( eSndState == STATE_M_TX_IDLE ); /* Always read the character. */ ( void )xMBMasterPortSerialGetByte( ( CHAR * ) & ucByte ); @@ -301,7 +301,7 @@ xMBMasterRTUTransmitFSM( void ) { BOOL xNeedPoll = FALSE; - assert_param( eRcvState == STATE_RX_IDLE ); + assert_param( eRcvState == STATE_M_RX_IDLE ); switch ( eSndState ) { diff --git a/FreeModbus/port/portserial.c b/FreeModbus/port/portserial.c index 1e9cfa1..32067c4 100644 --- a/FreeModbus/port/portserial.c +++ b/FreeModbus/port/portserial.c @@ -183,7 +183,6 @@ void USART1_IRQHandler(void) //·¢ËÍÖÐ¶Ï if (USART_GetITStatus(USART1, USART_IT_TXE) == SET) { - USART_ClearITPendingBit(USART1, USART_IT_TXE); prvvUARTTxReadyISR(); } rt_interrupt_leave(); diff --git a/FreeModbus/port/portserial_m.c b/FreeModbus/port/portserial_m.c index ddbb70a..fa062b7 100644 --- a/FreeModbus/port/portserial_m.c +++ b/FreeModbus/port/portserial_m.c @@ -184,7 +184,6 @@ void USART2_IRQHandler(void) //·¢ËÍÖÐ¶Ï if (USART_GetITStatus(USART2, USART_IT_TXE) == SET) { - USART_ClearITPendingBit(USART2, USART_IT_TXE); prvvUARTTxReadyISR(); } rt_interrupt_leave();