tj-kicad-lib/tools/stm32f407_100pin.csv

1	pin,pin_name,locate
2	X BOOT0/VPP 94 2300 9900 100 L 50 50 1 1 B
3	X NRST/RST 14 2300 9800 100 L 50 50 1 1 B
4	X PA0/WKUP/(PA0)/USART2_CTS/UART4_TX/ETH_MII_CRS/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/ADC123_IN0/WKUP 23 2300 9700 100 L 50 50 1 1 B
5	X PA1/USART2_RTS/UART4_RX/ETH_RMII_REF_CLK/ETH_MII_RX_CLK/TIM5_CH2/TIM2_CH2/ADC123_IN1 24 2300 9600 100 L 50 50 1 1 B
6	X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/ETH_MDIO/ADC123_IN2 25 2300 9500 100 L 50 50 1 1 B
7	X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/ETH_MII_COL/ADC123_IN3 26 2300 9400 100 L 50 50 1 1 B
8	X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/DCMI_HSYNC/OTG_HS_SOF/I2S3_WS/ADC12_IN4/DAC_OUT1 29 2300 9300 100 L 50 50 1 1 B
9	X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CH1N/ADC12_IN5/DAC_OUT2 30 2300 9200 100 L 50 50 1 1 B
10	X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/DCMI_PIXCLK/TIM3_CH1/TIM1_BKIN/ADC12_IN6 31 2300 9100 100 L 50 50 1 1 B
11	X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV/TIM1_CH1N/ETH_RMII_CRS_DV/ADC12_IN7 32 2300 9000 100 L 50 50 1 1 B
12	X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF 67 2300 8900 100 L 50 50 1 1 B
13	X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/DCMI_D0/OTG_FS_VBUS 68 2300 8800 100 L 50 50 1 1 B
14	X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/DCMI_D1 69 2300 8700 100 L 50 50 1 1 B
15	X PA11/USART1_CTS/CAN1_RX/TIM1_CH4/OTG_FS_DM 70 2300 8600 100 L 50 50 1 1 B
16	X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP 71 2300 8500 100 L 50 50 1 1 B
17	X PA13/(JTMS-SWDIO)/JTMS-SWDIO 72 2300 8400 100 L 50 50 1 1 B
18	X PA14/(JTCK/SWCLK)/JTCK-SWCLK 76 2300 8300 100 L 50 50 1 1 B
19	X PA15/(JTDI)/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS 77 2300 8200 100 L 50 50 1 1 B
20	X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/ETH_MII_RXD2/TIM1_CH2N/ADC12_IN8 35 2300 8100 100 L 50 50 1 1 B
21	X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/ETH_MII_RXD3/TIM1_CH3N/ADC12_IN9 36 2300 8000 100 L 50 50 1 1 B
22	X PB2/BOOT1/(PB2) 37 2300 7900 100 L 50 50 1 1 B
23	X PB3/(JTDO/TRACESWO)/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK 89 2300 7800 100 L 50 50 1 1 B
24	X PB4/(NJTRST)/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD 90 2300 7700 100 L 50 50 1 1 B
25	X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/ETH_PPS_OUT/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/DCMI_D10/I2S3_SD 91 2300 7600 100 L 50 50 1 1 B
26	X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/DCMI_D5/USART1_TX 92 2300 7500 100 L 50 50 1 1 B
27	X PB7/I2C1_SDA/FSMC_NL/DCMI_VSYNC/USART1_RX/TIM4_CH2 93 2300 7400 100 L 50 50 1 1 B
28	X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/DCMI_D6/ETH_MII_TXD3/I2C1_SCL/CAN1_RX 95 2300 7300 100 L 50 50 1 1 B
29	X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/DCMI_D7/I2C1_SDA/CAN1_TX 96 2300 7200 100 L 50 50 1 1 B
30	X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/ETH_MII_RX_ER/TIM2_CH3 47 2300 7100 100 L 50 50 1 1 B
31	X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/ETH_RMII_TX_EN/ETH_MII_TX_EN/TIM2_CH4 48 2300 7000 100 L 50 50 1 1 B
32	X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/ETH_RMII_TXD0/ETH_MII_TXD0/OTG_HS_ID 51 2300 6900 100 L 50 50 1 1 B
33	X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/ETH_RMII_TXD1/ETH_MII_TXD1/OTG_HS_VBUS 52 2300 6800 100 L 50 50 1 1 B
34	X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD 53 2300 6700 100 L 50 50 1 1 B
35	X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/RTC_REFIN 54 2300 6600 100 L 50 50 1 1 B
36	X PC0/OTG_HS_ULPI_STP/ADC123_IN10 15 2300 6500 100 L 50 50 1 1 B
37	X PC1/ETH_MDC/ADC123_IN11 16 2300 6400 100 L 50 50 1 1 B
38	X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/ETH_MII_TXD2/I2S2ext_SD/ADC123_IN12 17 2300 6300 100 L 50 50 1 1 B
39	X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/ETH_MII_TX_CLK/ADC123_IN13 18 2300 6200 100 L 50 50 1 1 B
40	X PC4/ETH_RMII_RX_D0/ETH_MII_RX_D0/ADC12_IN14 33 2300 6100 100 L 50 50 1 1 B
41	X PC5/ETH_RMII_RX_D1/ETH_MII_RX_D1/ADC12_IN15 34 2300 6000 100 L 50 50 1 1 B
42	X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/DCMI_D0/TIM3_CH1 63 2300 5900 100 L 50 50 1 1 B
43	X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/DCMI_D1/TIM3_CH2 64 2300 5800 100 L 50 50 1 1 B
44	X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/DCMI_D2 65 2300 5700 100 L 50 50 1 1 B
45	X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1//I2C3_SDA/DCMI_D3/TIM3_CH4 66 2300 5600 100 L 50 50 1 1 B
46	X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/DCMI_D8/USART3_TX 78 2300 5500 100 L 50 50 1 1 B
47	X PC11/UART4_RX/SPI3_MISO/SDIO_D3/DCMI_D4/USART3_RX/I2S3ext_SD 79 2300 5400 100 L 50 50 1 1 B
48	X PC12/UART5_TX/SDIO_CK/DCMI_D9/SPI3_MOSI/I2S3_SD/USART3_CK 80 2300 5300 100 L 50 50 1 1 B
49	X PC13/RTC_OUT/RTC_TAMP1/RTC_TS 7 2300 5200 100 L 50 50 1 1 B
50	X PC14/OSC32_IN/(PC14)/OSC32_IN 8 2300 5100 100 L 50 50 1 1 B
51	X PC15/OSC32_OUT/(PC15)/OSC32_OUT 9 2300 5000 100 L 50 50 1 1 B
52	X PD0/FSMC_D2/CAN1_RX 81 2300 4900 100 L 50 50 1 1 B
53	X PD1/FSMC_D3/CAN1_TX 82 2300 4800 100 L 50 50 1 1 B
54	X PD2/TIM3_ETR/UART5_RX/SDIO_CMD/DCMI_D11 83 2300 4700 100 L 50 50 1 1 B
55	X PD3/FSMC_CLK/USART2_CTS 84 2300 4600 100 L 50 50 1 1 B
56	X PD4/FSMC_NOE/USART2_RTS 85 2300 4500 100 L 50 50 1 1 B
57	X PD5/FSMC_NWE/USART2_TX 86 2300 4400 100 L 50 50 1 1 B
58	X PD6/FSMC_NWAIT/USART2_RX 87 2300 4300 100 L 50 50 1 1 B
59	X PD7/USART2_CK/FSMC_NE1/FSMC_NCE2 88 2300 4200 100 L 50 50 1 1 B
60	X PD8/FSMC_D13/USART3_TX 55 2300 4100 100 L 50 50 1 1 B
61	X PD9/FSMC_D14/USART3_RX 56 2300 4000 100 L 50 50 1 1 B
62	X PD10/FSMC_D15/USART3_CK 57 2300 3900 100 L 50 50 1 1 B
63	X PD11/FSMC_CLE/FSMC_A16/USART3_CTS 58 2300 3800 100 L 50 50 1 1 B
64	X PD12/FSMC_ALE/FSMC_A17/TIM4_CH1/USART3_RTS 59 2300 3700 100 L 50 50 1 1 B
65	X PD13/FSMC_A18/TIM4_CH2 60 2300 3600 100 L 50 50 1 1 B
66	X PD14/FSMC_D0/TIM4_CH3 61 2300 3500 100 L 50 50 1 1 B
67	X PD15/FSMC_D1/TIM4_CH4 62 2300 3400 100 L 50 50 1 1 B
68	X PE0/TIM4_ETR/FSMC_NBL0/DCMI_D2 97 2300 3300 100 L 50 50 1 1 B
69	X PE1/FSMC_NBL1/DCMI_D3 98 2300 3200 100 L 50 50 1 1 B
70	X PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3 1 2300 3100 100 L 50 50 1 1 B
71	X PE3/TRACED0/FSMC_A19 2 2300 3000 100 L 50 50 1 1 B
72	X PE4/TRACED1/FSMC_A20/DCMI_D4 3 2300 2900 100 L 50 50 1 1 B
73	X PE5/TRACED2/FSMC_A21/TIM9_CH1/DCMI_D6 4 2300 2800 100 L 50 50 1 1 B
74	X PE6/TRACED3/FSMC_A22/TIM9_CH2/DCMI_D7 5 2300 2700 100 L 50 50 1 1 B
75	X PE7/FSMC_D4/TIM1_ETR 38 2300 2600 100 L 50 50 1 1 B
76	X PE8/FSMC_D5/TIM1_CH1N 39 2300 2500 100 L 50 50 1 1 B
77	X PE9/FSMC_D6/TIM1_CH1 40 2300 2400 100 L 50 50 1 1 B
78	X PE10/FSMC_D7/TIM1_CH2N 41 2300 2300 100 L 50 50 1 1 B
79	X PE11/FSMC_D8/TIM1_CH2 42 2300 2200 100 L 50 50 1 1 B
80	X PE12/FSMC_D9/TIM1_CH3N 43 2300 2100 100 L 50 50 1 1 B
81	X PE13/FSMC_D10/TIM1_CH3 44 2300 2000 100 L 50 50 1 1 B
82	X PE14/FSMC_D11/TIM1_CH4 45 2300 1900 100 L 50 50 1 1 B
83	X PE15/FSMC_D12/TIM1_BKIN 46 2300 1800 100 L 50 50 1 1 B
84	X PH0/OSC_IN/(PH0)/OSC_IN 12 2300 1700 100 L 50 50 1 1 B
85	X PH1/OSC_OUT/(PH1)/OSC_OUT 13 2300 1600 100 L 50 50 1 1 B
86	X VBAT 6 2300 1500 100 L 50 50 1 1 B
87	X VCAP_1 49 2300 1400 100 L 50 50 1 1 B
88	X VCAP_2 73 2300 1300 100 L 50 50 1 1 B
89	X VDD 11 2300 1200 100 L 50 50 1 1 B
90	X VDD 19 2300 1100 100 L 50 50 1 1 B
91	X VDD 28 2300 1000 100 L 50 50 1 1 B
92	X VDD 50 2300 900 100 L 50 50 1 1 B
93	X VDD 75 2300 800 100 L 50 50 1 1 B
94	X VDD 100 2300 700 100 L 50 50 1 1 B
95	X VDDA 22 2300 600 100 L 50 50 1 1 B
96	X VREF+ 21 2300 500 100 L 50 50 1 1 B
97	X VSS 10 2300 400 100 L 50 50 1 1 B
98	X VSS 27 2300 300 100 L 50 50 1 1 B
99	X VSS 74 2300 200 100 L 50 50 1 1 B
100	X VSS 99 2300 100 100 L 50 50 1 1 B
101	X VSSA 20 2300 0 100 L 50 50 1 1 B