stm32f407

This commit is contained in:
chinky 2020-07-04 18:32:31 +08:00
parent b442d6a471
commit 132b9f3b1f
6 changed files with 3686 additions and 2792 deletions

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@ -70,6 +70,18 @@ $CMP STM32F401RETx
F https://www.st.com/resource/en/datasheet/stm32f401re.pdf
$ENDCMP
#
$CMP STM32F407VETx
D ARM Cortex-M4 MCU, 512KB flash, 128KB RAM, 168MHz, 1.8-3.6V, 82 GPIO, LQFP-100
K ARM Cortex-M4 STM32F4 STM32F407/417
F http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00037051.pdf
$ENDCMP
#
$CMP STM32F407VGTx
D ARM Cortex-M4 MCU, 1024KB flash, 128KB RAM, 168MHz, 1.8-3.6V, 82 GPIO, LQFP-100
K ARM Cortex-M4 STM32F4 STM32F407/417
F http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00037051.pdf
$ENDCMP
#
$CMP VNS3NV04DPTR-E
D OMNIFET II fully autoprotected Power MOSFET
K fully autoprotected Power MOSFET

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@ -70,6 +70,18 @@ $CMP STM32F401RETx
F https://www.st.com/resource/en/datasheet/stm32f401re.pdf
$ENDCMP
#
$CMP STM32F407VETx
D ARM Cortex-M4 MCU, 512KB flash, 128KB RAM, 168MHz, 1.8-3.6V, 82 GPIO, LQFP-100
K ARM Cortex-M4 STM32F4 STM32F407/417
F http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00037051.pdf
$ENDCMP
#
$CMP STM32F407VGTx
D ARM Cortex-M4 MCU, 1024KB flash, 128KB RAM, 168MHz, 1.8-3.6V, 82 GPIO, LQFP-100
K ARM Cortex-M4 STM32F4 STM32F407/417
F http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00037051.pdf
$ENDCMP
#
$CMP VNS3NV04DPTR-E
D OMNIFET II fully autoprotected Power MOSFET
K fully autoprotected Power MOSFET

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@ -2232,6 +2232,122 @@ X PC1/ADC1_IN11 9 2350 1500 150 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# STM32F407VETx
#
DEF STM32F407VETx U 0 20 Y Y 1 F N
F0 "U" 1050 2850 50 H V L CNN
F1 "STM32F407VETx" 1000 2750 50 H V L CNN
F2 "Package_QFP:LQFP-100_14x14mm_P0.5mm" 2950 -2750 50 H I R CNN
F3 "" 0 0 50 H I C CNN
ALIAS STM32F407VGTx
$FPLIST
LQFP*14x14mm*P0.5mm*
$ENDFPLIST
DRAW
S -3050 2700 3050 -2700 0 1 0 f
X PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3 1 3150 400 100 L 50 50 1 1 B
X VSS 10 200 -2800 100 U 50 50 1 1 W
X VDD 100 150 2800 100 D 50 50 1 1 W
X VDD 11 -350 2800 100 D 50 50 1 1 W
X PH0/OSC_IN 12 3150 -1200 100 L 50 50 1 1 B
X PH1/OSC_OUT 13 3150 -1300 100 L 50 50 1 1 B
X NRST/RST 14 3150 -1600 100 L 50 50 1 1 B
X PC0/OTG_HS_ULPI_STP/ADC123_IN10 15 -3150 -1100 100 R 50 50 1 1 B
X PC1/ETH_MDC/ADC123_IN11 16 -3150 -1200 100 R 50 50 1 1 B
X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/ETH_MII_TXD2/I2S2ext_SD/ADC123_IN12 17 -3150 -1300 100 R 50 50 1 1 B
X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/ETH_MII_TX_CLK/ADC123_IN13 18 -3150 -1400 100 R 50 50 1 1 B
X VDD 19 -250 2800 100 D 50 50 1 1 W
X PE3/TRACED0/FSMC_A19 2 3150 300 100 L 50 50 1 1 B
X VSSA 20 3150 -2500 100 L 50 50 1 1 W
X VREF+ 21 3150 -2000 100 L 50 50 1 1 W
X VDDA 22 3150 -2200 100 L 50 50 1 1 W
X PA0/USART2_CTS/UART4_TX/ETH_MII_CRS/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/ADC123_IN0/WKUP 23 -3150 2300 100 R 50 50 1 1 B
X PA1/USART2_RTS/UART4_RX/ETH_RMII_REF_CLK/ETH_MII_RX_CLK/TIM5_CH2/TIM2_CH2/ADC123_IN1 24 -3150 2200 100 R 50 50 1 1 B
X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/ETH_MDIO/ADC123_IN2 25 -3150 2100 100 R 50 50 1 1 B
X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/ETH_MII_COL/ADC123_IN3 26 -3150 2000 100 R 50 50 1 1 B
X VSS 27 100 -2800 100 U 50 50 1 1 W
X VDD 28 -150 2800 100 D 50 50 1 1 W
X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/DCMI_HSYNC/OTG_HS_SOF/I2S3_WS/ADC12_IN4/DAC_OUT1 29 -3150 1900 100 R 50 50 1 1 B
X PE4/TRACED1/FSMC_A20/DCMI_D4 3 3150 200 100 L 50 50 1 1 B
X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CH1N/ADC12_IN5/DAC_OUT2 30 -3150 1800 100 R 50 50 1 1 B
X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/DCMI_PIXCLK/TIM3_CH1/TIM1_BKIN/ADC12_IN6 31 -3150 1700 100 R 50 50 1 1 B
X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV/TIM1_CH1N/ETH_RMII_CRS_DV/ADC12_IN7 32 -3150 1600 100 R 50 50 1 1 B
X PC4/ETH_RMII_RX_D0/ETH_MII_RX_D0/ADC12_IN14 33 -3150 -1500 100 R 50 50 1 1 B
X PC5/ETH_RMII_RX_D1/ETH_MII_RX_D1/ADC12_IN15 34 -3150 -1600 100 R 50 50 1 1 B
X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/ETH_MII_RXD2/TIM1_CH2N/ADC12_IN8 35 -3150 600 100 R 50 50 1 1 B
X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/ETH_MII_RXD3/TIM1_CH3N/ADC12_IN9 36 -3150 500 100 R 50 50 1 1 B
X PB2/BOOT1 37 -3150 400 100 R 50 50 1 1 B
X PE7/FSMC_D4/TIM1_ETR 38 3150 -100 100 L 50 50 1 1 B
X PE8/FSMC_D5/TIM1_CH1N 39 3150 -200 100 L 50 50 1 1 B
X PE5/TRACED2/FSMC_A21/TIM9_CH1/DCMI_D6 4 3150 100 100 L 50 50 1 1 B
X PE9/FSMC_D6/TIM1_CH1 40 3150 -300 100 L 50 50 1 1 B
X PE10/FSMC_D7/TIM1_CH2N 41 3150 -400 100 L 50 50 1 1 B
X PE11/FSMC_D8/TIM1_CH2 42 3150 -500 100 L 50 50 1 1 B
X PE12/FSMC_D9/TIM1_CH3N 43 3150 -600 100 L 50 50 1 1 B
X PE13/FSMC_D10/TIM1_CH3 44 3150 -700 100 L 50 50 1 1 B
X PE14/FSMC_D11/TIM1_CH4 45 3150 -800 100 L 50 50 1 1 B
X PE15/FSMC_D12/TIM1_BKIN 46 3150 -900 100 L 50 50 1 1 B
X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/ETH_MII_RX_ER/TIM2_CH3 47 -3150 -400 100 R 50 50 1 1 B
X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/ETH_RMII_TX_EN/ETH_MII_TX_EN/TIM2_CH4 48 -3150 -500 100 R 50 50 1 1 B
X VCAP_1 49 -1150 -2800 100 U 50 50 1 1 W
X PE6/TRACED3/FSMC_A22/TIM9_CH2/DCMI_D7 5 3150 0 100 L 50 50 1 1 B
X VDD 50 -50 2800 100 D 50 50 1 1 E
X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/ETH_RMII_TXD0/ETH_MII_TXD0/OTG_HS_ID 51 -3150 -600 100 R 50 50 1 1 B
X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/ETH_RMII_TXD1/ETH_MII_TXD1/OTG_HS_VBUS 52 -3150 -700 100 R 50 50 1 1 B
X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD 53 -3150 -800 100 R 50 50 1 1 B
X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/RTC_REFIN 54 -3150 -900 100 R 50 50 1 1 B
X PD8/FSMC_D13/USART3_TX 55 3150 1500 100 L 50 50 1 1 B
X PD9/FSMC_D14/USART3_RX 56 3150 1400 100 L 50 50 1 1 B
X PD10/FSMC_D15/USART3_CK 57 3150 1300 100 L 50 50 1 1 B
X PD11/FSMC_CLE/FSMC_A16/USART3_CTS 58 3150 1200 100 L 50 50 1 1 B
X PD12/FSMC_ALE/FSMC_A17/TIM4_CH1/USART3_RTS 59 3150 1100 100 L 50 50 1 1 B
X VBAT 6 3150 -1800 100 L 50 50 1 1 W
X PD13/FSMC_A18/TIM4_CH2 60 3150 1000 100 L 50 50 1 1 B
X PD14/FSMC_D0/TIM4_CH3 61 3150 900 100 L 50 50 1 1 B
X PD15/FSMC_D1/TIM4_CH4 62 3150 800 100 L 50 50 1 1 B
X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/DCMI_D0/TIM3_CH1 63 -3150 -1700 100 R 50 50 1 1 B
X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/DCMI_D1/TIM3_CH2 64 -3150 -1800 100 R 50 50 1 1 B
X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/DCMI_D2 65 -3150 -1900 100 R 50 50 1 1 B
X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1//I2C3_SDA/DCMI_D3/TIM3_CH4 66 -3150 -2000 100 R 50 50 1 1 B
X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF 67 -3150 1500 100 R 50 50 1 1 B
X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/DCMI_D0/OTG_FS_VBUS 68 -3150 1400 100 R 50 50 1 1 B
X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/DCMI_D1 69 -3150 1300 100 R 50 50 1 1 B
X PC13/RTC_OUT/RTC_TAMP1/RTC_TS 7 -3150 -2400 100 R 50 50 1 1 B
X PA11/USART1_CTS/CAN1_RX/TIM1_CH4/OTG_FS_DM 70 -3150 1200 100 R 50 50 1 1 B
X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP 71 -3150 1100 100 R 50 50 1 1 B
X PA13/JTMS-SWDIO 72 -3150 1000 100 R 50 50 1 1 B
X VCAP_2 73 -850 -2800 100 U 50 50 1 1 W
X VSS 74 0 -2800 100 U 50 50 1 1 W
X VDD 75 50 2800 100 D 50 50 1 1 W
X PA14/JTCK-SWCLK 76 -3150 900 100 R 50 50 1 1 B
X PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS 77 -3150 800 100 R 50 50 1 1 B
X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/DCMI_D8/USART3_TX 78 -3150 -2100 100 R 50 50 1 1 B
X PC11/UART4_RX/SPI3_MISO/SDIO_D3/DCMI_D4/USART3_RX/I2S3ext_SD 79 -3150 -2200 100 R 50 50 1 1 B
X PC14/OSC32_IN 8 -3150 -2500 100 R 50 50 1 1 B
X PC12/UART5_TX/SDIO_CK/DCMI_D9/SPI3_MOSI/I2S3_SD/USART3_CK 80 -3150 -2300 100 R 50 50 1 1 B
X PD0/FSMC_D2/CAN1_RX 81 3150 2300 100 L 50 50 1 1 B
X PD1/FSMC_D3/CAN1_TX 82 3150 2200 100 L 50 50 1 1 B
X PD2/TIM3_ETR/UART5_RX/SDIO_CMD/DCMI_D11 83 3150 2100 100 L 50 50 1 1 B
X PD3/FSMC_CLK/USART2_CTS 84 3150 2000 100 L 50 50 1 1 B
X PD4/FSMC_NOE/USART2_RTS 85 3150 1900 100 L 50 50 1 1 B
X PD5/FSMC_NWE/USART2_TX 86 3150 1800 100 L 50 50 1 1 B
X PD6/FSMC_NWAIT/USART2_RX 87 3150 1700 100 L 50 50 1 1 B
X PD7/USART2_CK/FSMC_NE1/FSMC_NCE2 88 3150 1600 100 L 50 50 1 1 B
X PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK 89 -3150 300 100 R 50 50 1 1 B
X PC15/OSC32_OUT 9 -3150 -2600 100 R 50 50 1 1 B
X PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD 90 -3150 200 100 R 50 50 1 1 B
X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/ETH_PPS_OUT/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/DCMI_D10/I2S3_SD 91 -3150 100 100 R 50 50 1 1 B
X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/DCMI_D5/USART1_TX 92 -3150 0 100 R 50 50 1 1 B
X PB7/I2C1_SDA/FSMC_NL/DCMI_VSYNC/USART1_RX/TIM4_CH2 93 -3150 -100 100 R 50 50 1 1 B
X BOOT0/VPP 94 3150 -1500 100 L 50 50 1 1 I
X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/DCMI_D6/ETH_MII_TXD3/I2C1_SCL/CAN1_RX 95 -3150 -200 100 R 50 50 1 1 B
X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/DCMI_D7/I2C1_SDA/CAN1_TX 96 -3150 -300 100 R 50 50 1 1 B
X PE0/TIM4_ETR/FSMC_NBL0/DCMI_D2 97 3150 600 100 L 50 50 1 1 B
X PE1/FSMC_NBL1/DCMI_D3 98 3150 500 100 L 50 50 1 1 B
X VSS 99 -100 -2800 100 U 50 50 1 1 W
ENDDRAW
ENDDEF
#
# TCA505BG
#
DEF TCA505BG U 0 40 Y Y 1 F N

101
tools/stm32f407_100pin.csv Normal file
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@ -0,0 +1,101 @@
pin,pin_name,locate
X BOOT0/VPP 94 2300 9900 100 L 50 50 1 1 B
X NRST/RST 14 2300 9800 100 L 50 50 1 1 B
X PA0/WKUP/(PA0)/USART2_CTS/UART4_TX/ETH_MII_CRS/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/ADC123_IN0/WKUP 23 2300 9700 100 L 50 50 1 1 B
X PA1/USART2_RTS/UART4_RX/ETH_RMII_REF_CLK/ETH_MII_RX_CLK/TIM5_CH2/TIM2_CH2/ADC123_IN1 24 2300 9600 100 L 50 50 1 1 B
X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/ETH_MDIO/ADC123_IN2 25 2300 9500 100 L 50 50 1 1 B
X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/ETH_MII_COL/ADC123_IN3 26 2300 9400 100 L 50 50 1 1 B
X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/DCMI_HSYNC/OTG_HS_SOF/I2S3_WS/ADC12_IN4/DAC_OUT1 29 2300 9300 100 L 50 50 1 1 B
X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CH1N/ADC12_IN5/DAC_OUT2 30 2300 9200 100 L 50 50 1 1 B
X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/DCMI_PIXCLK/TIM3_CH1/TIM1_BKIN/ADC12_IN6 31 2300 9100 100 L 50 50 1 1 B
X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV/TIM1_CH1N/ETH_RMII_CRS_DV/ADC12_IN7 32 2300 9000 100 L 50 50 1 1 B
X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF 67 2300 8900 100 L 50 50 1 1 B
X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/DCMI_D0/OTG_FS_VBUS 68 2300 8800 100 L 50 50 1 1 B
X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/DCMI_D1 69 2300 8700 100 L 50 50 1 1 B
X PA11/USART1_CTS/CAN1_RX/TIM1_CH4/OTG_FS_DM 70 2300 8600 100 L 50 50 1 1 B
X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP 71 2300 8500 100 L 50 50 1 1 B
X PA13/(JTMS-SWDIO)/JTMS-SWDIO 72 2300 8400 100 L 50 50 1 1 B
X PA14/(JTCK/SWCLK)/JTCK-SWCLK 76 2300 8300 100 L 50 50 1 1 B
X PA15/(JTDI)/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS 77 2300 8200 100 L 50 50 1 1 B
X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/ETH_MII_RXD2/TIM1_CH2N/ADC12_IN8 35 2300 8100 100 L 50 50 1 1 B
X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/ETH_MII_RXD3/TIM1_CH3N/ADC12_IN9 36 2300 8000 100 L 50 50 1 1 B
X PB2/BOOT1/(PB2) 37 2300 7900 100 L 50 50 1 1 B
X PB3/(JTDO/TRACESWO)/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK 89 2300 7800 100 L 50 50 1 1 B
X PB4/(NJTRST)/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD 90 2300 7700 100 L 50 50 1 1 B
X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/ETH_PPS_OUT/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/DCMI_D10/I2S3_SD 91 2300 7600 100 L 50 50 1 1 B
X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/DCMI_D5/USART1_TX 92 2300 7500 100 L 50 50 1 1 B
X PB7/I2C1_SDA/FSMC_NL/DCMI_VSYNC/USART1_RX/TIM4_CH2 93 2300 7400 100 L 50 50 1 1 B
X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/DCMI_D6/ETH_MII_TXD3/I2C1_SCL/CAN1_RX 95 2300 7300 100 L 50 50 1 1 B
X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/DCMI_D7/I2C1_SDA/CAN1_TX 96 2300 7200 100 L 50 50 1 1 B
X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/ETH_MII_RX_ER/TIM2_CH3 47 2300 7100 100 L 50 50 1 1 B
X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/ETH_RMII_TX_EN/ETH_MII_TX_EN/TIM2_CH4 48 2300 7000 100 L 50 50 1 1 B
X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/ETH_RMII_TXD0/ETH_MII_TXD0/OTG_HS_ID 51 2300 6900 100 L 50 50 1 1 B
X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/ETH_RMII_TXD1/ETH_MII_TXD1/OTG_HS_VBUS 52 2300 6800 100 L 50 50 1 1 B
X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD 53 2300 6700 100 L 50 50 1 1 B
X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/RTC_REFIN 54 2300 6600 100 L 50 50 1 1 B
X PC0/OTG_HS_ULPI_STP/ADC123_IN10 15 2300 6500 100 L 50 50 1 1 B
X PC1/ETH_MDC/ADC123_IN11 16 2300 6400 100 L 50 50 1 1 B
X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/ETH_MII_TXD2/I2S2ext_SD/ADC123_IN12 17 2300 6300 100 L 50 50 1 1 B
X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/ETH_MII_TX_CLK/ADC123_IN13 18 2300 6200 100 L 50 50 1 1 B
X PC4/ETH_RMII_RX_D0/ETH_MII_RX_D0/ADC12_IN14 33 2300 6100 100 L 50 50 1 1 B
X PC5/ETH_RMII_RX_D1/ETH_MII_RX_D1/ADC12_IN15 34 2300 6000 100 L 50 50 1 1 B
X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/DCMI_D0/TIM3_CH1 63 2300 5900 100 L 50 50 1 1 B
X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/DCMI_D1/TIM3_CH2 64 2300 5800 100 L 50 50 1 1 B
X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/DCMI_D2 65 2300 5700 100 L 50 50 1 1 B
X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1//I2C3_SDA/DCMI_D3/TIM3_CH4 66 2300 5600 100 L 50 50 1 1 B
X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/DCMI_D8/USART3_TX 78 2300 5500 100 L 50 50 1 1 B
X PC11/UART4_RX/SPI3_MISO/SDIO_D3/DCMI_D4/USART3_RX/I2S3ext_SD 79 2300 5400 100 L 50 50 1 1 B
X PC12/UART5_TX/SDIO_CK/DCMI_D9/SPI3_MOSI/I2S3_SD/USART3_CK 80 2300 5300 100 L 50 50 1 1 B
X PC13/RTC_OUT/RTC_TAMP1/RTC_TS 7 2300 5200 100 L 50 50 1 1 B
X PC14/OSC32_IN/(PC14)/OSC32_IN 8 2300 5100 100 L 50 50 1 1 B
X PC15/OSC32_OUT/(PC15)/OSC32_OUT 9 2300 5000 100 L 50 50 1 1 B
X PD0/FSMC_D2/CAN1_RX 81 2300 4900 100 L 50 50 1 1 B
X PD1/FSMC_D3/CAN1_TX 82 2300 4800 100 L 50 50 1 1 B
X PD2/TIM3_ETR/UART5_RX/SDIO_CMD/DCMI_D11 83 2300 4700 100 L 50 50 1 1 B
X PD3/FSMC_CLK/USART2_CTS 84 2300 4600 100 L 50 50 1 1 B
X PD4/FSMC_NOE/USART2_RTS 85 2300 4500 100 L 50 50 1 1 B
X PD5/FSMC_NWE/USART2_TX 86 2300 4400 100 L 50 50 1 1 B
X PD6/FSMC_NWAIT/USART2_RX 87 2300 4300 100 L 50 50 1 1 B
X PD7/USART2_CK/FSMC_NE1/FSMC_NCE2 88 2300 4200 100 L 50 50 1 1 B
X PD8/FSMC_D13/USART3_TX 55 2300 4100 100 L 50 50 1 1 B
X PD9/FSMC_D14/USART3_RX 56 2300 4000 100 L 50 50 1 1 B
X PD10/FSMC_D15/USART3_CK 57 2300 3900 100 L 50 50 1 1 B
X PD11/FSMC_CLE/FSMC_A16/USART3_CTS 58 2300 3800 100 L 50 50 1 1 B
X PD12/FSMC_ALE/FSMC_A17/TIM4_CH1/USART3_RTS 59 2300 3700 100 L 50 50 1 1 B
X PD13/FSMC_A18/TIM4_CH2 60 2300 3600 100 L 50 50 1 1 B
X PD14/FSMC_D0/TIM4_CH3 61 2300 3500 100 L 50 50 1 1 B
X PD15/FSMC_D1/TIM4_CH4 62 2300 3400 100 L 50 50 1 1 B
X PE0/TIM4_ETR/FSMC_NBL0/DCMI_D2 97 2300 3300 100 L 50 50 1 1 B
X PE1/FSMC_NBL1/DCMI_D3 98 2300 3200 100 L 50 50 1 1 B
X PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3 1 2300 3100 100 L 50 50 1 1 B
X PE3/TRACED0/FSMC_A19 2 2300 3000 100 L 50 50 1 1 B
X PE4/TRACED1/FSMC_A20/DCMI_D4 3 2300 2900 100 L 50 50 1 1 B
X PE5/TRACED2/FSMC_A21/TIM9_CH1/DCMI_D6 4 2300 2800 100 L 50 50 1 1 B
X PE6/TRACED3/FSMC_A22/TIM9_CH2/DCMI_D7 5 2300 2700 100 L 50 50 1 1 B
X PE7/FSMC_D4/TIM1_ETR 38 2300 2600 100 L 50 50 1 1 B
X PE8/FSMC_D5/TIM1_CH1N 39 2300 2500 100 L 50 50 1 1 B
X PE9/FSMC_D6/TIM1_CH1 40 2300 2400 100 L 50 50 1 1 B
X PE10/FSMC_D7/TIM1_CH2N 41 2300 2300 100 L 50 50 1 1 B
X PE11/FSMC_D8/TIM1_CH2 42 2300 2200 100 L 50 50 1 1 B
X PE12/FSMC_D9/TIM1_CH3N 43 2300 2100 100 L 50 50 1 1 B
X PE13/FSMC_D10/TIM1_CH3 44 2300 2000 100 L 50 50 1 1 B
X PE14/FSMC_D11/TIM1_CH4 45 2300 1900 100 L 50 50 1 1 B
X PE15/FSMC_D12/TIM1_BKIN 46 2300 1800 100 L 50 50 1 1 B
X PH0/OSC_IN/(PH0)/OSC_IN 12 2300 1700 100 L 50 50 1 1 B
X PH1/OSC_OUT/(PH1)/OSC_OUT 13 2300 1600 100 L 50 50 1 1 B
X VBAT 6 2300 1500 100 L 50 50 1 1 B
X VCAP_1 49 2300 1400 100 L 50 50 1 1 B
X VCAP_2 73 2300 1300 100 L 50 50 1 1 B
X VDD 11 2300 1200 100 L 50 50 1 1 B
X VDD 19 2300 1100 100 L 50 50 1 1 B
X VDD 28 2300 1000 100 L 50 50 1 1 B
X VDD 50 2300 900 100 L 50 50 1 1 B
X VDD 75 2300 800 100 L 50 50 1 1 B
X VDD 100 2300 700 100 L 50 50 1 1 B
X VDDA 22 2300 600 100 L 50 50 1 1 B
X VREF+ 21 2300 500 100 L 50 50 1 1 B
X VSS 10 2300 400 100 L 50 50 1 1 B
X VSS 27 2300 300 100 L 50 50 1 1 B
X VSS 74 2300 200 100 L 50 50 1 1 B
X VSS 99 2300 100 100 L 50 50 1 1 B
X VSSA 20 2300 0 100 L 50 50 1 1 B
1 pin,pin_name,locate
2 X BOOT0/VPP 94 2300 9900 100 L 50 50 1 1 B
3 X NRST/RST 14 2300 9800 100 L 50 50 1 1 B
4 X PA0/WKUP/(PA0)/USART2_CTS/UART4_TX/ETH_MII_CRS/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/ADC123_IN0/WKUP 23 2300 9700 100 L 50 50 1 1 B
5 X PA1/USART2_RTS/UART4_RX/ETH_RMII_REF_CLK/ETH_MII_RX_CLK/TIM5_CH2/TIM2_CH2/ADC123_IN1 24 2300 9600 100 L 50 50 1 1 B
6 X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/ETH_MDIO/ADC123_IN2 25 2300 9500 100 L 50 50 1 1 B
7 X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/ETH_MII_COL/ADC123_IN3 26 2300 9400 100 L 50 50 1 1 B
8 X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/DCMI_HSYNC/OTG_HS_SOF/I2S3_WS/ADC12_IN4/DAC_OUT1 29 2300 9300 100 L 50 50 1 1 B
9 X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CH1N/ADC12_IN5/DAC_OUT2 30 2300 9200 100 L 50 50 1 1 B
10 X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/DCMI_PIXCLK/TIM3_CH1/TIM1_BKIN/ADC12_IN6 31 2300 9100 100 L 50 50 1 1 B
11 X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV/TIM1_CH1N/ETH_RMII_CRS_DV/ADC12_IN7 32 2300 9000 100 L 50 50 1 1 B
12 X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF 67 2300 8900 100 L 50 50 1 1 B
13 X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/DCMI_D0/OTG_FS_VBUS 68 2300 8800 100 L 50 50 1 1 B
14 X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/DCMI_D1 69 2300 8700 100 L 50 50 1 1 B
15 X PA11/USART1_CTS/CAN1_RX/TIM1_CH4/OTG_FS_DM 70 2300 8600 100 L 50 50 1 1 B
16 X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP 71 2300 8500 100 L 50 50 1 1 B
17 X PA13/(JTMS-SWDIO)/JTMS-SWDIO 72 2300 8400 100 L 50 50 1 1 B
18 X PA14/(JTCK/SWCLK)/JTCK-SWCLK 76 2300 8300 100 L 50 50 1 1 B
19 X PA15/(JTDI)/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS 77 2300 8200 100 L 50 50 1 1 B
20 X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/ETH_MII_RXD2/TIM1_CH2N/ADC12_IN8 35 2300 8100 100 L 50 50 1 1 B
21 X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/ETH_MII_RXD3/TIM1_CH3N/ADC12_IN9 36 2300 8000 100 L 50 50 1 1 B
22 X PB2/BOOT1/(PB2) 37 2300 7900 100 L 50 50 1 1 B
23 X PB3/(JTDO/TRACESWO)/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK 89 2300 7800 100 L 50 50 1 1 B
24 X PB4/(NJTRST)/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD 90 2300 7700 100 L 50 50 1 1 B
25 X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/ETH_PPS_OUT/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/DCMI_D10/I2S3_SD 91 2300 7600 100 L 50 50 1 1 B
26 X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/DCMI_D5/USART1_TX 92 2300 7500 100 L 50 50 1 1 B
27 X PB7/I2C1_SDA/FSMC_NL/DCMI_VSYNC/USART1_RX/TIM4_CH2 93 2300 7400 100 L 50 50 1 1 B
28 X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/DCMI_D6/ETH_MII_TXD3/I2C1_SCL/CAN1_RX 95 2300 7300 100 L 50 50 1 1 B
29 X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/DCMI_D7/I2C1_SDA/CAN1_TX 96 2300 7200 100 L 50 50 1 1 B
30 X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/ETH_MII_RX_ER/TIM2_CH3 47 2300 7100 100 L 50 50 1 1 B
31 X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/ETH_RMII_TX_EN/ETH_MII_TX_EN/TIM2_CH4 48 2300 7000 100 L 50 50 1 1 B
32 X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/ETH_RMII_TXD0/ETH_MII_TXD0/OTG_HS_ID 51 2300 6900 100 L 50 50 1 1 B
33 X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/ETH_RMII_TXD1/ETH_MII_TXD1/OTG_HS_VBUS 52 2300 6800 100 L 50 50 1 1 B
34 X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD 53 2300 6700 100 L 50 50 1 1 B
35 X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/RTC_REFIN 54 2300 6600 100 L 50 50 1 1 B
36 X PC0/OTG_HS_ULPI_STP/ADC123_IN10 15 2300 6500 100 L 50 50 1 1 B
37 X PC1/ETH_MDC/ADC123_IN11 16 2300 6400 100 L 50 50 1 1 B
38 X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/ETH_MII_TXD2/I2S2ext_SD/ADC123_IN12 17 2300 6300 100 L 50 50 1 1 B
39 X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/ETH_MII_TX_CLK/ADC123_IN13 18 2300 6200 100 L 50 50 1 1 B
40 X PC4/ETH_RMII_RX_D0/ETH_MII_RX_D0/ADC12_IN14 33 2300 6100 100 L 50 50 1 1 B
41 X PC5/ETH_RMII_RX_D1/ETH_MII_RX_D1/ADC12_IN15 34 2300 6000 100 L 50 50 1 1 B
42 X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/DCMI_D0/TIM3_CH1 63 2300 5900 100 L 50 50 1 1 B
43 X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/DCMI_D1/TIM3_CH2 64 2300 5800 100 L 50 50 1 1 B
44 X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/DCMI_D2 65 2300 5700 100 L 50 50 1 1 B
45 X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1//I2C3_SDA/DCMI_D3/TIM3_CH4 66 2300 5600 100 L 50 50 1 1 B
46 X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/DCMI_D8/USART3_TX 78 2300 5500 100 L 50 50 1 1 B
47 X PC11/UART4_RX/SPI3_MISO/SDIO_D3/DCMI_D4/USART3_RX/I2S3ext_SD 79 2300 5400 100 L 50 50 1 1 B
48 X PC12/UART5_TX/SDIO_CK/DCMI_D9/SPI3_MOSI/I2S3_SD/USART3_CK 80 2300 5300 100 L 50 50 1 1 B
49 X PC13/RTC_OUT/RTC_TAMP1/RTC_TS 7 2300 5200 100 L 50 50 1 1 B
50 X PC14/OSC32_IN/(PC14)/OSC32_IN 8 2300 5100 100 L 50 50 1 1 B
51 X PC15/OSC32_OUT/(PC15)/OSC32_OUT 9 2300 5000 100 L 50 50 1 1 B
52 X PD0/FSMC_D2/CAN1_RX 81 2300 4900 100 L 50 50 1 1 B
53 X PD1/FSMC_D3/CAN1_TX 82 2300 4800 100 L 50 50 1 1 B
54 X PD2/TIM3_ETR/UART5_RX/SDIO_CMD/DCMI_D11 83 2300 4700 100 L 50 50 1 1 B
55 X PD3/FSMC_CLK/USART2_CTS 84 2300 4600 100 L 50 50 1 1 B
56 X PD4/FSMC_NOE/USART2_RTS 85 2300 4500 100 L 50 50 1 1 B
57 X PD5/FSMC_NWE/USART2_TX 86 2300 4400 100 L 50 50 1 1 B
58 X PD6/FSMC_NWAIT/USART2_RX 87 2300 4300 100 L 50 50 1 1 B
59 X PD7/USART2_CK/FSMC_NE1/FSMC_NCE2 88 2300 4200 100 L 50 50 1 1 B
60 X PD8/FSMC_D13/USART3_TX 55 2300 4100 100 L 50 50 1 1 B
61 X PD9/FSMC_D14/USART3_RX 56 2300 4000 100 L 50 50 1 1 B
62 X PD10/FSMC_D15/USART3_CK 57 2300 3900 100 L 50 50 1 1 B
63 X PD11/FSMC_CLE/FSMC_A16/USART3_CTS 58 2300 3800 100 L 50 50 1 1 B
64 X PD12/FSMC_ALE/FSMC_A17/TIM4_CH1/USART3_RTS 59 2300 3700 100 L 50 50 1 1 B
65 X PD13/FSMC_A18/TIM4_CH2 60 2300 3600 100 L 50 50 1 1 B
66 X PD14/FSMC_D0/TIM4_CH3 61 2300 3500 100 L 50 50 1 1 B
67 X PD15/FSMC_D1/TIM4_CH4 62 2300 3400 100 L 50 50 1 1 B
68 X PE0/TIM4_ETR/FSMC_NBL0/DCMI_D2 97 2300 3300 100 L 50 50 1 1 B
69 X PE1/FSMC_NBL1/DCMI_D3 98 2300 3200 100 L 50 50 1 1 B
70 X PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3 1 2300 3100 100 L 50 50 1 1 B
71 X PE3/TRACED0/FSMC_A19 2 2300 3000 100 L 50 50 1 1 B
72 X PE4/TRACED1/FSMC_A20/DCMI_D4 3 2300 2900 100 L 50 50 1 1 B
73 X PE5/TRACED2/FSMC_A21/TIM9_CH1/DCMI_D6 4 2300 2800 100 L 50 50 1 1 B
74 X PE6/TRACED3/FSMC_A22/TIM9_CH2/DCMI_D7 5 2300 2700 100 L 50 50 1 1 B
75 X PE7/FSMC_D4/TIM1_ETR 38 2300 2600 100 L 50 50 1 1 B
76 X PE8/FSMC_D5/TIM1_CH1N 39 2300 2500 100 L 50 50 1 1 B
77 X PE9/FSMC_D6/TIM1_CH1 40 2300 2400 100 L 50 50 1 1 B
78 X PE10/FSMC_D7/TIM1_CH2N 41 2300 2300 100 L 50 50 1 1 B
79 X PE11/FSMC_D8/TIM1_CH2 42 2300 2200 100 L 50 50 1 1 B
80 X PE12/FSMC_D9/TIM1_CH3N 43 2300 2100 100 L 50 50 1 1 B
81 X PE13/FSMC_D10/TIM1_CH3 44 2300 2000 100 L 50 50 1 1 B
82 X PE14/FSMC_D11/TIM1_CH4 45 2300 1900 100 L 50 50 1 1 B
83 X PE15/FSMC_D12/TIM1_BKIN 46 2300 1800 100 L 50 50 1 1 B
84 X PH0/OSC_IN/(PH0)/OSC_IN 12 2300 1700 100 L 50 50 1 1 B
85 X PH1/OSC_OUT/(PH1)/OSC_OUT 13 2300 1600 100 L 50 50 1 1 B
86 X VBAT 6 2300 1500 100 L 50 50 1 1 B
87 X VCAP_1 49 2300 1400 100 L 50 50 1 1 B
88 X VCAP_2 73 2300 1300 100 L 50 50 1 1 B
89 X VDD 11 2300 1200 100 L 50 50 1 1 B
90 X VDD 19 2300 1100 100 L 50 50 1 1 B
91 X VDD 28 2300 1000 100 L 50 50 1 1 B
92 X VDD 50 2300 900 100 L 50 50 1 1 B
93 X VDD 75 2300 800 100 L 50 50 1 1 B
94 X VDD 100 2300 700 100 L 50 50 1 1 B
95 X VDDA 22 2300 600 100 L 50 50 1 1 B
96 X VREF+ 21 2300 500 100 L 50 50 1 1 B
97 X VSS 10 2300 400 100 L 50 50 1 1 B
98 X VSS 27 2300 300 100 L 50 50 1 1 B
99 X VSS 74 2300 200 100 L 50 50 1 1 B
100 X VSS 99 2300 100 100 L 50 50 1 1 B
101 X VSSA 20 2300 0 100 L 50 50 1 1 B

View File

@ -0,0 +1,578 @@
- - 1 1 A2 1 PE2 I/O FT -
TRACECLK/ FSMC_A23 /
ETH_MII_TXD3 /
EVENTOUT
-
- - 2 2 A1 2 PE3 I/O FT - TRACED0/FSMC_A19 /
EVENTOUT -
- - 3 3 B1 3 PE4 I/O FT - TRACED1/FSMC_A20 /
DCMI_D4/ EVENTOUT -
- - 4 4 B2 4 PE5 I/O FT -
TRACED2 / FSMC_A21 /
TIM9_CH1 / DCMI_D6 /
EVENTOUT
-
- - 5 5 B3 5 PE6 I/O FT -
TRACED3 / FSMC_A22 /
TIM9_CH2 / DCMI_D7 /
EVENTOUT
-
1 A10 6 6 C1 6 VBAT S- - - -
- - - - D2 7 PI8 I/O FT
(2)(
3) EVENTOUT
RTC_TAMP1,
RTC_TAMP2,
RTC_TS
2 A9 7 7 D1 8 PC13 I/O FT
(2)
(3) EVENTOUT
RTC_OUT,
RTC_TAMP1,
RTC_TS
3 B10 8 8 E1 9 PC14/OSC32_IN
(PC14) I/O FT
(2)(
3) EVENTOUT OSC32_IN(4)
4 B9 9 9 F1 10
PC15/
OSC32_OUT
(PC15)
I/O FT
(2)(
3) EVENTOUT OSC32_OUT(4)
- - - - D3 11 PI9 I/O FT - CAN1_RX / EVENTOUT -
- - - - E3 12 PI10 I/O FT - ETH_MII_RX_ER /
EVENTOUT -
- - - - E4 13 PI11 I/O FT - OTG_HS_ULPI_DIR /
EVENTOUT -
- - - - F2 14 VSS S- - - -
- - - - F3 15 VDD S- - - -
- - - 10 E2 16 PF0 I/O FT - FSMC_A0 / I2C2_SDA /
EVENTOUT -
- - - 11 H3 17 PF1 I/O FT - FSMC_A1 / I2C2_SCL /
EVENTOUT -
- - - 12 H2 18 PF2 I/O FT - FSMC_A2 / I2C2_SMBA /
EVENTOUT -
- - - 13 J2 19 PF3 I/O FT (4) FSMC_A3/EVENTOUT ADC3_IN9
- - - 14 J3 20 PF4 I/O FT (4) FSMC_A4/EVENTOUT ADC3_IN14
- - - 15 K3 21 PF5 I/O FT (4) FSMC_A5/EVENTOUT ADC3_IN15
- C9 10 16 G2 22 VSS S- - - -
- B8 11 17 G3 23 VDD S- - - -
- - - 18 K2 24 PF6 I/O FT (4)
TIM10_CH1 /
FSMC_NIORD/
EVENTOUT
ADC3_IN4
- - - 19 K1 25 PF7 I/O FT (4) TIM11_CH1/FSMC_NREG/
EVENTOUT ADC3_IN5
- - - 20 L3 26 PF8 I/O FT (4)
TIM13_CH1 /
FSMC_NIOWR/
EVENTOUT
ADC3_IN6
- - - 21 L2 27 PF9 I/O FT (4) TIM14_CH1 / FSMC_CD/
EVENTOUT ADC3_IN7
- - - 22 L1 28 PF10 I/O FT (4) FSMC_INTR/ EVENTOUT ADC3_IN8
5 F10 12 23 G1 29 PH0/OSC_IN
(PH0) I/O FT - EVENTOUT OSC_IN(4)
6 F9 13 24 H1 30 PH1/OSC_OUT
(PH1) I/O FT - EVENTOUT OSC_OUT(4)
7 G10 14 25 J1 31 NRST I/O RST - - -
8 E10 15 26 M2 32 PC0 I/O FT (4) OTG_HS_ULPI_STP/
EVENTOUT ADC123_IN10
9 - 16 27 M3 33 PC1 I/O FT (4) ETH_MDC/ EVENTOUT ADC123_IN11
10 D10 17 28 M4 34 PC2 I/O FT (4)
SPI2_MISO /
OTG_HS_ULPI_DIR /
ETH_MII_TXD2
/I2S2ext_SD/ EVENTOUT
ADC123_IN12
11 E9 18 29 M5 35 PC3 I/O FT (4)
SPI2_MOSI / I2S2_SD /
OTG_HS_ULPI_NXT /
ETH_MII_TX_CLK/
EVENTOUT
ADC123_IN13
- - 19 30 - 36 VDD S- - - -
12 H10 20 31 M1 37 VSSA S- - - -
- - - - N1 - VREF S- - - -
- - 21 32 P1 38 VREF+ S- - - -
13 G9 22 33 R1 39 VDDA S- - - -
14 C10 23 34 N3 40 PA0/WKUP
(PA0) I/O FT (5)
USART2_CTS/
UART4_TX/
ETH_MII_CRS /
TIM2_CH1_ETR/
TIM5_CH1 / TIM8_ETR/
EVENTOUT
ADC123_IN0/WKU
P(4)
15 F8 24 35 N2 41 PA1 I/O FT (4)
USART2_RTS /
UART4_RX/
ETH_RMII_REF_CLK /
ETH_MII_RX_CLK /
TIM5_CH2 / TIM2_CH2/
EVENTOUT
ADC123_IN1
16 J10 25 36 P2 42 PA2 I/O FT (4)
USART2_TX/TIM5_CH3 /
TIM9_CH1 / TIM2_CH3 /
ETH_MDIO/ EVENTOUT
ADC123_IN2
- - - - F4 43 PH2 I/O FT - ETH_MII_CRS/EVENTOUT -
- - - - G4 44 PH3 I/O FT - ETH_MII_COL/EVENTOUT -
- - - - H4 45 PH4 I/O FT -
I2C2_SCL /
OTG_HS_ULPI_NXT/
EVENTOUT
-
- - - - J4 46 PH5 I/O FT - I2C2_SDA/ EVENTOUT -
17 H9 26 37 R2 47 PA3 I/O FT (4)
USART2_RX/TIM5_CH4 /
TIM9_CH2 / TIM2_CH4 /
OTG_HS_ULPI_D0 /
ETH_MII_COL/
EVENTOUT
ADC123_IN3
18 E5 27 38 - - VSS S- - - -
- D9 - - L4 48 BYPASS_REG I FT - - -
19 E4 28 39 K4 49 VDD S- - - -
20 J9 29 40 N4 50 PA4 I/O TTa (4)
SPI1_NSS / SPI3_NSS /
USART2_CK /
DCMI_HSYNC /
OTG_HS_SOF/ I2S3_WS/
EVENTOUT
ADC12_IN4
/DAC_OUT1
21 G8 30 41 P4 51 PA5 I/O TTa (4)
SPI1_SCK/
OTG_HS_ULPI_CK /
TIM2_CH1_ETR/
TIM8_CH1N/ EVENTOUT
ADC12_IN5/DAC_
OUT2
22 H8 31 42 P3 52 PA6 I/O FT (4)
SPI1_MISO /
TIM8_BKIN/TIM13_CH1 /
DCMI_PIXCLK / TIM3_CH1
/ TIM1_BKIN/ EVENTOUT
ADC12_IN6
23 J8 32 43 R3 53 PA7 I/O FT (4)
SPI1_MOSI/ TIM8_CH1N /
TIM14_CH1/TIM3_CH2/
ETH_MII_RX_DV /
TIM1_CH1N /
ETH_RMII_CRS_DV/
EVENTOUT
ADC12_IN7
24 - 33 44 N5 54 PC4 I/O FT (4)
ETH_RMII_RX_D0 /
ETH_MII_RX_D0/
EVENTOUT
ADC12_IN14
25 - 34 45 P5 55 PC5 I/O FT (4)
ETH_RMII_RX_D1 /
ETH_MII_RX_D1/
EVENTOUT
ADC12_IN15
26 G7 35 46 R5 56 PB0 I/O FT (4)
TIM3_CH3 / TIM8_CH2N/
OTG_HS_ULPI_D1/
ETH_MII_RXD2 /
TIM1_CH2N/ EVENTOUT
ADC12_IN8
27 H7 36 47 R4 57 PB1 I/O FT (4)
TIM3_CH4 / TIM8_CH3N/
OTG_HS_ULPI_D2/
ETH_MII_RXD3 /
TIM1_CH3N/ EVENTOUT
ADC12_IN9
28 J7 37 48 M6 58 PB2/BOOT1
(PB2) I/O FT - EVENTOUT -
- - - 49 R6 59 PF11 I/O FT - DCMI_D12/ EVENTOUT -
- - - 50 P6 60 PF12 I/O FT - FSMC_A6/ EVENTOUT -
- - - 51 M8 61 VSS S- - - -
- - - 52 N8 62 VDD S- - - -
- - - 53 N6 63 PF13 I/O FT - FSMC_A7/ EVENTOUT -
- - - 54 R7 64 PF14 I/O FT - FSMC_A8/ EVENTOUT -
- - - 55 P7 65 PF15 I/O FT - FSMC_A9/ EVENTOUT -
- - - 56 N7 66 PG0 I/O FT - FSMC_A10/ EVENTOUT -
- - - 57 M7 67 PG1 I/O FT - FSMC_A11/ EVENTOUT -
- G6 38 58 R8 68 PE7 I/O FT - FSMC_D4/TIM1_ETR/
EVENTOUT -
- H6 39 59 P8 69 PE8 I/O FT - FSMC_D5/ TIM1_CH1N/
EVENTOUT -
- J6 40 60 P9 70 PE9 I/O FT - FSMC_D6/TIM1_CH1/
EVENTOUT -
- - - 61 M9 71 VSS S- - - -
- - - 62 N9 72 VDD S- - - -
- F6 41 63 R9 73 PE10 I/O FT - FSMC_D7/TIM1_CH2N/
EVENTOUT -
- J5 42 64 P10 74 PE11 I/O FT - FSMC_D8/TIM1_CH2/
EVENTOUT -
- H5 43 65 R10 75 PE12 I/O FT - FSMC_D9/TIM1_CH3N/
EVENTOUT -
- G5 44 66 N11 76 PE13 I/O FT - FSMC_D10/TIM1_CH3/
EVENTOUT -
- F5 45 67 P11 77 PE14 I/O FT - FSMC_D11/TIM1_CH4/
EVENTOUT -
- G4 46 68 R11 78 PE15 I/O FT - FSMC_D12/TIM1_BKIN/
EVENTOUT -
29 H4 47 69 R12 79 PB10 I/O FT -
SPI2_SCK / I2S2_CK /
I2C2_SCL/ USART3_TX /
OTG_HS_ULPI_D3 /
ETH_MII_RX_ER /
TIM2_CH3/ EVENTOUT
-
30 J4 48 70 R13 80 PB11 I/O FT -
I2C2_SDA/USART3_RX/
OTG_HS_ULPI_D4 /
ETH_RMII_TX_EN/
ETH_MII_TX_EN /
TIM2_CH4/ EVENTOUT
-
31 F4 49 71 M10 81 VCAP_1 S- - -
32 - 50 72 N10 82 VDD S- - -
- - - - M11 83 PH6 I/O FT -
I2C2_SMBA / TIM12_CH1 /
ETH_MII_RXD2/
EVENTOUT
-
- - - - N12 84 PH7 I/O FT -
I2C3_SCL /
ETH_MII_RXD3/
EVENTOUT
-
- - - - M12 85 PH8 I/O FT -
I2C3_SDA /
DCMI_HSYNC/
EVENTOUT
-
- - - - M13 86 PH9 I/O FT - I2C3_SMBA / TIM12_CH2/
DCMI_D0/ EVENTOUT -
- - - - L13 87 PH10 I/O FT - TIM5_CH1 / DCMI_D1/
EVENTOUT -
- - - - L12 88 PH11 I/O FT - TIM5_CH2 / DCMI_D2/
EVENTOUT -
- - - - K12 89 PH12 I/O FT - TIM5_CH3 / DCMI_D3/
EVENTOUT -
- - - - H12 90 VSS S- - - -
- - - - J12 91 VDD S- - - -
33 J3 51 73 P12 92 PB12 I/O FT -
SPI2_NSS / I2S2_WS /
I2C2_SMBA/
USART3_CK/ TIM1_BKIN /
CAN2_RX /
OTG_HS_ULPI_D5/
ETH_RMII_TXD0 /
ETH_MII_TXD0/
OTG_HS_ID/ EVENTOUT
-
34 J1 52 74 P13 93 PB13 I/O FT -
SPI2_SCK / I2S2_CK /
USART3_CTS/
TIM1_CH1N /CAN2_TX /
OTG_HS_ULPI_D6 /
ETH_RMII_TXD1 /
ETH_MII_TXD1/
EVENTOUT
OTG_HS_VBUS
35 J2 53 75 R14 94 PB14 I/O FT -
SPI2_MISO/ TIM1_CH2N /
TIM12_CH1 /
OTG_HS_DM/
USART3_RTS /
TIM8_CH2N/I2S2ext_SD/
EVENTOUT
-
36 H1 54 76 R15 95 PB15 I/O FT -
SPI2_MOSI / I2S2_SD/
TIM1_CH3N / TIM8_CH3N
/ TIM12_CH2 /
OTG_HS_DP/ EVENTOUT
RTC_REFIN
- H2 55 77 P15 96 PD8 I/O FT - FSMC_D13 / USART3_TX/
EVENTOUT -
- H3 56 78 P14 97 PD9 I/O FT - FSMC_D14 / USART3_RX/
EVENTOUT -
- G3 57 79 N15 98 PD10 I/O FT - FSMC_D15 / USART3_CK/
EVENTOUT -
- G1 58 80 N14 99 PD11 I/O FT -
FSMC_CLE /
FSMC_A16/USART3_CTS/
EVENTOUT
-
- G2 59 81 N13 100 PD12 I/O FT -
FSMC_ALE/
FSMC_A17/TIM4_CH1 /
USART3_RTS/
EVENTOUT
-
- - 60 82 M15 101 PD13 I/O FT - FSMC_A18/TIM4_CH2/
EVENTOUT -
- - - 83 - 102 VSS S- - -
- - - 84 J13 103 VDD S- - -
- F2 61 85 M14 104 PD14 I/O FT - FSMC_D0/TIM4_CH3/
EVENTOUT/ EVENTOUT -
- F1 62 86 L14 105 PD15 I/O FT - FSMC_D1/TIM4_CH4/
EVENTOUT -
- - - 87 L15 106 PG2 I/O FT - FSMC_A12/ EVENTOUT -
- - - 88 K15 107 PG3 I/O FT - FSMC_A13/ EVENTOUT -
- - - 89 K14 108 PG4 I/O FT - FSMC_A14/ EVENTOUT -
- - - 90 K13 109 PG5 I/O FT - FSMC_A15/ EVENTOUT -
- - - 91 J15 110 PG6 I/O FT - FSMC_INT2/ EVENTOUT -
- - - 92 J14 111 PG7 I/O FT - FSMC_INT3 /USART6_CK/
EVENTOUT -
- - - 93 H14 112 PG8 I/O FT -
USART6_RTS /
ETH_PPS_OUT/
EVENTOUT
-
- - - 94 G12 113 VSS S- - -
- - - 95 H13 114 VDD S- - -
37 F3 63 96 H15 115 PC6 I/O FT -
I2S2_MCK /
TIM8_CH1/SDIO_D6 /
USART6_TX /
DCMI_D0/TIM3_CH1/
EVENTOUT
-
38 E1 64 97 G15 116 PC7 I/O FT -
I2S3_MCK /
TIM8_CH2/SDIO_D7 /
USART6_RX /
DCMI_D1/TIM3_CH2/
EVENTOUT
-
39 E2 65 98 G14 117 PC8 I/O FT -
TIM8_CH3/SDIO_D0
/TIM3_CH3/ USART6_CK /
DCMI_D2/ EVENTOUT
-
40 E3 66 99 F14 118 PC9 I/O FT -
I2S_CKIN/ MCO2 /
TIM8_CH4/SDIO_D1 /
/I2C3_SDA / DCMI_D3 /
TIM3_CH4/ EVENTOUT
-
41 D1 67 100 F15 119 PA8 I/O FT -
MCO1 / USART1_CK/
TIM1_CH1/ I2C3_SCL/
OTG_FS_SOF/
EVENTOUT
-
42 D2 68 101 E15 120 PA9 I/O FT -
USART1_TX/ TIM1_CH2 /
I2C3_SMBA / DCMI_D0/
EVENTOUT
OTG_FS_VBUS
43 D3 69 102 D15 121 PA10 I/O FT -
USART1_RX/ TIM1_CH3/
OTG_FS_ID/DCMI_D1/
EVENTOUT
-
44 C1 70 103 C15 122 PA11 I/O FT -
USART1_CTS / CAN1_RX
/ TIM1_CH4 /
OTG_FS_DM/ EVENTOUT
-
45 C2 71 104 B15 123 PA12 I/O FT -
USART1_RTS / CAN1_TX/
TIM1_ETR/ OTG_FS_DP/
EVENTOUT
-
46 D4 72 105 A15 124 PA13
(JTMS-SWDIO) I/O FT - JTMS-SWDIO/ EVENTOUT -
47 B1 73 106 F13 125 VCAP_2 S- - - -
- E7 74 107 F12 126 VSS S- - - -
48 E6 75 108 G13 127 VDD S- - - -
- - - - E12 128 PH13 I/O FT - TIM8_CH1N / CAN1_TX/
EVENTOUT -
- - - - E13 129 PH14 I/O FT - TIM8_CH2N / DCMI_D4/
EVENTOUT -
- - - - D13 130 PH15 I/O FT - TIM8_CH3N / DCMI_D11/
EVENTOUT -
- C3 - - E14 131 PI0 I/O FT -
TIM5_CH4 / SPI2_NSS /
I2S2_WS / DCMI_D13/
EVENTOUT
-
- B2 - - D14 132 PI1 I/O FT - SPI2_SCK / I2S2_CK /
DCMI_D8/ EVENTOUT -
- - - - C14 133 PI2 I/O FT -
TIM8_CH4 /SPI2_MISO /
DCMI_D9 / I2S2ext_SD/
EVENTOUT
-
- - - - C13 134 PI3 I/O FT
TIM8_ETR / SPI2_MOSI /
I2S2_SD / DCMI_D10/
EVENTOUT
-
- - - - D9 135 VSS S- - - -
- - - - C9 136 VDD S- - - -
49 A2 76 109 A14 137
PA14
(JTCK/SWCLK) I/O FT - JTCK-SWCLK/ EVENTOUT -
50 B3 77 110 A13 138 PA15
(JTDI) I/O FT -
JTDI/ SPI3_NSS/
I2S3_WS/TIM2_CH1_ETR
/ SPI1_NSS / EVENTOUT
-
51 D5 78 111 B14 139 PC10 I/O FT -
SPI3_SCK / I2S3_CK/
UART4_TX/SDIO_D2 /
DCMI_D8 / USART3_TX/
EVENTOUT
-
52 C4 79 112 B13 140 PC11 I/O FT -
UART4_RX/ SPI3_MISO /
SDIO_D3 /
DCMI_D4/USART3_RX /
I2S3ext_SD/ EVENTOUT
-
53 A3 80 113 A12 141 PC12 I/O FT -
UART5_TX/SDIO_CK /
DCMI_D9 / SPI3_MOSI
/I2S3_SD / USART3_CK/
EVENTOUT
-
- D6 81 114 B12 142 PD0 I/O FT - FSMC_D2/CAN1_RX/
EVENTOUT -
- C5 82 115 C12 143 PD1 I/O FT - FSMC_D3 / CAN1_TX/
EVENTOUT -
54 B4 83 116 D12 144 PD2 I/O FT -
TIM3_ETR/UART5_RX/
SDIO_CMD / DCMI_D11/
EVENTOUT
-
- - 84 117 D11 145 PD3 I/O FT -
FSMC_CLK/
USART2_CTS/
EVENTOUT
-
- A4 85 118 D10 146 PD4 I/O FT -
FSMC_NOE/
USART2_RTS/
EVENTOUT
-
- C6 86 119 C11 147 PD5 I/O FT - FSMC_NWE/USART2_TX/
EVENTOUT -
- - - 120 D8 148 VSS S- - - -
- - - 121 C8 149 VDD S- - - -
- B5 87 122 B11 150 PD6 I/O FT - FSMC_NWAIT/
USART2_RX/ EVENTOUT -
- A5 88 123 A11 151 PD7 I/O FT - USART2_CK/FSMC_NE1/
FSMC_NCE2/ EVENTOUT -
- - - 124 C10 152 PG9 I/O FT -
USART6_RX /
FSMC_NE2/FSMC_NCE3/
EVENTOUT
-
- - - 125 B10 153 PG10 I/O FT - FSMC_NCE4_1/
FSMC_NE3/ EVENTOUT -
- - - 126 B9 154 PG11 I/O FT -
FSMC_NCE4_2 /
ETH_MII_TX_EN/
ETH _RMII_TX_EN/
EVENTOUT
-
- - - 127 B8 155 PG12 I/O FT -
FSMC_NE4 /
USART6_RTS/
EVENTOUT
-
- - - 128 A8 156 PG13 I/O FT -
FSMC_A24 /
USART6_CTS
/ETH_MII_TXD0/
ETH_RMII_TXD0/
EVENTOUT
-
- - - 129 A7 157 PG14 I/O FT -
FSMC_A25 / USART6_TX
/ETH_MII_TXD1/
ETH_RMII_TXD1/
EVENTOUT
-
- E8 - 130 D7 158 VSS S- - - -
- F7 - 131 C7 159 VDD S- - - -
- - - 132 B7 160 PG15 I/O FT - USART6_CTS /
DCMI_D13/ EVENTOUT -
55 B6 89 133 A10 161
PB3
(JTDO/
TRACESWO)
I/O FT -
JTDO/ TRACESWO/
SPI3_SCK / I2S3_CK /
TIM2_CH2 / SPI1_SCK/
EVENTOUT
-
56 A6 90 134 A9 162
PB4
(NJTRST) I/O FT -
NJTRST/ SPI3_MISO /
TIM3_CH1 / SPI1_MISO /
I2S3ext_SD/ EVENTOUT
-
57 D7 91 135 A6 163 PB5 I/O FT -
I2C1_SMBA/ CAN2_RX /
OTG_HS_ULPI_D7 /
ETH_PPS_OUT/TIM3_CH2
/ SPI1_MOSI/ SPI3_MOSI /
DCMI_D10 / I2S3_SD/
EVENTOUT
-
58 C7 92 136 B6 164 PB6 I/O FT -
I2C1_SCL/ TIM4_CH1 /
CAN2_TX /
DCMI_D5/USART1_TX/
EVENTOUT
-
59 B7 93 137 B5 165 PB7 I/O FT -
I2C1_SDA / FSMC_NL /
DCMI_VSYNC /
USART1_RX/ TIM4_CH2/
EVENTOUT
-
60 A7 94 138 D6 166 BOOT0 I B - - VPP
61 D8 95 139 A5 167 PB8 I/O FT -
TIM4_CH3/SDIO_D4/
TIM10_CH1 / DCMI_D6 /
ETH_MII_TXD3 /
I2C1_SCL/ CAN1_RX/
EVENTOUT
-
62 C8 96 140 B4 168 PB9 I/O FT -
SPI2_NSS/ I2S2_WS /
TIM4_CH4/ TIM11_CH1/
SDIO_D5 / DCMI_D7 /
I2C1_SDA / CAN1_TX/
EVENTOUT
-
- - 97 141 A4 169 PE0 I/O FT - TIM4_ETR / FSMC_NBL0 /
DCMI_D2/ EVENTOUT -
- - 98 142 A3 170 PE1 I/O FT - FSMC_NBL1 / DCMI_D3/
EVENTOUT -
63 - 99 - D5 - VSS S- - - -
- A8 - 143 C6 171 PDR_ON I FT - - -
64 A1 10
0 144 C5 172 VDD S- - - -
- - - - D4 173 PI4 I/O FT - TIM8_BKIN / DCMI_D5/
EVENTOUT -
- - - - C4 174 PI5 I/O FT -
TIM8_CH1 /
DCMI_VSYNC/
EVENTOUT
-
- - - - C3 175 PI6 I/O FT - TIM8_CH2 / DCMI_D6/
EVENTOUT -
- - - - C2 176 PI7 I/O FT - TIM8_CH3 / DCMI_D7/
EVENTOUT -

View File

@ -0,0 +1,75 @@
STM34F407 100pin 管脚定义
* PIN_Number--> aaaaaPIN_Number
```
查找: ^(\d+|-)\s\S+\s((\d+|-))\s\S+\s\S+\s\S+
替换: aaaaa$2
```
* \n --> (空格)
```
查找: \n
替换: (空格)
```
* aaaaa --> \n
```
查找: aaaaa
替换: \n
```
* 首字是"-",删除整行
```
查找: ^-.+\n
替换: (空白)
```
* "-","EVENTOUT","I/O","FT","," ,"I","O","B"-->(空格)
```
查找: \s-(?=\s|\n)|EVENTOUT|I/O|FT\w*|\(\d+\)|,|\sI(?=\s)|\sO(?=\s)|\sS(?=\s)|\sB(?=\s)
替换: (空格)
```
* 行首数字后的空白--> ","
```
查找: (?<=^\d+)\s+
替换: ,
```
* 删除"/"前后的空格
* 查找: /\s+
* 替换: ,
* 查找: \s+/
* 替换: ,
* 删除注释"(3)"
* 查找: \(\s*\d\s*\)
* 替换: (空格)
* 删除 “S-”
* 查找: \sS-\s
* 替换: (空格)
* 空白==>"/"
```
查找: \s+(?=\S)
替换: /
```
* 删除行末空白
```
查找: \s+$
替换: (空白)
```
* 删除 “TTa"
* 查找: TTa\s*/
* 替换: (空)
* 删除行末/
```
查找: /$
替换: (空白)
```
* 排序
* 在wps 排序
* 加locate : 公式 =(101-row())*100
* 转成kicad库
```
查找: ^(\d+),(.*),(\d+)$
替换: X $2 $1 2300 $3 100 L 50 50 1 1 B
```