From cc30b3f3d3a7299dcd02ecac9dcb0d580ea172a0 Mon Sep 17 00:00:00 2001 From: james <1943357252@qq.com> Date: Sun, 4 Aug 2024 15:57:12 +0800 Subject: [PATCH] S --- applications/main.c | 5 +- board/SConscript | 2 +- board/linker_scripts/link.lds | 126 ++++- board/startup_stm32f407xx.s | 535 ++++++++++++++++++ .../Templates/gcc/startup_stm32f407xx.s | 67 +-- 5 files changed, 657 insertions(+), 78 deletions(-) create mode 100644 board/startup_stm32f407xx.s diff --git a/applications/main.c b/applications/main.c index 79b67e5..5f67466 100644 --- a/applications/main.c +++ b/applications/main.c @@ -19,6 +19,7 @@ #include #include "my_func.h" +#include /* 配置 LED 灯引脚 */ @@ -102,7 +103,9 @@ void xy_sink() // } int main(void) { - // system("snake game"); + rt_pin_mode(PIN_LED_B, PIN_MODE_OUTPUT); + rt_pin_write(PIN_LED_B, PIN_HIGH); + system("snake game"); char str[] = "wifi join Dong abcd07691234"; my_round(20); rt_wlan_config_autoreconnect(RT_TRUE); diff --git a/board/SConscript b/board/SConscript index dcffdb0..34eece8 100644 --- a/board/SConscript +++ b/board/SConscript @@ -18,7 +18,7 @@ path += [cwd + '/CubeMX_Config/Inc'] startup_path_prefix = SDK_LIB if rtconfig.PLATFORM in ['gcc', 'llvm-arm']: - src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s'] + src += [ cwd + '/startup_stm32f407xx.s'] elif rtconfig.PLATFORM in ['armcc', 'armclang']: src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f407xx.s'] elif rtconfig.PLATFORM in ['iccarm']: diff --git a/board/linker_scripts/link.lds b/board/linker_scripts/link.lds index 2d48a9e..43f91c0 100644 --- a/board/linker_scripts/link.lds +++ b/board/linker_scripts/link.lds @@ -7,13 +7,12 @@ /* Program Entry, set to mark it as "used" and avoid gc */ MEMORY { - CODE (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ - RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */ - RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K sram */ - MCUlcdgrambysram (rw) : ORIGIN = 0x68000000, LENGTH = 1024k + FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1024k - 128k /* 1024KB - 128kB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */ + CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K ccm sram */ } ENTRY(Reset_Handler) -_system_stack_size = 0x400; +_system_stack_size = 0x200; SECTIONS { @@ -43,12 +42,6 @@ SECTIONS KEEP(*(VSymTab)) __vsymtab_end = .; - /* section information for utest */ - . = ALIGN(4); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - /* section information for initial. */ . = ALIGN(4); __rt_init_start = .; @@ -62,12 +55,16 @@ SECTIONS KEEP (*(.init_array)) PROVIDE(__ctors_end__ = .); + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + . = ALIGN(4); - KEEP(*(.eh_frame*)) - . = ALIGN(4); _etext = .; - } > CODE = 0 + } > FLASH = 0 /* .ARM.exidx is sorted, so has to go in its own output section. */ __exidx_start = .; @@ -77,12 +74,13 @@ SECTIONS /* This is used by the startup in order to initialize the .data secion */ _sidata = .; - } > CODE + } > FLASH __exidx_end = .; + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); /* .data section which is used for initialized data */ - - .data : AT (_sidata) + .data : { . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ @@ -100,7 +98,86 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; - } >RAM1 + } >RAM AT> FLASH + + _siccmdata = LOADADDR(.ccmdata); /* May be already present */ + + /* Initialized CCM-RAM section + * + * IMPORTANT NOTE! + * If initialized variables will be placed in this section, + * the startup code needs to be modified to copy the init-values. + */ + .ccmdata : + { + . = ALIGN(4); + _sccmdata = .; /* create a global symbol at data start */ + *(.ccmdata) /* .data sections */ + *(.ccmdata*) /* .data* sections */ +/* + *data_reg.o(.data .data*) + *monitor*.o(.data .data*) + *sender*.o(.data .data*) + *kernel*.o(.data .data*) +*/ + . = ALIGN(4); + _eccmdata = .; /* define a global symbol at data end */ + } >CCMRAM AT> FLASH + + + /* _siccm_bss = LOADADDR(.ccm_bss); */ + /* CCM-RAM section + * + * IMPORTANT NOTE! + * If initialized variables will be placed in this section, + * the startup code needs to be modified to copy the init-values. + */ + .ccm_bss : + { + . = ALIGN(4); + _sccm_bss = .; /* create a global symbol at ccmram start */ + *(.ccm_bss) + *(.ccm_bss*) + + /* build\\core\\*.o(.bss .bss*) */ + build\\monitor\\**.o(.bss .bss*) + build\\sender\\**.o(.bss .bss*) + /* build\\mapping\\**.o(.bss .bss*) */ + + /* *board*.o(.bss .bss*) */ + /* *autosave.o(.bss .bss*)*/ + /* *application*autosave.o(.bss .bss*) */ + /* *data_send.o(.bss .bss*) */ + /* *isee_http.o(.bss .bss*) */ + /* *config.o(.bss .bss*) */ + /* *dio.o(.bss .bss*) */ + /* *eth.o(.bss .bss*) */ + /* *led.o(.bss .bss*) */ + + /* *packages*agile_telnet*.o(.bss .bss*) */ + /* *packages*agile_console*.o(.bss .bss*) */ + /* *packages*cJSON*.o(.bss .bss*) */ + /* *packages*CmBacktrace*.o(.bss .bss*)*/ + /* *packages*easyblink*.o(.bss .bss*) */ + /* *packages*webclient*.o(.bss .bss*) */ + /* *packages*netutils*.o(.bss .bss*) */ + /* *packages*syswatch*.o(.bss .bss*) */ + /* *packages*UrlEncode*.o(.bss .bss*) */ + + build\\kernel\\src\\*.o(.bss .bss*) + /* build\\kernel\\libcpu\\*.o(.bss .bss*) */ + /* build\\kernel\\components\\libc\\*.o(.bss .bss*) + /* build\\kernel\\components\\drivers\\*.o(.bss .bss*) */ + /* build\\kernel\\components\\dfs\\*.o(.bss .bss*) */ + build\\kernel\\components\\net\\lwip\\lwip-2.0.3\\*.o(.bss .bss*) + /* build\\kernel\\components\\net\\lwip\\port\\**.o(.bss .bss*) */ + /* build\\kernel\\components\\net\\sal\\*.o(.bss .bss*) */ + /* build\\kernel\\components\\net\\netdev\\*.o(.bss .bss*) */ + /* build\\kernel\\components\\net\\sal_socket\\*.o(.bss .bss*) */ + + . = ALIGN(4); + _eccm_bss = .; /* create a global symbol at ccmram end */ + } >CCMRAM .stack : { @@ -109,7 +186,7 @@ SECTIONS . = . + _system_stack_size; . = ALIGN(4); _estack = .; - } >RAM1 + } >RAM __bss_start = .; .bss : @@ -127,18 +204,9 @@ SECTIONS _ebss = . ; *(.bss.init) - } > RAM1 + } > RAM __bss_end = .; - .MCUlcdgrambysram (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - *(.MCUlcdgrambysram) - *(.MCUlcdgrambysram.*) - . = ALIGN(4); - __MCUlcdgrambysram_free__ = .; - } > MCUlcdgrambysram - _end = .; /* Stabs debugging sections. */ diff --git a/board/startup_stm32f407xx.s b/board/startup_stm32f407xx.s new file mode 100644 index 0000000..0539dcf --- /dev/null +++ b/board/startup_stm32f407xx.s @@ -0,0 +1,535 @@ +/** + ****************************************************************************** + * @file startup_stm32f407xx.s + * @author MCD Application Team + * @brief STM32F407xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Copy from flash to CCMRAM */ + ldr r0, =_sccmdata + ldr r1, =_eccmdata + ldr r2, =_siccmdata + movs r3, #0 + b LoopCopyCcmInit +CopyCcmInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 +LoopCopyCcmInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyCcmInit +/* End of copy to CCMRAM */ + + ldr r2, =_sccm_bss + b LoopFillZeroCcm +/* Zero fill the ccm bss segment. */ +FillZeroCcm: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZeroCcm: + ldr r3, = _eccm_bss + cmp r2, r3 + bcc FillZeroCcm +/* End of zero fill to CCMRAM */ + + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ +/* bl __libc_init_array */ +/* Call the application's entry point.*/ + bl entry + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s b/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s index 0539dcf..85c0618 100644 --- a/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s +++ b/libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s @@ -62,67 +62,40 @@ Reset_Handler: ldr sp, =_estack /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Copy from flash to CCMRAM */ - ldr r0, =_sccmdata - ldr r1, =_eccmdata - ldr r2, =_siccmdata - movs r3, #0 - b LoopCopyCcmInit -CopyCcmInit: ldr r4, [r2, r3] str r4, [r0, r3] adds r3, r3, #4 -LoopCopyCcmInit: + +LoopCopyDataInit: adds r4, r0, r3 cmp r4, r1 - bcc CopyCcmInit -/* End of copy to CCMRAM */ + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss - ldr r2, =_sccm_bss - b LoopFillZeroCcm -/* Zero fill the ccm bss segment. */ -FillZeroCcm: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZeroCcm: - ldr r3, = _eccm_bss - cmp r2, r3 - bcc FillZeroCcm -/* End of zero fill to CCMRAM */ - - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ FillZerobss: - movs r3, #0 - str r3, [r2], #4 - + str r3, [r2] + adds r2, r2, #4 + LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ -/* bl __libc_init_array */ + bl __libc_init_array /* Call the application's entry point.*/ bl entry bx lr