This commit is contained in:
parent
e4ac1a31ca
commit
cc30b3f3d3
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@ -19,6 +19,7 @@
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#include <drv_lcd.h>
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#include "my_func.h"
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#include <drv_gpio.h>
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/* 配置 LED 灯引脚 */
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@ -102,7 +103,9 @@ void xy_sink()
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// }
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int main(void)
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{
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// system("snake game");
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rt_pin_mode(PIN_LED_B, PIN_MODE_OUTPUT);
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rt_pin_write(PIN_LED_B, PIN_HIGH);
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system("snake game");
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char str[] = "wifi join Dong abcd07691234";
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my_round(20);
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rt_wlan_config_autoreconnect(RT_TRUE);
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@ -18,7 +18,7 @@ path += [cwd + '/CubeMX_Config/Inc']
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startup_path_prefix = SDK_LIB
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if rtconfig.PLATFORM in ['gcc', 'llvm-arm']:
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src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s']
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src += [ cwd + '/startup_stm32f407xx.s']
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elif rtconfig.PLATFORM in ['armcc', 'armclang']:
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src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f407xx.s']
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elif rtconfig.PLATFORM in ['iccarm']:
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@ -7,13 +7,12 @@
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/* Program Entry, set to mark it as "used" and avoid gc */
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MEMORY
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{
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CODE (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */
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RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */
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RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K sram */
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MCUlcdgrambysram (rw) : ORIGIN = 0x68000000, LENGTH = 1024k
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FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1024k - 128k /* 1024KB - 128kB flash */
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RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */
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CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K ccm sram */
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}
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ENTRY(Reset_Handler)
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_system_stack_size = 0x400;
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_system_stack_size = 0x200;
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SECTIONS
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{
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@ -43,12 +42,6 @@ SECTIONS
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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/* section information for utest */
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. = ALIGN(4);
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__rt_utest_tc_tab_start = .;
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KEEP(*(UtestTcTab))
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__rt_utest_tc_tab_end = .;
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/* section information for initial. */
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. = ALIGN(4);
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__rt_init_start = .;
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@ -62,12 +55,16 @@ SECTIONS
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KEEP (*(.init_array))
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PROVIDE(__ctors_end__ = .);
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/* section information for utest */
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. = ALIGN(4);
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__rt_utest_tc_tab_start = .;
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KEEP(*(UtestTcTab))
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__rt_utest_tc_tab_end = .;
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. = ALIGN(4);
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KEEP(*(.eh_frame*))
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. = ALIGN(4);
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_etext = .;
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} > CODE = 0
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} > FLASH = 0
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/* .ARM.exidx is sorted, so has to go in its own output section. */
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__exidx_start = .;
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@ -77,12 +74,13 @@ SECTIONS
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/* This is used by the startup in order to initialize the .data secion */
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_sidata = .;
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} > CODE
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} > FLASH
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__exidx_end = .;
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/* used by the startup to initialize data */
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_sidata = LOADADDR(.data);
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/* .data section which is used for initialized data */
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.data : AT (_sidata)
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.data :
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{
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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@ -100,7 +98,86 @@ SECTIONS
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_edata = . ;
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} >RAM1
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} >RAM AT> FLASH
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_siccmdata = LOADADDR(.ccmdata); /* May be already present */
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/* Initialized CCM-RAM section
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*
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* IMPORTANT NOTE!
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* If initialized variables will be placed in this section,
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* the startup code needs to be modified to copy the init-values.
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*/
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.ccmdata :
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{
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. = ALIGN(4);
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_sccmdata = .; /* create a global symbol at data start */
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*(.ccmdata) /* .data sections */
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*(.ccmdata*) /* .data* sections */
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/*
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*data_reg.o(.data .data*)
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*monitor*.o(.data .data*)
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*sender*.o(.data .data*)
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*kernel*.o(.data .data*)
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*/
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. = ALIGN(4);
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_eccmdata = .; /* define a global symbol at data end */
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} >CCMRAM AT> FLASH
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/* _siccm_bss = LOADADDR(.ccm_bss); */
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/* CCM-RAM section
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*
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* IMPORTANT NOTE!
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* If initialized variables will be placed in this section,
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* the startup code needs to be modified to copy the init-values.
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*/
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.ccm_bss :
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{
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. = ALIGN(4);
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_sccm_bss = .; /* create a global symbol at ccmram start */
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*(.ccm_bss)
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*(.ccm_bss*)
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/* build\\core\\*.o(.bss .bss*) */
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build\\monitor\\**.o(.bss .bss*)
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build\\sender\\**.o(.bss .bss*)
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/* build\\mapping\\**.o(.bss .bss*) */
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/* *board*.o(.bss .bss*) */
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/* *autosave.o(.bss .bss*)*/
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/* *application*autosave.o(.bss .bss*) */
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/* *data_send.o(.bss .bss*) */
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/* *isee_http.o(.bss .bss*) */
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/* *config.o(.bss .bss*) */
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/* *dio.o(.bss .bss*) */
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/* *eth.o(.bss .bss*) */
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/* *led.o(.bss .bss*) */
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/* *packages*agile_telnet*.o(.bss .bss*) */
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/* *packages*agile_console*.o(.bss .bss*) */
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/* *packages*cJSON*.o(.bss .bss*) */
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/* *packages*CmBacktrace*.o(.bss .bss*)*/
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/* *packages*easyblink*.o(.bss .bss*) */
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/* *packages*webclient*.o(.bss .bss*) */
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/* *packages*netutils*.o(.bss .bss*) */
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/* *packages*syswatch*.o(.bss .bss*) */
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/* *packages*UrlEncode*.o(.bss .bss*) */
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build\\kernel\\src\\*.o(.bss .bss*)
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/* build\\kernel\\libcpu\\*.o(.bss .bss*) */
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/* build\\kernel\\components\\libc\\*.o(.bss .bss*)
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/* build\\kernel\\components\\drivers\\*.o(.bss .bss*) */
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/* build\\kernel\\components\\dfs\\*.o(.bss .bss*) */
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build\\kernel\\components\\net\\lwip\\lwip-2.0.3\\*.o(.bss .bss*)
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/* build\\kernel\\components\\net\\lwip\\port\\**.o(.bss .bss*) */
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/* build\\kernel\\components\\net\\sal\\*.o(.bss .bss*) */
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/* build\\kernel\\components\\net\\netdev\\*.o(.bss .bss*) */
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/* build\\kernel\\components\\net\\sal_socket\\*.o(.bss .bss*) */
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. = ALIGN(4);
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_eccm_bss = .; /* create a global symbol at ccmram end */
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} >CCMRAM
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.stack :
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{
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@ -109,7 +186,7 @@ SECTIONS
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. = . + _system_stack_size;
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. = ALIGN(4);
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_estack = .;
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} >RAM1
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} >RAM
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__bss_start = .;
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.bss :
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@ -127,18 +204,9 @@ SECTIONS
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_ebss = . ;
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*(.bss.init)
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} > RAM1
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} > RAM
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__bss_end = .;
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.MCUlcdgrambysram (NOLOAD) : ALIGN(4)
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{
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. = ALIGN(4);
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*(.MCUlcdgrambysram)
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*(.MCUlcdgrambysram.*)
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. = ALIGN(4);
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__MCUlcdgrambysram_free__ = .;
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} > MCUlcdgrambysram
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_end = .;
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/* Stabs debugging sections. */
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@ -0,0 +1,535 @@
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/**
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******************************************************************************
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* @file startup_stm32f407xx.s
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* @author MCD Application Team
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* @brief STM32F407xx Devices vector table for GCC based toolchains.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M4 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m4
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr sp, =_estack /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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/* Copy from flash to CCMRAM */
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ldr r0, =_sccmdata
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ldr r1, =_eccmdata
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ldr r2, =_siccmdata
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movs r3, #0
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b LoopCopyCcmInit
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CopyCcmInit:
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ldr r4, [r2, r3]
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str r4, [r0, r3]
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adds r3, r3, #4
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LoopCopyCcmInit:
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adds r4, r0, r3
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cmp r4, r1
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bcc CopyCcmInit
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/* End of copy to CCMRAM */
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ldr r2, =_sccm_bss
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b LoopFillZeroCcm
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/* Zero fill the ccm bss segment. */
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FillZeroCcm:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZeroCcm:
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ldr r3, = _eccm_bss
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cmp r2, r3
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bcc FillZeroCcm
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/* End of zero fill to CCMRAM */
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors */
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/* bl __libc_init_array */
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/* Call the application's entry point.*/
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bl entry
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bx lr
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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* @param None
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* @retval None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M3. Note that the proper constructs
|
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* must be placed on this to ensure that it ends up at physical address
|
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* 0x0000.0000.
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*
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
|
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
|
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
|
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
|
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.word PendSV_Handler
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.word SysTick_Handler
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|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window WatchDog */
|
||||
.word PVD_IRQHandler /* PVD through EXTI Line detection */
|
||||
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||
.word FLASH_IRQHandler /* FLASH */
|
||||
.word RCC_IRQHandler /* RCC */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||
.word CAN1_TX_IRQHandler /* CAN1 TX */
|
||||
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
|
||||
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
|
||||
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
|
||||
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||
.word FSMC_IRQHandler /* FSMC */
|
||||
.word SDIO_IRQHandler /* SDIO */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||
.word CAN2_TX_IRQHandler /* CAN2 TX */
|
||||
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
|
||||
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
|
||||
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word DCMI_IRQHandler /* DCMI */
|
||||
.word 0 /* CRYP crypto */
|
||||
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_TIM9_IRQHandler
|
||||
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM10_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_WKUP_IRQHandler
|
||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FSMC_IRQHandler
|
||||
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_WKUP_IRQHandler
|
||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_TX_IRQHandler
|
||||
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX0_IRQHandler
|
||||
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX1_IRQHandler
|
||||
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_SCE_IRQHandler
|
||||
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_WKUP_IRQHandler
|
||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_IRQHandler
|
||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_RNG_IRQHandler
|
||||
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -62,67 +62,40 @@ Reset_Handler:
|
|||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Copy from flash to CCMRAM */
|
||||
ldr r0, =_sccmdata
|
||||
ldr r1, =_eccmdata
|
||||
ldr r2, =_siccmdata
|
||||
movs r3, #0
|
||||
b LoopCopyCcmInit
|
||||
CopyCcmInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
LoopCopyCcmInit:
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyCcmInit
|
||||
/* End of copy to CCMRAM */
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
ldr r2, =_sccm_bss
|
||||
b LoopFillZeroCcm
|
||||
/* Zero fill the ccm bss segment. */
|
||||
FillZeroCcm:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZeroCcm:
|
||||
ldr r3, = _eccm_bss
|
||||
cmp r2, r3
|
||||
bcc FillZeroCcm
|
||||
/* End of zero fill to CCMRAM */
|
||||
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
/* bl __libc_init_array */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl entry
|
||||
bx lr
|
||||
|
|
|
|||
Loading…
Reference in New Issue