rtt更新

rt-thread/components/drivers/usb/cherryusb/port/xhci/phytium/README.md

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+# USB 3.0 Host 控制器 (XHCI)
+
+- Phytium PI 和 Phyium E2000 系列开发板提供符合 XHCI 1.1 规范的 USB 3.0 Host 控制器, 其它 Phytium 系列平台可以通过 PCIe 扩展卡获得 XHCI 控制器
+- 相关的使用例程可以在 Phytium PI（飞腾派）、E2000 D/Q Demo 板以及 D2000 和后续平台上运行，例程包括
+
+---------------------------------------------
+
+- FreeRTOS
+
+- - 1. [XHCI 平台控制器使用鼠标/键盘/U盘功能](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/xhci_platform/README.md)
+- - 2. [XHCI PCIe控制器使用鼠标/键盘/U盘功能](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/xhci_pcie/README.md)
+- - 3. [LVGL 中使用 XHCI 平台控制器连接的鼠标/键盘/U盘](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/example/peripheral/media/lvgl_indev/README.md)
+
+---------------------------------------------
+
+- RT-Thread 
+
+- - 1. [XHCI 平台控制器识别鼠标/键盘/U盘](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md)
+
+---------------------------------------------
+
+- Standalone 裸机
+
+- - 暂不支持 
+
+---------------------------------------------
+
+- XHCI 的驱动功能以静态库的方式提供，仅限在 Phytium 系列 CPU 平台使用，
+
+- - libxhci_a64.a : AARCH64 驱动库
+- - libxhci_a32_hardfp.a : AARCH32 驱动库，使用硬浮点
+- - libxhci_a32_softfp.a : AARCH32 驱动库，使用软浮点
+
+需要获取源代码请联系 `opensource_embedded@phytium.com.cn` 获取，如需移植运行到非 Phytium 系列 CPU 平台请提前联系`opensource_embedded@phytium.com.cn`获得允许
+
+# USB 3.0 Host Controller (XHCI)
+
+- The Phytium PI and Phytium E2000 series development boards provide USB 3.0 Host controllers that conform to the XHCI 1.1 specification. Other Phytium series platforms can obtain XHCI controllers through PCIe expansion cards.
+- Related example routines can be run on Phytium PI (Fetion Pi), E2000 D/Q Demo boards, and D2000 and later platforms. Examples include:
+
+---------------------------------------------
+
+- FreeRTOS
+
+  - 1. [XHCI platform controller for mouse/keyboard/USB drive functions](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/xhci_platform/README.md)
+  - 2. [XHCI PCIe controller for mouse/keyboard/USB drive functions](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/xhci_pcie/README.md)
+  - 3. [Using XHCI platform controller-connected mouse/keyboard/USB drive in LVGL](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/example/peripheral/media/lvgl_indev/README.md)
+
+---------------------------------------------
+
+- RT-Thread
+
+  - 1. [XHCI platform controller recognizing mouse/keyboard/USB drive](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md)
+
+---------------------------------------------
+
+- Standalone (Bare Metal)
+
+  - Not supported yet
+
+---------------------------------------------
+
+- This XHCI driver functionality is provided as a static library and is only available for Phytium series CPU platforms. 
+
+  - - `libxhci_a64.a` : Driver library for AARCH64
+  - - `libxhci_a32_hardfp.a` : Driver library for AARCH32, using hard floating point
+  - - `libxhci_a32_softfp.a` : Driver library for AARCH32, using soft floating point
+
+- To obtain the source code, please contact `opensource_embedded@phytium.com.cn`. 
+- For porting to non-Phytium CPU platforms, shall contact `opensource_embedded@phytium.com.cn` in advance for permission.

rt-thread/components/drivers/usb/cherryusb/port/xhci/phytium/rt-thread/usb_config.h

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+/*
+ * Copyright : (C) 2024 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2024/6/26 first commit
+ */
+#ifndef CHERRYUSB_CONFIG_H
+#define CHERRYUSB_CONFIG_H
+
+#include "rtthread.h"
+
+/* ================ USB common Configuration ================ */
+
+#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__)
+
+void *xhci_mem_malloc(size_t align, size_t size);
+void xhci_mem_free(void *ptr);
+
+#define XHCI_DCACHE_FLUSH      (1 << 0)
+#define XHCI_DCACHE_INVALIDATE (1 << 1)
+void xhci_dcache_sync(void *ptr, size_t len, uint32_t flags);
+
+unsigned long usb_hc_get_register_base(uint32_t id);
+
+#define usb_malloc(size) xhci_mem_malloc(sizeof(int), size)
+#define usb_free(ptr)    xhci_mem_free(ptr)
+
+#ifndef CONFIG_USB_DBG_LEVEL
+#if defined(CONFIG_LOG_ERROR)
+#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR
+#elif defined(CONFIG_LOG_WARN)
+#define CONFIG_USB_DBG_LEVEL USB_DBG_WARNING
+#elif defined(CONFIG_LOG_INFO)
+#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
+#elif defined(CONFIG_LOG_DEBUG) || defined(CONFIG_LOG_VERBOS)
+#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG
+#else
+#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR
+#endif
+#endif
+
+/* Enable print with color */
+#define CONFIG_USB_PRINTF_COLOR_ENABLE
+
+/* data align size when use dma */
+#ifndef CONFIG_USB_ALIGN_SIZE
+#define CONFIG_USB_ALIGN_SIZE 4
+#endif
+
+/* attribute data into no cache ram */
+#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
+
+/* ================= USB Device Stack Configuration ================ */
+
+/* Ep0 in and out transfer buffer */
+#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN
+#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
+#endif
+
+/* Setup packet log for debug */
+// #define CONFIG_USBDEV_SETUP_LOG_PRINT
+
+/* Send ep0 in data from user buffer instead of copying into ep0 reqdata
+ * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE
+*/
+// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY
+
+/* Check if the input descriptor is correct */
+// #define CONFIG_USBDEV_DESC_CHECK
+
+/* Enable test mode */
+// #define CONFIG_USBDEV_TEST_MODE
+
+#ifndef CONFIG_USBDEV_MSC_MAX_LUN
+#define CONFIG_USBDEV_MSC_MAX_LUN 1
+#endif
+
+#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE
+#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512
+#endif
+
+#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING
+#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING ""
+#endif
+
+#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING
+#define CONFIG_USBDEV_MSC_PRODUCT_STRING ""
+#endif
+
+#ifndef CONFIG_USBDEV_MSC_VERSION_STRING
+#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01"
+#endif
+
+// #define CONFIG_USBDEV_MSC_THREAD
+
+#ifndef CONFIG_USBDEV_MSC_PRIO
+#define CONFIG_USBDEV_MSC_PRIO 4
+#endif
+
+#ifndef CONFIG_USBDEV_MSC_STACKSIZE
+#define CONFIG_USBDEV_MSC_STACKSIZE 2048
+#endif
+
+#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
+#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
+#endif
+
+/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/
+#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE
+#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580
+#endif
+
+#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID
+#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff
+#endif
+
+#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC
+#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB"
+#endif
+
+#define CONFIG_USBDEV_RNDIS_USING_LWIP
+
+/* ================ USB HOST Stack Configuration ================== */
+
+#define CONFIG_USBHOST_MAX_RHPORTS          8
+#define CONFIG_USBHOST_MAX_EXTHUBS          4
+#define CONFIG_USBHOST_MAX_EHPORTS          8
+#define CONFIG_USBHOST_MAX_INTERFACES       8
+#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8
+#define CONFIG_USBHOST_MAX_ENDPOINTS        8
+
+#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4
+#define CONFIG_USBHOST_MAX_HID_CLASS     4
+#define CONFIG_USBHOST_MAX_MSC_CLASS     2
+#define CONFIG_USBHOST_MAX_AUDIO_CLASS   1
+#define CONFIG_USBHOST_MAX_VIDEO_CLASS   1
+
+#define CONFIG_USBHOST_DEV_NAMELEN 16
+
+#ifndef CONFIG_USBHOST_PSC_PRIO
+#define CONFIG_USBHOST_PSC_PRIO 0
+#endif
+#ifndef CONFIG_USBHOST_PSC_STACKSIZE
+#define CONFIG_USBHOST_PSC_STACKSIZE 8192
+#endif
+
+//#define CONFIG_USBHOST_GET_STRING_DESC
+
+// #define CONFIG_USBHOST_MSOS_ENABLE
+#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE
+#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00
+#endif
+
+/* Ep0 max transfer buffer */
+#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN
+#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512
+#endif
+
+#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT
+#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500
+#endif
+
+#ifndef CONFIG_USBHOST_MSC_TIMEOUT
+#define CONFIG_USBHOST_MSC_TIMEOUT 0xffffffff
+#endif
+
+#ifndef CONFIG_INPUT_MOUSE_WHEEL
+#define CONFIG_INPUT_MOUSE_WHEEL
+#endif
+
+/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
+ * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
+ */
+#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE
+#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048)
+#endif
+
+/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
+#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE
+#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048)
+#endif
+
+/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
+ * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
+ */
+#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE
+#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048)
+#endif
+/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
+#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE
+#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048)
+#endif
+
+/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
+ * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
+ */
+#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE
+#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048)
+#endif
+/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
+#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE
+#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048)
+#endif
+
+/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
+ * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
+ */
+#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE
+#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048)
+#endif
+/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
+#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE
+#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048)
+#endif
+
+#define CONFIG_USBHOST_BLUETOOTH_HCI_H4
+// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG
+
+#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE
+#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048
+#endif
+#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE
+#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048
+#endif
+
+/* ================ USB Device Port Configuration ================*/
+
+#ifndef CONFIG_USBDEV_MAX_BUS
+#define CONFIG_USBDEV_MAX_BUS 2 // for now, bus num must be 1 except hpm ip
+#endif
+
+#ifndef CONFIG_USBDEV_EP_NUM
+#define CONFIG_USBDEV_EP_NUM 8
+#endif
+
+/* ---------------- FSDEV Configuration ---------------- */
+//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
+
+/* ---------------- DWC2 Configuration ---------------- */
+// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
+// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
+// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
+// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
+// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
+// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
+// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4)
+// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4)
+// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
+// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
+
+/* ---------------- MUSB Configuration ---------------- */
+// #define CONFIG_USB_MUSB_SUNXI
+
+/* ================ USB Host Port Configuration ==================*/
+#ifndef CONFIG_USBHOST_MAX_BUS
+#define CONFIG_USBHOST_MAX_BUS 2
+#endif
+
+#ifndef CONFIG_USBHOST_PIPE_NUM
+#define CONFIG_USBHOST_PIPE_NUM 10
+#endif
+
+/* ---------------- EHCI Configuration ---------------- */
+
+#define CONFIG_USB_EHCI_HCCR_OFFSET     (0x0)
+#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024
+#define CONFIG_USB_EHCI_QH_NUM          CONFIG_USBHOST_PIPE_NUM
+#define CONFIG_USB_EHCI_QTD_NUM         3
+#define CONFIG_USB_EHCI_ITD_NUM         20
+// #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
+// #define CONFIG_USB_EHCI_CONFIGFLAG
+// #define CONFIG_USB_EHCI_ISO
+// #define CONFIG_USB_EHCI_WITH_OHCI
+
+/* ---------------- OHCI Configuration ---------------- */
+#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0)
+
+/* ---------------- XHCI Configuration ---------------- */
+#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
+
+#ifndef CONFIG_USB_XHCI_ENABLE_SOFT_ISR
+#define CONFIG_USB_XHCI_ENABLE_SOFT_ISR   0
+#endif
+
+#endif

rt-thread/components/drivers/usb/cherryusb/port/xhci/phytium/rt-thread/usb_glue_phytium.c

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+/*
+ * Copyright : (C) 2024 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2024/6/26 first commit
+ */
+#include "rtthread.h"
+#include "usbh_core.h"
+
+#include "usb_config.h"
+
+void usb_hc_setup_xhci_interrupt(uint32_t id);
+void usb_hc_revoke_xhci_interrupt(uint32_t id);
+
+void *xhci_mem_malloc(size_t align, size_t size)
+{
+    void *result = rt_malloc_align(size, align);
+
+    if (result)
+    {
+        memset(result, 0U, size);
+    }
+
+    return result;
+}
+
+void xhci_mem_free(void *ptr)
+{
+    if (NULL != ptr)
+    {
+        rt_free(ptr);
+    }
+}
+
+void xhci_dcache_sync(void *ptr, size_t len, uint32_t flags)
+{
+    if (flags & XHCI_DCACHE_FLUSH)
+    {
+        rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, ptr, len);
+    }
+    else if (flags & XHCI_DCACHE_INVALIDATE)
+    {
+        rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, ptr, len);
+    }
+}
+
+void usb_assert(const char *filename, int linenum)
+{
+    rt_assert_handler("", filename, linenum);
+}
+
+void usb_hc_low_level_init(struct usbh_bus *bus)
+{
+    /* platform XHCI controller */
+    usb_hc_setup_xhci_interrupt(bus->busid);
+}
+
+void usb_hc_low_level_deinit(struct usbh_bus *bus)
+{
+    usb_hc_revoke_xhci_interrupt(bus->busid);
+}

rt-thread/components/drivers/usb/cherryusb/port/xhci/phytium/rt-thread/usb_glue_phytium_plat.c

@@ -0,0 +1,49 @@
+/*
+ * Copyright : (C) 2024 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2024/6/26 first commit
+ */
+#include "rtthread.h"
+#include "interrupt.h"
+
+#include "fparameters.h"
+
+void USBH_IRQHandler(uint8_t busid);
+
+static void usb_hc_xhci_interrupt_handler(int irqno, void *param)
+{
+    if (irqno == FUSB3_0_IRQ_NUM) {
+        USBH_IRQHandler(FUSB3_ID_0);
+    } else if (irqno == FUSB3_1_IRQ_NUM) {
+        USBH_IRQHandler(FUSB3_ID_1);
+    }
+}
+
+void usb_hc_setup_xhci_interrupt(uint32_t id)
+{
+    uint32_t irq_num = (id == FUSB3_ID_0) ? FUSB3_0_IRQ_NUM : FUSB3_1_IRQ_NUM;
+    rt_hw_interrupt_set_priority(irq_num, 0xd0);
+    rt_hw_interrupt_install(irq_num, usb_hc_xhci_interrupt_handler, 
+                            NULL, "xhci");
+    rt_hw_interrupt_umask(irq_num);
+}
+
+void usb_hc_revoke_xhci_interrupt(uint32_t id)
+{
+    uint32_t irq_num = (id == FUSB3_ID_0) ? FUSB3_0_IRQ_NUM : FUSB3_1_IRQ_NUM;
+
+    rt_hw_interrupt_mask(irq_num);
+}
+
+unsigned long usb_hc_get_register_base(uint32_t id)
+{
+    if (FUSB3_ID_0 == id)
+        return FUSB3_0_BASE_ADDR + FUSB3_XHCI_OFFSET;
+    else
+        return FUSB3_1_BASE_ADDR + FUSB3_XHCI_OFFSET;
+}