rtt更新

rt-thread/components/drivers/pin/Kconfig

@@ -1,3 +1,7 @@
 menuconfig RT_USING_PIN
     bool "Using Generic GPIO device drivers"
     default y
+
+if RT_USING_PIN
+    osource "$(SOC_DM_PIN_DIR)/Kconfig"
+endif

rt-thread/components/drivers/pin/SConscript

@@ -8,13 +8,13 @@ if not GetDepend(['RT_USING_PIN']):
 cwd = GetCurrentDir()
 CPPPATH = [cwd + '/../include']
 
-src = ['pin.c']
+src = ['dev_pin.c']
 
 if GetDepend(['RT_USING_DM']):
-    src += ['pin_dm.c']
+    src += ['dev_pin_dm.c']
 
 if GetDepend(['RT_USING_OFW']):
-    src += ['pin_ofw.c']
+    src += ['dev_pin_ofw.c']
 
 group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)
 

rt-thread/components/drivers/pin/dev_pin.c

@@ -0,0 +1,383 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-01-20     Bernard      the first version
+ * 2021-02-06     Meco Man     fix RT_ENOSYS code in negative
+ * 2022-04-29     WangQiang    add pin operate command in MSH
+ */
+
+#include <drivers/dev_pin.h>
+
+static struct rt_device_pin _hw_pin;
+static rt_ssize_t _pin_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    struct rt_device_pin_value *value;
+    struct rt_device_pin *pin = (struct rt_device_pin *)dev;
+
+    /* check parameters */
+    RT_ASSERT(pin != RT_NULL);
+
+    value = (struct rt_device_pin_value *)buffer;
+    if (value == RT_NULL || size != sizeof(*value))
+        return 0;
+
+    value->value = pin->ops->pin_read(dev, value->pin);
+    return size;
+}
+
+static rt_ssize_t _pin_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    struct rt_device_pin_value *value;
+    struct rt_device_pin *pin = (struct rt_device_pin *)dev;
+
+    /* check parameters */
+    RT_ASSERT(pin != RT_NULL);
+
+    value = (struct rt_device_pin_value *)buffer;
+    if (value == RT_NULL || size != sizeof(*value))
+        return 0;
+
+    pin->ops->pin_write(dev, (rt_base_t)value->pin, (rt_base_t)value->value);
+
+    return size;
+}
+
+static rt_err_t _pin_control(rt_device_t dev, int cmd, void *args)
+{
+    struct rt_device_pin_mode *mode;
+    struct rt_device_pin *pin = (struct rt_device_pin *)dev;
+
+    /* check parameters */
+    RT_ASSERT(pin != RT_NULL);
+
+    mode = (struct rt_device_pin_mode *)args;
+    if (mode == RT_NULL)
+        return -RT_ERROR;
+
+    pin->ops->pin_mode(dev, (rt_base_t)mode->pin, (rt_base_t)mode->mode);
+
+    return 0;
+}
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops pin_ops =
+{
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    _pin_read,
+    _pin_write,
+    _pin_control
+};
+#endif
+
+int rt_device_pin_register(const char *name, const struct rt_pin_ops *ops, void *user_data)
+{
+    _hw_pin.parent.type         = RT_Device_Class_Pin;
+    _hw_pin.parent.rx_indicate  = RT_NULL;
+    _hw_pin.parent.tx_complete  = RT_NULL;
+
+#ifdef RT_USING_DEVICE_OPS
+    _hw_pin.parent.ops          = &pin_ops;
+#else
+    _hw_pin.parent.init         = RT_NULL;
+    _hw_pin.parent.open         = RT_NULL;
+    _hw_pin.parent.close        = RT_NULL;
+    _hw_pin.parent.read         = _pin_read;
+    _hw_pin.parent.write        = _pin_write;
+    _hw_pin.parent.control      = _pin_control;
+#endif
+
+    _hw_pin.ops                 = ops;
+    _hw_pin.parent.user_data    = user_data;
+
+    /* register a character device */
+    rt_device_register(&_hw_pin.parent, name, RT_DEVICE_FLAG_RDWR);
+
+    return 0;
+}
+
+rt_err_t rt_pin_attach_irq(rt_base_t pin, rt_uint8_t mode,
+                           void (*hdr)(void *args), void *args)
+{
+    RT_ASSERT(_hw_pin.ops != RT_NULL);
+    if (_hw_pin.ops->pin_attach_irq)
+    {
+        return _hw_pin.ops->pin_attach_irq(&_hw_pin.parent, pin, mode, hdr, args);
+    }
+    return -RT_ENOSYS;
+}
+
+rt_err_t rt_pin_detach_irq(rt_base_t pin)
+{
+    RT_ASSERT(_hw_pin.ops != RT_NULL);
+    if (_hw_pin.ops->pin_detach_irq)
+    {
+        return _hw_pin.ops->pin_detach_irq(&_hw_pin.parent, pin);
+    }
+    return -RT_ENOSYS;
+}
+
+rt_err_t rt_pin_irq_enable(rt_base_t pin, rt_uint8_t enabled)
+{
+    RT_ASSERT(_hw_pin.ops != RT_NULL);
+    if (_hw_pin.ops->pin_irq_enable)
+    {
+        return _hw_pin.ops->pin_irq_enable(&_hw_pin.parent, pin, enabled);
+    }
+    return -RT_ENOSYS;
+}
+
+rt_err_t rt_pin_debounce(rt_base_t pin, rt_uint32_t debounce)
+{
+    RT_ASSERT(_hw_pin.ops != RT_NULL);
+    if (_hw_pin.ops->pin_debounce)
+    {
+        return _hw_pin.ops->pin_debounce(&_hw_pin.parent, pin, debounce);
+    }
+    return -RT_ENOSYS;
+}
+
+/* RT-Thread Hardware PIN APIs */
+void rt_pin_mode(rt_base_t pin, rt_uint8_t mode)
+{
+    RT_ASSERT(_hw_pin.ops != RT_NULL);
+    _hw_pin.ops->pin_mode(&_hw_pin.parent, pin, mode);
+}
+
+void rt_pin_write(rt_base_t pin, rt_ssize_t value)
+{
+    RT_ASSERT(_hw_pin.ops != RT_NULL);
+    _hw_pin.ops->pin_write(&_hw_pin.parent, pin, value);
+}
+
+rt_ssize_t rt_pin_read(rt_base_t pin)
+{
+    RT_ASSERT(_hw_pin.ops != RT_NULL);
+    return _hw_pin.ops->pin_read(&_hw_pin.parent, pin);
+}
+
+/* Get pin number by name, such as PA.0, P0.12 */
+rt_base_t rt_pin_get(const char *name)
+{
+    RT_ASSERT(_hw_pin.ops != RT_NULL);
+
+    if (_hw_pin.ops->pin_get == RT_NULL)
+    {
+        return -RT_ENOSYS;
+    }
+    return _hw_pin.ops->pin_get(name);
+}
+
+#ifdef RT_USING_FINSH
+#include <string.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include <finsh.h>
+#include <msh_parse.h>
+
+/*
+ * convert function for port name
+ */
+static rt_base_t _pin_cmd_conv(const char *name)
+{
+    return rt_pin_get(name);
+}
+
+static void _pin_cmd_print_usage(void)
+{
+    rt_kprintf("pin [option] GPIO\n");
+    rt_kprintf("     num:      get pin number from hardware pin\n");
+    rt_kprintf("     mode:     set pin mode to output/input/input_pullup/input_pulldown/output_od\n");
+    rt_kprintf("               e.g. MSH >pin mode GPIO output\n");
+    rt_kprintf("     read:     read pin level of hardware pin\n");
+    rt_kprintf("               e.g. MSH >pin read GPIO\n");
+    rt_kprintf("     write:    write pin level(high/low or on/off) to hardware pin\n");
+    rt_kprintf("               e.g. MSH >pin write GPIO high\n");
+    rt_kprintf("     help:     this help list\n");
+    rt_kprintf("GPIO e.g.:");
+    rt_pin_get(" ");
+}
+
+/* e.g. MSH >pin num PA.16 */
+static void _pin_cmd_get(int argc, char *argv[])
+{
+    rt_base_t pin;
+    if (argc < 3)
+    {
+        _pin_cmd_print_usage();
+        return;
+    }
+    pin = _pin_cmd_conv(argv[2]);
+    if (pin < 0)
+    {
+        rt_kprintf("Parameter invalid : %s!\n", argv[2]);
+        _pin_cmd_print_usage();
+        return ;
+    }
+    rt_kprintf("%s : %d\n", argv[2], pin);
+}
+
+/* e.g. MSH >pin mode PA.16 output */
+static void _pin_cmd_mode(int argc, char *argv[])
+{
+    rt_base_t pin;
+    rt_base_t mode;
+    if (argc < 4)
+    {
+        _pin_cmd_print_usage();
+        return;
+    }
+    if (!msh_isint(argv[2]))
+    {
+        pin = _pin_cmd_conv(argv[2]);
+        if (pin < 0)
+        {
+            rt_kprintf("Parameter invalid : %s!\n", argv[2]);
+            _pin_cmd_print_usage();
+            return;
+        }
+    }
+    else
+    {
+        pin = atoi(argv[2]);
+    }
+    if (0 == rt_strcmp("output", argv[3]))
+    {
+        mode = PIN_MODE_OUTPUT;
+    }
+    else if (0 == rt_strcmp("input", argv[3]))
+    {
+        mode = PIN_MODE_INPUT;
+    }
+    else if (0 == rt_strcmp("input_pullup", argv[3]))
+    {
+        mode = PIN_MODE_INPUT_PULLUP;
+    }
+    else if (0 == rt_strcmp("input_pulldown", argv[3]))
+    {
+        mode = PIN_MODE_INPUT_PULLDOWN;
+    }
+    else if (0 == rt_strcmp("output_od", argv[3]))
+    {
+        mode = PIN_MODE_OUTPUT_OD;
+    }
+    else
+    {
+        _pin_cmd_print_usage();
+        return;
+    }
+
+    rt_pin_mode(pin, mode);
+}
+
+/* e.g. MSH >pin read PA.16 */
+static void _pin_cmd_read(int argc, char *argv[])
+{
+    rt_base_t pin;
+    rt_uint8_t value;
+    if (argc < 3)
+    {
+        _pin_cmd_print_usage();
+        return;
+    }
+    if (!msh_isint(argv[2]))
+    {
+        pin = _pin_cmd_conv(argv[2]);
+        if (pin < 0)
+        {
+            rt_kprintf("Parameter invalid : %s!\n", argv[2]);
+            _pin_cmd_print_usage();
+            return;
+        }
+    }
+    else
+    {
+        pin = atoi(argv[2]);
+    }
+    value = rt_pin_read(pin);
+    if (value == PIN_HIGH)
+    {
+        rt_kprintf("pin[%d] = high\n", pin);
+    }
+    else
+    {
+        rt_kprintf("pin[%d] = low\n", pin);
+    }
+}
+
+/* e.g. MSH >pin write PA.16 high */
+static void _pin_cmd_write(int argc, char *argv[])
+{
+    rt_base_t pin;
+    rt_uint8_t value;
+    if (argc < 4)
+    {
+        _pin_cmd_print_usage();
+        return;
+    }
+    if (!msh_isint(argv[2]))
+    {
+        pin = _pin_cmd_conv(argv[2]);
+        if (pin < 0)
+        {
+            rt_kprintf("Parameter invalid : %s!\n", argv[2]);
+            _pin_cmd_print_usage();
+            return;
+        }
+    }
+    else
+    {
+        pin = atoi(argv[2]);
+    }
+    if ((0 == rt_strcmp("high", argv[3])) || (0 == rt_strcmp("on", argv[3])))
+    {
+        value = PIN_HIGH;
+    }
+    else if ((0 == rt_strcmp("low", argv[3])) || (0 == rt_strcmp("off", argv[3])))
+    {
+        value = PIN_LOW;
+    }
+    else
+    {
+        _pin_cmd_print_usage();
+        return;
+    }
+    rt_pin_write(pin, value);
+}
+
+static void _pin_cmd(int argc, char *argv[])
+{
+    if (argc < 3)
+    {
+        _pin_cmd_print_usage();
+        return ;
+    }
+    if (0 == rt_strcmp("num", argv[1]))
+    {
+        _pin_cmd_get(argc, argv);
+    }
+    else if (0 == rt_strcmp("mode", argv[1]))
+    {
+        _pin_cmd_mode(argc, argv);
+    }
+    else if (0 == rt_strcmp("read", argv[1]))
+    {
+        _pin_cmd_read(argc, argv);
+    }
+    else if (0 == rt_strcmp("write", argv[1]))
+    {
+        _pin_cmd_write(argc, argv);
+    }
+    else
+    {
+        _pin_cmd_print_usage();
+        return;
+    }
+}
+MSH_CMD_EXPORT_ALIAS(_pin_cmd, pin, pin [option]);
+#endif /* RT_USING_FINSH */

rt-thread/components/drivers/pin/dev_pin_dm.c

@@ -0,0 +1,458 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-11-26     GuEe-GUI     first version
+ */
+
+#include "dev_pin_dm.h"
+
+static rt_size_t pin_total_nr = 0;
+static struct rt_spinlock pin_lock = {};
+static rt_list_t pin_nodes = RT_LIST_OBJECT_INIT(pin_nodes);
+
+static struct rt_device_pin *pin_device_find(rt_ubase_t pin)
+{
+    struct rt_device_pin *gpio = RT_NULL, *gpio_tmp;
+
+    rt_spin_lock(&pin_lock);
+
+    rt_list_for_each_entry(gpio_tmp, &pin_nodes, list)
+    {
+        if (pin >= gpio_tmp->pin_start &&
+            pin - gpio_tmp->pin_start < gpio_tmp->pin_nr)
+        {
+            gpio = gpio_tmp;
+            break;
+        }
+    }
+
+    rt_spin_unlock(&pin_lock);
+
+    return gpio;
+}
+
+static void pin_api_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
+{
+    struct rt_device_pin *gpio = pin_device_find(pin);
+
+    if (gpio && gpio->ops->pin_mode)
+    {
+        gpio->ops->pin_mode(&gpio->parent, pin - gpio->pin_start, mode);
+    }
+}
+
+static void pin_api_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
+{
+    struct rt_device_pin *gpio = pin_device_find(pin);
+
+    if (gpio && gpio->ops->pin_write)
+    {
+        gpio->ops->pin_write(&gpio->parent, pin - gpio->pin_start, value);
+    }
+}
+
+static rt_ssize_t pin_api_read(struct rt_device *device, rt_base_t pin)
+{
+    struct rt_device_pin *gpio = pin_device_find(pin);
+
+    if (gpio && gpio->ops->pin_read)
+    {
+        return gpio->ops->pin_read(&gpio->parent, pin - gpio->pin_start);
+    }
+
+    return -RT_EINVAL;
+}
+
+static rt_err_t pin_api_attach_irq(struct rt_device *device, rt_base_t pin,
+        rt_uint8_t mode, void (*hdr)(void *args), void *args)
+{
+    struct rt_device_pin *gpio = pin_device_find(pin);
+
+    if (gpio)
+    {
+        rt_base_t pin_index = pin - gpio->pin_start;
+
+        if (!gpio->ops->pin_attach_irq)
+        {
+            rt_err_t err;
+            struct rt_pin_irq_hdr *legacy_isr;
+
+            if ((err = gpio->ops->pin_irq_mode(&gpio->parent, pin_index, mode)))
+            {
+                return err;
+            }
+
+            legacy_isr = &gpio->legacy_isr[pin_index];
+            legacy_isr->pin = pin_index;
+            legacy_isr->mode = mode;
+            legacy_isr->hdr = hdr;
+            legacy_isr->args = args;
+
+            return RT_EOK;
+        }
+        else
+        {
+            return gpio->ops->pin_attach_irq(&gpio->parent, pin_index, mode, hdr, args);
+        }
+    }
+
+    return -RT_EINVAL;
+}
+
+static rt_err_t pin_api_detach_irq(struct rt_device *device, rt_base_t pin)
+{
+    struct rt_device_pin *gpio = pin_device_find(pin);
+
+    if (gpio)
+    {
+        rt_base_t pin_index = pin - gpio->pin_start;
+
+        if (!gpio->ops->pin_detach_irq)
+        {
+            struct rt_pin_irq_hdr *legacy_isr;
+
+            legacy_isr = &gpio->legacy_isr[pin_index];
+            rt_memset(legacy_isr, 0, sizeof(*legacy_isr));
+
+            return RT_EOK;
+        }
+        else
+        {
+            return gpio->ops->pin_detach_irq(&gpio->parent, pin);
+        }
+    }
+
+    return -RT_EINVAL;
+}
+
+static rt_err_t pin_api_irq_enable(struct rt_device *device, rt_base_t pin,
+        rt_uint8_t enabled)
+{
+    struct rt_device_pin *gpio = pin_device_find(pin);
+
+    if (gpio && gpio->ops->pin_irq_enable)
+    {
+        return gpio->ops->pin_irq_enable(&gpio->parent, pin - gpio->pin_start, enabled);
+    }
+
+    return -RT_EINVAL;
+}
+
+static rt_base_t pin_api_get(const char *name)
+{
+    rt_base_t res = -RT_EINVAL;
+    struct rt_device_pin *gpio;
+
+    rt_spin_lock(&pin_lock);
+
+    rt_list_for_each_entry(gpio, &pin_nodes, list)
+    {
+        if (gpio->ops->pin_get && !(res = gpio->ops->pin_get(name)))
+        {
+            break;
+        }
+    }
+
+    rt_spin_unlock(&pin_lock);
+
+    return res;
+}
+
+static rt_err_t pin_api_debounce(struct rt_device *device, rt_base_t pin,
+        rt_uint32_t debounce)
+{
+    struct rt_device_pin *gpio = pin_device_find(pin);
+
+    if (gpio && gpio->ops->pin_debounce)
+    {
+        return gpio->ops->pin_debounce(&gpio->parent, pin - gpio->pin_start, debounce);
+    }
+
+    return -RT_EINVAL;
+}
+
+static rt_err_t pin_api_irq_mode(struct rt_device *device, rt_base_t pin,
+        rt_uint8_t mode)
+{
+    struct rt_device_pin *gpio = pin_device_find(pin);
+
+    if (gpio && gpio->ops->pin_irq_mode)
+    {
+        return gpio->ops->pin_irq_mode(&gpio->parent, pin - gpio->pin_start, mode);
+    }
+
+    return -RT_EINVAL;
+}
+
+static const struct rt_pin_ops pin_api_dm_ops =
+{
+    .pin_mode = pin_api_mode,
+    .pin_write = pin_api_write,
+    .pin_read = pin_api_read,
+    .pin_attach_irq = pin_api_attach_irq,
+    .pin_detach_irq = pin_api_detach_irq,
+    .pin_irq_enable = pin_api_irq_enable,
+    .pin_get = pin_api_get,
+    .pin_debounce = pin_api_debounce,
+    .pin_irq_mode = pin_api_irq_mode,
+};
+
+rt_err_t pin_api_init(struct rt_device_pin *gpio, rt_size_t pin_nr)
+{
+    rt_err_t err = RT_EOK;
+
+    if (!gpio || !gpio->ops)
+    {
+        return -RT_EINVAL;
+    }
+
+    rt_spin_lock(&pin_lock);
+
+    if (rt_list_isempty(&pin_nodes))
+    {
+        rt_spin_unlock(&pin_lock);
+        rt_device_pin_register("gpio", &pin_api_dm_ops, RT_NULL);
+        rt_spin_lock(&pin_lock);
+    }
+
+    gpio->pin_start = pin_total_nr;
+    gpio->pin_nr = pin_nr;
+    pin_total_nr += pin_nr;
+
+    rt_list_init(&gpio->list);
+    rt_list_insert_before(&pin_nodes, &gpio->list);
+
+    rt_spin_unlock(&pin_lock);
+
+    return err;
+}
+
+static void pin_dm_irq_mask(struct rt_pic_irq *pirq)
+{
+    struct rt_device_pin *gpio = pirq->pic->priv_data;
+
+    gpio->ops->pin_irq_enable(&gpio->parent, pirq->hwirq, 0);
+}
+
+static void pin_dm_irq_unmask(struct rt_pic_irq *pirq)
+{
+    struct rt_device_pin *gpio = pirq->pic->priv_data;
+
+    gpio->ops->pin_irq_enable(&gpio->parent, pirq->hwirq, 1);
+}
+
+static rt_err_t pin_dm_irq_set_triger_mode(struct rt_pic_irq *pirq, rt_uint32_t mode)
+{
+    rt_uint8_t pin_mode;
+    struct rt_device_pin *gpio = pirq->pic->priv_data;
+
+    switch (mode)
+    {
+    case RT_IRQ_MODE_EDGE_RISING:
+        pin_mode = PIN_IRQ_MODE_RISING;
+        break;
+
+    case RT_IRQ_MODE_EDGE_FALLING:
+        pin_mode = PIN_IRQ_MODE_FALLING;
+        break;
+
+    case RT_IRQ_MODE_EDGE_BOTH:
+        pin_mode = PIN_IRQ_MODE_RISING_FALLING;
+        break;
+
+    case RT_IRQ_MODE_LEVEL_HIGH:
+        pin_mode = PIN_IRQ_MODE_HIGH_LEVEL;
+        break;
+
+    case RT_IRQ_MODE_LEVEL_LOW:
+        pin_mode = PIN_IRQ_MODE_LOW_LEVEL;
+        break;
+
+    default:
+        return -RT_ENOSYS;
+    }
+
+    return gpio->ops->pin_irq_mode(&gpio->parent, pirq->hwirq, pin_mode);
+}
+
+static int pin_dm_irq_map(struct rt_pic *pic, int hwirq, rt_uint32_t mode)
+{
+    int irq = -1;
+    struct rt_device_pin *gpio = pic->priv_data;
+    struct rt_pic_irq *pirq = rt_pic_find_irq(pic, hwirq);
+
+    if (pirq)
+    {
+        irq = rt_pic_config_irq(pic, hwirq, hwirq);
+
+        if (irq >= 0)
+        {
+            rt_pic_cascade(pirq, gpio->irqchip.irq);
+            rt_pic_irq_set_triger_mode(irq, mode);
+        }
+    }
+
+    return irq;
+}
+
+static rt_err_t pin_dm_irq_parse(struct rt_pic *pic,
+        struct rt_ofw_cell_args *args, struct rt_pic_irq *out_pirq)
+{
+    rt_err_t err = RT_EOK;
+
+    if (args->args_count == 2)
+    {
+        out_pirq->hwirq = args->args[0];
+        out_pirq->mode = args->args[1] & RT_IRQ_MODE_MASK;
+    }
+    else
+    {
+        err = -RT_EINVAL;
+    }
+
+    return err;
+}
+
+const static struct rt_pic_ops pin_dm_ops =
+{
+    .name = "GPIO",
+    .irq_enable = pin_dm_irq_mask,
+    .irq_disable = pin_dm_irq_unmask,
+    .irq_mask = pin_dm_irq_mask,
+    .irq_unmask = pin_dm_irq_unmask,
+    .irq_set_triger_mode = pin_dm_irq_set_triger_mode,
+    .irq_map = pin_dm_irq_map,
+    .irq_parse = pin_dm_irq_parse,
+};
+
+rt_err_t pin_pic_handle_isr(struct rt_device_pin *gpio, rt_base_t pin)
+{
+    rt_err_t err;
+
+    if (gpio)
+    {
+        rt_ubase_t pin_index = pin;
+        struct rt_pin_irqchip *irqchip = &gpio->irqchip;
+
+        if (pin_index < gpio->pin_nr)
+        {
+            struct rt_pic_irq *pirq;
+            struct rt_pin_irq_hdr *legacy_isr;
+
+            pirq = rt_pic_find_irq(&irqchip->parent, pin_index);
+
+            if (pirq->irq >= 0)
+            {
+                err = rt_pic_handle_isr(pirq);
+            }
+            else
+            {
+                err = -RT_EINVAL;
+            }
+
+            legacy_isr = &gpio->legacy_isr[pin_index];
+
+            if (legacy_isr->hdr)
+            {
+                legacy_isr->hdr(legacy_isr->args);
+            }
+        }
+        else
+        {
+            err = -RT_EINVAL;
+        }
+    }
+    else
+    {
+        err = -RT_EINVAL;
+    }
+
+    return err;
+}
+
+rt_err_t pin_pic_init(struct rt_device_pin *gpio, int pin_irq)
+{
+    rt_err_t err;
+
+    if (gpio)
+    {
+        struct rt_pin_irqchip *irqchip = &gpio->irqchip;
+        struct rt_pic *pic = &irqchip->parent;
+
+        irqchip->irq = pin_irq;
+
+        if (!gpio->pin_nr)
+        {
+            return -RT_EINVAL;
+        }
+
+        gpio->legacy_isr = rt_calloc(gpio->pin_nr, sizeof(*gpio->legacy_isr));
+
+        if (!gpio->legacy_isr)
+        {
+            return -RT_ENOMEM;
+        }
+
+        pic->priv_data = gpio;
+        pic->ops = &pin_dm_ops;
+        /* Make sure the type of gpio for pic */
+        gpio->parent.parent.type = RT_Object_Class_Device;
+        rt_pic_default_name(&irqchip->parent);
+
+        err = rt_pic_linear_irq(pic, gpio->pin_nr);
+        rt_pic_user_extends(pic);
+
+        err = RT_EOK;
+    }
+    else
+    {
+        err = -RT_EINVAL;
+    }
+
+    return err;
+}
+
+rt_ssize_t rt_pin_get_named_pin(struct rt_device *dev, const char *propname, int index,
+        rt_uint8_t *out_mode, rt_uint8_t *out_value)
+{
+    rt_ssize_t res = -RT_ENOSYS;
+
+    RT_ASSERT(dev != RT_NULL);
+
+#ifdef RT_USING_OFW
+    if (dev->ofw_node)
+    {
+        res = rt_ofw_get_named_pin(dev->ofw_node, propname, index, out_mode, out_value);
+    }
+    else
+    {
+        res = -RT_EINVAL;
+    }
+#endif /* RT_USING_OFW */
+
+    return res;
+}
+
+rt_ssize_t rt_pin_get_named_pin_count(struct rt_device *dev, const char *propname)
+{
+    rt_ssize_t count = -RT_ENOSYS;
+
+    RT_ASSERT(dev != RT_NULL);
+
+#ifdef RT_USING_OFW
+    if (dev->ofw_node)
+    {
+        count = rt_ofw_get_named_pin_count(dev->ofw_node, propname);
+    }
+    else
+    {
+        count = -RT_EINVAL;
+    }
+#endif /* RT_USING_OFW */
+
+    return count;
+}

rt-thread/components/drivers/pin/dev_pin_dm.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-11-26     GuEe-GUI     first version
+ */
+
+#ifndef __PIN_DM_H__
+#define __PIN_DM_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+rt_err_t pin_api_init(struct rt_device_pin *gpio, rt_size_t pin_nr);
+
+rt_err_t pin_pic_init(struct rt_device_pin *gpio, int pin_irq);
+rt_err_t pin_pic_handle_isr(struct rt_device_pin *gpio, rt_base_t pin);
+
+#endif /* __DEV_PIN_DM_H__ */

rt-thread/components/drivers/pin/dev_pin_ofw.c

@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-11-26     GuEe-GUI     first version
+ */
+
+#include <dt-bindings/pin/pin.h>
+
+#include "dev_pin_dm.h"
+
+static const char * const gpio_suffixes[] =
+{
+    "gpios", "gpio"
+};
+
+rt_ssize_t rt_ofw_get_named_pin(struct rt_ofw_node *np, const char *propname, int index,
+        rt_uint8_t *out_mode, rt_uint8_t *out_value)
+{
+    rt_ssize_t pin = -1;
+    rt_uint8_t mode;
+    rt_uint8_t value;
+    rt_uint32_t flags;
+    char gpios_name[64];
+    struct rt_device_pin *pin_dev = 0;
+    struct rt_ofw_node *pin_dev_np = 0;
+    struct rt_ofw_cell_args pin_args = {0};
+
+    if (!np && index < 0)
+    {
+        return -RT_EINVAL;
+    }
+
+    for (int i = 0; i < RT_ARRAY_SIZE(gpio_suffixes); ++i)
+    {
+        if (propname)
+        {
+            rt_snprintf(gpios_name, sizeof(gpios_name), "%s-%s", propname, gpio_suffixes[i]);
+        }
+        else
+        {
+            rt_snprintf(gpios_name, sizeof(gpios_name), "%s", gpio_suffixes[i]);
+        }
+
+        pin = rt_ofw_parse_phandle_cells(np, gpios_name, "#gpio-cells", index, &pin_args);
+
+        if (pin >= 0)
+        {
+            break;
+        }
+    }
+
+    if (pin < 0)
+    {
+        return pin;
+    }
+
+    pin_dev_np = pin_args.data;
+
+    if (!rt_ofw_data(pin_dev_np))
+    {
+        rt_platform_ofw_request(pin_dev_np);
+    }
+
+    pin_dev = rt_ofw_data(pin_dev_np);
+
+    if (!pin_dev)
+    {
+        pin = -RT_ERROR;
+
+        goto _out_converts;
+    }
+
+    value = PIN_LOW;
+    mode = PIN_MODE_OUTPUT;
+
+    if (pin_dev->ops->pin_parse)
+    {
+        pin = pin_dev->ops->pin_parse(&pin_dev->parent, &pin_args, &flags);
+    }
+    else
+    {
+        /*
+         * We always assume that the args[0] is the pin number if driver not
+         * implemented `pin_parse`.
+         */
+        pin = pin_args.args[0];
+
+        goto _out_converts;
+    }
+
+    if (out_mode)
+    {
+        if (flags & PIN_OPEN_DRAIN)
+        {
+            mode = PIN_MODE_OUTPUT_OD;
+        }
+
+        switch (flags & RT_GENMASK(6, 4))
+        {
+        case PIN_PULL_UP:
+            mode = PIN_MODE_INPUT_PULLUP;
+            break;
+
+        case PIN_PULL_DOWN:
+            mode = PIN_MODE_INPUT_PULLDOWN;
+            break;
+
+        case PIN_PULL_DISABLE:
+            mode = PIN_MODE_INPUT;
+            break;
+        }
+    }
+
+    if (out_value)
+    {
+        if ((flags & 1) == PIN_ACTIVE_HIGH)
+        {
+            value = PIN_HIGH;
+        }
+        else if ((flags & 1) == PIN_ACTIVE_LOW)
+        {
+            value = PIN_LOW;
+        }
+    }
+
+_out_converts:
+    rt_ofw_node_put(pin_dev_np);
+
+    if (pin >= 0)
+    {
+        /* Get virtual pin */
+        pin += pin_dev->pin_start;
+
+        if (out_mode)
+        {
+            *out_mode = mode;
+        }
+
+        if (out_value)
+        {
+            *out_value = value;
+        }
+    }
+
+    return pin;
+}
+
+rt_ssize_t rt_ofw_get_named_pin_count(struct rt_ofw_node *np, const char *propname)
+{
+    char gpios_name[64];
+    rt_ssize_t count = 0;
+
+    if (!np)
+    {
+        return -RT_EINVAL;
+    }
+
+    for (int i = 0; i < RT_ARRAY_SIZE(gpio_suffixes); ++i)
+    {
+        if (propname)
+        {
+            rt_snprintf(gpios_name, sizeof(gpios_name), "%s-%s", propname, gpio_suffixes[i]);
+        }
+        else
+        {
+            rt_snprintf(gpios_name, sizeof(gpios_name), "%s", gpio_suffixes[i]);
+        }
+
+        count = rt_ofw_count_phandle_cells(np, propname, "#gpio-cells");
+
+        if (count > 0)
+        {
+            break;
+        }
+    }
+
+    return count;
+}