From c431b61900d5fc2ef32c6266e01d0a408e1f2cce Mon Sep 17 00:00:00 2001 From: dgjames <1943357252@qq.com> Date: Fri, 14 Mar 2025 11:04:51 +0800 Subject: [PATCH] =?UTF-8?q?=E6=9B=B4=E6=96=B0rtt=E6=88=90=E5=8A=9F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .config | 152 +- .vscode/c_cpp_properties.json | 486 ++- .vscode/project.json | 519 +++ applications/init.c | 6 +- board/ports/fal/fal_spi_flash_sfud_port.c | 2 +- board/ports/spi_flash_init.c | 4 +- libraries/HAL_Drivers/drivers/drv_pwm.c | 2 +- libraries/HAL_Drivers/drivers/drv_sdio.h | 4 +- rt-thread/README.md | 3 +- rt-thread/components/dfs/Kconfig | 22 +- rt-thread/components/dfs/dfs_v1/SConscript | 10 +- .../dfs/dfs_v1/filesystems/iso9660/SConscript | 11 + .../dfs_v1/filesystems/iso9660/dfs_iso9660.c | 698 ++++ .../dfs_v1/filesystems/iso9660/dfs_iso9660.h | 16 + .../dfs/dfs_v1/filesystems/ramfs/dfs_ramfs.c | 6 +- rt-thread/components/dfs/dfs_v1/src/dfs.c | 122 +- .../components/dfs/dfs_v1/src/dfs_file.c | 58 +- rt-thread/components/dfs/dfs_v1/src/dfs_fs.c | 12 +- .../components/dfs/dfs_v1/src/dfs_posix.c | 60 +- .../dfs_v2/filesystems/cromfs/dfs_cromfs.c | 6 +- .../dfs_v2/filesystems/cromfs/dfs_cromfs.h | 3 + .../dfs/dfs_v2/filesystems/devfs/devfs.c | 55 +- .../dfs/dfs_v2/filesystems/devfs/devtmpfs.c | 50 +- .../dfs/dfs_v2/filesystems/procfs/README.md | 166 + .../dfs/dfs_v2/filesystems/procfs/SConscript | 11 + .../dfs/dfs_v2/filesystems/procfs/proc.c | 733 ++++ .../dfs/dfs_v2/filesystems/procfs/proc.h | 75 + .../dfs_v2/filesystems/procfs/proc_cmdline.c | 53 + .../dfs_v2/filesystems/procfs/proc_cpuinfo.c | 86 + .../dfs_v2/filesystems/procfs/proc_devices.c | 307 ++ .../filesystems/procfs/proc_filesystems.c | 85 + .../dfs_v2/filesystems/procfs/proc_loadavg.c | 41 + .../dfs_v2/filesystems/procfs/proc_meminfo.c | 66 + .../dfs_v2/filesystems/procfs/proc_mounts.c | 101 + .../dfs/dfs_v2/filesystems/procfs/proc_net.c | 107 + .../filesystems/procfs/proc_partitions.c | 215 ++ .../dfs/dfs_v2/filesystems/procfs/proc_pid.c | 449 +++ .../dfs/dfs_v2/filesystems/procfs/proc_self.c | 66 + .../dfs/dfs_v2/filesystems/procfs/proc_stat.c | 114 + .../dfs/dfs_v2/filesystems/procfs/proc_tty.c | 100 + .../dfs_v2/filesystems/procfs/proc_uptime.c | 38 + .../dfs_v2/filesystems/procfs/proc_version.c | 45 + .../dfs/dfs_v2/filesystems/procfs/procfs.c | 447 +++ .../dfs/dfs_v2/filesystems/procfs/procfs.h | 19 + .../dfs/dfs_v2/filesystems/ptyfs/ptyfs.c | 4 +- .../dfs/dfs_v2/filesystems/romfs/dfs_romfs.c | 1 + .../dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.c | 35 +- .../dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.h | 4 +- .../components/dfs/dfs_v2/include/dfs_fs.h | 33 + .../components/dfs/dfs_v2/include/dfs_mnt.h | 9 + .../dfs/dfs_v2/include/dfs_pcache.h | 1 + .../dfs/dfs_v2/include/dfs_seq_file.h | 2 +- .../components/dfs/dfs_v2/include/dfs_vfs.h | 50 + rt-thread/components/dfs/dfs_v2/src/dfs.c | 10 +- .../components/dfs/dfs_v2/src/dfs_file.c | 5 + rt-thread/components/dfs/dfs_v2/src/dfs_fs.c | 60 +- rt-thread/components/dfs/dfs_v2/src/dfs_mnt.c | 35 +- .../components/dfs/dfs_v2/src/dfs_pcache.c | 51 +- .../components/dfs/dfs_v2/src/dfs_posix.c | 70 +- .../components/dfs/dfs_v2/src/dfs_seq_file.c | 2 +- rt-thread/components/drivers/Kconfig | 13 + rt-thread/components/drivers/ata/Kconfig | 22 + rt-thread/components/drivers/ata/SConscript | 21 + rt-thread/components/drivers/ata/ahci-pci.c | 206 ++ rt-thread/components/drivers/ata/ahci.c | 896 +++++ .../drivers/audio/{audio.c => dev_audio.c} | 0 .../audio/{audio_pipe.c => dev_audio_pipe.c} | 32 +- .../audio/{audio_pipe.h => dev_audio_pipe.h} | 6 +- rt-thread/components/drivers/block/Kconfig | 7 + rt-thread/components/drivers/block/SConscript | 23 + rt-thread/components/drivers/block/blk.c | 573 +++ rt-thread/components/drivers/block/blk_dev.c | 297 ++ rt-thread/components/drivers/block/blk_dev.h | 49 + rt-thread/components/drivers/block/blk_dfs.c | 274 ++ rt-thread/components/drivers/block/blk_dfs.h | 23 + .../components/drivers/block/blk_partition.c | 154 + .../components/drivers/block/blk_partition.h | 22 + .../drivers/block/partitions/Kconfig | 12 + .../drivers/block/partitions/SConscript | 18 + .../components/drivers/block/partitions/dfs.c | 55 + .../components/drivers/block/partitions/efi.c | 738 ++++ .../components/drivers/block/partitions/efi.h | 141 + .../drivers/can/{can.c => dev_can.c} | 4 +- rt-thread/components/drivers/clk/Kconfig | 4 + rt-thread/components/drivers/clk/clk.c | 251 +- rt-thread/components/drivers/core/bus.c | 4 +- rt-thread/components/drivers/core/device.c | 20 +- rt-thread/components/drivers/core/dm.c | 131 + rt-thread/components/drivers/core/platform.c | 16 +- .../components/drivers/core/platform_ofw.c | 61 +- rt-thread/components/drivers/dma/Kconfig | 10 + rt-thread/components/drivers/dma/SConscript | 15 + rt-thread/components/drivers/dma/dma.c | 589 +++ rt-thread/components/drivers/dma/dma_pool.c | 691 ++++ .../components/drivers/hwtimer/hwtimer.c | 11 +- rt-thread/components/drivers/i2c/Kconfig | 414 ++- rt-thread/components/drivers/i2c/SConscript | 10 +- .../i2c/{i2c-bit-ops.c => dev_i2c_bit_ops.c} | 0 .../drivers/i2c/{i2c_bus.c => dev_i2c_bus.c} | 2 +- .../i2c/{i2c_core.c => dev_i2c_core.c} | 2 +- .../drivers/i2c/{i2c_dev.c => dev_i2c_dev.c} | 0 .../drivers/i2c/{i2c_dm.c => dev_i2c_dm.c} | 2 +- .../i2c/{soft_i2c.c => dev_soft_i2c.c} | 12 +- rt-thread/components/drivers/iio/SConscript | 15 + rt-thread/components/drivers/iio/iio.c | 71 + .../components/drivers/include/drivers/adc.h | 102 +- .../components/drivers/include/drivers/ahci.h | 397 +++ .../components/drivers/include/drivers/blk.h | 87 + .../components/drivers/include/drivers/clk.h | 6 + .../drivers/include/drivers/core/dm.h | 20 + .../drivers/include/drivers/core/master_id.h | 94 + .../drivers/include/drivers/cputime.h | 4 + .../components/drivers/include/drivers/dac.h | 96 +- .../include/drivers/{alarm.h => dev_alarm.h} | 6 +- .../include/drivers/{audio.h => dev_audio.h} | 8 +- .../include/drivers/{can.h => dev_can.h} | 203 +- .../drivers/include/drivers/dev_i2c.h | 401 +++ .../{i2c-bit-ops.h => dev_i2c_bit_ops.h} | 4 +- .../drivers/{i2c_dm.h => dev_i2c_dm.h} | 6 +- .../include/drivers/{mmc.h => dev_mmc.h} | 4 +- .../{mmcsd_core.h => dev_mmcsd_core.h} | 6 +- .../include/drivers/{pin.h => dev_pin.h} | 188 +- .../drivers/include/drivers/dev_pwm.h | 209 ++ .../include/drivers/{rtc.h => dev_rtc.h} | 122 +- .../include/drivers/{sd.h => dev_sd.h} | 4 +- .../include/drivers/{sdio.h => dev_sdio.h} | 4 +- .../drivers/{serial.h => dev_serial.h} | 139 +- .../drivers/{serial_v2.h => dev_serial_v2.h} | 172 +- .../drivers/include/drivers/dev_spi.h | 633 ++++ .../include/drivers/{touch.h => dev_touch.h} | 147 +- .../drivers/{watchdog.h => dev_watchdog.h} | 6 +- .../components/drivers/include/drivers/dma.h | 234 ++ .../components/drivers/include/drivers/gpt.h | 132 - .../components/drivers/include/drivers/i2c.h | 136 - .../drivers/include/drivers/i2c_dev.h | 44 - .../components/drivers/include/drivers/iio.h | 17 + .../components/drivers/include/drivers/led.h | 57 + .../drivers/include/drivers/mailbox.h | 77 + .../components/drivers/include/drivers/misc.h | 60 + .../drivers/include/drivers/mmcsd_card.h | 2 +- .../drivers/include/drivers/mmcsd_host.h | 1 + .../components/drivers/include/drivers/nvme.h | 899 +++++ .../components/drivers/include/drivers/ofw.h | 7 +- .../drivers/include/drivers/ofw_fdt.h | 1 + .../drivers/include/drivers/ofw_io.h | 21 + .../components/drivers/include/drivers/pci.h | 604 ++++ .../drivers/include/drivers/pci_endpoint.h | 203 ++ .../drivers/include/drivers/pci_msi.h | 189 + .../components/drivers/include/drivers/phy.h | 168 +- .../drivers/include/drivers/phy_mdio.h | 43 - .../components/drivers/include/drivers/phye.h | 91 + .../components/drivers/include/drivers/pic.h | 1 + .../drivers/include/drivers/platform.h | 10 +- .../components/drivers/include/drivers/pm.h | 40 +- .../drivers/include/drivers/regulator.h | 153 + .../drivers/include/drivers/reset.h | 82 + .../drivers/include/drivers/rt_drv_pwm.h | 66 - .../components/drivers/include/drivers/scsi.h | 461 +++ .../drivers/include/drivers/sensor.h | 15 +- .../drivers/include/drivers/sensor_v2.h | 2 +- .../drivers/include/drivers/serial_bypass.h | 69 + .../components/drivers/include/drivers/spi.h | 373 -- .../drivers/include/drivers/syscon.h | 35 + .../drivers/include/drivers/thermal.h | 205 ++ .../components/drivers/include/drivers/wlan.h | 10 +- .../drivers/include/dt-bindings/phye/phye.h | 24 + .../include/dt-bindings/thermal/thermal.h | 13 + .../drivers/include/ipc/completion.h | 18 +- .../drivers/include/ipc/workqueue.h | 4 +- .../components/drivers/include/rtdevice.h | 105 +- .../components/drivers/ipc/completion_comm.c | 22 + .../components/drivers/ipc/completion_mp.c | 36 +- .../components/drivers/ipc/completion_up.c | 22 + rt-thread/components/drivers/ipc/workqueue.c | 176 +- rt-thread/components/drivers/led/Kconfig | 15 + rt-thread/components/drivers/led/SConscript | 18 + rt-thread/components/drivers/led/led-gpio.c | 228 ++ rt-thread/components/drivers/led/led.c | 349 ++ rt-thread/components/drivers/mailbox/Kconfig | 14 + .../components/drivers/mailbox/SConscript | 18 + .../components/drivers/mailbox/mailbox-pic.c | 292 ++ .../components/drivers/mailbox/mailbox.c | 352 ++ rt-thread/components/drivers/mfd/Kconfig | 10 + rt-thread/components/drivers/mfd/SConscript | 17 + rt-thread/components/drivers/mfd/mfd-syscon.c | 244 ++ rt-thread/components/drivers/misc/rt_random.c | 4 +- rt-thread/components/drivers/nvme/Kconfig | 23 + rt-thread/components/drivers/nvme/SConscript | 18 + rt-thread/components/drivers/nvme/nvme-pci.c | 171 + rt-thread/components/drivers/nvme/nvme.c | 1302 +++++++ rt-thread/components/drivers/ofw/base.c | 4 +- rt-thread/components/drivers/ofw/fdt.c | 75 +- rt-thread/components/drivers/ofw/io.c | 69 + rt-thread/components/drivers/ofw/ofw.c | 34 +- rt-thread/components/drivers/pci/Kconfig | 49 + rt-thread/components/drivers/pci/SConscript | 28 + rt-thread/components/drivers/pci/access.c | 159 + rt-thread/components/drivers/pci/ecam.c | 72 + rt-thread/components/drivers/pci/ecam.h | 69 + .../drivers/pci/endpoint/SConscript | 15 + .../drivers/pci/endpoint/endpoint.c | 504 +++ .../components/drivers/pci/endpoint/mem.c | 205 ++ .../components/drivers/pci/host-bridge.c | 129 + rt-thread/components/drivers/pci/host/Kconfig | 12 + .../components/drivers/pci/host/SConscript | 25 + .../components/drivers/pci/host/dw/Kconfig | 13 + .../components/drivers/pci/host/dw/SConscript | 21 + .../components/drivers/pci/host/dw/pcie-dw.c | 645 ++++ .../components/drivers/pci/host/dw/pcie-dw.h | 440 +++ .../drivers/pci/host/dw/pcie-dw_ep.c | 863 +++++ .../drivers/pci/host/dw/pcie-dw_host.c | 644 ++++ .../drivers/pci/host/dw/pcie-dw_platfrom.c | 295 ++ .../drivers/pci/host/pci-host-common.c | 85 + .../drivers/pci/host/pci-host-generic.c | 66 + rt-thread/components/drivers/pci/irq.c | 60 + .../components/drivers/pci/msi/SConscript | 15 + rt-thread/components/drivers/pci/msi/device.c | 46 + rt-thread/components/drivers/pci/msi/irq.c | 146 + rt-thread/components/drivers/pci/msi/msi.c | 949 +++++ rt-thread/components/drivers/pci/ofw.c | 609 ++++ rt-thread/components/drivers/pci/pci.c | 1018 ++++++ rt-thread/components/drivers/pci/pci_ids.h | 272 ++ rt-thread/components/drivers/pci/pci_regs.h | 1090 ++++++ rt-thread/components/drivers/pci/pme.c | 121 + rt-thread/components/drivers/pci/probe.c | 926 +++++ rt-thread/components/drivers/phy/Kconfig | 5 + rt-thread/components/drivers/phy/SConscript | 14 +- rt-thread/components/drivers/phy/general.c | 349 ++ .../components/drivers/phy/general_phy.h | 143 + rt-thread/components/drivers/phy/mdio.c | 75 + rt-thread/components/drivers/phy/mdio.h | 98 + rt-thread/components/drivers/phy/ofw.c | 156 + rt-thread/components/drivers/phy/ofw.h | 58 + rt-thread/components/drivers/phy/phy.c | 513 ++- rt-thread/components/drivers/phye/Kconfig | 11 + rt-thread/components/drivers/phye/SConscript | 15 + rt-thread/components/drivers/phye/phye.c | 320 ++ rt-thread/components/drivers/pic/Kconfig | 23 +- rt-thread/components/drivers/pic/SConscript | 6 + .../components/drivers/pic/pic-gic-common.c | 5 +- .../components/drivers/pic/pic-gic-common.h | 10 +- rt-thread/components/drivers/pic/pic-gicv2.c | 9 + rt-thread/components/drivers/pic/pic-gicv2.h | 2 + rt-thread/components/drivers/pic/pic-gicv2m.c | 378 ++ .../components/drivers/pic/pic-gicv3-its.c | 1584 +++++++++ rt-thread/components/drivers/pic/pic-gicv3.c | 39 +- rt-thread/components/drivers/pic/pic-gicv3.h | 179 +- rt-thread/components/drivers/pic/pic.c | 58 +- rt-thread/components/drivers/pin/Kconfig | 4 + rt-thread/components/drivers/pin/SConscript | 6 +- .../drivers/pin/{pin.c => dev_pin.c} | 12 +- rt-thread/components/drivers/pin/dev_pin_dm.c | 458 +++ .../drivers/pin/{pin_dm.h => dev_pin_dm.h} | 8 +- .../drivers/pin/{pin_ofw.c => dev_pin_ofw.c} | 32 +- rt-thread/components/drivers/pin/pin_dm.c | 220 -- rt-thread/components/drivers/pinctrl/Kconfig | 3 + .../components/drivers/pinctrl/pinctrl.c | 7 + rt-thread/components/drivers/pm/pm.c | 287 +- .../components/drivers/regulator/Kconfig | 23 + .../components/drivers/regulator/SConscript | 21 + .../drivers/regulator/regulator-fixed.c | 171 + .../drivers/regulator/regulator-gpio.c | 309 ++ .../components/drivers/regulator/regulator.c | 629 ++++ .../drivers/regulator/regulator_dm.c | 59 + .../drivers/regulator/regulator_dm.h | 26 + rt-thread/components/drivers/reset/Kconfig | 14 + rt-thread/components/drivers/reset/SConscript | 18 + .../components/drivers/reset/reset-simple.c | 202 ++ .../components/drivers/reset/reset-simple.h | 50 + rt-thread/components/drivers/reset/reset.c | 432 +++ rt-thread/components/drivers/rtc/Kconfig | 14 + rt-thread/components/drivers/rtc/SConscript | 6 +- .../drivers/rtc/{alarm.c => dev_alarm.c} | 16 +- .../drivers/rtc/{rtc.c => dev_rtc.c} | 2 +- .../rtc/{soft_rtc.c => dev_soft_rtc.c} | 35 +- rt-thread/components/drivers/scsi/Kconfig | 20 + rt-thread/components/drivers/scsi/SConscript | 21 + rt-thread/components/drivers/scsi/scsi.c | 669 ++++ .../components/drivers/scsi/scsi_cdrom.c | 136 + rt-thread/components/drivers/scsi/scsi_sd.c | 251 ++ rt-thread/components/drivers/sdio/Kconfig | 8 +- rt-thread/components/drivers/sdio/SConscript | 18 +- rt-thread/components/drivers/sdio/block_dev.c | 952 ----- rt-thread/components/drivers/sdio/dev_block.c | 422 +++ .../drivers/sdio/{mmc.c => dev_mmc.c} | 4 +- .../sdio/{mmcsd_core.c => dev_mmcsd_core.c} | 8 +- .../drivers/sdio/{sd.c => dev_sd.c} | 6 +- .../drivers/sdio/{sdio.c => dev_sdio.c} | 6 +- rt-thread/components/drivers/sdio/gpt.c | 563 --- .../components/drivers/sdio/sdhci/fit-mmc.c | 320 ++ .../sdio/sdhci/include/sdhci-platform.h | 66 + .../drivers/sdio/sdhci/include/sdhci.h | 677 ++++ .../drivers/sdio/sdhci/include/sdhci_host.h | 345 ++ .../drivers/sdio/sdhci/include/sdhci_misc.h | 70 + .../drivers/sdio/sdhci/sdhci-platform.c | 125 + .../components/drivers/sdio/sdhci/sdhci.c | 3152 +++++++++++++++++ rt-thread/components/drivers/sensor/Kconfig | 2 +- .../components/drivers/sensor/v1/sensor.c | 5 +- .../components/drivers/sensor/v1/sensor_cmd.c | 34 +- .../components/drivers/sensor/v2/sensor_cmd.c | 26 +- rt-thread/components/drivers/serial/Kconfig | 5 +- .../components/drivers/serial/SConscript | 7 +- rt-thread/components/drivers/serial/bypass.c | 355 ++ .../drivers/serial/{serial.c => dev_serial.c} | 60 +- .../serial/{serial_v2.c => dev_serial_v2.c} | 4 +- .../components/drivers/serial/serial_tty.c | 54 +- .../components/drivers/smp_call/SConscript | 10 + .../components/drivers/smp_call/smp_call.c | 374 ++ .../components/drivers/smp_call/smp_call.h | 74 + rt-thread/components/drivers/spi/SConscript | 15 +- .../spi/{qspi_core.c => dev_qspi_core.c} | 21 +- .../drivers/spi/{spi_dev.c => dev_spi.c} | 73 +- .../spi/{spi-bit-ops.c => dev_spi_bit_ops.c} | 57 +- .../spi/{spi-bit-ops.h => dev_spi_bit_ops.h} | 4 +- .../components/drivers/spi/dev_spi_bus.c | 203 ++ .../spi/{spi_core.c => dev_spi_core.c} | 72 +- rt-thread/components/drivers/spi/dev_spi_dm.c | 106 + rt-thread/components/drivers/spi/dev_spi_dm.h | 29 + .../spi/{spi_flash.h => dev_spi_flash.h} | 4 +- ...{spi_flash_sfud.c => dev_spi_flash_sfud.c} | 4 +- ...{spi_flash_sfud.h => dev_spi_flash_sfud.h} | 17 +- .../drivers/spi/{spi_msd.c => dev_spi_msd.c} | 2 +- .../drivers/spi/{spi_msd.h => dev_spi_msd.h} | 8 +- ...{spi_wifi_rw009.c => dev_spi_wifi_rw009.c} | 4 +- ...{spi_wifi_rw009.h => dev_spi_wifi_rw009.h} | 6 +- rt-thread/components/drivers/spi/enc28j60.h | 8 +- rt-thread/components/drivers/thermal/Kconfig | 28 + .../components/drivers/thermal/SConscript | 18 + .../drivers/thermal/thermal-cool-pwm-fan.c | 288 ++ .../components/drivers/thermal/thermal.c | 917 +++++ .../components/drivers/thermal/thermal_dm.c | 64 + .../components/drivers/thermal/thermal_dm.h | 27 + rt-thread/components/drivers/touch/SConscript | 2 +- .../drivers/touch/{touch.c => dev_touch.c} | 0 .../drivers/usb/cherryusb/CherryUSB.svg | 2 +- .../components/drivers/usb/cherryusb/Kconfig | 36 +- .../drivers/usb/cherryusb/Kconfig.cherryusb | 312 -- .../drivers/usb/cherryusb/README.md | 92 +- .../drivers/usb/cherryusb/README_zh.md | 90 +- .../drivers/usb/cherryusb/SConscript | 62 +- .../components/drivers/usb/cherryusb/VERSION | 4 +- .../drivers/usb/cherryusb/cherryusb.cmake | 62 +- .../usb/cherryusb/cherryusb_config_template.h | 19 +- .../usb/cherryusb/class/adb/usbd_adb.c | 310 ++ .../usb/cherryusb/class/adb/usbd_adb.h | 38 + .../drivers/usb/cherryusb/class/aoa/usb_aoa.h | 48 + .../usb/cherryusb/class/aoa/usbh_aoa.c | 289 ++ .../usb/cherryusb/class/aoa/usbh_aoa.h | 40 + .../usb/cherryusb/class/audio/usb_audio.h | 135 +- .../usb/cherryusb/class/audio/usbd_audio.c | 69 +- .../usb/cherryusb/class/audio/usbd_audio.h | 2 +- .../usb/cherryusb/class/audio/usbh_audio.c | 442 ++- .../usb/cherryusb/class/audio/usbh_audio.h | 54 +- .../drivers/usb/cherryusb/class/cdc/usb_cdc.h | 16 +- .../usb/cherryusb/class/cdc/usbd_cdc.h | 24 +- .../class/cdc/{usbd_cdc.c => usbd_cdc_acm.c} | 18 +- .../usb/cherryusb/class/cdc/usbd_cdc_acm.h | 29 + .../usb/cherryusb/class/cdc/usbd_cdc_ecm.c | 105 +- .../usb/cherryusb/class/cdc/usbd_cdc_ecm.h | 14 +- .../usb/cherryusb/class/cdc/usbh_cdc_acm.c | 42 +- .../usb/cherryusb/class/cdc/usbh_cdc_ecm.c | 9 +- .../usb/cherryusb/class/cdc/usbh_cdc_ncm.c | 13 +- .../drivers/usb/cherryusb/class/hid/usb_hid.h | 12 +- .../usb/cherryusb/class/hid/usbd_hid.c | 37 + .../usb/cherryusb/class/hid/usbh_hid.c | 98 +- .../usb/cherryusb/class/hid/usbh_hid.h | 5 +- .../drivers/usb/cherryusb/class/hub/usb_hub.h | 96 +- .../usb/cherryusb/class/hub/usbh_hub.c | 177 +- .../usb/cherryusb/class/hub/usbh_hub.h | 4 - .../usb/cherryusb/class/msc/usbd_msc.c | 87 +- .../usb/cherryusb/class/msc/usbd_msc.h | 4 +- .../usb/cherryusb/class/msc/usbh_msc.c | 66 +- .../usb/cherryusb/class/template/usbh_xxx.c | 18 +- .../cherryusb/class/vendor/net/usbh_asix.c | 22 +- .../cherryusb/class/vendor/net/usbh_rtl8152.c | 41 +- .../class/vendor/serial/usbh_ch34x.c | 20 +- .../class/vendor/serial/usbh_cp210x.c | 22 +- .../cherryusb/class/vendor/serial/usbh_ftdi.c | 24 +- .../class/vendor/serial/usbh_pl2303.c | 22 +- .../usb/cherryusb/class/vendor/wifi/README.md | 6 + .../cherryusb/class/vendor/wifi/usbh_bl616.c | 512 +++ .../cherryusb/class/vendor/wifi/usbh_bl616.h | 220 ++ .../cherryusb/class/vendor/xbox/usbh_xbox.c | 228 ++ .../cherryusb/class/vendor/xbox/usbh_xbox.h | 31 + .../usb/cherryusb/class/video/usbd_video.c | 144 +- .../usb/cherryusb/class/video/usbd_video.h | 4 +- .../usb/cherryusb/class/video/usbh_video.c | 30 +- .../usb/cherryusb/class/wireless/usbd_rndis.c | 43 +- .../usb/cherryusb/class/wireless/usbd_rndis.h | 3 +- .../cherryusb/class/wireless/usbh_bluetooth.c | 16 +- .../usb/cherryusb/class/wireless/usbh_rndis.c | 27 +- .../drivers/usb/cherryusb/common/usb_dc.h | 7 + .../drivers/usb/cherryusb/common/usb_def.h | 2 +- .../drivers/usb/cherryusb/common/usb_log.h | 29 + .../drivers/usb/cherryusb/common/usb_osal.h | 3 + .../usb/cherryusb/common/usb_version.h | 21 + .../drivers/usb/cherryusb/core/usbd_core.c | 194 +- .../drivers/usb/cherryusb/core/usbd_core.h | 10 +- .../drivers/usb/cherryusb/core/usbh_core.c | 91 +- .../drivers/usb/cherryusb/core/usbh_core.h | 26 +- .../usb/cherryusb/demo/adb/cherryadb.png | Bin 0 -> 42508 bytes .../usb/cherryusb/demo/adb/cherrysh_port.c | 330 ++ .../cherryusb/demo/adb/usbd_adb_template.c | 228 ++ .../demo/audio_v1_mic_multichan_template.c | 4 +- .../audio_v1_mic_speaker_multichan_template.c | 4 +- .../demo/audio_v2_mic_multichan_template.c | 4 +- .../audio_v2_mic_speaker_multichan_template.c | 4 +- .../audio_v2_speaker_multichan_template.c | 4 +- .../usb/cherryusb/demo/bootuf2/bootuf2.c | 463 +++ .../usb/cherryusb/demo/bootuf2/bootuf2.h | 218 ++ .../cherryusb/demo/bootuf2/bootuf2_config.h | 25 + .../usb/cherryusb/demo/bootuf2/cherryuf2.png | Bin 0 -> 19847 bytes .../demo/bootuf2/msc_bootuf2_template.c | 168 + .../cherryusb/demo/cdc_acm_hid_msc_template.c | 15 +- .../usb/cherryusb/demo/cdc_acm_msc_template.c | 8 +- .../cherryusb/demo/cdc_acm_multi_template.c | 6 +- .../usb/cherryusb/demo/cdc_acm_template.c | 6 +- .../usb/cherryusb/demo/cdc_ecm_template.c | 14 +- .../usb/cherryusb/demo/cdc_rndis_template.c | 16 +- .../demo/dfu_with_st_tool_template.c | 4 +- .../demo/hid_custom_inout_template.c | 4 +- .../cherryusb/demo/hid_keyboard_template.c | 11 +- .../usb/cherryusb/demo/hid_mouse_template.c | 74 +- .../demo/hid_remote_wakeup_template.c | 331 ++ .../usb/cherryusb/demo/midi_template.c | 4 +- .../usb/cherryusb/demo/msc_ram_template.c | 13 +- .../usb/cherryusb/demo/msc_storage_template.c | 4 +- .../drivers/usb/cherryusb/demo/usb_host.c | 37 +- .../demo/video_audiov1_hid_template.c | 52 +- .../demo/video_static_h264_template.c | 42 +- .../demo/video_static_mjpeg_template.c | 47 +- .../demo/video_static_yuyv_template.c | 45 +- .../usb/cherryusb/demo/webusb_hid_template.c | 383 ++ .../usb/cherryusb/demo/webusb_template.c | 76 - .../usb/cherryusb/demo/winusb1.0_template.c | 12 +- .../cherryusb/demo/winusb2.0_cdc_template.c | 6 +- .../cherryusb/demo/winusb2.0_hid_template.c | 4 +- .../drivers/usb/cherryusb/idf_component.yml | 25 + .../usb/cherryusb/osal/usb_osal_rtthread.c | 44 +- .../cherryusb/platform/rtthread/usb_check.c | 8 +- .../cherryusb/platform/rtthread/usbh_dfs.c | 29 +- .../cherryusb/platform/rtthread/usbh_lwip.c | 19 + .../cherryusb/port/bouffalolab/usb_dc_bl.c | 47 +- .../usb/cherryusb/port/ch32/usb_dc_usbfs.c | 5 + .../usb/cherryusb/port/ch32/usb_dc_usbhs.c | 5 + .../usb/cherryusb/port/chipidea/README.md | 14 + .../port/chipidea/usb_chipidea_reg.h | 2249 ++++++++++++ .../cherryusb/port/chipidea/usb_dc_chipidea.c | 718 ++++ .../cherryusb/port/chipidea/usb_glue_mcx.c | 99 + .../drivers/usb/cherryusb/port/dwc2/README.md | 7 + .../usb/cherryusb/port/dwc2/usb_dc_dwc2.c | 369 +- .../usb/cherryusb/port/dwc2/usb_dwc2_reg.h | 3 + .../usb/cherryusb/port/dwc2/usb_glue_at.c | 12 +- .../usb/cherryusb/port/dwc2/usb_glue_esp.c | 23 +- .../usb/cherryusb/port/dwc2/usb_glue_gd.c | 11 +- .../usb/cherryusb/port/dwc2/usb_glue_hc.c | 5 + .../cherryusb/port/dwc2/usb_glue_kendryte.c | 157 + .../usb/cherryusb/port/dwc2/usb_glue_st.c | 13 +- .../usb/cherryusb/port/dwc2/usb_hc_dwc2.c | 48 +- .../drivers/usb/cherryusb/port/ehci/README.md | 11 + .../usb/cherryusb/port/ehci/usb_ehci_priv.h | 84 - .../usb/cherryusb/port/ehci/usb_ehci_reg.h | 393 ++ .../usb/cherryusb/port/ehci/usb_glue_aic.c | 38 +- .../usb/cherryusb/port/ehci/usb_glue_hpm.c | 15 +- .../usb/cherryusb/port/ehci/usb_glue_ma35d0.c | 4 +- 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.../usb/cherryusb/port/ohci/usb_hc_ohci.h | 520 +-- .../usb/cherryusb/port/ohci/usb_ohci_priv.h | 24 - .../usb/cherryusb/port/ohci/usb_ohci_reg.h | 484 +++ .../usb/cherryusb/port/pusb2/README.md | 66 + .../port/pusb2/libpusb2_dc_a32_hardfp.a | Bin 0 -> 171332 bytes .../libpusb2_dc_a32_softfp_crypto_neon.a | Bin 0 -> 171328 bytes .../port/pusb2/libpusb2_dc_a32_softfp_neon.a | Bin 0 -> 325436 bytes .../cherryusb/port/pusb2/libpusb2_dc_a64.a | Bin 0 -> 141528 bytes .../port/pusb2/libpusb2_hc_a32_hardfp.a | Bin 0 -> 923220 bytes .../libpusb2_hc_a32_softfp_crypto_neon.a | Bin 0 -> 923192 bytes .../port/pusb2/libpusb2_hc_a32_softfp_neon.a | Bin 0 -> 328504 bytes .../cherryusb/port/pusb2/libpusb2_hc_a64.a | Bin 0 -> 1179500 bytes .../port/pusb2/rt-thread/usb_config.h | 265 ++ .../pusb2/rt-thread/usb_dc_glue_phytium.c | 89 + .../pusb2/rt-thread/usb_hc_glue_phytium.c | 109 + .../usb/cherryusb/port/xhci/phytium/README.md | 70 + .../port/xhci/phytium/libxhci_a32_hardfp.a | Bin 0 -> 52784 bytes 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dev_wlan_prot.h} | 4 +- ...{wlan_workqueue.c => dev_wlan_workqueue.c} | 2 +- ...{wlan_workqueue.h => dev_wlan_workqueue.h} | 4 +- rt-thread/components/fal/Kconfig | 10 +- rt-thread/components/fal/docs/fal_api.md | 10 +- rt-thread/components/fal/docs/fal_api_en.md | 10 +- rt-thread/components/fal/inc/fal.h | 10 +- rt-thread/components/fal/inc/fal_def.h | 79 +- .../components/fal/samples/porting/README.md | 6 +- .../fal/samples/porting/fal_flash_sfud_port.c | 26 +- .../samples/porting/fal_flash_stm32f2_port.c | 58 +- rt-thread/components/fal/src/fal.c | 15 +- rt-thread/components/fal/src/fal_flash.c | 42 +- rt-thread/components/fal/src/fal_partition.c | 126 +- rt-thread/components/fal/src/fal_rtt.c | 85 +- rt-thread/components/finsh/finsh.h | 21 +- rt-thread/components/finsh/msh.c | 6 +- rt-thread/components/finsh/shell.c | 7 +- rt-thread/components/legacy/fdt/Kconfig | 2 +- .../libc/compilers/common/cstring.c | 10 +- .../components/libc/compilers/common/ctime.c | 46 +- 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rt-thread/include/rtdef.h | 104 +- rt-thread/include/rthw.h | 4 +- rt-thread/include/rtklibc.h | 42 +- rt-thread/include/rtsched.h | 43 +- rt-thread/include/rtservice.h | 15 + rt-thread/include/rtthread.h | 13 +- rt-thread/include/rttypes.h | 36 +- rt-thread/libcpu/Kconfig | 62 +- rt-thread/libcpu/arm/AT91SAM7S/interrupt.c | 2 +- rt-thread/libcpu/arm/AT91SAM7X/interrupt.c | 2 +- rt-thread/libcpu/arm/am335x/interrupt.c | 2 +- rt-thread/libcpu/arm/cortex-a/backtrace.c | 2 +- rt-thread/libcpu/arm/cortex-m23/cpuport.c | 29 +- rt-thread/libcpu/arm/cortex-m23/cpuport.h | 45 + rt-thread/libcpu/arm/cortex-m4/README.md | 53 + rt-thread/libcpu/arm/cortex-m4/context_gcc.S | 7 + rt-thread/libcpu/arm/cortex-m4/context_iar.S | 11 +- rt-thread/libcpu/arm/cortex-m4/context_rvds.S | 9 +- rt-thread/libcpu/arm/cortex-m7/context_gcc.S | 4 +- rt-thread/libcpu/arm/cortex-r4/interrupt.c | 2 +- rt-thread/libcpu/arm/cortex-r52/backtrace.c | 2 +- rt-thread/libcpu/arm/cortex-r52/context_gcc.S | 227 +- rt-thread/libcpu/arm/cortex-r52/start_gcc.S | 58 +- rt-thread/libcpu/arm/cortex-r52/start_iar.S | 16 +- rt-thread/libcpu/arm/cortex-r52/vector_gcc.S | 10 +- rt-thread/libcpu/arm/cortex-r52/vector_iar.S | 2 + rt-thread/libcpu/arm/lpc214x/cpuport.c | 2 +- rt-thread/libcpu/arm/lpc24xx/interrupt.c | 2 +- .../libcpu/arm/realview-a8-vmm/interrupt.c | 2 +- rt-thread/libcpu/arm/s3c24x0/interrupt.c | 2 +- rt-thread/libcpu/arm/s3c44b0/interrupt.c | 2 +- rt-thread/libcpu/arm/sep4020/interrupt.c | 2 +- rt-thread/libcpu/arm/zynqmp-r5/interrupt.c | 2 +- rt-thread/src/Kconfig | 82 +- rt-thread/src/SConscript | 6 +- rt-thread/src/clock.c | 68 +- rt-thread/src/components.c | 7 +- rt-thread/src/defunct.c | 178 + rt-thread/src/idle.c | 183 +- rt-thread/src/ipc.c | 42 +- rt-thread/src/irq.c | 20 + rt-thread/src/klibc/Kconfig | 258 ++ rt-thread/src/klibc/SConscript | 23 + rt-thread/src/klibc/kerrno.c | 161 + rt-thread/src/klibc/kstdio.c | 779 +--- rt-thread/src/klibc/kstring.c | 100 +- rt-thread/src/klibc/rt_vsnprintf_std.c | 1351 +++++++ rt-thread/src/klibc/rt_vsnprintf_tiny.c | 611 ++++ rt-thread/src/klibc/rt_vsscanf.c | 700 ++++ rt-thread/src/klibc/utest/SConscript | 10 + rt-thread/src/klibc/utest/TC_rt_memcmp.c | 161 + rt-thread/src/klibc/utest/TC_rt_memcpy.c | 108 + rt-thread/src/klibc/utest/TC_rt_memmove.c | 108 + rt-thread/src/klibc/utest/TC_rt_memset.c | 102 + rt-thread/src/klibc/utest/TC_rt_sprintf.c | 1065 ++++++ rt-thread/src/klibc/utest/TC_rt_sscanf.c | 250 ++ rt-thread/src/kservice.c | 53 +- rt-thread/src/mem.c | 50 +- rt-thread/src/memheap.c | 10 +- rt-thread/src/object.c | 2 +- rt-thread/src/scheduler_comm.c | 30 +- rt-thread/src/scheduler_mp.c | 3 - rt-thread/src/scheduler_up.c | 12 +- rt-thread/src/signal.c | 10 +- rt-thread/src/slab.c | 52 +- rt-thread/src/thread.c | 80 +- rt-thread/tools/building.py | 74 +- rt-thread/tools/ci/bsp_buildings.py | 85 +- rt-thread/tools/ci/bsp_detail.py | 206 ++ rt-thread/tools/ci/bsp_detail.yml | 2606 ++++++++++++++ rt-thread/tools/ci/cpp_check.py | 39 +- rt-thread/tools/ci/install.sh | 219 ++ rt-thread/tools/ci/manual_bsp_build_all.py | 338 ++ rt-thread/tools/ci/requirements.txt | 2 + rt-thread/tools/ci/toolchain.sh | 87 + rt-thread/tools/ci/toolchain_bsp.yml | 428 +++ rt-thread/tools/cmake.py | 145 +- rt-thread/tools/eclipse.py | 2 +- rt-thread/tools/env.py | 55 - rt-thread/tools/env_utility.py | 488 +++ rt-thread/tools/install_env.py | 191 - rt-thread/tools/menukconfig.py | 392 -- rt-thread/tools/mkdist.py | 2 +- rt-thread/tools/options.py | 10 +- rt-thread/tools/utils.py | 2 +- rt-thread/tools/vsc.py | 225 +- rt-thread/tools/wizard.py | 2 +- rt-thread/tools/zigbuild.py | 100 + rtconfig.h | 90 +- 731 files changed, 77517 insertions(+), 9955 deletions(-) create mode 100644 .vscode/project.json create mode 100644 rt-thread/components/dfs/dfs_v1/filesystems/iso9660/SConscript create mode 100644 rt-thread/components/dfs/dfs_v1/filesystems/iso9660/dfs_iso9660.c create mode 100644 rt-thread/components/dfs/dfs_v1/filesystems/iso9660/dfs_iso9660.h create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/README.md create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/SConscript create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc.h create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_cmdline.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_cpuinfo.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_devices.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_filesystems.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_loadavg.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_meminfo.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_mounts.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_net.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_partitions.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_pid.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_self.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_stat.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_tty.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_uptime.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_version.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/procfs.c create mode 100644 rt-thread/components/dfs/dfs_v2/filesystems/procfs/procfs.h create mode 100644 rt-thread/components/dfs/dfs_v2/include/dfs_vfs.h create mode 100644 rt-thread/components/drivers/ata/Kconfig create mode 100644 rt-thread/components/drivers/ata/SConscript create mode 100644 rt-thread/components/drivers/ata/ahci-pci.c create mode 100644 rt-thread/components/drivers/ata/ahci.c rename rt-thread/components/drivers/audio/{audio.c => dev_audio.c} (100%) rename rt-thread/components/drivers/audio/{audio_pipe.c => dev_audio_pipe.c} (90%) rename rt-thread/components/drivers/audio/{audio_pipe.h => dev_audio_pipe.h} (95%) create mode 100644 rt-thread/components/drivers/block/Kconfig create mode 100644 rt-thread/components/drivers/block/SConscript create mode 100644 rt-thread/components/drivers/block/blk.c create mode 100644 rt-thread/components/drivers/block/blk_dev.c create mode 100644 rt-thread/components/drivers/block/blk_dev.h create mode 100644 rt-thread/components/drivers/block/blk_dfs.c create mode 100644 rt-thread/components/drivers/block/blk_dfs.h create mode 100644 rt-thread/components/drivers/block/blk_partition.c create mode 100644 rt-thread/components/drivers/block/blk_partition.h create mode 100644 rt-thread/components/drivers/block/partitions/Kconfig create mode 100644 rt-thread/components/drivers/block/partitions/SConscript create mode 100644 rt-thread/components/drivers/block/partitions/dfs.c create mode 100644 rt-thread/components/drivers/block/partitions/efi.c create mode 100644 rt-thread/components/drivers/block/partitions/efi.h rename rt-thread/components/drivers/can/{can.c => dev_can.c} (99%) create mode 100644 rt-thread/components/drivers/dma/Kconfig create mode 100644 rt-thread/components/drivers/dma/SConscript create mode 100644 rt-thread/components/drivers/dma/dma.c create mode 100644 rt-thread/components/drivers/dma/dma_pool.c rename rt-thread/components/drivers/i2c/{i2c-bit-ops.c => dev_i2c_bit_ops.c} (100%) rename rt-thread/components/drivers/i2c/{i2c_bus.c => dev_i2c_bus.c} (99%) rename rt-thread/components/drivers/i2c/{i2c_core.c => dev_i2c_core.c} (98%) rename rt-thread/components/drivers/i2c/{i2c_dev.c => dev_i2c_dev.c} (100%) rename rt-thread/components/drivers/i2c/{i2c_dm.c => dev_i2c_dm.c} (98%) rename rt-thread/components/drivers/i2c/{soft_i2c.c => dev_soft_i2c.c} (94%) create mode 100644 rt-thread/components/drivers/iio/SConscript create mode 100644 rt-thread/components/drivers/iio/iio.c create mode 100644 rt-thread/components/drivers/include/drivers/ahci.h create mode 100644 rt-thread/components/drivers/include/drivers/blk.h create mode 100644 rt-thread/components/drivers/include/drivers/core/master_id.h rename rt-thread/components/drivers/include/drivers/{alarm.h => dev_alarm.h} (96%) rename rt-thread/components/drivers/include/drivers/{audio.h => dev_audio.h} (98%) rename rt-thread/components/drivers/include/drivers/{can.h => dev_can.h} (65%) create mode 100644 rt-thread/components/drivers/include/drivers/dev_i2c.h rename rt-thread/components/drivers/include/drivers/{i2c-bit-ops.h => dev_i2c_bit_ops.h} (93%) rename rt-thread/components/drivers/include/drivers/{i2c_dm.h => dev_i2c_dm.h} (95%) rename rt-thread/components/drivers/include/drivers/{mmc.h => dev_mmc.h} (99%) rename rt-thread/components/drivers/include/drivers/{mmcsd_core.h => dev_mmcsd_core.h} (98%) rename rt-thread/components/drivers/include/drivers/{pin.h => dev_pin.h} (50%) create mode 100644 rt-thread/components/drivers/include/drivers/dev_pwm.h rename rt-thread/components/drivers/include/drivers/{rtc.h => dev_rtc.h} (59%) rename rt-thread/components/drivers/include/drivers/{sd.h => dev_sd.h} (96%) rename rt-thread/components/drivers/include/drivers/{sdio.h => dev_sdio.h} (99%) rename rt-thread/components/drivers/include/drivers/{serial.h => dev_serial.h} (66%) rename rt-thread/components/drivers/include/drivers/{serial_v2.h => dev_serial_v2.h} (61%) create mode 100644 rt-thread/components/drivers/include/drivers/dev_spi.h rename rt-thread/components/drivers/include/drivers/{touch.h => dev_touch.h} (53%) rename rt-thread/components/drivers/include/drivers/{watchdog.h => dev_watchdog.h} (94%) create mode 100644 rt-thread/components/drivers/include/drivers/dma.h delete mode 100644 rt-thread/components/drivers/include/drivers/gpt.h delete mode 100644 rt-thread/components/drivers/include/drivers/i2c.h delete mode 100644 rt-thread/components/drivers/include/drivers/i2c_dev.h create mode 100644 rt-thread/components/drivers/include/drivers/iio.h create mode 100644 rt-thread/components/drivers/include/drivers/led.h create mode 100644 rt-thread/components/drivers/include/drivers/mailbox.h create mode 100644 rt-thread/components/drivers/include/drivers/nvme.h create mode 100644 rt-thread/components/drivers/include/drivers/pci.h create mode 100644 rt-thread/components/drivers/include/drivers/pci_endpoint.h create mode 100644 rt-thread/components/drivers/include/drivers/pci_msi.h delete mode 100644 rt-thread/components/drivers/include/drivers/phy_mdio.h create mode 100644 rt-thread/components/drivers/include/drivers/phye.h create mode 100644 rt-thread/components/drivers/include/drivers/regulator.h create mode 100644 rt-thread/components/drivers/include/drivers/reset.h delete mode 100644 rt-thread/components/drivers/include/drivers/rt_drv_pwm.h create mode 100644 rt-thread/components/drivers/include/drivers/scsi.h create mode 100644 rt-thread/components/drivers/include/drivers/serial_bypass.h delete mode 100644 rt-thread/components/drivers/include/drivers/spi.h create mode 100644 rt-thread/components/drivers/include/drivers/syscon.h create mode 100644 rt-thread/components/drivers/include/drivers/thermal.h create mode 100644 rt-thread/components/drivers/include/dt-bindings/phye/phye.h create mode 100644 rt-thread/components/drivers/include/dt-bindings/thermal/thermal.h create mode 100644 rt-thread/components/drivers/led/Kconfig create mode 100644 rt-thread/components/drivers/led/SConscript create mode 100644 rt-thread/components/drivers/led/led-gpio.c create mode 100644 rt-thread/components/drivers/led/led.c create mode 100644 rt-thread/components/drivers/mailbox/Kconfig create mode 100644 rt-thread/components/drivers/mailbox/SConscript create mode 100644 rt-thread/components/drivers/mailbox/mailbox-pic.c create mode 100644 rt-thread/components/drivers/mailbox/mailbox.c create mode 100644 rt-thread/components/drivers/mfd/Kconfig create mode 100644 rt-thread/components/drivers/mfd/SConscript create mode 100644 rt-thread/components/drivers/mfd/mfd-syscon.c create mode 100644 rt-thread/components/drivers/nvme/Kconfig create mode 100644 rt-thread/components/drivers/nvme/SConscript create mode 100644 rt-thread/components/drivers/nvme/nvme-pci.c create mode 100644 rt-thread/components/drivers/nvme/nvme.c create mode 100644 rt-thread/components/drivers/pci/Kconfig create mode 100644 rt-thread/components/drivers/pci/SConscript create mode 100644 rt-thread/components/drivers/pci/access.c create mode 100644 rt-thread/components/drivers/pci/ecam.c create mode 100644 rt-thread/components/drivers/pci/ecam.h create mode 100644 rt-thread/components/drivers/pci/endpoint/SConscript create mode 100644 rt-thread/components/drivers/pci/endpoint/endpoint.c create mode 100644 rt-thread/components/drivers/pci/endpoint/mem.c create mode 100644 rt-thread/components/drivers/pci/host-bridge.c create mode 100644 rt-thread/components/drivers/pci/host/Kconfig create mode 100644 rt-thread/components/drivers/pci/host/SConscript create mode 100644 rt-thread/components/drivers/pci/host/dw/Kconfig create mode 100644 rt-thread/components/drivers/pci/host/dw/SConscript create mode 100644 rt-thread/components/drivers/pci/host/dw/pcie-dw.c create mode 100644 rt-thread/components/drivers/pci/host/dw/pcie-dw.h create mode 100644 rt-thread/components/drivers/pci/host/dw/pcie-dw_ep.c create mode 100644 rt-thread/components/drivers/pci/host/dw/pcie-dw_host.c create mode 100644 rt-thread/components/drivers/pci/host/dw/pcie-dw_platfrom.c create mode 100644 rt-thread/components/drivers/pci/host/pci-host-common.c create mode 100644 rt-thread/components/drivers/pci/host/pci-host-generic.c create mode 100644 rt-thread/components/drivers/pci/irq.c create mode 100644 rt-thread/components/drivers/pci/msi/SConscript create mode 100644 rt-thread/components/drivers/pci/msi/device.c create mode 100644 rt-thread/components/drivers/pci/msi/irq.c create mode 100644 rt-thread/components/drivers/pci/msi/msi.c create mode 100644 rt-thread/components/drivers/pci/ofw.c create mode 100644 rt-thread/components/drivers/pci/pci.c create mode 100644 rt-thread/components/drivers/pci/pci_ids.h create mode 100644 rt-thread/components/drivers/pci/pci_regs.h create mode 100644 rt-thread/components/drivers/pci/pme.c create mode 100644 rt-thread/components/drivers/pci/probe.c create mode 100644 rt-thread/components/drivers/phy/general.c create mode 100644 rt-thread/components/drivers/phy/general_phy.h create mode 100644 rt-thread/components/drivers/phy/mdio.c create mode 100644 rt-thread/components/drivers/phy/mdio.h create mode 100644 rt-thread/components/drivers/phy/ofw.c create mode 100644 rt-thread/components/drivers/phy/ofw.h create mode 100644 rt-thread/components/drivers/phye/Kconfig create mode 100644 rt-thread/components/drivers/phye/SConscript create mode 100644 rt-thread/components/drivers/phye/phye.c create mode 100644 rt-thread/components/drivers/pic/pic-gicv2m.c create mode 100644 rt-thread/components/drivers/pic/pic-gicv3-its.c rename rt-thread/components/drivers/pin/{pin.c => dev_pin.c} (96%) create mode 100644 rt-thread/components/drivers/pin/dev_pin_dm.c rename rt-thread/components/drivers/pin/{pin_dm.h => dev_pin_dm.h} (70%) rename rt-thread/components/drivers/pin/{pin_ofw.c => dev_pin_ofw.c} (87%) delete mode 100644 rt-thread/components/drivers/pin/pin_dm.c create mode 100644 rt-thread/components/drivers/regulator/Kconfig create mode 100644 rt-thread/components/drivers/regulator/SConscript create mode 100644 rt-thread/components/drivers/regulator/regulator-fixed.c create mode 100644 rt-thread/components/drivers/regulator/regulator-gpio.c create mode 100644 rt-thread/components/drivers/regulator/regulator.c create mode 100644 rt-thread/components/drivers/regulator/regulator_dm.c create mode 100644 rt-thread/components/drivers/regulator/regulator_dm.h create mode 100644 rt-thread/components/drivers/reset/Kconfig create mode 100644 rt-thread/components/drivers/reset/SConscript create mode 100644 rt-thread/components/drivers/reset/reset-simple.c create mode 100644 rt-thread/components/drivers/reset/reset-simple.h create mode 100644 rt-thread/components/drivers/reset/reset.c rename rt-thread/components/drivers/rtc/{alarm.c => dev_alarm.c} (97%) rename rt-thread/components/drivers/rtc/{rtc.c => dev_rtc.c} (99%) rename rt-thread/components/drivers/rtc/{soft_rtc.c => dev_soft_rtc.c} (87%) create mode 100644 rt-thread/components/drivers/scsi/Kconfig create mode 100644 rt-thread/components/drivers/scsi/SConscript create mode 100644 rt-thread/components/drivers/scsi/scsi.c create mode 100644 rt-thread/components/drivers/scsi/scsi_cdrom.c create mode 100644 rt-thread/components/drivers/scsi/scsi_sd.c delete mode 100644 rt-thread/components/drivers/sdio/block_dev.c create mode 100644 rt-thread/components/drivers/sdio/dev_block.c rename rt-thread/components/drivers/sdio/{mmc.c => dev_mmc.c} (99%) rename rt-thread/components/drivers/sdio/{mmcsd_core.c => dev_mmcsd_core.c} (99%) rename rt-thread/components/drivers/sdio/{sd.c => dev_sd.c} (99%) rename rt-thread/components/drivers/sdio/{sdio.c => dev_sdio.c} (99%) delete mode 100644 rt-thread/components/drivers/sdio/gpt.c create mode 100644 rt-thread/components/drivers/sdio/sdhci/fit-mmc.c create mode 100644 rt-thread/components/drivers/sdio/sdhci/include/sdhci-platform.h create mode 100644 rt-thread/components/drivers/sdio/sdhci/include/sdhci.h create mode 100644 rt-thread/components/drivers/sdio/sdhci/include/sdhci_host.h create mode 100644 rt-thread/components/drivers/sdio/sdhci/include/sdhci_misc.h create mode 100644 rt-thread/components/drivers/sdio/sdhci/sdhci-platform.c create mode 100644 rt-thread/components/drivers/sdio/sdhci/sdhci.c create mode 100644 rt-thread/components/drivers/serial/bypass.c rename rt-thread/components/drivers/serial/{serial.c => dev_serial.c} (96%) rename rt-thread/components/drivers/serial/{serial_v2.c => dev_serial_v2.c} (99%) create mode 100644 rt-thread/components/drivers/smp_call/SConscript create mode 100644 rt-thread/components/drivers/smp_call/smp_call.c create mode 100644 rt-thread/components/drivers/smp_call/smp_call.h rename rt-thread/components/drivers/spi/{qspi_core.c => dev_qspi_core.c} (93%) rename rt-thread/components/drivers/spi/{spi_dev.c => dev_spi.c} (69%) rename rt-thread/components/drivers/spi/{spi-bit-ops.c => dev_spi_bit_ops.c} (90%) rename rt-thread/components/drivers/spi/{spi-bit-ops.h => dev_spi_bit_ops.h} (95%) create mode 100644 rt-thread/components/drivers/spi/dev_spi_bus.c rename rt-thread/components/drivers/spi/{spi_core.c => dev_spi_core.c} (89%) create mode 100644 rt-thread/components/drivers/spi/dev_spi_dm.c create mode 100644 rt-thread/components/drivers/spi/dev_spi_dm.h rename rt-thread/components/drivers/spi/{spi_flash.h => dev_spi_flash.h} (93%) rename rt-thread/components/drivers/spi/{spi_flash_sfud.c => dev_spi_flash_sfud.c} (99%) rename rt-thread/components/drivers/spi/{spi_flash_sfud.h => dev_spi_flash_sfud.h} (88%) rename rt-thread/components/drivers/spi/{spi_msd.c => dev_spi_msd.c} (99%) rename rt-thread/components/drivers/spi/{spi_msd.h => dev_spi_msd.h} (97%) rename rt-thread/components/drivers/spi/{spi_wifi_rw009.c => dev_spi_wifi_rw009.c} (99%) rename rt-thread/components/drivers/spi/{spi_wifi_rw009.h => dev_spi_wifi_rw009.h} (98%) create mode 100644 rt-thread/components/drivers/thermal/Kconfig create mode 100644 rt-thread/components/drivers/thermal/SConscript create mode 100644 rt-thread/components/drivers/thermal/thermal-cool-pwm-fan.c create mode 100644 rt-thread/components/drivers/thermal/thermal.c create mode 100644 rt-thread/components/drivers/thermal/thermal_dm.c create mode 100644 rt-thread/components/drivers/thermal/thermal_dm.h rename rt-thread/components/drivers/touch/{touch.c => dev_touch.c} (100%) delete mode 100644 rt-thread/components/drivers/usb/cherryusb/Kconfig.cherryusb create mode 100644 rt-thread/components/drivers/usb/cherryusb/class/adb/usbd_adb.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/class/adb/usbd_adb.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/class/aoa/usb_aoa.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/class/aoa/usbh_aoa.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/class/aoa/usbh_aoa.h rename rt-thread/components/drivers/usb/cherryusb/class/cdc/{usbd_cdc.c => usbd_cdc_acm.c} (94%) create mode 100644 rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_acm.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/class/vendor/wifi/README.md create mode 100644 rt-thread/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/class/vendor/xbox/usbh_xbox.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/class/vendor/xbox/usbh_xbox.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/common/usb_version.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/demo/adb/cherryadb.png create mode 100644 rt-thread/components/drivers/usb/cherryusb/demo/adb/cherrysh_port.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/demo/adb/usbd_adb_template.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/bootuf2.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/bootuf2.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/bootuf2_config.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/cherryuf2.png create mode 100644 rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/msc_bootuf2_template.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/demo/hid_remote_wakeup_template.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/demo/webusb_hid_template.c delete mode 100644 rt-thread/components/drivers/usb/cherryusb/demo/webusb_template.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/idf_component.yml create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/chipidea/README.md create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/chipidea/usb_chipidea_reg.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/chipidea/usb_dc_chipidea.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/chipidea/usb_glue_mcx.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_kendryte.c delete mode 100644 rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_ehci_priv.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_ehci_reg.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_mcx.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/kinetis/README.md create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_dc_kinetis.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_glue_mcx.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_hc_kinetis.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_kinetis_reg.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_glue_lpc.c delete mode 100644 rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_ohci_priv.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_ohci_reg.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/pusb2/README.md create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/pusb2/libpusb2_dc_a32_hardfp.a create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/pusb2/libpusb2_dc_a32_softfp_crypto_neon.a create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/pusb2/libpusb2_dc_a32_softfp_neon.a create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/pusb2/libpusb2_dc_a64.a create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/pusb2/libpusb2_hc_a32_hardfp.a create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/pusb2/libpusb2_hc_a32_softfp_crypto_neon.a create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/pusb2/libpusb2_hc_a32_softfp_neon.a create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/pusb2/libpusb2_hc_a64.a create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/pusb2/rt-thread/usb_config.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/pusb2/rt-thread/usb_dc_glue_phytium.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/pusb2/rt-thread/usb_hc_glue_phytium.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/xhci/phytium/README.md create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/xhci/phytium/libxhci_a32_hardfp.a create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/xhci/phytium/libxhci_a32_softfp_crypto_neon.a create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/xhci/phytium/libxhci_a32_softfp_neon.a create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/xhci/phytium/libxhci_a64.a create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/xhci/phytium/rt-thread/usb_config.h create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/xhci/phytium/rt-thread/usb_glue_phytium.c create mode 100644 rt-thread/components/drivers/usb/cherryusb/port/xhci/phytium/rt-thread/usb_glue_phytium_plat.c rename rt-thread/components/drivers/watchdog/{watchdog.c => dev_watchdog.c} (98%) rename rt-thread/components/drivers/wlan/{wlan_dev.c => dev_wlan.c} (93%) rename rt-thread/components/drivers/wlan/{wlan_dev.h => dev_wlan.h} (96%) rename rt-thread/components/drivers/wlan/{wlan_cfg.c => dev_wlan_cfg.c} (99%) rename rt-thread/components/drivers/wlan/{wlan_cfg.h => dev_wlan_cfg.h} (94%) rename rt-thread/components/drivers/wlan/{wlan_cmd.c => dev_wlan_cmd.c} (99%) rename rt-thread/components/drivers/wlan/{wlan_lwip.c => dev_wlan_lwip.c} (99%) rename rt-thread/components/drivers/wlan/{wlan_mgnt.c => dev_wlan_mgnt.c} (98%) rename rt-thread/components/drivers/wlan/{wlan_mgnt.h => dev_wlan_mgnt.h} (98%) rename rt-thread/components/drivers/wlan/{wlan_prot.c => dev_wlan_prot.c} (99%) rename rt-thread/components/drivers/wlan/{wlan_prot.h => dev_wlan_prot.h} (97%) rename rt-thread/components/drivers/wlan/{wlan_workqueue.c => dev_wlan_workqueue.c} (98%) rename rt-thread/components/drivers/wlan/{wlan_workqueue.h => dev_wlan_workqueue.h} (92%) create mode 100644 rt-thread/components/lwp/arch/aarch64/common/vdso.c create mode 100644 rt-thread/components/lwp/arch/aarch64/common/vdso_data.c create mode 100644 rt-thread/components/lwp/lwp_runtime.c create mode 100644 rt-thread/components/lwp/vdso/Kconfig create mode 100644 rt-thread/components/lwp/vdso/SConscript create mode 100644 rt-thread/components/lwp/vdso/kernel/vdso.h create mode 100644 rt-thread/components/lwp/vdso/kernel/vdso_data.h create mode 100644 rt-thread/components/lwp/vdso/kernel/vdso_text.S create mode 100644 rt-thread/components/lwp/vdso/user/SConstruct create mode 100644 rt-thread/components/lwp/vdso/user/vdso.lds.S create mode 100644 rt-thread/components/lwp/vdso/user/vdso_sys.c create mode 100644 rt-thread/components/lwp/vdso/user/vdso_sys.h create mode 100644 rt-thread/components/lwp/vdso/user/xmake.lua create mode 100644 rt-thread/components/lwp/vdso/vdso_config.h create mode 100644 rt-thread/components/lwp/vdso/vdso_datapage.h create mode 100644 rt-thread/components/lwp/vdso/vdso_weak.c create mode 100644 rt-thread/components/utilities/utest/TC_uassert.c create mode 100644 rt-thread/include/klibc/kerrno.h create mode 100644 rt-thread/include/klibc/kstdio.h create mode 100644 rt-thread/include/klibc/kstring.h create mode 100644 rt-thread/libcpu/arm/cortex-m23/cpuport.h create mode 100644 rt-thread/libcpu/arm/cortex-m4/README.md create mode 100644 rt-thread/src/defunct.c create mode 100644 rt-thread/src/klibc/Kconfig create mode 100644 rt-thread/src/klibc/SConscript create mode 100644 rt-thread/src/klibc/kerrno.c create mode 100644 rt-thread/src/klibc/rt_vsnprintf_std.c create mode 100644 rt-thread/src/klibc/rt_vsnprintf_tiny.c create mode 100644 rt-thread/src/klibc/rt_vsscanf.c create mode 100644 rt-thread/src/klibc/utest/SConscript create mode 100644 rt-thread/src/klibc/utest/TC_rt_memcmp.c create mode 100644 rt-thread/src/klibc/utest/TC_rt_memcpy.c create mode 100644 rt-thread/src/klibc/utest/TC_rt_memmove.c create mode 100644 rt-thread/src/klibc/utest/TC_rt_memset.c create mode 100644 rt-thread/src/klibc/utest/TC_rt_sprintf.c create mode 100644 rt-thread/src/klibc/utest/TC_rt_sscanf.c create mode 100644 rt-thread/tools/ci/bsp_detail.py create mode 100644 rt-thread/tools/ci/bsp_detail.yml create mode 100644 rt-thread/tools/ci/install.sh create mode 100644 rt-thread/tools/ci/manual_bsp_build_all.py create mode 100644 rt-thread/tools/ci/requirements.txt create mode 100644 rt-thread/tools/ci/toolchain.sh create mode 100644 rt-thread/tools/ci/toolchain_bsp.yml delete mode 100644 rt-thread/tools/env.py create mode 100644 rt-thread/tools/env_utility.py delete mode 100644 rt-thread/tools/install_env.py delete mode 100644 rt-thread/tools/menukconfig.py create mode 100644 rt-thread/tools/zigbuild.py diff --git a/.config b/.config index f7bff01..f870e88 100644 --- a/.config +++ b/.config @@ -4,10 +4,126 @@ CONFIG_BOARD_STM32F407_SPARK=y # # RT-Thread Kernel # + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options + +# CONFIG_RT_UTEST_TC_USING_KLIBC is not set +# end of klibc options + CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_AMP is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_CPUS_NR=1 @@ -17,6 +133,7 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -30,25 +147,17 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_CPU_USAGE_TRACER is not set # -# kservice optimization +# kservice options # # CONFIG_RT_USING_TINY_FFS is not set -# end of kservice optimization - -# -# klibc optimization -# -# CONFIG_RT_KLIBC_USING_STDLIB is not set -# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set -# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set -# end of klibc optimization +# end of kservice options CONFIG_RT_USING_DEBUG=y CONFIG_RT_DEBUGING_ASSERT=y CONFIG_RT_DEBUGING_COLOR=y CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_AUTO_INIT is not set -CONFIG_RT_USING_OVERFLOW_CHECK=y +# CONFIG_RT_USING_CI_ACTION is not set # # Inter-Thread communication @@ -83,7 +192,6 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set # CONFIG_RT_USING_THREADSAFE_PRINTF is not set -# CONFIG_RT_USING_SCHED_THREAD_CTX is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" @@ -172,8 +280,7 @@ CONFIG_RT_USING_DFS_ROMFS=y # end of DFS: device virtual file system CONFIG_RT_USING_FAL=y -CONFIG_FAL_DEBUG_CONFIG=y -CONFIG_FAL_DEBUG=1 +CONFIG_FAL_USING_DEBUG=y CONFIG_FAL_PART_HAS_TABLE_CFG=y CONFIG_FAL_USING_SFUD_PORT=y CONFIG_FAL_USING_NOR_FLASH_DEV_NAME="norflash0" @@ -193,6 +300,7 @@ CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set CONFIG_RT_USING_I2C=y @@ -201,6 +309,7 @@ CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_I2C_BITOPS_DEBUG is not set # CONFIG_RT_USING_SOFT_I2C is not set # CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set CONFIG_RT_USING_ADC=y # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set @@ -222,6 +331,7 @@ CONFIG_RT_MMCSD_STACK_SIZE=1024 CONFIG_RT_MMCSD_THREAD_PREORITY=22 CONFIG_RT_MMCSD_MAX_PARTITION=16 # CONFIG_RT_SDIO_DEBUG is not set +# CONFIG_RT_USING_SDHCI is not set CONFIG_RT_USING_SPI=y # CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_QSPI is not set @@ -270,6 +380,15 @@ CONFIG_RT_WLAN_WORKQUEUE_THREAD_NAME="wlan" CONFIG_RT_WLAN_WORKQUEUE_THREAD_SIZE=2048 CONFIG_RT_WLAN_WORKQUEUE_THREAD_PRIO=15 # CONFIG_RT_WLAN_DEBUG is not set +CONFIG_RT_USING_BLK=y + +# +# Partition Types +# +CONFIG_RT_BLK_PARTITION_DFS=y +CONFIG_RT_BLK_PARTITION_EFI=y +# end of Partition Types + # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_KTIME is not set @@ -355,6 +474,7 @@ CONFIG_NETDEV_USING_IFCONFIG=y CONFIG_NETDEV_USING_PING=y CONFIG_NETDEV_USING_NETSTAT=y CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_LINK_STATUS_CALLBACK is not set # CONFIG_NETDEV_USING_IPV6 is not set CONFIG_NETDEV_IPV4=1 CONFIG_NETDEV_IPV6=0 @@ -418,6 +538,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set CONFIG_RT_LWIP_USING_PING=y # CONFIG_LWIP_USING_DHCPD is not set +# CONFIG_RT_LWIP_ENABLE_USER_HOOKS is not set # CONFIG_RT_LWIP_DEBUG is not set CONFIG_RT_USING_AT=y CONFIG_AT_DEBUG=y @@ -955,6 +1076,7 @@ CONFIG_PKG_PERF_COUNTER_PATH="/packages/system/perf_counter" CONFIG_PKG_USING_PERF_COUNTER_V2241=y # CONFIG_PKG_USING_PERF_COUNTER_LATEST_VERSION is not set CONFIG_PKG_PERF_COUNTER_VER="v2.2.4.1" +CONFIG_FAL_DEBUG_CONFIG=y # CONFIG_PKG_USING_FILEX is not set # CONFIG_PKG_USING_LEVELX is not set # CONFIG_PKG_USING_FLASHDB is not set diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json index f5dfcb1..824a4ca 100644 --- a/.vscode/c_cpp_properties.json +++ b/.vscode/c_cpp_properties.json @@ -4,12 +4,379 @@ "name": "rt-thread", "defines": [ "RT_USING_LIBC", - "RT_USING_NEWLIBC", - "STM32F407xx", "USE_HAL_DRIVER", - "_POSIX_C_SOURCE=1", "__RTTHREAD__", - "__perf_counter_printf__=rt_kprintf" + "__STDC_LIMIT_MACROS", + "__CLK_TCK=RT_TICK_PER_SECOND", + "STM32F407xx", + "RT_USING_ARMLIBC", + "__alignof__(x)=", + "__asm(x)=", + "__asm__(x)=", + "__forceinline=", + "__restrict=", + "__volatile__=", + "__inline=", + "__inline__=", + "__declspec(x)=", + "__attribute__(x)=", + "__nonnull__(x)=", + "__unaligned=", + "__promise(x)=", + "__irq=", + "__swi=", + "__weak=", + "__register=", + "__pure=", + "__value_in_regs=", + "__breakpoint(x)=", + "__current_pc()=0U", + "__current_sp()=0U", + "__disable_fiq()=", + "__disable_irq()=", + "__enable_fiq()=", + "__enable_irq()=", + "__force_stores()=", + "__memory_changed()=", + "__schedule_barrier()=", + "__semihost(x,y)=0", + "__vfp_status(x,y)=0", + "__builtin_arm_nop()=", + "__builtin_arm_wfi()=", + "__builtin_arm_wfe()=", + "__builtin_arm_sev()=", + "__builtin_arm_sevl()=", + "__builtin_arm_yield()=", + "__builtin_arm_isb(x)=", + "__builtin_arm_dsb(x)=", + "__builtin_arm_dmb(x)=", + "__builtin_bswap32(x)=0U", + "__builtin_bswap16(x)=0U", + "__builtin_arm_rbit(x)=0U", + "__builtin_clz(x)=0U", + "__builtin_arm_ldrex(x)=0U", + "__builtin_arm_strex(x,y)=0U", + "__builtin_arm_clrex()=", + "__builtin_arm_ssat(x,y)=0U", + "__builtin_arm_usat(x,y)=0U", + "__builtin_arm_ldaex(x)=0U", + "__builtin_arm_stlex(x,y)=0U", + "_ILP32=1", + "_USE_STATIC_INLINE=1", + "__APCS_32__=1", + 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"rt-thread\\components\\net\\lwip\\port\\ethernetif.c", + "rt-thread\\components\\net\\lwip\\port\\sys_arch.c", + "rt-thread\\components\\net\\lwip\\lwip-2.0.3\\SConscript" + ] + }, + { + "name": "NetUtils", + "path": "packages\\netutils-latest\\ntp", + "files": [ + "packages\\netutils-latest\\ntp\\ntp.c", + "packages\\netutils-latest\\ntp\\SConscript" + ] + }, + { + "name": "perf_counter", + "path": "packages\\perf_counter-v2.2.4.1", + "files": [ + "packages\\perf_counter-v2.2.4.1\\os\\perf_os_patch_rt_thread.c", + "packages\\perf_counter-v2.2.4.1\\perf_counter.c", + "packages\\perf_counter-v2.2.4.1\\SConscript" + ] + }, + { + "name": "POSIX", + "path": "rt-thread\\components\\libc\\posix\\io\\epoll", + "files": [ + "rt-thread\\components\\libc\\posix\\io\\poll\\poll.c", + "rt-thread\\components\\libc\\posix\\io\\poll\\select.c", + "rt-thread\\components\\libc\\posix\\io\\epoll\\SConscript" + ] + }, + { + "name": "RS485_port", + "path": "board\\ports\\rs485", + "files": [ + "board\\ports\\rs485\\drv_rs485.c", + "board\\ports\\rs485\\SConscript" + ] + }, + { + "name": "rt_usbd", + "path": "rt-thread\\components\\legacy\\usb\\usbdevice", + "files": [ + "rt-thread\\components\\legacy\\usb\\usbdevice\\core\\usbdevice.c", + "rt-thread\\components\\legacy\\usb\\usbdevice\\class\\cdc_vcom.c", + "rt-thread\\components\\legacy\\usb\\usbdevice\\core\\usbdevice_core.c", + "rt-thread\\components\\legacy\\usb\\usbdevice\\SConscript" + ] + }, + { + "name": "rw007", + "path": "packages\\rw007-v2.1.0", + "files": [ + "packages\\rw007-v2.1.0\\src\\spi_wifi_rw007.c", + "packages\\rw007-v2.1.0\\example\\rw007_stm32_port.c", + "packages\\rw007-v2.1.0\\SConscript" + ] + }, + { + "name": "SAL", + "path": "rt-thread\\components\\net\\netdev", + "files": [ + "rt-thread\\components\\net\\netdev\\src\\netdev.c", + "rt-thread\\components\\net\\netdev\\src\\netdev_ipaddr.c", + "rt-thread\\components\\net\\sal\\dfs_net\\dfs_net.c", + "rt-thread\\components\\net\\sal\\impl\\af_inet_lwip.c", + "rt-thread\\components\\net\\sal\\socket\\net_netdb.c", + "rt-thread\\components\\net\\sal\\socket\\net_sockets.c", + "rt-thread\\components\\net\\sal\\src\\sal_socket.c", + "rt-thread\\components\\net\\netdev\\SConscript" + ] + }, + { + "name": "Utilities", + "path": "rt-thread\\components\\utilities\\ulog", + "files": [ + "rt-thread\\components\\utilities\\ulog\\backend\\console_be.c", + "rt-thread\\components\\utilities\\ulog\\ulog.c", + "rt-thread\\components\\utilities\\ulog\\SConscript" + ] + }, + { + "name": "vconsole", + "path": "packages\\vconsole-latest", + "files": [ + "packages\\vconsole-latest\\vconsole.c", + "packages\\vconsole-latest\\SConscript" + ] + } + ] +} \ No newline at end of file diff --git a/applications/init.c b/applications/init.c index 26ae60a..2981fd8 100644 --- a/applications/init.c +++ b/applications/init.c @@ -1,9 +1,9 @@ #include "sim.h" #include #include -#include -#include -#include +#include +#include +#include #include #include "my_func.h" diff --git a/board/ports/fal/fal_spi_flash_sfud_port.c b/board/ports/fal/fal_spi_flash_sfud_port.c index 760fbfe..977430f 100644 --- a/board/ports/fal/fal_spi_flash_sfud_port.c +++ b/board/ports/fal/fal_spi_flash_sfud_port.c @@ -12,7 +12,7 @@ #include #ifdef RT_USING_SFUD -#include +#include #endif static int init(void); diff --git a/board/ports/spi_flash_init.c b/board/ports/spi_flash_init.c index 4b1f0f5..56f40fa 100644 --- a/board/ports/spi_flash_init.c +++ b/board/ports/spi_flash_init.c @@ -9,8 +9,8 @@ */ #include -#include "spi_flash.h" -#include "spi_flash_sfud.h" +#include "dev_spi_flash.h" +#include "dev_spi_flash_sfud.h" #include #include diff --git a/libraries/HAL_Drivers/drivers/drv_pwm.c b/libraries/HAL_Drivers/drivers/drv_pwm.c index 478d1d8..d097e68 100644 --- a/libraries/HAL_Drivers/drivers/drv_pwm.c +++ b/libraries/HAL_Drivers/drivers/drv_pwm.c @@ -15,7 +15,7 @@ #ifdef BSP_USING_PWM #include "drv_config.h" #include "drv_tim.h" -#include +#include //#define DRV_DEBUG #define LOG_TAG "drv.pwm" diff --git a/libraries/HAL_Drivers/drivers/drv_sdio.h b/libraries/HAL_Drivers/drivers/drv_sdio.h index 9a122e4..ebd0ff8 100644 --- a/libraries/HAL_Drivers/drivers/drv_sdio.h +++ b/libraries/HAL_Drivers/drivers/drv_sdio.h @@ -17,8 +17,8 @@ #include #include "drv_dma.h" #include -#include -#include +#include +#include #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) #define SDCARD_INSTANCE_TYPE SDIO_TypeDef diff --git a/rt-thread/README.md b/rt-thread/README.md index 070c2fc..f0e7d25 100644 --- a/rt-thread/README.md +++ b/rt-thread/README.md @@ -11,7 +11,8 @@ [![Gitter](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/RT-Thread/rt-thread?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge) [![GitHub pull-requests](https://img.shields.io/github/issues-pr/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/pulls) [![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg?style=flat)](https://github.com/RT-Thread/rt-thread/pulls) - +[![RT-Thread BSP Static Build Check](https://github.com/RT-Thread/rt-thread/actions/workflows/bsp_buildings.yml/badge.svg)](https://github.com/RT-Thread/rt-thread/actions/workflows/bsp_buildings.yml) +Featured｜HelloGitHub # RT-Thread RT-Thread was born in 2006, it is an open source, neutral, and community-based real-time operating system (RTOS). diff --git a/rt-thread/components/dfs/Kconfig b/rt-thread/components/dfs/Kconfig index 2c822cf..9b2f1b4 100644 --- a/rt-thread/components/dfs/Kconfig +++ b/rt-thread/components/dfs/Kconfig @@ -162,20 +162,32 @@ endif bool "Using devfs for device objects" default y - config RT_USING_DFS_ROMFS +if RT_USING_DFS_V1 + config RT_USING_DFS_ISO9660 + bool "Using ISO9660 filesystem" + depends on RT_USING_MEMHEAP + default n +endif + + menuconfig RT_USING_DFS_ROMFS bool "Enable ReadOnly file system on flash" default n - config RT_USING_DFS_ROMFS_USER_ROOT - bool "Use user's romfs root" - depends on RT_USING_DFS_ROMFS - default n + if RT_USING_DFS_ROMFS + config RT_USING_DFS_ROMFS_USER_ROOT + bool "Use user's romfs root" + depends on RT_USING_DFS_V1 + default n + endif if RT_USING_SMART config RT_USING_DFS_PTYFS bool "Using Pseudo-Teletype Filesystem (UNIX98 PTY)" depends on RT_USING_DFS_DEVFS default y + config RT_USING_DFS_PROCFS + bool "Enable proc file system" + default n endif config RT_USING_DFS_CROMFS diff --git a/rt-thread/components/dfs/dfs_v1/SConscript b/rt-thread/components/dfs/dfs_v1/SConscript index 181cf67..42f8b95 100644 --- a/rt-thread/components/dfs/dfs_v1/SConscript +++ b/rt-thread/components/dfs/dfs_v1/SConscript @@ -1,4 +1,6 @@ from building import * +from gcc import * +import rtconfig import os # The set of source files associated with this SConscript file. @@ -6,6 +8,7 @@ src = [] cwd = GetCurrentDir() CPPPATH = [cwd + "/include"] group = [] +LOCAL_CFLAGS = '' if GetDepend('RT_USING_DFS') and not GetDepend('RT_USING_DFS_V2'): src = ['src/dfs.c', 'src/dfs_file.c', 'src/dfs_fs.c'] @@ -13,7 +16,12 @@ if GetDepend('RT_USING_DFS') and not GetDepend('RT_USING_DFS_V2'): if GetDepend('DFS_USING_POSIX'): src += ['src/dfs_posix.c'] - group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS'], CPPPATH = CPPPATH) + if rtconfig.PLATFORM in GetGCCLikePLATFORM(): + LOCAL_CFLAGS += ' -std=c99' + elif rtconfig.PLATFORM in ['armcc']: + LOCAL_CFLAGS += ' --c99' + + group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS'], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS) # search in the file system implementation list = os.listdir(cwd) diff --git a/rt-thread/components/dfs/dfs_v1/filesystems/iso9660/SConscript b/rt-thread/components/dfs/dfs_v1/filesystems/iso9660/SConscript new file mode 100644 index 0000000..d3d8e8c --- /dev/null +++ b/rt-thread/components/dfs/dfs_v1/filesystems/iso9660/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_ISO9660'], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/dfs/dfs_v1/filesystems/iso9660/dfs_iso9660.c b/rt-thread/components/dfs/dfs_v1/filesystems/iso9660/dfs_iso9660.c new file mode 100644 index 0000000..612b68c --- /dev/null +++ b/rt-thread/components/dfs/dfs_v1/filesystems/iso9660/dfs_iso9660.c @@ -0,0 +1,698 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "dfs.iso9660" +#define DBG_LVL DBG_INFO +#include + +#include "dfs_iso9660.h" +#include +#include +#include +#include +#include +#include + +#include + +#define ISO9660_FSTYPE_DIR 0040000 +#define ISO9660_FSTYPE_REG 0100000 +#define ISO9660_FSTYPE_SYMLINK 0120000 +#define ISO9660_FSTYPE_MASK 0170000 + +#define ISO9660_BLKSZ 2048 + +#define ISO9660_VOLDESC_BOOT 0 +#define ISO9660_VOLDESC_PRIMARY 1 +#define ISO9660_VOLDESC_SUPP 2 +#define ISO9660_VOLDESC_PART 3 +#define ISO9660_VOLDESC_END 255 + +rt_packed(struct iso9660_voldesc +{ + rt_uint8_t type; + rt_uint8_t magic[5]; + rt_uint8_t version; +}); + +rt_packed(struct iso9660_date2 +{ + rt_uint8_t year; + rt_uint8_t month; + rt_uint8_t day; + rt_uint8_t hour; + rt_uint8_t minute; + rt_uint8_t second; + rt_uint8_t offset; +}); + +/* Directory entry */ +rt_packed(struct iso9660_dir +{ + rt_uint8_t len; + rt_uint8_t ext_sectors; + rt_le32_t first_sector; + rt_le32_t first_sector_be; + rt_le32_t size; + rt_le32_t size_be; + struct iso9660_date2 mtime; +#define FLAG_TYPE_PLAIN 0 +#define FLAG_TYPE_DIR 2 +#define FLAG_TYPE 3 +#define FLAG_MORE_EXTENTS 0x80 + rt_uint8_t flags; + rt_uint8_t file_unit_size; + rt_uint8_t interleave_gap_size; + rt_le16_t vol_seq_num; + rt_le16_t vol_seq_num_be; +#define MAX_NAMELEN 255 + rt_uint8_t namelen; + char name[0]; +}); + +rt_packed(struct iso9660_date +{ + rt_uint8_t year[4]; + rt_uint8_t month[2]; + rt_uint8_t day[2]; + rt_uint8_t hour[2]; + rt_uint8_t minute[2]; + rt_uint8_t second[2]; + rt_uint8_t hundredth[2]; + rt_uint8_t offset; +}); + +/* Common volume descriptor */ +rt_packed(struct iso9660_common_voldesc +{ + struct iso9660_voldesc voldesc; + rt_uint8_t sysname[33]; + rt_uint8_t volname[32]; + rt_uint8_t unused2[8]; + rt_le32_t vol_space_size_le; + rt_le32_t vol_space_size_be; + rt_uint8_t escape[32]; + rt_le16_t vol_set_size_le; + rt_le16_t vol_set_size_be; + rt_le16_t vol_seq_num_le; + rt_le16_t vol_seq_num_be; + rt_le16_t logical_block_size_le; + rt_le16_t logical_block_size_be; + rt_le32_t path_table_size; + rt_le32_t path_table_size_be; + rt_le32_t path_table; + rt_le32_t path_table_be; + rt_uint8_t unused3[8]; + struct iso9660_dir rootdir; + rt_uint8_t unused4[624]; + struct iso9660_date created; + struct iso9660_date modified; + rt_uint8_t unused5[0 /* 1201 */]; +}); + +struct iso9660 +{ + struct rt_device *dev; + + rt_uint8_t joliet; + rt_uint8_t swap[ISO9660_BLKSZ]; + + struct iso9660_common_voldesc primary, supp; +}; + +struct iso9660_fd +{ + struct iso9660 *iso; + + struct iso9660_dir dirent; +}; + +struct iso9660_iterate +{ + struct iso9660_fd *fd; + + int i, index, count; + struct dirent *dirp; +}; + +static void iso9660_convert_string(char *dest, rt_uint16_t *src, int len) +{ + /* UTF16 to ASCII */ + len >>= 1; + + for (int i = 0; i < len; ++i) + { + rt_uint16_t utf16 = rt_be16_to_cpu(*src++); + + if (utf16 < 0x80) + { + *dest++ = (rt_uint8_t)utf16; + } + else + { + *dest++ = '?'; + } + } + *dest = '\0'; +} + +static void iso9660_convert_lower(char *dest, rt_uint8_t *src, int len) +{ + for (int i = 0; i < len; ++i, ++src) + { + if (*src >= 'A' && *src <= 'Z') + { + *dest++ = *src - ('A' - 'a'); + } + else + { + *dest++ = *src; + } + } + + *dest = '\0'; +} + +static time_t iso9660_convert_unixtime(struct iso9660_date *date) +{ + struct tm tm; + + tm.tm_sec = (date->second[0] - '0') * 10 + (date->second[1] - '0'); + tm.tm_min = (date->minute[0] - '0') * 10 + (date->minute[1] - '0'); + tm.tm_hour = (date->hour[0] - '0') * 10 + (date->hour[1] - '0'); + tm.tm_mday = (date->day[0] - '0') * 10 + (date->day[1] - '0'); + tm.tm_mon = (date->month[0] - '0') * 10 + (date->month[1] - '0'); + tm.tm_year = (date->year[0] - '0') * 1000 + (date->year[1] - '0') * 100 + + (date->year[2] - '0') * 10 + (date->year[3] - '0'); + tm.tm_wday = 0; + + return mktime(&tm); +} + +static time_t iso9660_convert_unixtime2(struct iso9660_date2 *date) +{ + struct tm tm; + + tm.tm_sec = date->second; + tm.tm_min = date->minute; + tm.tm_hour = date->hour; + tm.tm_mday = date->day; + tm.tm_mon = date->month; + tm.tm_year = date->year + 1900; + tm.tm_wday = 0; + + return mktime(&tm); +} + +static struct iso9660_fd *iso9660_lookup(struct iso9660 *iso, const char *path, + struct iso9660_iterate *it) +{ + rt_uint32_t lba; + rt_size_t sz, len, namelen; + char sname[MAX_NAMELEN]; + struct iso9660_fd *fd; + struct iso9660_dir *dirent; + + if (it) + { + fd = it->fd; + iso = fd->iso; + dirent = &fd->dirent; + + /* No next entry, always goon */ + len = 1; + } + else + { + if (!(fd = rt_malloc(sizeof(*fd)))) + { + return fd; + } + + fd->iso = iso; + dirent = iso->joliet ? &iso->supp.rootdir : &iso->primary.rootdir; + + if (!rt_strcmp(path, "/")) + { + rt_memcpy(&fd->dirent, dirent, sizeof(*dirent)); + return fd; + } + + /* Skip the first '/' */ + ++path; + len = strchrnul(path, '/') - path; + } + + lba = rt_le32_to_cpu(dirent->first_sector); + if (rt_device_read(iso->dev, lba, iso->swap, 1) <= 0) + { + goto _fail; + } + dirent = (void *)iso->swap; + sz = 0; + + do { + /* Ignore "." and ".." */ + do { + rt_uint32_t dlen = rt_le32_to_cpu(dirent->len); + + dirent = (void *)dirent + dlen; + sz += dlen; + + if (ISO9660_BLKSZ - sz < sizeof(*dirent)) + { + /* Sector end, goto the next sector */ + if (rt_device_read(iso->dev, ++lba, iso->swap, 1) <= 0) + { + goto _fail; + } + dirent = (void *)iso->swap; + sz = 0; + } + + if (rt_le32_to_cpu(dirent->first_sector) == 0) + { + /* Is end, no found. */ + goto _fail; + } + } while (dirent->name[0] >> 1 == 0 && rt_le32_to_cpu(dirent->namelen) == 1); + + namelen = rt_le32_to_cpu(dirent->namelen); + + if (iso->joliet) + { + iso9660_convert_string(sname, (rt_uint16_t *)dirent->name, namelen); + } + else + { + if (!(rt_le32_to_cpu(dirent->flags) & FLAG_TYPE_DIR)) + { + /* Remove ";1" */ + namelen -= 2; + } + + iso9660_convert_lower(sname, (rt_uint8_t *)dirent->name, namelen); + } + + if (it) + { + if (it->i < it->index) + { + goto _next; + } + + if ((rt_le32_to_cpu(dirent->flags) & FLAG_TYPE) == FLAG_TYPE_DIR) + { + it->dirp->d_type = DT_DIR; + } + else + { + it->dirp->d_type = DT_REG; + } + + it->dirp->d_namlen = namelen; + rt_strncpy(it->dirp->d_name, sname, namelen); + it->dirp->d_name[namelen] = '\0'; + it->dirp->d_reclen = (rt_uint16_t)sizeof(struct dirent); + + ++it->dirp; + + _next: + ++it->i; + + if (it->i - it->index >= it->count) + { + /* Iterate end */ + return RT_NULL; + } + + /* No next entry */ + continue; + } + + if (!rt_strncmp(sname, path, len)) + { + /* The end of path, found ok */ + if (!path[len]) + { + rt_memcpy(&fd->dirent, dirent, sizeof(*dirent)); + return fd; + } + + /* Next entry */ + lba = rt_le32_to_cpu(dirent->first_sector); + if (rt_device_read(iso->dev, lba, iso->swap, 1) <= 0) + { + goto _fail; + } + dirent = (void *)iso->swap; + sz = 0; + + path += len + 1; + len = strchrnul(path, '/') - path; + } + } while (len); + +_fail: + if (!it) + { + rt_free(fd); + } + + return RT_NULL; +} + +static int dfs_iso9660_open(struct dfs_file *fd) +{ + struct iso9660 *iso = fd->vnode->fs->data; + + fd->vnode->data = iso9660_lookup(iso, fd->vnode->path, RT_NULL); + + return fd->vnode->data ? 0 : -EINVAL; +} + +static int dfs_iso9660_close(struct dfs_file *fd) +{ + struct iso9660_fd *iso_fd = fd->vnode->data; + + rt_free(iso_fd); + + return 0; +} + +static int dfs_iso9660_read(struct dfs_file *fd, void *buf, size_t count) +{ + rt_uint32_t pos; + void *buf_ptr; + ssize_t read_blk, toread_blk; + size_t rcount = 0, remain, size; + struct iso9660_fd *iso_fd = fd->vnode->data; + struct iso9660 *iso = iso_fd->iso; + + if (fd->pos + count > rt_le32_to_cpu(iso_fd->dirent.size)) + { + count = rt_le32_to_cpu(iso_fd->dirent.size) - fd->pos; + } + pos = rt_le32_to_cpu(iso_fd->dirent.first_sector); + + /* Align to a sector */ + if (fd->pos) + { + pos += fd->pos / ISO9660_BLKSZ; + remain = fd->pos & (ISO9660_BLKSZ - 1); + + if (rt_device_read(iso->dev, pos, iso->swap, 1) <= 0) + { + return -EIO; + } + + size = rt_min_t(size_t, ISO9660_BLKSZ - remain, count); + rt_memcpy(buf, &iso->swap[remain], size); + rcount += size; + count -= size; + buf += size; + pos += 1; + fd->pos += size; + + if (!count) + { + goto _end; + } + } + + remain = count & (ISO9660_BLKSZ - 1); + count = rt_max_t(size_t, count / ISO9660_BLKSZ, 1); + + while ((ssize_t)count > 0) + { + if (count == 1) + { + buf_ptr = iso->swap; + toread_blk = 1; + } + else + { + buf_ptr = buf; + toread_blk = count; + } + + read_blk = rt_device_read(iso->dev, pos, buf_ptr, toread_blk); + + if (read_blk <= 0) + { + return (int)read_blk; + } + + if (count == 1) + { + size = remain; + rt_memcpy(buf, iso->swap, size); + } + else + { + size = read_blk * ISO9660_BLKSZ; + } + + rcount += size; + count -= read_blk; + buf += size; + pos += read_blk; + fd->pos += size; + } + +_end: + return rcount; +} + +static off_t dfs_iso9660_lseek(struct dfs_file *fd, off_t offset) +{ + int ret = -EIO; + + if (offset <= fd->vnode->size) + { + fd->pos = offset; + ret = fd->pos; + } + + return ret; +} + +static int dfs_iso9660_getdents(struct dfs_file *fd, struct dirent *dirp, uint32_t count) +{ + struct iso9660_iterate it; + struct iso9660_fd *iso_fd = fd->vnode->data; + + count = (count / sizeof(struct dirent)); + + if (!count) + { + return -EINVAL; + } + + it.fd = iso_fd; + it.i = 0; + it.index = fd->pos; + it.count = count; + it.dirp = dirp; + + iso9660_lookup(RT_NULL, RT_NULL, &it); + + count = it.i - it.index; + if (count > 0) + { + fd->pos += count; + } + + count *= sizeof(struct dirent); + + return count; +} + +static const struct dfs_file_ops _iso9660_fops = +{ + .open = dfs_iso9660_open, + .close = dfs_iso9660_close, + .read = dfs_iso9660_read, + .lseek = dfs_iso9660_lseek, + .getdents = dfs_iso9660_getdents, +}; + +static int dfs_iso9660_mount(struct dfs_filesystem *fs, + unsigned long rwflag, const void *data) +{ + int err; + struct iso9660 *iso; + struct iso9660_voldesc *voldesc; + struct rt_device_blk_geometry geometry; + + if (!(iso = rt_malloc(sizeof(*iso)))) + { + return -RT_ENOMEM; + } + + iso->dev = fs->dev_id; + rt_device_control(iso->dev, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); + + if (geometry.bytes_per_sector != ISO9660_BLKSZ) + { + LOG_E("%s: Logical block size = %d is not supported", + iso->dev->parent.name, geometry.bytes_per_sector); + + err = -EINVAL; + goto _fail; + } + + iso->primary.rootdir.first_sector = 0; + iso->supp.rootdir.first_sector = 0; + + /* LBA 0-15 is the bootloader's information */ + for (int lba = 16; ; ++lba) + { + if (rt_device_read(iso->dev, lba, &iso->swap, 1) <= 0) + { + err = -EIO; + goto _fail; + } + + voldesc = (void *)iso->swap; + + if (rt_strncmp((char *)voldesc->magic, "CD001", 5)) + { + LOG_E("%s: Invalid magic \"%s\"", voldesc->magic); + + err = -EINVAL; + goto _fail; + } + + if (voldesc->type == ISO9660_VOLDESC_BOOT) + { + LOG_D("System Name: %s", ((struct iso9660_common_voldesc *)voldesc)->sysname); + LOG_D("Volume Name: %s", ((struct iso9660_common_voldesc *)voldesc)->volname); + } + else if (voldesc->type == ISO9660_VOLDESC_PRIMARY) + { + iso->joliet = 0; + rt_memcpy(&iso->primary, &iso->swap, sizeof(iso->primary)); + } + else if (voldesc->type == ISO9660_VOLDESC_SUPP) + { + rt_memcpy(&iso->supp, &iso->swap, sizeof(iso->supp)); + + if (iso->supp.escape[0] == 0x25 && iso->supp.escape[1] == 0x2f) + { + if (iso->supp.escape[2] == 0x40) + { + iso->joliet = 1; + } + else if (iso->supp.escape[2] == 0x43) + { + iso->joliet = 2; + } + else if (iso->supp.escape[2] == 0x45) + { + iso->joliet = 3; + } + else + { + continue; + } + } + } + else if (voldesc->type == ISO9660_VOLDESC_PART) + { + LOG_D("System Name: %s", ((struct iso9660_common_voldesc *)voldesc)->sysname); + LOG_D("Volume Name: %s", ((struct iso9660_common_voldesc *)voldesc)->volname); + } + else if (voldesc->type == ISO9660_VOLDESC_END) + { + break; + } + } + + if (!iso->primary.rootdir.first_sector || !iso->supp.rootdir.first_sector) + { + LOG_E("No primary or secondary partition found"); + + err = -EINVAL; + goto _fail; + } + + fs->data = iso; + + return 0; + +_fail: + rt_free(iso); + + return err; +} + +static int dfs_iso9660_unmount(struct dfs_filesystem *fs) +{ + struct iso9660 *iso = fs->data; + + rt_free(iso); + + return 0; +} + +static int dfs_iso9660_stat(struct dfs_filesystem *fs, + const char *filename, struct stat *st) +{ + struct iso9660 *iso = fs->data; + struct iso9660_fd *fd = iso9660_lookup(iso, filename, RT_NULL); + + if (!fd) + { + return -EINVAL; + } + + st->st_dev = 0; + st->st_mode = S_IFREG | S_IRUSR | S_IRGRP | S_IROTH | + S_IWUSR | S_IWGRP | S_IWOTH; + + if ((fd->dirent.flags & FLAG_TYPE) == FLAG_TYPE_DIR) + { + st->st_mode &= ~S_IFREG; + st->st_mode |= S_IFDIR | S_IXUSR | S_IXGRP | S_IXOTH; + } + + st->st_atime = iso9660_convert_unixtime(iso->joliet ? + &iso->supp.created : &iso->primary.created); + st->st_mtime = iso9660_convert_unixtime2(&fd->dirent.mtime); + st->st_size = rt_le32_to_cpu(fd->dirent.size); + + rt_free(fd); + + return 0; +} + +static const struct dfs_filesystem_ops _iso9660 = +{ + .name = "iso9660", + .flags = DFS_FS_FLAG_DEFAULT, + .fops = &_iso9660_fops, + + .mount = dfs_iso9660_mount, + .unmount = dfs_iso9660_unmount, + + .stat = dfs_iso9660_stat, +}; + +int dfs_iso9660_init(void) +{ + /* register iso9660 file system */ + return dfs_register(&_iso9660); +} +INIT_COMPONENT_EXPORT(dfs_iso9660_init); diff --git a/rt-thread/components/dfs/dfs_v1/filesystems/iso9660/dfs_iso9660.h b/rt-thread/components/dfs/dfs_v1/filesystems/iso9660/dfs_iso9660.h new file mode 100644 index 0000000..d4e524e --- /dev/null +++ b/rt-thread/components/dfs/dfs_v1/filesystems/iso9660/dfs_iso9660.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#ifndef __DFS_ISO9660_H__ +#define __DFS_ISO9660_H__ + +int dfs_iso9660_init(void); + +#endif /* __DFS_ISO9660_H__ */ diff --git a/rt-thread/components/dfs/dfs_v1/filesystems/ramfs/dfs_ramfs.c b/rt-thread/components/dfs/dfs_v1/filesystems/ramfs/dfs_ramfs.c index fd7326b..92807a2 100644 --- a/rt-thread/components/dfs/dfs_v1/filesystems/ramfs/dfs_ramfs.c +++ b/rt-thread/components/dfs/dfs_v1/filesystems/ramfs/dfs_ramfs.c @@ -92,7 +92,7 @@ struct ramfs_dirent *dfs_ramfs_lookup(struct dfs_ramfs *ramfs, return NULL; } -int dfs_ramfs_read(struct dfs_file *file, void *buf, size_t count) +ssize_t dfs_ramfs_read(struct dfs_file *file, void *buf, size_t count) { rt_size_t length; struct ramfs_dirent *dirent; @@ -114,7 +114,7 @@ int dfs_ramfs_read(struct dfs_file *file, void *buf, size_t count) return length; } -int dfs_ramfs_write(struct dfs_file *fd, const void *buf, size_t count) +ssize_t dfs_ramfs_write(struct dfs_file *fd, const void *buf, size_t count) { struct ramfs_dirent *dirent; struct dfs_ramfs *ramfs; @@ -151,7 +151,7 @@ int dfs_ramfs_write(struct dfs_file *fd, const void *buf, size_t count) return count; } -int dfs_ramfs_lseek(struct dfs_file *file, off_t offset) +off_t dfs_ramfs_lseek(struct dfs_file *file, off_t offset) { if (offset <= (off_t)file->vnode->size) { diff --git a/rt-thread/components/dfs/dfs_v1/src/dfs.c b/rt-thread/components/dfs/dfs_v1/src/dfs.c index 8d2e9b1..fdaf93d 100644 --- a/rt-thread/components/dfs/dfs_v1/src/dfs.c +++ b/rt-thread/components/dfs/dfs_v1/src/dfs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -107,7 +107,8 @@ int dfs_init(void) INIT_PREV_EXPORT(dfs_init); /** - * this function will lock device file system. + * @brief this function will lock device file system. + * this lock (fslock) is used for protecting filesystem_operation_table and filesystem_table. * * @note please don't invoke it on ISR. */ @@ -126,6 +127,12 @@ void dfs_lock(void) } } +/** + * @brief this function will lock file descriptors. + * this lock (fdlock) is used for protecting fd table (_fdtab). + * + * @note please don't invoke it on ISR. + */ void dfs_file_lock(void) { rt_err_t result = -RT_EBUSY; @@ -142,7 +149,7 @@ void dfs_file_lock(void) } /** - * this function will lock device file system. + * @brief this function will unlock device file system. * * @note please don't invoke it on ISR. */ @@ -151,33 +158,56 @@ void dfs_unlock(void) rt_mutex_release(&fslock); } -#ifdef DFS_USING_POSIX - +/** + * @brief this function will unlock fd table. + */ void dfs_file_unlock(void) { rt_mutex_release(&fdlock); } +#ifdef DFS_USING_POSIX +/** + * @brief Expand the file descriptor table to accommodate a specific file descriptor. + * + * This function ensures that the file descriptor table in the given `dfs_fdtable` structure + * has sufficient capacity to include the specified file descriptor `fd`. If the table + * needs to be expanded, it reallocates memory and initializes new slots to `NULL`. + * + * @param fdt Pointer to the `dfs_fdtable` structure representing the file descriptor table. + * @param fd The file descriptor that the table must accommodate. + * @return int + * - The input file descriptor `fd` if it is within the current or newly expanded table's capacity. + * - `-1` if the requested file descriptor exceeds `DFS_FD_MAX` or memory allocation fails. + */ static int fd_slot_expand(struct dfs_fdtable *fdt, int fd) { int nr; int index; struct dfs_file **fds = NULL; + /* If the file descriptor is already within the current capacity, no expansion is needed.*/ if (fd < fdt->maxfd) { return fd; } + + /* If the file descriptor exceeds the maximum allowable limit, return an error.*/ if (fd >= DFS_FD_MAX) { return -1; } + /* Calculate the new capacity, rounding up to the nearest multiple of 4.*/ nr = ((fd + 4) & ~3); + + /* Ensure the new capacity does not exceed the maximum limit.*/ if (nr > DFS_FD_MAX) { nr = DFS_FD_MAX; } + + /* Attempt to reallocate the file descriptor table to the new capacity.*/ fds = (struct dfs_file **)rt_realloc(fdt->fds, nr * sizeof(struct dfs_file *)); if (!fds) { @@ -189,12 +219,23 @@ static int fd_slot_expand(struct dfs_fdtable *fdt, int fd) { fds[index] = NULL; } + + /* Update the file descriptor table and its capacity.*/ fdt->fds = fds; fdt->maxfd = nr; return fd; } +/** + * @brief Allocate a file descriptor slot starting from a specified index. + * + * @param fdt fdt Pointer to the `dfs_fdtable` structure representing the file descriptor table. + * @param startfd The starting index for the search for an empty slot. + * @return int + * - The index of the first available slot if successful. + * - `-1` if no slot is available or if table expansion fails + */ static int fd_slot_alloc(struct dfs_fdtable *fdt, int startfd) { int idx; @@ -219,6 +260,17 @@ static int fd_slot_alloc(struct dfs_fdtable *fdt, int startfd) } return idx; } + +/** + * @brief Allocate a new file descriptor and associate it with a newly allocated `struct dfs_file`. + * + * @param fdt Pointer to the `dfs_fdtable` structure representing the file descriptor table. + * @param startfd The starting index for searching an available file descriptor slot. + * + * @return + * - The index of the allocated file descriptor if successful. + * - `-1` if no slot is available or memory allocation fails. + */ static int fd_alloc(struct dfs_fdtable *fdt, int startfd) { int idx; @@ -323,7 +375,11 @@ struct dfs_file *fd_get(int fd) /** * @ingroup Fd * - * This function will put the file descriptor. + * @brief This function will release the file descriptor. + * + * This function releases a file descriptor slot in the file descriptor table, decrements reference + * counts, and cleans up resources associated with the `dfs_file` and `dfs_vnode` structures when applicable. + * */ void fdt_fd_release(struct dfs_fdtable* fdt, int fd) { @@ -378,6 +434,20 @@ void fd_release(int fd) fdt_fd_release(fdt, fd); } +/** + * @brief Duplicates a file descriptor. + * + * This function duplicates an existing file descriptor (`oldfd`) and returns + * a new file descriptor that refers to the same underlying file object. + * + * @param oldfd The file descriptor to duplicate. It must be a valid file + * descriptor within the range of allocated descriptors. + * + * @return The new file descriptor if successful, or a negative value + * (e.g., -1) if an error occurs. + * + * @see sys_dup2() + */ rt_err_t sys_dup(int oldfd) { int newfd = -1; @@ -470,6 +540,23 @@ int fd_is_open(const char *pathname) return -1; } +/** + * @brief Duplicates a file descriptor to a specified file descriptor. + * + * This function duplicates an existing file descriptor (`oldfd`) and assigns it + * to the specified file descriptor (`newfd`). + * + * @param oldfd The file descriptor to duplicate. It must be a valid and open file + * descriptor within the range of allocated descriptors. + * @param newfd The target file descriptor. If `newfd` is already in use, it will + * be closed before duplication. If `newfd` exceeds the current file + * descriptor table size, the table will be expanded to accommodate it. + * + * @return The value of `newfd` on success, or a negative value (e.g., -1) if an + * error occurs. + * + * @see sys_dup() + */ rt_err_t sys_dup2(int oldfd, int newfd) { struct dfs_fdtable *fdt = NULL; @@ -550,6 +637,10 @@ static int fd_get_fd_index_form_fdt(struct dfs_fdtable *fdt, struct dfs_file *fi return fd; } +/** + * @brief get fd (index) by dfs file object. + * + */ int fd_get_fd_index(struct dfs_file *file) { struct dfs_fdtable *fdt; @@ -558,6 +649,21 @@ int fd_get_fd_index(struct dfs_file *file) return fd_get_fd_index_form_fdt(fdt, file); } +/** + * @brief Associates a file descriptor with a file object. + * + * This function associates a given file descriptor (`fd`) with a specified + * file object (`file`) in the file descriptor table (`fdt`). + * + * @param fdt The file descriptor table to operate on. It must be a valid + * and initialized `dfs_fdtable` structure. + * @param fd The file descriptor to associate. It must be within the range + * of allocated file descriptors and currently unoccupied. + * @param file The file object to associate with the file descriptor. It must + * be a valid and initialized `dfs_file` structure. + * + * @return The value of `fd` on success, or -1 if an error occurs. + */ int fd_associate(struct dfs_fdtable *fdt, int fd, struct dfs_file *file) { int retfd = -1; @@ -591,6 +697,10 @@ exit: return retfd; } +/** + * @brief initialize a dfs file object. + * + */ void fd_init(struct dfs_file *fd) { if (fd) diff --git a/rt-thread/components/dfs/dfs_v1/src/dfs_file.c b/rt-thread/components/dfs/dfs_v1/src/dfs_file.c index acdc124..be5747a 100644 --- a/rt-thread/components/dfs/dfs_v1/src/dfs_file.c +++ b/rt-thread/components/dfs/dfs_v1/src/dfs_file.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,10 +18,12 @@ #define DFS_VNODE_HASH_NR 128 +/*dfs vnode manager, for saving and searching vnodes.*/ struct dfs_vnode_mgr { - struct rt_mutex lock; - rt_list_t head[DFS_VNODE_HASH_NR]; + struct rt_mutex lock; /* mutex for protecting dfs vnode lists */ + rt_list_t head[DFS_VNODE_HASH_NR]; /* a group of dfs vnode lists, the dfs vnode is inserted to one of the lists + according to path string's hash-value mod DFS_VNODE_HASH_NR. */ }; static struct dfs_vnode_mgr dfs_fm; @@ -36,6 +38,10 @@ void dfs_fm_unlock(void) rt_mutex_release(&dfs_fm.lock); } +/** + * @brief Initialize dfs vnode manager structure, including a lock and hash tables for vnode. + * + */ void dfs_vnode_mgr_init(void) { int i = 0; @@ -47,6 +53,23 @@ void dfs_vnode_mgr_init(void) } } +/** + * @brief Initialize a DFS vnode structure. + * + * @param vnode Pointer to the DFS vnode structure to be initialized. + * The caller must ensure this is a valid, allocated structure. + * @param type The type of the vnode, representing its role or category (e.g., regular file, directory). + * @param fops Pointer to the file operations structure associated with this vnode. + * This structure defines the behavior of the vnode for operations such as open, read, write, etc. + * If `fops` is NULL, the vnode will have no associated file operations. + * + * @return 0 on success, or a negative error code on failure. + * + * @note The caller should ensure that: + * - The `vnode` pointer is valid and properly allocated. + * - The `fops` pointer (if not NULL) points to a valid `struct dfs_file_ops` + * instance, where all necessary function pointers are properly set. + */ int dfs_vnode_init(struct dfs_vnode *vnode, int type, const struct dfs_file_ops *fops) { if (vnode) @@ -64,7 +87,7 @@ int dfs_vnode_init(struct dfs_vnode *vnode, int type, const struct dfs_file_ops /* BKDR Hash Function */ static unsigned int bkdr_hash(const char *str) { - unsigned int seed = 131; // 31 131 1313 13131 131313 etc.. + unsigned int seed = 131; /* 31 131 1313 13131 131313 etc..*/ unsigned int hash = 0; while (*str) @@ -75,6 +98,22 @@ static unsigned int bkdr_hash(const char *str) return (hash % DFS_VNODE_HASH_NR); } +/** + * @brief Find a DFS vnode by its path. + * + * This function searches for a vnode in the vnode hash table using the specified path. + * If found, it returns a pointer to the vnode and updates the hash head if required. + * + * @param path The file path to search for. This should be a valid null-terminated string. + * @param hash_head Pointer to a location where the hash table head associated with the vnode + * can be stored. This can be NULL if the hash head is not needed. + * + * @return Pointer to the DFS vnode if found, or NULL if no vnode matches the specified path. + * + * @note The caller must ensure that: + * - The `path` pointer is valid and points to a properly null-terminated string. + * - If `hash_head` is not NULL, it points to a valid location to store the hash head. + */ static struct dfs_vnode *dfs_vnode_find(const char *path, rt_list_t **hash_head) { struct dfs_vnode *vnode = NULL; @@ -329,11 +368,12 @@ int dfs_file_close(struct dfs_file *fd) } /** - * this function will perform a io control on a file descriptor. + * this function will perform an io control on a file descriptor. * * @param fd the file descriptor. * @param cmd the command to send to file descriptor. * @param args the argument to send to file descriptor. + * - When `cmd` is `F_SETFL`, an additional integer argument specifies the new status flags. * * @return 0 on successful, -1 on failed. */ @@ -846,7 +886,7 @@ void cat(const char *filename) { buffer[length] = '\0'; rt_device_t out_device = rt_console_get_device(); - rt_device_write(out_device, 0, (void *)buffer, sizeof(buffer)); + rt_device_write(out_device, 0, (void *)buffer, length); } } while (length > 0); rt_kprintf("\n"); @@ -1026,14 +1066,14 @@ void copy(const char *src, const char *dst) flag |= FLAG_DST_IS_FILE; } - //2. check status + /*2. check status*/ if ((flag & FLAG_SRC_IS_DIR) && (flag & FLAG_DST_IS_FILE)) { rt_kprintf("cp faild, cp dir to file is not permitted!\n"); return ; } - //3. do copy + /*3. do copy*/ if (flag & FLAG_SRC_IS_FILE) { if (flag & FLAG_DST_IS_DIR) @@ -1053,7 +1093,7 @@ void copy(const char *src, const char *dst) copyfile(src, dst); } } - else //flag & FLAG_SRC_IS_DIR + else /*flag & FLAG_SRC_IS_DIR*/ { if (flag & FLAG_DST_IS_DIR) { diff --git a/rt-thread/components/dfs/dfs_v1/src/dfs_fs.c b/rt-thread/components/dfs/dfs_v1/src/dfs_fs.c index 4240736..3d35c5f 100644 --- a/rt-thread/components/dfs/dfs_v1/src/dfs_fs.c +++ b/rt-thread/components/dfs/dfs_v1/src/dfs_fs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -322,8 +322,8 @@ int dfs_mount(const char *device_name, /* open device, but do not check the status of device */ if (dev_id != NULL) { - if (rt_device_open(fs->dev_id, - RT_DEVICE_OFLAG_RDWR) != RT_EOK) + if (rt_device_open(fs->dev_id, RT_DEVICE_OFLAG_RDWR) != RT_EOK && + rt_device_open(fs->dev_id, RT_DEVICE_OFLAG_RDONLY) != RT_EOK) { /* The underlying device has error, clear the entry. */ dfs_lock(); @@ -529,7 +529,8 @@ int dfs_mount_device(rt_device_t dev) { int index = 0; - if(dev == RT_NULL) { + if(dev == RT_NULL) + { rt_kprintf("the device is NULL to be mounted.\n"); return -RT_ERROR; } @@ -538,7 +539,8 @@ int dfs_mount_device(rt_device_t dev) { if (mount_table[index].path == NULL) break; - if(strcmp(mount_table[index].device_name, dev->parent.name) == 0) { + if(strcmp(mount_table[index].device_name, dev->parent.name) == 0) + { if (dfs_mount(mount_table[index].device_name, mount_table[index].path, mount_table[index].filesystemtype, diff --git a/rt-thread/components/dfs/dfs_v1/src/dfs_posix.c b/rt-thread/components/dfs/dfs_v1/src/dfs_posix.c index 07276a8..d4ac04a 100644 --- a/rt-thread/components/dfs/dfs_v1/src/dfs_posix.c +++ b/rt-thread/components/dfs/dfs_v1/src/dfs_posix.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,7 +28,17 @@ * return a file descriptor according specified flags. * * @param file the path name of file. - * @param flags the file open flags. + * @param flags the file open flags. Common values include: + * - Access modes (mutually exclusive): + * - `O_RDONLY`: Open for read-only access. + * - `O_WRONLY`: Open for write-only access. + * - `O_RDWR`: Open for both reading and writing. + * - File status flags (can be combined with bitwise OR `|`): + * - `O_CREAT`: Create the file if it does not exist. Requires a `mode` argument. + * - `O_TRUNC`: Truncate the file to zero length if it already exists. + * - `O_APPEND`: Append writes to the end of the file. + * - `O_EXCL`: Ensure that `O_CREAT` creates the file exclusively. + * - Other platform-specific flags * * @return the non-negative integer on successful open, others for failed. */ @@ -65,6 +75,22 @@ RTM_EXPORT(open); #ifndef AT_FDCWD #define AT_FDCWD (-100) #endif + +/** + * @brief Opens a file relative to a directory file descriptor. + * + * @param dirfd The file descriptor of the directory to base the relative path on. + * @param pathname The path to the file to be opened, relative to the directory specified by `dirfd`. + * Can be an absolute path (in which case `dirfd` is ignored). + * @param flags File access and status flags (e.g., `O_RDONLY`, `O_WRONLY`, `O_CREAT`). + * + * @return On success, returns a new file descriptor for the opened file. + * On failure, returns `-1` and sets `errno` to indicate the error. + * + * @note When using relative paths, ensure `dirfd` is a valid directory descriptor. + * When `pathname` is absolute, the `dirfd` argument is ignored. + * + */ int openat(int dirfd, const char *path, int flag, ...) { struct dfs_file *d; @@ -241,14 +267,22 @@ ssize_t write(int fd, const void *buf, size_t len) RTM_EXPORT(write); /** - * this function is a POSIX compliant version, which will seek the offset for + * this function is a POSIX compliant version, which will Reposition the file offset for * an open file descriptor. * - * @param fd the file descriptor. - * @param offset the offset to be seeked. - * @param whence the directory of seek. + * The `lseek` function sets the file offset for the file descriptor `fd` + * to a new value, determined by the `offset` and `whence` parameters. + * It can be used to seek to specific positions in a file for reading or writing. * - * @return the current read/write position in the file, or -1 on failed. + * @param fd the file descriptor. + * @param offset The offset, in bytes, to set the file position. + * The meaning of `offset` depends on the value of `whence`. + * @param whence the directive of seek. It can be one of: + * - `SEEK_SET`: Set the offset to `offset` bytes from the beginning of the file. + * - `SEEK_CUR`: Set the offset to its current location plus `offset` bytes. + * - `SEEK_END`: Set the offset to the size of the file plus `offset` bytes. + * + * @return the resulting read/write position in the file, or -1 on failed. */ off_t lseek(int fd, off_t offset, int whence) { @@ -436,9 +470,15 @@ RTM_EXPORT(fsync); * control functions on devices. * * @param fildes the file description - * @param cmd the specified command + * @param cmd the specified command, Common values include: + * - `F_DUPFD`: Duplicate a file descriptor. + * - `F_GETFD`: Get the file descriptor flags. + * - `F_SETFD`: Set the file descriptor flags. + * - `F_GETFL`: Get the file status flags. + * - `F_SETFL`: Set the file status flags. * @param ... represents the additional information that is needed by this - * specific device to perform the requested function. + * specific device to perform the requested function. For example: + * - When `cmd` is `F_SETFL`, an additional integer argument specifies the new status flags. * * @return 0 on successful completion. Otherwise, -1 shall be returned and errno * set to indicate the error. @@ -595,7 +635,7 @@ RTM_EXPORT(fstatfs); * this function is a POSIX compliant version, which will make a directory * * @param path the directory path to be made. - * @param mode + * @param mode The permission mode for the new directory (unused here, can be set to 0). * * @return 0 on successful, others on failed. */ diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c b/rt-thread/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c index 0d82914..ae67887 100644 --- a/rt-thread/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c +++ b/rt-thread/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c @@ -786,18 +786,18 @@ static ssize_t dfs_cromfs_read(struct dfs_file *file, void *buf, size_t count, o rt_err_t result = RT_EOK; file_info *fi = NULL; cromfs_info *ci = NULL; - uint32_t length = 0; + ssize_t length = 0; ci = (cromfs_info *)file->dentry->mnt->data; fi = (file_info *)file->vnode->data; - if (count < file->vnode->size - *pos) + if ((off_t)count < (off_t)file->vnode->size - *pos) { length = count; } else { - length = file->vnode->size - *pos; + length = (off_t)file->vnode->size - *pos; } if (length > 0) diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.h b/rt-thread/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.h index 97339bc..a22bd5e 100644 --- a/rt-thread/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.h +++ b/rt-thread/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.h @@ -11,6 +11,9 @@ #ifndef __DFS_CROMFS_H__ #define __DFS_CROMFS_H__ +#include + int dfs_cromfs_init(void); +uint8_t *cromfs_get_partition_data(uint32_t *len); #endif /*__DFS_CROMFS_H__*/ diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/devfs/devfs.c b/rt-thread/components/dfs/dfs_v2/filesystems/devfs/devfs.c index 6db468f..38e9a2e 100644 --- a/rt-thread/components/dfs/dfs_v2/filesystems/devfs/devfs.c +++ b/rt-thread/components/dfs/dfs_v2/filesystems/devfs/devfs.c @@ -77,6 +77,7 @@ static int dfs_devfs_open(struct dfs_file *file) } } } + rt_free(device_name); } return ret; @@ -113,6 +114,29 @@ static int dfs_devfs_close(struct dfs_file *file) return ret; } +static rt_ubase_t _get_unit_shift(rt_device_t device) +{ + rt_ubase_t shift = 0; + + /** + * transfer unit size from POSIX RW(in bytes) to rt_device_R/W + * (block size for blk device, otherwise in bytes). + */ + if (device->type == RT_Device_Class_Block) + { + struct rt_device_blk_geometry geometry = {0}; + + /* default to 512 */ + shift = 9; + if (!rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry)) + { + shift = __rt_ffs(geometry.block_size) - 1; + } + } + + return shift; +} + static ssize_t dfs_devfs_read(struct dfs_file *file, void *buf, size_t count, off_t *pos) { ssize_t ret = -RT_EIO; @@ -135,9 +159,14 @@ static ssize_t dfs_devfs_read(struct dfs_file *file, void *buf, size_t count, of if (device->ops) #endif /* RT_USING_POSIX_DEVIO */ { - /* read device data */ - ret = rt_device_read(device, *pos, buf, count); - *pos += ret; + rt_ubase_t shift = _get_unit_shift(device); + + ret = rt_device_read(device, *pos, buf, count >> shift); + if (ret > 0) + { + ret <<= shift; + *pos += ret; + } } } @@ -169,9 +198,15 @@ static ssize_t dfs_devfs_write(struct dfs_file *file, const void *buf, size_t co if (device->ops) #endif /* RT_USING_POSIX_DEVIO */ { + rt_ubase_t shift = _get_unit_shift(device); + /* read device data */ - ret = rt_device_write(device, *pos, buf, count); - *pos += ret; + ret = rt_device_write(device, *pos, buf, count >> shift); + if (ret > 0) + { + ret <<= shift; + *pos += ret; + } } } @@ -265,7 +300,7 @@ static int dfs_devfs_flush(struct dfs_file *file) static off_t dfs_devfs_lseek(struct dfs_file *file, off_t offset, int wherece) { - off_t ret = 0; + off_t ret = -EPERM; rt_device_t device; RT_ASSERT(file != RT_NULL); @@ -408,16 +443,16 @@ mode_t dfs_devfs_device_to_mode(struct rt_device *device) switch (device->type) { case RT_Device_Class_Char: - mode = S_IFCHR | 0777; + mode = S_IFCHR | 0666; break; case RT_Device_Class_Block: - mode = S_IFBLK | 0777; + mode = S_IFBLK | 0666; break; case RT_Device_Class_Pipe: - mode = S_IFIFO | 0777; + mode = S_IFIFO | 0666; break; default: - mode = S_IFCHR | 0777; + mode = S_IFCHR | 0666; break; } diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/devfs/devtmpfs.c b/rt-thread/components/dfs/dfs_v2/filesystems/devfs/devtmpfs.c index 3bea0c1..82ab422 100644 --- a/rt-thread/components/dfs/dfs_v2/filesystems/devfs/devtmpfs.c +++ b/rt-thread/components/dfs/dfs_v2/filesystems/devfs/devtmpfs.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -34,10 +35,9 @@ struct devtmpfs_file char name[DIRENT_NAME_MAX]; /* file name */ rt_uint32_t type; /* file type */ - rt_list_t subdirs; /* file subdir list */ - rt_list_t sibling; /* file sibling list */ + struct dfs_vfs_node node; /* file node in the devtmpfs */ - struct devtmpfs_sb *sb; /* superblock ptr */ + struct devtmpfs_sb *sb; /* superblock ptr */ rt_uint32_t mode; char *link; @@ -48,7 +48,6 @@ struct devtmpfs_sb rt_uint32_t magic; /* TMPFS_MAGIC */ struct devtmpfs_file root; /* root dir */ rt_size_t df_size; /* df size */ - rt_list_t sibling; /* sb sibling list */ struct rt_spinlock lock; /* tmpfs lock */ }; @@ -111,15 +110,13 @@ static int _get_subdir(const char *path, char *name) #if 0 static int _free_subdir(struct devtmpfs_file *dfile) { - struct devtmpfs_file *file; - rt_list_t *list, *temp_list; + struct devtmpfs_file *file, *tmp; struct devtmpfs_sb *superblock; RT_ASSERT(dfile->type == TMPFS_TYPE_DIR); - rt_list_for_each_safe(list, temp_list, &dfile->subdirs) + dfs_vfs_for_each_subnode(file, tmp, dfile, node) { - file = rt_list_entry(list, struct devtmpfs_file, sibling); if (file->type == TMPFS_TYPE_DIR) { _free_subdir(file); @@ -134,7 +131,7 @@ static int _free_subdir(struct devtmpfs_file *dfile) RT_ASSERT(superblock); rt_spin_lock(&superblock->lock); - rt_list_remove(&(file->sibling)); + dfs_vfs_remove_node(&file->node); rt_spin_unlock(&superblock->lock); rt_free(file); @@ -152,14 +149,12 @@ static int devtmpfs_mount(struct dfs_mnt *mnt, unsigned long rwflag, const void { superblock->df_size = sizeof(struct devtmpfs_sb); superblock->magic = TMPFS_MAGIC; - rt_list_init(&superblock->sibling); superblock->root.name[0] = '/'; superblock->root.sb = superblock; superblock->root.type = TMPFS_TYPE_DIR; superblock->root.mode = S_IFDIR | (S_IRUSR | S_IRGRP | S_IROTH) | (S_IXUSR | S_IXGRP | S_IXOTH); - rt_list_init(&superblock->root.sibling); - rt_list_init(&superblock->root.subdirs); + dfs_vfs_init_node(&superblock->root.node); rt_spin_lock_init(&superblock->lock); @@ -193,8 +188,7 @@ static struct devtmpfs_file *devtmpfs_file_lookup(struct devtmpfs_sb *superblock { const char *subpath, *curpath, *filename = RT_NULL; char subdir_name[DIRENT_NAME_MAX]; - struct devtmpfs_file *file, *curfile; - rt_list_t *list; + struct devtmpfs_file *file, *curfile, *tmp; subpath = path; while (*subpath == '/' && *subpath) @@ -222,9 +216,8 @@ find_subpath: rt_spin_lock(&superblock->lock); - rt_list_for_each(list, &curfile->subdirs) + dfs_vfs_for_each_subnode(file, tmp, curfile, node) { - file = rt_list_entry(list, struct devtmpfs_file, sibling); if (filename) /* find file */ { if (rt_strcmp(file->name, filename) == 0) @@ -293,7 +286,9 @@ static int devtmpfs_stat(struct dfs_dentry *dentry, struct stat *st) static int devtmpfs_getdents(struct dfs_file *file, struct dirent *dirp, uint32_t count) { - struct devtmpfs_file *d_file; + rt_size_t index, end; + struct dirent *d; + struct devtmpfs_file *d_file, *n_file = RT_NULL, *tmp; struct devtmpfs_sb *superblock; RT_ASSERT(file); @@ -306,11 +301,6 @@ static int devtmpfs_getdents(struct dfs_file *file, struct dirent *dirp, uint32_ d_file = devtmpfs_file_lookup(superblock, file->dentry->pathname); if (d_file) { - rt_size_t index, end; - struct dirent *d; - struct devtmpfs_file *n_file; - rt_list_t *list; - /* make integer count */ count = (count / sizeof(struct dirent)); if (count == 0) @@ -322,12 +312,10 @@ static int devtmpfs_getdents(struct dfs_file *file, struct dirent *dirp, uint32_ index = 0; count = 0; - rt_list_for_each(list, &d_file->subdirs) + dfs_vfs_for_each_subnode(n_file, tmp, d_file, node) { if (index >= (rt_size_t)file->fpos) { - n_file = rt_list_entry(list, struct devtmpfs_file, sibling); - d = dirp + count; if (n_file->type == TMPFS_TYPE_FILE) { @@ -378,8 +366,7 @@ static int devtmpfs_symlink(struct dfs_dentry *parent_dentry, const char *target strncpy(l_file->name, linkpath, DIRENT_NAME_MAX - 1); - rt_list_init(&(l_file->subdirs)); - rt_list_init(&(l_file->sibling)); + dfs_vfs_init_node(&l_file->node); l_file->sb = superblock; l_file->type = TMPFS_TYPE_FILE; l_file->mode = p_file->mode; @@ -388,7 +375,7 @@ static int devtmpfs_symlink(struct dfs_dentry *parent_dentry, const char *target l_file->link = rt_strdup(target); rt_spin_lock(&superblock->lock); - rt_list_insert_after(&(p_file->subdirs), &(l_file->sibling)); + dfs_vfs_append_node(&p_file->node, &l_file->node); rt_spin_unlock(&superblock->lock); } } @@ -460,7 +447,7 @@ static int devtmpfs_unlink(struct dfs_dentry *dentry) } rt_spin_lock(&superblock->lock); - rt_list_remove(&(d_file->sibling)); + dfs_vfs_remove_node(&d_file->node); rt_spin_unlock(&superblock->lock); rt_free(d_file); @@ -537,8 +524,7 @@ static struct dfs_vnode *devtmpfs_create_vnode(struct dfs_dentry *dentry, int ty strncpy(d_file->name, file_name, DIRENT_NAME_MAX); - rt_list_init(&(d_file->subdirs)); - rt_list_init(&(d_file->sibling)); + dfs_vfs_init_node(&d_file->node); d_file->sb = superblock; vnode->nlink = 1; @@ -563,7 +549,7 @@ static struct dfs_vnode *devtmpfs_create_vnode(struct dfs_dentry *dentry, int ty d_file->mode = vnode->mode; rt_spin_lock(&superblock->lock); - rt_list_insert_after(&(p_file->subdirs), &(d_file->sibling)); + dfs_vfs_append_node(&p_file->node, &d_file->node); rt_spin_unlock(&superblock->lock); } diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/README.md b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/README.md new file mode 100644 index 0000000..7ab0127 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/README.md @@ -0,0 +1,166 @@ +# 进程文件系统 (procfs) + +## 数据结构 + +```c +struct proc_dentry +{ + rt_uint32_t mode; + rt_atomic_t ref_count; + + struct proc_dentry *parent; + struct dfs_vfs_node node; + + const struct dfs_file_ops *fops; + const struct proc_ops *ops; + + char *name; + void *data; +}; +``` + +```log +root { mode: S_IFDIR, ref_count: 1, parent: root, name: /, child->next: file1->node } + | + |—— file1 { mode: S_IFREG, ref_count: 1, parent: root, name: file1, node->next: link1->node } + |—— link1 { mode: S_IFLNK, ref_count: 1, parent: root, name: link1, data: fullpath, node->next: dir1->node } + |—— dir1 { mode: S_IFDIR, ref_count: 1, parent: root, name: dir1, node->next: file3->node, child->next: file2->node } + | | + | |—— dir2 { mode: S_IFDIR, ref_count: 1, parent: dir1, name: dir2, node->next: link2->node } + | |—— link2 { mode: S_IFLNK, ref_count: 1, parent: dir1, name: link2, data: fullpath, node->next: file2->node } + | |—— file2 { mode: S_IFREG, ref_count: 1, parent: dir1, name: file2 } + | + |—— file3 { mode: S_IFREG, ref_count: 1, parent: root, name: file3 } +``` + +## API 介绍 + +```c +struct proc_dentry *dfs_proc_find(const char *name); + +struct proc_dentry *proc_mkdir_data(const char *name, mode_t mode, struct proc_dentry *parent, + const struct dfs_file_ops *fops, void *data); +struct proc_dentry *proc_mkdir_mode(const char *name, mode_t mode, struct proc_dentry *parent); +struct proc_dentry *proc_mkdir(const char *name, struct proc_dentry *parent); + +struct proc_dentry *proc_create_data(const char *name, mode_t mode, struct proc_dentry *parent, + const struct dfs_file_ops *fops, void *data); + +struct proc_dentry *proc_symlink(const char *name, struct proc_dentry *parent, const char *dest); + +struct proc_dentry *proc_acquire(struct proc_dentry *dentry); +void proc_release(struct proc_dentry *dentry); + +void proc_remove(struct proc_dentry *dentry); +``` + +- dfs_proc_find + + 查找指定节点，并返回节点数据指针 + + | 入参 | 说明 | + | ---- | ---------------------------------------------------- | + | name | 从 procfs 的 root 起始的完整路径，比如 “/dir1/file2” | + +- proc_mkdir_data + + 创建一个目录，并返回节点数据指针 + + | 入参 | 说明 | + | ------ | ------------------------------------------------------------ | + | name | 从 procfs 的 root 起始的完整路径，比如 “/dir1/file2”
从 parent 起始的完整路径 | + | mode | 权限配置 | + | parent | 指定创建目录的起始节点 | + | fops | 文件操作接口配置 | + | data | 私有数据 | + +- proc_mkdir_mode + + 创建一个目录，并返回节点数据指针 + + | 入参 | 说明 | + | ------ | ------------------------------------------------------------ | + | name | 从 procfs 的 root 起始的完整路径，比如 “/dir1/file2”
从 parent 起始的完整路径 | + | mode | 权限配置 | + | parent | 指定创建目录的起始节点 | + +- proc_mkdir + + 创建一个目录，并返回节点数据指针 + + | 入参 | 说明 | + | ---- | ------------------------------------------------------------ | + | name | 从 procfs 的 root 起始的完整路径，比如 “/dir1/file2”
从 parent 起始的完整路径 | + | mode | 权限配置 | + +- proc_create_data + + 创建一个文件，并返回节点数据指针 + + | 入参 | 说明 | + | ------ | ------------------------------------------------------------ | + | name | 从 procfs 的 root 起始的完整路径，比如 “/dir1/file2”
从 parent 起始的完整路径 | + | mode | 权限配置 | + | parent | 指定创建文件的起始节点 | + | fops | 文件操作接口配置 | + | data | 私有数据 | + +- proc_symlink + + 创建一个符号链接，并返回节点数据指针 + + | 入参 | 说明 | + | ------ | ------------------------------------------------------------ | + | name | 从 procfs 的 root 起始的完整路径，比如 “/dir1/file2”
从 parent 起始的完整路径 | + | parent | 指定创建文件的起始节点 | + | dest | 链接的目标文件完整路径 | + +- proc_acquire + + 引用一个节点，并返回节点数据指针 + + | 入参 | 说明 | + | ------ | -------------- | + | dentry | 需要引用的节点 | + +- proc_release + + 释放一个节点 + + | 入参 | 说明 | + | ------ | -------------- | + | dentry | 需要释放的节点 | + +- proc_remove + + 删除一个节点包含子节点 + + | 入参 | 说明 | + | ------ | -------------- | + | dentry | 需要删除的节点 | + +## msh 调试命令 + +- proc_dump + + 遍历打印指定节点含子节点的信息（名称、引用计数），比如 `proc_dump /dir1` 或者 `proc_dump` + +- proc_remove + + 删除指定节点含子节点，比如 `proc_remove /dir1` 或者 `proc_remove /file3` + +- proc_symlink + + 创建一个符号链接，`proc_symlink /link3 /mnt` + +- proc_echo + + 创建一个空文件，`proc_echo /file4` + +- proc_mkdir + + 创建一个空目录，`proc_mkdir /dir3` + +- proc_pid + + 创建一个 pid 目录，`proc_pid /101` diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/SConscript b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/SConscript new file mode 100644 index 0000000..4af49a1 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_PROCFS'], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc.c new file mode 100644 index 0000000..0e0d202 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc.c @@ -0,0 +1,733 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +/* + * This is the root in the proc tree.. + */ +static struct proc_dentry _proc_root = { + .mode = S_IFDIR | (S_IRUSR | S_IRGRP | S_IROTH) | (S_IXUSR | S_IXGRP | S_IXOTH), + .ref_count = 1, + + .parent = &_proc_root, + .node.sibling = RT_LIST_OBJECT_INIT(_proc_root.node.sibling), + .node.subnode = RT_LIST_OBJECT_INIT(_proc_root.node.subnode), + + .fops = RT_NULL, + + .name = "/", + .data = RT_NULL, +}; + +static int _proc_find(struct proc_dentry **parent, const char *name) +{ + struct proc_dentry *dentry = RT_NULL, *tmp; + + dfs_vfs_for_each_subnode(dentry, tmp, (*parent), node) + { + if (dentry == RT_NULL) + { + break; + } + + if (rt_strcmp(dentry->name, name) == 0) + { + *parent = dentry; + return 0; + } + } + + return -1; +} + +static int proc_find(struct proc_dentry **parent, const char **name, rt_bool_t force_lookup) +{ + int ret = 0; + char *tmp = RT_NULL; + + if (!(*parent)) + { + *parent = &_proc_root; + } + + tmp = rt_strdup(*name); + if (tmp) + { + char *begin = tmp, *end = RT_NULL; + if (*begin == '/') + { + begin++; + if (*begin == '\0') + { + rt_free(tmp); + *parent = proc_acquire(*parent); + return ret; + } + } + + while (1) + { + end = rt_strstr(begin, "/"); + if (end) + { + *end = '\0'; + ret = _proc_find(parent, begin); + if (ret < 0 || !S_ISDIR((*parent)->mode)) + { + *parent = RT_NULL; + ret = -1; + break; + } + begin = end + 1; + } + else if (force_lookup) + { + ret = _proc_find(parent, begin); + if (ret < 0) + { + if ((*parent)->ops && (*parent)->ops->lookup) + { + *parent = (*parent)->ops->lookup(*parent, begin); + if (*parent == RT_NULL) + { + ret = -1; + } + } + else + { + *parent = RT_NULL; + } + } + else + { + *parent = proc_acquire(*parent); + } + break; + } + else + { + *parent = proc_acquire(*parent); + break; + } + } + + *name = *name + (begin - tmp); + + rt_free(tmp); + } + + return ret; +} + +static void *single_start(struct dfs_seq_file *seq, off_t *index) +{ + return NULL + (*index == 0); +} + +static void *single_next(struct dfs_seq_file *seq, void *data, off_t *index) +{ + ++*index; + return NULL; +} + +static void single_stop(struct dfs_seq_file *seq, void *data) +{ +} + +static int proc_open(struct dfs_file *file) +{ + struct proc_dentry *entry = (struct proc_dentry *)file->vnode->data; + + if (entry->single_show) + { + struct dfs_seq_ops *seq_ops = (struct dfs_seq_ops *)rt_calloc(1, sizeof(struct dfs_seq_ops)); + if (seq_ops) + { + int ret = 0; + + seq_ops->start = single_start; + seq_ops->next = single_next; + seq_ops->stop = single_stop; + seq_ops->show = entry->single_show; + + ret = dfs_seq_open(file, seq_ops); + if (ret != 0) + { + rt_free(seq_ops); + } + return ret; + } + } + + return dfs_seq_open(file, entry->seq_ops); +} + +static int proc_close(struct dfs_file *file) +{ + struct dfs_seq_file *seq = file->data; + struct proc_dentry *entry = (struct proc_dentry *)file->vnode->data; + + if (seq && entry->single_show && seq->ops) + { + rt_free((void *)seq->ops); + seq->ops = RT_NULL; + } + + return dfs_seq_release(file); +} + +static const struct dfs_file_ops proc_file_ops = { + .open = proc_open, + .read = dfs_seq_read, + .lseek = dfs_seq_lseek, + .close = proc_close, +}; + +static struct proc_dentry *proc_create(struct proc_dentry **parent, const char *name, mode_t mode) +{ + int ret = 0; + struct proc_dentry *dentry = RT_NULL; + + ret = proc_find(parent, &name, 0); + if (ret >= 0) + { + dentry = *parent; + ret = proc_find(&dentry, &name, 1); + if (ret < 0) + { + dentry = rt_calloc(1, sizeof(struct proc_dentry)); + if (dentry) + { + dentry->mode = mode; + dentry->ref_count = 1; + dentry->name = rt_strdup(name); + dfs_vfs_init_node(&dentry->node); + } + } + else + { + proc_release(dentry); + dentry = RT_NULL; + } + } + + return dentry; +} + +/** + * @brief The dentry reference count is incremented by one + * + * @param dentry + * + * @return dentry + */ +struct proc_dentry *proc_acquire(struct proc_dentry *dentry) +{ + if (dentry) + { + dentry->ref_count += 1; + } + + return dentry; +} + +/** + * @brief The dentry reference count is minus one, or release + * + * @param dentry + * + * @return none + */ +void proc_release(struct proc_dentry *dentry) +{ + if (dentry) + { + if (dentry->ref_count == 1) + { + if (dentry->name) + { + rt_free(dentry->name); + } + + if (S_ISLNK(dentry->mode) && dentry->data) + { + rt_free(dentry->data); + } + + rt_free(dentry); + } + else + { + dentry->ref_count -= 1; + } + } +} + +static struct proc_dentry *proc_register(struct proc_dentry *parent, struct proc_dentry *child) +{ + child->parent = parent; + dfs_vfs_append_node(&parent->node, &child->node); + child->ref_count += 1; + child->pid = parent->pid; + + return child; +} + +/** + * @brief Make a dir + * + * @param name fullpath based on _proc_root or parent + * @param mode permission configuration + * @param parent can be empty + * @param fops + * @param data + * + * @return dentry + */ +struct proc_dentry *proc_mkdir_data(const char *name, mode_t mode, struct proc_dentry *parent, + const struct dfs_file_ops *fops, void *data) +{ + struct proc_dentry *dentry, *_parent = parent; + + if (mode == 0) + mode = (S_IRUSR | S_IRGRP | S_IROTH) | (S_IXUSR | S_IXGRP | S_IXOTH); + + dentry = proc_create(&_parent, name, S_IFDIR | mode); + if (dentry) + { + dentry->fops = fops; + dentry->data = data; + + dentry = proc_register(_parent, dentry); + } + proc_release(_parent); + + return dentry; +} + +/** + * @brief Make a dir + * + * @param name fullpath based on _proc_root or parent + * @param mode permission configuration + * @param parent can be empty + * + * @return dentry + */ +struct proc_dentry *proc_mkdir_mode(const char *name, mode_t mode, struct proc_dentry *parent) +{ + return proc_mkdir_data(name, mode, parent, NULL, NULL); +} + +/** + * @brief Make a dir + * + * @param name fullpath based on _proc_root or parent + * @param parent can be empty + * + * @return dentry + */ +struct proc_dentry *proc_mkdir(const char *name, struct proc_dentry *parent) +{ + return proc_mkdir_data(name, 0, parent, NULL, NULL); +} + +static struct proc_dentry *proc_create_reg(const char *name, mode_t mode, struct proc_dentry **parent) +{ + struct proc_dentry *dentry = RT_NULL; + + if ((mode & S_IFMT) == 0) + mode |= S_IFREG; + if ((mode & (S_ISUID | S_ISGID | S_ISVTX | S_IRWXU | S_IRWXG | S_IRWXO)) == 0) + mode |= S_IRUSR | S_IRGRP | S_IROTH; + + if (!S_ISREG(mode)) + { + *parent = RT_NULL; + return dentry; + } + + return proc_create(parent, name, mode); +} + +/** + * @brief Make a file + * + * @param name fullpath based on _proc_root or parent + * @param mode permission configuration + * @param parent can be empty + * @param fops + * @param data + * + * @return dentry + */ +struct proc_dentry *proc_create_data(const char *name, mode_t mode, struct proc_dentry *parent, + const struct dfs_file_ops *fops, void *data) +{ + struct proc_dentry *dentry, *_parent = parent; + + dentry = proc_create_reg(name, mode, &_parent); + if (dentry) + { + dentry->fops = fops ? fops : &proc_file_ops; + dentry->data = data; + + dentry = proc_register(_parent, dentry); + } + proc_release(_parent); + + return dentry; +} + +/** + * @brief Make a file + * + * @param name fullpath based on _proc_root or parent + * @param mode permission configuration + * @param parent can be empty + * @param show + * @param data + * + * @return dentry + */ +struct proc_dentry *proc_create_single_data(const char *name, mode_t mode, struct proc_dentry *parent, + int (*show)(struct dfs_seq_file *, void *), void *data) +{ + struct proc_dentry *dentry, *_parent = parent; + + dentry = proc_create_reg(name, mode, &_parent); + if (dentry) + { + dentry->fops = &proc_file_ops; + dentry->single_show = show; + dentry->data = data; + + dentry = proc_register(_parent, dentry); + } + proc_release(_parent); + + return dentry; +} + +/** + * @brief Make a symlink + * + * @param name fullpath based on _proc_root or parent + * @param parent can be empty + * @param dest link file fullpath + * + * @return dentry + */ +struct proc_dentry *proc_symlink(const char *name, struct proc_dentry *parent, const char *dest) +{ + struct proc_dentry *dentry, *_parent = parent; + + dentry = proc_create(&_parent, name, (S_IFLNK | (S_IRUSR | S_IRGRP | S_IROTH) + | (S_IWUSR | S_IWGRP | S_IWOTH) | (S_IXUSR | S_IXGRP | S_IXOTH))); + if (dentry) + { + dentry->data = (void *)rt_strdup(dest); + if (dentry->data) + { + dentry = proc_register(_parent, dentry); + } + else + { + proc_release(dentry); + dentry = NULL; + } + } + proc_release(_parent); + + return dentry; +} + +static void remove_proc_subtree(struct proc_dentry *dentry) +{ + struct proc_dentry *iter = RT_NULL, *iter_tmp, *tmp = RT_NULL; + + dfs_vfs_for_each_subnode(iter, iter_tmp, dentry, node) + { + if (iter == RT_NULL) + { + break; + } + + if (tmp) + { + proc_release(tmp); + tmp = RT_NULL; + } + + tmp = iter; + + if (S_ISDIR(dentry->mode)) + { + remove_proc_subtree(iter); + } + } + + if (tmp) + { + proc_release(tmp); + tmp = RT_NULL; + } +} + +/** + * @brief remove a dentry + * + * @param dentry + * + * @return none + */ +void proc_remove(struct proc_dentry *dentry) +{ + if (dentry && dentry != &_proc_root) + { + if (S_ISDIR(dentry->mode)) + { + remove_proc_subtree(dentry); + } + + dfs_vfs_remove_node(&dentry->node); + proc_release(dentry); + } +} + +/** + * @brief find dentry exist + * + * @param name fullpath based on _proc_root + * + * @return dentry + */ +struct proc_dentry *dfs_proc_find(const char *name) +{ + struct proc_dentry *dentry = RT_NULL; + + proc_find(&dentry, &name, 1); + + return dentry; +} + +/** + * @brief remove a dentry on parent + * + * @param name fullpath based on parent + * @param parent + * + * @return none + */ +void proc_remove_dentry(const char *name, struct proc_dentry *parent) +{ + struct proc_dentry *dentry = parent; + + if (proc_find(&dentry, &name, 1) >= 0) + { + proc_remove(dentry); + proc_release(dentry); + } +} + +#define _COLOR_RED "\033[31m" +#define _COLOR_GREEN "\033[32m" +#define _COLOR_BLUE "\033[34m" +#define _COLOR_CYAN "\033[36m" +#define _COLOR_WHITE "\033[37m" +#define _COLOR_NORMAL "\033[0m" + +static void dump_proc_subtree(struct proc_dentry *dentry, int tab) +{ + struct proc_dentry *iter = RT_NULL, *tmp; + + dfs_vfs_for_each_subnode(iter, tmp, dentry, node) + { + if (iter == RT_NULL) + { + break; + } + + for(int i = 0; i < tab; i ++) + { + rt_kprintf("%-4s", i + 1 >= tab ? "|-" : " "); + } + + if (S_ISDIR(iter->mode)) + { + rt_kprintf(_COLOR_BLUE "%-20s" _COLOR_NORMAL " %d\n", iter->name, iter->ref_count); + dump_proc_subtree(iter, tab + 1); + } + else if (S_ISLNK(iter->mode)) + { + rt_kprintf(_COLOR_CYAN "%-20s" _COLOR_NORMAL " %d\n", iter->name, iter->ref_count); + } + else + { + rt_kprintf("%-20s %d\n", iter->name, iter->ref_count); + } + } +} + +static void proc_dump(struct proc_dentry *dentry) +{ + if (dentry) + { + if (S_ISDIR(dentry->mode)) + { + rt_kprintf(_COLOR_BLUE "%-20s" _COLOR_NORMAL " %d\n", dentry->name, dentry->ref_count); + dump_proc_subtree(dentry, 1); + } + else if (S_ISLNK(dentry->mode)) + { + rt_kprintf(_COLOR_CYAN "%-20s" _COLOR_NORMAL " %d\n", dentry->name, dentry->ref_count); + } + else + { + rt_kprintf("%-20s %d\n", dentry->name, dentry->ref_count); + } + } +} + +static int msh_proc_dump(int argc, char** argv) +{ + const char *name = argc > 1 ? argv[1] : "/"; + struct proc_dentry *dentry = RT_NULL; + + int ret = proc_find(&dentry, &name, 1); + if (ret >= 0) + { + proc_dump(dentry); + } + proc_release(dentry); + + return 0; +} +MSH_CMD_EXPORT_ALIAS(msh_proc_dump, proc_dump, proc dump); + +static int msh_proc_remove(int argc, char** argv) +{ + if (argc > 1) + { + const char *name = argv[1]; + struct proc_dentry *dentry = RT_NULL; + + int ret = proc_find(&dentry, &name, 1); + if (ret >= 0) + { + if (dentry != &_proc_root) + { + proc_remove(dentry); + } + else + { + struct proc_dentry *iter = RT_NULL, *iter_tmp, *tmp = RT_NULL; + + dfs_vfs_for_each_subnode(iter, iter_tmp, dentry, node) + { + if (iter == RT_NULL) + { + break; + } + + if (tmp) + { + proc_remove(tmp); + } + + tmp = iter; + } + + if (tmp) + { + proc_remove(tmp); + } + } + } + proc_release(dentry); + } + else + { + rt_kprintf("proc_remove path\n"); + } + + return 0; +} +MSH_CMD_EXPORT_ALIAS(msh_proc_remove, proc_remove, proc remove); + +static int msh_proc_symlink(int argc, char** argv) +{ + if (argc > 2) + { + struct proc_dentry *entry = proc_symlink(argv[1], 0, argv[2]); + if (entry) + { + proc_release(entry); + } + } + else + { + rt_kprintf("proc_symlink path dest\n"); + } + + return 0; +} +MSH_CMD_EXPORT_ALIAS(msh_proc_symlink, proc_symlink, proc symlink); + +static int msh_proc_echo(int argc, char** argv) +{ + if (argc > 1) + { + for(int i = 1; i <= argc - 1; i ++) + { + struct proc_dentry *entry = proc_create_data(argv[i], 0, 0, 0, 0); + if (entry) + { + proc_release(entry); + } + } + } + else + { + rt_kprintf("proc_echo path\n"); + } + + return 0; +} +MSH_CMD_EXPORT_ALIAS(msh_proc_echo, proc_echo, proc echo); + +static int msh_proc_mkdir(int argc, char** argv) +{ + if (argc > 1) + { + for(int i = 1; i <= argc - 1; i ++) + { + struct proc_dentry *entry = proc_mkdir(argv[i], 0); + if (entry) + { + proc_release(entry); + } + } + } + else + { + rt_kprintf("proc_mkdir path\n"); + } + + return 0; +} +MSH_CMD_EXPORT_ALIAS(msh_proc_mkdir, proc_mkdir, proc mkdir); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc.h b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc.h new file mode 100644 index 0000000..e697860 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __PROC_H__ +#define __PROC_H__ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +struct proc_dentry; + +struct proc_ops +{ + struct proc_dentry *(*lookup)(struct proc_dentry *parent, const char *name); + int (*readlink)(struct proc_dentry *dentry, char *buf, int len); +}; + +struct proc_dentry +{ + rt_uint32_t mode; + rt_atomic_t ref_count; + + struct proc_dentry *parent; + struct dfs_vfs_node node; + + const struct dfs_file_ops *fops; + const struct proc_ops *ops; + const struct dfs_seq_ops *seq_ops; + int (*single_show)(struct dfs_seq_file *seq, void *data); + + int pid; + + char *name; + void *data; +}; + +struct proc_dentry *dfs_proc_find(const char *name); + +struct proc_dentry *proc_mkdir_data(const char *name, mode_t mode, struct proc_dentry *parent, + const struct dfs_file_ops *fops, void *data); +struct proc_dentry *proc_mkdir_mode(const char *name, mode_t mode, struct proc_dentry *parent); +struct proc_dentry *proc_mkdir(const char *name, struct proc_dentry *parent); + +struct proc_dentry *proc_create_data(const char *name, mode_t mode, struct proc_dentry *parent, + const struct dfs_file_ops *fops, void *data); +struct proc_dentry *proc_create_single_data(const char *name, mode_t mode, struct proc_dentry *parent, + int (*show)(struct dfs_seq_file *, void *), void *data); + +struct proc_dentry *proc_symlink(const char *name, struct proc_dentry *parent, const char *dest); + +struct proc_dentry *proc_acquire(struct proc_dentry *dentry); +void proc_release(struct proc_dentry *dentry); + +void proc_remove(struct proc_dentry *dentry); +void proc_remove_dentry(const char *name, struct proc_dentry *parent); + +int proc_pid(int pid); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_cmdline.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_cmdline.c new file mode 100644 index 0000000..5845b5f --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_cmdline.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include + +static char *__proc_cmdline = NULL; + +int proc_cmdline_save(const char *cmdline) +{ + if (__proc_cmdline) + { + free(__proc_cmdline); + __proc_cmdline = NULL; + } + + __proc_cmdline = strdup(cmdline); + + return 0; +} + +static int single_show(struct dfs_seq_file *seq, void *data) +{ + if (__proc_cmdline) + { + dfs_seq_puts(seq, __proc_cmdline); + } + + return 0; +} + +int proc_cmdline_init(void) +{ + struct proc_dentry *dentry = proc_create_single_data("cmdline", 0, NULL, single_show, NULL); + proc_release(dentry); + + return 0; +} +INIT_ENV_EXPORT(proc_cmdline_init); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_cpuinfo.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_cpuinfo.c new file mode 100644 index 0000000..6f49832 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_cpuinfo.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include + +static void *seq_start(struct dfs_seq_file *seq, off_t *index) +{ + off_t i = *index; // seq->index + + return NULL + (i == 0); +} + +static void seq_stop(struct dfs_seq_file *seq, void *data) +{ +} + +static void *seq_next(struct dfs_seq_file *seq, void *data, off_t *index) +{ + /* data: The return value of the start or next*/ + off_t i = *index + 1; // seq->index + + *index = i; + + return NULL; +} + +static int seq_show(struct dfs_seq_file *seq, void *data) +{ + /* data: The return value of the start or next*/ + dfs_seq_puts(seq, "rt_weak const struct dfs_seq_ops *cpuinfo_get_seq_ops(void)\n--need your own function--\n"); + + return 0; +} + +static const struct dfs_seq_ops seq_ops = { + .start = seq_start, + .stop = seq_stop, + .next = seq_next, + .show = seq_show, +}; + +rt_weak const struct dfs_seq_ops *cpuinfo_get_seq_ops(void) +{ + return &seq_ops; +} + +static int proc_open(struct dfs_file *file) +{ + return dfs_seq_open(file, cpuinfo_get_seq_ops()); +} + +static int proc_close(struct dfs_file *file) +{ + return dfs_seq_release(file); +} + +static const struct dfs_file_ops file_ops = { + .open = proc_open, + .read = dfs_seq_read, + .lseek = dfs_seq_lseek, + .close = proc_close, +}; + +int proc_cpuinfo_init(void) +{ + struct proc_dentry *dentry = proc_create_data("cpuinfo", 0, NULL, &file_ops, NULL); + proc_release(dentry); + + return 0; +} +INIT_ENV_EXPORT(proc_cpuinfo_init); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_devices.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_devices.c new file mode 100644 index 0000000..7bd0718 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_devices.c @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include +#include +#include +#include + + +#define LIST_FIND_OBJ_NR 8 + +struct device_show +{ + char *buf; + int size; + int len; + int index; +}; + +typedef struct +{ + rt_list_t *list; + rt_list_t **array; + rt_uint8_t type; + int nr; /* input: max nr, can't be 0 */ + int nr_out; /* out: got nr */ +} list_get_next_t; + +static void list_find_init(list_get_next_t *p, rt_uint8_t type, rt_list_t **array, int nr) +{ + struct rt_object_information *info; + rt_list_t *list; + + info = rt_object_get_information((enum rt_object_class_type)type); + list = &info->object_list; + + p->list = list; + p->type = type; + p->array = array; + p->nr = nr; + p->nr_out = 0; +} + +static rt_list_t *list_get_next(rt_list_t *current, list_get_next_t *arg) +{ + int first_flag = 0; + rt_base_t level; + rt_list_t *node, *list; + rt_list_t **array; + struct rt_object_information *info; + int nr; + + arg->nr_out = 0; + + if (!arg->nr || !arg->type) + { + return (rt_list_t *)RT_NULL; + } + + list = arg->list; + info = rt_list_entry(list, struct rt_object_information, object_list); + + if (!current) /* find first */ + { + node = list; + first_flag = 1; + } + else + { + node = current; + } + + level = rt_spin_lock_irqsave(&info->spinlock); + + if (!first_flag) + { + struct rt_object *obj; + /* The node in the list? */ + obj = rt_list_entry(node, struct rt_object, list); + if ((obj->type & ~RT_Object_Class_Static) != arg->type) + { + rt_spin_unlock_irqrestore(&info->spinlock, level); + return (rt_list_t *)RT_NULL; + } + } + + nr = 0; + array = arg->array; + while (1) + { + node = node->next; + + if (node == list) + { + node = (rt_list_t *)RT_NULL; + break; + } + nr++; + *array++ = node; + if (nr == arg->nr) + { + break; + } + } + + rt_spin_unlock_irqrestore(&info->spinlock, level); + arg->nr_out = nr; + return node; +} + +static char *const device_type_str[RT_Device_Class_Unknown] = +{ + "Character Device", + "Block Device", + "Network Interface", + "MTD Device", + "CAN Device", + "RTC", + "Sound Device", + "Graphic Device", + "I2C Bus", + "USB Slave Device", + "USB Host Bus", + "USB OTG Bus", + "SPI Bus", + "SPI Device", + "SDIO Bus", + "PM Pseudo Device", + "Pipe", + "Portal Device", + "Timer Device", + "Miscellaneous Device", + "Sensor Device", + "Touch Device", + "Phy Device", + "Security Device", + "WLAN Device", + "Pin Device", + "ADC Device", + "DAC Device", + "WDT Device", + "PWM Device", + "Bus Device", +}; + +static void save_info(struct device_show *dev, char *dev_name) +{ + char tmp[256] = {0}; + int len; + + dev->index ++; + + rt_snprintf(tmp, 256, "%d %s\n", dev->index, dev_name); + tmp[255] = 0; + + len = rt_strlen(tmp); + if (dev->size > dev->len + len) + { + strcat(dev->buf, tmp); + dev->len += len; + } + else + { + if (dev->buf == RT_NULL) + { + dev->buf = rt_calloc(1, 4096); + } + else + { + dev->buf = rt_realloc(dev->buf, dev->size + 4096); + } + if (dev->buf) + { + dev->size += 4096; + strcat(dev->buf, tmp); + dev->len += len; + } + } +} + +static void list_device(struct device_show *dev) +{ + rt_base_t level; + list_get_next_t find_arg; + struct rt_object_information *info; + rt_list_t *obj_list[LIST_FIND_OBJ_NR]; + rt_list_t *next = (rt_list_t *)RT_NULL; + + list_find_init(&find_arg, RT_Object_Class_Device, obj_list, sizeof(obj_list) / sizeof(obj_list[0])); + info = rt_list_entry(find_arg.list, struct rt_object_information, object_list); + + do + { + next = list_get_next(next, &find_arg); + { + int i; + for (i = 0; i < find_arg.nr_out; i++) + { + struct rt_object *obj; + struct rt_device *device; + + obj = rt_list_entry(obj_list[i], struct rt_object, list); + level = rt_spin_lock_irqsave(&info->spinlock); + if ((obj->type & ~RT_Object_Class_Static) != find_arg.type) + { + rt_spin_unlock_irqrestore(&info->spinlock, level); + continue; + } + + rt_spin_unlock_irqrestore(&info->spinlock, level); + + device = (struct rt_device *)obj; + + if (device->type < RT_Device_Class_Unknown) + { + save_info(dev + device->type, device->parent.name); + } + } + } + } + while (next != (rt_list_t *)RT_NULL); +} + +static int show_info(struct dfs_seq_file *seq) +{ + struct device_show _show[RT_Device_Class_Unknown] = {0}; + + list_device(_show); + + for (int i = 0; i < RT_Device_Class_Unknown; i++) + { + if (_show[i].buf) + { + dfs_seq_printf(seq, "%s:\n", device_type_str[i]); + dfs_seq_write(seq, _show[i].buf, _show[i].len); + dfs_seq_putc(seq, '\n'); + + rt_free(_show[i].buf); + } + } + + return 0; +} + +static void *seq_start(struct dfs_seq_file *seq, off_t *index) +{ + off_t i = *index; // seq->index + + return NULL + (i == 0); +} + +static void seq_stop(struct dfs_seq_file *seq, void *data) +{ +} + +static void *seq_next(struct dfs_seq_file *seq, void *data, off_t *index) +{ + /* data: The return value of the start or next*/ + off_t i = *index + 1; // seq->index + + *index = i; + + return NULL; +} + +static int seq_show(struct dfs_seq_file *seq, void *data) +{ + /* data: The return value of the start or next*/ + show_info(seq); + + return 0; +} + +static const struct dfs_seq_ops seq_ops = { + .start = seq_start, + .stop = seq_stop, + .next = seq_next, + .show = seq_show, +}; + +int proc_devices_init(void) +{ + struct proc_dentry *dentry = proc_create_data("devices", 0, NULL, NULL, NULL); + if (dentry) + { + dentry->seq_ops = &seq_ops; + } + proc_release(dentry); + + return 0; +} +INIT_ENV_EXPORT(proc_devices_init); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_filesystems.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_filesystems.c new file mode 100644 index 0000000..94e7a85 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_filesystems.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include +#include + +static void *seq_start(struct dfs_seq_file *seq, off_t *index) +{ + off_t i = *index; // seq->index + struct dfs_filesystem_type *fs = dfs_filesystems(); + + if (fs) + { + while (i--) + { + fs = fs->next; + if (!fs) + { + break; + } + } + } + + return fs; +} + +static void seq_stop(struct dfs_seq_file *seq, void *data) +{ +} + +static void *seq_next(struct dfs_seq_file *seq, void *data, off_t *index) +{ + /* data: The return value of the start or next*/ + off_t i = *index + 1; // seq->index + struct dfs_filesystem_type *fs = (struct dfs_filesystem_type *)data; + + *index = i; + + return fs->next; +} + +static int seq_show(struct dfs_seq_file *seq, void *data) +{ + /* data: The return value of the start or next*/ + struct dfs_filesystem_type *fs = (struct dfs_filesystem_type *)data; + + dfs_seq_printf(seq, "%-9s%s\n", (fs->fs_ops->flags == FS_NEED_DEVICE) ? "" : "nodev", fs->fs_ops->name); + + return 0; +} + +static const struct dfs_seq_ops seq_ops = { + .start = seq_start, + .stop = seq_stop, + .next = seq_next, + .show = seq_show, +}; + +int proc_filesystems_init(void) +{ + struct proc_dentry *dentry = proc_create_data("filesystems", 0, NULL, NULL, NULL); + if (dentry) + { + dentry->seq_ops = &seq_ops; + } + proc_release(dentry); + + return 0; +} +INIT_ENV_EXPORT(proc_filesystems_init); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_loadavg.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_loadavg.c new file mode 100644 index 0000000..6ce1bc4 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_loadavg.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include +#include + + +extern void rt_memory_info(rt_size_t *total, + rt_size_t *used, + rt_size_t *max_used); + +static int single_show(struct dfs_seq_file *seq, void *data) +{ + dfs_seq_printf(seq, "0.13 0.16 0.17 1/1035 380436\n"); + + return 0; +} + +int proc_loadavg_init(void) +{ + struct proc_dentry *dentry = proc_create_single_data("loadavg", 0, NULL, single_show, NULL); + proc_release(dentry); + + return 0; +} +INIT_ENV_EXPORT(proc_loadavg_init); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_meminfo.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_meminfo.c new file mode 100644 index 0000000..b6ae562 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_meminfo.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include +#include + + +extern void rt_memory_info(rt_size_t *total, + rt_size_t *used, + rt_size_t *max_used); + +static int single_show(struct dfs_seq_file *seq, void *data) +{ + rt_size_t total, used, max_used, freed; + rt_size_t total_sum = 0; + rt_size_t total_freed = 0; + + rt_memory_info(&total, &used, &max_used); + total_sum = total_sum + total; + total_freed = total_freed + total - used; + + dfs_seq_printf(seq, "%-16s%8d KB\n", "MemMaxUsed:", max_used / 1024); + dfs_seq_printf(seq, "%-16s%8d KB\n", "MemAvailable:", (total - used) / 1024); + dfs_seq_printf(seq, "%-16s%8d KB\n", "Cached:", 0); + dfs_seq_printf(seq, "%-16s%8d KB\n", "SReclaimable:", 0); + + rt_page_get_info(&total, &freed); + total_sum = total_sum + total * RT_MM_PAGE_SIZE; + total_freed = total_freed + freed * RT_MM_PAGE_SIZE; + + dfs_seq_printf(seq, "%-16s%8d KB\n", "MemTotal:", total_sum / 1024); + dfs_seq_printf(seq, "%-16s%8d KB\n", "MemFree:", total_freed / 1024); + dfs_seq_printf(seq, "%-16s%8d KB\n", "LowPageTotal:", total * RT_MM_PAGE_SIZE / 1024); + dfs_seq_printf(seq, "%-16s%8d KB\n", "lowPageFree:", freed * RT_MM_PAGE_SIZE/ 1024); + + rt_page_high_get_info(&total, &freed); + + dfs_seq_printf(seq, "%-16s%8d KB\n", "HighPageTotal:", total * RT_MM_PAGE_SIZE / 1024); + dfs_seq_printf(seq, "%-16s%8d KB\n", "HighPageFree:", freed * RT_MM_PAGE_SIZE / 1024); + + return 0; +} + +int proc_meminfo_init(void) +{ + struct proc_dentry *dentry = proc_create_single_data("meminfo", 0, NULL, single_show, NULL); + proc_release(dentry); + + return 0; +} +INIT_ENV_EXPORT(proc_meminfo_init); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_mounts.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_mounts.c new file mode 100644 index 0000000..49a6ba9 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_mounts.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include +#include + + +const char *mnt_flag(int flag) +{ + /*if (flag & MNT_READONLY) + { + return "ro"; + }*/ + + return "rw"; +} + +static struct dfs_mnt* mnt_show(struct dfs_mnt *mnt, void *parameter) +{ + struct dfs_seq_file *seq = (struct dfs_seq_file *)parameter; + + if (mnt) + { + if (mnt->dev_id) + { + dfs_seq_printf(seq, "%s %s %s %s 0 0\n", mnt->dev_id->parent.name, mnt->fullpath, + mnt->fs_ops->name, mnt_flag(mnt->flags)); + } + else + { + dfs_seq_printf(seq, "%s %s %s %s 0 0\n", mnt->fs_ops->name, mnt->fullpath, + mnt->fs_ops->name, mnt_flag(mnt->flags)); + } + } + + return RT_NULL; +} + +static void *seq_start(struct dfs_seq_file *seq, off_t *index) +{ + off_t i = *index; // seq->index + + return NULL + (i == 0); +} + +static void seq_stop(struct dfs_seq_file *seq, void *data) +{ +} + +static void *seq_next(struct dfs_seq_file *seq, void *data, off_t *index) +{ + /* data: The return value of the start or next*/ + off_t i = *index + 1; // seq->index + + *index = i; + + return NULL; +} + +static int seq_show(struct dfs_seq_file *seq, void *data) +{ + /* data: The return value of the start or next*/ + dfs_mnt_foreach(mnt_show, seq); + + return 0; +} + +static const struct dfs_seq_ops seq_ops = { + .start = seq_start, + .stop = seq_stop, + .next = seq_next, + .show = seq_show, +}; + +int proc_mounts_init(void) +{ + struct proc_dentry *dentry = proc_create_data("mounts", 0, NULL, NULL, NULL); + if (dentry) + { + dentry->seq_ops = &seq_ops; + } + proc_release(dentry); + + return 0; +} +INIT_ENV_EXPORT(proc_mounts_init); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_net.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_net.c new file mode 100644 index 0000000..e2b38e0 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_net.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include + +#ifdef RT_USING_LWIP +#include "lwip/opt.h" +#endif + +#if LWIP_ROUTE +extern int inet_route_foreach(void (*func)(const char *name, uint32_t ip_addr, uint32_t netmask, void *parameter), void *parameter); +#endif + +static void *seq_start(struct dfs_seq_file *seq, off_t *index) +{ + off_t i = *index; // seq->index + + return NULL + (i == 0); +} + +static void seq_stop(struct dfs_seq_file *seq, void *data) +{ +} + +static void *seq_next(struct dfs_seq_file *seq, void *data, off_t *index) +{ + /* data: The return value of the start or next*/ + off_t i = *index + 1; // seq->index + + *index = i; + + return NULL; +} + +static void route_show(const char *name, uint32_t ip_addr, uint32_t netmask, void *parameter) +{ + struct dfs_seq_file *seq = (struct dfs_seq_file *)parameter; + /* "Iface\tDestination\tGateway " + "\tFlags\tRefCnt\tUse\tMetric\tMask\t\tMTU" + "\tWindow\tIRTT"); */ + /* "%63s%lx%lx%X%d%d%d%lx%d%d%d\n" */ + dfs_seq_printf(seq, "%s ", name); + dfs_seq_printf(seq, "%lx ", ip_addr); + dfs_seq_printf(seq, "%lx ", 0); + dfs_seq_printf(seq, "%X ", 1); + dfs_seq_printf(seq, "%d ", 0); + dfs_seq_printf(seq, "%d ", 0); + dfs_seq_printf(seq, "%d ", 0); + dfs_seq_printf(seq, "%lx ", netmask); + dfs_seq_printf(seq, "%d ", 0); + dfs_seq_printf(seq, "%d ", 0); + dfs_seq_printf(seq, "%d\n", 0); +} + +static int seq_show(struct dfs_seq_file *seq, void *data) +{ + /* data: The return value of the start or next*/ + dfs_seq_printf(seq, "\n"); +#if LWIP_ROUTE + inet_route_foreach(route_show, seq); +#endif + + return 0; +} + +static const struct dfs_seq_ops seq_ops = { + .start = seq_start, + .stop = seq_stop, + .next = seq_next, + .show = seq_show, +}; + +int proc_net_init(void) +{ + struct proc_dentry *dentry; + + dentry = proc_mkdir("net", NULL); + if (!dentry) + return -1; + + proc_release(dentry); + + dentry = proc_create_data("net/route", 0, NULL, NULL, NULL); + if (dentry) + { + dentry->seq_ops = &seq_ops; + } + proc_release(dentry); + + return 0; +} +INIT_ENV_EXPORT(proc_net_init); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_partitions.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_partitions.c new file mode 100644 index 0000000..1c7a48a --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_partitions.c @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include +#include +#include +#include + + +#define LIST_FIND_OBJ_NR 8 + +typedef struct +{ + rt_list_t *list; + rt_list_t **array; + rt_uint8_t type; + int nr; /* input: max nr, can't be 0 */ + int nr_out; /* out: got nr */ +} list_get_next_t; + +static void list_find_init(list_get_next_t *p, rt_uint8_t type, rt_list_t **array, int nr) +{ + struct rt_object_information *info; + rt_list_t *list; + + info = rt_object_get_information((enum rt_object_class_type)type); + list = &info->object_list; + + p->list = list; + p->type = type; + p->array = array; + p->nr = nr; + p->nr_out = 0; +} + +static rt_list_t *list_get_next(rt_list_t *current, list_get_next_t *arg) +{ + int first_flag = 0; + rt_base_t level; + rt_list_t *node, *list; + rt_list_t **array; + struct rt_object_information *info; + int nr; + + arg->nr_out = 0; + + if (!arg->nr || !arg->type) + { + return (rt_list_t *)RT_NULL; + } + + list = arg->list; + info = rt_list_entry(list, struct rt_object_information, object_list); + + if (!current) /* find first */ + { + node = list; + first_flag = 1; + } + else + { + node = current; + } + + level = rt_spin_lock_irqsave(&info->spinlock); + + if (!first_flag) + { + struct rt_object *obj; + /* The node in the list? */ + obj = rt_list_entry(node, struct rt_object, list); + if ((obj->type & ~RT_Object_Class_Static) != arg->type) + { + rt_spin_unlock_irqrestore(&info->spinlock, level); + return (rt_list_t *)RT_NULL; + } + } + + nr = 0; + array = arg->array; + while (1) + { + node = node->next; + + if (node == list) + { + node = (rt_list_t *)RT_NULL; + break; + } + nr++; + *array++ = node; + if (nr == arg->nr) + { + break; + } + } + + rt_spin_unlock_irqrestore(&info->spinlock, level); + arg->nr_out = nr; + return node; +} + +static int show_info(struct dfs_seq_file *seq) +{ + rt_base_t level; + list_get_next_t find_arg; + struct rt_object_information *info; + rt_list_t *obj_list[LIST_FIND_OBJ_NR]; + rt_list_t *next = (rt_list_t *)RT_NULL; + + list_find_init(&find_arg, RT_Object_Class_Device, obj_list, sizeof(obj_list) / sizeof(obj_list[0])); + info = rt_list_entry(find_arg.list, struct rt_object_information, object_list); + + do + { + next = list_get_next(next, &find_arg); + { + int i; + for (i = 0; i < find_arg.nr_out; i++) + { + struct rt_object *obj; + struct rt_device *device; + + obj = rt_list_entry(obj_list[i], struct rt_object, list); + level = rt_spin_lock_irqsave(&info->spinlock); + if ((obj->type & ~RT_Object_Class_Static) != find_arg.type) + { + rt_spin_unlock_irqrestore(&info->spinlock, level); + continue; + } + + rt_spin_unlock_irqrestore(&info->spinlock, level); + + device = (struct rt_device *)obj; + + if (device->type == RT_Device_Class_Block) + { + struct rt_device_blk_geometry geometry = { 0 }; + + rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); + + dfs_seq_printf(seq, "%4d %7d %14llu %s\n", 0, 0, + geometry.sector_count, device->parent.name); + } + } + } + } while (next != (rt_list_t *)RT_NULL); + + return 0; +} + +static void *seq_start(struct dfs_seq_file *seq, off_t *index) +{ + off_t i = *index; // seq->index + + return NULL + (i == 0); +} + +static void seq_stop(struct dfs_seq_file *seq, void *data) +{ +} + +static void *seq_next(struct dfs_seq_file *seq, void *data, off_t *index) +{ + /* data: The return value of the start or next*/ + off_t i = *index + 1; // seq->index + + *index = i; + + return NULL; +} + +static int seq_show(struct dfs_seq_file *seq, void *data) +{ + dfs_seq_puts(seq, "major minor #blocks name\n\n"); + /* data: The return value of the start or next*/ + show_info(seq); + + return 0; +} + +static const struct dfs_seq_ops seq_ops = { + .start = seq_start, + .stop = seq_stop, + .next = seq_next, + .show = seq_show, +}; + +int proc_partitions_init(void) +{ + struct proc_dentry *dentry = proc_create_data("partitions", 0, NULL, NULL, NULL); + if (dentry) + { + dentry->seq_ops = &seq_ops; + } + proc_release(dentry); + + return 0; +} +INIT_ENV_EXPORT(proc_partitions_init); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_pid.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_pid.c new file mode 100644 index 0000000..a413f64 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_pid.c @@ -0,0 +1,449 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#define __RT_IPC_SOURCE__ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include "lwp_internal.h" +#include +#include "lwp_internal.h" + +#if defined(RT_USING_SMART) + +#include "lwp.h" +#include "lwp_pid.h" +#include + +struct pid_dentry +{ + const char *name; + mode_t mode; + const struct dfs_file_ops *fops; + const struct proc_ops *ops; + const struct dfs_seq_ops *seq_ops; + int (*single_show)(struct dfs_seq_file *seq, void *data); + void *data; +}; + +static char stat_transform(int __stat) +{ + switch (__stat) + { + case RT_THREAD_RUNNING: + return 'R'; + default: + return 'T'; + } +} + +static int stat_single_show(struct dfs_seq_file *seq, void *data) +{ + struct proc_dentry *dentry = (struct proc_dentry *)seq->file->vnode->data; + rt_list_t *list; + int mask = 0; + rt_thread_t thread; + rt_uint64_t user_time_lwp = 0; + rt_uint64_t system_time_lwp = 0; + int lwp_oncpu = RT_CPUS_NR; + int lwp_oncpu_ok = 0; + struct rt_lwp *lwp = RT_NULL; + char** argv = RT_NULL; + char *filename = RT_NULL; + char *dot = RT_NULL; + + lwp_pid_lock_take(); + + lwp = lwp_from_pid_locked(dentry->pid); + argv = lwp_get_command_line_args(lwp); + + if (lwp) + { + dfs_seq_printf(seq,"%d ",dentry->pid); + if (argv) + { + filename = strrchr(argv[0], '/'); + dot = strchr(argv[0], '.'); + + if (filename != NULL) + { + filename++; + } + else + { + filename = argv[0]; + } + + if (dot != NULL) + { + *dot = '\0'; + } + + if (filename != NULL) + { + dfs_seq_printf(seq,"(%s) ", filename); + } + else + { + dfs_seq_printf(seq,"(%s) ", argv[0]); + } + + lwp_free_command_line_args(argv); + } + else + { + dfs_seq_printf(seq,"(%s) ", ""); + } + + if (lwp->terminated) + { + dfs_seq_printf(seq,"%c ",'Z'); + } + else + { + list = lwp->t_grp.next; + while (list != &lwp->t_grp) + { + thread = rt_list_entry(list, struct rt_thread, sibling); + user_time_lwp = user_time_lwp + thread->user_time; + system_time_lwp = system_time_lwp + thread->system_time; + + #if RT_CPUS_NR > 1 + #define ONCPU(thread) RT_SCHED_CTX(thread).oncpu + #else + #define ONCPU(thread) 0 + #endif + if (lwp_oncpu_ok == 0) + { + lwp_oncpu = ONCPU(thread); + lwp_oncpu_ok = 1; + } + if (stat_transform(RT_SCHED_CTX(thread).stat) == 'R') + { + lwp_oncpu = ONCPU(thread); + mask = 1; + } + list = list->next; + } + + if (mask == 1) + { + dfs_seq_printf(seq,"%c ",'R'); + } + else + { + dfs_seq_printf(seq,"%c ",'S'); + } + } + lwp_pid_lock_release(); + + if (lwp->parent != NULL) + dfs_seq_printf(seq,"%d ",lwp->parent->pid); + else + dfs_seq_printf(seq,"0 "); + + dfs_seq_printf(seq, "1 1 0 -1 4194560 48245 133976064 732 425574 "); + dfs_seq_printf(seq,"%llu ",user_time_lwp);//utime + dfs_seq_printf(seq,"%llu ",system_time_lwp);//stime + dfs_seq_printf(seq, "1204291 518742 20 0 1 0 50 "); + dfs_seq_printf(seq, "%d ",rt_aspace_count_vsz(lwp->aspace));//VSZ + dfs_seq_printf(seq, "1422 18446744073709551615 "); + dfs_seq_printf(seq, "1 1 0 0 0 0 671173123 4096 1260 0 0 0 17 "); + dfs_seq_printf(seq, "%d ", lwp_oncpu);//CPU + dfs_seq_printf(seq, "0 0 0 0 0 0 0 0 0 0 0 0 0"); + dfs_seq_printf(seq,"\n"); + } + else + { + lwp_pid_lock_release(); + } + + return 0; +} + +static int cmdline_single_show(struct dfs_seq_file *seq, void *data) +{ + struct proc_dentry *dentry = (struct proc_dentry *)seq->file->vnode->data; + struct rt_lwp *lwp; + char** argv; + + lwp_pid_lock_take(); + lwp = lwp_from_pid_locked(dentry->pid); + argv = lwp_get_command_line_args(lwp); + lwp_pid_lock_release(); + + if (argv) + { + for (int i = 0; argv[i] != NULL; i++) + { + dfs_seq_printf(seq, "%s ", argv[i]); + } + dfs_seq_puts(seq, "\n"); + + lwp_free_command_line_args(argv); + } + else + { + dfs_seq_puts(seq, "error\n"); + } + + return 0; +} + +struct proc_dentry *proc_pid_fd_lookup(struct proc_dentry *parent, const char *name) +{ + struct proc_dentry *dentry = RT_NULL; + char num[DIRENT_NAME_MAX]; + struct rt_lwp *lwp; + struct dfs_fdtable *table; + + lwp_pid_lock_take(); + lwp = lwp_from_pid_locked(parent->pid); + table = lwp ? &lwp->fdt : RT_NULL; + lwp_pid_lock_release(); + + if (!table) + { + return RT_NULL; + } + + dfs_file_lock(); + for (int i = 0; i < table->maxfd; i++) + { + struct dfs_file *file = table->fds[i]; + if (file) + { + rt_snprintf(num, DIRENT_NAME_MAX, "%d", i); + if (rt_strcmp(num, name) == 0) + { + dentry = rt_calloc(1, sizeof(struct proc_dentry)); + if (dentry) + { + dentry->mode = (S_IFLNK | (S_IRUSR | S_IRGRP | S_IROTH) | (S_IWUSR | S_IWGRP | S_IWOTH) | (S_IXUSR | S_IXGRP | S_IXOTH)); + dentry->ref_count = 1; + dentry->name = rt_strdup(name); + dentry->data = (void *)dfs_dentry_full_path(file->dentry); + + if (dentry->data == RT_NULL) + { + //todo add vnode->data + if (file->vnode->type == FT_SOCKET) + dentry->data = (void *)rt_strdup("socket"); + else if (file->vnode->type == FT_USER) + dentry->data = (void *)rt_strdup("user"); + else if (file->vnode->type == FT_DEVICE) + dentry->data = (void *)rt_strdup("device"); + else + dentry->data = (void *)rt_strdup("unknown"); + } + + dentry->pid = parent->pid; + break; + } + } + } + } + dfs_file_unlock(); + + return dentry; +} + +int proc_pid_fd_getdents(struct dfs_file *file, struct dirent *dirp, uint32_t count) +{ + int ret = 0, index = 0; + struct proc_dentry *entry = (struct proc_dentry *)file->vnode->data; + struct rt_lwp *lwp; + struct dfs_fdtable *table; + + lwp_pid_lock_take(); + lwp = lwp_from_pid_locked(entry->pid); + LWP_LOCK(lwp); + table = lwp ? &lwp->fdt : RT_NULL; + + if (!table->fds) + { + LWP_UNLOCK(lwp); + lwp_pid_lock_release(); + return 0; + } + + count = (count / sizeof(struct dirent)); + if (count == 0) + { + LWP_UNLOCK(lwp); + lwp_pid_lock_release(); + return -EINVAL; + } + + dfs_file_lock(); + for (int i = 0; i < table->maxfd; i++) + { + struct dfs_file *df = table->fds[i]; + if (df) + { + if (index >= file->fpos) + { + struct dirent *d = dirp + index - file->fpos; + + d->d_type = DT_SYMLINK; + d->d_reclen = (rt_uint16_t)sizeof(struct dirent); + rt_snprintf(d->d_name, DIRENT_NAME_MAX, "%d", i); + d->d_namlen = rt_strlen(d->d_name); + + ret++; + } + + index++; + if (index - file->fpos >= count) + { + break; + } + } + } + dfs_file_unlock(); + LWP_UNLOCK(lwp); + lwp_pid_lock_release(); + + if (ret > 0) + { + file->fpos = index; + ret = ret * sizeof(struct dirent); + } + + return ret; +} + +static const struct proc_ops proc_pid_fd_ops = { + .lookup = proc_pid_fd_lookup, +}; + +static const struct dfs_file_ops proc_pid_fd_fops = { + .getdents = proc_pid_fd_getdents, +}; + +int proc_pid_exe_readlink(struct proc_dentry *dentry, char *buf, int len) +{ + struct rt_lwp *lwp; + + lwp = lwp_self(); + len = rt_snprintf(buf, len, "%s", lwp ? lwp->exe_file : "null"); + + return len; +} + +static const struct proc_ops proc_pid_exe_ops = { + .readlink = proc_pid_exe_readlink, +}; + +int proc_pid_cwd_readlink(struct proc_dentry *dentry, char *buf, int len) +{ + struct rt_lwp *lwp; + + lwp = lwp_self(); + len = rt_snprintf(buf, len, "%s", lwp ? lwp->working_directory : "null"); + + return len; +} + +static const struct proc_ops proc_pid_cwd_ops = { + .readlink = proc_pid_cwd_readlink, +}; + +static struct pid_dentry pid_dentry_base[] = { + {"cmdline", S_IFREG | S_IRUSR | S_IRGRP | S_IROTH, 0, 0, 0, cmdline_single_show, 0}, + {"cwd", S_IFLNK | S_IRUSR | S_IXUSR, 0, &proc_pid_cwd_ops, 0, 0}, + {"exe", S_IFLNK | S_IRUSR | S_IXUSR, 0, &proc_pid_exe_ops, 0, 0}, + {"fd", S_IFDIR | S_IRUSR | S_IXUSR, &proc_pid_fd_fops, &proc_pid_fd_ops, 0, 0, 0}, + {"mounts", S_IFLNK | S_IRUSR | S_IXUSR, 0, 0, 0, 0, "/proc/mounts"}, + {"stat", S_IFREG | S_IRUSR | S_IRGRP | S_IROTH, 0, 0, 0, stat_single_show, 0}, +}; + +int proc_pid(int pid) +{ + char pid_str[64] = {0}; + struct proc_dentry *dentry; + + rt_snprintf(pid_str, 64, "%d", pid); + pid_str[63] = 0; + + dentry = proc_mkdir(pid_str, 0); + if (dentry) + { + struct proc_dentry *ent; + + dentry->pid = pid; + for (int j = 0; j < sizeof(pid_dentry_base) / sizeof(struct pid_dentry); j++) + { + if (S_ISDIR(pid_dentry_base[j].mode)) + { + ent = proc_mkdir_data(pid_dentry_base[j].name, pid_dentry_base[j].mode, dentry, + pid_dentry_base[j].fops, pid_dentry_base[j].data); + } + else if (S_ISLNK(pid_dentry_base[j].mode)) + { + if (pid_dentry_base[j].data == RT_NULL) + { + pid_dentry_base[j].data = "NULL"; + } + + ent = proc_symlink(pid_dentry_base[j].name, dentry, pid_dentry_base[j].data); + } + else + { + ent = proc_create_data(pid_dentry_base[j].name, pid_dentry_base[j].mode, dentry, + pid_dentry_base[j].fops, pid_dentry_base[j].data); + } + + if (ent) + { + if (pid_dentry_base[j].ops) + { + ent->ops = pid_dentry_base[j].ops; + } + + if (pid_dentry_base[j].seq_ops) + { + ent->seq_ops = pid_dentry_base[j].seq_ops; + } + + if (pid_dentry_base[j].single_show) + { + ent->single_show = pid_dentry_base[j].single_show; + } + + proc_release(ent); + } + } + proc_release(dentry); + } + + return 0; +} + +int msh_proc_pid(int argc, char **argv) +{ + if (argc > 1) + { + for (int i = 1; i <= argc - 1; i++) + { + proc_pid(atoi(argv[i])); + } + } + + return 0; +} +MSH_CMD_EXPORT_ALIAS(msh_proc_pid, proc_pid, proc pid); + +#endif diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_self.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_self.c new file mode 100644 index 0000000..a1082ea --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_self.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include + +#if defined(RT_USING_SMART) + +#include + + +int proc_self_readlink(struct proc_dentry *dentry, char *buf, int len) +{ + struct rt_lwp *lwp = RT_NULL; + + lwp = lwp_self(); + if (lwp) + { + rt_snprintf(buf, len, "%d", lwp_to_pid(lwp)); + buf[len - 1] = 0; + return rt_strlen(buf); + } + else + { + rt_snprintf(buf, len, "null"); + buf[len - 1] = 0; + return rt_strlen(buf); + } + + return -1; +} + +static const struct proc_ops proc_pid_fd_ops = { + .readlink = proc_self_readlink, +}; + +int proc_self_init(void) +{ + struct proc_dentry *ent; + + ent = proc_symlink("self", NULL, "NULL"); + if (ent) + { + ent->ops = &proc_pid_fd_ops; + } + proc_release(ent); + + return 0; +} +INIT_ENV_EXPORT(proc_self_init); + +#endif diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_stat.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_stat.c new file mode 100644 index 0000000..aeba99d --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_stat.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include + + +static void *seq_start(struct dfs_seq_file *seq, off_t *index) +{ + off_t i = *index; // seq->index + + return NULL + (i == 0); +} + +static void seq_stop(struct dfs_seq_file *seq, void *data) +{ +} + +static void *seq_next(struct dfs_seq_file *seq, void *data, off_t *index) +{ + /* data: The return value of the start or next*/ + off_t i = *index + 1; // seq->index + + *index = i; + + return NULL; +} + +static int seq_show(struct dfs_seq_file *seq, void *data) +{ + int i; + rt_cpu_t pcpu; + rt_uint64_t user_total = 0; + rt_uint64_t system_total = 0; + rt_uint64_t idle_total = 0; + + for (i = 0; i < RT_CPUS_NR; i++) + { + pcpu = rt_cpu_index(i); + user_total = user_total + pcpu->cpu_stat.user; + system_total = system_total + pcpu->cpu_stat.system; + idle_total = idle_total + pcpu->cpu_stat.idle; + } + dfs_seq_printf(seq, "cpu %llu 0 %llu %llu 0 0 0 0 0 0\n", user_total, system_total, idle_total); + + for (i = 0; i < RT_CPUS_NR; i++) + { + pcpu = rt_cpu_index(i); + dfs_seq_printf(seq, "cpu%d ",i); + dfs_seq_printf(seq, "%llu ",pcpu->cpu_stat.user);//user + dfs_seq_printf(seq, "0 ");//nice + dfs_seq_printf(seq, "%llu ",pcpu->cpu_stat.system);//system + dfs_seq_printf(seq, "%llu ",pcpu->cpu_stat.idle);//idle + dfs_seq_printf(seq, "0 ");//iowait + dfs_seq_printf(seq, "0 ");//irq + dfs_seq_printf(seq, "0 ");//softirq + dfs_seq_printf(seq, "0 0 0\n");//steal,guest,guest_nice + + } + + return 0; +} + +static const struct dfs_seq_ops seq_ops = { + .start = seq_start, + .stop = seq_stop, + .next = seq_next, + .show = seq_show, +}; + +rt_weak const struct dfs_seq_ops *stat_get_seq_ops(void) +{ + return &seq_ops; +} + +static int proc_open(struct dfs_file *file) +{ + return dfs_seq_open(file, stat_get_seq_ops()); +} + +static int proc_close(struct dfs_file *file) +{ + return dfs_seq_release(file); +} + +static const struct dfs_file_ops file_ops = { + .open = proc_open, + .read = dfs_seq_read, + .lseek = dfs_seq_lseek, + .close = proc_close, +}; + +int proc_stat_init(void) +{ + struct proc_dentry *dentry = proc_create_data("stat", 0, NULL, &file_ops, NULL); + proc_release(dentry); + + return 0; +} +INIT_ENV_EXPORT(proc_stat_init); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_tty.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_tty.c new file mode 100644 index 0000000..dc77e4c --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_tty.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include + + +static void *seq_start(struct dfs_seq_file *seq, off_t *index) +{ + off_t i = *index; // seq->index + + return NULL + (i == 0); +} + +static void seq_stop(struct dfs_seq_file *seq, void *data) +{ +} + +static void *seq_next(struct dfs_seq_file *seq, void *data, off_t *index) +{ + /* data: The return value of the start or next*/ + off_t i = *index + 1; // seq->index + + *index = i; + + return NULL; +} + +static int seq_show(struct dfs_seq_file *seq, void *data) +{ + /* data: The return value of the start or next*/ + dfs_seq_puts(seq, "todo\n"); + + return 0; +} + +static const struct dfs_seq_ops seq_ops = { + .start = seq_start, + .stop = seq_stop, + .next = seq_next, + .show = seq_show, +}; + +void proc_tty_register_driver(void *driver) +{ + //todo +} + +void proc_tty_unregister_driver(void *driver) +{ + //todo +} + +int proc_tty_init(void) +{ + struct proc_dentry *dentry; + + dentry = proc_mkdir("tty", NULL); + if (!dentry) + return -1; + + proc_release(dentry); + + dentry = proc_mkdir("tty/ldisc", NULL); + proc_release(dentry); + + dentry = proc_mkdir_mode("tty/driver", S_IRUSR|S_IXUSR, NULL); + proc_release(dentry); + + dentry = proc_create_data("tty/ldiscs", 0, NULL, NULL, NULL); + if (dentry) + { + dentry->seq_ops = &seq_ops; + } + proc_release(dentry); + + dentry = proc_create_data("tty/drivers", 0, NULL, NULL, NULL); + if (dentry) + { + dentry->seq_ops = &seq_ops; + } + proc_release(dentry); + + return 0; +} +INIT_ENV_EXPORT(proc_tty_init); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_uptime.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_uptime.c new file mode 100644 index 0000000..f16ab72 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_uptime.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include + + +static int single_show(struct dfs_seq_file *seq, void *data) +{ + dfs_seq_printf(seq, "%lu.%02lu %lu.%02lu\n", + (unsigned long)rt_tick_get_millisecond() / 1000, (unsigned long)(rt_tick_get_millisecond() % 1000) / 100, + (unsigned long)rt_tick_get_millisecond() / 1000, (unsigned long)(rt_tick_get_millisecond() % 1000) / 100); + + return 0; +} + +int proc_uptime_init(void) +{ + struct proc_dentry *dentry = proc_create_single_data("uptime", 0, NULL, single_show, NULL); + proc_release(dentry); + + return 0; +} +INIT_ENV_EXPORT(proc_uptime_init); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_version.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_version.c new file mode 100644 index 0000000..1ca8035 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/proc_version.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "proc.h" +#include "procfs.h" + +#include +#include + +#include +#include + +#include + + +static int single_show(struct dfs_seq_file *seq, void *data) +{ + dfs_seq_puts(seq, "\n \\ | /\n"); +#ifdef RT_USING_SMART + dfs_seq_puts(seq, "- RT - Thread Smart Operating System\n"); +#else + dfs_seq_puts(seq, "- RT - Thread Operating System\n"); +#endif + dfs_seq_printf(seq, " / | \\ %d.%d.%d build %s %s\n", + (rt_int32_t)RT_VERSION_MAJOR, (rt_int32_t)RT_VERSION_MINOR, (rt_int32_t)RT_VERSION_PATCH, + __DATE__, __TIME__); + dfs_seq_puts(seq, " 2006 - 2022 Copyright by RT-Thread team\n"); + + return 0; +} + +int proc_version_init(void) +{ + struct proc_dentry *dentry = proc_create_single_data("version", 0, NULL, single_show, NULL); + proc_release(dentry); + + return 0; +} +INIT_ENV_EXPORT(proc_version_init); diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/procfs.c b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/procfs.c new file mode 100644 index 0000000..c8b5c14 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/procfs.c @@ -0,0 +1,447 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "proc.h" +#include "procfs.h" + +#define PROC_DEBUG(...) //rt_kprintf + +static int dfs_procfs_open(struct dfs_file *file) +{ + rt_err_t ret = RT_EOK; + struct proc_dentry *entry = (struct proc_dentry *)file->vnode->data; + + + RT_ASSERT(file->ref_count > 0); + + // this file is opened and in an fdtable + if (file->ref_count > 1) + { + file->fpos = 0; + return ret; + } + + if (entry->fops && entry->fops->open) + { + ret = entry->fops->open(file); + } + + PROC_DEBUG(" %s %d >> %s ret: %d\n", __func__, __LINE__, file->dentry->pathname, ret); + + return ret; +} + +static int dfs_procfs_close(struct dfs_file *file) +{ + rt_err_t ret = RT_EOK; + struct proc_dentry *entry = (struct proc_dentry *)file->vnode->data; + + RT_ASSERT(file->vnode->ref_count > 0); + if (file->vnode->ref_count > 1) + { + return ret; + } + + if (entry && entry->fops && entry->fops->close) + { + ret = entry->fops->close(file); + } + + PROC_DEBUG(" %s %d >> %s ret: %d\n", __func__, __LINE__, file->dentry->pathname, ret); + + return ret; +} + +static ssize_t dfs_procfs_read(struct dfs_file *file, void *buf, size_t count, off_t *pos) +{ + ssize_t ret = -RT_ERROR; + struct proc_dentry *entry = (struct proc_dentry *)file->vnode->data; + + if (entry && entry->fops && entry->fops->read) + { + ret = entry->fops->read(file, buf, count, pos); + } + + PROC_DEBUG(" %s %d >> %s ret: %d\n", __func__, __LINE__, file->dentry->pathname, ret); + + return ret; +} + +static ssize_t dfs_procfs_write(struct dfs_file *file, const void *buf, size_t count, off_t *pos) +{ + ssize_t ret = -RT_ERROR; + struct proc_dentry *entry = (struct proc_dentry *)file->vnode->data; + + if (entry && entry->fops && entry->fops->write) + { + ret = entry->fops->write(file, buf, count, pos); + } + + PROC_DEBUG(" %s %d >> %s ret: %d\n", __func__, __LINE__, file->dentry->pathname, ret); + + return ret; +} + +static int dfs_procfs_ioctl(struct dfs_file *file, int cmd, void *args) +{ + int ret = -RT_ERROR; + struct proc_dentry *entry = (struct proc_dentry *)file->vnode->data; + + if (entry && entry->fops && entry->fops->ioctl) + { + ret = entry->fops->ioctl(file, cmd, args); + } + + PROC_DEBUG(" %s %d >> %s ret: %d\n", __func__, __LINE__, file->dentry->pathname, ret); + + return ret; +} + +static int dfs_procfs_getdents(struct dfs_file *file, struct dirent *dirp, uint32_t count) +{ + int ret = 0; + rt_uint32_t index = 0; + struct dirent *d; + struct proc_dentry *entry = (struct proc_dentry *)file->vnode->data; + + if (entry) + { + struct proc_dentry *iter = RT_NULL, *tmp; + + /* make integer count */ + count = (count / sizeof(struct dirent)); + if (count == 0) + { + return -EINVAL; + } + + dfs_vfs_for_each_subnode(iter, tmp, entry, node) + { + if (iter == RT_NULL) + { + break; + } + + if (index >= file->fpos) + { + d = dirp + index - file->fpos; + + if (S_ISDIR(entry->mode)) + { + d->d_type = DT_DIR; + } + else if (S_ISLNK(entry->mode)) + { + d->d_type = DT_SYMLINK; + } + else + { + d->d_type = DT_REG; + } + + d->d_namlen = rt_strlen(iter->name); + d->d_reclen = (rt_uint16_t)sizeof(struct dirent); + rt_strncpy(d->d_name, iter->name, rt_strlen(iter->name) + 1); + + ret ++; + } + + index++; + if (index - file->fpos >= count) + { + break; + } + } + + if (ret > 0) + { + file->fpos = index; + } + + if (entry->fops && entry->fops->getdents && ret < count) + { + int r; + + file->fpos -= index; + + r = entry->fops->getdents(file, dirp + ret, (count - ret) * sizeof(struct dirent)); + + ret = ret * sizeof(struct dirent); + + if (r > 0) + { + ret += r; + } + + file->fpos += index; + } + else + { + ret = ret * sizeof(struct dirent); + } + } + + PROC_DEBUG(" %s %d >> %s ret: %d\n", __func__, __LINE__, file->dentry->pathname, ret); + + return ret; +} + +static int dfs_procfs_poll(struct dfs_file *file, struct rt_pollreq *req) +{ + int ret = -RT_ERROR; + struct proc_dentry *entry = (struct proc_dentry *)file->vnode->data; + + if (entry && entry->fops && entry->fops->poll) + { + ret = entry->fops->poll(file, req); + } + + PROC_DEBUG(" %s %d >> %s ret: %d\n", __func__, __LINE__, file->dentry->pathname, ret); + + return ret; +} + +static int dfs_procfs_flush(struct dfs_file *file) +{ + int ret = -RT_ERROR; + struct proc_dentry *entry = (struct proc_dentry *)file->vnode->data; + + if (entry && entry->fops && entry->fops->flush) + { + ret = entry->fops->flush(file); + } + + PROC_DEBUG(" %s %d >> %s ret: %d\n", __func__, __LINE__, file->dentry->pathname, ret); + + return ret; +} + +static int dfs_procfs_mount(struct dfs_mnt *mnt, unsigned long rwflag, const void *data) +{ + RT_ASSERT(mnt != RT_NULL); + + return RT_EOK; +} + +static int dfs_procfs_umount(struct dfs_mnt *mnt) +{ + RT_ASSERT(mnt != RT_NULL); + + return RT_EOK; +} + +static int dfs_procfs_readlink(struct dfs_dentry *dentry, char *buf, int len) +{ + int ret = 0; + struct proc_dentry *entry = dfs_proc_find(dentry->pathname); + + if (entry) + { + if (S_ISLNK(entry->mode) && entry->data) + { + if (entry->ops && entry->ops->readlink) + { + ret = entry->ops->readlink(entry, buf, len); + } + else + { + rt_strncpy(buf, (const char *)entry->data, len); + buf[len - 1] = '\0'; + ret = rt_strlen(buf); + } + } + + proc_release(entry); + } + + PROC_DEBUG(" %s %d >> %s ret: %d\n", __func__, __LINE__, dentry->pathname, ret); + + return ret; +} + +static int dfs_procfs_unlink(struct dfs_dentry *dentry) +{ + PROC_DEBUG(" %s %d >> %s ret: %d\n", __func__, __LINE__, dentry->pathname, -1); + return -RT_ERROR; +} + +static int dfs_procfs_stat(struct dfs_dentry *dentry, struct stat *st) +{ + int ret = RT_EOK; + struct dfs_vnode *vnode; + + if (dentry && dentry->vnode) + { + vnode = dentry->vnode; + + st->st_dev = (dev_t)(dentry->mnt->dev_id); + st->st_ino = (ino_t)dfs_dentry_full_path_crc32(dentry); + + st->st_gid = vnode->gid; + st->st_uid = vnode->uid; + st->st_mode = vnode->mode; + st->st_nlink = vnode->nlink; + st->st_size = vnode->size; + st->st_mtim.tv_nsec = vnode->mtime.tv_nsec; + st->st_mtim.tv_sec = vnode->mtime.tv_sec; + st->st_ctim.tv_nsec = vnode->ctime.tv_nsec; + st->st_ctim.tv_sec = vnode->ctime.tv_sec; + st->st_atim.tv_nsec = vnode->atime.tv_nsec; + st->st_atim.tv_sec = vnode->atime.tv_sec; + } + + PROC_DEBUG(" %s %d >> %s ret: %d\n", __func__, __LINE__, dentry->pathname, ret); + + return ret; +} + +static int dfs_procfs_statfs(struct dfs_mnt *mnt, struct statfs *buf) +{ + if (mnt && buf) + { + buf->f_bsize = 512; + buf->f_blocks = 2048 * 64; // 64M + buf->f_bfree = buf->f_blocks; + buf->f_bavail = buf->f_bfree; + } + + PROC_DEBUG(" %s %d\n", __func__, __LINE__); + + return RT_EOK; +} + +static struct dfs_vnode *dfs_procfs_lookup(struct dfs_dentry *dentry) +{ + struct dfs_vnode *vnode = RT_NULL; + struct proc_dentry *entry = dfs_proc_find(dentry->pathname); + + if (entry) + { + vnode = dfs_vnode_create(); + if (vnode) + { + vnode->nlink = 1; + vnode->size = 0; + if (S_ISDIR(entry->mode)) + { + vnode->mode = entry->mode; + vnode->type = FT_DIRECTORY; + } + else if (S_ISLNK(entry->mode)) + { + vnode->mode = entry->mode; + vnode->type = FT_SYMLINK; + } + else + { + vnode->mode = entry->mode; + vnode->type = FT_REGULAR; + } + + vnode->data = entry; + vnode->mnt = dentry->mnt; + } + + proc_release(entry); + } + + PROC_DEBUG(" %s %d >> %s\n", __func__, __LINE__, dentry->pathname); + + return vnode; +} + +static struct dfs_vnode *dfs_procfs_create_vnode(struct dfs_dentry *dentry, int type, mode_t mode) +{ + return RT_NULL; +} + +static int dfs_procfs_free_vnode(struct dfs_vnode *vnode) +{ + return 0; +} + +static const struct dfs_file_ops _procfs_fops = +{ + .open = dfs_procfs_open, + .close = dfs_procfs_close, + .lseek = generic_dfs_lseek, + .read = dfs_procfs_read, + .write = dfs_procfs_write, + .ioctl = dfs_procfs_ioctl, + .getdents = dfs_procfs_getdents, + .poll = dfs_procfs_poll, + .flush = dfs_procfs_flush, +}; + +static const struct dfs_filesystem_ops _procfs_ops = +{ + .name = "procfs", + + .default_fops = &_procfs_fops, + + .mount = dfs_procfs_mount, + .umount = dfs_procfs_umount, + .readlink = dfs_procfs_readlink, + .unlink = dfs_procfs_unlink, + .stat = dfs_procfs_stat, + .statfs = dfs_procfs_statfs, + .lookup = dfs_procfs_lookup, + .create_vnode = dfs_procfs_create_vnode, + .free_vnode = dfs_procfs_free_vnode, +}; + +static struct dfs_filesystem_type _procfs = +{ + .fs_ops = &_procfs_ops, +}; + +int dfs_procfs_init(void) +{ + /* register procfs file system */ + dfs_register(&_procfs); + + return 0; +} +INIT_COMPONENT_EXPORT(dfs_procfs_init); + +int proc_read_data(struct dfs_file *file, void *buf, size_t count, off_t *pos) +{ + if (file->fpos >= file->vnode->size) + { + return 0; + } + + if (file->data) + { + count = file->vnode->size - file->fpos >= count ? count : file->vnode->size - file->fpos; + rt_strncpy(buf, file->data + file->fpos, count); + + file->fpos += count; + *pos = file->fpos; + } + else + { + return 0; + } + + return count; +} diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/procfs/procfs.h b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/procfs.h new file mode 100644 index 0000000..6e921ae --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/filesystems/procfs/procfs.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __PROC_FS_H__ +#define __PROC_FS_H__ + +#include + +int dfs_procfs_init(void); + +int proc_read_data(struct dfs_file *file, void *buf, size_t count, off_t *pos); + +#endif diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/ptyfs/ptyfs.c b/rt-thread/components/dfs/dfs_v2/filesystems/ptyfs/ptyfs.c index c6f4f3d..75bffdf 100644 --- a/rt-thread/components/dfs/dfs_v2/filesystems/ptyfs/ptyfs.c +++ b/rt-thread/components/dfs/dfs_v2/filesystems/ptyfs/ptyfs.c @@ -262,7 +262,7 @@ ptsno_t ptyfs_register_pts(rt_device_t ptmx, rt_device_t pts) pts_file = rt_calloc(1, sizeof(struct ptyfs_file)); if (pts_file) { - snprintf(pts_file->basename, DIRENT_NAME_MAX, "%lu", rc); + snprintf(pts_file->basename, DIRENT_NAME_MAX, "%lu", (unsigned long)rc); ptyfile_init(pts_file, sb, 0, PTYFS_TYPE_FILE_SLAVE, PTS_DEFAULT_FILE_MODE, pts); ptyfile_add_to_root(sb, pts_file); @@ -296,7 +296,7 @@ rt_err_t ptyfs_unregister_pts(rt_device_t ptmx, ptsno_t ptsno) else { /* get path and findout device */ - snprintf(path_buf, sizeof(path_buf), "%lu", ptsno); + snprintf(path_buf, sizeof(path_buf), "%lu", (unsigned long)ptsno); pts_file = ptyfile_lookup(sb, path_buf); if (pts_file) { diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/romfs/dfs_romfs.c b/rt-thread/components/dfs/dfs_v2/filesystems/romfs/dfs_romfs.c index 7cb30b3..6350ad7 100644 --- a/rt-thread/components/dfs/dfs_v2/filesystems/romfs/dfs_romfs.c +++ b/rt-thread/components/dfs/dfs_v2/filesystems/romfs/dfs_romfs.c @@ -365,6 +365,7 @@ static const struct dfs_file_ops _rom_fops = { .open = dfs_romfs_open, .close = dfs_romfs_close, + .ioctl = dfs_romfs_ioctl, .lseek = generic_dfs_lseek, .read = dfs_romfs_read, .getdents = dfs_romfs_getdents, diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.c b/rt-thread/components/dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.c index 1c2a509..c1ff4a1 100644 --- a/rt-thread/components/dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.c +++ b/rt-thread/components/dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.c @@ -99,15 +99,13 @@ static int _get_subdir(const char *path, char *name) static int _free_subdir(struct tmpfs_file *dfile) { - struct tmpfs_file *file; - rt_list_t *list, *temp_list; + struct tmpfs_file *file = RT_NULL, *tmp; struct tmpfs_sb *superblock; RT_ASSERT(dfile->type == TMPFS_TYPE_DIR); - rt_list_for_each_safe(list, temp_list, &dfile->subdirs) + dfs_vfs_for_each_subnode(file, tmp, dfile, node) { - file = rt_list_entry(list, struct tmpfs_file, sibling); if (file->type == TMPFS_TYPE_DIR) { _free_subdir(file); @@ -122,7 +120,7 @@ static int _free_subdir(struct tmpfs_file *dfile) RT_ASSERT(superblock != NULL); rt_spin_lock(&superblock->lock); - rt_list_remove(&(file->sibling)); + dfs_vfs_remove_node(&file->node); rt_spin_unlock(&superblock->lock); rt_free(file); @@ -141,13 +139,11 @@ static int dfs_tmpfs_mount(struct dfs_mnt *mnt, { superblock->df_size = sizeof(struct tmpfs_sb); superblock->magic = TMPFS_MAGIC; - rt_list_init(&superblock->sibling); superblock->root.name[0] = '/'; superblock->root.sb = superblock; superblock->root.type = TMPFS_TYPE_DIR; - rt_list_init(&superblock->root.sibling); - rt_list_init(&superblock->root.subdirs); + dfs_vfs_init_node(&superblock->root.node); rt_spin_lock_init(&superblock->lock); @@ -236,8 +232,7 @@ struct tmpfs_file *dfs_tmpfs_lookup(struct tmpfs_sb *superblock, { const char *subpath, *curpath, *filename = RT_NULL; char subdir_name[TMPFS_NAME_MAX]; - struct tmpfs_file *file, *curfile; - rt_list_t *list; + struct tmpfs_file *file, *curfile, *tmp; subpath = path; while (*subpath == '/' && *subpath) @@ -265,9 +260,8 @@ find_subpath: rt_spin_lock(&superblock->lock); - rt_list_for_each(list, &curfile->subdirs) + dfs_vfs_for_each_subnode(file, tmp, curfile, node) { - file = rt_list_entry(list, struct tmpfs_file, sibling); if (filename) /* find file */ { if (rt_strcmp(file->name, filename) == 0) @@ -503,8 +497,7 @@ static int dfs_tmpfs_getdents(struct dfs_file *file, { rt_size_t index, end; struct dirent *d; - struct tmpfs_file *d_file, *n_file; - rt_list_t *list; + struct tmpfs_file *d_file, *n_file, *tmp; struct tmpfs_sb *superblock; d_file = (struct tmpfs_file *)file->vnode->data; @@ -527,9 +520,8 @@ static int dfs_tmpfs_getdents(struct dfs_file *file, index = 0; count = 0; - rt_list_for_each(list, &d_file->subdirs) + dfs_vfs_for_each_subnode(n_file, tmp, d_file, node) { - n_file = rt_list_entry(list, struct tmpfs_file, sibling); if (index >= (rt_size_t)file->fpos) { d = dirp + count; @@ -573,7 +565,7 @@ static int dfs_tmpfs_unlink(struct dfs_dentry *dentry) return -ENOENT; rt_spin_lock(&superblock->lock); - rt_list_remove(&(d_file->sibling)); + dfs_vfs_remove_node(&d_file->node); rt_spin_unlock(&superblock->lock); if (rt_atomic_load(&(dentry->ref_count)) == 1) @@ -631,13 +623,13 @@ static int dfs_tmpfs_rename(struct dfs_dentry *old_dentry, struct dfs_dentry *ne RT_ASSERT(p_file != NULL); rt_spin_lock(&superblock->lock); - rt_list_remove(&(d_file->sibling)); + dfs_vfs_remove_node(&d_file->node); rt_spin_unlock(&superblock->lock); strncpy(d_file->name, file_name, TMPFS_NAME_MAX); rt_spin_lock(&superblock->lock); - rt_list_insert_after(&(p_file->subdirs), &(d_file->sibling)); + dfs_vfs_append_node(&p_file->node, &d_file->node); rt_spin_unlock(&superblock->lock); rt_free(parent_path); @@ -745,8 +737,7 @@ static struct dfs_vnode *dfs_tmpfs_create_vnode(struct dfs_dentry *dentry, int t strncpy(d_file->name, file_name, TMPFS_NAME_MAX); - rt_list_init(&(d_file->subdirs)); - rt_list_init(&(d_file->sibling)); + dfs_vfs_init_node(&d_file->node); d_file->data = NULL; d_file->size = 0; d_file->sb = superblock; @@ -767,7 +758,7 @@ static struct dfs_vnode *dfs_tmpfs_create_vnode(struct dfs_dentry *dentry, int t #endif } rt_spin_lock(&superblock->lock); - rt_list_insert_after(&(p_file->subdirs), &(d_file->sibling)); + dfs_vfs_append_node(&p_file->node, &d_file->node); rt_spin_unlock(&superblock->lock); vnode->mnt = dentry->mnt; diff --git a/rt-thread/components/dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.h b/rt-thread/components/dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.h index 365f1e0..8f822c6 100644 --- a/rt-thread/components/dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.h +++ b/rt-thread/components/dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.h @@ -12,6 +12,7 @@ #define __DFS_TMPFS_H__ #include +#include #define TMPFS_NAME_MAX 32 #define TMPFS_MAGIC 0x0B0B0B0B @@ -25,8 +26,7 @@ struct tmpfs_file { rt_uint32_t type; /* file type */ char name[TMPFS_NAME_MAX]; /* file name */ - rt_list_t subdirs; /* file subdir list */ - rt_list_t sibling; /* file sibling list */ + struct dfs_vfs_node node; /* file node in the tmpfs */ struct tmpfs_sb *sb; /* superblock ptr */ rt_uint8_t *data; /* file date ptr */ rt_size_t size; /* file size */ diff --git a/rt-thread/components/dfs/dfs_v2/include/dfs_fs.h b/rt-thread/components/dfs/dfs_v2/include/dfs_fs.h index d30967a..dcf2fa2 100644 --- a/rt-thread/components/dfs/dfs_v2/include/dfs_fs.h +++ b/rt-thread/components/dfs/dfs_v2/include/dfs_fs.h @@ -20,6 +20,38 @@ extern "C" { #endif +#define MS_RDONLY 1 +#define MS_NOSUID 2 +#define MS_NODEV 4 +#define MS_NOEXEC 8 +#define MS_SYNCHRONOUS 16 +#define MS_REMOUNT 32 +#define MS_MANDLOCK 64 +#define MS_DIRSYNC 128 +#define MS_NOATIME 1024 +#define MS_NODIRATIME 2048 +#define MS_BIND 4096 +#define MS_MOVE 8192 +#define MS_REC 16384 +#define MS_SILENT 32768 +#define MS_POSIXACL (1<<16) +#define MS_UNBINDABLE (1<<17) +#define MS_PRIVATE (1<<18) +#define MS_SLAVE (1<<19) +#define MS_SHARED (1<<20) +#define MS_RELATIME (1<<21) +#define MS_KERNMOUNT (1<<22) +#define MS_I_VERSION (1<<23) +#define MS_STRICTATIME (1<<24) +#define MS_LAZYTIME (1<<25) +#define MS_NOREMOTELOCK (1<<27) +#define MS_NOSEC (1<<28) +#define MS_BORN (1<<29) +#define MS_ACTIVE (1<<30) +#define MS_NOUSER (1U<<31) + +#define MS_RMT_MASK (MS_RDONLY|MS_SYNCHRONOUS|MS_MANDLOCK|MS_I_VERSION|MS_LAZYTIME) + /* file system partition table */ struct dfs_partition { @@ -87,6 +119,7 @@ int dfs_unregister(struct dfs_filesystem_type *fs); int dfs_register(struct dfs_filesystem_type *fs); const char *dfs_filesystem_get_mounted_path(struct rt_device *device); +int dfs_remount(const char *path, rt_ubase_t flags, void *data); int dfs_mount(const char *device_name, const char *path, const char *filesystemtype, diff --git a/rt-thread/components/dfs/dfs_v2/include/dfs_mnt.h b/rt-thread/components/dfs/dfs_v2/include/dfs_mnt.h index 207c9b6..da99ec2 100644 --- a/rt-thread/components/dfs/dfs_v2/include/dfs_mnt.h +++ b/rt-thread/components/dfs/dfs_v2/include/dfs_mnt.h @@ -39,6 +39,8 @@ struct dfs_mnt #define MNT_IS_UMOUNT 0x8 /* the mnt is unmount */ #define MNT_IS_LOCKED 0x10 /* the mnt is locked */ #define MNT_FORCE 0x20 /* the mnt force unmount */ +#define MNT_LAZY_UMNT 0x40 /* the mnt has pending umount */ +#define MNT_RDONLY 0x80 /* the mnt is read only */ rt_atomic_t ref_count; /* reference count */ @@ -60,9 +62,16 @@ const char *dfs_mnt_get_mounted_path(struct rt_device *device); struct dfs_mnt* dfs_mnt_ref(struct dfs_mnt* mnt); int dfs_mnt_unref(struct dfs_mnt* mnt); +int dfs_mnt_umount(struct dfs_mnt *mnt, int flags); +int dfs_mnt_setflags(struct dfs_mnt *mnt, int flags); + rt_bool_t dfs_mnt_has_child_mnt(struct dfs_mnt *mnt, const char* fullpath); int dfs_mnt_foreach(struct dfs_mnt* (*func)(struct dfs_mnt *mnt, void *parameter), void *parameter); +int dfs_mnt_umount_iter(rt_bool_t (*filter)(struct dfs_mnt *mnt, void *parameter), void *parameter); + +typedef void (*dfs_mnt_umnt_cb_t)(struct dfs_mnt *mnt); +RT_OBJECT_HOOKLIST_DECLARE(dfs_mnt_umnt_cb_t, dfs_mnt_umnt); #ifdef __cplusplus } diff --git a/rt-thread/components/dfs/dfs_v2/include/dfs_pcache.h b/rt-thread/components/dfs/dfs_v2/include/dfs_pcache.h index 01abfe3..5452196 100644 --- a/rt-thread/components/dfs/dfs_v2/include/dfs_pcache.h +++ b/rt-thread/components/dfs/dfs_v2/include/dfs_pcache.h @@ -118,6 +118,7 @@ int dfs_aspace_mmap_write(struct dfs_file *file, struct rt_varea *varea, void *d void dfs_pcache_release(size_t count); void dfs_pcache_unmount(struct dfs_mnt *mnt); +void dfs_pcache_clean(struct dfs_mnt *mnt); #ifdef __cplusplus } diff --git a/rt-thread/components/dfs/dfs_v2/include/dfs_seq_file.h b/rt-thread/components/dfs/dfs_v2/include/dfs_seq_file.h index 6dbc30f..f0c1de7 100644 --- a/rt-thread/components/dfs/dfs_v2/include/dfs_seq_file.h +++ b/rt-thread/components/dfs/dfs_v2/include/dfs_seq_file.h @@ -56,7 +56,7 @@ static inline void dfs_seq_setwidth(struct dfs_seq_file *seq, size_t size) int dfs_seq_open(struct dfs_file *file, const struct dfs_seq_ops *ops); ssize_t dfs_seq_read(struct dfs_file *file, void *buf, size_t size, off_t *pos); -ssize_t dfs_seq_lseek(struct dfs_file *file, off_t offset, int whence); +off_t dfs_seq_lseek(struct dfs_file *file, off_t offset, int whence); int dfs_seq_release(struct dfs_file *file); int dfs_seq_write(struct dfs_seq_file *seq, const void *data, size_t len); diff --git a/rt-thread/components/dfs/dfs_v2/include/dfs_vfs.h b/rt-thread/components/dfs/dfs_v2/include/dfs_vfs.h new file mode 100644 index 0000000..3674192 --- /dev/null +++ b/rt-thread/components/dfs/dfs_v2/include/dfs_vfs.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __DFS_VFS_H__ +#define __DFS_VFS_H__ + +#include "dfs_file.h" +#include "dfs_fs.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +struct dfs_vfs_node +{ + rt_list_t subnode; /* file subnode list */ + rt_list_t sibling; /* file sibling list */ +}; + +rt_inline void dfs_vfs_init_node(struct dfs_vfs_node *node) +{ + rt_list_init(&node->subnode); + rt_list_init(&node->sibling); +} + +rt_inline void dfs_vfs_append_node(struct dfs_vfs_node *dir, struct dfs_vfs_node *node) +{ + rt_list_insert_after(&(dir->subnode), &(node->sibling)); +} + +rt_inline void dfs_vfs_remove_node(struct dfs_vfs_node *node) +{ + rt_list_remove(&(node->sibling)); +} + +#define dfs_vfs_for_each_subnode(node, tmp, dir, member) \ + rt_list_for_each_entry_safe(node, tmp, &dir->member.subnode, member.sibling) + +#ifdef __cplusplus +} +#endif + +#endif /*__DFS_VFS_H__*/ diff --git a/rt-thread/components/dfs/dfs_v2/src/dfs.c b/rt-thread/components/dfs/dfs_v2/src/dfs.c index 939e4dd..527ba89 100644 --- a/rt-thread/components/dfs/dfs_v2/src/dfs.c +++ b/rt-thread/components/dfs/dfs_v2/src/dfs.c @@ -537,6 +537,7 @@ int dfs_dup(int oldfd, int startfd) fdt = dfs_fdtable_get(); if ((oldfd < 0) || (oldfd >= fdt->maxfd)) { + rt_set_errno(-EBADF); goto exit; } if (!fdt->fds[oldfd]) @@ -668,12 +669,17 @@ sysret_t sys_dup(int oldfd) int sys_dup(int oldfd) #endif { + int err = 0; int newfd = dfs_dup(oldfd, (dfs_fdtable_get() == &_fdtab) ? DFS_STDIO_OFFSET : 0); + if(newfd < 0) + { + err = rt_get_errno(); + } #ifdef RT_USING_SMART - return (sysret_t)newfd; + return err < 0 ? err : newfd; #else - return newfd; + return err < 0 ? err : newfd; #endif } diff --git a/rt-thread/components/dfs/dfs_v2/src/dfs_file.c b/rt-thread/components/dfs/dfs_v2/src/dfs_file.c index 53e110e..57ff2e9 100644 --- a/rt-thread/components/dfs/dfs_v2/src/dfs_file.c +++ b/rt-thread/components/dfs/dfs_v2/src/dfs_file.c @@ -1379,6 +1379,7 @@ int dfs_file_link(const char *oldname, const char *newname) if (dfs_file_isdir(oldname) == 0) { + rt_set_errno(-EPERM); return ret; } @@ -1567,6 +1568,10 @@ int dfs_file_symlink(const char *target, const char *linkpath) rt_free(parent); } } + else + { + rt_set_errno(-EPERM); + } if (fullpath != linkpath) rt_free(fullpath); diff --git a/rt-thread/components/dfs/dfs_v2/src/dfs_fs.c b/rt-thread/components/dfs/dfs_v2/src/dfs_fs.c index e65ccee..ee077cd 100644 --- a/rt-thread/components/dfs/dfs_v2/src/dfs_fs.c +++ b/rt-thread/components/dfs/dfs_v2/src/dfs_fs.c @@ -95,6 +95,52 @@ int dfs_unregister(struct dfs_filesystem_type *fs) return ret; } +#define REMNT_UNSUPP_FLAGS (~(MS_REMOUNT | MS_RMT_MASK)) +int dfs_remount(const char *path, rt_ubase_t flags, void *data) +{ + int rc = 0; + char *fullpath = RT_NULL; + struct dfs_mnt *mnt = RT_NULL; + + if (flags & REMNT_UNSUPP_FLAGS) + { + return -EINVAL; + } + + fullpath = dfs_normalize_path(RT_NULL, path); + if (!fullpath) + { + rc = -ENOENT; + } + else + { + DLOG(msg, "dfs", "mnt", DLOG_MSG, "mnt = dfs_mnt_lookup(%s)", fullpath); + mnt = dfs_mnt_lookup(fullpath); + if (mnt) + { + dfs_lock(); + dfs_mnt_setflags(mnt, flags); + dfs_unlock(); + } + else + { + struct stat buf = {0}; + if (dfs_file_stat(fullpath, &buf) == 0 && S_ISBLK(buf.st_mode)) + { + /* path was not already mounted on target */ + rc = -EINVAL; + } + else + { + /* path is not a directory */ + rc = -ENOTDIR; + } + } + } + + return rc; +} + /* * parent(mount path) * mnt_parent <- - - - - - - + @@ -127,7 +173,7 @@ int dfs_mount(const char *device_name, } else { - rt_set_errno(ENOENT); + rt_set_errno(ENODEV); ret = -1; } @@ -300,7 +346,7 @@ int dfs_mount(const char *device_name, int dfs_umount(const char *specialfile, int flags) { - int ret = -RT_ERROR; + int ret = -1; char *fullpath = RT_NULL; struct dfs_mnt *mnt = RT_NULL; @@ -314,7 +360,7 @@ int dfs_umount(const char *specialfile, int flags) if (strcmp(mnt->fullpath, fullpath) == 0) { /* is the mount point */ - rt_atomic_t ref_count = rt_atomic_load(&(mnt->ref_count)); + rt_base_t ref_count = rt_atomic_load(&(mnt->ref_count)); if (!(mnt->flags & MNT_IS_LOCKED) && rt_list_isempty(&mnt->child) && (ref_count == 1 || (flags & MNT_FORCE))) { @@ -327,17 +373,19 @@ int dfs_umount(const char *specialfile, int flags) } else { - LOG_E("the file system is busy!"); + LOG_I("the file system is busy!"); + ret = -EBUSY; } } else { - LOG_E("the path:%s is not a mountpoint!", fullpath); + LOG_I("the path:%s is not a mountpoint!", fullpath); + ret = -EINVAL; } } else { - LOG_E("no filesystem found."); + LOG_I("no filesystem found."); } rt_free(fullpath); } diff --git a/rt-thread/components/dfs/dfs_v2/src/dfs_mnt.c b/rt-thread/components/dfs/dfs_v2/src/dfs_mnt.c index 4ad73c6..a207072 100644 --- a/rt-thread/components/dfs/dfs_v2/src/dfs_mnt.c +++ b/rt-thread/components/dfs/dfs_v2/src/dfs_mnt.c @@ -10,17 +10,21 @@ #include -#include "dfs.h" -#include "dfs_mnt.h" -#include "dfs_dentry.h" #include "dfs_private.h" +#include +#include +#include +#include + #define DBG_TAG "DFS.mnt" #define DBG_LVL DBG_WARNING #include static struct dfs_mnt *_root_mnt = RT_NULL; +RT_OBJECT_HOOKLIST_DEFINE(dfs_mnt_umnt); + /* * mnt tree structure * @@ -75,6 +79,7 @@ int dfs_mnt_insert(struct dfs_mnt* mnt, struct dfs_mnt* child) child = _root_mnt; rt_atomic_sub(&(_root_mnt->parent->ref_count), 1); rt_atomic_sub(&(_root_mnt->ref_count), 1); + _root_mnt->flags &= ~MNT_IS_LOCKED; _root_mnt = dfs_mnt_ref(mnt); mnt->parent = dfs_mnt_ref(mnt); @@ -242,21 +247,24 @@ struct dfs_mnt* dfs_mnt_ref(struct dfs_mnt* mnt) return mnt; } -int dfs_mnt_unref(struct dfs_mnt* mnt) +int dfs_mnt_unref(struct dfs_mnt *mnt) { rt_err_t ret = RT_EOK; + rt_base_t ref_count; if (mnt) { - rt_atomic_sub(&(mnt->ref_count), 1); + ref_count = rt_atomic_sub(&(mnt->ref_count), 1) - 1; - if (rt_atomic_load(&(mnt->ref_count)) == 0) + if (ref_count == 0) { dfs_lock(); if (mnt->flags & MNT_IS_UMOUNT) { mnt->fs_ops->umount(mnt); + + RT_OBJECT_HOOKLIST_CALL(dfs_mnt_umnt, (mnt)); } /* free full path */ @@ -278,6 +286,21 @@ int dfs_mnt_unref(struct dfs_mnt* mnt) return ret; } +int dfs_mnt_setflags(struct dfs_mnt *mnt, int flags) +{ + int error = 0; + + if (flags & MS_RDONLY) + { + mnt->flags |= MNT_RDONLY; +#ifdef RT_USING_PAGECACHE + dfs_pcache_clean(mnt); +#endif + } + + return error; +} + int dfs_mnt_destroy(struct dfs_mnt* mnt) { rt_err_t ret = RT_EOK; diff --git a/rt-thread/components/dfs/dfs_v2/src/dfs_pcache.c b/rt-thread/components/dfs/dfs_v2/src/dfs_pcache.c index 350ad1f..cba36d8 100644 --- a/rt-thread/components/dfs/dfs_v2/src/dfs_pcache.c +++ b/rt-thread/components/dfs/dfs_v2/src/dfs_pcache.c @@ -13,17 +13,19 @@ #define DBG_LVL DBG_WARNING #include -#include "dfs_pcache.h" -#include "dfs_dentry.h" -#include "dfs_mnt.h" -#include "mm_page.h" -#include -#include +#include +#include +#include #include #ifdef RT_USING_PAGECACHE +#include +#include +#include +#include + #ifndef RT_PAGECACHE_COUNT #define RT_PAGECACHE_COUNT 4096 #endif @@ -160,7 +162,7 @@ void dfs_pcache_release(size_t count) dfs_pcache_unlock(); } -void dfs_pcache_unmount(struct dfs_mnt *mnt) +static void _pcache_clean(struct dfs_mnt *mnt, int (*cb)(struct dfs_aspace *aspace)) { rt_list_t *node = RT_NULL; struct dfs_aspace *aspace = RT_NULL; @@ -175,7 +177,7 @@ void dfs_pcache_unmount(struct dfs_mnt *mnt) if (aspace && aspace->mnt == mnt) { dfs_aspace_clean(aspace); - dfs_aspace_release(aspace); + cb(aspace); } } @@ -187,13 +189,28 @@ void dfs_pcache_unmount(struct dfs_mnt *mnt) if (aspace && aspace->mnt == mnt) { dfs_aspace_clean(aspace); - dfs_aspace_release(aspace); + cb(aspace); } } dfs_pcache_unlock(); } +void dfs_pcache_unmount(struct dfs_mnt *mnt) +{ + _pcache_clean(mnt, dfs_aspace_release); +} + +static int _dummy_cb(struct dfs_aspace *mnt) +{ + return 0; +} + +void dfs_pcache_clean(struct dfs_mnt *mnt) +{ + _pcache_clean(mnt, _dummy_cb); +} + static int dfs_pcache_limit_check(void) { int index = 4; @@ -1138,14 +1155,21 @@ int dfs_aspace_write(struct dfs_file *file, const void *buf, size_t count, off_t if (file && file->vnode && file->vnode->aspace) { - if (!(file->vnode->aspace->ops->write)) - return ret; struct dfs_vnode *vnode = file->vnode; struct dfs_aspace *aspace = vnode->aspace; struct dfs_page *page; char *ptr = (char *)buf; + if (!(aspace->ops->write)) + { + return ret; + } + else if (aspace->mnt && (aspace->mnt->flags & MNT_RDONLY)) + { + return -EROFS; + } + ret = 0; while (count) @@ -1380,7 +1404,8 @@ int dfs_aspace_unmap(struct dfs_file *file, struct rt_varea *varea) rt_varea_unmap_page(map_varea, vaddr); - if (varea->attr == MMU_MAP_U_RWCB && page->fpos < page->aspace->vnode->size) + if (!rt_varea_is_private_locked(varea) && + page->fpos < page->aspace->vnode->size) { dfs_page_dirty(page); } @@ -1425,7 +1450,7 @@ int dfs_aspace_page_unmap(struct dfs_file *file, struct rt_varea *varea, void *v if (map && varea->aspace == map->aspace && vaddr == map->vaddr) { - if (varea->attr == MMU_MAP_U_RWCB) + if (!rt_varea_is_private_locked(varea)) { dfs_page_dirty(page); } diff --git a/rt-thread/components/dfs/dfs_v2/src/dfs_posix.c b/rt-thread/components/dfs/dfs_v2/src/dfs_posix.c index ef6e8e7..38e17c3 100644 --- a/rt-thread/components/dfs/dfs_v2/src/dfs_posix.c +++ b/rt-thread/components/dfs/dfs_v2/src/dfs_posix.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,17 @@ * return a file descriptor according specified flags. * * @param file the path name of file. - * @param flags the file open flags. + * @param flags the file open flags. Common values include: + * - Access modes (mutually exclusive): + * - `O_RDONLY`: Open for read-only access. + * - `O_WRONLY`: Open for write-only access. + * - `O_RDWR`: Open for both reading and writing. + * - File status flags (can be combined with bitwise OR `|`): + * - `O_CREAT`: Create the file if it does not exist. Requires a `mode` argument. + * - `O_TRUNC`: Truncate the file to zero length if it already exists. + * - `O_APPEND`: Append writes to the end of the file. + * - `O_EXCL`: Ensure that `O_CREAT` creates the file exclusively. + * - Other platform-specific flags * * @return the non-negative integer on successful open, others for failed. */ @@ -81,6 +91,22 @@ RTM_EXPORT(open); #ifndef AT_FDCWD #define AT_FDCWD (-100) #endif + +/** + * @brief Opens a file relative to a directory file descriptor. + * + * @param dirfd The file descriptor of the directory to base the relative path on. + * @param path The path to the file to be opened, relative to the directory specified by `dirfd`. + * Can be an absolute path (in which case `dirfd` is ignored). + * @param flag File access and status flags (e.g., `O_RDONLY`, `O_WRONLY`, `O_CREAT`). + * + * @return On success, returns a new file descriptor for the opened file. + * On failure, returns `-1` and sets `errno` to indicate the error. + * + * @note When using relative paths, ensure `dirfd` is a valid directory descriptor. + * When `pathname` is absolute, the `dirfd` argument is ignored. + * + */ int openat(int dirfd, const char *path, int flag, ...) { struct dfs_file *d; @@ -171,7 +197,7 @@ int utimensat(int __fd, const char *__path, const struct timespec __times[2], in } } - //update time + /*update time*/ attr.ia_valid = ATTR_ATIME_SET | ATTR_MTIME_SET; time(¤t_time); if (UTIME_NOW == __times[0].tv_nsec) @@ -374,14 +400,22 @@ ssize_t write(int fd, const void *buf, size_t len) RTM_EXPORT(write); /** - * this function is a POSIX compliant version, which will seek the offset for + * this function is a POSIX compliant version, which will Reposition the file offset for * an open file descriptor. * - * @param fd the file descriptor. - * @param offset the offset to be seeked. - * @param whence the directory of seek. + * The `lseek` function sets the file offset for the file descriptor `fd` + * to a new value, determined by the `offset` and `whence` parameters. + * It can be used to seek to specific positions in a file for reading or writing. * - * @return the current read/write position in the file, or -1 on failed. + * @param fd the file descriptor. + * @param offset The offset, in bytes, to set the file position. + * The meaning of `offset` depends on the value of `whence`. + * @param whence the directive of seek. It can be one of: + * - `SEEK_SET`: Set the offset to `offset` bytes from the beginning of the file. + * - `SEEK_CUR`: Set the offset to its current location plus `offset` bytes. + * - `SEEK_END`: Set the offset to the size of the file plus `offset` bytes. + * + * @return the resulting read/write position in the file, or -1 on failed. */ off_t lseek(int fd, off_t offset, int whence) { @@ -399,7 +433,7 @@ off_t lseek(int fd, off_t offset, int whence) result = dfs_file_lseek(file, offset, whence); if (result < 0) { - rt_set_errno(result); + rt_set_errno(-EPERM); return -1; } @@ -581,9 +615,15 @@ RTM_EXPORT(fsync); * control functions on devices. * * @param fildes the file description - * @param cmd the specified command + * @param cmd the specified command, Common values include: + * - `F_DUPFD`: Duplicate a file descriptor. + * - `F_GETFD`: Get the file descriptor flags. + * - `F_SETFD`: Set the file descriptor flags. + * - `F_GETFL`: Get the file status flags. + * - `F_SETFL`: Set the file status flags. * @param ... represents the additional information that is needed by this - * specific device to perform the requested function. + * specific device to perform the requested function. For example: + * - When `cmd` is `F_SETFL`, an additional integer argument specifies the new status flags. * * @return 0 on successful completion. Otherwise, -1 shall be returned and errno * set to indicate the error. @@ -765,7 +805,7 @@ RTM_EXPORT(fstatfs); * this function is a POSIX compliant version, which will make a directory * * @param path the directory path to be made. - * @param mode + * @param mode The permission mode for the new directory (unused here, can be set to 0). * * @return 0 on successful, others on failed. */ @@ -827,7 +867,7 @@ int rmdir(const char *pathname) if (!pathname) { - rt_set_errno(-RT_ERROR); + rt_set_errno(-EPERM); return -1; } @@ -852,7 +892,7 @@ int rmdir(const char *pathname) if (dirent) { - rt_set_errno(-RT_ERROR); + rt_set_errno(-EPERM); return -1; } } @@ -861,7 +901,7 @@ int rmdir(const char *pathname) { if (S_ISLNK(stat.st_mode)) { - rt_set_errno(-RT_ERROR); + rt_set_errno(-EPERM); return -1; } } diff --git a/rt-thread/components/dfs/dfs_v2/src/dfs_seq_file.c b/rt-thread/components/dfs/dfs_v2/src/dfs_seq_file.c index 9521f53..2980b03 100644 --- a/rt-thread/components/dfs/dfs_v2/src/dfs_seq_file.c +++ b/rt-thread/components/dfs/dfs_v2/src/dfs_seq_file.c @@ -256,7 +256,7 @@ Enomem: goto Done; } -ssize_t dfs_seq_lseek(struct dfs_file *file, off_t offset, int whence) +off_t dfs_seq_lseek(struct dfs_file *file, off_t offset, int whence) { struct dfs_seq_file *seq = file->data; off_t retval = -EINVAL; diff --git a/rt-thread/components/drivers/Kconfig b/rt-thread/components/drivers/Kconfig index 24856d5..3ffa4c3 100644 --- a/rt-thread/components/drivers/Kconfig +++ b/rt-thread/components/drivers/Kconfig @@ -21,8 +21,21 @@ rsource "touch/Kconfig" rsource "graphic/Kconfig" rsource "hwcrypto/Kconfig" rsource "wlan/Kconfig" +rsource "led/Kconfig" +rsource "mailbox/Kconfig" +rsource "phye/Kconfig" +rsource "ata/Kconfig" +rsource "nvme/Kconfig" +rsource "block/Kconfig" +rsource "scsi/Kconfig" +rsource "regulator/Kconfig" +rsource "reset/Kconfig" +rsource "thermal/Kconfig" rsource "virtio/Kconfig" +rsource "dma/Kconfig" +rsource "mfd/Kconfig" rsource "ofw/Kconfig" +rsource "pci/Kconfig" rsource "pic/Kconfig" rsource "pin/Kconfig" rsource "pinctrl/Kconfig" diff --git a/rt-thread/components/drivers/ata/Kconfig b/rt-thread/components/drivers/ata/Kconfig new file mode 100644 index 0000000..4b5cee5 --- /dev/null +++ b/rt-thread/components/drivers/ata/Kconfig @@ -0,0 +1,22 @@ +menuconfig RT_USING_ATA + bool "Using Advanced Technology Attachment (ATA) device drivers" + depends on RT_USING_DM + depends on RT_USING_BLK + depends on RT_USING_DMA + default n + +config RT_ATA_AHCI + bool "Advanced Host Controller Interface (AHCI)" + depends on RT_USING_ATA + depends on RT_USING_SCSI + default y + +config RT_ATA_AHCI_PCI + bool "AHCI support on PCI bus" + depends on RT_ATA_AHCI + depends on RT_USING_PCI + default n + +if RT_USING_ATA + osource "$(SOC_DM_ATA_DIR)/Kconfig" +endif diff --git a/rt-thread/components/drivers/ata/SConscript b/rt-thread/components/drivers/ata/SConscript new file mode 100644 index 0000000..f4a0922 --- /dev/null +++ b/rt-thread/components/drivers/ata/SConscript @@ -0,0 +1,21 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_ATA']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] + +src = [] + +if GetDepend(['RT_ATA_AHCI']): + src += ['ahci.c'] + + if GetDepend(['RT_ATA_AHCI_PCI']): + src += ['ahci-pci.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/ata/ahci-pci.c b/rt-thread/components/drivers/ata/ahci-pci.c new file mode 100644 index 0000000..0bbec3e --- /dev/null +++ b/rt-thread/components/drivers/ata/ahci-pci.c @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include + +#define AHCI_REG_BAR 5 + +struct pci_ahci_quirk +{ + int bar_idx; + rt_bool_t bar_offset; + + const struct rt_ahci_ops *ops; +}; + +struct pci_ahci_host +{ + struct rt_ahci_host parent; + const struct pci_ahci_quirk *quirk; + + rt_bool_t is_msi; +}; + +#define raw_to_pci_ahci_host(raw) rt_container_of(raw, struct pci_ahci_host, parent) + +static rt_err_t pci_ahci_init(struct rt_ahci_host *host) +{ + struct rt_pci_device *pdev; + + pdev = rt_container_of(host->parent.dev, struct rt_pci_device, parent); + + if (pdev->vendor == PCI_VENDOR_ID_JMICRON) + { + rt_pci_write_config_u8(pdev, 0x41, 0xa1); + } + + return RT_EOK; +} + +static const struct rt_ahci_ops pci_ahci_ops = +{ + .host_init = pci_ahci_init, +}; + +static rt_err_t pci_ahci_intel_init(struct rt_ahci_host *host) +{ + rt_uint16_t val; + struct rt_pci_device *pdev; + + pdev = rt_container_of(host->parent.dev, struct rt_pci_device, parent); + + rt_pci_read_config_u16(pdev, 0x92, &val); + rt_pci_write_config_u16(pdev, 0x92, val & ~0xf); + + rt_thread_mdelay(10); + rt_pci_write_config_u16(pdev, 0x92, val | 0xf); + + return RT_EOK; +} + +static const struct rt_ahci_ops pci_ahci_intel_ops = +{ + .host_init = pci_ahci_intel_init, +}; + +static rt_err_t pci_ahci_probe(struct rt_pci_device *pdev) +{ + rt_err_t err; + int bar_idx; + struct rt_ahci_host *ahci; + struct pci_ahci_host *pci_ahci = rt_calloc(1, sizeof(*pci_ahci)); + const struct pci_ahci_quirk *quirk = pdev->id->data; + + if (!pci_ahci) + { + return -RT_ENOMEM; + } + + pci_ahci->quirk = quirk; + ahci = &pci_ahci->parent; + ahci->parent.dev = &pdev->parent; + + bar_idx = quirk && quirk->bar_offset ? quirk->bar_idx : AHCI_REG_BAR; + + ahci->regs = rt_pci_iomap(pdev, bar_idx); + + if (!ahci->regs) + { + err = -RT_EIO; + goto _fail; + } + + ahci->ops = quirk && quirk->ops ? quirk->ops : &pci_ahci_ops; + + if (rt_pci_msi_enable(pdev) > 0) + { + pci_ahci->is_msi = RT_TRUE; + } + else + { + rt_pci_irq_unmask(pdev); + } + ahci->irq = pdev->irq; + + rt_pci_set_master(pdev); + + if ((err = rt_ahci_host_register(ahci))) + { + goto _disable; + } + + pdev->parent.user_data = pci_ahci; + + return RT_EOK; + +_disable: + if (pci_ahci->is_msi) + { + rt_pci_msix_disable(pdev); + } + else + { + rt_pci_irq_mask(pdev); + } + rt_pci_clear_master(pdev); + rt_iounmap(ahci->regs); + +_fail: + rt_free(pci_ahci); + + return err; +} + +static rt_err_t pci_ahci_remove(struct rt_pci_device *pdev) +{ + struct rt_ahci_host *ahci; + struct pci_ahci_host *pci_ahci = pdev->parent.user_data; + + ahci = &pci_ahci->parent; + + rt_ahci_host_unregister(ahci); + + if (pci_ahci->is_msi) + { + rt_pci_msi_disable(pdev); + } + else + { + /* INTx is shared, don't mask all */ + rt_hw_interrupt_umask(pdev->irq); + rt_pci_irq_mask(pdev); + } + + rt_pci_clear_master(pdev); + + rt_iounmap(ahci->regs); + rt_free(pci_ahci); + + return RT_EOK; +} + +static rt_err_t pci_ahci_shutdown(struct rt_pci_device *pdev) +{ + return pci_ahci_remove(pdev); +} + +static struct pci_ahci_quirk intel_quirk = +{ + .ops = &pci_ahci_intel_ops, +}; + +static struct pci_ahci_quirk cavium_sata_quirk = +{ + .bar_idx = 0, + .bar_offset = RT_TRUE, +}; + +static const struct rt_pci_device_id pci_ahci_ids[] = +{ + { RT_PCI_DEVICE_ID(PCI_VENDOR_ID_INTEL, 0x2922), .data = &intel_quirk }, + { RT_PCI_DEVICE_ID(PCI_VENDOR_ID_ASMEDIA, 0x0611) }, + { RT_PCI_DEVICE_ID(PCI_VENDOR_ID_MARVELL, 0x6121) }, + { RT_PCI_DEVICE_ID(PCI_VENDOR_ID_MARVELL, 0x6145) }, + { RT_PCI_DEVICE_ID(PCI_VENDOR_ID_CAVIUM, 0xa01c), .data = &cavium_sata_quirk }, + { RT_PCI_DEVICE_CLASS(PCIS_STORAGE_SATA_AHCI, ~0) }, + { /* sentinel */ } +}; + +static struct rt_pci_driver pci_ahci_driver = +{ + .name = "ahci-pci", + + .ids = pci_ahci_ids, + .probe = pci_ahci_probe, + .remove = pci_ahci_remove, + .shutdown = pci_ahci_shutdown, +}; +RT_PCI_DRIVER_EXPORT(pci_ahci_driver); diff --git a/rt-thread/components/drivers/ata/ahci.c b/rt-thread/components/drivers/ata/ahci.c new file mode 100644 index 0000000..c8a191b --- /dev/null +++ b/rt-thread/components/drivers/ata/ahci.c @@ -0,0 +1,896 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "rtdm.ahci" +#define DBG_LVL DBG_INFO +#include + +#define HWREG32_FLUSH(base, value) \ +do { \ + rt_uint32_t __value = value; \ + HWREG32(base) = __value; \ + __value = HWREG32(base); \ +} while (0) + +static void ahci_fill_cmd_slot(struct rt_ahci_port *port, rt_uint32_t opts) +{ + rt_ubase_t dma_addr = port->cmd_tbl_dma; + struct rt_ahci_cmd_hdr *cmd_slot = port->cmd_slot; + + cmd_slot->opts = rt_cpu_to_le32(opts); + cmd_slot->status = 0; + cmd_slot->tbl_addr_lo = rt_cpu_to_le32(rt_lower_32_bits(dma_addr)); + cmd_slot->tbl_addr_hi = rt_cpu_to_le32(rt_upper_32_bits(dma_addr)); +} + +static int ahci_fill_sg(struct rt_ahci_host *host, int id, + void *buffer, rt_size_t buffer_size) +{ + int sg_count; + rt_ubase_t dma_addr; + struct rt_ahci_port *port = &host->ports[id]; + struct rt_ahci_sg *ahci_sg = port->cmd_tbl_sg; + + sg_count = ((buffer_size - 1) / RT_ACHI_PRDT_BYTES_MAX) + 1; + + if (sg_count > RT_AHCI_MAX_SG) + { + return -1; + } + + dma_addr = (rt_ubase_t)rt_kmem_v2p(buffer); + + for (int i = 0; i < sg_count; ++i, ++ahci_sg) + { + ahci_sg->addr_lo = rt_cpu_to_le32(rt_lower_32_bits(dma_addr)); + ahci_sg->addr_hi = rt_cpu_to_le32(rt_upper_32_bits(dma_addr)); + + if (ahci_sg->addr_hi && !(host->cap & RT_AHCI_CAP_64)) + { + return -1; + } + + ahci_sg->flags_size = rt_cpu_to_le32(0x3fffff & + (rt_min_t(rt_uint32_t, buffer_size, RT_ACHI_PRDT_BYTES_MAX) - 1)); + + dma_addr += RT_ACHI_PRDT_BYTES_MAX; + buffer_size -= RT_ACHI_PRDT_BYTES_MAX; + } + + return sg_count; +} + +static rt_err_t ahci_request_io(struct rt_ahci_host *host, int id, + void *fis, rt_size_t fis_size, + void *buffer, rt_size_t buffer_size, rt_bool_t is_read) +{ + int sg_count; + rt_err_t err; + struct rt_ahci_port *port = &host->ports[id]; + + if ((HWREG32(port->regs + RT_AHCI_PORT_SSTS) & 0xf) != RT_AHCI_PORT_SSTS_DET_PHYRDY) + { + return -RT_EIO; + } + + if ((sg_count = ahci_fill_sg(host, id, buffer, buffer_size)) <= 0) + { + return -RT_EINVAL; + } + + rt_memcpy(port->cmd_tbl, fis, fis_size); + ahci_fill_cmd_slot(port, (fis_size >> 2) | (sg_count << 16) | (!is_read << 6)); + + if (!is_read) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, buffer, buffer_size); + } + + HWREG32_FLUSH(port->regs + RT_AHCI_PORT_CI, 1); + + err = rt_completion_wait(&port->done, rt_tick_from_millisecond(10000)); + + if (!err && is_read) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, buffer, buffer_size); + } + + return err; +} + +static rt_err_t ahci_scsi_cmd_rw(struct rt_ahci_host *host, int id, + rt_off_t lba, void *buffer, rt_ssize_t size, rt_bool_t is_read) +{ + rt_err_t err; + rt_uint8_t fis[20]; + struct rt_ahci_port *port = &host->ports[id]; + + rt_memset(fis, 0, sizeof(fis)); + fis[0] = RT_AHCI_FIS_TYPE_REG_H2D; + fis[1] = 1 << 7; /* Command */ + fis[2] = is_read ? RT_AHCI_ATA_CMD_READ_EXT : RT_AHCI_ATA_CMD_WRITE_EXT; + + while (size > 0) + { + rt_size_t t_size, t_lba; + + t_lba = rt_min_t(rt_size_t, host->max_blocks, size); + t_size = port->block_size * t_lba; + + fis[3] = 0xe0; /* Features */ + fis[4] = (lba >> 0) & 0xff; /* LBA low register */ + fis[5] = (lba >> 8) & 0xff; /* LBA mid register */ + fis[6] = (lba >> 16) & 0xff; /* LBA high register */ + fis[7] = 1 << 6; /* Device */ + fis[8] = ((lba >> 24) & 0xff); /* LBA register, 31:24 */ + fis[9] = ((lba >> 32) & 0xff); /* LBA register, 39:32 */ + fis[10] = ((lba >> 40) & 0xff); /* LBA register, 47:40 */ + fis[12] = (t_lba >> 0) & 0xff; /* Count register, 7:0 */ + fis[13] = (t_lba >> 8) & 0xff; /* Count register, 15:8 */ + + if ((err = ahci_request_io(host, id, fis, sizeof(fis), buffer, t_size, is_read))) + { + return err; + } + + size -= t_lba; + lba += t_lba; + buffer += t_size; + } + + return RT_EOK; +} + +static rt_err_t ahci_scsi_synchronize_cache(struct rt_ahci_host *host, int id, + rt_off_t lba, rt_size_t size) +{ + rt_uint8_t fis[20]; + rt_uint16_t *ataid; + struct rt_ahci_port *port = &host->ports[id]; + + ataid = port->ataid; + + if (!rt_ahci_ata_id_wcache_enabled(ataid) && + !rt_ahci_ata_id_has_flush(ataid) && + !rt_ahci_ata_id_has_flush_ext(ataid)) + { + return -RT_ENOSYS; + } + + rt_memset(fis, 0, sizeof(fis)); + fis[0] = RT_AHCI_FIS_TYPE_REG_H2D; + fis[1] = 1 << 7; /* Command */ + + if (rt_ahci_ata_id_has_flush_ext(ataid)) + { + fis[2] = RT_AHCI_ATA_CMD_FLUSH_EXT; + } + else + { + fis[2] = RT_AHCI_ATA_CMD_FLUSH; + } + + rt_memcpy(port->cmd_tbl, fis, 20); + ahci_fill_cmd_slot(port, 5); + + HWREG32_FLUSH(port->regs + RT_AHCI_PORT_CI, 1); + + return rt_completion_wait(&port->done, rt_tick_from_millisecond(5000)); +} + +static rt_err_t ahci_scsi_cmd_write_same(struct rt_ahci_host *host, int id, + rt_off_t lba, rt_size_t size) +{ + rt_uint8_t fis[20]; + struct rt_ahci_port *port = &host->ports[id]; + + rt_memset(fis, 0, sizeof(fis)); + fis[0] = RT_AHCI_FIS_TYPE_REG_H2D; + fis[1] = 1 << 7; /* Command */ + fis[2] = RT_AHCI_ATA_CMD_DSM; + fis[3] = RT_AHCI_ATA_DSM_TRIM; /* Features */ + fis[4] = (lba >> 0) & 0xff; /* LBA low register */ + fis[5] = (lba >> 8) & 0xff; /* LBA mid register */ + fis[6] = (lba >> 16) & 0xff; /* LBA high register */ + fis[7] = 1 << 6; /* Device */ + fis[8] = ((lba >> 24) & 0xff); /* LBA register, 31:24 */ + fis[9] = ((lba >> 32) & 0xff); /* LBA register, 39:32 */ + fis[10] = ((lba >> 40) & 0xff); /* LBA register, 47:40 */ + fis[12] = (size >> 0) & 0xff; /* Count register, 7:0 */ + fis[13] = (size >> 8) & 0xff; /* Count register, 15:8 */ + + HWREG32_FLUSH(port->regs + RT_AHCI_PORT_CI, 1); + + return rt_completion_wait(&port->done, rt_tick_from_millisecond(5000)); +} + +static rt_err_t ahci_scsi_cmd_read_capacity(struct rt_ahci_host *host, int id, + rt_size_t *out_last_block, rt_size_t *out_block_size) +{ + struct rt_ahci_port *port = &host->ports[id]; + + if (!port->ataid) + { + return -RT_EIO; + } + + *out_last_block = rt_ahci_ata_id_n_sectors(port->ataid) - 1; + *out_block_size = port->block_size; + + return RT_EOK; +} + +static rt_err_t ahci_scsi_cmd_test_unit_ready(struct rt_ahci_host *host, int id) +{ + struct rt_ahci_port *port = &host->ports[id]; + + return port->ataid ? RT_EOK : -RT_EIO; +} + +static rt_err_t ahci_scsi_cmd_inquiry(struct rt_ahci_host *host, int id, + char *prodid, rt_size_t prodid_len, char *prodrev, rt_size_t prodrev_len) +{ + rt_err_t err; + rt_uint8_t fis[20]; + rt_uint16_t *ataid; + struct rt_ahci_port *port = &host->ports[id]; + + if (!port->link) + { + return -RT_EIO; + } + + if (!port->ataid && !(port->ataid = rt_malloc(RT_AHCI_ATA_ID_WORDS * 2))) + { + return -RT_ENOMEM; + } + ataid = port->ataid; + + rt_memset(fis, 0, sizeof(fis)); + fis[0] = RT_AHCI_FIS_TYPE_REG_H2D; + fis[1] = 1 << 7; /* Command */ + fis[2] = RT_AHCI_ATA_CMD_ID_ATA; + + if ((err = ahci_request_io(host, id, fis, sizeof(fis), + ataid, RT_AHCI_ATA_ID_WORDS * 2, RT_TRUE))) + { + return err; + } + + for (int i = 0; i < RT_AHCI_ATA_ID_WORDS; ++i) + { + ataid[i] = rt_le16_to_cpu(ataid[i]); + } + + for (int i = 0; i < prodid_len / 2; ++i) + { + rt_uint16_t src = ataid[RT_AHCI_ATA_ID_PROD + i]; + + prodid[i] = (src & 0x00ff) << 8 | (src & 0xff00) >> 8; + } + + for (int i = 0; i < prodrev_len / 2; ++i) + { + rt_uint16_t src = ataid[RT_AHCI_ATA_ID_FW_REV + i]; + + prodrev[i] = (src & 0x00ff) << 8 | (src & 0xff00) >> 8; + } + + return err; +} + +static rt_err_t ahci_scsi_transfer(struct rt_scsi_device *sdev, + struct rt_scsi_cmd *cmd) +{ + rt_err_t err; + struct rt_ahci_host *host; + + host = rt_container_of(sdev->host, struct rt_ahci_host, parent); + + switch (cmd->op.unknow.opcode) + { + case RT_SCSI_CMD_REQUEST_SENSE: + { + struct rt_scsi_request_sense_data *request_sense = &cmd->data.request_sense; + + request_sense->error_code = 0x72; + + err = RT_EOK; + } + break; + + case RT_SCSI_CMD_READ10: + { + struct rt_scsi_read10 *read10 = &cmd->op.read10; + + err = ahci_scsi_cmd_rw(host, sdev->id, + rt_be32_to_cpu(read10->lba), + cmd->data.ptr, + rt_be16_to_cpu(read10->size), + RT_TRUE); + } + break; + + case RT_SCSI_CMD_READ16: + { + struct rt_scsi_read16 *read16 = &cmd->op.read16; + + err = ahci_scsi_cmd_rw(host, sdev->id, + rt_be64_to_cpu(read16->lba), + cmd->data.ptr, + rt_be32_to_cpu(read16->size), + RT_TRUE); + } + break; + + case RT_SCSI_CMD_READ12: + { + struct rt_scsi_read12 *read12 = &cmd->op.read12; + + err = ahci_scsi_cmd_rw(host, sdev->id, + rt_be32_to_cpu(read12->lba), + cmd->data.ptr, + rt_be32_to_cpu(read12->size), + RT_TRUE); + } + break; + + case RT_SCSI_CMD_WRITE10: + { + struct rt_scsi_write10 *write10 = &cmd->op.write10; + + err = ahci_scsi_cmd_rw(host, sdev->id, + rt_be32_to_cpu(write10->lba), + cmd->data.ptr, + rt_be16_to_cpu(write10->size), + RT_FALSE); + } + break; + + case RT_SCSI_CMD_WRITE16: + { + struct rt_scsi_write16 *write16 = &cmd->op.write16; + + err = ahci_scsi_cmd_rw(host, sdev->id, + rt_be64_to_cpu(write16->lba), + cmd->data.ptr, + rt_be32_to_cpu(write16->size), + RT_FALSE); + } + break; + + case RT_SCSI_CMD_WRITE12: + { + struct rt_scsi_write12 *write12 = &cmd->op.write12; + + err = ahci_scsi_cmd_rw(host, sdev->id, + rt_be32_to_cpu(write12->lba), + cmd->data.ptr, + rt_be32_to_cpu(write12->size), + RT_FALSE); + } + break; + + case RT_SCSI_CMD_SYNCHRONIZE_CACHE10: + { + struct rt_scsi_synchronize_cache10 *synchronize_cache10 = &cmd->op.synchronize_cache10; + + err = ahci_scsi_synchronize_cache(host, sdev->id, + rt_be32_to_cpu(synchronize_cache10->lba), + rt_be16_to_cpu(synchronize_cache10->size)); + } + break; + + case RT_SCSI_CMD_SYNCHRONIZE_CACHE16: + { + struct rt_scsi_synchronize_cache16 *synchronize_cache16 = &cmd->op.synchronize_cache16; + + err = ahci_scsi_synchronize_cache(host, sdev->id, + rt_be64_to_cpu(synchronize_cache16->lba), + rt_be32_to_cpu(synchronize_cache16->size)); + } + break; + + case RT_SCSI_CMD_WRITE_SAME10: + { + struct rt_scsi_write_same10 *write_same10 = &cmd->op.write_same10; + + err = ahci_scsi_cmd_write_same(host, sdev->id, + rt_be32_to_cpu(write_same10->lba), rt_be16_to_cpu(write_same10->size)); + } + break; + + case RT_SCSI_CMD_WRITE_SAME16: + { + struct rt_scsi_write_same16 *write_same16 = &cmd->op.write_same16; + + err = ahci_scsi_cmd_write_same(host, sdev->id, + rt_be64_to_cpu(write_same16->lba), rt_be32_to_cpu(write_same16->size)); + } + break; + + case RT_SCSI_CMD_READ_CAPACITY10: + { + rt_size_t last_block, block_size; + struct rt_scsi_read_capacity10_data *data = &cmd->data.read_capacity10; + + err = ahci_scsi_cmd_read_capacity(host, sdev->id, &last_block, &block_size); + + if (!err) + { + if (last_block > 0x100000000ULL) + { + last_block = 0xffffffff; + } + + data->last_block = rt_cpu_to_be32(last_block); + data->block_size = rt_cpu_to_be32(block_size); + } + } + break; + + case RT_SCSI_CMD_READ_CAPACITY16: + { + rt_size_t last_block, block_size; + struct rt_scsi_read_capacity16_data *data = &cmd->data.read_capacity16; + + err = ahci_scsi_cmd_read_capacity(host, sdev->id, &last_block, &block_size); + + if (!err) + { + data->last_block = rt_cpu_to_be64(last_block); + data->block_size = rt_cpu_to_be32(block_size); + } + } + break; + + case RT_SCSI_CMD_TEST_UNIT_READY: + err = ahci_scsi_cmd_test_unit_ready(host, sdev->id); + break; + + case RT_SCSI_CMD_INQUIRY: + { + struct rt_ahci_port *port = &host->ports[sdev->id]; + struct rt_scsi_inquiry_data *inquiry = &cmd->data.inquiry; + + err = ahci_scsi_cmd_inquiry(host, sdev->id, + inquiry->prodid, sizeof(inquiry->prodid), + inquiry->prodrev, sizeof(inquiry->prodrev)); + + if (!err) + { + rt_memcpy(inquiry->vendor, "ATA ", sizeof(inquiry->vendor)); + + if (HWREG32(port->regs + RT_AHCI_PORT_SIG) != RT_AHCI_PORT_SIG_SATA_CDROM) + { + port->block_size = 512; + inquiry->devtype = SCSI_DEVICE_TYPE_DIRECT; + } + else + { + port->block_size = 2048; + inquiry->devtype = SCSI_DEVICE_TYPE_CDROM; + } + inquiry->rmb = 0; + inquiry->length = 95 - 4; + } + } + break; + + case RT_SCSI_CMD_MODE_SENSE: + case RT_SCSI_CMD_MODE_SENSE10: + case RT_SCSI_CMD_MODE_SELECT: + case RT_SCSI_CMD_MODE_SELECT10: + return -RT_ENOSYS; + + default: + return -RT_EINVAL; + } + + return err; +} + +static struct rt_scsi_ops ahci_scsi_ops = +{ + .transfer = ahci_scsi_transfer, +}; + +static void ahci_isr(int irqno, void *param) +{ + int id; + rt_uint32_t isr; + rt_bitmap_t int_map; + struct rt_ahci_port *port; + struct rt_ahci_host *host = param; + + int_map = HWREG32(host->regs + RT_AHCI_HBA_INTS); + + rt_bitmap_for_each_set_bit(&int_map, id, host->ports_nr) + { + port = &host->ports[id]; + + isr = HWREG32(port->regs + RT_AHCI_PORT_INTS); + + if (port->link) + { + if (host->ops->port_isr) + { + host->ops->port_isr(host, port, isr); + } + + rt_completion_done(&port->done); + } + + HWREG32(port->regs + RT_AHCI_PORT_INTS) = isr; + } + + HWREG32(host->regs + RT_AHCI_HBA_INTS) = int_map; +} + +rt_err_t rt_ahci_host_register(struct rt_ahci_host *host) +{ + rt_err_t err; + rt_uint32_t value; + char dev_name[RT_NAME_MAX]; + struct rt_scsi_host *scsi; + + if (!host || !host->parent.dev || !host->ops) + { + return -RT_EINVAL; + } + + host->max_blocks = host->max_blocks ? : 0x80; + + /* + * 1. Reset HBA. + */ + err = -RT_EIO; + value = HWREG32(host->regs + RT_AHCI_HBA_GHC); + + if (!(value & RT_AHCI_GHC_RESET)) + { + HWREG32_FLUSH(host->regs + RT_AHCI_HBA_GHC, value | RT_AHCI_GHC_RESET); + } + + for (int i = 0; i < 5; ++i) + { + rt_thread_mdelay(200); + + if (!(HWREG32(host->regs + RT_AHCI_HBA_GHC) & RT_AHCI_GHC_RESET)) + { + err = RT_EOK; + break; + } + } + + if (err) + { + goto _fail; + } + + /* + * 2. Enable AHCI and get the ports' information. + */ + HWREG32_FLUSH(host->regs + RT_AHCI_HBA_GHC, RT_AHCI_GHC_AHCI_EN); + + host->cap = HWREG32(host->regs + RT_AHCI_HBA_CAP); + host->cap &= RT_AHCI_CAP_SPM | RT_AHCI_CAP_SSS | RT_AHCI_CAP_SIS; + HWREG32(host->regs + RT_AHCI_HBA_CAP) = host->cap; + host->cap = HWREG32(host->regs + RT_AHCI_HBA_CAP); + + HWREG32_FLUSH(host->regs + RT_AHCI_HBA_PI, 0xf); + + if (host->ops->host_init && (err = host->ops->host_init(host))) + { + goto _fail; + } + + host->ports_nr = (host->cap & RT_AHCI_CAP_NP) + 1; + host->ports_map = HWREG32(host->regs + RT_AHCI_HBA_PI); + + /* Check implemented in firmware */ + rt_dm_dev_prop_read_u32(host->parent.dev, "ports-implemented", &host->ports_map); + + for (int i = 0; i < host->ports_nr; ++i) + { + struct rt_ahci_port *port; + + if (!(host->ports_map & RT_BIT(i))) + { + continue; + } + port = &host->ports[i]; + + /* + * 3. Alloc port io memory. + */ + port->regs = host->regs + 0x100 + (i * 0x80); + + /* + * 4. Make port stop. + */ + value = HWREG32(port->regs + RT_AHCI_PORT_CMD); + if (value & (RT_AHCI_PORT_CMD_LIST_ON | RT_AHCI_PORT_CMD_FIS_ON | + RT_AHCI_PORT_CMD_FIS_RX | RT_AHCI_PORT_CMD_START)) + { + value &= ~(RT_AHCI_PORT_CMD_LIST_ON | RT_AHCI_PORT_CMD_FIS_ON | + RT_AHCI_PORT_CMD_FIS_RX | RT_AHCI_PORT_CMD_START); + + HWREG32_FLUSH(port->regs + RT_AHCI_PORT_CMD, value); + + rt_thread_mdelay(500); + } + + if (host->ops->port_init && (err = host->ops->port_init(host, port))) + { + LOG_E("Init port[%d] error = %s", rt_strerror(err)); + continue; + } + + value = HWREG32(port->regs + RT_AHCI_PORT_CMD); + value |= RT_AHCI_PORT_CMD_SPIN_UP; + HWREG32(port->regs + RT_AHCI_PORT_CMD) = value; + + /* + * 5. Enable port's SATA link. + */ + if (host->ops->port_link_up) + { + err = host->ops->port_link_up(host, port); + } + else + { + err = -RT_ETIMEOUT; + + for (int retry = 0; retry < 5; ++retry) + { + value = HWREG32(port->regs + RT_AHCI_PORT_SSTS); + + if ((value & RT_AHCI_PORT_SSTS_DET_MASK) == RT_AHCI_PORT_SSTS_DET_PHYRDY) + { + err = RT_EOK; + break; + } + + rt_thread_mdelay(2); + } + } + + if (err) + { + if (HWREG32(port->regs + RT_AHCI_PORT_SSTS) & RT_AHCI_PORT_SSTS_DET_MASK) + { + LOG_E("SATA[%d] link error = %s", i, rt_strerror(err)); + } + else + { + LOG_D("SATA[%d] not device", i); + } + + continue; + } + + /* Clear error status */ + if ((value = HWREG32(port->regs + RT_AHCI_PORT_SERR))) + { + HWREG32(port->regs + RT_AHCI_PORT_SERR) = value; + } + + for (int retry = 0; retry < 5; ++retry) + { + value = HWREG32(port->regs + RT_AHCI_PORT_TFD); + if (!(value & (RT_AHCI_PORT_TFDATA_BSY | RT_AHCI_PORT_TFDATA_DRQ))) + { + break; + } + + rt_thread_mdelay(2); + + value = HWREG32(port->regs + RT_AHCI_PORT_SSTS); + if ((value & RT_AHCI_PORT_SSTS_DET_MASK) == RT_AHCI_PORT_SSTS_DET_PHYRDY) + { + break; + } + } + + value = HWREG32(port->regs + RT_AHCI_PORT_SSTS) & RT_AHCI_PORT_SSTS_DET_MASK; + if (value == RT_AHCI_PORT_SSTS_DET_COMINIT) + { + /* Retry to setup */ + --i; + continue; + } + + /* Clear error */ + value = HWREG32(port->regs + RT_AHCI_PORT_SERR); + HWREG32(port->regs + RT_AHCI_PORT_SERR) = value; + + /* Clear pending IRQ */ + if ((value = HWREG32(port->regs + RT_AHCI_PORT_INTS))) + { + HWREG32(port->regs + RT_AHCI_PORT_INTS) = value; + } + + HWREG32(host->regs + RT_AHCI_HBA_INTS) = RT_BIT(i); + + value = HWREG32(port->regs + RT_AHCI_PORT_SSTS); + if ((value & RT_AHCI_PORT_SSTS_DET_MASK) == RT_AHCI_PORT_SSTS_DET_PHYRDY) + { + port->link = RT_TRUE; + } + } + + HWREG32(host->regs + RT_AHCI_HBA_GHC) |= RT_AHCI_GHC_IRQ_EN; + + for (int i = 0; i < host->ports_nr; ++i) + { + void *dma; + rt_ubase_t dma_addr; + rt_tick_t timeout; + struct rt_ahci_port *port = &host->ports[i]; + + if (!port->link) + { + continue; + } + + /* + * 6. Alloc transport memory, Port x Command List and FIS Base Address. + */ + port->dma = rt_dma_alloc_coherent(host->parent.dev, + RT_AHCI_DMA_SIZE, &port->dma_handle); + + if (!port->dma) + { + LOG_E("No memory to setup port[%d]", i); + break; + } + dma = port->dma; + + rt_memset(dma, 0, RT_AHCI_DMA_SIZE); + + port->cmd_slot = dma; + dma += (RT_AHCI_CMD_SLOT_SIZE + 224); + + port->rx_fis = dma; + dma += RT_AHCI_RX_FIS_SIZE; + + port->cmd_tbl = dma; + port->cmd_tbl_dma = (rt_ubase_t)rt_kmem_v2p(dma); + dma += RT_AHCI_CMD_TBL_HDR; + + port->cmd_tbl_sg = dma; + + dma_addr = (rt_ubase_t)rt_kmem_v2p(port->cmd_slot); + HWREG32_FLUSH(port->regs + RT_AHCI_PORT_CLB, rt_lower_32_bits(dma_addr)); + HWREG32_FLUSH(port->regs + RT_AHCI_PORT_CLBU, rt_upper_32_bits(dma_addr)); + + dma_addr = (rt_ubase_t)rt_kmem_v2p(port->rx_fis); + HWREG32_FLUSH(port->regs + RT_AHCI_PORT_FB, rt_lower_32_bits(dma_addr)); + HWREG32_FLUSH(port->regs + RT_AHCI_PORT_FBU, rt_upper_32_bits(dma_addr)); + + if (host->ops->port_dma_init && (err = host->ops->port_dma_init(host, port))) + { + LOG_E("Init port[%d] DMA error = %s", rt_strerror(err)); + } + + HWREG32_FLUSH(port->regs + RT_AHCI_PORT_CMD, RT_AHCI_PORT_CMD_ACTIVE | + RT_AHCI_PORT_CMD_FIS_RX | RT_AHCI_PORT_CMD_POWER_ON | + RT_AHCI_PORT_CMD_SPIN_UP | RT_AHCI_PORT_CMD_START); + + /* Wait spinup */ + err = -RT_ETIMEOUT; + timeout = rt_tick_from_millisecond(20000); + timeout += rt_tick_get(); + do { + if (!(HWREG32(port->regs + RT_AHCI_PORT_TFD) & RT_AHCI_PORT_TFDATA_BSY)) + { + err = RT_EOK; + break; + } + + rt_hw_cpu_relax(); + } while (rt_tick_get() < timeout); + + if (err) + { + rt_dma_free_coherent(host->parent.dev, RT_AHCI_DMA_SIZE, port->dma, + port->dma_handle); + port->dma = RT_NULL; + + LOG_E("Start up port[%d] fail", i); + continue; + } + + port->int_enabled |= RT_AHCI_PORT_INTE_HBUS_ERR | RT_AHCI_PORT_INTE_IF_ERR | + RT_AHCI_PORT_INTE_CONNECT | RT_AHCI_PORT_INTE_PHYRDY | + RT_AHCI_PORT_INTE_UNK_FIS | RT_AHCI_PORT_INTE_BAD_PMP | + RT_AHCI_PORT_INTE_TF_ERR | RT_AHCI_PORT_INTE_HBUS_DATA_ERR | + RT_AHCI_PORT_INTE_SG_DONE | RT_AHCI_PORT_INTE_SDB_FIS | + RT_AHCI_PORT_INTE_DMAS_FIS | RT_AHCI_PORT_INTE_PIOS_FIS | + RT_AHCI_PORT_INTE_D2H_REG_FIS; + + HWREG32(port->regs + RT_AHCI_PORT_INTE) = port->int_enabled; + + rt_completion_init(&port->done); + } + + rt_snprintf(dev_name, sizeof(dev_name), "ahci-%s", + rt_dm_dev_get_name(host->parent.dev)); + + rt_hw_interrupt_install(host->irq, ahci_isr, host, dev_name); + rt_hw_interrupt_umask(host->irq); + + scsi = &host->parent; + scsi->max_lun = rt_max_t(rt_size_t, scsi->max_lun, 1); + scsi->max_id = host->ports_nr; + scsi->ops = &ahci_scsi_ops; + + if ((err = rt_scsi_host_register(scsi))) + { + goto _fail; + } + + return RT_EOK; + +_fail: + rt_hw_interrupt_mask(host->irq); + rt_pic_detach_irq(host->irq, host); + + return err; +} + +rt_err_t rt_ahci_host_unregister(struct rt_ahci_host *host) +{ + rt_err_t err; + struct rt_scsi_host *scsi; + + if (!host) + { + return -RT_EINVAL; + } + + scsi = &host->parent; + + if ((err = rt_scsi_host_unregister(scsi))) + { + return err; + } + + rt_hw_interrupt_mask(host->irq); + rt_pic_detach_irq(host->irq, host); + + for (int i = 0; i < host->ports_nr; ++i) + { + struct rt_ahci_port *port = &host->ports[i]; + + if (port->ataid) + { + rt_free(port->ataid); + } + + HWREG32(port->regs) &= ~(RT_AHCI_PORT_CMD_ACTIVE | RT_AHCI_PORT_CMD_POWER_ON | + RT_AHCI_PORT_CMD_SPIN_UP | RT_AHCI_PORT_CMD_START); + + if (port->dma) + { + rt_dma_free_coherent(host->parent.dev, RT_AHCI_DMA_SIZE, port->dma, + port->dma_handle); + } + } + + HWREG32(host->regs + RT_AHCI_HBA_GHC) &= ~(RT_AHCI_GHC_AHCI_EN | RT_AHCI_GHC_IRQ_EN); + + return RT_EOK; +} diff --git a/rt-thread/components/drivers/audio/audio.c b/rt-thread/components/drivers/audio/dev_audio.c similarity index 100% rename from rt-thread/components/drivers/audio/audio.c rename to rt-thread/components/drivers/audio/dev_audio.c diff --git a/rt-thread/components/drivers/audio/audio_pipe.c b/rt-thread/components/drivers/audio/dev_audio_pipe.c similarity index 90% rename from rt-thread/components/drivers/audio/audio_pipe.c rename to rt-thread/components/drivers/audio/dev_audio_pipe.c index d4d24b8..24c0f26 100644 --- a/rt-thread/components/drivers/audio/audio_pipe.c +++ b/rt-thread/components/drivers/audio/dev_audio_pipe.c @@ -10,9 +10,9 @@ #include #include -#include "audio_pipe.h" +#include "dev_audio_pipe.h" -static void _rt_pipe_resume_writer(struct rt_audio_pipe *pipe) +static void _rt_audio_pipe_resume_writer(struct rt_audio_pipe *pipe) { if (!rt_list_isempty(&pipe->suspended_write_list)) { @@ -30,7 +30,7 @@ static void _rt_pipe_resume_writer(struct rt_audio_pipe *pipe) } } -static rt_ssize_t rt_pipe_read(rt_device_t dev, +static rt_ssize_t rt_audio_pipe_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) @@ -50,7 +50,7 @@ static rt_ssize_t rt_pipe_read(rt_device_t dev, /* if the ringbuffer is empty, there won't be any writer waiting */ if (read_nbytes) - _rt_pipe_resume_writer(pipe); + _rt_audio_pipe_resume_writer(pipe); rt_hw_interrupt_enable(level); @@ -78,7 +78,7 @@ static rt_ssize_t rt_pipe_read(rt_device_t dev, } else { - _rt_pipe_resume_writer(pipe); + _rt_audio_pipe_resume_writer(pipe); rt_hw_interrupt_enable(level); break; } @@ -88,7 +88,7 @@ static rt_ssize_t rt_pipe_read(rt_device_t dev, return read_nbytes; } -static void _rt_pipe_resume_reader(struct rt_audio_pipe *pipe) +static void _rt_audio_pipe_resume_reader(struct rt_audio_pipe *pipe) { if (pipe->parent.rx_indicate) pipe->parent.rx_indicate(&pipe->parent, @@ -110,7 +110,7 @@ static void _rt_pipe_resume_reader(struct rt_audio_pipe *pipe) } } -static rt_ssize_t rt_pipe_write(rt_device_t dev, +static rt_ssize_t rt_audio_pipe_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) @@ -135,7 +135,7 @@ static rt_ssize_t rt_pipe_write(rt_device_t dev, write_nbytes = rt_ringbuffer_put(&(pipe->ringbuffer), (const rt_uint8_t *)buffer, size); - _rt_pipe_resume_reader(pipe); + _rt_audio_pipe_resume_reader(pipe); rt_hw_interrupt_enable(level); @@ -164,7 +164,7 @@ static rt_ssize_t rt_pipe_write(rt_device_t dev, } else { - _rt_pipe_resume_reader(pipe); + _rt_audio_pipe_resume_reader(pipe); rt_hw_interrupt_enable(level); break; } @@ -174,7 +174,7 @@ static rt_ssize_t rt_pipe_write(rt_device_t dev, return write_nbytes; } -static rt_err_t rt_pipe_control(rt_device_t dev, int cmd, void *args) +static rt_err_t rt_audio_pipe_control(rt_device_t dev, int cmd, void *args) { struct rt_audio_pipe *pipe; @@ -191,9 +191,9 @@ const static struct rt_device_ops audio_pipe_ops = RT_NULL, RT_NULL, RT_NULL, - rt_pipe_read, - rt_pipe_write, - rt_pipe_control + rt_audio_pipe_read, + rt_audio_pipe_write, + rt_audio_pipe_control }; #endif @@ -235,9 +235,9 @@ rt_err_t rt_audio_pipe_init(struct rt_audio_pipe *pipe, pipe->parent.init = RT_NULL; pipe->parent.open = RT_NULL; pipe->parent.close = RT_NULL; - pipe->parent.read = rt_pipe_read; - pipe->parent.write = rt_pipe_write; - pipe->parent.control = rt_pipe_control; + pipe->parent.read = rt_audio_pipe_read; + pipe->parent.write = rt_audio_pipe_write; + pipe->parent.control = rt_audio_pipe_control; #endif return rt_device_register(&(pipe->parent), name, RT_DEVICE_FLAG_RDWR); diff --git a/rt-thread/components/drivers/audio/audio_pipe.h b/rt-thread/components/drivers/audio/dev_audio_pipe.h similarity index 95% rename from rt-thread/components/drivers/audio/audio_pipe.h rename to rt-thread/components/drivers/audio/dev_audio_pipe.h index 88cbeca..f22fd14 100644 --- a/rt-thread/components/drivers/audio/audio_pipe.h +++ b/rt-thread/components/drivers/audio/dev_audio_pipe.h @@ -6,8 +6,8 @@ * Change Logs: * Date Author Notes */ -#ifndef __AUDIO_PIPE_H__ -#define __AUDIO_PIPE_H__ +#ifndef __DEV_AUDIO_PIPE_H__ +#define __DEV_AUDIO_PIPE_H__ /** * Pipe Device @@ -72,4 +72,4 @@ rt_err_t rt_audio_pipe_create(const char *name, rt_int32_t flag, rt_size_t size) void rt_audio_pipe_destroy(struct rt_audio_pipe *pipe); #endif /* RT_USING_HEAP */ -#endif /* __AUDIO_PIPE_H__ */ +#endif /* __DEV_AUDIO_PIPE_H__ */ diff --git a/rt-thread/components/drivers/block/Kconfig b/rt-thread/components/drivers/block/Kconfig new file mode 100644 index 0000000..865df5e --- /dev/null +++ b/rt-thread/components/drivers/block/Kconfig @@ -0,0 +1,7 @@ +menuconfig RT_USING_BLK + bool "Using Block device drivers" + default n + +if RT_USING_BLK + rsource "partitions/Kconfig" +endif diff --git a/rt-thread/components/drivers/block/SConscript b/rt-thread/components/drivers/block/SConscript new file mode 100644 index 0000000..4aff1a8 --- /dev/null +++ b/rt-thread/components/drivers/block/SConscript @@ -0,0 +1,23 @@ +from building import * + +group = [] +objs = [] + +if not GetDepend(['RT_USING_BLK']): + Return('group') + +cwd = GetCurrentDir() +list = os.listdir(cwd) +CPPPATH = [cwd + '/../include'] + +src = ['blk.c', 'blk_dev.c', 'blk_dfs.c', 'blk_partition.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +objs = objs + group + +Return('objs') diff --git a/rt-thread/components/drivers/block/blk.c b/rt-thread/components/drivers/block/blk.c new file mode 100644 index 0000000..9f2659d --- /dev/null +++ b/rt-thread/components/drivers/block/blk.c @@ -0,0 +1,573 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#define DBG_TAG "rtdm.blk" +#define DBG_LVL DBG_INFO +#include + +#include "blk_dev.h" +#include "blk_dfs.h" + +static void blk_remove_all(struct rt_blk_disk *disk) +{ + struct rt_blk_device *blk, *blk_next; + + /* Remove all partitions */ + rt_list_for_each_entry_safe(blk, blk_next, &disk->part_nodes, list) + { + disk_remove_blk_dev(blk, RT_TRUE); + } +} + +static rt_err_t blk_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct rt_blk_disk *disk = to_blk_disk(dev); + + if (disk->read_only && (oflag & RT_DEVICE_OFLAG_WRONLY)) + { + return -RT_EINVAL; + } + + return RT_EOK; +} + +static rt_err_t blk_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_ssize_t blk_read(rt_device_t dev, rt_off_t sector, + void *buffer, rt_size_t sector_count) +{ + rt_ssize_t res; + struct rt_blk_disk *disk = to_blk_disk(dev); + + rt_sem_take(&disk->usr_lock, RT_WAITING_FOREVER); + + res = disk->ops->read(disk, sector, buffer, sector_count); + + rt_sem_release(&disk->usr_lock); + + return res; +} + +static rt_ssize_t blk_write(rt_device_t dev, rt_off_t sector, + const void *buffer, rt_size_t sector_count) +{ + rt_ssize_t res; + struct rt_blk_disk *disk = to_blk_disk(dev); + + if (!disk->read_only) + { + rt_sem_take(&disk->usr_lock, RT_WAITING_FOREVER); + + res = disk->ops->write(disk, sector, buffer, sector_count); + + rt_sem_release(&disk->usr_lock); + + return res; + } + + return -RT_ENOSYS; +} + +static rt_ssize_t blk_parallel_read(rt_device_t dev, rt_off_t sector, + void *buffer, rt_size_t sector_count) +{ + struct rt_blk_disk *disk = to_blk_disk(dev); + + return disk->ops->read(disk, sector, buffer, sector_count); +} + +static rt_ssize_t blk_parallel_write(rt_device_t dev, rt_off_t sector, + const void *buffer, rt_size_t sector_count) +{ + struct rt_blk_disk *disk = to_blk_disk(dev); + + if (!disk->read_only) + { + return disk->ops->write(disk, sector, buffer, sector_count); + } + + return -RT_ENOSYS; +} + +static rt_err_t blk_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t err; + struct rt_blk_disk *disk = to_blk_disk(dev); + + switch (cmd) + { + case RT_DEVICE_CTRL_BLK_GETGEOME: + if (args) + { + err = disk->ops->getgeome(disk, args); + } + else + { + err = -RT_EINVAL; + } + + break; + + case RT_DEVICE_CTRL_BLK_SYNC: + if (disk->ops->sync) + { + rt_sem_take(&disk->usr_lock, RT_WAITING_FOREVER); + + spin_lock(&disk->lock); + + err = disk->ops->sync(disk); + + spin_unlock(&disk->lock); + + rt_sem_release(&disk->usr_lock); + } + else + { + err = -RT_ENOSYS; + } + break; + + case RT_DEVICE_CTRL_BLK_ERASE: + if (disk->ops->erase) + { + rt_sem_take(&disk->usr_lock, RT_WAITING_FOREVER); + + spin_lock(&disk->lock); + + if (disk->parent.ref_count != 1) + { + err = -RT_EBUSY; + goto _unlock; + } + + blk_remove_all(disk); + + err = disk->ops->erase(disk); + + _unlock: + spin_unlock(&disk->lock); + + rt_sem_release(&disk->usr_lock); + } + else + { + err = -RT_ENOSYS; + } + break; + + case RT_DEVICE_CTRL_BLK_AUTOREFRESH: + if (disk->ops->autorefresh) + { + err = disk->ops->autorefresh(disk, !!args); + } + else + { + err = -RT_ENOSYS; + } + break; + + case RT_DEVICE_CTRL_BLK_PARTITION: + err = -RT_EINVAL; + break; + + case RT_DEVICE_CTRL_BLK_SSIZEGET: + device_get_blk_ssize(dev, args); + err = RT_EOK; + break; + + case RT_DEVICE_CTRL_ALL_BLK_SSIZEGET: + device_get_all_blk_ssize(dev, args); + err = RT_EOK; + break; + + default: + if (disk->ops->control) + { + err = disk->ops->control(disk, RT_NULL, cmd, args); + } + else + { + err = -RT_ENOSYS; + } + break; + } + + return err; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops blk_ops = +{ + .open = blk_open, + .close = blk_close, + .read = blk_read, + .write = blk_write, + .control = blk_control, +}; + +const static struct rt_device_ops blk_parallel_ops = +{ + .open = blk_open, + .close = blk_close, + .read = blk_parallel_read, + .write = blk_parallel_write, + .control = blk_control, +}; +#endif /* RT_USING_DEVICE_OPS */ + +rt_err_t rt_hw_blk_disk_register(struct rt_blk_disk *disk) +{ + rt_err_t err; +#ifdef RT_USING_DM + int device_id; +#endif + const char *disk_name; + rt_uint16_t flags = RT_DEVICE_FLAG_RDONLY; + + if (!disk || !disk->ops) + { + return -RT_EINVAL; + } + +#ifdef RT_USING_DM + if (!disk->ida) + { + return -RT_EINVAL; + } +#endif + +#if RT_NAME_MAX > 0 + if (disk->parent.parent.name[0] == '\0') +#else + if (disk->parent.parent.name) +#endif + { + return -RT_EINVAL; + } + +#ifdef RT_USING_DM + if ((device_id = rt_dm_ida_alloc(disk->ida)) < 0) + { + return -RT_EFULL; + } +#endif + + disk->__magic = RT_BLK_DISK_MAGIC; + disk_name = to_disk_name(disk); + + err = rt_sem_init(&disk->usr_lock, disk_name, 1, RT_IPC_FLAG_PRIO); + + if (err) + { + #ifdef RT_USING_DM + rt_dm_ida_free(disk->ida, device_id); + #endif + + LOG_E("%s: Init user mutex error = %s", rt_strerror(err)); + + return err; + } + + rt_list_init(&disk->part_nodes); + rt_spin_lock_init(&disk->lock); + + disk->parent.type = RT_Device_Class_Block; +#ifdef RT_USING_DEVICE_OPS + if (disk->parallel_io) + { + disk->parent.ops = &blk_parallel_ops; + } + else + { + disk->parent.ops = &blk_ops; + } +#else + disk->parent.open = blk_open; + disk->parent.close = blk_close; + + if (disk->parallel_io) + { + disk->parent.read = blk_parallel_read; + disk->parent.write = blk_parallel_write; + } + else + { + disk->parent.read = blk_read; + disk->parent.write = blk_write; + } + disk->parent.control = blk_control; +#endif + + if (!disk->ops->write) + { + disk->read_only = RT_TRUE; + } + + if (!disk->read_only) + { + flags |= RT_DEVICE_FLAG_WRONLY; + } + +#ifdef RT_USING_DM + disk->parent.master_id = disk->ida->master_id; + disk->parent.device_id = device_id; +#endif + device_set_blk_fops(&disk->parent); + + err = rt_device_register(&disk->parent, disk_name, flags); + + if (err) + { + rt_sem_detach(&disk->usr_lock); + } + + /* Ignore partition scanning errors */ + rt_blk_disk_probe_partition(disk); + + return err; +} + +rt_err_t rt_hw_blk_disk_unregister(struct rt_blk_disk *disk) +{ + rt_err_t err; + + if (!disk) + { + return -RT_EINVAL; + } + + spin_lock(&disk->lock); + + if (disk->parent.ref_count > 0) + { + err = -RT_EBUSY; + goto _unlock; + } + + /* Flush all data */ + if (disk->ops->sync) + { + err = disk->ops->sync(disk); + + if (err) + { + LOG_E("%s: Sync error = %s", to_disk_name(disk), rt_strerror(err)); + + goto _unlock; + } + } + + rt_sem_detach(&disk->usr_lock); + + blk_remove_all(disk); + +#ifdef RT_USING_DM + rt_dm_ida_free(disk->ida, disk->parent.device_id); +#endif + + err = rt_device_unregister(&disk->parent); + +_unlock: + spin_unlock(&disk->lock); + + return err; +} + +rt_ssize_t rt_blk_disk_get_capacity(struct rt_blk_disk *disk) +{ + rt_ssize_t res; + struct rt_device_blk_geometry geometry; + + if (!disk) + { + return -RT_EINVAL; + } + + res = disk->ops->getgeome(disk, &geometry); + + if (!res) + { + return geometry.sector_count; + } + + return res; +} + +rt_ssize_t rt_blk_disk_get_logical_block_size(struct rt_blk_disk *disk) +{ + rt_ssize_t res; + struct rt_device_blk_geometry geometry; + + if (!disk) + { + return -RT_EINVAL; + } + + res = disk->ops->getgeome(disk, &geometry); + + if (!res) + { + return geometry.bytes_per_sector; + } + + return res; +} + +#ifdef RT_USING_DFS_MNTTABLE +static int blk_dfs_mnt_table(void) +{ + rt_ubase_t level; + struct rt_object *obj; + struct rt_device *dev; + struct rt_blk_disk *disk; + struct rt_blk_device *blk_dev; + struct rt_object_information *info = rt_object_get_information(RT_Object_Class_Device); + + level = rt_hw_interrupt_disable(); + + rt_list_for_each_entry(obj, &info->object_list, list) + { + dev = rt_container_of(obj, struct rt_device, parent); + + if (dev->type != RT_Device_Class_Block) + { + continue; + } + + disk = to_blk_disk(dev); + + if (disk->__magic != RT_BLK_DISK_MAGIC) + { + continue; + } + + if (disk->max_partitions == RT_BLK_PARTITION_NONE) + { + dfs_mount_device(&disk->parent); + continue; + } + + rt_list_for_each_entry(blk_dev, &disk->part_nodes, list) + { + dfs_mount_device(&blk_dev->parent); + } + } + + rt_hw_interrupt_enable(level); + + return 0; +} +INIT_ENV_EXPORT(blk_dfs_mnt_table); +#endif /* RT_USING_DFS_MNTTABLE */ + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_MSH) +const char *convert_size(struct rt_device_blk_geometry *geome, + rt_size_t sector_count, rt_size_t *out_cap, rt_size_t *out_minor) +{ + rt_size_t cap, minor = 0; + int size_index = 0; + const char *size_name[] = { "B", "K", "M", "G", "T", "P", "E" }; + + cap = geome->bytes_per_sector * sector_count; + + for (size_index = 0; size_index < RT_ARRAY_SIZE(size_name) - 1; ++size_index) + { + if (cap < 1024) + { + break; + } + + /* Only one decimal point */ + minor = (cap % 1024) * 10 / 1024; + cap = cap / 1024; + } + + *out_cap = cap; + *out_minor = minor; + + return size_name[size_index]; +} + +static int list_blk(int argc, char**argv) +{ + rt_ubase_t level; + rt_size_t cap, minor; + const char *size_name; + struct rt_object *obj; + struct rt_device *dev; + struct rt_blk_disk *disk; + struct rt_blk_device *blk_dev; + struct rt_device_blk_geometry geome; + struct rt_object_information *info = rt_object_get_information(RT_Object_Class_Device); + + level = rt_hw_interrupt_disable(); + + rt_kprintf("%-*.s MAJ:MIN RM SIZE\tRO TYPE MOUNTPOINT\n", RT_NAME_MAX, "NAME"); + + rt_list_for_each_entry(obj, &info->object_list, list) + { + dev = rt_container_of(obj, struct rt_device, parent); + + if (dev->type != RT_Device_Class_Block) + { + continue; + } + + disk = to_blk_disk(dev); + + if (disk->__magic != RT_BLK_DISK_MAGIC) + { + continue; + } + + if (disk->ops->getgeome(disk, &geome)) + { + continue; + } + + size_name = convert_size(&geome, geome.sector_count, &cap, &minor); + + rt_kprintf("%-*.s %3u.%-3u %u %u.%u%s\t%u disk %s\n", + RT_NAME_MAX, to_disk_name(disk), + #ifdef RT_USING_DM + disk->parent.master_id, disk->parent.device_id, + #else + 0, 0, + #endif + disk->removable, cap, minor, size_name, disk->read_only, + disk->max_partitions != RT_BLK_PARTITION_NONE ? "\b" : + (dfs_filesystem_get_mounted_path(&disk->parent) ? : "\b")); + + rt_list_for_each_entry(blk_dev, &disk->part_nodes, list) + { + size_name = convert_size(&geome, blk_dev->sector_count, &cap, &minor); + + rt_kprintf("%c--%-*.s %3u.%-3u %u %u.%u%s\t%u part %s\n", + blk_dev->list.next != &disk->part_nodes ? '|' : '`', + RT_NAME_MAX - 3, to_blk_name(blk_dev), + #ifdef RT_USING_DM + blk_dev->parent.master_id, blk_dev->parent.device_id, + #else + 0, 0, + #endif + disk->removable, cap, minor, size_name, disk->read_only, + dfs_filesystem_get_mounted_path(&blk_dev->parent) ? : ""); + } + } + + rt_hw_interrupt_enable(level); + + return 0; +} +MSH_CMD_EXPORT(list_blk, dump all of blks information); +#endif /* RT_USING_CONSOLE && RT_USING_MSH */ diff --git a/rt-thread/components/drivers/block/blk_dev.c b/rt-thread/components/drivers/block/blk_dev.c new file mode 100644 index 0000000..5c45aa5 --- /dev/null +++ b/rt-thread/components/drivers/block/blk_dev.c @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI first version + */ + +#include "blk_dev.h" +#include "blk_dfs.h" + +#define DBG_TAG "blk.dm" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_DFS +#include +#endif + +static rt_err_t blk_dev_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct rt_blk_device *blk = to_blk(dev); + + return rt_device_open(&blk->disk->parent, oflag); +} + +static rt_err_t blk_dev_close(rt_device_t dev) +{ + struct rt_blk_device *blk = to_blk(dev); + + return rt_device_close(&blk->disk->parent); +} + +static rt_ssize_t blk_dev_read(rt_device_t dev, rt_off_t sector, + void *buffer, rt_size_t sector_count) +{ + struct rt_blk_device *blk = to_blk(dev); + + if (sector <= blk->sector_start + blk->sector_count && + sector_count <= blk->sector_count) + { + return rt_device_read(&blk->disk->parent, + blk->sector_start + sector, buffer, sector_count); + } + + return -RT_EINVAL; +} + +static rt_ssize_t blk_dev_write(rt_device_t dev, rt_off_t sector, + const void *buffer, rt_size_t sector_count) +{ + struct rt_blk_device *blk = to_blk(dev); + + if (sector <= blk->sector_start + blk->sector_count && + sector_count <= blk->sector_count) + { + return rt_device_write(&blk->disk->parent, + blk->sector_start + sector, buffer, sector_count); + } + + return -RT_EINVAL; +} + +static rt_err_t blk_dev_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t err = -RT_EINVAL; + struct rt_blk_device *blk = to_blk(dev); + struct rt_blk_disk *disk = blk->disk; + struct rt_device_blk_geometry disk_geometry, *geometry; + + switch (cmd) + { + case RT_DEVICE_CTRL_BLK_GETGEOME: + if ((geometry = args)) + { + if (!(err = disk->ops->getgeome(disk, &disk_geometry))) + { + geometry->bytes_per_sector = disk_geometry.bytes_per_sector; + geometry->block_size = disk_geometry.block_size; + geometry->sector_count = blk->sector_count; + } + } + else + { + err = -RT_EINVAL; + } + + break; + + case RT_DEVICE_CTRL_BLK_SYNC: + rt_device_control(&disk->parent, cmd, args); + break; + + case RT_DEVICE_CTRL_BLK_ERASE: + case RT_DEVICE_CTRL_BLK_AUTOREFRESH: + if (disk->partitions <= 1) + { + rt_device_control(&disk->parent, cmd, args); + } + else + { + err = -RT_EIO; + } + break; + + case RT_DEVICE_CTRL_BLK_PARTITION: + if (args) + { + rt_memcpy(args, &blk->partition, sizeof(blk->partition)); + } + else + { + err = -RT_EINVAL; + } + + break; + + case RT_DEVICE_CTRL_BLK_SSIZEGET: + device_get_blk_ssize(dev, args); + err = RT_EOK; + break; + + case RT_DEVICE_CTRL_ALL_BLK_SSIZEGET: + device_get_all_blk_ssize(dev, args); + err = RT_EOK; + break; + + default: + if (disk->ops->control) + { + err = disk->ops->control(disk, blk, cmd, args); + } + break; + } + + return err; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops blk_dev_ops = +{ + .open = blk_dev_open, + .close = blk_dev_close, + .read = blk_dev_read, + .write = blk_dev_write, + .control = blk_dev_control, +}; +#endif + +rt_err_t blk_dev_initialize(struct rt_blk_device *blk) +{ + struct rt_device *dev; + + if (!blk) + { + return -RT_EINVAL; + } + + dev = &blk->parent; + dev->type = RT_Device_Class_Block; +#ifdef RT_USING_DEVICE_OPS + dev->ops = &blk_dev_ops; +#else + dev->open = blk_dev_open; + dev->close = blk_dev_close; + dev->read = blk_dev_read; + dev->write = blk_dev_write; + dev->control = blk_dev_control; +#endif + + return RT_EOK; +} + +rt_err_t disk_add_blk_dev(struct rt_blk_disk *disk, struct rt_blk_device *blk) +{ + rt_err_t err; +#ifdef RT_USING_DM + int device_id; +#endif + const char *disk_name, *name_fmt; + + if (!disk || !blk) + { + return -RT_EINVAL; + } + +#ifdef RT_USING_DM + if ((device_id = rt_dm_ida_alloc(disk->ida)) < 0) + { + return -RT_EFULL; + } +#endif + + blk->disk = disk; + rt_list_init(&blk->list); + + disk_name = to_disk_name(disk); + + /* End is [a-zA-Z] or [0-9] */ + if (disk_name[rt_strlen(disk_name) - 1] < 'a') + { + name_fmt = "%sp%d"; + } + else + { + name_fmt = "%s%d"; + } + +#ifdef RT_USING_DM + rt_dm_dev_set_name(&blk->parent, name_fmt, disk_name, blk->partno); + blk->parent.master_id = disk->ida->master_id; + blk->parent.device_id = device_id; +#else + rt_snprintf(blk->parent.parent.name, RT_NAME_MAX, name_fmt, disk_name, blk->partno); +#endif + device_set_blk_fops(&blk->parent); + + err = rt_device_register(&blk->parent, to_blk_name(blk), + disk->parent.flag & RT_DEVICE_FLAG_RDWR); + + if (err) + { + #ifdef RT_USING_DM + rt_dm_ida_free(disk->ida, device_id); + #endif + return err; + } + + spin_lock(&disk->lock); + + rt_list_insert_before(&disk->part_nodes, &blk->list); + + spin_unlock(&disk->lock); + + return RT_EOK; +} + +rt_err_t disk_remove_blk_dev(struct rt_blk_device *blk, rt_bool_t lockless) +{ + struct rt_blk_disk *disk; + + if (!blk) + { + return -RT_EINVAL; + } + + disk = blk->disk; + + if (!disk) + { + return -RT_EINVAL; + } + else + { + #ifdef RT_USING_DFS + const char *mountpath; + + if ((mountpath = dfs_filesystem_get_mounted_path(&blk->parent))) + { + dfs_unmount(mountpath); + LOG_D("%s: Unmount file system on %s", + to_blk_name(blk), mountpath); + } + #endif + } + +#ifdef RT_USING_DM + rt_dm_ida_free(disk->ida, blk->parent.device_id); +#endif + + rt_device_unregister(&blk->parent); + + if (!lockless) + { + spin_lock(&disk->lock); + } + + rt_list_remove(&blk->list); + + if (!lockless) + { + spin_unlock(&disk->lock); + } + + --disk->partitions; + + return RT_EOK; +} + +rt_uint32_t blk_request_ioprio(void) +{ + struct rt_thread *task = rt_thread_self(); + + return task ? RT_SCHED_PRIV(task).current_priority : 0; +} diff --git a/rt-thread/components/drivers/block/blk_dev.h b/rt-thread/components/drivers/block/blk_dev.h new file mode 100644 index 0000000..b433f57 --- /dev/null +++ b/rt-thread/components/drivers/block/blk_dev.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI first version + */ + +#ifndef __BLK_DEV_H__ +#define __BLK_DEV_H__ + +#include +#include +#include +#include + +#define to_blk_disk(dev) rt_container_of(dev, struct rt_blk_disk, parent) +#define to_blk(dev) rt_container_of(dev, struct rt_blk_device, parent) + +#ifdef RT_USING_DM +#define to_disk_name(disk) rt_dm_dev_get_name(&(disk)->parent) +#define to_blk_name(blk) rt_dm_dev_get_name(&(blk)->parent) +#else +#define to_disk_name(disk) (disk)->parent.parent.name +#define to_blk_name(blk) (blk)->parent.parent.name +#endif + +/* %c%c name */ +#define letter_name(n) ('a' + (n) / ((n) >= 26 ? (26 * 2) : 1)), ((n) >= 26 ? 'a' + (n) % 26 : '\0') + +rt_inline void spin_lock(struct rt_spinlock *spinlock) +{ + rt_hw_spin_lock(&spinlock->lock); +} + +rt_inline void spin_unlock(struct rt_spinlock *spinlock) +{ + rt_hw_spin_unlock(&spinlock->lock); +} + +rt_err_t blk_dev_initialize(struct rt_blk_device *blk); +rt_err_t disk_add_blk_dev(struct rt_blk_disk *disk, struct rt_blk_device *blk); +rt_err_t disk_remove_blk_dev(struct rt_blk_device *blk, rt_bool_t lockless); + +rt_uint32_t blk_request_ioprio(void); + +#endif /* __BLK_DEV_H__ */ diff --git a/rt-thread/components/drivers/block/blk_dfs.c b/rt-thread/components/drivers/block/blk_dfs.c new file mode 100644 index 0000000..96800e1 --- /dev/null +++ b/rt-thread/components/drivers/block/blk_dfs.c @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-08-08 GuEe-GUI first version + */ + +#include "blk_dfs.h" + +#include +#include + +#if defined(RT_USING_POSIX_DEVIO) && defined(RT_USING_DFS_V2) +struct blk_fops_data +{ + struct rt_device_blk_geometry geometry; +}; + +static int blk_fops_open(struct dfs_file *file) +{ + struct rt_device *dev = file->vnode->data; + struct blk_fops_data *data = rt_malloc(sizeof(*data)); + + if (!data) + { + return (int)-RT_ENOMEM; + } + + dev->user_data = data; + rt_device_control(dev, RT_DEVICE_CTRL_BLK_GETGEOME, &data->geometry); + rt_device_control(dev, RT_DEVICE_CTRL_ALL_BLK_SSIZEGET, &file->vnode->size); + + return 0; +} + +static int blk_fops_close(struct dfs_file *file) +{ + struct rt_device *dev = file->vnode->data; + + rt_free(dev->user_data); + dev->user_data = RT_NULL; + + return 0; +} + +static int blk_fops_ioctl(struct dfs_file *file, int cmd, void *arg) +{ + struct rt_device *dev = file->vnode->data; + + return (int)rt_device_control(dev, cmd, arg); +} + +static ssize_t blk_fops_read(struct dfs_file *file, void *buf, size_t count, off_t *pos) +{ + void *rbuf; + rt_ssize_t res = 0; + int bytes_per_sector, blk_pos, first_offs, rsize = 0; + struct rt_device *dev = file->vnode->data; + struct blk_fops_data *data = dev->user_data; + + bytes_per_sector = data->geometry.bytes_per_sector; + blk_pos = *pos / bytes_per_sector; + first_offs = *pos % bytes_per_sector; + + if ((rbuf = rt_malloc(bytes_per_sector))) + { + /* + ** #1: read first unalign block size. + */ + res = rt_device_read(dev, blk_pos, rbuf, 1); + + if (res == 1) + { + if (count > bytes_per_sector - first_offs) + { + rsize = bytes_per_sector - first_offs; + } + else + { + rsize = count; + } + rt_memcpy(buf, rbuf + first_offs, rsize); + ++blk_pos; + + /* + ** #2: read continuous block size. + */ + while (rsize < count) + { + res = rt_device_read(dev, blk_pos++, rbuf, 1); + + if (res != 1) + { + break; + } + + if (count - rsize >= bytes_per_sector) + { + rt_memcpy(buf + rsize, rbuf, bytes_per_sector); + rsize += bytes_per_sector; + } + else + { + rt_memcpy(buf + rsize, rbuf, count - rsize); + rsize = count; + } + } + + *pos += rsize; + } + + rt_free(rbuf); + } + + return rsize; +} + +static ssize_t blk_fops_write(struct dfs_file *file, const void *buf, size_t count, off_t *pos) +{ + void *rbuf; + rt_ssize_t res = 0; + int bytes_per_sector, blk_pos, first_offs, wsize = 0; + struct rt_device *dev = file->vnode->data; + struct blk_fops_data *data = dev->user_data; + + bytes_per_sector = data->geometry.bytes_per_sector; + blk_pos = *pos / bytes_per_sector; + first_offs = *pos % bytes_per_sector; + + /* + ** #1: write first unalign block size. + */ + if (first_offs != 0) + { + if (count > bytes_per_sector - first_offs) + { + wsize = bytes_per_sector - first_offs; + } + else + { + wsize = count; + } + + if ((rbuf = rt_malloc(bytes_per_sector))) + { + res = rt_device_read(dev, blk_pos, rbuf, 1); + + if (res == 1) + { + rt_memcpy(rbuf + first_offs, buf, wsize); + res = rt_device_write(dev, blk_pos, (const void *)rbuf, 1); + + if (res == 1) + { + blk_pos += 1; + rt_free(rbuf); + + goto _goon; + } + } + + rt_free(rbuf); + } + + return 0; + } + +_goon: + /* + ** #2: write continuous block size. + */ + if ((count - wsize) / bytes_per_sector != 0) + { + res = rt_device_write(dev, blk_pos, buf + wsize, (count - wsize) / bytes_per_sector); + wsize += res * bytes_per_sector; + blk_pos += res; + + if (res != (count - wsize) / bytes_per_sector) + { + *pos += wsize; + return wsize; + } + } + + /* + ** # 3: write last unalign block size. + */ + if ((count - wsize) != 0) + { + if ((rbuf = rt_malloc(bytes_per_sector))) + { + res = rt_device_read(dev, blk_pos, rbuf, 1); + + if (res == 1) + { + rt_memcpy(rbuf, buf + wsize, count - wsize); + res = rt_device_write(dev, blk_pos, (const void *)rbuf, 1); + + if (res == 1) + { + wsize += count - wsize; + } + } + + rt_free(rbuf); + } + } + + *pos += wsize; + return wsize; +} + +static int blk_fops_flush(struct dfs_file *file) +{ + struct rt_device *dev = file->vnode->data; + + return (int)rt_device_control(dev, RT_DEVICE_CTRL_BLK_SYNC, RT_NULL); +} + +static int blk_fops_poll(struct dfs_file *file, struct rt_pollreq *req) +{ + int mask = 0; + + return mask; +} + +const static struct dfs_file_ops blk_fops = +{ + .open = blk_fops_open, + .close = blk_fops_close, + .ioctl = blk_fops_ioctl, + .read = blk_fops_read, + .write = blk_fops_write, + .flush = blk_fops_flush, + .lseek = generic_dfs_lseek, + .poll = blk_fops_poll +}; + +void device_set_blk_fops(struct rt_device *dev) +{ + dev->fops = &blk_fops; +} +#else +void device_set_blk_fops(struct rt_device *dev) +{ +} +#endif /* RT_USING_POSIX_DEVIO && RT_USING_DFS_V2 */ + +void device_get_blk_ssize(struct rt_device *dev, void *args) +{ + rt_uint32_t bytes_per_sector; + struct rt_device_blk_geometry geometry; + + rt_device_control(dev, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); + bytes_per_sector = geometry.bytes_per_sector; + + RT_ASSERT(sizeof(bytes_per_sector) == sizeof(geometry.bytes_per_sector)); + + rt_memcpy(args, &bytes_per_sector, sizeof(bytes_per_sector)); +} + +void device_get_all_blk_ssize(struct rt_device *dev, void *args) +{ + rt_uint64_t count_mul_per; + struct rt_device_blk_geometry geometry; + + rt_device_control(dev, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); + count_mul_per = geometry.bytes_per_sector * geometry.sector_count; + + rt_memcpy(args, &count_mul_per, sizeof(count_mul_per)); +} diff --git a/rt-thread/components/drivers/block/blk_dfs.h b/rt-thread/components/drivers/block/blk_dfs.h new file mode 100644 index 0000000..c532869 --- /dev/null +++ b/rt-thread/components/drivers/block/blk_dfs.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-08-08 GuEe-GUI first version + */ + +#ifndef __BLK_DFS_H__ +#define __BLK_DFS_H__ + +#include + +#define RT_DEVICE_CTRL_BLK_SSIZEGET 0x00001268 /**< get number of bytes per sector */ +#define RT_DEVICE_CTRL_ALL_BLK_SSIZEGET 0x80081272 /**< get number of bytes per sector * sector counts */ + +void device_set_blk_fops(struct rt_device *dev); +void device_get_blk_ssize(struct rt_device *dev, void *args); +void device_get_all_blk_ssize(struct rt_device *dev, void *args); + +#endif /* __BLK_DFS_H__ */ diff --git a/rt-thread/components/drivers/block/blk_partition.c b/rt-thread/components/drivers/block/blk_partition.c new file mode 100644 index 0000000..5a9e39d --- /dev/null +++ b/rt-thread/components/drivers/block/blk_partition.c @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#define DBG_TAG "blk.part" +#define DBG_LVL DBG_INFO +#include + +#include "blk_partition.h" + +static rt_err_t (*partition_list[])(struct rt_blk_disk *) = +{ +#ifdef RT_BLK_PARTITION_EFI + efi_partition, +#endif +#ifdef RT_BLK_PARTITION_DFS + dfs_partition, +#endif +}; + +rt_err_t blk_put_partition(struct rt_blk_disk *disk, const char *type, + rt_size_t start, rt_size_t count, int partno) +{ + rt_err_t err; + + struct rt_blk_device *blk = rt_calloc(1, sizeof(*blk)); + + if (type && rt_strcmp(type, "dfs")) + { + rt_uint32_t ssz = rt_blk_disk_get_logical_block_size(disk); + + rt_kprintf("found part[%u], begin: %lu, size: ", partno, start * ssz); + + if ((count >> 11) == 0) + { + rt_kprintf("%u%cB\n", count >> 1, 'K'); /* KB */ + } + else + { + rt_uint32_t size_mb = count >> 11; /* MB */ + + if ((size_mb >> 10) == 0) + { + rt_kprintf("%u.%u%cB\n", size_mb, (count >> 1) & 0x3ff, 'M'); + } + else + { + rt_kprintf("%u.%u%cB\n", size_mb >> 10, size_mb & 0x3ff, 'G'); + } + } + } + + if (!blk) + { + err = -RT_ENOMEM; + goto _fail; + } + + err = blk_dev_initialize(blk); + + if (err) + { + goto _fail; + } + + blk->partno = partno; + blk->sector_start = start; + blk->sector_count = count; + + blk->partition.offset = start; + blk->partition.size = count; + blk->partition.lock = &disk->usr_lock; + + err = disk_add_blk_dev(disk, blk); + + if (err) + { + goto _fail; + } + + ++disk->partitions; + + return RT_EOK; + +_fail: + LOG_E("%s: Put partition.%s[%u] start = %lu count = %lu error = %s", + to_disk_name(disk), type, partno, start, count, rt_strerror(err)); + + if (blk) + { + rt_free(blk); + } + + return err; +} + +rt_err_t rt_blk_disk_probe_partition(struct rt_blk_disk *disk) +{ + rt_err_t err = RT_EOK; + + if (!disk) + { + return -RT_EINVAL; + } + + LOG_D("%s: Probing disk partitions", to_disk_name(disk)); + + if (disk->partitions) + { + return err; + } + + err = -RT_EEMPTY; + + if (disk->max_partitions == RT_BLK_PARTITION_NONE) + { + LOG_D("%s: Unsupported partitions", to_disk_name(disk)); + + return err; + } + + for (int i = 0; i < RT_ARRAY_SIZE(partition_list); ++i) + { + rt_err_t part_err = partition_list[i](disk); + + if (part_err == -RT_ENOMEM) + { + err = part_err; + break; + } + + if (!part_err) + { + err = RT_EOK; + break; + } + } + + if ((err && err != -RT_ENOMEM) || disk->partitions == 0) + { + /* No partition found */ + rt_size_t total_sectors = rt_blk_disk_get_capacity(disk); + + err = blk_put_partition(disk, RT_NULL, 0, total_sectors, 0); + } + + return err; +} diff --git a/rt-thread/components/drivers/block/blk_partition.h b/rt-thread/components/drivers/block/blk_partition.h new file mode 100644 index 0000000..fb7158f --- /dev/null +++ b/rt-thread/components/drivers/block/blk_partition.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI first version + */ + +#ifndef __BLK_PARTITION_H__ +#define __BLK_PARTITION_H__ + +#include "blk_dev.h" + +rt_err_t blk_put_partition(struct rt_blk_disk *disk, const char *type, + rt_size_t start, rt_size_t count, int partno); + +rt_err_t dfs_partition(struct rt_blk_disk *disk); +rt_err_t efi_partition(struct rt_blk_disk *disk); + +#endif /* __BLK_PARTITION_H__ */ diff --git a/rt-thread/components/drivers/block/partitions/Kconfig b/rt-thread/components/drivers/block/partitions/Kconfig new file mode 100644 index 0000000..6df5e71 --- /dev/null +++ b/rt-thread/components/drivers/block/partitions/Kconfig @@ -0,0 +1,12 @@ +menu "Partition Types" + +config RT_BLK_PARTITION_DFS + bool "DFS Partition support" + depends on RT_USING_DFS + default y + +config RT_BLK_PARTITION_EFI + bool "EFI Globally Unique Identifier (GUID) Partition support" + default y + +endmenu diff --git a/rt-thread/components/drivers/block/partitions/SConscript b/rt-thread/components/drivers/block/partitions/SConscript new file mode 100644 index 0000000..06b320b --- /dev/null +++ b/rt-thread/components/drivers/block/partitions/SConscript @@ -0,0 +1,18 @@ +from building import * + +group = [] + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../../include'] + +src = [] + +if GetDepend(['RT_BLK_PARTITION_DFS']): + src += ['dfs.c'] + +if GetDepend(['RT_BLK_PARTITION_EFI']): + src += ['efi.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/block/partitions/dfs.c b/rt-thread/components/drivers/block/partitions/dfs.c new file mode 100644 index 0000000..3fdad1a --- /dev/null +++ b/rt-thread/components/drivers/block/partitions/dfs.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-07-25 weety first version + * 2023-02-25 GuEe-GUI make blk interface + */ + +#include "efi.h" + +#define DBG_TAG "blk.part.dfs" +#define DBG_LVL DBG_INFO +#include + +rt_err_t dfs_partition(struct rt_blk_disk *disk) +{ + rt_ssize_t res; + struct dfs_partition part; + rt_uint8_t *sector = rt_malloc(rt_blk_disk_get_logical_block_size(disk)); + + if (!sector) + { + return -RT_ENOMEM; + } + + res = disk->ops->read(disk, 0, sector, 1); + + if (res < 0) + { + rt_free(sector); + return res; + } + + for (rt_size_t i = 0; i < disk->max_partitions; ++i) + { + res = dfs_filesystem_get_partition(&part, sector, i); + + if (res) + { + break; + } + + if (blk_put_partition(disk, "dfs", part.offset, part.size, i) == -RT_ENOMEM) + { + break; + } + } + + rt_free(sector); + + return RT_EOK; +} diff --git a/rt-thread/components/drivers/block/partitions/efi.c b/rt-thread/components/drivers/block/partitions/efi.c new file mode 100644 index 0000000..a68a147 --- /dev/null +++ b/rt-thread/components/drivers/block/partitions/efi.c @@ -0,0 +1,738 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-05-05 linzhenxing first version + * 2023-02-25 GuEe-GUI make blk interface + */ + +#include "efi.h" + +#define DBG_TAG "blk.part.efi" +#define DBG_LVL DBG_INFO +#include + +static rt_bool_t force_gpt = 0; + +static int force_gpt_setup(void) +{ +#ifdef RT_USING_OFW + force_gpt = !!rt_ofw_bootargs_select("gpt", 0); +#endif + + return 0; +} +INIT_CORE_EXPORT(force_gpt_setup); + +/** + * @brief This function is EFI version of crc32 function. + * + * @param buf the buffer to calculate crc32 of. + * @param len the length of buf. + * @return EFI-style CRC32 value for @buf. + */ +rt_inline rt_uint32_t efi_crc32(const rt_uint8_t *buf, rt_size_t len) +{ + rt_ubase_t crc = 0xffffffffUL; + + for (rt_size_t i = 0; i < len; ++i) + { + crc ^= buf[i]; + + for (int j = 0; j < 8; ++j) + { + crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320L : 0); + } + } + + return ~crc; +} + +/** + * @brief This function get number of last logical block of device. + * + * @param disk the blk of disk. + * @return last LBA value on success, 0 on error. + * This is stored (by sd and ide-geometry) in + * the part[0] entry for this disk, and is the number of + * physical sectors available on the disk. + */ +static rt_size_t last_lba(struct rt_blk_disk *disk) +{ + return rt_blk_disk_get_capacity(disk) - 1ULL; +} + +rt_inline int pmbr_part_valid(gpt_mbr_record *part) +{ + if (part->os_type != EFI_PMBR_OSTYPE_EFI_GPT) + { + return 0; + } + + /* set to 0x00000001 (i.e., the LBA of the GPT Partition Header) */ + if (rt_le32_to_cpu(part->starting_lba) != GPT_PRIMARY_PARTITION_TABLE_LBA) + { + return 0; + } + + return GPT_MBR_PROTECTIVE; +} + +/** + * @brief This function test Protective MBR for validity. + * + * @param mbr the pointer to a legacy mbr structure. + * @param total_sectors the amount of sectors in the device + * @return + * 0 -> Invalid MBR + * 1 -> GPT_MBR_PROTECTIVE + * 2 -> GPT_MBR_HYBRID + */ +static int is_pmbr_valid(legacy_mbr *mbr, rt_size_t total_sectors) +{ + rt_uint32_t sz = 0; + int part = 0, ret = 0; /* invalid by default */ + + if (!mbr || rt_le16_to_cpu(mbr->signature) != MSDOS_MBR_SIGNATURE) + { + goto _done; + } + + for (int i = 0; i < 4; ++i) + { + ret = pmbr_part_valid(&mbr->partition_record[i]); + + if (ret == GPT_MBR_PROTECTIVE) + { + part = i; + /* + * Ok, we at least know that there's a protective MBR, + * now check if there are other partition types for + * hybrid MBR. + */ + goto _check_hybrid; + } + } + + if (ret != GPT_MBR_PROTECTIVE) + { + goto _done; + } + +_check_hybrid: + for (int i = 0; i < 4; i++) + { + if (mbr->partition_record[i].os_type != EFI_PMBR_OSTYPE_EFI_GPT && + mbr->partition_record[i].os_type != 0x00) + { + ret = GPT_MBR_HYBRID; + } + } + + /* + * Protective MBRs take up the lesser of the whole disk + * or 2 TiB (32bit LBA), ignoring the rest of the disk. + * Some partitioning programs, nonetheless, choose to set + * the size to the maximum 32-bit limitation, disregarding + * the disk size. + * + * Hybrid MBRs do not necessarily comply with this. + * + * Consider a bad value here to be a warning to support dd'ing + * an image from a smaller disk to a larger disk. + */ + if (ret == GPT_MBR_PROTECTIVE) + { + sz = rt_le32_to_cpu(mbr->partition_record[part].size_in_lba); + + if (sz != (rt_uint32_t)total_sectors - 1 && sz != 0xffffffff) + { + LOG_W("GPT: mbr size in lba (%u) different than whole disk (%u)", + sz, rt_min_t(rt_uint32_t, total_sectors - 1, 0xffffffff)); + } + } + +_done: + return ret; +} + +/** + * @brief This function read bytes from disk, starting at given LBA. + * + * @param disk the blk of disk. + * @param lba the Logical Block Address of the partition table. + * @param buffer the destination buffer. + * @param count the bytes to read. + * @return number of bytes read on success, 0 on error. + */ +static rt_size_t read_lba(struct rt_blk_disk *disk, + rt_uint64_t lba, rt_uint8_t *buffer, rt_size_t count) +{ + rt_size_t totalreadcount = 0; + + if (!buffer || lba > last_lba(disk)) + { + return 0; + } + + for (rt_uint64_t n = lba; count; ++n) + { + int copied = 512; + + disk->ops->read(disk, n, buffer, 1); + + if (copied > count) + { + copied = count; + } + + buffer += copied; + totalreadcount += copied; + count -= copied; + } + + return totalreadcount; +} + +/** + * @brief This function reads partition entries from disk. + * + * @param disk the blk of disk. + * @param gpt the GPT header + * @return ptes on success, null on error. + */ +static gpt_entry *alloc_read_gpt_entries(struct rt_blk_disk *disk, + gpt_header *gpt) +{ + rt_size_t count; + gpt_entry *pte; + rt_uint64_t entry_lba; + + if (!gpt) + { + return RT_NULL; + } + + count = (rt_size_t)rt_le32_to_cpu(gpt->num_partition_entries) * + rt_le32_to_cpu(gpt->sizeof_partition_entry); + + if (!count) + { + return RT_NULL; + } + + pte = rt_malloc(count); + + if (!pte) + { + return RT_NULL; + } + + entry_lba = rt_le64_to_cpu(gpt->partition_entry_lba); + + if (read_lba(disk, entry_lba, (rt_uint8_t *)pte, count) < count) + { + rt_free(pte); + pte = RT_NULL; + + return RT_NULL; + } + + /* Remember to free pte when done */ + return pte; +} + +/** + * @brief This function allocates GPT header, reads into it from disk. + * + * @param disk the blk of disk. + * @param lba the Logical Block Address of the partition table + * @return GPT header on success, null on error. + */ +static gpt_header *alloc_read_gpt_header(struct rt_blk_disk *disk, rt_uint64_t lba) +{ + gpt_header *gpt; + rt_uint32_t ssz = rt_blk_disk_get_logical_block_size(disk); + + gpt = rt_malloc(ssz); + + if (!gpt) + { + return RT_NULL; + } + + if (read_lba(disk, lba, (rt_uint8_t *)gpt, ssz) < ssz) + { + rt_free(gpt); + gpt = RT_NULL; + + return RT_NULL; + } + + /* Remember to free gpt when finished with it */ + return gpt; +} + +/** + * @brief This function tests one GPT header and PTEs for validity. + * + * @param disk the blk of disk. + * @param lba the Logical Block Address of the GPT header to test. + * @param gpt the GPT header ptr, filled on return. + * @param ptes the PTEs ptr, filled on return. + * @returns true if valid, false on error. + * If valid, returns pointers to newly allocated GPT header and PTEs. + */ +static rt_bool_t is_gpt_valid(struct rt_blk_disk *disk, + rt_uint64_t lba, gpt_header **gpt, gpt_entry **ptes) +{ + rt_uint32_t crc, origcrc; + rt_uint64_t lastlba, pt_size; + rt_ssize_t logical_block_size; + + if (!ptes) + { + return RT_FALSE; + } + + if (!(*gpt = alloc_read_gpt_header(disk, lba))) + { + return RT_FALSE; + } + + /* Check the GUID Partition Table signature */ + if (rt_le64_to_cpu((*gpt)->signature) != GPT_HEADER_SIGNATURE) + { + LOG_D("%s: GUID Partition Table Header signature is wrong: %lld != %lld", + to_disk_name(disk), + (rt_uint64_t)rt_le64_to_cpu((*gpt)->signature), + (rt_uint64_t)GPT_HEADER_SIGNATURE); + + goto _fail; + } + + /* Check the GUID Partition Table header size is too big */ + logical_block_size = rt_blk_disk_get_logical_block_size(disk); + + if (rt_le32_to_cpu((*gpt)->header_size) > logical_block_size) + { + LOG_D("%s: GUID Partition Table Header size is too large: %u > %u", + to_disk_name(disk), + rt_le32_to_cpu((*gpt)->header_size), + logical_block_size); + + goto _fail; + } + + /* Check the GUID Partition Table header size is too small */ + if (rt_le32_to_cpu((*gpt)->header_size) < sizeof(gpt_header)) + { + LOG_D("%s: GUID Partition Table Header size is too small: %u < %u", + to_disk_name(disk), + rt_le32_to_cpu((*gpt)->header_size), + sizeof(gpt_header)); + + goto _fail; + } + + /* Check the GUID Partition Table CRC */ + origcrc = rt_le32_to_cpu((*gpt)->header_crc32); + (*gpt)->header_crc32 = 0; + crc = efi_crc32((const rt_uint8_t *)(*gpt), rt_le32_to_cpu((*gpt)->header_size)); + + if (crc != origcrc) + { + LOG_D("%s: GUID Partition Table Header CRC is wrong: %x != %x", + to_disk_name(disk), crc, origcrc); + + goto _fail; + } + + (*gpt)->header_crc32 = rt_cpu_to_le32(origcrc); + + /* + * Check that the start_lba entry points to the LBA that contains + * the GUID Partition Table + */ + if (rt_le64_to_cpu((*gpt)->start_lba) != lba) + { + LOG_D("%s: GPT start_lba incorrect: %lld != %lld", + to_disk_name(disk), + (rt_uint64_t)rt_le64_to_cpu((*gpt)->start_lba), + (rt_uint64_t)lba); + + goto _fail; + } + + /* Check the first_usable_lba and last_usable_lba are within the disk */ + lastlba = last_lba(disk); + + if (rt_le64_to_cpu((*gpt)->first_usable_lba) > lastlba) + { + LOG_D("%s: GPT: first_usable_lba incorrect: %lld > %lld", + to_disk_name(disk), + (rt_uint64_t)rt_le64_to_cpu((*gpt)->first_usable_lba), + (rt_uint64_t)lastlba); + + goto _fail; + } + + if (rt_le64_to_cpu((*gpt)->last_usable_lba) > lastlba) + { + LOG_D("%s: GPT: last_usable_lba incorrect: %lld > %lld", + to_disk_name(disk), + (rt_uint64_t)rt_le64_to_cpu((*gpt)->last_usable_lba), + (rt_uint64_t)lastlba); + + goto _fail; + } + if (rt_le64_to_cpu((*gpt)->last_usable_lba) < rt_le64_to_cpu((*gpt)->first_usable_lba)) + { + LOG_D("%s: GPT: last_usable_lba incorrect: %lld > %lld", + to_disk_name(disk), + (rt_uint64_t)rt_le64_to_cpu((*gpt)->last_usable_lba), + (rt_uint64_t)rt_le64_to_cpu((*gpt)->first_usable_lba)); + + goto _fail; + } + + /* Check that sizeof_partition_entry has the correct value */ + if (rt_le32_to_cpu((*gpt)->sizeof_partition_entry) != sizeof(gpt_entry)) + { + LOG_D("%s: GUID Partition Entry Size check failed", to_disk_name(disk)); + + goto _fail; + } + + /* Sanity check partition table size */ + pt_size = (rt_uint64_t)rt_le32_to_cpu((*gpt)->num_partition_entries) * + rt_le32_to_cpu((*gpt)->sizeof_partition_entry); + + if (!(*ptes = alloc_read_gpt_entries(disk, *gpt))) + { + goto _fail; + } + + /* Check the GUID Partition Entry Array CRC */ + crc = efi_crc32((const rt_uint8_t *)(*ptes), pt_size); + + if (crc != rt_le32_to_cpu((*gpt)->partition_entry_array_crc32)) + { + LOG_D("%s: GUID Partition Entry Array CRC check failed", to_disk_name(disk)); + + goto _fail_ptes; + } + + /* We're done, all's well */ + return RT_TRUE; + +_fail_ptes: + rt_free(*ptes); + *ptes = RT_NULL; + +_fail: + rt_free(*gpt); + *gpt = RT_NULL; + + return RT_FALSE; +} + +/** + * @brief This function tests one PTE for validity. + * + * @param pte the pte to check. + * @param lastlba the last lba of the disk. + * @return valid boolean of pte. + */ +rt_inline rt_bool_t is_pte_valid(const gpt_entry *pte, const rt_size_t lastlba) +{ + if ((!efi_guidcmp(pte->partition_type_guid, NULL_GUID)) || + rt_le64_to_cpu(pte->starting_lba) > lastlba || + rt_le64_to_cpu(pte->ending_lba) > lastlba) + { + return RT_FALSE; + } + + return RT_TRUE; +} + +/** + * @brief This function search disk for valid GPT headers and PTEs. + * + * @param disk the blk of disk. + * @param pgpt the primary GPT header. + * @param agpt the alternate GPT header. + * @param lastlba the last LBA number. + */ +static void compare_gpts(struct rt_blk_disk *disk, + gpt_header *pgpt, gpt_header *agpt, rt_uint64_t lastlba) +{ + int error_found = 0; + + if (!pgpt || !agpt) + { + return; + } + + if (rt_le64_to_cpu(pgpt->start_lba) != rt_le64_to_cpu(agpt->alternate_lba)) + { + LOG_W("%s: GPT:Primary header LBA(%lld) != Alt(%lld), header alternate_lba", + to_disk_name(disk), + (rt_uint64_t)rt_le64_to_cpu(pgpt->start_lba), + (rt_uint64_t)rt_le64_to_cpu(agpt->alternate_lba)); + + ++error_found; + } + + if (rt_le64_to_cpu(pgpt->alternate_lba) != rt_le64_to_cpu(agpt->start_lba)) + { + LOG_W("%s: GPT:Primary header alternate_lba(%lld) != Alt(%lld), header start_lba", + to_disk_name(disk), + (rt_uint64_t)rt_le64_to_cpu(pgpt->alternate_lba), + (rt_uint64_t)rt_le64_to_cpu(agpt->start_lba)); + + ++error_found; + } + + if (rt_le64_to_cpu(pgpt->first_usable_lba) != rt_le64_to_cpu(agpt->first_usable_lba)) + { + LOG_W("%s: GPT:first_usable_lbas don't match %lld != %lld", + to_disk_name(disk), + (rt_uint64_t)rt_le64_to_cpu(pgpt->first_usable_lba), + (rt_uint64_t)rt_le64_to_cpu(agpt->first_usable_lba)); + + ++error_found; + } + + if (rt_le64_to_cpu(pgpt->last_usable_lba) != rt_le64_to_cpu(agpt->last_usable_lba)) + { + LOG_W("%s: GPT:last_usable_lbas don't match %lld != %lld", + to_disk_name(disk), + (rt_uint64_t)rt_le64_to_cpu(pgpt->last_usable_lba), + (rt_uint64_t)rt_le64_to_cpu(agpt->last_usable_lba)); + + ++error_found; + } + + if (efi_guidcmp(pgpt->disk_guid, agpt->disk_guid)) + { + LOG_W("%s: GPT:disk_guids don't match", to_disk_name(disk)); + + ++error_found; + } + + if (rt_le32_to_cpu(pgpt->num_partition_entries) != + rt_le32_to_cpu(agpt->num_partition_entries)) + { + LOG_W("%s: GPT:num_partition_entries don't match: 0x%x != 0x%x", + to_disk_name(disk), + rt_le32_to_cpu(pgpt->num_partition_entries), + rt_le32_to_cpu(agpt->num_partition_entries)); + + ++error_found; + } + + if (rt_le32_to_cpu(pgpt->sizeof_partition_entry) != + rt_le32_to_cpu(agpt->sizeof_partition_entry)) + { + LOG_W("%s: GPT:sizeof_partition_entry values don't match: 0x%x != 0x%x", + to_disk_name(disk), + rt_le32_to_cpu(pgpt->sizeof_partition_entry), + rt_le32_to_cpu(agpt->sizeof_partition_entry)); + + ++error_found; + } + + if (rt_le32_to_cpu(pgpt->partition_entry_array_crc32) != + rt_le32_to_cpu(agpt->partition_entry_array_crc32)) + { + LOG_W("%s: GPT:partition_entry_array_crc32 values don't match: 0x%x != 0x%x", + to_disk_name(disk), + rt_le32_to_cpu(pgpt->partition_entry_array_crc32), + rt_le32_to_cpu(agpt->partition_entry_array_crc32)); + + ++error_found; + } + + if (rt_le64_to_cpu(pgpt->alternate_lba) != lastlba) + { + LOG_W("%s: GPT:Primary header thinks Alt. header is not at the end of the disk: %lld != %lld", + to_disk_name(disk), + (rt_uint64_t)rt_le64_to_cpu(pgpt->alternate_lba), + (rt_uint64_t)lastlba); + + ++error_found; + } + + if (rt_le64_to_cpu(agpt->start_lba) != lastlba) + { + LOG_W("%s: GPT:Alternate GPT header not at the end of the disk: %lld != %lld", + to_disk_name(disk), + (rt_uint64_t)rt_le64_to_cpu(agpt->start_lba), + (rt_uint64_t)lastlba); + + ++error_found; + } + + if (error_found) + { + LOG_W("GPT: Use GNU Parted to correct GPT errors"); + } +} + +/** + * @brief This function search disk for valid GPT headers and PTEs. + * + * @param disk the disk parsed partitions. + * @param gpt the GPT header ptr, filled on return. + * @param ptes the PTEs ptr, filled on return. + * @return 1 if valid, 0 on error. + * If valid, returns pointers to newly allocated GPT header and PTEs. + * Validity depends on PMBR being valid (or being overridden by the + * 'gpt' kernel command line option) and finding either the Primary + * GPT header and PTEs valid, or the Alternate GPT header and PTEs + * valid. If the Primary GPT header is not valid, the Alternate GPT header + * is not checked unless the 'gpt' kernel command line option is passed. + * This protects against devices which misreport their size, and forces + * the user to decide to use the Alternate GPT. + */ +static rt_bool_t find_valid_gpt(struct rt_blk_disk *disk, + gpt_header **gpt, gpt_entry **ptes) +{ + int good_pgpt = 0, good_agpt = 0, good_pmbr = 0; + gpt_header *pgpt = RT_NULL, *agpt = RT_NULL; + gpt_entry *pptes = RT_NULL, *aptes = RT_NULL; + legacy_mbr *legacymbr; + rt_size_t total_sectors = rt_blk_disk_get_capacity(disk); + rt_size_t lastlba; + + if (!ptes) + { + return RT_FALSE; + } + + lastlba = last_lba(disk); + + if (!force_gpt) + { + /* This will be added to the EFI Spec. per Intel after v1.02. */ + legacymbr = rt_malloc(sizeof(*legacymbr)); + + if (!legacymbr) + { + return RT_FALSE; + } + + read_lba(disk, 0, (rt_uint8_t *)legacymbr, sizeof(*legacymbr)); + good_pmbr = is_pmbr_valid(legacymbr, total_sectors); + rt_free(legacymbr); + + if (!good_pmbr) + { + return RT_FALSE; + } + + LOG_D("%s: Device has a %s MBR", to_disk_name(disk), + good_pmbr == GPT_MBR_PROTECTIVE ? "protective" : "hybrid"); + } + + good_pgpt = is_gpt_valid(disk, GPT_PRIMARY_PARTITION_TABLE_LBA, &pgpt, &pptes); + + if (good_pgpt) + { + good_agpt = is_gpt_valid(disk, rt_le64_to_cpu(pgpt->alternate_lba), &agpt, &aptes); + } + + if (!good_agpt && force_gpt) + { + good_agpt = is_gpt_valid(disk, lastlba, &agpt, &aptes); + } + + /* The obviously unsuccessful case */ + if (!good_pgpt && !good_agpt) + { + goto _fail; + } + + compare_gpts(disk, pgpt, agpt, lastlba); + + /* The good cases */ + if (good_pgpt) + { + *gpt = pgpt; + *ptes = pptes; + rt_free(agpt); + rt_free(aptes); + + if (!good_agpt) + { + LOG_D("%s: Alternate GPT is invalid, using primary GPT", to_disk_name(disk)); + } + + return RT_TRUE; + } + else if (good_agpt) + { + *gpt = agpt; + *ptes = aptes; + rt_free(pgpt); + rt_free(pptes); + + LOG_D("%s: Primary GPT is invalid, using alternate GPT", to_disk_name(disk)); + + return RT_TRUE; + } + +_fail: + rt_free(pgpt); + rt_free(agpt); + rt_free(pptes); + rt_free(aptes); + + *gpt = RT_NULL; + *ptes = RT_NULL; + + return RT_FALSE; +} + +rt_err_t efi_partition(struct rt_blk_disk *disk) +{ + rt_uint32_t entries_nr; + gpt_header *gpt = RT_NULL; + gpt_entry *ptes = RT_NULL; + + if (!find_valid_gpt(disk, &gpt, &ptes) || !gpt || !ptes) + { + rt_free(gpt); + rt_free(ptes); + + return -RT_EINVAL; + } + + entries_nr = rt_le32_to_cpu(gpt->num_partition_entries); + + for (int i = 0; i < entries_nr && i < disk->max_partitions; ++i) + { + rt_uint64_t start = rt_le64_to_cpu(ptes[i].starting_lba); + rt_uint64_t size = rt_le64_to_cpu(ptes[i].ending_lba) - + rt_le64_to_cpu(ptes[i].starting_lba) + 1ULL; + + if (!is_pte_valid(&ptes[i], last_lba(disk))) + { + continue; + } + + if (blk_put_partition(disk, "gpt", start, size, i) == -RT_ENOMEM) + { + break; + } + } + + rt_free(gpt); + rt_free(ptes); + + return RT_EOK; +} diff --git a/rt-thread/components/drivers/block/partitions/efi.h b/rt-thread/components/drivers/block/partitions/efi.h new file mode 100644 index 0000000..6a10ec8 --- /dev/null +++ b/rt-thread/components/drivers/block/partitions/efi.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-05-05 linzhenxing first version + * 2023-02-25 GuEe-GUI make blk interface + */ + +#ifndef __PARTITIONS_EFI_H__ +#define __PARTITIONS_EFI_H__ + +#include "../blk_partition.h" +#include +#include + +#define MSDOS_MBR_SIGNATURE 0xaa55 +#define EFI_PMBR_OSTYPE_EFI 0xef +#define EFI_PMBR_OSTYPE_EFI_GPT 0xee + +#define GPT_MBR_PROTECTIVE 1 +#define GPT_MBR_HYBRID 2 + +#define GPT_HEADER_SIGNATURE 0x5452415020494645ULL +#define GPT_HEADER_REVISION_V1 0x00010000 +#define GPT_PRIMARY_PARTITION_TABLE_LBA 1 + +#ifndef __UUID_H__ +#define UUID_SIZE 16 + +typedef struct +{ + rt_uint8_t b[UUID_SIZE]; +} guid_t; +#endif /* __UUID_H__ */ + +#ifndef __EFI_H__ +typedef guid_t efi_guid_t rt_align(4); + +#define EFI_GUID(a, b, c, d...) (efi_guid_t) \ +{{ \ + (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \ + (b) & 0xff, ((b) >> 8) & 0xff, \ + (c) & 0xff, ((c) >> 8) & 0xff, \ + d \ +}} + +#define NULL_GUID \ + EFI_GUID(0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00) + +rt_inline int efi_guidcmp(efi_guid_t left, efi_guid_t right) +{ + return rt_memcmp(&left, &right, sizeof (efi_guid_t)); +} +#endif /* __EFI_H__ */ + +#define PARTITION_SYSTEM_GUID \ + EFI_GUID(0xc12a7328, 0xf81f, 0x11d2, 0xba, 0x4b, 0x00, 0xa0, 0xc9, 0x3e, 0xc9, 0x3b) + +#define LEGACY_MBR_PARTITION_GUID \ + EFI_GUID(0x024dee41, 0x33e7, 0x11d3, 0x9d, 0x69, 0x00, 0x08, 0xc7, 0x81, 0xf3, 0x9f) + +#define PARTITION_MSFT_RESERVED_GUID \ + EFI_GUID(0xe3c9e316, 0x0b5c, 0x4db8, 0x81, 0x7d, 0xf9, 0x2d, 0xf0, 0x02, 0x15, 0xae) + +#define PARTITION_BASIC_DATA_GUID \ + EFI_GUID(0xebd0a0a2, 0xb9e5, 0x4433, 0x87, 0xc0, 0x68, 0xb6, 0xb7, 0x26, 0x99, 0xc7) + +rt_packed(struct _gpt_header +{ + rt_le64_t signature; + rt_le32_t revision; + rt_le32_t header_size; + rt_le32_t header_crc32; + rt_le32_t reserved1; + rt_le64_t start_lba; + rt_le64_t alternate_lba; + rt_le64_t first_usable_lba; + rt_le64_t last_usable_lba; + efi_guid_t disk_guid; + rt_le64_t partition_entry_lba; + rt_le32_t num_partition_entries; + rt_le32_t sizeof_partition_entry; + rt_le32_t partition_entry_array_crc32; + + /* + * The rest of the logical block is reserved by UEFI and must be zero. + * EFI standard handles this by: + * + * uint8_t reserved2[BlockSize - 92]; + */ +}); +typedef struct _gpt_header gpt_header; + +rt_packed(struct _gpt_entry_attributes +{ + rt_uint64_t required_to_function:1; + rt_uint64_t reserved:47; + rt_uint64_t type_guid_specific:16; +}); +typedef struct _gpt_entry_attributes gpt_entry_attributes; + +rt_packed(struct _gpt_entry +{ + efi_guid_t partition_type_guid; + efi_guid_t unique_partition_guid; + rt_le64_t starting_lba; + rt_le64_t ending_lba; + gpt_entry_attributes attributes; + rt_le16_t partition_name[72/sizeof(rt_le16_t)]; +}); +typedef struct _gpt_entry gpt_entry; + +rt_packed(struct _gpt_mbr_record +{ + rt_uint8_t boot_indicator; /* unused by EFI, set to 0x80 for bootable */ + rt_uint8_t start_head; /* unused by EFI, pt start in CHS */ + rt_uint8_t start_sector; /* unused by EFI, pt start in CHS */ + rt_uint8_t start_track; + rt_uint8_t os_type; /* EFI and legacy non-EFI OS types */ + rt_uint8_t end_head; /* unused by EFI, pt end in CHS */ + rt_uint8_t end_sector; /* unused by EFI, pt end in CHS */ + rt_uint8_t end_track; /* unused by EFI, pt end in CHS */ + rt_le32_t starting_lba; /* used by EFI - start addr of the on disk pt */ + rt_le32_t size_in_lba; /* used by EFI - size of pt in LBA */ +}); +typedef struct _gpt_mbr_record gpt_mbr_record; + +rt_packed(struct _legacy_mbr +{ + rt_uint8_t boot_code[440]; + rt_le32_t unique_mbr_signature; + rt_le16_t unknown; + gpt_mbr_record partition_record[4]; + rt_le16_t signature; +}); +typedef struct _legacy_mbr legacy_mbr; + +#endif /* __PARTITIONS_EFI_H__ */ diff --git a/rt-thread/components/drivers/can/can.c b/rt-thread/components/drivers/can/dev_can.c similarity index 99% rename from rt-thread/components/drivers/can/can.c rename to rt-thread/components/drivers/can/dev_can.c index f10e05d..186f113 100644 --- a/rt-thread/components/drivers/can/can.c +++ b/rt-thread/components/drivers/can/dev_can.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -435,7 +435,7 @@ static rt_err_t rt_can_close(struct rt_device *dev) } can->ops->control(can, RT_DEVICE_CTRL_CLR_INT, (void *)RT_DEVICE_CAN_INT_ERR); - + can->ops->control(can, RT_CAN_CMD_START, RT_FALSE); CAN_UNLOCK(can); return RT_EOK; diff --git a/rt-thread/components/drivers/clk/Kconfig b/rt-thread/components/drivers/clk/Kconfig index 3c34d38..c13ccbf 100644 --- a/rt-thread/components/drivers/clk/Kconfig +++ b/rt-thread/components/drivers/clk/Kconfig @@ -3,3 +3,7 @@ menuconfig RT_USING_CLK depends on RT_USING_DM select RT_USING_ADT_REF default y + +if RT_USING_CLK + osource "$(SOC_DM_CLK_DIR)/Kconfig" +endif diff --git a/rt-thread/components/drivers/clk/clk.c b/rt-thread/components/drivers/clk/clk.c index 053c67d..2bb45f8 100644 --- a/rt-thread/components/drivers/clk/clk.c +++ b/rt-thread/components/drivers/clk/clk.c @@ -55,6 +55,10 @@ static struct rt_clk *clk_alloc(struct rt_clk_node *clk_np, const char *dev_id, clk->fw_node = fw_node; } + else + { + clk = rt_err_ptr(-RT_ENOMEM); + } return clk; } @@ -76,7 +80,7 @@ static struct rt_clk *clk_create(struct rt_clk_node *clk_np, const char *dev_id, { struct rt_clk *clk = clk_alloc(clk_np, dev_id, con_id, fw_node); - if (clk) + if (!rt_is_err(clk)) { clk_get(clk_np); @@ -135,15 +139,6 @@ rt_err_t rt_clk_register(struct rt_clk_node *clk_np, struct rt_clk_node *parent_ struct rt_clk *clk = RT_NULL; if (clk_np) - { - clk = clk_alloc(clk_np, RT_NULL, RT_NULL, RT_NULL); - } - else - { - err = -RT_EINVAL; - } - - if (!err && clk_np) { clk_np->clk = clk; @@ -152,6 +147,12 @@ rt_err_t rt_clk_register(struct rt_clk_node *clk_np, struct rt_clk_node *parent_ clk_np->ops = &unused_clk_ops; } + #if RT_NAME_MAX > 0 + rt_strncpy(clk_np->rt_parent.name, RT_CLK_NODE_OBJ_NAME, RT_NAME_MAX); + #else + clk_np->rt_parent.name = RT_CLK_NODE_OBJ_NAME; + #endif + rt_ref_init(&clk_np->ref); rt_list_init(&clk_np->list); rt_list_init(&clk_np->children_nodes); @@ -159,7 +160,16 @@ rt_err_t rt_clk_register(struct rt_clk_node *clk_np, struct rt_clk_node *parent_ if (parent_np) { - clk_set_parent(clk_np, parent_np); + clk_np->clk = clk_alloc(clk_np, RT_NULL, RT_NULL, RT_NULL); + + if (clk_np->clk) + { + clk_set_parent(clk_np, parent_np); + } + else + { + err = -RT_ENOMEM; + } } else { @@ -265,11 +275,16 @@ static rt_err_t clk_prepare(struct rt_clk *clk, struct rt_clk_node *clk_np) clk_prepare(clk_np->clk, clk_np->parent); } - if (clk_np->ops->prepare) + if (clk->prepare_count == 0 && clk_np->ops->prepare) { err = clk_np->ops->prepare(clk); } + if (!err) + { + ++clk->prepare_count; + } + return err; } @@ -287,10 +302,6 @@ rt_err_t rt_clk_prepare(struct rt_clk *clk) rt_hw_spin_unlock(&_clk_lock.lock); } - else - { - err = -RT_EINVAL; - } return err; } @@ -302,10 +313,14 @@ static void clk_unprepare(struct rt_clk *clk, struct rt_clk_node *clk_np) clk_unprepare(clk_np->clk, clk_np->parent); } - if (clk_np->ops->unprepare) + if (clk->prepare_count == 1 && clk_np->ops->unprepare) { clk_np->ops->unprepare(clk); } + if (clk->prepare_count) + { + --clk->prepare_count; + } } rt_err_t rt_clk_unprepare(struct rt_clk *clk) @@ -322,10 +337,6 @@ rt_err_t rt_clk_unprepare(struct rt_clk *clk) rt_hw_spin_unlock(&_clk_lock.lock); } - else - { - err = -RT_EINVAL; - } return err; } @@ -339,11 +350,16 @@ static rt_err_t clk_enable(struct rt_clk *clk, struct rt_clk_node *clk_np) clk_enable(clk_np->clk, clk_np->parent); } - if (clk_np->ops->enable) + if (clk->enable_count == 0 && clk_np->ops->enable) { err = clk_np->ops->enable(clk); } + if (!err) + { + ++clk->enable_count; + } + return err; } @@ -359,10 +375,6 @@ rt_err_t rt_clk_enable(struct rt_clk *clk) rt_hw_spin_unlock(&_clk_lock.lock); } - else - { - err = -RT_EINVAL; - } return err; } @@ -374,10 +386,14 @@ static void clk_disable(struct rt_clk *clk, struct rt_clk_node *clk_np) clk_disable(clk_np->clk, clk_np->parent); } - if (clk_np->ops->disable) + if (clk->enable_count == 1 && clk_np->ops->disable) { clk_np->ops->disable(clk); } + if (clk->enable_count) + { + --clk->enable_count; + } } void rt_clk_disable(struct rt_clk *clk) @@ -394,7 +410,7 @@ void rt_clk_disable(struct rt_clk *clk) rt_err_t rt_clk_prepare_enable(struct rt_clk *clk) { - rt_err_t err; + rt_err_t err = RT_EOK; RT_DEBUG_NOT_IN_INTERRUPT; @@ -412,10 +428,6 @@ rt_err_t rt_clk_prepare_enable(struct rt_clk *clk) } } } - else - { - err = -RT_EINVAL; - } return err; } @@ -453,10 +465,6 @@ rt_err_t rt_clk_array_prepare(struct rt_clk_array *clk_arr) } } } - else - { - err = -RT_EINVAL; - } return err; } @@ -478,10 +486,6 @@ rt_err_t rt_clk_array_unprepare(struct rt_clk_array *clk_arr) } } } - else - { - err = -RT_EINVAL; - } return err; } @@ -508,10 +512,6 @@ rt_err_t rt_clk_array_enable(struct rt_clk_array *clk_arr) } } } - else - { - err = -RT_EINVAL; - } return err; } @@ -529,29 +529,16 @@ void rt_clk_array_disable(struct rt_clk_array *clk_arr) rt_err_t rt_clk_array_prepare_enable(struct rt_clk_array *clk_arr) { - rt_err_t err = RT_EOK; + rt_err_t err; - if (clk_arr) + if ((err = rt_clk_array_prepare(clk_arr))) { - for (int i = 0; i < clk_arr->count; ++i) - { - if ((err = rt_clk_prepare_enable(clk_arr->clks[i]))) - { - LOG_E("CLK Array[%d] %s failed error = %s", i, - "prepare_enable", rt_strerror(err)); - - while (i --> 0) - { - rt_clk_disable_unprepare(clk_arr->clks[i]); - } - - break; - } - } + return err; } - else + + if ((err = rt_clk_array_enable(clk_arr))) { - err = -RT_EINVAL; + rt_clk_array_unprepare(clk_arr); } return err; @@ -559,13 +546,8 @@ rt_err_t rt_clk_array_prepare_enable(struct rt_clk_array *clk_arr) void rt_clk_array_disable_unprepare(struct rt_clk_array *clk_arr) { - if (clk_arr) - { - for (int i = 0; i < clk_arr->count; ++i) - { - rt_clk_disable_unprepare(clk_arr->clks[i]); - } - } + rt_clk_array_disable(clk_arr); + rt_clk_array_unprepare(clk_arr); } rt_err_t rt_clk_set_rate_range(struct rt_clk *clk, rt_ubase_t min, rt_ubase_t max) @@ -604,10 +586,6 @@ rt_err_t rt_clk_set_rate_range(struct rt_clk *clk, rt_ubase_t min, rt_ubase_t ma rt_hw_spin_unlock(&_clk_lock.lock); } - else - { - err = -RT_EINVAL; - } return err; } @@ -622,10 +600,6 @@ rt_err_t rt_clk_set_min_rate(struct rt_clk *clk, rt_ubase_t rate) err = rt_clk_set_rate_range(clk, rate, clk_np->max_rate); } - else - { - err = -RT_EINVAL; - } return err; } @@ -640,10 +614,6 @@ rt_err_t rt_clk_set_max_rate(struct rt_clk *clk, rt_ubase_t rate) err = rt_clk_set_rate_range(clk, clk_np->min_rate, rate); } - else - { - err = -RT_EINVAL; - } return err; } @@ -652,7 +622,9 @@ rt_err_t rt_clk_set_rate(struct rt_clk *clk, rt_ubase_t rate) { rt_err_t err = RT_EOK; - if (clk && clk->clk_np) + rate = rt_clk_round_rate(clk, rate); + + if (clk && clk->clk_np && rate > 0) { struct rt_clk_node *clk_np = clk->clk_np; @@ -690,17 +662,13 @@ rt_err_t rt_clk_set_rate(struct rt_clk *clk, rt_ubase_t rate) rt_hw_spin_unlock(&_clk_lock.lock); } - else - { - err = -RT_EINVAL; - } return err; } rt_ubase_t rt_clk_get_rate(struct rt_clk *clk) { - rt_ubase_t rate = -1UL; + rt_ubase_t rate = 0; if (clk) { @@ -729,10 +697,6 @@ rt_err_t rt_clk_set_phase(struct rt_clk *clk, int degrees) rt_hw_spin_unlock(&_clk_lock.lock); } - else - { - err = -RT_EINVAL; - } return err; } @@ -749,38 +713,49 @@ rt_base_t rt_clk_get_phase(struct rt_clk *clk) rt_hw_spin_unlock(&_clk_lock.lock); } - else - { - res = -RT_EINVAL; - } return res; } rt_base_t rt_clk_round_rate(struct rt_clk *clk, rt_ubase_t rate) { - rt_base_t res = RT_EOK; + rt_base_t res = -RT_EINVAL; - if (clk && clk->clk_np && clk->clk_np->ops->round_rate) + if (clk && clk->clk_np) { - rt_ubase_t best_parent_rate; struct rt_clk_node *clk_np = clk->clk_np; - rt_hw_spin_lock(&_clk_lock.lock); - - if (clk_np->min_rate && clk_np->max_rate) + if (clk_np->ops->round_rate) { - rate = rt_clamp(rate, clk_np->min_rate, clk_np->max_rate); + rt_ubase_t best_parent_rate; + + rt_hw_spin_lock(&_clk_lock.lock); + + if (clk_np->min_rate && clk_np->max_rate) + { + rate = rt_clamp(rate, clk_np->min_rate, clk_np->max_rate); + } + + res = clk_np->ops->round_rate(clk, rate, &best_parent_rate); + (void)best_parent_rate; + + rt_hw_spin_unlock(&_clk_lock.lock); + } + else + { + if (rate < clk_np->min_rate) + { + res = clk_np->min_rate; + } + else if (rate > clk_np->max_rate) + { + res = clk_np->max_rate; + } + else + { + res = rate; + } } - - res = clk->clk_np->ops->round_rate(clk, rate, &best_parent_rate); - (void)best_parent_rate; - - rt_hw_spin_unlock(&_clk_lock.lock); - } - else - { - res = -RT_EINVAL; } return res; @@ -798,10 +773,6 @@ rt_err_t rt_clk_set_parent(struct rt_clk *clk, struct rt_clk *clk_parent) rt_hw_spin_unlock(&_clk_lock.lock); } - else - { - err = -RT_EINVAL; - } return err; } @@ -887,7 +858,7 @@ void rt_clk_put(struct rt_clk *clk) } #ifdef RT_USING_OFW -static struct rt_clk *ofw_get_clk_no_lock(struct rt_ofw_node *np, int index, const char *name) +static struct rt_clk *ofw_get_clk_no_lock(struct rt_ofw_node *np, int index, const char *name, rt_bool_t locked) { struct rt_clk *clk = RT_NULL; struct rt_ofw_cell_args clk_args; @@ -895,10 +866,32 @@ static struct rt_clk *ofw_get_clk_no_lock(struct rt_ofw_node *np, int index, con if (!rt_ofw_parse_phandle_cells(np, "clocks", "#clock-cells", index, &clk_args)) { int count; + struct rt_object *obj; + struct rt_clk_node *clk_np = RT_NULL; struct rt_ofw_node *clk_ofw_np = clk_args.data; - struct rt_clk_node *clk_np = rt_ofw_data(clk_ofw_np); - count = rt_ofw_count_of_clk(clk_ofw_np); + if (!rt_ofw_data(clk_ofw_np)) + { + if (locked) + { + rt_hw_spin_unlock(&_clk_lock.lock); + } + + rt_platform_ofw_request(clk_ofw_np); + + if (locked) + { + rt_hw_spin_lock(&_clk_lock.lock); + } + } + + if (rt_ofw_data(clk_ofw_np) && (obj = rt_ofw_parse_object(clk_ofw_np, + RT_CLK_NODE_OBJ_NAME, "#clock-cells"))) + { + clk_np = rt_container_of(obj, struct rt_clk_node, rt_parent); + + count = rt_ofw_count_of_clk(clk_ofw_np); + } rt_ofw_node_put(clk_ofw_np); @@ -912,6 +905,10 @@ static struct rt_clk *ofw_get_clk_no_lock(struct rt_ofw_node *np, int index, con clk = clk_create(clk_np, np->full_name, name, &clk_args, np); } + else + { + clk = rt_err_ptr(-RT_ERROR); + } } return clk; @@ -923,7 +920,7 @@ static struct rt_clk *ofw_get_clk(struct rt_ofw_node *np, int index, const char rt_hw_spin_lock(&_clk_lock.lock); - clk = ofw_get_clk_no_lock(np, index, name); + clk = ofw_get_clk_no_lock(np, index, name, RT_TRUE); rt_hw_spin_unlock(&_clk_lock.lock); @@ -935,6 +932,11 @@ struct rt_clk_array *rt_ofw_get_clk_array(struct rt_ofw_node *np) int count; struct rt_clk_array *clk_arr = RT_NULL; + if (!np) + { + return rt_err_ptr(-RT_EINVAL); + } + if ((count = rt_ofw_count_phandle_cells(np, "clocks", "#clock-cells")) > 0) { clk_arr = rt_calloc(1, sizeof(*clk_arr) + sizeof(clk_arr->clks[0]) * count); @@ -942,6 +944,7 @@ struct rt_clk_array *rt_ofw_get_clk_array(struct rt_ofw_node *np) if (clk_arr) { int i; + rt_err_t err = RT_EOK; rt_bool_t has_name = rt_ofw_prop_read_bool(np, "clock-names"); clk_arr->count = count; @@ -957,10 +960,12 @@ struct rt_clk_array *rt_ofw_get_clk_array(struct rt_ofw_node *np) rt_ofw_prop_read_string_index(np, "clock-names", i, &name); } - clk_arr->clks[i] = ofw_get_clk_no_lock(np, i, name); + clk_arr->clks[i] = ofw_get_clk_no_lock(np, i, name, RT_FALSE); - if (!clk_arr->clks[i]) + if (rt_is_err(clk_arr->clks[i])) { + err = rt_ptr_err(clk_arr->clks[i]); + --i; break; } @@ -971,7 +976,7 @@ struct rt_clk_array *rt_ofw_get_clk_array(struct rt_ofw_node *np) if (i > 0 && i < count) { rt_clk_array_put(clk_arr); - clk_arr = RT_NULL; + clk_arr = rt_err_ptr(err); } } } diff --git a/rt-thread/components/drivers/core/bus.c b/rt-thread/components/drivers/core/bus.c index 13e154f..a1d6d7e 100644 --- a/rt-thread/components/drivers/core/bus.c +++ b/rt-thread/components/drivers/core/bus.c @@ -360,9 +360,9 @@ rt_err_t rt_bus_remove_device(rt_device_t dev) } else if (drv) { - if (drv->shutdown) + if (drv->remove) { - err = drv->shutdown(dev); + err = drv->remove(dev); } /* device and driver are in the same bus */ diff --git a/rt-thread/components/drivers/core/device.c b/rt-thread/components/drivers/core/device.c index c99cddf..751b662 100644 --- a/rt-thread/components/drivers/core/device.c +++ b/rt-thread/components/drivers/core/device.c @@ -13,6 +13,8 @@ * 2013-07-09 Grissiom add ref_count support * 2016-04-02 Bernard fix the open_flag initialization issue. * 2021-03-19 Meco Man remove rt_device_init_all() + * 2024-09-15 milo fix log format issue + * fix reopen with a different oflag issue */ #include @@ -29,9 +31,9 @@ #include /* for wqueue_init */ #endif /* RT_USING_POSIX_DEVIO */ -#ifdef RT_USING_DFS_V2 +#if defined (RT_USING_DFS_V2) && defined (RT_USING_DFS_DEVFS) #include -#endif /* RT_USING_DFS_V2 */ +#endif /* RT_USING_DFS_V2 RT_USING_DFS_DEVFS */ #ifdef RT_USING_DEVICE @@ -82,7 +84,7 @@ rt_err_t rt_device_register(rt_device_t dev, rt_wqueue_init(&(dev->wait_queue)); #endif /* RT_USING_POSIX_DEVIO */ -#ifdef RT_USING_DFS_V2 +#if defined (RT_USING_DFS_V2) && defined (RT_USING_DFS_DEVFS) dfs_devfs_device_add(dev); #endif /* RT_USING_DFS_V2 */ @@ -163,7 +165,7 @@ void rt_device_destroy(rt_device_t dev) { /* parameter check */ RT_ASSERT(dev != RT_NULL); - RT_ASSERT(rt_object_get_type(&dev->parent) == RT_Object_Class_Device); + RT_ASSERT(rt_object_get_type(&dev->parent) == RT_Object_Class_Null); RT_ASSERT(rt_object_is_systemobject(&dev->parent) == RT_FALSE); rt_object_detach(&(dev->parent)); @@ -195,8 +197,8 @@ rt_err_t rt_device_init(rt_device_t dev) result = device_init(dev); if (result != RT_EOK) { - LOG_E("To initialize device:%s failed. The error code is %d", - dev->parent.name, result); + LOG_E("To initialize device:%.*s failed. The error code is %d", + RT_NAME_MAX, dev->parent.name, result); } else { @@ -233,8 +235,8 @@ rt_err_t rt_device_open(rt_device_t dev, rt_uint16_t oflag) result = device_init(dev); if (result != RT_EOK) { - LOG_E("To initialize device:%s failed. The error code is %d", - dev->parent.name, result); + LOG_E("To initialize device:%.*s failed. The error code is %d", + RT_NAME_MAX, dev->parent.name, result); return result; } @@ -252,7 +254,7 @@ rt_err_t rt_device_open(rt_device_t dev, rt_uint16_t oflag) /* device is not opened or opened by other oflag, call device_open interface */ if (!(dev->open_flag & RT_DEVICE_OFLAG_OPEN) || - ((dev->open_flag & RT_DEVICE_OFLAG_MASK) != (oflag & RT_DEVICE_OFLAG_MASK))) + ((dev->open_flag & RT_DEVICE_OFLAG_MASK) != ((oflag & RT_DEVICE_OFLAG_MASK) | RT_DEVICE_OFLAG_OPEN))) { if (device_open != RT_NULL) { diff --git a/rt-thread/components/drivers/core/dm.c b/rt-thread/components/drivers/core/dm.c index 8c87cae..9d9f93f 100644 --- a/rt-thread/components/drivers/core/dm.c +++ b/rt-thread/components/drivers/core/dm.c @@ -53,6 +53,137 @@ void rt_dm_secondary_cpu_init(void) } #endif /* RT_USING_SMP */ +/** + * @brief This function will alloc an id in an IDA object + * + * @param ida is the IDA object + * + * @return the id or -RT_EEMPTY + */ +int rt_dm_ida_alloc(struct rt_dm_ida *ida) +{ + int id; + RT_ASSERT(ida != RT_NULL); + + rt_spin_lock(&ida->lock); + + id = rt_bitmap_next_clear_bit(ida->map, 0, RT_DM_IDA_NUM); + + if (id != RT_DM_IDA_NUM) + { + rt_bitmap_set_bit(ida->map, id); + } + + rt_spin_unlock(&ida->lock); + + if (id != RT_DM_IDA_NUM) + { + return id; + } + + return -RT_EEMPTY; +} + +/** + * @brief This function will take (force) an id in an IDA object + * + * @param ida is the IDA object + * + * @param id is the id that want to take + * + * @return the result of taking + */ +rt_bool_t rt_dm_ida_take(struct rt_dm_ida *ida, int id) +{ + RT_ASSERT(ida != RT_NULL); + RT_ASSERT(id >= 0); + + rt_spin_lock(&ida->lock); + + if (!rt_bitmap_test_bit(ida->map, id)) + { + rt_bitmap_set_bit(ida->map, id); + } + else + { + id = RT_DM_IDA_NUM; + } + + rt_spin_unlock(&ida->lock); + + return id != RT_DM_IDA_NUM; +} + +/** + * @brief This function will release an id in an IDA object + * + * @param ida is the IDA object + * + * @param id is the id of IDA object + */ +void rt_dm_ida_free(struct rt_dm_ida *ida, int id) +{ + RT_ASSERT(ida != RT_NULL); + RT_ASSERT(id >= 0); + + rt_spin_lock(&ida->lock); + + rt_bitmap_clear_bit(ida->map, id); + + rt_spin_unlock(&ida->lock); +} + +/** + * @brief This function will return the specified master id and device id of device. + * + * @param master_id is the master id (0, 255] of device + * + * @param device_id is the device id [-1, 255] of device, when device_id is -1, + * the function will end when find the first device. + * + * @return the device object or RT_NULL + */ +rt_device_t rt_dm_device_find(int master_id, int device_id) +{ + struct rt_device *dev, *ret_dev = RT_NULL; + struct rt_object_information *information = RT_NULL; + + if (master_id <= 0 || device_id > 255) + { + return RT_NULL; + } + + information = rt_object_get_information(RT_Object_Class_Device); + + /* parameter check */ + if (!information) + { + return RT_NULL; + } + + /* which is invoke in interrupt status */ + RT_DEBUG_NOT_IN_INTERRUPT; + + /* enter critical */ + rt_enter_critical(); + + /* try to find object */ + rt_list_for_each_entry(dev, &information->object_list, parent.list) + { + if (master_id == dev->master_id && + (device_id == -1 || device_id == dev->device_id)) + { + ret_dev = dev; + break; + } + } + + /* leave critical */ + rt_exit_critical(); + + return ret_dev; +} + struct prefix_track { rt_list_t list; diff --git a/rt-thread/components/drivers/core/platform.c b/rt-thread/components/drivers/core/platform.c index d8c6679..c3a1416 100644 --- a/rt-thread/components/drivers/core/platform.c +++ b/rt-thread/components/drivers/core/platform.c @@ -78,21 +78,21 @@ static rt_bool_t platform_match(rt_driver_t drv, rt_device_t dev) { struct rt_platform_driver *pdrv = rt_container_of(drv, struct rt_platform_driver, parent); struct rt_platform_device *pdev = rt_container_of(dev, struct rt_platform_device, parent); - -#ifdef RT_USING_OFW struct rt_ofw_node *np = dev->ofw_node; /* 1、match with ofw node */ if (np) { + #ifdef RT_USING_OFW pdev->id = rt_ofw_node_match(np, pdrv->ids); - + #else + pdev->id = RT_NULL; + #endif if (pdev->id) { return RT_TRUE; } } -#endif /* 2、match with name */ if (pdev->name && pdrv->name) @@ -123,7 +123,13 @@ static rt_err_t platform_probe(rt_device_t dev) if (err && err != -RT_EEMPTY) { - LOG_E("Attach power domain error = %s in device %s", pdev->name, rt_strerror(err)); + LOG_E("Attach power domain error = %s in device %s", rt_strerror(err), + #ifdef RT_USING_OFW + (pdev->name && pdev->name[0]) ? pdev->name : rt_ofw_node_full_name(np) + #else + pdev->name + #endif + ); return err; } diff --git a/rt-thread/components/drivers/core/platform_ofw.c b/rt-thread/components/drivers/core/platform_ofw.c index f305fde..1b1aa27 100644 --- a/rt-thread/components/drivers/core/platform_ofw.c +++ b/rt-thread/components/drivers/core/platform_ofw.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "../ofw/ofw_internal.h" @@ -161,6 +162,7 @@ static rt_err_t platform_ofw_device_probe_once(struct rt_ofw_node *parent_np) } pdev->dev_id = ofw_alias_node_id(np); + np->dev = &pdev->parent; LOG_D("%s register to bus", np->full_name); rt_platform_device_register(pdev); @@ -199,6 +201,53 @@ rt_err_t rt_platform_ofw_device_probe_child(struct rt_ofw_node *np) return err; } +rt_err_t rt_platform_ofw_request(struct rt_ofw_node *np) +{ + rt_err_t err; + + if (np) + { + struct rt_device *dev = np->dev; + + if (dev) + { + /* Was create */ + if (dev->drv) + { + /* Was probe OK */ + err = RT_EOK; + } + else + { + err = rt_bus_reload_driver_device(dev->bus, dev); + } + } + else + { + struct rt_platform_device *pdev = alloc_ofw_platform_device(np); + + if (pdev) + { + pdev->dev_id = ofw_alias_node_id(np); + np->dev = &pdev->parent; + LOG_D("%s register to bus", np->full_name); + + err = rt_platform_device_register(pdev); + } + else + { + err = -RT_ENOMEM; + } + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + static int platform_ofw_device_probe(void) { rt_err_t err = RT_EOK; @@ -206,6 +255,8 @@ static int platform_ofw_device_probe(void) if (ofw_node_root) { + rt_ofw_node_get(ofw_node_root); + err = platform_ofw_device_probe_once(ofw_node_root); rt_ofw_node_put(ofw_node_root); @@ -216,11 +267,19 @@ static int platform_ofw_device_probe(void) rt_ofw_node_put(node); } + if ((node = rt_ofw_find_node_by_path("/clocks"))) + { + platform_ofw_device_probe_once(node); + rt_ofw_node_put(node); + } + + rt_ofw_node_get(ofw_node_chosen); if ((node = rt_ofw_get_child_by_compatible(ofw_node_chosen, "simple-framebuffer"))) { platform_ofw_device_probe_once(node); rt_ofw_node_put(node); } + rt_ofw_node_get(ofw_node_chosen); } else { @@ -244,7 +303,7 @@ rt_err_t rt_platform_ofw_free(struct rt_platform_device *pdev) rt_ofw_node_clear_flag(np, RT_OFW_F_PLATFORM); rt_ofw_node_put(np); - pdev->parent.ofw_node = RT_NULL; + rt_free(pdev); } } else diff --git a/rt-thread/components/drivers/dma/Kconfig b/rt-thread/components/drivers/dma/Kconfig new file mode 100644 index 0000000..7bf9d59 --- /dev/null +++ b/rt-thread/components/drivers/dma/Kconfig @@ -0,0 +1,10 @@ +menuconfig RT_USING_DMA + bool "Using Direct Memory Access (DMA)" + depends on RT_USING_DM + select RT_USING_ADT + select RT_USING_ADT_BITMAP + default n + +if RT_USING_DMA + osource "$(SOC_DM_DMA_DIR)/Kconfig" +endif diff --git a/rt-thread/components/drivers/dma/SConscript b/rt-thread/components/drivers/dma/SConscript new file mode 100644 index 0000000..ea3500c --- /dev/null +++ b/rt-thread/components/drivers/dma/SConscript @@ -0,0 +1,15 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_DMA']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] + +src = ['dma.c', 'dma_pool.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/dma/dma.c b/rt-thread/components/drivers/dma/dma.c new file mode 100644 index 0000000..da2d80a --- /dev/null +++ b/rt-thread/components/drivers/dma/dma.c @@ -0,0 +1,589 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "rtdm.dma" +#define DBG_LVL DBG_INFO +#include + +static rt_list_t dmac_nodes = RT_LIST_OBJECT_INIT(dmac_nodes); +static struct rt_spinlock dmac_nodes_lock = {}; + +rt_err_t rt_dma_controller_register(struct rt_dma_controller *ctrl) +{ + const char *dev_name; + char dma_name[RT_NAME_MAX]; + + if (!ctrl || !ctrl->dev || !ctrl->ops) + { + return -RT_EINVAL; + } + + dev_name = rt_dm_dev_get_name(ctrl->dev); + + if (rt_bitmap_next_set_bit(ctrl->dir_cap, 0, RT_DMA_DIR_MAX) == RT_DMA_DIR_MAX) + { + LOG_E("%s: Not direction capability", dev_name); + + return -RT_EINVAL; + } + + rt_snprintf(dma_name, sizeof(dma_name), "%s-dmac", dev_name); + + rt_list_init(&ctrl->list); + + rt_spin_lock(&dmac_nodes_lock); + rt_list_insert_before(&dmac_nodes, &ctrl->list); + rt_spin_unlock(&dmac_nodes_lock); + + rt_list_init(&ctrl->channels_nodes); + rt_mutex_init(&ctrl->mutex, dma_name, RT_IPC_FLAG_PRIO); + + if (ctrl->dev->ofw_node) + { + rt_dm_dev_bind_fwdata(ctrl->dev, RT_NULL, ctrl); + } + + return RT_EOK; +} + +rt_err_t rt_dma_controller_unregister(struct rt_dma_controller *ctrl) +{ + if (!ctrl) + { + return -RT_EINVAL; + } + + rt_mutex_take(&ctrl->mutex, RT_WAITING_FOREVER); + + if (!rt_list_isempty(&ctrl->channels_nodes)) + { + rt_mutex_release(&ctrl->mutex); + return -RT_EBUSY; + } + + if (ctrl->dev->ofw_node) + { + rt_dm_dev_unbind_fwdata(ctrl->dev, RT_NULL); + } + + rt_mutex_release(&ctrl->mutex); + rt_mutex_detach(&ctrl->mutex); + + rt_spin_lock(&dmac_nodes_lock); + rt_list_remove(&ctrl->list); + rt_spin_unlock(&dmac_nodes_lock); + + return RT_EOK; +} + +rt_err_t rt_dma_chan_start(struct rt_dma_chan *chan) +{ + rt_err_t err; + struct rt_dma_controller *ctrl; + + if (!chan) + { + return -RT_EINVAL; + } + + if (chan->prep_err) + { + LOG_D("%s: Not config done", rt_dm_dev_get_name(chan->slave)); + + return chan->prep_err; + } + + ctrl = chan->ctrl; + + rt_mutex_take(&ctrl->mutex, RT_WAITING_FOREVER); + + err = ctrl->ops->start(chan); + + rt_mutex_release(&ctrl->mutex); + + return err; +} + +rt_err_t rt_dma_chan_stop(struct rt_dma_chan *chan) +{ + rt_err_t err; + struct rt_dma_controller *ctrl; + + if (!chan) + { + return -RT_EINVAL; + } + + if (chan->prep_err) + { + LOG_D("%s: Not prepare done", rt_dm_dev_get_name(chan->slave)); + + return chan->prep_err; + } + + ctrl = chan->ctrl; + + rt_mutex_take(&ctrl->mutex, RT_WAITING_FOREVER); + + err = ctrl->ops->stop(chan); + + rt_mutex_release(&ctrl->mutex); + + return err; +} + +rt_err_t rt_dma_chan_config(struct rt_dma_chan *chan, + struct rt_dma_slave_config *conf) +{ + rt_err_t err; + struct rt_dma_controller *ctrl; + enum rt_dma_transfer_direction dir; + + if (!chan || !conf) + { + err = -RT_EINVAL; + goto _end; + } + + dir = conf->direction; + + if (dir >= RT_DMA_DIR_MAX) + { + err = -RT_EINVAL; + goto _end; + } + + if (conf->src_addr_width >= RT_DMA_SLAVE_BUSWIDTH_BYTES_MAX || + conf->dst_addr_width >= RT_DMA_SLAVE_BUSWIDTH_BYTES_MAX) + { + err = -RT_EINVAL; + goto _end; + } + + ctrl = chan->ctrl; + + if (!rt_bitmap_test_bit(ctrl->dir_cap, dir)) + { + err = -RT_ENOSYS; + goto _end; + } + + if (!chan->name && dir != RT_DMA_MEM_TO_MEM) + { + LOG_E("%s: illegal config for uname channels", + rt_dm_dev_get_name(ctrl->dev)); + + err = -RT_EINVAL; + goto _end; + } + + rt_mutex_take(&ctrl->mutex, RT_WAITING_FOREVER); + + err = ctrl->ops->config(chan, conf); + + rt_mutex_release(&ctrl->mutex); + + if (!err) + { + rt_memcpy(&chan->conf, conf, sizeof(*conf)); + } + +_end: + chan->conf_err = err; + + return err; +} + +rt_err_t rt_dma_chan_done(struct rt_dma_chan *chan, rt_size_t size) +{ + if (!chan) + { + return -RT_EINVAL; + } + + if (chan->callback) + { + chan->callback(chan, size); + } + + return RT_EOK; +} + +static rt_bool_t range_is_illegal(const char *name, const char *desc, + rt_ubase_t addr0, rt_ubase_t addr1) +{ + rt_bool_t illegal = addr0 < addr1; + + if (illegal) + { + LOG_E("%s: %s %p is out of config %p", name, desc, addr0, addr1); + } + + return illegal; +} + +rt_err_t rt_dma_prep_memcpy(struct rt_dma_chan *chan, + struct rt_dma_slave_transfer *transfer) +{ + rt_err_t err; + rt_size_t len; + rt_ubase_t dma_addr_src, dma_addr_dst; + struct rt_dma_controller *ctrl; + struct rt_dma_slave_config *conf; + + if (!chan || !transfer) + { + return -RT_EINVAL; + } + + ctrl = chan->ctrl; + conf = &chan->conf; + + if (chan->conf_err) + { + LOG_D("%s: Not config done", rt_dm_dev_get_name(chan->slave)); + + return chan->conf_err; + } + + RT_ASSERT(chan->conf.direction == RT_DMA_MEM_TO_MEM); + dma_addr_src = transfer->src_addr; + dma_addr_dst = transfer->dst_addr; + len = transfer->buffer_len; + + if (range_is_illegal(rt_dm_dev_get_name(ctrl->dev), "source", + dma_addr_src, conf->src_addr)) + { + return -RT_EINVAL; + } + + if (range_is_illegal(rt_dm_dev_get_name(ctrl->dev), "dest", + dma_addr_dst, conf->dst_addr)) + { + return -RT_EINVAL; + } + + if (ctrl->ops->prep_memcpy) + { + rt_mutex_take(&ctrl->mutex, RT_WAITING_FOREVER); + + err = ctrl->ops->prep_memcpy(chan, dma_addr_dst, dma_addr_src, len); + + rt_mutex_release(&ctrl->mutex); + } + else + { + err = -RT_ENOSYS; + } + + if (!err) + { + rt_memcpy(&chan->transfer, transfer, sizeof(*transfer)); + } + + chan->prep_err = err; + + return err; +} + +rt_err_t rt_dma_prep_cyclic(struct rt_dma_chan *chan, + struct rt_dma_slave_transfer *transfer) +{ + rt_err_t err; + rt_ubase_t dma_buf_addr; + struct rt_dma_controller *ctrl; + struct rt_dma_slave_config *conf; + enum rt_dma_transfer_direction dir; + + if (!chan || !transfer) + { + return -RT_EINVAL; + } + + ctrl = chan->ctrl; + conf = &chan->conf; + + if (chan->conf_err) + { + LOG_D("%s: Not config done", rt_dm_dev_get_name(chan->slave)); + + return chan->conf_err; + } + + dir = chan->conf.direction; + + if (dir == RT_DMA_MEM_TO_DEV || dir == RT_DMA_MEM_TO_MEM) + { + dma_buf_addr = transfer->src_addr; + + if (range_is_illegal(rt_dm_dev_get_name(ctrl->dev), "source", + dma_buf_addr, conf->src_addr)) + { + return -RT_EINVAL; + } + } + else if (dir == RT_DMA_DEV_TO_MEM) + { + dma_buf_addr = transfer->dst_addr; + + if (range_is_illegal(rt_dm_dev_get_name(ctrl->dev), "dest", + dma_buf_addr, conf->dst_addr)) + { + return -RT_EINVAL; + } + } + else + { + dma_buf_addr = ~0UL; + } + + if (ctrl->ops->prep_cyclic) + { + rt_mutex_take(&ctrl->mutex, RT_WAITING_FOREVER); + + err = ctrl->ops->prep_cyclic(chan, dma_buf_addr, + transfer->buffer_len, transfer->period_len, dir); + + rt_mutex_release(&ctrl->mutex); + } + else + { + err = -RT_ENOSYS; + } + + if (!err) + { + rt_memcpy(&chan->transfer, transfer, sizeof(*transfer)); + } + + chan->prep_err = err; + + return err; +} + +rt_err_t rt_dma_prep_single(struct rt_dma_chan *chan, + struct rt_dma_slave_transfer *transfer) +{ + rt_err_t err; + rt_ubase_t dma_buf_addr; + struct rt_dma_controller *ctrl; + struct rt_dma_slave_config *conf; + enum rt_dma_transfer_direction dir; + + if (!chan || !transfer) + { + return -RT_EINVAL; + } + + ctrl = chan->ctrl; + conf = &chan->conf; + + if (chan->conf_err) + { + LOG_D("%s: Not config done", rt_dm_dev_get_name(chan->slave)); + + return chan->conf_err; + } + + dir = chan->conf.direction; + + if (dir == RT_DMA_MEM_TO_DEV || dir == RT_DMA_MEM_TO_MEM) + { + dma_buf_addr = transfer->src_addr; + + if (range_is_illegal(rt_dm_dev_get_name(ctrl->dev), "source", + dma_buf_addr, conf->src_addr)) + { + return -RT_EINVAL; + } + } + else if (dir == RT_DMA_DEV_TO_MEM) + { + dma_buf_addr = transfer->dst_addr; + + if (range_is_illegal(rt_dm_dev_get_name(ctrl->dev), "dest", + dma_buf_addr, conf->dst_addr)) + { + return -RT_EINVAL; + } + } + else + { + dma_buf_addr = ~0UL; + } + + if (ctrl->ops->prep_single) + { + rt_mutex_take(&ctrl->mutex, RT_WAITING_FOREVER); + + err = ctrl->ops->prep_single(chan, dma_buf_addr, + transfer->buffer_len, dir); + + rt_mutex_release(&ctrl->mutex); + } + else + { + err = -RT_ENOSYS; + } + + if (!err) + { + rt_memcpy(&chan->transfer, transfer, sizeof(*transfer)); + } + + chan->prep_err = err; + + return err; +} + +static struct rt_dma_controller *ofw_find_dma_controller(struct rt_device *dev, + const char *name, struct rt_ofw_cell_args *args) +{ + struct rt_dma_controller *ctrl = RT_NULL; +#ifdef RT_USING_OFW + int index; + struct rt_ofw_node *np = dev->ofw_node, *ctrl_np; + + if (!np) + { + return RT_NULL; + } + + index = rt_ofw_prop_index_of_string(np, "dma-names", name); + + if (index < 0) + { + return RT_NULL; + } + + if (!rt_ofw_parse_phandle_cells(np, "dmas", "#dma-cells", index, args)) + { + ctrl_np = args->data; + + if (!rt_ofw_data(ctrl_np)) + { + rt_platform_ofw_request(ctrl_np); + } + + ctrl = rt_ofw_data(ctrl_np); + rt_ofw_node_put(ctrl_np); + } +#endif /* RT_USING_OFW */ + return ctrl; +} + +struct rt_dma_chan *rt_dma_chan_request(struct rt_device *dev, const char *name) +{ + void *fw_data = RT_NULL; + struct rt_dma_chan *chan; + struct rt_ofw_cell_args dma_args; + struct rt_dma_controller *ctrl = RT_NULL; + + if (!dev) + { + return rt_err_ptr(-RT_EINVAL); + } + + if (name) + { + fw_data = &dma_args; + ctrl = ofw_find_dma_controller(dev, name, &dma_args); + } + else + { + struct rt_dma_controller *ctrl_tmp; + + rt_spin_lock(&dmac_nodes_lock); + rt_list_for_each_entry(ctrl_tmp, &dmac_nodes, list) + { + /* Only memory to memory for uname request */ + if (rt_bitmap_test_bit(ctrl_tmp->dir_cap, RT_DMA_MEM_TO_MEM)) + { + ctrl = ctrl_tmp; + break; + } + } + rt_spin_unlock(&dmac_nodes_lock); + } + + if (rt_is_err_or_null(ctrl)) + { + return ctrl ? ctrl : rt_err_ptr(-RT_ENOSYS); + } + + if (ctrl->ops->request_chan) + { + chan = ctrl->ops->request_chan(ctrl, dev, fw_data); + } + else + { + chan = rt_calloc(1, sizeof(*chan)); + + if (!chan) + { + chan = rt_err_ptr(-RT_ENOMEM); + } + } + + if (rt_is_err(chan)) + { + return chan; + } + + if (!chan) + { + LOG_E("%s: unset request channels error", rt_dm_dev_get_name(ctrl->dev)); + + return rt_err_ptr(-RT_ERROR); + } + + chan->name = name; + chan->ctrl = ctrl; + chan->slave = dev; + + rt_list_init(&chan->list); + chan->conf_err = -RT_ERROR; + chan->prep_err = -RT_ERROR; + + rt_mutex_take(&ctrl->mutex, RT_WAITING_FOREVER); + rt_list_insert_before(&ctrl->channels_nodes, &chan->list); + rt_mutex_release(&ctrl->mutex); + + return chan; +} + +rt_err_t rt_dma_chan_release(struct rt_dma_chan *chan) +{ + rt_err_t err = RT_EOK; + + if (!chan) + { + return -RT_EINVAL; + } + + rt_mutex_take(&chan->ctrl->mutex, RT_WAITING_FOREVER); + rt_list_remove(&chan->list); + rt_mutex_release(&chan->ctrl->mutex); + + if (chan->ctrl->ops->release_chan) + { + err = chan->ctrl->ops->release_chan(chan); + } + else + { + rt_free(chan); + } + + return err; +} diff --git a/rt-thread/components/drivers/dma/dma_pool.c b/rt-thread/components/drivers/dma/dma_pool.c new file mode 100644 index 0000000..8bd5291 --- /dev/null +++ b/rt-thread/components/drivers/dma/dma_pool.c @@ -0,0 +1,691 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "dma.pool" +#define DBG_LVL DBG_INFO +#include + +#include +#include + +static struct rt_spinlock dma_pools_lock = {}; +static rt_list_t dma_pool_nodes = RT_LIST_OBJECT_INIT(dma_pool_nodes); + +static struct rt_dma_pool *dma_pool_install(rt_region_t *region); + +static void *dma_alloc(struct rt_device *dev, rt_size_t size, + rt_ubase_t *dma_handle, rt_ubase_t flags); +static void dma_free(struct rt_device *dev, rt_size_t size, + void *cpu_addr, rt_ubase_t dma_handle, rt_ubase_t flags); + +rt_inline void region_pool_lock(void) +{ + rt_hw_spin_lock(&dma_pools_lock.lock); +} + +rt_inline void region_pool_unlock(void) +{ + rt_hw_spin_unlock(&dma_pools_lock.lock); +} + +static rt_err_t dma_map_coherent_sync_out_data(struct rt_device *dev, + void *data, rt_size_t size, rt_ubase_t *dma_handle, rt_ubase_t flags) +{ + if (dma_handle) + { + *dma_handle = (rt_ubase_t)rt_kmem_v2p(data); + } + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, data, size); + + return RT_EOK; +} + +static rt_err_t dma_map_coherent_sync_in_data(struct rt_device *dev, + void *out_data, rt_size_t size, rt_ubase_t dma_handle, rt_ubase_t flags) +{ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, out_data, size); + + return RT_EOK; +} + +static const struct rt_dma_map_ops dma_map_coherent_ops = +{ + .sync_out_data = dma_map_coherent_sync_out_data, + .sync_in_data = dma_map_coherent_sync_in_data, +}; + +static rt_err_t dma_map_nocoherent_sync_out_data(struct rt_device *dev, + void *data, rt_size_t size, rt_ubase_t *dma_handle, rt_ubase_t flags) +{ + if (dma_handle) + { + *dma_handle = (rt_ubase_t)rt_kmem_v2p(data); + } + + return RT_EOK; +} + +static rt_err_t dma_map_nocoherent_sync_in_data(struct rt_device *dev, + void *out_data, rt_size_t size, rt_ubase_t dma_handle, rt_ubase_t flags) +{ + return RT_EOK; +} + +static const struct rt_dma_map_ops dma_map_nocoherent_ops = +{ + .sync_out_data = dma_map_nocoherent_sync_out_data, + .sync_in_data = dma_map_nocoherent_sync_in_data, +}; + +#ifdef RT_USING_OFW +rt_inline rt_ubase_t ofw_addr_cpu2dma(struct rt_device *dev, rt_ubase_t addr) +{ + return (rt_ubase_t)rt_ofw_translate_cpu2dma(dev->ofw_node, addr); +} + +rt_inline rt_ubase_t ofw_addr_dma2cpu(struct rt_device *dev, rt_ubase_t addr) +{ + return (rt_ubase_t)rt_ofw_translate_dma2cpu(dev->ofw_node, addr); +} + +static void *ofw_dma_map_alloc(struct rt_device *dev, rt_size_t size, + rt_ubase_t *dma_handle, rt_ubase_t flags) +{ + void *cpu_addr = dma_alloc(dev, size, dma_handle, flags); + + if (cpu_addr && dma_handle) + { + *dma_handle = ofw_addr_cpu2dma(dev, *dma_handle); + } + + return cpu_addr; +} + +static void ofw_dma_map_free(struct rt_device *dev, rt_size_t size, + void *cpu_addr, rt_ubase_t dma_handle, rt_ubase_t flags) +{ + dma_handle = ofw_addr_dma2cpu(dev, dma_handle); + + dma_free(dev, size, cpu_addr, dma_handle, flags); +} + +static rt_err_t ofw_dma_map_sync_out_data(struct rt_device *dev, + void *data, rt_size_t size, + rt_ubase_t *dma_handle, rt_ubase_t flags) +{ + rt_err_t err; + + if (flags & RT_DMA_F_NOCACHE) + { + err = dma_map_nocoherent_sync_out_data(dev, data, size, dma_handle, flags); + } + else + { + err = dma_map_coherent_sync_out_data(dev, data, size, dma_handle, flags); + } + + if (!err && dma_handle) + { + *dma_handle = ofw_addr_cpu2dma(dev, *dma_handle); + } + + return err; +} + +static rt_err_t ofw_dma_map_sync_in_data(struct rt_device *dev, + void *out_data, rt_size_t size, + rt_ubase_t dma_handle, rt_ubase_t flags) +{ + dma_handle = ofw_addr_dma2cpu(dev, dma_handle); + + if (flags & RT_DMA_F_NOCACHE) + { + return dma_map_nocoherent_sync_in_data(dev, out_data, size, dma_handle, flags); + } + + return dma_map_coherent_sync_in_data(dev, out_data, size, dma_handle, flags); +} + +static const struct rt_dma_map_ops ofw_dma_map_ops = +{ + .alloc = ofw_dma_map_alloc, + .free = ofw_dma_map_free, + .sync_out_data = ofw_dma_map_sync_out_data, + .sync_in_data = ofw_dma_map_sync_in_data, +}; + +static const struct rt_dma_map_ops *ofw_device_dma_ops(struct rt_device *dev) +{ + rt_err_t err; + int region_nr = 0; + const fdt32_t *cell; + rt_phandle phandle; + rt_region_t region; + struct rt_ofw_prop *prop; + struct rt_dma_pool *dma_pool; + const struct rt_dma_map_ops *ops = RT_NULL; + struct rt_ofw_node *mem_np, *np = dev->ofw_node; + + rt_ofw_foreach_prop_u32(np, "memory-region", prop, cell, phandle) + { + rt_uint64_t addr, size; + + if (!(mem_np = rt_ofw_find_node_by_phandle(phandle))) + { + if (region_nr == 0) + { + return RT_NULL; + } + + break; + } + + if ((err = rt_ofw_get_address(mem_np, 0, &addr, &size))) + { + LOG_E("%s: Read '%s' error = %s", rt_ofw_node_full_name(mem_np), + "memory-region", rt_strerror(err)); + + rt_ofw_node_put(mem_np); + continue; + } + + region.start = addr; + region.end = addr + size; + region.name = rt_dm_dev_get_name(dev); + + rt_ofw_node_put(mem_np); + + if (!(dma_pool = dma_pool_install(®ion))) + { + return RT_NULL; + } + + if (rt_ofw_prop_read_bool(mem_np, "no-map")) + { + dma_pool->flags |= RT_DMA_F_NOMAP; + } + + if (!rt_dma_device_is_coherent(dev)) + { + dma_pool->flags |= RT_DMA_F_NOCACHE; + } + + dma_pool->dev = dev; + ++region_nr; + } + + if (region_nr) + { + ops = &ofw_dma_map_ops; + } + + return ops; +} +#endif /* RT_USING_OFW */ + +static const struct rt_dma_map_ops *device_dma_ops(struct rt_device *dev) +{ + const struct rt_dma_map_ops *ops = dev->dma_ops; + + if (ops) + { + return ops; + } + +#ifdef RT_USING_OFW + if (dev->ofw_node && (ops = ofw_device_dma_ops(dev))) + { + return ops; + } +#endif + + if (rt_dma_device_is_coherent(dev)) + { + ops = &dma_map_coherent_ops; + } + else + { + ops = &dma_map_nocoherent_ops; + } + + dev->dma_ops = ops; + + return ops; +} + +static rt_ubase_t dma_pool_alloc(struct rt_dma_pool *pool, rt_size_t size) +{ + rt_size_t bit, next_bit, end_bit, max_bits; + + size = RT_DIV_ROUND_UP(size, ARCH_PAGE_SIZE); + max_bits = pool->bits - size; + + rt_bitmap_for_each_clear_bit(pool->map, bit, max_bits) + { + end_bit = bit + size; + + for (next_bit = bit + 1; next_bit < end_bit; ++next_bit) + { + if (rt_bitmap_test_bit(pool->map, next_bit)) + { + bit = next_bit; + goto _next; + } + } + + if (next_bit == end_bit) + { + while (next_bit --> bit) + { + rt_bitmap_set_bit(pool->map, next_bit); + } + + return pool->start + bit * ARCH_PAGE_SIZE; + } + _next: + } + + return RT_NULL; +} + +static void dma_pool_free(struct rt_dma_pool *pool, rt_ubase_t offset, rt_size_t size) +{ + rt_size_t bit = (offset - pool->start) / ARCH_PAGE_SIZE, end_bit; + + size = RT_DIV_ROUND_UP(size, ARCH_PAGE_SIZE); + end_bit = bit + size; + + for (; bit < end_bit; ++bit) + { + rt_bitmap_clear_bit(pool->map, bit); + } +} + +static void *dma_alloc(struct rt_device *dev, rt_size_t size, + rt_ubase_t *dma_handle, rt_ubase_t flags) +{ + void *dma_buffer = RT_NULL; + struct rt_dma_pool *pool; + + region_pool_lock(); + + rt_list_for_each_entry(pool, &dma_pool_nodes, list) + { + if (pool->flags & RT_DMA_F_DEVICE) + { + if (!(flags & RT_DMA_F_DEVICE) || pool->dev != dev) + { + continue; + } + } + else if ((flags & RT_DMA_F_DEVICE)) + { + continue; + } + + if ((flags & RT_DMA_F_NOMAP) && !((pool->flags & RT_DMA_F_NOMAP))) + { + continue; + } + + if ((flags & RT_DMA_F_32BITS) && !((pool->flags & RT_DMA_F_32BITS))) + { + continue; + } + + if ((flags & RT_DMA_F_LINEAR) && !((pool->flags & RT_DMA_F_LINEAR))) + { + continue; + } + + *dma_handle = dma_pool_alloc(pool, size); + + if (*dma_handle && !(flags & RT_DMA_F_NOMAP)) + { + if (flags & RT_DMA_F_NOCACHE) + { + dma_buffer = rt_ioremap_nocache((void *)*dma_handle, size); + } + else + { + dma_buffer = rt_ioremap_cached((void *)*dma_handle, size); + } + + if (!dma_buffer) + { + dma_pool_free(pool, *dma_handle, size); + + continue; + } + + break; + } + else if (*dma_handle) + { + dma_buffer = (void *)*dma_handle; + + break; + } + } + + region_pool_unlock(); + + return dma_buffer; +} + +static void dma_free(struct rt_device *dev, rt_size_t size, + void *cpu_addr, rt_ubase_t dma_handle, rt_ubase_t flags) +{ + struct rt_dma_pool *pool; + + region_pool_lock(); + + rt_list_for_each_entry(pool, &dma_pool_nodes, list) + { + if (dma_handle >= pool->region.start && + dma_handle <= pool->region.end) + { + rt_iounmap(cpu_addr); + + dma_pool_free(pool, dma_handle, size); + + break; + } + } + + region_pool_unlock(); +} + +void *rt_dma_alloc(struct rt_device *dev, rt_size_t size, + rt_ubase_t *dma_handle, rt_ubase_t flags) +{ + void *dma_buffer = RT_NULL; + rt_ubase_t dma_handle_s = 0; + const struct rt_dma_map_ops *ops; + + if (!dev || !size) + { + return RT_NULL; + } + + ops = device_dma_ops(dev); + + if (ops->alloc) + { + dma_buffer = ops->alloc(dev, size, &dma_handle_s, flags); + } + else + { + dma_buffer = dma_alloc(dev, size, &dma_handle_s, flags); + } + + if (!dma_buffer) + { + return dma_buffer; + } + + if (dma_handle) + { + *dma_handle = dma_handle_s; + } + + return dma_buffer; +} + +void rt_dma_free(struct rt_device *dev, rt_size_t size, + void *cpu_addr, rt_ubase_t dma_handle, rt_ubase_t flags) +{ + const struct rt_dma_map_ops *ops; + + if (!dev || !size || !cpu_addr) + { + return; + } + + ops = device_dma_ops(dev); + + if (ops->free) + { + ops->free(dev, size, cpu_addr, dma_handle, flags); + } + else + { + dma_free(dev, size, cpu_addr, dma_handle, flags); + } +} + +rt_err_t rt_dma_sync_out_data(struct rt_device *dev, void *data, rt_size_t size, + rt_ubase_t *dma_handle, rt_ubase_t flags) +{ + rt_err_t err; + rt_ubase_t dma_handle_s = 0; + const struct rt_dma_map_ops *ops; + + if (!data || !size) + { + return -RT_EINVAL; + } + + ops = device_dma_ops(dev); + err = ops->sync_out_data(dev, data, size, &dma_handle_s, flags); + + if (dma_handle) + { + *dma_handle = dma_handle_s; + } + + return err; +} + +rt_err_t rt_dma_sync_in_data(struct rt_device *dev, void *out_data, rt_size_t size, + rt_ubase_t dma_handle, rt_ubase_t flags) +{ + rt_err_t err; + const struct rt_dma_map_ops *ops; + + if (!out_data || !size) + { + return -RT_EINVAL; + } + + ops = device_dma_ops(dev); + err = ops->sync_in_data(dev, out_data, size, dma_handle, flags); + + return err; +} + +static struct rt_dma_pool *dma_pool_install(rt_region_t *region) +{ + rt_err_t err; + struct rt_dma_pool *pool; + + if (!(pool = rt_calloc(1, sizeof(*pool)))) + { + LOG_E("Install pool[%p, %p] error = %s", + region->start, region->end, rt_strerror(-RT_ENOMEM)); + + return RT_NULL; + } + + rt_memcpy(&pool->region, region, sizeof(*region)); + + pool->flags |= RT_DMA_F_LINEAR; + + if (region->end < 4UL * SIZE_GB) + { + pool->flags |= RT_DMA_F_32BITS; + } + + pool->start = RT_ALIGN(pool->region.start, ARCH_PAGE_SIZE); + pool->bits = (pool->region.end - pool->start) / ARCH_PAGE_SIZE; + + if (!pool->bits) + { + err = -RT_EINVAL; + goto _fail; + } + + pool->map = rt_calloc(RT_BITMAP_LEN(pool->bits), sizeof(*pool->map)); + + if (!pool->map) + { + err = -RT_ENOMEM; + goto _fail; + } + + rt_list_init(&pool->list); + + region_pool_lock(); + rt_list_insert_before(&dma_pool_nodes, &pool->list); + region_pool_unlock(); + + return pool; + +_fail: + rt_free(pool); + + LOG_E("Install pool[%p, %p] error = %s", + region->start, region->end, rt_strerror(err)); + + return RT_NULL; +} + +struct rt_dma_pool *rt_dma_pool_install(rt_region_t *region) +{ + struct rt_dma_pool *pool; + + if (!region) + { + return RT_NULL; + } + + if ((pool = dma_pool_install(region))) + { + region = &pool->region; + + LOG_I("%s: Reserved %u.%u MiB at %p", + region->name, + (region->end - region->start) / SIZE_MB, + (region->end - region->start) / SIZE_KB & (SIZE_KB - 1), + region->start); + } + + return pool; +} + +rt_err_t rt_dma_pool_extract(rt_region_t *region_list, rt_size_t list_len, + rt_size_t cma_size, rt_size_t coherent_pool_size) +{ + struct rt_dma_pool *pool; + rt_region_t *region = region_list, *region_high = RT_NULL, cma, coherent_pool; + + if (!region_list || !list_len || cma_size < coherent_pool_size) + { + return -RT_EINVAL; + } + + for (rt_size_t i = 0; i < list_len; ++i, ++region) + { + if (!region->name) + { + continue; + } + + /* Always use low address in 4G */ + if (region->end - region->start >= cma_size) + { + if ((rt_ssize_t)((4UL * SIZE_GB) - region->start) < cma_size) + { + region_high = region; + continue; + } + + goto _found; + } + } + + if (region_high) + { + region = region_high; + LOG_W("No available DMA zone in 4G"); + + goto _found; + } + + return -RT_EEMPTY; + +_found: + if (region->end - region->start != cma_size) + { + cma.start = region->start; + cma.end = cma.start + cma_size; + + /* Update input region */ + region->start += cma_size; + } + else + { + rt_memcpy(&cma, region, sizeof(cma)); + } + + coherent_pool.name = "coherent-pool"; + coherent_pool.start = cma.start; + coherent_pool.end = coherent_pool.start + coherent_pool_size; + + cma.name = "cma"; + cma.start += coherent_pool_size; + + if (!(pool = rt_dma_pool_install(&coherent_pool))) + { + return -RT_ENOMEM; + } + + /* Use: CMA > coherent-pool */ + if (!(pool = rt_dma_pool_install(&cma))) + { + return -RT_ENOMEM; + } + + return RT_EOK; +} + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_MSH) +static int list_dma_pool(int argc, char**argv) +{ + int count = 0; + rt_region_t *region; + struct rt_dma_pool *pool; + + rt_kprintf("%-*.s Region\n", RT_NAME_MAX, "Name"); + + region_pool_lock(); + + rt_list_for_each_entry(pool, &dma_pool_nodes, list) + { + region = &pool->region; + + rt_kprintf("%-*.s [%p, %p]\n", RT_NAME_MAX, region->name, + region->start, region->end); + + ++count; + } + + rt_kprintf("%d DMA memory found\n", count); + + region_pool_unlock(); + + return 0; +} +MSH_CMD_EXPORT(list_dma_pool, dump all dma memory pool); +#endif /* RT_USING_CONSOLE && RT_USING_MSH */ diff --git a/rt-thread/components/drivers/hwtimer/hwtimer.c b/rt-thread/components/drivers/hwtimer/hwtimer.c index bcf9ea9..1b27925 100644 --- a/rt-thread/components/drivers/hwtimer/hwtimer.c +++ b/rt-thread/components/drivers/hwtimer/hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -320,7 +320,14 @@ static rt_err_t rt_hwtimer_control(struct rt_device *dev, int cmd, void *args) break; default: { - result = -RT_ENOSYS; + if (timer->ops->control != RT_NULL) + { + result = timer->ops->control(timer, cmd, args); + } + else + { + result = -RT_ENOSYS; + } } break; } diff --git a/rt-thread/components/drivers/i2c/Kconfig b/rt-thread/components/drivers/i2c/Kconfig index 40f04d1..bb4c90d 100644 --- a/rt-thread/components/drivers/i2c/Kconfig +++ b/rt-thread/components/drivers/i2c/Kconfig @@ -17,203 +17,227 @@ if RT_USING_I2C default n endif - config RT_USING_SOFT_I2C + menuconfig RT_USING_SOFT_I2C bool "Use GPIO to soft simulate I2C" default n select RT_USING_PIN select RT_USING_I2C_BITOPS - if RT_USING_SOFT_I2C - config RT_USING_SOFT_I2C1 - bool "Enable I2C1 Bus (software simulation)" - default y - if RT_USING_SOFT_I2C1 - config RT_SOFT_I2C1_SCL_PIN - int "SCL pin number" - range 0 32767 - default 1 - config RT_SOFT_I2C1_SDA_PIN - int "SDA pin number" - range 0 32767 - default 2 - config RT_SOFT_I2C1_BUS_NAME - string "Bus name" - default "i2c1" - config RT_SOFT_I2C1_TIMING_DELAY - int "Timing delay (us)" - range 0 32767 - default 10 - config RT_SOFT_I2C1_TIMING_TIMEOUT - int "Timing timeout (tick)" - range 0 32767 - default 10 - endif - config RT_USING_SOFT_I2C2 - bool "Enable I2C2 Bus (software simulation)" - default n - if RT_USING_SOFT_I2C2 - config RT_SOFT_I2C2_SCL_PIN - int "SCL pin number" - range 0 32767 - default 3 - config RT_SOFT_I2C2_SDA_PIN - int "SDA pin number" - range 0 32767 - default 4 - config RT_SOFT_I2C2_BUS_NAME - string "Bus name" - default "i2c2" - config RT_SOFT_I2C2_TIMING_DELAY - int "Timing delay (us)" - range 0 32767 - default 10 - config RT_SOFT_I2C2_TIMING_TIMEOUT - int "Timing timeout (tick)" - range 0 32767 - default 10 - endif - config RT_USING_SOFT_I2C3 - bool "Enable I2C3 Bus (software simulation)" - default n - if RT_USING_SOFT_I2C3 - config RT_SOFT_I2C3_SCL_PIN - int "SCL pin number" - range 0 32767 - default 5 - config RT_SOFT_I2C3_SDA_PIN - int "SDA pin number" - range 0 32767 - default 6 - config RT_SOFT_I2C3_BUS_NAME - string "Bus name" - default "i2c3" - config RT_SOFT_I2C3_TIMING_DELAY - int "Timing delay (us)" - range 0 32767 - default 10 - config RT_SOFT_I2C3_TIMING_TIMEOUT - int "Timing timeout (tick)" - range 0 32767 - default 10 - endif - config RT_USING_SOFT_I2C4 - bool "Enable I2C4 Bus (software simulation)" - default n - if RT_USING_SOFT_I2C4 - config RT_SOFT_I2C4_SCL_PIN - int "SCL pin number" - range 0 32767 - default 7 - config RT_SOFT_I2C4_SDA_PIN - int "SDA pin number" - range 0 32767 - default 8 - config RT_SOFT_I2C4_BUS_NAME - string "Bus name" - default "i2c4" - config RT_SOFT_I2C4_TIMING_DELAY - int "Timing delay (us)" - range 0 32767 - default 10 - config RT_SOFT_I2C4_TIMING_TIMEOUT - int "Timing timeout (tick)" - range 0 32767 - default 10 - endif - config RT_USING_SOFT_I2C5 - bool "Enable I2C5 Bus (software simulation)" - default n - if RT_USING_SOFT_I2C5 - config RT_SOFT_I2C5_SCL_PIN - int "SCL pin number" - range 0 32767 - default 9 - config RT_SOFT_I2C5_SDA_PIN - int "SDA pin number" - range 0 32767 - default 10 - config RT_SOFT_I2C5_BUS_NAME - string "Bus name" - default "i2c5" - config RT_SOFT_I2C5_TIMING_DELAY - int "Timing delay (us)" - range 0 32767 - default 10 - config RT_SOFT_I2C5_TIMING_TIMEOUT - int "Timing timeout (tick)" - range 0 32767 - default 10 - endif - config RT_USING_SOFT_I2C6 - bool "Enable I2C6 Bus (software simulation)" - default n - if RT_USING_SOFT_I2C6 - config RT_SOFT_I2C6_SCL_PIN - int "SCL pin number" - range 0 32767 - default 11 - config RT_SOFT_I2C6_SDA_PIN - int "SDA pin number" - range 0 32767 - default 12 - config RT_SOFT_I2C6_BUS_NAME - string "Bus name" - default "i2c6" - config RT_SOFT_I2C6_TIMING_DELAY - int "Timing delay (us)" - range 0 32767 - default 10 - config RT_SOFT_I2C6_TIMING_TIMEOUT - int "Timing timeout (tick)" - range 0 32767 - default 10 - endif - config RT_USING_SOFT_I2C7 - bool "Enable I2C7 Bus (software simulation)" - default n - if RT_USING_SOFT_I2C7 - config RT_SOFT_I2C7_SCL_PIN - int "SCL pin number" - range 0 32767 - default 13 - config RT_SOFT_I2C7_SDA_PIN - int "SDA pin number" - range 0 32767 - default 14 - config RT_SOFT_I2C7_BUS_NAME - string "Bus name" - default "i2c7" - config RT_SOFT_I2C7_TIMING_DELAY - int "Timing delay (us)" - range 0 32767 - default 10 - config RT_SOFT_I2C7_TIMING_TIMEOUT - int "Timing timeout (tick)" - range 0 32767 - default 10 - endif - config RT_USING_SOFT_I2C8 - bool "Enable I2C8 Bus (software simulation)" - default n - if RT_USING_SOFT_I2C8 - config RT_SOFT_I2C8_SCL_PIN - int "SCL pin number" - range 0 32767 - default 15 - config RT_SOFT_I2C8_SDA_PIN - int "SDA pin number" - range 0 32767 - default 16 - config RT_SOFT_I2C8_BUS_NAME - string "Bus name" - default "i2c8" - config RT_SOFT_I2C8_TIMING_DELAY - int "Timing delay (us)" - range 0 32767 - default 10 - config RT_SOFT_I2C8_TIMING_TIMEOUT - int "Timing timeout (tick)" - range 0 32767 - default 10 - endif - endif + if RT_USING_SOFT_I2C + menuconfig RT_USING_SOFT_I2C0 + bool "Enable I2C0 Bus (software simulation)" + default y + if RT_USING_SOFT_I2C0 + config RT_SOFT_I2C0_SCL_PIN + int "SCL pin number" + range 0 32767 + default 1 + config RT_SOFT_I2C0_SDA_PIN + int "SDA pin number" + range 0 32767 + default 2 + config RT_SOFT_I2C0_BUS_NAME + string "Bus name" + default "i2c0" + config RT_SOFT_I2C0_TIMING_DELAY + int "Timing delay (us)" + range 0 32767 + default 10 + config RT_SOFT_I2C0_TIMING_TIMEOUT + int "Timing timeout (tick)" + range 0 32767 + default 10 + endif + menuconfig RT_USING_SOFT_I2C1 + bool "Enable I2C1 Bus (software simulation)" + default y + if RT_USING_SOFT_I2C1 + config RT_SOFT_I2C1_SCL_PIN + int "SCL pin number" + range 0 32767 + default 3 + config RT_SOFT_I2C1_SDA_PIN + int "SDA pin number" + range 0 32767 + default 4 + config RT_SOFT_I2C1_BUS_NAME + string "Bus name" + default "i2c1" + config RT_SOFT_I2C1_TIMING_DELAY + int "Timing delay (us)" + range 0 32767 + default 10 + config RT_SOFT_I2C1_TIMING_TIMEOUT + int "Timing timeout (tick)" + range 0 32767 + default 10 + endif + menuconfig RT_USING_SOFT_I2C2 + bool "Enable I2C2 Bus (software simulation)" + default n + if RT_USING_SOFT_I2C2 + config RT_SOFT_I2C2_SCL_PIN + int "SCL pin number" + range 0 32767 + default 5 + config RT_SOFT_I2C2_SDA_PIN + int "SDA pin number" + range 0 32767 + default 6 + config RT_SOFT_I2C2_BUS_NAME + string "Bus name" + default "i2c2" + config RT_SOFT_I2C2_TIMING_DELAY + int "Timing delay (us)" + range 0 32767 + default 10 + config RT_SOFT_I2C2_TIMING_TIMEOUT + int "Timing timeout (tick)" + range 0 32767 + default 10 + endif + menuconfig RT_USING_SOFT_I2C3 + bool "Enable I2C3 Bus (software simulation)" + default n + if RT_USING_SOFT_I2C3 + config RT_SOFT_I2C3_SCL_PIN + int "SCL pin number" + range 0 32767 + default 7 + config RT_SOFT_I2C3_SDA_PIN + int "SDA pin number" + range 0 32767 + default 8 + config RT_SOFT_I2C3_BUS_NAME + string "Bus name" + default "i2c3" + config RT_SOFT_I2C3_TIMING_DELAY + int "Timing delay (us)" + range 0 32767 + default 10 + config RT_SOFT_I2C3_TIMING_TIMEOUT + int "Timing timeout (tick)" + range 0 32767 + default 10 + endif + menuconfig RT_USING_SOFT_I2C4 + bool "Enable I2C4 Bus (software simulation)" + default n + if RT_USING_SOFT_I2C4 + config RT_SOFT_I2C4_SCL_PIN + int "SCL pin number" + range 0 32767 + default 9 + config RT_SOFT_I2C4_SDA_PIN + int "SDA pin number" + range 0 32767 + default 10 + config RT_SOFT_I2C4_BUS_NAME + string "Bus name" + default "i2c4" + config RT_SOFT_I2C4_TIMING_DELAY + int "Timing delay (us)" + range 0 32767 + default 10 + config RT_SOFT_I2C4_TIMING_TIMEOUT + int "Timing timeout (tick)" + range 0 32767 + default 10 + endif + menuconfig RT_USING_SOFT_I2C5 + bool "Enable I2C5 Bus (software simulation)" + default n + if RT_USING_SOFT_I2C5 + config RT_SOFT_I2C5_SCL_PIN + int "SCL pin number" + range 0 32767 + default 11 + config RT_SOFT_I2C5_SDA_PIN + int "SDA pin number" + range 0 32767 + default 12 + config RT_SOFT_I2C5_BUS_NAME + string "Bus name" + default "i2c5" + config RT_SOFT_I2C5_TIMING_DELAY + int "Timing delay (us)" + range 0 32767 + default 10 + config RT_SOFT_I2C5_TIMING_TIMEOUT + int "Timing timeout (tick)" + range 0 32767 + default 10 + endif + menuconfig RT_USING_SOFT_I2C6 + bool "Enable I2C6 Bus (software simulation)" + default n + if RT_USING_SOFT_I2C6 + config RT_SOFT_I2C6_SCL_PIN + int "SCL pin number" + range 0 32767 + default 13 + config RT_SOFT_I2C6_SDA_PIN + int "SDA pin number" + range 0 32767 + default 14 + config RT_SOFT_I2C6_BUS_NAME + string "Bus name" + default "i2c6" + config RT_SOFT_I2C6_TIMING_DELAY + int "Timing delay (us)" + range 0 32767 + default 10 + config RT_SOFT_I2C6_TIMING_TIMEOUT + int "Timing timeout (tick)" + range 0 32767 + default 10 + endif + menuconfig RT_USING_SOFT_I2C7 + bool "Enable I2C7 Bus (software simulation)" + default n + if RT_USING_SOFT_I2C7 + config RT_SOFT_I2C7_SCL_PIN + int "SCL pin number" + range 0 32767 + default 15 + config RT_SOFT_I2C7_SDA_PIN + int "SDA pin number" + range 0 32767 + default 16 + config RT_SOFT_I2C7_BUS_NAME + string "Bus name" + default "i2c7" + config RT_SOFT_I2C7_TIMING_DELAY + int "Timing delay (us)" + range 0 32767 + default 10 + config RT_SOFT_I2C7_TIMING_TIMEOUT + int "Timing timeout (tick)" + range 0 32767 + default 10 + endif + menuconfig RT_USING_SOFT_I2C8 + bool "Enable I2C8 Bus (software simulation)" + default n + if RT_USING_SOFT_I2C8 + config RT_SOFT_I2C8_SCL_PIN + int "SCL pin number" + range 0 32767 + default 17 + config RT_SOFT_I2C8_SDA_PIN + int "SDA pin number" + range 0 32767 + default 18 + config RT_SOFT_I2C8_BUS_NAME + string "Bus name" + default "i2c8" + config RT_SOFT_I2C8_TIMING_DELAY + int "Timing delay (us)" + range 0 32767 + default 10 + config RT_SOFT_I2C8_TIMING_TIMEOUT + int "Timing timeout (tick)" + range 0 32767 + default 10 + endif + endif endif diff --git a/rt-thread/components/drivers/i2c/SConscript b/rt-thread/components/drivers/i2c/SConscript index 3685e44..269c6f5 100644 --- a/rt-thread/components/drivers/i2c/SConscript +++ b/rt-thread/components/drivers/i2c/SConscript @@ -3,16 +3,16 @@ from building import * cwd = GetCurrentDir() src = Split(""" -i2c_core.c -i2c_dev.c +dev_i2c_core.c +dev_i2c_dev.c """) if GetDepend('RT_USING_I2C_BITOPS'): - src = src + ['i2c-bit-ops.c'] + src = src + ['dev_i2c_bit_ops.c'] if GetDepend('RT_USING_SOFT_I2C'): - src = src + ['soft_i2c.c'] + src = src + ['dev_soft_i2c.c'] if GetDepend(['RT_USING_DM']): - src += ['i2c_bus.c', 'i2c_dm.c'] + src += ['dev_i2c_bus.c', 'dev_i2c_dm.c'] # The set of source files associated with this SConscript file. path = [cwd + '/../include'] diff --git a/rt-thread/components/drivers/i2c/i2c-bit-ops.c b/rt-thread/components/drivers/i2c/dev_i2c_bit_ops.c similarity index 100% rename from rt-thread/components/drivers/i2c/i2c-bit-ops.c rename to rt-thread/components/drivers/i2c/dev_i2c_bit_ops.c diff --git a/rt-thread/components/drivers/i2c/i2c_bus.c b/rt-thread/components/drivers/i2c/dev_i2c_bus.c similarity index 99% rename from rt-thread/components/drivers/i2c/i2c_bus.c rename to rt-thread/components/drivers/i2c/dev_i2c_bus.c index e9626ca..8a52471 100644 --- a/rt-thread/components/drivers/i2c/i2c_bus.c +++ b/rt-thread/components/drivers/i2c/dev_i2c_bus.c @@ -10,7 +10,7 @@ #include -#define DBG_TAG "i2c.bus" +#define DBG_TAG "dev.i2c.bus" #define DBG_LVL DBG_INFO #include diff --git a/rt-thread/components/drivers/i2c/i2c_core.c b/rt-thread/components/drivers/i2c/dev_i2c_core.c similarity index 98% rename from rt-thread/components/drivers/i2c/i2c_core.c rename to rt-thread/components/drivers/i2c/dev_i2c_core.c index 2b8e58c..9d9bf6b 100644 --- a/rt-thread/components/drivers/i2c/i2c_core.c +++ b/rt-thread/components/drivers/i2c/dev_i2c_core.c @@ -30,7 +30,7 @@ rt_err_t rt_i2c_bus_device_register(struct rt_i2c_bus_device *bus, res = rt_i2c_bus_device_device_init(bus, bus_name); - LOG_I("I2C bus [%s] registered", bus_name); + LOG_D("I2C bus [%s] registered", bus_name); #ifdef RT_USING_DM if (!res) diff --git a/rt-thread/components/drivers/i2c/i2c_dev.c b/rt-thread/components/drivers/i2c/dev_i2c_dev.c similarity index 100% rename from rt-thread/components/drivers/i2c/i2c_dev.c rename to rt-thread/components/drivers/i2c/dev_i2c_dev.c diff --git a/rt-thread/components/drivers/i2c/i2c_dm.c b/rt-thread/components/drivers/i2c/dev_i2c_dm.c similarity index 98% rename from rt-thread/components/drivers/i2c/i2c_dm.c rename to rt-thread/components/drivers/i2c/dev_i2c_dm.c index 95b1fe6..5701dd5 100644 --- a/rt-thread/components/drivers/i2c/i2c_dm.c +++ b/rt-thread/components/drivers/i2c/dev_i2c_dm.c @@ -10,7 +10,7 @@ #include -#define DBG_TAG "i2c.dm" +#define DBG_TAG "dev.i2c.dm" #define DBG_LVL DBG_INFO #include diff --git a/rt-thread/components/drivers/i2c/soft_i2c.c b/rt-thread/components/drivers/i2c/dev_soft_i2c.c similarity index 94% rename from rt-thread/components/drivers/i2c/soft_i2c.c rename to rt-thread/components/drivers/i2c/dev_soft_i2c.c index 54c7395..a9c661e 100644 --- a/rt-thread/components/drivers/i2c/soft_i2c.c +++ b/rt-thread/components/drivers/i2c/dev_soft_i2c.c @@ -11,7 +11,8 @@ #include #ifdef RT_USING_SOFT_I2C -#if !defined(RT_USING_SOFT_I2C1) && !defined(RT_USING_SOFT_I2C2) &&\ +#if !defined(RT_USING_SOFT_I2C0) &&\ + !defined(RT_USING_SOFT_I2C1) && !defined(RT_USING_SOFT_I2C2) &&\ !defined(RT_USING_SOFT_I2C3) && !defined(RT_USING_SOFT_I2C4) &&\ !defined(RT_USING_SOFT_I2C5) && !defined(RT_USING_SOFT_I2C6) &&\ !defined(RT_USING_SOFT_I2C7) && !defined(RT_USING_SOFT_I2C8) @@ -48,6 +49,15 @@ struct rt_soft_i2c struct soft_i2c_config i2c_cfg[] = { + #ifdef RT_USING_SOFT_I2C0 + { + .scl_pin = RT_SOFT_I2C0_SCL_PIN, + .sda_pin = RT_SOFT_I2C0_SDA_PIN, + .bus_name = RT_SOFT_I2C0_BUS_NAME, + .timing_delay = RT_SOFT_I2C0_TIMING_DELAY, + .timing_timeout = RT_SOFT_I2C0_TIMING_TIMEOUT, + }, + #endif //RT_USING_SOFT_I2C0 #ifdef RT_USING_SOFT_I2C1 { .scl_pin = RT_SOFT_I2C1_SCL_PIN, diff --git a/rt-thread/components/drivers/iio/SConscript b/rt-thread/components/drivers/iio/SConscript new file mode 100644 index 0000000..577dab2 --- /dev/null +++ b/rt-thread/components/drivers/iio/SConscript @@ -0,0 +1,15 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_DM']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] + +src = ['iio.c',] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/iio/iio.c b/rt-thread/components/drivers/iio/iio.c new file mode 100644 index 0000000..548308d --- /dev/null +++ b/rt-thread/components/drivers/iio/iio.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-3-08 GuEe-GUI the first version + */ + +#include +#include + +static void *ofw_iio_channel_get_by_index(struct rt_ofw_node *np, int index, int *out_channel) +{ + void *iio = RT_NULL; +#ifdef RT_USING_OFW + struct rt_ofw_node *iio_np; + struct rt_ofw_cell_args iio_args; + + if (!rt_ofw_parse_phandle_cells(np, "io-channels", "#io-channel-cells", index, &iio_args)) + { + iio_np = iio_args.data; + + if (!rt_ofw_data(iio_np)) + { + rt_platform_ofw_request(iio_np); + } + + iio = rt_ofw_data(iio_np); + rt_ofw_node_put(iio_np); + + if (out_channel) + { + *out_channel = iio_args.args[0]; + } + } +#endif /* RT_USING_OFW */ + return iio; +} + +void *rt_iio_channel_get_by_index(struct rt_device *dev, int index, int *out_channel) +{ + void *iio = RT_NULL; + + if (!dev || index < 0) + { + return RT_NULL; + } + + if (dev->ofw_node) + { + iio = ofw_iio_channel_get_by_index(dev->ofw_node, index, out_channel); + } + + return iio; +} + +void *rt_iio_channel_get_by_name(struct rt_device *dev, const char *name, int *out_channel) +{ + int index; + + if (!dev || !name) + { + return RT_NULL; + } + + index = rt_dm_dev_prop_index_of_string(dev, "io-channel-names", name); + + return rt_iio_channel_get_by_index(dev, index, out_channel); +} diff --git a/rt-thread/components/drivers/include/drivers/adc.h b/rt-thread/components/drivers/include/drivers/adc.h index 7c35f1e..7189ae5 100644 --- a/rt-thread/components/drivers/include/drivers/adc.h +++ b/rt-thread/components/drivers/include/drivers/adc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,12 +14,65 @@ #define __ADC_H__ #include +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup ADC ADC + * + * @brief ADC driver api + * + * Example + * @code {.c} + * #define ADC_DEV_NAME "adc1" + * #define ADC_DEV_CHANNEL 5 + * #define REFER_VOLTAGE 330 + * #define CONVERT_BITS (1 << 12) + * + * static int adc_vol_sample(int argc, char *argv[]) + * { + * rt_adc_device_t adc_dev; + * rt_uint32_t value, vol; + * + * rt_err_t ret = RT_EOK; + * + * adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME); + * if (adc_dev == RT_NULL) + * { + * rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME); + * return -RT_ERROR; + * } + * + * ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL); + * + * value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL); + * rt_kprintf("the value is :%d \n", value); + * + * vol = value * REFER_VOLTAGE / CONVERT_BITS; + * rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); + * + * ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL); + * + * return ret; + * } + * MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); + * + * @endcode + * + * @ingroup Drivers + */ + +/*! + * @addtogroup ADC + * @{ + */ #define RT_ADC_INTERN_CH_TEMPER (-1) #define RT_ADC_INTERN_CH_VREF (-2) #define RT_ADC_INTERN_CH_VBAT (-3) struct rt_adc_device; +/** + * @brief Configure the adc device + */ struct rt_adc_ops { rt_err_t (*enabled)(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled); @@ -27,7 +80,9 @@ struct rt_adc_ops rt_uint8_t (*get_resolution)(struct rt_adc_device *device); rt_int16_t (*get_vref) (struct rt_adc_device *device); }; - +/** + * @brief adc device + */ struct rt_adc_device { struct rt_device parent; @@ -43,10 +98,53 @@ typedef enum RT_ADC_CMD_GET_VREF = RT_DEVICE_CTRL_BASE(ADC) + 4, /* get reference voltage */ } rt_adc_cmd_t; +/** + * @brief register the adc device + * @param adc adc device + * @param name device name + * @param ops device ops + * @param user_data device private data + * @return rt_err_t error code + * @ingroup ADC + */ rt_err_t rt_hw_adc_register(rt_adc_device_t adc,const char *name, const struct rt_adc_ops *ops, const void *user_data); + +/** + * @brief read the adc value + * @param dev adc device + * @param channel adc channel + * @return rt_uint32_t adc value + * @ingroup ADC + */ rt_uint32_t rt_adc_read(rt_adc_device_t dev, rt_int8_t channel); + +/** + * @brief enable the adc channel + * @param dev adc device + * @param channel adc channel + * @return rt_err_t error code + * @ingroup ADC + */ rt_err_t rt_adc_enable(rt_adc_device_t dev, rt_int8_t channel); + +/** + * @brief disable the adc channel + * @param dev adc device + * @param channel adc channel + * @return rt_err_t error code + * @ingroup ADC + */ rt_err_t rt_adc_disable(rt_adc_device_t dev, rt_int8_t channel); + +/** + * @brief get the adc resolution + * @param dev adc device + * @param channel adc channel + * @return rt_int16_t adc resolution + * @ingroup ADC + */ rt_int16_t rt_adc_voltage(rt_adc_device_t dev, rt_int8_t channel); +/*! @}*/ + #endif /* __ADC_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/ahci.h b/rt-thread/components/drivers/include/drivers/ahci.h new file mode 100644 index 0000000..45e47a8 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/ahci.h @@ -0,0 +1,397 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#ifndef __AHCI_H__ +#define __AHCI_H__ + +#include +#include +#include +#include + +struct rt_ahci_ops; + +/* Generic Host Control */ +#define RT_AHCI_HBA_CAP 0x00 /* Host capability*/ +#define RT_AHCI_CAP_NP RT_GENMASK(4, 0) /* Number of Ports */ +#define RT_AHCI_CAP_NCS RT_GENMASK(8, 12) /* Number of Command Slots */ +#define RT_AHCI_CAP_PSC RT_BIT(13) /* Partial State Capable */ +#define RT_AHCI_CAP_SSC RT_BIT(14) /* Slumber capable */ +#define RT_AHCI_CAP_PMD RT_BIT(15) /* PIO Multiple DRQ Block */ +#define RT_AHCI_CAP_SPM RT_BIT(17) /* Port Multiplier */ +#define RT_AHCI_CAP_AHCI RT_BIT(18) /* AHCI only */ +#define RT_AHCI_CAP_SNZO RT_BIT(19) /* Non-Zero DMA Offsets */ +#define RT_AHCI_CAP_ISS RT_GENMASK(23, 20) /* Interface Speed Support */ +#define RT_AHCI_CAP_CLO RT_BIT(24) /* Command List Override support */ +#define RT_AHCI_CAP_SAL RT_BIT(25) /* Activity LED */ +#define RT_AHCI_CAP_SALP RT_BIT(26) /* Aggressive Link Power Management */ +#define RT_AHCI_CAP_SSS RT_BIT(27) /* Staggered Spin-up */ +#define RT_AHCI_CAP_SIS RT_BIT(28) /* Interlock Switch */ +#define RT_AHCI_CAP_NCQ RT_BIT(30) /* Native Command Queueing */ +#define RT_AHCI_CAP_64 RT_BIT(31) /* PCI DAC (64-bit DMA) support */ +#define RT_AHCI_HBA_GHC 0x04 /* Global host control */ +#define RT_AHCI_GHC_RESET RT_BIT(0) /* Reset controller; self-clear */ +#define RT_AHCI_GHC_IRQ_EN RT_BIT(1) /* Global IRQ enable */ +#define RT_AHCI_GHC_AHCI_EN RT_BIT(31) /* AHCI enabled */ +#define RT_AHCI_HBA_INTS 0x08 /* Interrupt status */ +#define RT_AHCI_HBA_PI 0x0c /* Port implemented */ +#define RT_AHCI_HBA_VS 0x10 /* Version */ +#define RT_AHCI_HBA_CCC_CTL 0x14 /* Command completion coalescing control */ +#define RT_AHCI_HBA_CCC_PTS 0x18 /* Command completion coalescing ports */ +#define RT_AHCI_HBA_EM_LOC 0x1c /* Enclosure management location */ +#define RT_AHCI_HBA_EM_CTL 0x20 /* Enclosure management control */ +#define RT_AHCI_HBA_CAP2 0x24 /* Host capabilities extended */ +#define RT_AHCI_HBA_BOHC 0x28 /* BIOS/OS handoff control and status */ +#define RT_AHCI_HBA_VENDOR 0xa0 /* Vendor specific registers (0xa0 - 0xff) */ + +#define RT_AHCI_PORT_CLB 0x00 /* Command list base address, 1K-byte aligned */ +#define RT_AHCI_PORT_CLBU 0x04 /* Command list base address upper 32 bits */ +#define RT_AHCI_PORT_FB 0x08 /* FIS base address, 256-byte aligned */ +#define RT_AHCI_PORT_FBU 0x0C /* FIS base address upper 32 bits */ +#define RT_AHCI_PORT_INTS 0x10 /* Interrupt status */ +#define RT_AHCI_PORT_INTE 0x14 /* Interrupt enable */ +#define RT_AHCI_PORT_INTE_D2H_REG_FIS RT_BIT(0) /* D2H Register FIS rx'd */ +#define RT_AHCI_PORT_INTE_PIOS_FIS RT_BIT(1) /* PIO Setup FIS rx'd */ +#define RT_AHCI_PORT_INTE_DMAS_FIS RT_BIT(2) /* DMA Setup FIS rx'd */ +#define RT_AHCI_PORT_INTE_SDB_FIS RT_BIT(3) /* Set Device Bits FIS rx'd */ +#define RT_AHCI_PORT_INTE_UNK_FIS RT_BIT(4) /* Unknown FIS rx'd */ +#define RT_AHCI_PORT_INTE_SG_DONE RT_BIT(5) /* Descriptor processed */ +#define RT_AHCI_PORT_INTE_CONNECT RT_BIT(6) /* Port connect change status */ +#define RT_AHCI_PORT_INTE_DMPS RT_BIT(7) /* Mechanical presence status */ +#define RT_AHCI_PORT_INTE_PHYRDY RT_BIT(22) /* PhyRdy changed */ +#define RT_AHCI_PORT_INTE_BAD_PMP RT_BIT(23) /* Incorrect port multiplier */ +#define RT_AHCI_PORT_INTE_OVERFLOW RT_BIT(24) /* Xfer exhausted available S/G */ +#define RT_AHCI_PORT_INTE_IF_NONFATAL RT_BIT(26) /* Interface non-fatal error */ +#define RT_AHCI_PORT_INTE_IF_ERR RT_BIT(27) /* Interface fatal error */ +#define RT_AHCI_PORT_INTE_HBUS_DATA_ERR RT_BIT(28) /* Host bus data error */ +#define RT_AHCI_PORT_INTE_HBUS_ERR RT_BIT(29) /* Host bus fatal error */ +#define RT_AHCI_PORT_INTE_TF_ERR RT_BIT(30) /* Task file error */ +#define RT_AHCI_PORT_INTE_COLD_PRES RT_BIT(31) /* Cold presence detect */ +#define RT_AHCI_PORT_CMD 0x18 /* Command and status */ +#define RT_AHCI_PORT_CMD_START RT_BIT(0) /* Enable port DMA engine */ +#define RT_AHCI_PORT_CMD_SPIN_UP RT_BIT(1) /* Spin up device */ +#define RT_AHCI_PORT_CMD_POWER_ON RT_BIT(2) /* Power up device */ +#define RT_AHCI_PORT_CMD_CLO RT_BIT(3) /* Command list override */ +#define RT_AHCI_PORT_CMD_FIS_RX RT_BIT(4) /* Enable FIS receive DMA engine */ +#define RT_AHCI_PORT_CMD_FIS_ON RT_BIT(14) /* FIS DMA engine running */ +#define RT_AHCI_PORT_CMD_LIST_ON RT_BIT(15) /* cmd list DMA engine running */ +#define RT_AHCI_PORT_CMD_ATAPI RT_BIT(24) /* Device is ATAPI */ +#define RT_AHCI_PORT_CMD_ACTIVE RT_BIT(28) /* Active state */ +#define RT_AHCI_PORT_TFD 0x20 /* Task file data */ +#define RT_AHCI_PORT_TFDATA_ERR RT_BIT(0) /* Indicates an error during the transfer */ +#define RT_AHCI_PORT_TFDATA_DRQ RT_BIT(3) /* Indicates a data transfer is requested */ +#define RT_AHCI_PORT_TFDATA_BSY RT_BIT(7) /* Indicates the interface is busy */ +#define RT_AHCI_PORT_SIG 0x24 /* Signature */ +#define RT_AHCI_PORT_SIG_REG_MASK 0xff +#define RT_AHCI_PORT_SIG_SECTOR_NR_SHIFT 0 /* Sector Count Register */ +#define RT_AHCI_PORT_SIG_LBA_LOW_SHIFT 8 /* LBA Low Register */ +#define RT_AHCI_PORT_SIG_LBA_MID_SHIFT 16 /* LBA Mid Register */ +#define RT_AHCI_PORT_SIG_LBA_HIGH_SHIFT 24 /* LBA High Register */ +#define RT_AHCI_PORT_SIG_SATA_CDROM 0xeb140101 +#define RT_AHCI_PORT_SIG_SATA_DISK 0x00000101 +#define RT_AHCI_PORT_SSTS 0x28 /* SATA status (SCR0:SStatus) */ +#define RT_AHCI_PORT_SSTS_DET_MASK 0x3 +#define RT_AHCI_PORT_SSTS_DET_COMINIT 0x1 +#define RT_AHCI_PORT_SSTS_DET_PHYRDY 0x3 +#define RT_AHCI_PORT_SCTL 0x2c /* SATA control (SCR2:SControl) */ +#define RT_AHCI_PORT_SERR 0x30 /* SATA error (SCR1:SError) */ +#define RT_AHCI_PORT_SERR_ERR_I RT_BIT(0) /* Recovered Data Integrity Error */ +#define RT_AHCI_PORT_SERR_ERR_M RT_BIT(1) /* Recovered Communications Error */ +#define RT_AHCI_PORT_SERR_ERR_T RT_BIT(8) /* Transient Data Integrity Error */ +#define RT_AHCI_PORT_SERR_ERR_C RT_BIT(9) /* Persistent Communication or Data Integrity Error */ +#define RT_AHCI_PORT_SERR_ERR_P RT_BIT(10) /* Protocol Error */ +#define RT_AHCI_PORT_SERR_ERR_E RT_BIT(11) /* Internal Error */ +#define RT_AHCI_PORT_SERR_DIAG_N RT_BIT(16) /* PhyRdy Change */ +#define RT_AHCI_PORT_SERR_DIAG_I RT_BIT(17) /* Phy Internal Error */ +#define RT_AHCI_PORT_SERR_DIAG_W RT_BIT(18) /* Comm Wake */ +#define RT_AHCI_PORT_SERR_DIAG_B RT_BIT(19) /* 10B to 8B Decode Error */ +#define RT_AHCI_PORT_SERR_DIAG_D RT_BIT(20) /* Disparity Error */ +#define RT_AHCI_PORT_SERR_DIAG_C RT_BIT(21) /* CRC Error */ +#define RT_AHCI_PORT_SERR_DIAG_H RT_BIT(22) /* Handshake Error */ +#define RT_AHCI_PORT_SERR_DIAG_S RT_BIT(23) /* Link Sequence Error */ +#define RT_AHCI_PORT_SERR_DIAG_T RT_BIT(24) /* Transport state transition error */ +#define RT_AHCI_PORT_SERR_DIAG_F RT_BIT(25) /* Unknown FIS Type */ +#define RT_AHCI_PORT_SERR_DIAG_X RT_BIT(26) /* Exchanged */ +#define RT_AHCI_PORT_SACT 0x34 /* SATA active (SCR3:SActive) */ +#define RT_AHCI_PORT_CI 0x38 /* Command issue */ +#define RT_AHCI_PORT_SNTF 0x3c /* SATA notification (SCR4:SNotification) */ +#define RT_AHCI_PORT_FBS 0x40 /* FIS-based switch control */ +#define RT_AHCI_PORT_VENDOR 0x70 /* Vendor specific (0x70 - 0x7f) */ + +#define RT_AHCI_MAX_SG 56 +#define RT_AHCI_CMD_SLOT_SIZE 32 +#define RT_AHCI_MAX_CMD_SLOT 32 +#define RT_AHCI_RX_FIS_SIZE 256 +#define RT_AHCI_CMD_TBL_HDR 0x80 +#define RT_AHCI_CMD_TBL_CDB 0x40 +#define RT_AHCI_CMD_TBL_SIZE RT_AHCI_CMD_TBL_HDR + (RT_AHCI_MAX_SG * 16) +#define RT_AHCI_DMA_SIZE (RT_AHCI_CMD_SLOT_SIZE * RT_AHCI_MAX_CMD_SLOT + RT_AHCI_CMD_TBL_SIZE + RT_AHCI_RX_FIS_SIZE) +#define RT_ACHI_PRDT_BYTES_MAX (4 * 1024 * 1024) + +#define RT_AHCI_FIS_TYPE_REG_H2D 0x27 /* Register FIS - host to device */ +#define RT_AHCI_FIS_TYPE_REG_D2H 0x34 /* Register FIS - device to host */ +#define RT_AHCI_FIS_TYPE_DMA_ACT 0x39 /* DMA activate FIS - device to host */ +#define RT_AHCI_FIS_TYPE_DMA_SETUP 0x41 /* DMA setup FIS - bidirectional */ +#define RT_AHCI_FIS_TYPE_DATA 0x46 /* Data FIS - bidirectional */ +#define RT_AHCI_FIS_TYPE_BIST 0x58 /* BIST activate FIS - bidirectional */ +#define RT_AHCI_FIS_TYPE_PIO_SETUP 0x5f /* PIO setup FIS - device to host */ +#define RT_AHCI_FIS_TYPE_DEV_BITS 0xa1 /* Set device bits FIS - device to host */ + +#define RT_AHCI_ATA_ID_WORDS 256 +#define RT_AHCI_ATA_ID_CONFIG 0 +#define RT_AHCI_ATA_ID_CYLS 1 +#define RT_AHCI_ATA_ID_HEADS 3 +#define RT_AHCI_ATA_ID_SECTORS 6 +#define RT_AHCI_ATA_ID_SERNO 10 +#define RT_AHCI_ATA_ID_BUF_SIZE 21 +#define RT_AHCI_ATA_ID_FW_REV 23 +#define RT_AHCI_ATA_ID_PROD 27 +#define RT_AHCI_ATA_ID_MAX_MULTSECT 47 +#define RT_AHCI_ATA_ID_DWORD_IO 48 +#define RT_AHCI_ATA_ID_TRUSTED 48 +#define RT_AHCI_ATA_ID_CAPABILITY 49 +#define RT_AHCI_ATA_ID_OLD_PIO_MODES 51 +#define RT_AHCI_ATA_ID_OLD_DMA_MODES 52 +#define RT_AHCI_ATA_ID_FIELD_VALID 53 +#define RT_AHCI_ATA_ID_CUR_CYLS 54 +#define RT_AHCI_ATA_ID_CUR_HEADS 55 +#define RT_AHCI_ATA_ID_CUR_SECTORS 56 +#define RT_AHCI_ATA_ID_MULTSECT 59 +#define RT_AHCI_ATA_ID_LBA_CAPACITY 60 +#define RT_AHCI_ATA_ID_SWDMA_MODES 62 +#define RT_AHCI_ATA_ID_MWDMA_MODES 63 +#define RT_AHCI_ATA_ID_PIO_MODES 64 +#define RT_AHCI_ATA_ID_EIDE_DMA_MIN 65 +#define RT_AHCI_ATA_ID_EIDE_DMA_TIME 66 +#define RT_AHCI_ATA_ID_EIDE_PIO 67 +#define RT_AHCI_ATA_ID_EIDE_PIO_IORDY 68 +#define RT_AHCI_ATA_ID_ADDITIONAL_SUPP 69 +#define RT_AHCI_ATA_ID_QUEUE_DEPTH 75 +#define RT_AHCI_ATA_ID_SATA_CAPABILITY 76 +#define RT_AHCI_ATA_ID_SATA_CAPABILITY_2 77 +#define RT_AHCI_ATA_ID_FEATURE_SUPP 78 +#define RT_AHCI_ATA_ID_MAJOR_VER 80 +#define RT_AHCI_ATA_ID_COMMAND_SET_1 82 +#define RT_AHCI_ATA_ID_COMMAND_SET_2 83 +#define RT_AHCI_ATA_ID_CFSSE 84 +#define RT_AHCI_ATA_ID_CFS_ENABLE_1 85 +#define RT_AHCI_ATA_ID_CFS_ENABLE_2 86 +#define RT_AHCI_ATA_ID_CSF_DEFAULT 87 +#define RT_AHCI_ATA_ID_UDMA_MODES 88 +#define RT_AHCI_ATA_ID_HW_CONFIG 93 +#define RT_AHCI_ATA_ID_SPG 98 +#define RT_AHCI_ATA_ID_LBA_CAPACITY_2 100 +#define RT_AHCI_ATA_ID_SECTOR_SIZE 106 +#define RT_AHCI_ATA_ID_WWN 108 +#define RT_AHCI_ATA_ID_LOGICAL_SECTOR_SIZE 117 +#define RT_AHCI_ATA_ID_COMMAND_SET_3 119 +#define RT_AHCI_ATA_ID_COMMAND_SET_4 120 +#define RT_AHCI_ATA_ID_LAST_LUN 126 +#define RT_AHCI_ATA_ID_DLF 128 +#define RT_AHCI_ATA_ID_CSFO 129 +#define RT_AHCI_ATA_ID_CFA_POWER 160 +#define RT_AHCI_ATA_ID_CFA_KEY_MGMT 162 +#define RT_AHCI_ATA_ID_CFA_MODES 163 +#define RT_AHCI_ATA_ID_DATA_SET_MGMT 169 +#define RT_AHCI_ATA_ID_SCT_CMD_XPORT 206 +#define RT_AHCI_ATA_ID_ROT_SPEED 217 +#define RT_AHCI_ATA_ID_PIO4 (1 << 1) +#define RT_AHCI_ATA_ID_SERNO_LEN 20 +#define RT_AHCI_ATA_ID_FW_REV_LEN 8 +#define RT_AHCI_ATA_ID_PROD_LEN 40 +#define RT_AHCI_ATA_ID_WWN_LEN 8 + +#define RT_AHCI_ATA_CMD_DSM 0x06 +#define RT_AHCI_ATA_CMD_DEV_RESET 0x08 /* ATAPI device reset */ +#define RT_AHCI_ATA_CMD_PIO_READ 0x20 /* Read sectors with retry */ +#define RT_AHCI_ATA_CMD_PIO_READ_EXT 0x24 +#define RT_AHCI_ATA_CMD_READ_EXT 0x25 +#define RT_AHCI_ATA_CMD_READ_NATIVE_MAX_EXT 0x27 +#define RT_AHCI_ATA_CMD_READ_MULTI_EXT 0x29 +#define RT_AHCI_ATA_CMD_READ_LOG_EXT 0x2f +#define RT_AHCI_ATA_CMD_PIO_WRITE 0x30 /* Write sectors with retry */ +#define RT_AHCI_ATA_CMD_PIO_WRITE_EXT 0x34 +#define RT_AHCI_ATA_CMD_WRITE_EXT 0x35 +#define RT_AHCI_ATA_CMD_SET_MAX_EXT 0x37 +#define RT_AHCI_ATA_CMD_WRITE_MULTI_EXT 0x39 +#define RT_AHCI_ATA_CMD_WRITE_FUA_EXT 0x3d +#define RT_AHCI_ATA_CMD_VERIFY 0x40 /* Read verify sectors with retry */ +#define RT_AHCI_ATA_CMD_VERIFY_EXT 0x42 +#define RT_AHCI_ATA_CMD_FPDMA_READ 0x60 +#define RT_AHCI_ATA_CMD_FPDMA_WRITE 0x61 +#define RT_AHCI_ATA_CMD_EDD 0x90 /* Execute device diagnostic */ +#define RT_AHCI_ATA_CMD_INIT_DEV_PARAMS 0x91 /* Initialize device parameters */ +#define RT_AHCI_ATA_CMD_PACKET 0xa0 /* ATAPI packet */ +#define RT_AHCI_ATA_CMD_ID_ATAPI 0xa1 /* ATAPI identify device */ +#define RT_AHCI_ATA_CMD_CONF_OVERLAY 0xb1 +#define RT_AHCI_ATA_CMD_READ_MULTI 0xc4 /* Read multiple */ +#define RT_AHCI_ATA_CMD_WRITE_MULTI 0xc5 /* Write multiple */ +#define RT_AHCI_ATA_CMD_SET_MULTI 0xc6 /* Set multiple mode */ +#define RT_AHCI_ATA_CMD_READ 0xc8 /* Read DMA with retry */ +#define RT_AHCI_ATA_CMD_WRITE 0xca /* Write DMA with retry */ +#define RT_AHCI_ATA_CMD_WRITE_MULTI_FUA_EXT 0xce +#define RT_AHCI_ATA_CMD_STANDBYNOW1 0xe0 /* Standby immediate */ +#define RT_AHCI_ATA_CMD_IDLEIMMEDIATE 0xe1 /* Idle immediate */ +#define RT_AHCI_ATA_CMD_STANDBY 0xe2 /* Place in standby power mode */ +#define RT_AHCI_ATA_CMD_IDLE 0xe3 /* Place in idle power mode */ +#define RT_AHCI_ATA_CMD_PMP_READ 0xe4 /* Read buffer */ +#define RT_AHCI_ATA_CMD_CHK_POWER 0xe5 /* Check power mode */ +#define RT_AHCI_ATA_CMD_SLEEP 0xe6 /* Sleep */ +#define RT_AHCI_ATA_CMD_FLUSH 0xe7 +#define RT_AHCI_ATA_CMD_PMP_WRITE 0xe8 /* Write buffer */ +#define RT_AHCI_ATA_CMD_FLUSH_EXT 0xea +#define RT_AHCI_ATA_CMD_ID_ATA 0xec /* Identify device */ +#define RT_AHCI_ATA_CMD_SET_FEATURES 0xef /* Set features */ +#define RT_AHCI_ATA_CMD_SEC_FREEZE_LOCK 0xf5 /* Security freeze */ +#define RT_AHCI_ATA_CMD_READ_NATIVE_MAX 0xf8 +#define RT_AHCI_ATA_CMD_SET_MAX 0xf9 + +#define RT_AHCI_ATA_DSM_TRIM 0x01 + +#define RT_AHCI_ATA_PROT_FLAG_PIO RT_BIT(0) +#define RT_AHCI_ATA_PROT_FLAG_DMA RT_BIT(1) +#define RT_AHCI_ATA_PROT_FLAG_NCQ RT_BIT(2) +#define RT_AHCI_ATA_PROT_FLAG_ATAPI RT_BIT(3) + +#define rt_ahci_ata_id_is_ata(id) (((id)[0] & (1 << 15)) == 0) +#define rt_ahci_ata_id_has_lba(id) ((id)[49] & (1 << 9)) +#define rt_ahci_ata_id_has_dma(id) ((id)[49] & (1 << 8)) +#define rt_ahci_ata_id_has_ncq(id) ((id)[76] & (1 << 8)) +#define rt_ahci_ata_id_queue_depth(id) (((id)[75] & 0x1f) + 1) +#define rt_ahci_ata_id_removeable(id) ((id)[0] & (1 << 7)) +#define rt_ahci_ata_id_iordy_disable(id) ((id)[49] & (1 << 10)) +#define rt_ahci_ata_id_has_iordy(id) ((id)[49] & (1 << 11)) + +#define rt_ahci_ata_id_u32(id, n) (((rt_uint32_t)(id)[(n) + 1] << 16) | ((rt_uint32_t) (id)[(n)])) +#define rt_ahci_ata_id_u64(id, n) (((rt_uint64_t)(id)[(n) + 3] << 48) | ((rt_uint64_t)(id)[(n) + 2] << 32) | \ + ((rt_uint64_t)(id)[(n) + 1] << 16) | ((rt_uint64_t)(id)[(n) + 0]) ) + +rt_inline rt_bool_t rt_ahci_ata_id_has_lba48(const rt_uint16_t *id) +{ + if ((id[RT_AHCI_ATA_ID_COMMAND_SET_2] & 0xc000) != 0x4000 || + !rt_ahci_ata_id_u64(id, RT_AHCI_ATA_ID_LBA_CAPACITY_2)) + { + return 0; + } + + return !!(id[RT_AHCI_ATA_ID_COMMAND_SET_2] & (1 << 10)); +} + +rt_inline rt_uint64_t rt_ahci_ata_id_n_sectors(rt_uint16_t *id) +{ + if (rt_ahci_ata_id_has_lba(id)) + { + if (rt_ahci_ata_id_has_lba48(id)) + { + return rt_ahci_ata_id_u64(id, RT_AHCI_ATA_ID_LBA_CAPACITY_2); + } + + return rt_ahci_ata_id_u32(id, RT_AHCI_ATA_ID_LBA_CAPACITY); + } + + return 0; +} + +rt_inline rt_bool_t rt_ahci_ata_id_wcache_enabled(const rt_uint16_t *id) +{ + if ((id[RT_AHCI_ATA_ID_CSF_DEFAULT] & 0xc000) != 0x4000) + { + return RT_FALSE; + } + return id[RT_AHCI_ATA_ID_CFS_ENABLE_1] & (1 << 5); +} + +rt_inline rt_bool_t rt_ahci_ata_id_has_flush(const rt_uint16_t *id) +{ + if ((id[RT_AHCI_ATA_ID_COMMAND_SET_2] & 0xc000) != 0x4000) + { + return RT_FALSE; + } + return id[RT_AHCI_ATA_ID_COMMAND_SET_2] & (1 << 12); +} + +rt_inline rt_bool_t rt_ahci_ata_id_has_flush_ext(const rt_uint16_t *id) +{ + if ((id[RT_AHCI_ATA_ID_COMMAND_SET_2] & 0xc000) != 0x4000) + { + return RT_FALSE; + } + return id[RT_AHCI_ATA_ID_COMMAND_SET_2] & (1 << 13); +} + +struct rt_ahci_cmd_hdr +{ + rt_uint32_t opts; + rt_uint32_t status; + rt_uint32_t tbl_addr_lo; + rt_uint32_t tbl_addr_hi; + rt_uint32_t reserved[4]; +}; + +struct rt_ahci_sg +{ + rt_uint32_t addr_lo; + rt_uint32_t addr_hi; + rt_uint32_t reserved; + rt_uint32_t flags_size; +}; + +struct rt_ahci_port +{ + void *regs; + + void *dma; + rt_ubase_t dma_handle; + + struct rt_ahci_cmd_hdr *cmd_slot; + struct rt_ahci_sg *cmd_tbl_sg; + void *cmd_tbl; + rt_ubase_t cmd_tbl_dma; + void *rx_fis; + + rt_uint32_t int_enabled; + rt_size_t block_size; + + rt_uint16_t *ataid; + + rt_bool_t link; + struct rt_completion done; +}; + +struct rt_ahci_host +{ + struct rt_scsi_host parent; + + int irq; + void *regs; + + rt_size_t ports_nr; + rt_uint32_t ports_map; + struct rt_ahci_port ports[32]; + + rt_uint32_t cap; + rt_uint32_t max_blocks; + + const struct rt_ahci_ops *ops; +}; + +struct rt_ahci_ops +{ + rt_err_t (*host_init)(struct rt_ahci_host *host); + rt_err_t (*port_init)(struct rt_ahci_host *host, struct rt_ahci_port *port); + rt_err_t (*port_link_up)(struct rt_ahci_host *host, struct rt_ahci_port *port); + rt_err_t (*port_dma_init)(struct rt_ahci_host *host, struct rt_ahci_port *port); + rt_err_t (*port_isr)(struct rt_ahci_host *host, struct rt_ahci_port *port, rt_uint32_t isr); +}; + +rt_err_t rt_ahci_host_register(struct rt_ahci_host *host); +rt_err_t rt_ahci_host_unregister(struct rt_ahci_host *host); + +#endif /* __AHCI_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/blk.h b/rt-thread/components/drivers/include/drivers/blk.h new file mode 100644 index 0000000..42159c4 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/blk.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI first version + */ + +#ifndef __BLK_H__ +#define __BLK_H__ + +#include +#include +#include + +struct rt_dm_ida; +struct rt_blk_device; +struct rt_blk_disk_ops; + +struct rt_blk_disk +{ + struct rt_device parent; + + const struct rt_blk_disk_ops *ops; +#ifdef RT_USING_DM + struct rt_dm_ida *ida; +#endif + + rt_uint32_t read_only:1; + rt_uint32_t parallel_io:1; + rt_uint32_t removable:1; +#define RT_BLK_DISK_MAGIC 0xbdaabdaa + rt_uint32_t __magic; + + rt_uint32_t partitions; +#define RT_BLK_PARTITION_NONE (-1) +#define RT_BLK_PARTITION_MAX (RT_UINT32_MAX >> 1) + rt_int32_t max_partitions; + rt_list_t part_nodes; + + struct rt_spinlock lock; + struct rt_semaphore usr_lock; +}; + +struct rt_blk_disk_ops +{ + rt_ssize_t (*read)(struct rt_blk_disk *disk, rt_off_t sector, void *buffer, + rt_size_t sector_count); + rt_ssize_t (*write)(struct rt_blk_disk *disk, rt_off_t sector, const void *buffer, + rt_size_t sector_count); + rt_err_t (*getgeome)(struct rt_blk_disk *disk, struct rt_device_blk_geometry *geometry); + rt_err_t (*sync)(struct rt_blk_disk *disk); + rt_err_t (*erase)(struct rt_blk_disk *disk); + rt_err_t (*autorefresh)(struct rt_blk_disk *disk, rt_bool_t is_auto); + rt_err_t (*control)(struct rt_blk_disk *disk, struct rt_blk_device *blk, int cmd, void *args); +}; + +#ifndef __DFS_H__ +#include + +struct rt_blk_device +{ + struct rt_device parent; + + int partno; + struct dfs_partition partition; + + rt_list_t list; + struct rt_blk_disk *disk; + + rt_size_t sector_start; + rt_size_t sector_count; +}; +#else +struct rt_blk_device; +#endif /* __DFS_H__ */ + +rt_err_t rt_hw_blk_disk_register(struct rt_blk_disk *disk); +rt_err_t rt_hw_blk_disk_unregister(struct rt_blk_disk *disk); + +rt_err_t rt_blk_disk_probe_partition(struct rt_blk_disk *disk); +rt_ssize_t rt_blk_disk_get_capacity(struct rt_blk_disk *disk); +rt_ssize_t rt_blk_disk_get_logical_block_size(struct rt_blk_disk *disk); + +#endif /* __BLK_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/clk.h b/rt-thread/components/drivers/include/drivers/clk.h index 83662d7..97491bf 100644 --- a/rt-thread/components/drivers/include/drivers/clk.h +++ b/rt-thread/components/drivers/include/drivers/clk.h @@ -16,6 +16,8 @@ #include #include +#define RT_CLK_NODE_OBJ_NAME "CLKNP" + struct rt_clk_ops; struct rt_reset_control_node; @@ -37,6 +39,8 @@ struct rt_clk_node * }; * We assume the 'N' is the max value of element in 'clock-indices' if OFW. */ + struct rt_object rt_parent; + rt_list_t list; rt_list_t children_nodes; @@ -74,6 +78,8 @@ struct rt_clk const char *con_id; rt_ubase_t rate; + int prepare_count; + int enable_count; void *fw_node; void *priv; diff --git a/rt-thread/components/drivers/include/drivers/core/dm.h b/rt-thread/components/drivers/include/drivers/core/dm.h index 94821fe..1a3723a 100644 --- a/rt-thread/components/drivers/include/drivers/core/dm.h +++ b/rt-thread/components/drivers/include/drivers/core/dm.h @@ -13,9 +13,11 @@ #include #include +#include #include #include #include +#include #ifndef RT_CPUS_NR #define RT_CPUS_NR 1 @@ -27,6 +29,24 @@ extern int rt_hw_cpu_id(void); void rt_dm_secondary_cpu_init(void); +/* ID Allocation */ +struct rt_dm_ida +{ + rt_uint8_t master_id; + +#define RT_DM_IDA_NUM 256 + RT_BITMAP_DECLARE(map, RT_DM_IDA_NUM); + struct rt_spinlock lock; +}; + +#define RT_DM_IDA_INIT(id) { .master_id = MASTER_ID_##id } + +int rt_dm_ida_alloc(struct rt_dm_ida *ida); +rt_bool_t rt_dm_ida_take(struct rt_dm_ida *ida, int id); +void rt_dm_ida_free(struct rt_dm_ida *ida, int id); + +rt_device_t rt_dm_device_find(int master_id, int device_id); + int rt_dm_dev_set_name_auto(rt_device_t dev, const char *prefix); int rt_dm_dev_get_name_id(rt_device_t dev); diff --git a/rt-thread/components/drivers/include/drivers/core/master_id.h b/rt-thread/components/drivers/include/drivers/core/master_id.h new file mode 100644 index 0000000..90f2699 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/core/master_id.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-04-20 GuEe-GUI the first version + */ + +#ifndef __RT_DM_MASTER_ID_H__ +#define __RT_DM_MASTER_ID_H__ + +#define MASTER_ID_CUSTOM 0 + +/* Block */ +#define MASTER_ID_NVME 1 +#define MASTER_ID_SCSI_SD 2 +#define MASTER_ID_SCSI_CDROM 3 +#define MASTER_ID_SDIO 4 +#define MASTER_ID_VIRTUAL_BLOCK 5 + +/* Char */ +#define MASTER_ID_RPMSG_EPT 11 +#define MASTER_ID_RPMSG_CHAR 12 +#define MASTER_ID_SERIAL 13 + +/* Clock Timer */ +#define MASTER_ID_HWTIMER 21 +#define MASTER_ID_PTP 22 +#define MASTER_ID_RTC 23 + +/* Graphic Display */ +#define MASTER_ID_GRAPHIC_BACKLIGHT 31 +#define MASTER_ID_GRAPHIC_FRAMEBUFFER 32 +#define MASTER_ID_LED 33 + +/* Hardware Monitor */ +#define MASTER_ID_DVFS 41 +#define MASTER_ID_SENSOR 42 +#define MASTER_ID_THERMAL 43 +#define MASTER_ID_WATCHDOG 44 + +/* I2C */ +#define MASTER_ID_I2C_BUS 51 +#define MASTER_ID_I2C_DEV 52 + +/* IO Contorl */ +#define MASTER_ID_ADC 61 +#define MASTER_ID_DAC 62 +#define MASTER_ID_PIN 63 +#define MASTER_ID_PWM 64 + +/* Memory */ +#define MASTER_ID_MEM 71 +#define MASTER_ID_MTD 72 + +/* MISC */ +#define MASTER_ID_MISC 81 + +/* Multimedia */ +#define MASTER_ID_AUDIO 91 + +/* Net */ +#define MASTER_ID_CAN 101 +#define MASTER_ID_ETH 102 +#define MASTER_ID_PHY 103 +#define MASTER_ID_WLAN 104 + +/* Input */ +#define MASTER_ID_INPUT 111 +#define MASTER_ID_TOUCH 112 + +/* Security */ +#define MASTER_ID_HWCRYPTO 121 +#define MASTER_ID_RNG 122 +#define MASTER_ID_TEE 123 + +/* SPI */ +#define MASTER_ID_SPI_BUS 131 +#define MASTER_ID_SPI_DEV 132 + +/* TTY */ +#define MASTER_ID_TTY 141 +#define MASTER_ID_TTY_SLAVES 142 +#define MASTER_ID_TTY_ALTERNATE 143 +#define MASTER_ID_PTMX 144 + +/* USB */ +#define MASTER_ID_USB_DEV 151 +#define MASTER_ID_USB_BUS 152 +#define MASTER_ID_USB_OTG 153 + +#endif /* __RT_DM_MASTER_ID_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/cputime.h b/rt-thread/components/drivers/include/drivers/cputime.h index 3b1eb2a..478ccfd 100644 --- a/rt-thread/components/drivers/include/drivers/cputime.h +++ b/rt-thread/components/drivers/include/drivers/cputime.h @@ -31,4 +31,8 @@ uint64_t clock_cpu_millisecond(uint64_t cpu_tick); int clock_cpu_setops(const struct rt_clock_cputime_ops *ops); +#ifdef RT_USING_CPUTIME_RISCV +int riscv_cputime_init(void); +#endif /* RT_USING_CPUTIME_RISCV */ + #endif diff --git a/rt-thread/components/drivers/include/drivers/dac.h b/rt-thread/components/drivers/include/drivers/dac.h index c03fa10..b1360c3 100644 --- a/rt-thread/components/drivers/include/drivers/dac.h +++ b/rt-thread/components/drivers/include/drivers/dac.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,8 +11,66 @@ #ifndef __DAC_H__ #define __DAC_H__ #include +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup DAC DAC + * + * @brief DAC driver api + * + * Example + * @code {.c} + * + * #include + * #include + * #include + * #define DAC_DEV_NAME "dac1" + * #define DAC_DEV_CHANNEL 1 + * #define REFER_VOLTAGE 330 + * #define CONVERT_BITS (1 << 12) + * + * static int dac_vol_sample(int argc, char *argv[]) + * { + * rt_dac_device_t dac_dev; + * rt_uint32_t value, vol; + * rt_err_t ret = RT_EOK; + * + * dac_dev = (rt_dac_device_t)rt_device_find(DAC_DEV_NAME); + * if (dac_dev == RT_NULL) + * { + * rt_kprintf("dac sample run failed! can't find %s device!\n", DAC_DEV_NAME); + * return -RT_ERROR; + * } + * + * ret = rt_dac_enable(dac_dev, DAC_DEV_CHANNEL); + * + * value = atoi(argv[1]); + * rt_dac_write(dac_dev, DAC_DEV_NAME, DAC_DEV_CHANNEL, value); + * rt_kprintf("the value is :%d \n", value); + * + * vol = value * REFER_VOLTAGE / CONVERT_BITS; + * rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); + * + * rt_thread_mdelay(500); + * + * ret = rt_dac_disable(dac_dev, DAC_DEV_CHANNEL); + * + * return ret; + * } + * MSH_CMD_EXPORT(dac_vol_sample, dac voltage convert sample); + * + * @endcode + * + * @ingroup Drivers + */ +/*! + * @addtogroup DAC + * @{ + */ struct rt_dac_device; +/** + * @brief Configuration of DAC device + */ struct rt_dac_ops { rt_err_t (*disabled)(struct rt_dac_device *device, rt_uint32_t channel); @@ -20,7 +78,10 @@ struct rt_dac_ops rt_err_t (*convert)(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value); rt_uint8_t (*get_resolution)(struct rt_dac_device *device); }; - +/** + * @brief DAC device structure + * + */ struct rt_dac_device { struct rt_device parent; @@ -35,10 +96,41 @@ typedef enum RT_DAC_CMD_GET_RESOLUTION = RT_DEVICE_CTRL_BASE(DAC) + 2, } rt_dac_cmd_t; +/** + * @brief Register a DAC device + * @param dac DAC device + * @param name DAC name + * @param ops the operations of DAC device + * @param user_data device private data + * @return rt_err_t error code + */ rt_err_t rt_hw_dac_register(rt_dac_device_t dac,const char *name, const struct rt_dac_ops *ops, const void *user_data); +/** + * @brief set the value of DAC + * @param dev DAC device + * @param channel DAC channel + * @param value the value of DAC + * @return rt_err_t error code + */ rt_err_t rt_dac_write(rt_dac_device_t dev, rt_uint32_t channel, rt_uint32_t value); + +/** + * @brief enable the DAC channel + * @param dev DAC device + * @param channel DAC channel + * @return rt_err_t error code + */ rt_err_t rt_dac_enable(rt_dac_device_t dev, rt_uint32_t channel); + +/** + * @brief disable the DAC channel + * @param dev DAC device + * @param channel DAC channel + * @return rt_err_t error code + */ rt_err_t rt_dac_disable(rt_dac_device_t dev, rt_uint32_t channel); +/*! @}*/ + #endif /* __dac_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/alarm.h b/rt-thread/components/drivers/include/drivers/dev_alarm.h similarity index 96% rename from rt-thread/components/drivers/include/drivers/alarm.h rename to rt-thread/components/drivers/include/drivers/dev_alarm.h index 864933d..4553569 100644 --- a/rt-thread/components/drivers/include/drivers/alarm.h +++ b/rt-thread/components/drivers/include/drivers/dev_alarm.h @@ -10,8 +10,8 @@ * 2020-10-15 zhangsz add alarm flags hour minute second. */ -#ifndef __ALARM_H__ -#define __ALARM_H__ +#ifndef __DEV_ALARM_H__ +#define __DEV_ALARM_H__ #include #include @@ -72,4 +72,4 @@ rt_err_t rt_alarm_start(rt_alarm_t alarm); rt_err_t rt_alarm_stop(rt_alarm_t alarm); int rt_alarm_system_init(void); -#endif /* __ALARM_H__ */ +#endif /* __DEV_ALARM_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/audio.h b/rt-thread/components/drivers/include/drivers/dev_audio.h similarity index 98% rename from rt-thread/components/drivers/include/drivers/audio.h rename to rt-thread/components/drivers/include/drivers/dev_audio.h index 6d98272..ef92a93 100644 --- a/rt-thread/components/drivers/include/drivers/audio.h +++ b/rt-thread/components/drivers/include/drivers/dev_audio.h @@ -10,10 +10,10 @@ * */ -#ifndef __AUDIO_H__ -#define __AUDIO_H__ +#ifndef __DEV_AUDIO_H__ +#define __DEV_AUDIO_H__ -#include "audio_pipe.h" +#include "dev_audio_pipe.h" /* AUDIO command */ #define _AUDIO_CTL(a) (RT_DEVICE_CTRL_BASE(Sound) + a) @@ -173,4 +173,4 @@ void rt_audio_rx_done(struct rt_audio_device *audio, rt_uint8_t *pbuf, rt #define CODEC_VOLUME_MAX (63) -#endif /* __AUDIO_H__ */ +#endif /* __DEV_AUDIO_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/can.h b/rt-thread/components/drivers/include/drivers/dev_can.h similarity index 65% rename from rt-thread/components/drivers/include/drivers/can.h rename to rt-thread/components/drivers/include/drivers/dev_can.h index 2ce60d8..aed78b2 100644 --- a/rt-thread/components/drivers/include/drivers/can.h +++ b/rt-thread/components/drivers/include/drivers/dev_can.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,8 +10,8 @@ * 2022-05-08 hpmicro add CANFD support, fixed typos */ -#ifndef CAN_H_ -#define CAN_H_ +#ifndef __DEV_CAN_H_ +#define __DEV_CAN_H_ #include @@ -63,12 +63,157 @@ enum CANBAUD #define RT_CAN_MODE_PRIV 0x01 #define RT_CAN_MODE_NOPRIV 0x00 -/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number - * @{ - */ +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup CAN_Device CAN Driver + * + * @brief CAN driver api + * + * Example + * @code {.c} + * #include + * #include "rtdevice.h" + * + * #define CAN_DEV_NAME "can1" // CAN 设备名称 + * + * static struct rt_semaphore rx_sem; // 用于接收消息的信号量 + * static rt_device_t can_dev; // CAN 设备句柄 + * + * // 接收数据回调函数 + * static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size) + * { + * // CAN 接收到数据后产生中断，调用此回调函数，然后发送接收信号量 + * rt_sem_release(&rx_sem); + * + * return RT_EOK; + * } + * + * static void can_rx_thread(void *parameter) + * { + * int i; + * rt_err_t res; + * struct rt_can_msg rxmsg = {0}; + * + * // 设置接收回调函数 + * rt_device_set_rx_indicate(can_dev, can_rx_call); + * + * #ifdef RT_CAN_USING_HDR + * struct rt_can_filter_item items[5] = + * { + * RT_CAN_FILTER_ITEM_INIT(0x100, 0, 0, 0, 0x700, RT_NULL, RT_NULL), // std,match ID:0x100~0x1ff，hdr 为 - 1，设置默认过滤表 + * RT_CAN_FILTER_ITEM_INIT(0x300, 0, 0, 0, 0x700, RT_NULL, RT_NULL), // std,match ID:0x300~0x3ff，hdr 为 - 1 + * RT_CAN_FILTER_ITEM_INIT(0x211, 0, 0, 0, 0x7ff, RT_NULL, RT_NULL), // std,match ID:0x211，hdr 为 - 1 + * RT_CAN_FILTER_STD_INIT(0x486, RT_NULL, RT_NULL), // std,match ID:0x486，hdr 为 - 1 + * {0x555, 0, 0, 0, 0x7ff, 7,} // std,match ID:0x555，hdr 为 7，指定设置 7 号过滤表 + * }; + * struct rt_can_filter_config cfg = {5, 1, items}; // 一共有 5 个过滤表 + * // 设置硬件过滤表 + * res = rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg); + * RT_ASSERT(res == RT_EOK); + * #endif + * res = RT_TRUE; + * res = rt_device_control(can_dev, RT_CAN_CMD_START, &res); + * while (1) + * { + * // hdr 值为 - 1，表示直接从 uselist 链表读取数据 + * rxmsg.hdr = -1; + * // 阻塞等待接收信号量 + * rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + * // 从 CAN 读取一帧数据 + * rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg)); + * // 打印数据 ID 及内容 + * rt_kprintf("ID:%x", rxmsg.id); + * for (i = 0; i < 8; i++) + * { + * rt_kprintf("%2x", rxmsg.data[i]); + * } + * + * rt_kprintf("\n"); + * } + * } + * + * int can_sample(int argc, char *argv[]) + * { + * struct rt_can_msg msg = {0}; + * rt_err_t res; + * rt_size_t size; + * rt_thread_t thread; + * char can_name[RT_NAME_MAX]; + * + * if (argc == 2) + * { + * rt_strncpy(can_name, argv[1], RT_NAME_MAX); + * } + * else + * { + * rt_strncpy(can_name, CAN_DEV_NAME, RT_NAME_MAX); + * } + * // 查找 CAN 设备 + * can_dev = rt_device_find(can_name); + * if (!can_dev) + * { + * rt_kprintf("find %s failed!\n", can_name); + * return -RT_ERROR; + * } + * + * // 初始化 CAN 接收信号量 + * rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); + * + * // 以中断接收及发送方式打开 CAN 设备 + * res = rt_device_open(can_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX); + * RT_ASSERT(res == RT_EOK); + * // 创建数据接收线程 + * thread = rt_thread_create("can_rx", can_rx_thread, RT_NULL, 1024, 25, 10); + * if (thread != RT_NULL) + * { + * rt_thread_startup(thread); + * } + * else + * { + * rt_kprintf("create can_rx thread failed!\n"); + * } + * + * msg.id = 0x78; // ID 为 0x78 + * msg.ide = RT_CAN_STDID; // 标准格式 + * msg.rtr = RT_CAN_DTR; // 数据帧 + * msg.len = 8; // 数据长度为 8 + * // 待发送的 8 字节数据 + * msg.data[0] = 0x00; + * msg.data[1] = 0x11; + * msg.data[2] = 0x22; + * msg.data[3] = 0x33; + * msg.data[4] = 0x44; + * msg.data[5] = 0x55; + * msg.data[6] = 0x66; + * msg.data[7] = 0x77; + * // 发送一帧 CAN 数据 + * size = rt_device_write(can_dev, 0, &msg, sizeof(msg)); + * if (size == 0) + * { + * rt_kprintf("can dev write data failed!\n"); + * } + * + * return res; + * } + * // 导出到 msh 命令列表中 + * MSH_CMD_EXPORT(can_sample, can device sample); + * @endcode + * + * @ingroup Drivers + * + */ + + +/*! + * @addtogroup CAN_Device + * @{ + */ #define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ #define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ +/** + * @brief CAN filter item + */ struct rt_can_filter_item { rt_uint32_t id : 29; @@ -118,6 +263,10 @@ struct rt_can_filter_item RT_CAN_FILTER_ITEM_INIT(id,1,0,1,0xFFFFFFFF) #endif + +/** + * @brief CAN filter configuration + */ struct rt_can_filter_config { rt_uint32_t count; @@ -125,6 +274,9 @@ struct rt_can_filter_config struct rt_can_filter_item *items; }; +/** + * @brief CAN timing configuration + */ struct rt_can_bit_timing { rt_uint16_t prescaler; /* Pre-scaler */ @@ -135,8 +287,8 @@ struct rt_can_bit_timing }; /** - * CAN bit timing configuration list - * NOTE: + * @brief CAN bit timing configuration list + * @note * items[0] always for CAN2.0/CANFD Arbitration Phase * items[1] always for CANFD (if it exists) */ @@ -146,6 +298,10 @@ struct rt_can_bit_timing_config struct rt_can_bit_timing *items; }; + +/** + * @brief CAN configuration + */ struct can_configure { rt_uint32_t baud_rate; @@ -190,6 +346,7 @@ struct rt_can_ops; #define RT_CAN_CMD_SET_CANFD 0x1A #define RT_CAN_CMD_SET_BAUD_FD 0x1B #define RT_CAN_CMD_SET_BITTIMING 0x1C +#define RT_CAN_CMD_START 0x1D #define RT_DEVICE_CAN_INT_ERR 0x1000 @@ -211,6 +368,9 @@ enum RT_CAN_BUS_ERR RT_CAN_BUS_CRC_ERR = 6, }; +/** + * @brief CAN status + */ struct rt_can_status { rt_uint32_t rcverrcnt; @@ -241,6 +401,7 @@ struct rt_can_hdr #endif struct rt_can_device; typedef rt_err_t (*rt_canstatus_ind)(struct rt_can_device *, void *); + typedef struct rt_can_status_ind_type { rt_canstatus_ind ind; @@ -347,6 +508,9 @@ struct rt_can_tx_fifo struct rt_list_node freelist; }; +/** + * @brief CAN operators + */ struct rt_can_ops { rt_err_t (*configure)(struct rt_can_device *can, struct can_configure *cfg); @@ -355,10 +519,29 @@ struct rt_can_ops rt_ssize_t (*recvmsg)(struct rt_can_device *can, void *buf, rt_uint32_t boxno); }; +/** + * @brief Register a CAN device to device list + * + * @param can the CAN device object + * @param name the name of CAN device + * @param ops the CAN device operators + * @param data the private data of CAN device + * + * @return the error code, RT_EOK on successfully + */ rt_err_t rt_hw_can_register(struct rt_can_device *can, const char *name, const struct rt_can_ops *ops, void *data); -void rt_hw_can_isr(struct rt_can_device *can, int event); -#endif /*_CAN_H*/ +/** + * @brief CAN interrupt service routine + * + * @param can the CAN device + * @param event the event mask + */ +void rt_hw_can_isr(struct rt_can_device *can, int event); + +/*! @}*/ + +#endif /*__DEV_CAN_H*/ diff --git a/rt-thread/components/drivers/include/drivers/dev_i2c.h b/rt-thread/components/drivers/include/drivers/dev_i2c.h new file mode 100644 index 0000000..dea75d2 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/dev_i2c.h @@ -0,0 +1,401 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-04-25 weety first version + * 2021-04-20 RiceChen added support for bus control api + */ + +#ifndef __DEV_I2C_H__ +#define __DEV_I2C_H__ + +#include +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup I2C I2C + * + * @brief I2C driver api + * + * Example + * @code {.c} + * #include + * #include + * + * #define AHT10_I2C_BUS_NAME "i2c1" // 传感器连接的I2C总线设备名称 + * #define AHT10_ADDR 0x38 // 从机地址 + * #define AHT10_CALIBRATION_CMD 0xE1 // 校准命令 + * #define AHT10_NORMAL_CMD 0xA8 // 一般命令 + * #define AHT10_GET_DATA 0xAC // 获取数据命令 + * + * static struct rt_i2c_bus_device *i2c_bus = RT_NULL; // I2C总线设备句柄 + * static rt_bool_t initialized = RT_FALSE; // 传感器初始化状态 + * + * // 写传感器寄存器 + * static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data) + * { + * rt_uint8_t buf[3]; + * struct rt_i2c_msg msgs; + * rt_uint32_t buf_size = 1; + * + * buf[0] = reg; //cmd + * if (data != RT_NULL) + * { + * buf[1] = data[0]; + * buf[2] = data[1]; + * buf_size = 3; + * } + * + * msgs.addr = AHT10_ADDR; + * msgs.flags = RT_I2C_WR; + * msgs.buf = buf; + * msgs.len = buf_size; + * + * // 调用I2C设备接口传输数据 + * if (rt_i2c_transfer(bus, &msgs, 1) == 1) + * { + * return RT_EOK; + * } + * else + * { + * return -RT_ERROR; + * } + * } + * + * // 读传感器寄存器数据 + * static rt_err_t read_regs(struct rt_i2c_bus_device *bus, rt_uint8_t len, rt_uint8_t *buf) + * { + * struct rt_i2c_msg msgs; + * + * msgs.addr = AHT10_ADDR; + * msgs.flags = RT_I2C_RD; + * msgs.buf = buf; + * msgs.len = len; + * + * // 调用I2C设备接口传输数据 + * if (rt_i2c_transfer(bus, &msgs, 1) == 1) + * { + * return RT_EOK; + * } + * else + * { + * return -RT_ERROR; + * } + * } + * + * static void read_temp_humi(float *cur_temp, float *cur_humi) + * { + * rt_uint8_t temp[6]; + * + * write_reg(i2c_bus, AHT10_GET_DATA, RT_NULL); // 发送命令 + * rt_thread_mdelay(400); + * read_regs(i2c_bus, 6, temp); // 获取传感器数据 + * + * // 湿度数据转换 + * *cur_humi = (temp[1] << 12 | temp[2] << 4 | (temp[3] & 0xf0) >> 4) * 100.0 / (1 << 20); + * // 温度数据转换 + * *cur_temp = ((temp[3] & 0xf) << 16 | temp[4] << 8 | temp[5]) * 200.0 / (1 << 20) - 50; + * } + * + * static void aht10_init(const char *name) + * { + * rt_uint8_t temp[2] = {0, 0}; + * + * // 查找I2C总线设备，获取I2C总线设备句柄 + * i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name); + * + * if (i2c_bus == RT_NULL) + * { + * rt_kprintf("can't find %s device!\n", name); + * } + * else + * { + * write_reg(i2c_bus, AHT10_NORMAL_CMD, temp); + * rt_thread_mdelay(400); + * + * temp[0] = 0x08; + * temp[1] = 0x00; + * write_reg(i2c_bus, AHT10_CALIBRATION_CMD, temp); + * rt_thread_mdelay(400); + * initialized = RT_TRUE; + * } + * } + * + * static void i2c_aht10_sample(int argc, char *argv[]) + * { + * float humidity, temperature; + * char name[RT_NAME_MAX]; + * + * humidity = 0.0; + * temperature = 0.0; + * + * if (argc == 2) + * { + * rt_strncpy(name, argv[1], RT_NAME_MAX); + * } + * else + * { + * rt_strncpy(name, AHT10_I2C_BUS_NAME, RT_NAME_MAX); + * } + * + * if (!initialized) + * { + * // 传感器初始化 + * aht10_init(name); + * } + * if (initialized) + * { + * // 读取温湿度数据 + * read_temp_humi(&temperature, &humidity); + * + * rt_kprintf("read aht10 sensor humidity : %d.%d %%\n", (int)humidity, (int)(humidity * 10) % 10); + * if( temperature >= 0 ) + * { + * rt_kprintf("read aht10 sensor temperature: %d.%d°C\n", (int)temperature, (int)(temperature * 10) % 10); + * } + * else + * { + * rt_kprintf("read aht10 sensor temperature: %d.%d°C\n", (int)temperature, (int)(-temperature * 10) % 10); + * } + * } + * else + * { + * rt_kprintf("initialize sensor failed!\n"); + * } + * } + * // 导出到 msh 命令列表中 + * MSH_CMD_EXPORT(i2c_aht10_sample, i2c aht10 sample); + * @endcode + * + * @ingroup Drivers + */ + +/*! + * @addtogroup I2C + * @{ + */ +#ifdef __cplusplus +extern "C" { +#endif + +#define RT_I2C_WR 0x0000 /*!< i2c wirte flag */ +#define RT_I2C_RD (1u << 0) /*!< i2c read flag */ +#define RT_I2C_ADDR_10BIT (1u << 2) /*!< this is a ten bit chip address */ +#define RT_I2C_NO_START (1u << 4) /*!< do not generate START condition */ +#define RT_I2C_IGNORE_NACK (1u << 5) /*!< ignore NACK from slave */ +#define RT_I2C_NO_READ_ACK (1u << 6) /* when I2C reading, we do not ACK */ +#define RT_I2C_NO_STOP (1u << 7) /*!< do not generate STOP condition */ + +#define RT_I2C_DEV_CTRL_10BIT (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x01) +#define RT_I2C_DEV_CTRL_ADDR (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x02) +#define RT_I2C_DEV_CTRL_TIMEOUT (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x03) +#define RT_I2C_DEV_CTRL_RW (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x04) +#define RT_I2C_DEV_CTRL_CLK (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x05) +#define RT_I2C_DEV_CTRL_UNLOCK (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x06) +#define RT_I2C_DEV_CTRL_GET_STATE (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x07) +#define RT_I2C_DEV_CTRL_GET_MODE (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x08) +#define RT_I2C_DEV_CTRL_GET_ERROR (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x09) + +/** + * @brief I2C Private Data + */ +struct rt_i2c_priv_data +{ + struct rt_i2c_msg *msgs; + rt_size_t number; +}; + +/** + * @brief I2C Message + */ +struct rt_i2c_msg +{ + rt_uint16_t addr; + rt_uint16_t flags; + rt_uint16_t len; + rt_uint8_t *buf; +}; + +struct rt_i2c_bus_device; + +/** + * @brief I2C Bus Device Operations + */ +struct rt_i2c_bus_device_ops +{ + rt_ssize_t (*master_xfer)(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num); + rt_ssize_t (*slave_xfer)(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num); + rt_err_t (*i2c_bus_control)(struct rt_i2c_bus_device *bus, + int cmd, + void *args); +}; + +/** + * @brief I2C Bus Device + */ +struct rt_i2c_bus_device +{ + struct rt_device parent; + const struct rt_i2c_bus_device_ops *ops; + rt_uint16_t flags; + struct rt_mutex lock; + rt_uint32_t timeout; + rt_uint32_t retries; + void *priv; +}; + +/** + * @brief I2C Client + */ +struct rt_i2c_client +{ +#ifdef RT_USING_DM + struct rt_device parent; + + const char *name; + const struct rt_i2c_device_id *id; + const struct rt_ofw_node_id *ofw_id; +#endif + struct rt_i2c_bus_device *bus; + rt_uint16_t client_addr; +}; + +#ifdef RT_USING_DM +struct rt_i2c_device_id +{ + char name[20]; + void *data; +}; + +struct rt_i2c_driver +{ + struct rt_driver parent; + + const struct rt_i2c_device_id *ids; + const struct rt_ofw_node_id *ofw_ids; + + rt_err_t (*probe)(struct rt_i2c_client *client); + rt_err_t (*remove)(struct rt_i2c_client *client); + rt_err_t (*shutdown)(struct rt_i2c_client *client); +}; + +rt_err_t rt_i2c_driver_register(struct rt_i2c_driver *driver); +rt_err_t rt_i2c_device_register(struct rt_i2c_client *client); + +#define RT_I2C_DRIVER_EXPORT(driver) RT_DRIVER_EXPORT(driver, i2c, BUILIN) +#endif /* RT_USING_DM */ + +/** + * @brief I2C Bus Device Initialization + * + * @param bus the I2C bus device + * @param name the name of I2C bus device + * + * @return rt_err_t error code + */ +rt_err_t rt_i2c_bus_device_device_init(struct rt_i2c_bus_device *bus, + const char *name); + +/** + * @brief I2C Bus Device Register + * + * @param bus the I2C bus device + * @param bus_name the name of I2C bus device + * + * @return rt_err_t error code + */ +rt_err_t rt_i2c_bus_device_register(struct rt_i2c_bus_device *bus, + const char *bus_name); + +/** + * @brief I2C Bus Device Find + * + * @param bus_name the name of I2C bus device + * + * @return rt_i2c_bus_device the I2C bus device + */ +struct rt_i2c_bus_device *rt_i2c_bus_device_find(const char *bus_name); + +/** + * @brief I2C data transmission. + * + * @param bus the I2C bus device + * @param msgs the I2C message list + * @param num the number of I2C message + * + * @return rt_ssize_t the actual length of transmitted + */ +rt_ssize_t rt_i2c_transfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num); + +/** + * @brief I2C Control + * + * @param bus the I2C bus device + * @param cmd the I2C control command + * @param args the I2C control arguments + * + * @return rt_err_t error code + */ +rt_err_t rt_i2c_control(struct rt_i2c_bus_device *bus, + int cmd, + void *args); + +/** + * @brief I2C Master Send + * + * @param bus the I2C bus device + * @param addr the I2C slave address + * @param flags the I2C flags + * @param buf the I2C send buffer + * @param count the I2C send buffer length + * + * @return rt_ssize_t the actual length of transmitted + */ +rt_ssize_t rt_i2c_master_send(struct rt_i2c_bus_device *bus, + rt_uint16_t addr, + rt_uint16_t flags, + const rt_uint8_t *buf, + rt_uint32_t count); + +/** + * @brief I2C Master Receive + * + * @param bus the I2C bus device + * @param addr the I2C slave address + * @param flags the I2C flags + * @param buf the I2C receive buffer + * @param count the I2C receive buffer length + * + * @return rt_ssize_t the actual length of received + */ +rt_ssize_t rt_i2c_master_recv(struct rt_i2c_bus_device *bus, + rt_uint16_t addr, + rt_uint16_t flags, + rt_uint8_t *buf, + rt_uint32_t count); + +rt_inline rt_err_t rt_i2c_bus_lock(struct rt_i2c_bus_device *bus, rt_tick_t timeout) +{ + return rt_mutex_take(&bus->lock, timeout); +} + +rt_inline rt_err_t rt_i2c_bus_unlock(struct rt_i2c_bus_device *bus) +{ + return rt_mutex_release(&bus->lock); +} + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif diff --git a/rt-thread/components/drivers/include/drivers/i2c-bit-ops.h b/rt-thread/components/drivers/include/drivers/dev_i2c_bit_ops.h similarity index 93% rename from rt-thread/components/drivers/include/drivers/i2c-bit-ops.h rename to rt-thread/components/drivers/include/drivers/dev_i2c_bit_ops.h index 2b4ea57..3c28714 100644 --- a/rt-thread/components/drivers/include/drivers/i2c-bit-ops.h +++ b/rt-thread/components/drivers/include/drivers/dev_i2c_bit_ops.h @@ -8,8 +8,8 @@ * 2012-04-25 weety first version */ -#ifndef __I2C_BIT_OPS_H__ -#define __I2C_BIT_OPS_H__ +#ifndef __DEV_I2C_BIT_OPS_H__ +#define __DEV_I2C_BIT_OPS_H__ #ifdef __cplusplus extern "C" { diff --git a/rt-thread/components/drivers/include/drivers/i2c_dm.h b/rt-thread/components/drivers/include/drivers/dev_i2c_dm.h similarity index 95% rename from rt-thread/components/drivers/include/drivers/i2c_dm.h rename to rt-thread/components/drivers/include/drivers/dev_i2c_dm.h index 4f5b251..c59d6e9 100644 --- a/rt-thread/components/drivers/include/drivers/i2c_dm.h +++ b/rt-thread/components/drivers/include/drivers/dev_i2c_dm.h @@ -8,8 +8,8 @@ * 2022-11-26 GuEe-GUI first version */ -#ifndef __I2C_DM_H__ -#define __I2C_DM_H__ +#ifndef __DEV_I2C_DM_H__ +#define __DEV_I2C_DM_H__ #include #include @@ -48,4 +48,4 @@ rt_inline rt_err_t i2c_timings_ofw_parse(struct rt_ofw_node *dev_np, struct i2c_ void i2c_bus_scan_clients(struct rt_i2c_bus_device *bus); -#endif /* __I2C_DM_H__ */ +#endif /* __DEV_I2C_DM_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/mmc.h b/rt-thread/components/drivers/include/drivers/dev_mmc.h similarity index 99% rename from rt-thread/components/drivers/include/drivers/mmc.h rename to rt-thread/components/drivers/include/drivers/dev_mmc.h index 88ee740..a537287 100644 --- a/rt-thread/components/drivers/include/drivers/mmc.h +++ b/rt-thread/components/drivers/include/drivers/dev_mmc.h @@ -9,8 +9,8 @@ * 2024-05-25 HPMicro add strobe support */ -#ifndef __MMC_H__ -#define __MMC_H__ +#ifndef __DEV_MMC_H__ +#define __DEV_MMC_H__ #include #include diff --git a/rt-thread/components/drivers/include/drivers/mmcsd_core.h b/rt-thread/components/drivers/include/drivers/dev_mmcsd_core.h similarity index 98% rename from rt-thread/components/drivers/include/drivers/mmcsd_core.h rename to rt-thread/components/drivers/include/drivers/dev_mmcsd_core.h index 3a6ac13..c86e9dd 100644 --- a/rt-thread/components/drivers/include/drivers/mmcsd_core.h +++ b/rt-thread/components/drivers/include/drivers/dev_mmcsd_core.h @@ -8,8 +8,8 @@ * 2011-07-25 weety first version */ -#ifndef __CORE_H__ -#define __CORE_H__ +#ifndef __DEV_MMCSD_CORE_H__ +#define __DEV_MMCSD_CORE_H__ #include #include @@ -249,8 +249,6 @@ struct rt_mmcsd_host *mmcsd_alloc_host(void); void mmcsd_free_host(struct rt_mmcsd_host *host); int rt_mmcsd_core_init(void); -int rt_mmcsd_blk_init(void); -rt_int32_t read_lba(struct rt_mmcsd_card *card, size_t lba, uint8_t *buffer, size_t count); rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card); void rt_mmcsd_blk_remove(struct rt_mmcsd_card *card); diff --git a/rt-thread/components/drivers/include/drivers/pin.h b/rt-thread/components/drivers/include/drivers/dev_pin.h similarity index 50% rename from rt-thread/components/drivers/include/drivers/pin.h rename to rt-thread/components/drivers/include/drivers/dev_pin.h index 22d4328..b1705ae 100644 --- a/rt-thread/components/drivers/include/drivers/pin.h +++ b/rt-thread/components/drivers/include/drivers/dev_pin.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,11 +9,72 @@ * 2017-10-20 ZYH add mode open drain and input pull down */ -#ifndef PIN_H__ -#define PIN_H__ +#ifndef DEV_PIN_H__ +#define DEV_PIN_H__ #include +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup Pin Pin + * + * @brief Pin driver api + * + * Example + * @code {.c} + * #include + * #include + * + * + * #ifndef BEEP_PIN_NUM + * #define BEEP_PIN_NUM 35 // PB0 + * #endif + * #ifndef KEY0_PIN_NUM + * #define KEY0_PIN_NUM 55 // PD8 + * #endif + * #ifndef KEY1_PIN_NUM + * #define KEY1_PIN_NUM 56 // PD9 + * #endif + * + * void beep_on(void *args) + * { + * rt_kprintf("turn on beep!\n"); + * + * rt_pin_write(BEEP_PIN_NUM, PIN_HIGH); + * } + * + * void beep_off(void *args) + * { + * rt_kprintf("turn off beep!\n"); + * + * rt_pin_write(BEEP_PIN_NUM, PIN_LOW); + * } + * + * static void pin_beep_sample(void) + * { + * rt_pin_mode(BEEP_PIN_NUM, PIN_MODE_OUTPUT); + * rt_pin_write(BEEP_PIN_NUM, PIN_LOW); + * + * rt_pin_mode(KEY0_PIN_NUM, PIN_MODE_INPUT_PULLUP); + * rt_pin_attach_irq(KEY0_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_on, RT_NULL); + * rt_pin_irq_enable(KEY0_PIN_NUM, PIN_IRQ_ENABLE); + * + * + * rt_pin_mode(KEY1_PIN_NUM, PIN_MODE_INPUT_PULLUP); + * rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_off, RT_NULL); + * rt_pin_irq_enable(KEY1_PIN_NUM, PIN_IRQ_ENABLE); + * } + * + * MSH_CMD_EXPORT(pin_beep_sample, pin beep sample); + * @endcode + * + * @ingroup Drivers + */ + +/*! + * @addtogroup Pin + * @{ + */ #ifdef __cplusplus extern "C" { #endif @@ -28,28 +89,38 @@ struct rt_pin_irqchip int irq; rt_base_t pin_range[2]; }; + +struct rt_pin_irq_hdr; #endif /* RT_USING_DM */ -/* pin device and operations for RT-Thread */ +/** + * @brief pin device structure + */ struct rt_device_pin { struct rt_device parent; #ifdef RT_USING_DM + /* MUST keep the order member after parent */ struct rt_pin_irqchip irqchip; + /* Fill by DM */ + rt_base_t pin_start; + rt_size_t pin_nr; + rt_list_t list; + struct rt_pin_irq_hdr *legacy_isr; #endif /* RT_USING_DM */ const struct rt_pin_ops *ops; }; #define PIN_NONE (-1) -#define PIN_LOW 0x00 -#define PIN_HIGH 0x01 +#define PIN_LOW 0x00 /*!< low level */ +#define PIN_HIGH 0x01 /*!< high level */ -#define PIN_MODE_OUTPUT 0x00 -#define PIN_MODE_INPUT 0x01 -#define PIN_MODE_INPUT_PULLUP 0x02 -#define PIN_MODE_INPUT_PULLDOWN 0x03 -#define PIN_MODE_OUTPUT_OD 0x04 +#define PIN_MODE_OUTPUT 0x00 /*!< output mode */ +#define PIN_MODE_INPUT 0x01 /*!< input mode */ +#define PIN_MODE_INPUT_PULLUP 0x02 /*!< input mode with pull-up */ +#define PIN_MODE_INPUT_PULLDOWN 0x03 /*!< input mode with pull-down */ +#define PIN_MODE_OUTPUT_OD 0x04 /*!< output mode with open-drain */ #ifdef RT_USING_PINCTRL enum @@ -84,29 +155,38 @@ enum }; #endif /* RT_USING_PINCTRL */ -#define PIN_IRQ_MODE_RISING 0x00 -#define PIN_IRQ_MODE_FALLING 0x01 -#define PIN_IRQ_MODE_RISING_FALLING 0x02 -#define PIN_IRQ_MODE_HIGH_LEVEL 0x03 -#define PIN_IRQ_MODE_LOW_LEVEL 0x04 +#define PIN_IRQ_MODE_RISING 0x00 /*!< rising edge trigger */ +#define PIN_IRQ_MODE_FALLING 0x01 /*!< falling edge trigger */ +#define PIN_IRQ_MODE_RISING_FALLING 0x02 /*!< rising and falling edge trigger */ +#define PIN_IRQ_MODE_HIGH_LEVEL 0x03 /*!< high level trigger */ +#define PIN_IRQ_MODE_LOW_LEVEL 0x04 /*!< low level trigger */ -#define PIN_IRQ_DISABLE 0x00 -#define PIN_IRQ_ENABLE 0x01 +#define PIN_IRQ_DISABLE 0x00 /*!< disable irq */ +#define PIN_IRQ_ENABLE 0x01 /*!< enable irq */ -#define PIN_IRQ_PIN_NONE PIN_NONE +#define PIN_IRQ_PIN_NONE PIN_NONE /*!< no pin irq */ +/** + * @brief pin mode structure + */ struct rt_device_pin_mode { rt_base_t pin; rt_uint8_t mode; /* e.g. PIN_MODE_OUTPUT */ }; +/** + * @brief pin value structure + */ struct rt_device_pin_value { rt_base_t pin; rt_uint8_t value; /* PIN_LOW or PIN_HIGH */ }; +/** + * @brief pin irq structure + */ struct rt_pin_irq_hdr { rt_base_t pin; @@ -116,6 +196,9 @@ struct rt_pin_irq_hdr }; #ifdef RT_USING_PINCTRL +/** + * @brief pin control configure structure + */ struct rt_pin_ctrl_conf_params { const char *propname; @@ -124,6 +207,9 @@ struct rt_pin_ctrl_conf_params }; #endif /* RT_USING_PINCTRL */ +/** + * @brief pin device operations + */ struct rt_pin_ops { void (*pin_mode)(struct rt_device *device, rt_base_t pin, rt_uint8_t mode); @@ -134,6 +220,7 @@ struct rt_pin_ops rt_err_t (*pin_detach_irq)(struct rt_device *device, rt_base_t pin); rt_err_t (*pin_irq_enable)(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled); rt_base_t (*pin_get)(const char *name); + rt_err_t (*pin_debounce)(struct rt_device *device, rt_base_t pin, rt_uint32_t debounce); #ifdef RT_USING_DM rt_err_t (*pin_irq_mode)(struct rt_device *device, rt_base_t pin, rt_uint8_t mode); rt_ssize_t (*pin_parse)(struct rt_device *device, struct rt_ofw_cell_args *args, rt_uint32_t *flags); @@ -143,16 +230,77 @@ struct rt_pin_ops #endif /* RT_USING_PINCTRL */ }; +/** + * @brief register a pin device + * @param name the name of pin device + * @param ops the operations of pin device + * @param user_data the user data of pin device + * @return int error code + */ int rt_device_pin_register(const char *name, const struct rt_pin_ops *ops, void *user_data); + +/** + * @brief set pin mode + * @param pin the pin number + * @param mode the pin mode + */ void rt_pin_mode(rt_base_t pin, rt_uint8_t mode); + +/** + * @brief write pin value + * @param pin the pin number + * @param value the pin value + */ void rt_pin_write(rt_base_t pin, rt_ssize_t value); + +/** + * @brief read pin value + * @param pin the pin number + * @return rt_ssize_t the pin value + */ rt_ssize_t rt_pin_read(rt_base_t pin); + +/** + * @brief get pin number by name + * @param name the pin name + * @return rt_base_t the pin number + */ rt_base_t rt_pin_get(const char *name); + +/** + * @brief bind the pin interrupt callback function + * @param pin the pin number + * @param mode the irq mode + * @param hdr the irq callback function + * @param args the argument of the callback function + * @return rt_err_t error code + */ rt_err_t rt_pin_attach_irq(rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args); + +/** + * @brief detach the pin interrupt callback function + * @param pin the pin number + * @return rt_err_t error code + */ rt_err_t rt_pin_detach_irq(rt_base_t pin); + +/** + * @brief enable or disable the pin interrupt + * @param pin the pin number + * @param enabled PIN_IRQ_ENABLE or PIN_IRQ_DISABLE + * @return rt_err_t error code + */ rt_err_t rt_pin_irq_enable(rt_base_t pin, rt_uint8_t enabled); +/** + * @brief set the pin's debounce time + * @param pin the pin number + * @param debounce time + * @return rt_err_t error code + */ +rt_err_t rt_pin_debounce(rt_base_t pin, rt_uint32_t debounce); + #ifdef RT_USING_DM rt_ssize_t rt_pin_get_named_pin(struct rt_device *dev, const char *propname, int index, rt_uint8_t *out_mode, rt_uint8_t *out_value); @@ -175,4 +323,6 @@ rt_err_t rt_pin_ctrl_confs_apply_by_name(struct rt_device *device, const char *n } #endif +/*! @}*/ + #endif diff --git a/rt-thread/components/drivers/include/drivers/dev_pwm.h b/rt-thread/components/drivers/include/drivers/dev_pwm.h new file mode 100644 index 0000000..1e0970f --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/dev_pwm.h @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-07 aozima the first version + * 2022-09-24 yuqi add phase and dead time configuration + */ + +#ifndef __DEV_PWM_H__ +#define __DEV_PWM_H__ + +#include +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup PWM PWM + * + * @brief PWM driver api + * + * Example + * @code {.c} + * #include + * #include + * + * #define PWM_DEV_NAME "pwm3" // PWM设备名称 + * #define PWM_DEV_CHANNEL 4 // PWM通道 + * + * struct rt_device_pwm *pwm_dev; // PWM设备句柄 + * + * static int pwm_led_sample(int argc, char *argv[]) + * { + * rt_uint32_t period, pulse, dir; + * + * period = 500000; // 周期为0.5ms，单位为纳秒ns + * dir = 1; // PWM脉冲宽度值的增减方向 + * pulse = 0; // PWM脉冲宽度值，单位为纳秒ns + * + * // 查找设备 + * pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME); + * if (pwm_dev == RT_NULL) + * { + * rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME); + * return -RT_ERROR; + * } + * + * // 设置PWM周期和脉冲宽度默认值 + * rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); + * // 使能设备 + * rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL); + * + * while (1) + * { + * rt_thread_mdelay(50); + * if (dir) + * { + * pulse += 5000; // 从0值开始每次增加5000ns + * } + * else + * { + * pulse -= 5000; // 从最大值开始每次减少5000ns + * } + * if (pulse >= period) + * { + * dir = 0; + * } + * if (0 == pulse) + * { + * dir = 1; + * } + * + * // 设置PWM周期和脉冲宽度 + * rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); + * } + * } + * + * MSH_CMD_EXPORT(pwm_led_sample, pwm sample); + * @endcode + * + * @ingroup Drivers + */ + +/*! + * @addtogroup PWM + * @{ + */ +#define PWM_CMD_ENABLE (RT_DEVICE_CTRL_BASE(PWM) + 0) +#define PWM_CMD_DISABLE (RT_DEVICE_CTRL_BASE(PWM) + 1) +#define PWM_CMD_SET (RT_DEVICE_CTRL_BASE(PWM) + 2) +#define PWM_CMD_GET (RT_DEVICE_CTRL_BASE(PWM) + 3) +#define PWMN_CMD_ENABLE (RT_DEVICE_CTRL_BASE(PWM) + 4) +#define PWMN_CMD_DISABLE (RT_DEVICE_CTRL_BASE(PWM) + 5) +#define PWM_CMD_SET_PERIOD (RT_DEVICE_CTRL_BASE(PWM) + 6) +#define PWM_CMD_SET_PULSE (RT_DEVICE_CTRL_BASE(PWM) + 7) +#define PWM_CMD_SET_DEAD_TIME (RT_DEVICE_CTRL_BASE(PWM) + 8) +#define PWM_CMD_SET_PHASE (RT_DEVICE_CTRL_BASE(PWM) + 9) +#define PWM_CMD_ENABLE_IRQ (RT_DEVICE_CTRL_BASE(PWM) + 10) +#define PWM_CMD_DISABLE_IRQ (RT_DEVICE_CTRL_BASE(PWM) + 11) + +/** + * @brief PWM configuration + */ +struct rt_pwm_configuration +{ + rt_uint32_t channel; /* 0 ~ n or 0 ~ -n, which depends on specific MCU requirements */ + rt_uint32_t period; /* unit:ns 1ns~4.29s:1Ghz~0.23hz */ + rt_uint32_t pulse; /* unit:ns (pulse<=period) */ + rt_uint32_t dead_time; /* unit:ns */ + rt_uint32_t phase; /*unit: degree, 0~360, which is the phase of pwm output, */ + /* + * RT_TRUE : The channel of pwm is complememtary. + * RT_FALSE : The channel of pwm is nomal. + */ + rt_bool_t complementary; +}; + +struct rt_device_pwm; +/** + * @brief PWM operations + */ +struct rt_pwm_ops +{ + rt_err_t (*control)(struct rt_device_pwm *device, int cmd, void *arg); +}; + +/** + * @brief PWM device + */ +struct rt_device_pwm +{ + struct rt_device parent; + const struct rt_pwm_ops *ops; +}; +/** + * @brief register a PWM device + * @param device the PWM device + * @param name the name of PWM device + * @param ops the operations of PWM device + * @param user_data the user data of PWM device + * @return rt_err_t error code + */ +rt_err_t rt_device_pwm_register(struct rt_device_pwm *device, const char *name, const struct rt_pwm_ops *ops, const void *user_data); + +/** + * @brief enable the PWM channel + * @param device the PWM device + * @param channel the channel of PWM + * @return rt_err_t error code + */ +rt_err_t rt_pwm_enable(struct rt_device_pwm *device, int channel); + +/** + * @brief disable the PWM channel + * @param device the PWM device + * @param channel the channel of PWM + * @return rt_err_t error code + */ +rt_err_t rt_pwm_disable(struct rt_device_pwm *device, int channel); + +/** + * @brief set the PWM channel + * @param device the PWM device + * @param channel the channel of PWM + * @param period the period of PWM + * @param pulse the pulse of PWM + * @return rt_err_t error code + */ +rt_err_t rt_pwm_set(struct rt_device_pwm *device, int channel, rt_uint32_t period, rt_uint32_t pulse); + +/** + * @brief set the PWM channel period + * @param device the PWM device + * @param channel the channel of PWM + * @param period the period of PWM + * @return rt_err_t error code +*/ +rt_err_t rt_pwm_set_period(struct rt_device_pwm *device, int channel, rt_uint32_t period); + +/** + * @brief set the PWM channel pulse + * @param device the PWM device + * @param channel the channel of PWM + * @param pulse the period of PWM + * @return rt_err_t error code +*/ +rt_err_t rt_pwm_set_pulse(struct rt_device_pwm *device, int channel, rt_uint32_t pulse); + +/** + * @brief set the dead zone time of PWM + * @param device the PWM device + * @param channel the channel of PWM + * @param dead_time dead zone time + * @return rt_err_t error code +*/ +rt_err_t rt_pwm_set_dead_time(struct rt_device_pwm *device, int channel, rt_uint32_t dead_time); + +/** + * @brief set the phase of PWM + * @param device the PWM device + * @param channel the channel of PWM + * @param phase phase + * @return rt_err_t error code +*/ +rt_err_t rt_pwm_set_phase(struct rt_device_pwm *device, int channel, rt_uint32_t phase); + +/*! @}*/ + +#endif /* __DEV_PWM_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/rtc.h b/rt-thread/components/drivers/include/drivers/dev_rtc.h similarity index 59% rename from rt-thread/components/drivers/include/drivers/rtc.h rename to rt-thread/components/drivers/include/drivers/dev_rtc.h index cba0ff9..740142d 100644 --- a/rt-thread/components/drivers/include/drivers/rtc.h +++ b/rt-thread/components/drivers/include/drivers/dev_rtc.h @@ -11,12 +11,75 @@ * 2022-04-05 tyx add timestamp function */ -#ifndef __RTC_H__ -#define __RTC_H__ +#ifndef __DEV_RTC_H__ +#define __DEV_RTC_H__ #include #include +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup RTC RTC + * + * @brief RTC driver api + * + * Example + * @code {.c} + * + * #include + * #include + * + * #define RTC_NAME "rtc" + * + * static int rtc_sample(int argc, char *argv[]) + * { + * rt_err_t ret = RT_EOK; + * time_t now; + * rt_device_t device = RT_NULL; + * + * device = rt_device_find(RTC_NAME); + * if (!device) + * { + * LOG_E("find %s failed!", RTC_NAME); + * return RT_ERROR; + * } + * + * if(rt_device_open(device, 0) != RT_EOK) + * { + * LOG_E("open %s failed!", RTC_NAME); + * return RT_ERROR; + * } + * + * ret = set_date(2018, 12, 3); + * if (ret != RT_EOK) + * { + * rt_kprintf("set RTC date failed\n"); + * return ret; + * } + * + * ret = set_time(11, 15, 50); + * if (ret != RT_EOK) + * { + * rt_kprintf("set RTC time failed\n"); + * return ret; + * } + * + * rt_thread_mdelay(3000); + * + * now = time(RT_NULL); + * rt_kprintf("%s\n", ctime(&now)); + * + * return ret; + * } + * MSH_CMD_EXPORT(rtc_sample, rtc sample); + * @endcode + * + * @ingroup Drivers + */ +/*! + * @addtogroup RTC + * @{ + */ #ifdef __cplusplus extern "C" { #endif @@ -31,7 +94,9 @@ extern "C" { #define RT_DEVICE_CTRL_RTC_SET_TIMESPEC (RT_DEVICE_CTRL_BASE(RTC) + 0x08) /**< set timespec for clock_settime */ #define RT_DEVICE_CTRL_RTC_GET_TIMERES (RT_DEVICE_CTRL_BASE(RTC) + 0x09) /**< get resolution for clock_getres */ -/* used for alarm function */ +/** + * @brief RTC alarm structure + */ struct rt_rtc_wkalarm { rt_bool_t enable; /* 0 = alarm disabled, 1 = alarm enabled */ @@ -42,7 +107,9 @@ struct rt_rtc_wkalarm rt_int32_t tm_mon; /* alarm at tm_mon */ rt_int32_t tm_year; /* alarm at tm_year */ }; - +/** + * @brief RTC operations + */ struct rt_rtc_ops { rt_err_t (*init)(void); @@ -54,20 +121,63 @@ struct rt_rtc_ops rt_err_t (*set_timeval)(struct timeval *tv); }; +/** + * @brief RTC device structure + */ typedef struct rt_rtc_device { struct rt_device parent; const struct rt_rtc_ops *ops; } rt_rtc_dev_t; +/** + * @brief Register a RTC device + * + * @param rtc RTC device + * @param name RTC device name + * @param flag RTC device flag + * @param data RTC device data + * @return rt_err_t error code + */ rt_err_t rt_hw_rtc_register(rt_rtc_dev_t *rtc, const char *name, rt_uint32_t flag, void *data); +/** + * @brief set date + * + * @param year year + * @param month month + * @param day day + * @return rt_err_t error code + */ rt_err_t set_date(rt_uint32_t year, rt_uint32_t month, rt_uint32_t day); + +/** + * @brief set time + * + * @param hour hour + * @param minute minute + * @param second second + * @return rt_err_t error code +*/ rt_err_t set_time(rt_uint32_t hour, rt_uint32_t minute, rt_uint32_t second); + +/** + * @brief set timestamp + * + * @param timestamp A pointer to time + * @return rt_err_t error code + */ rt_err_t set_timestamp(time_t timestamp); + +/** + * @brief get timestamp + * + * @param timestamp A secondary pointer to time + * @return rt_err_t error code + */ rt_err_t get_timestamp(time_t *timestamp); #ifdef RT_USING_SYSTEM_WORKQUEUE @@ -79,4 +189,6 @@ rt_err_t rt_soft_rtc_set_source(const char *name); } #endif -#endif /* __RTC_H__ */ +/*! @}*/ + +#endif /* __DEV_RTC_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/sd.h b/rt-thread/components/drivers/include/drivers/dev_sd.h similarity index 96% rename from rt-thread/components/drivers/include/drivers/sd.h rename to rt-thread/components/drivers/include/drivers/dev_sd.h index 4b7b093..ca8bb0c 100644 --- a/rt-thread/components/drivers/include/drivers/sd.h +++ b/rt-thread/components/drivers/include/drivers/dev_sd.h @@ -9,8 +9,8 @@ * 2024-05-26 HPMicro Add UHS-I support */ -#ifndef __SD_H__ -#define __SD_H__ +#ifndef __DEV_SD_H__ +#define __DEV_SD_H__ #include #include diff --git a/rt-thread/components/drivers/include/drivers/sdio.h b/rt-thread/components/drivers/include/drivers/dev_sdio.h similarity index 99% rename from rt-thread/components/drivers/include/drivers/sdio.h rename to rt-thread/components/drivers/include/drivers/dev_sdio.h index b145ffd..a8d30fd 100644 --- a/rt-thread/components/drivers/include/drivers/sdio.h +++ b/rt-thread/components/drivers/include/drivers/dev_sdio.h @@ -8,8 +8,8 @@ * 2012-01-15 weety first version */ -#ifndef __SDIO_H__ -#define __SDIO_H__ +#ifndef __DEV_SDIO_H__ +#define __DEV_SDIO_H__ #include #include diff --git a/rt-thread/components/drivers/include/drivers/serial.h b/rt-thread/components/drivers/include/drivers/dev_serial.h similarity index 66% rename from rt-thread/components/drivers/include/drivers/serial.h rename to rt-thread/components/drivers/include/drivers/dev_serial.h index d90b906..b7f627e 100644 --- a/rt-thread/components/drivers/include/drivers/serial.h +++ b/rt-thread/components/drivers/include/drivers/dev_serial.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,11 +11,109 @@ * the size of ring buffer. */ -#ifndef __SERIAL_H__ -#define __SERIAL_H__ +#ifndef __DEV_SERIAL_H__ +#define __DEV_SERIAL_H__ #include +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup Serial Serial + * + * @brief Serial driver api + * + * Example + * @code {.c} + * + * #include + * + * #define SAMPLE_UART_NAME "uart2" + * static struct rt_semaphore rx_sem; + * static rt_device_t serial; + * + * static rt_err_t uart_input(rt_device_t dev, rt_size_t size) + * { + * + * rt_sem_release(&rx_sem); + * + * return RT_EOK; + * } + * + * static void serial_thread_entry(void *parameter) + * { + * char ch; + * + * while (1) + * { + * + * while (rt_device_read(serial, -1, &ch, 1) != 1) + * { + * + * rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + * } + * + * ch = ch + 1; + * rt_device_write(serial, 0, &ch, 1); + * } + * } + * + * static int uart_sample(int argc, char *argv[]) + * { + * rt_err_t ret = RT_EOK; + * char uart_name[RT_NAME_MAX]; + * char str[] = "hello RT-Thread!\r\n"; + * + * if (argc == 2) + * { + * rt_strncpy(uart_name, argv[1], RT_NAME_MAX); + * } + * else + * { + * rt_strncpy(uart_name, SAMPLE_UART_NAME, RT_NAME_MAX); + * } + * + * + * serial = rt_device_find(uart_name); + * if (!serial) + * { + * rt_kprintf("find %s failed!\n", uart_name); + * return -RT_ERROR; + * } + * + * + * rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); + * + * rt_device_open(serial, RT_DEVICE_FLAG_INT_RX); + * + * rt_device_set_rx_indicate(serial, uart_input); + * + * rt_device_write(serial, 0, str, (sizeof(str) - 1)); + * + * + * rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10); + * + * if (thread != RT_NULL) + * { + * rt_thread_startup(thread); + * } + * else + * { + * ret = -RT_ERROR; + * } + * + * return ret; + * } + * + * MSH_CMD_EXPORT(uart_sample, uart device sample); + * @endcode + * + * @ingroup Drivers + */ + +/*! + * @addtogroup Serial + * @{ + */ #define BAUD_RATE_2400 2400 #define BAUD_RATE_4800 4800 #define BAUD_RATE_9600 9600 @@ -105,7 +203,6 @@ /** * @brief Sets a hook function when RX indicate is called * - * @param thread is the target thread that initializing */ typedef void (*rt_hw_serial_rxind_hookproto_t)(rt_device_t dev, rt_size_t size); RT_OBJECT_HOOKLIST_DECLARE(rt_hw_serial_rxind_hookproto_t, rt_hw_serial_rxind); @@ -167,13 +264,15 @@ struct rt_serial_device void *serial_tx; struct rt_spinlock spinlock; - +#ifdef RT_USING_SERIAL_BYPASS + struct rt_serial_bypass* bypass; +#endif struct rt_device_notify rx_notify; }; typedef struct rt_serial_device rt_serial_t; /** - * uart operators + * @brief Configure the serial device */ struct rt_uart_ops { @@ -186,13 +285,41 @@ struct rt_uart_ops rt_ssize_t (*dma_transmit)(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction); }; +/** + * @brief Serial interrupt service routine + * @param serial serial device + * @param event event mask + * @ingroup Serial + */ void rt_hw_serial_isr(struct rt_serial_device *serial, int event); +/** + * @brief Register a serial device to device list + * + * @param serial serial device + * @param name device name + * @param flag device flag + * @param data device private data + * @return rt_err_t error code + * @note This function will register a serial device to system device list, + * and add a device object to system object list. + * @ingroup Serial + */ rt_err_t rt_hw_serial_register(struct rt_serial_device *serial, const char *name, rt_uint32_t flag, void *data); +/** + * @brief register a serial device to system device list and add a device object to system object list + * + * @param serial serial device + * @return rt_err_t error code + * + * @ingroup Serial + */ rt_err_t rt_hw_serial_register_tty(struct rt_serial_device *serial); +/*! @}*/ + #endif diff --git a/rt-thread/components/drivers/include/drivers/serial_v2.h b/rt-thread/components/drivers/include/drivers/dev_serial_v2.h similarity index 61% rename from rt-thread/components/drivers/include/drivers/serial_v2.h rename to rt-thread/components/drivers/include/drivers/dev_serial_v2.h index d0dcf37..0bdc51b 100644 --- a/rt-thread/components/drivers/include/drivers/serial_v2.h +++ b/rt-thread/components/drivers/include/drivers/dev_serial_v2.h @@ -8,11 +8,127 @@ * 2021-06-01 KyleChan first version */ -#ifndef __SERIAL_V2_H__ -#define __SERIAL_V2_H__ +#ifndef __DEV_SERIAL_V2_H__ +#define __DEV_SERIAL_V2_H__ #include + +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup Serial_v2 Serial v2 + * + * @brief Serial v2 driver api + * + * Example + * @code {.c} + * + * #include + * #include + * + * #define SAMPLE_UART_NAME "uart1" + * + * struct rx_msg + * { + * rt_device_t dev; + * rt_size_t size; + * }; + * static rt_device_t serial; + * static struct rt_messagequeue rx_mq; + * + * static rt_err_t uart_input(rt_device_t dev, rt_size_t size) + * { + * struct rx_msg msg; + * rt_err_t result; + * msg.dev = dev; + * msg.size = size; + * + * result = rt_mq_send(&rx_mq, &msg, sizeof(msg)); + * if (result == -RT_EFULL) + * { + * rt_kprintf("message queue full！\n"); + * } + * return result; + * } + * + * static void serial_thread_entry(void *parameter) + * { + * struct rx_msg msg; + * rt_err_t result; + * rt_uint32_t rx_length; + * static char rx_buffer[BSP_UART1_RX_BUFSIZE + 1]; + * + * while (1) + * { + * rt_memset(&msg, 0, sizeof(msg)); + * result = rt_mq_recv(&rx_mq, &msg, sizeof(msg), RT_WAITING_FOREVER); + * if (result > 0) + * { + * rx_length = rt_device_read(msg.dev, 0, rx_buffer, msg.size); + * rx_buffer[rx_length] = '\0'; + * rt_device_write(serial, 0, rx_buffer, rx_length); + * rt_kprintf("%s\n",rx_buffer); + * } + * } + * } + * + * static int uart_dma_sample(int argc, char *argv[]) + * { + * rt_err_t ret = RT_EOK; + * char uart_name[RT_NAME_MAX]; + * static char msg_pool[256]; + * char str[] = "hello RT-Thread!\r\n"; + * + * if (argc == 2) + * { + * rt_strncpy(uart_name, argv[1], RT_NAME_MAX); + * } + * else + * { + * rt_strncpy(uart_name, SAMPLE_UART_NAME, RT_NAME_MAX); + * } + * + * serial = rt_device_find(uart_name); + * if (!serial) + * { + * rt_kprintf("find %s failed!\n", uart_name); + * return RT_ERROR; + * } + * + * rt_mq_init(&rx_mq, "rx_mq", + * msg_pool, + * sizeof(struct rx_msg), + * sizeof(msg_pool), + * RT_IPC_FLAG_FIFO); + * + * rt_device_open(serial, RT_DEVICE_FLAG_RX_NON_BLOCKING | RT_DEVICE_FLAG_TX_BLOCKING); + * rt_device_set_rx_indicate(serial, uart_input); + * rt_device_write(serial, 0, str, (sizeof(str) - 1)); + * + * rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10); + * if (thread != RT_NULL) + * { + * rt_thread_startup(thread); + * } + * else + * { + * ret = RT_ERROR; + * } + * + * return ret; + * } + * MSH_CMD_EXPORT(uart_dma_sample, uart device dma sample); + * @endcode + * + * @ingroup Drivers + */ + + +/*! + * @addtogroup Serial_v2 + * @{ + */ + #define BAUD_RATE_2400 2400 #define BAUD_RATE_4800 4800 #define BAUD_RATE_9600 9600 @@ -104,9 +220,8 @@ } /** - * @brief Sets a hook function when RX indicate is called - * - * @param thread is the target thread that initializing + * @brief Serial receive indicate hook function type + * */ typedef void (*rt_hw_serial_rxind_hookproto_t)(rt_device_t dev, rt_size_t size); RT_OBJECT_HOOKLIST_DECLARE(rt_hw_serial_rxind_hookproto_t, rt_hw_serial_rxind); @@ -126,8 +241,8 @@ struct serial_configure rt_uint32_t reserved :5; }; -/* - * Serial Receive FIFO mode +/** + * @brief Serial Receive FIFO mode */ struct rt_serial_rx_fifo { @@ -141,8 +256,9 @@ struct rt_serial_rx_fifo rt_uint8_t buffer[]; }; -/* - * Serial Transmit FIFO mode +/** + * @brief Serial Transmit FIFO mode + * */ struct rt_serial_tx_fifo { @@ -158,6 +274,10 @@ struct rt_serial_tx_fifo rt_uint8_t buffer[]; }; +/** + * @brief serial device structure + * + */ struct rt_serial_device { struct rt_device parent; @@ -172,7 +292,8 @@ struct rt_serial_device }; /** - * uart operators + * @brief uart device operations + * */ struct rt_uart_ops { @@ -192,12 +313,43 @@ struct rt_uart_ops rt_uint32_t tx_flag); }; +/** + * @brief Serial interrupt service routine + * @param serial serial device + * @param event event mask + * @ingroup Serial_v2 + */ void rt_hw_serial_isr(struct rt_serial_device *serial, int event); + +/** + * @brief Register a serial device to device list + * + * @param serial serial device + * @param name device name + * @param flag device flag + * @param data device private data + * @return rt_err_t error code + * @note This function will register a serial device to system device list, + * and add a device object to system object list. + * @ingroup Serial_v2 + */ rt_err_t rt_hw_serial_register(struct rt_serial_device *serial, const char *name, rt_uint32_t flag, void *data); +/** + * @brief register a serial device to system device list and add a device object to system object list + * + * @param serial serial device + * @return rt_err_t error code + * + * @ingroup Serial_v2 + */ rt_err_t rt_hw_serial_register_tty(struct rt_serial_device *serial); + + +/*! @}*/ + #endif diff --git a/rt-thread/components/drivers/include/drivers/dev_spi.h b/rt-thread/components/drivers/include/drivers/dev_spi.h new file mode 100644 index 0000000..0aa08c4 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/dev_spi.h @@ -0,0 +1,633 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-11-23 Bernard Add extern "C" + * 2020-06-13 armink fix the 3 wires issue + * 2022-09-01 liYony fix api rt_spi_sendrecv16 about MSB and LSB bug + */ + +#ifndef __DEV_SPI_H__ +#define __DEV_SPI_H__ + +#include +#include +#include +#include + +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup SPI SPI + * + * @brief SPI driver api + * + * Example + * @code {.c} + * #include + * #include + * + * #define W25Q_SPI_DEVICE_NAME "qspi10" + * + * static void spi_w25q_sample(int argc, char *argv[]) + * { + * struct rt_spi_device *spi_dev_w25q; + * char name[RT_NAME_MAX]; + * rt_uint8_t w25x_read_id = 0x90; + * rt_uint8_t id[5] = {0}; + * + * if (argc == 2) + * { + * rt_strncpy(name, argv[1], RT_NAME_MAX); + * } + * else + * { + * rt_strncpy(name, W25Q_SPI_DEVICE_NAME, RT_NAME_MAX); + * } + * + * // 查找 spi 设备获取设备句柄 + * spi_dev_w25q = (struct rt_spi_device *)rt_device_find(name); + * if (!spi_dev_w25q) + * { + * rt_kprintf("spi sample run failed! can't find %s device!\n", name); + * } + * else + * { + * // 方式1：使用 rt_spi_send_then_recv()发送命令读取ID + * rt_spi_send_then_recv(spi_dev_w25q, &w25x_read_id, 1, id, 5); + * rt_kprintf("use rt_spi_send_then_recv() read w25q ID is:%x%x\n", id[3], id[4]); + * + * // 方式2：使用 rt_spi_transfer_message()发送命令读取ID + * struct rt_spi_message msg1, msg2; + * + * msg1.send_buf = &w25x_read_id; + * msg1.recv_buf = RT_NULL; + * msg1.length = 1; + * msg1.cs_take = 1; + * msg1.cs_release = 0; + * msg1.next = &msg2; + * + * msg2.send_buf = RT_NULL; + * msg2.recv_buf = id; + * msg2.length = 5; + * msg2.cs_take = 0; + * msg2.cs_release = 1; + * msg2.next = RT_NULL; + * + * rt_spi_transfer_message(spi_dev_w25q, &msg1); + * rt_kprintf("use rt_spi_transfer_message() read w25q ID is:%x%x\n", id[3], id[4]); + * + * } + * } + * // 导出到 msh 命令列表中 + * MSH_CMD_EXPORT(spi_w25q_sample, spi w25q sample); + * @endcode + * + * @ingroup Drivers + */ + +/*! + * @addtogroup SPI + * @{ + */ +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * At CPOL=0 the base value of the clock is zero + * - For CPHA=0, data are captured on the clock's rising edge (low->high transition) + * and data are propagated on a falling edge (high->low clock transition). + * - For CPHA=1, data are captured on the clock's falling edge and data are + * propagated on a rising edge. + * At CPOL=1 the base value of the clock is one (inversion of CPOL=0) + * - For CPHA=0, data are captured on clock's falling edge and data are propagated + * on a rising edge. + * - For CPHA=1, data are captured on clock's rising edge and data are propagated + * on a falling edge. + */ +#define RT_SPI_CPHA (1<<0) /*!< bit[0]:CPHA, clock phase */ +#define RT_SPI_CPOL (1<<1) /*!< bit[1]:CPOL, clock polarity */ + +#define RT_SPI_LSB (0<<2) /*!< bit[2]: 0-LSB */ +#define RT_SPI_MSB (1<<2) /*!< bit[2]: 1-MSB */ + +#define RT_SPI_MASTER (0<<3) /*!< SPI master device */ +#define RT_SPI_SLAVE (1<<3) /*!< SPI slave device */ + +#define RT_SPI_CS_HIGH (1<<4) /*!< Chipselect active high */ +#define RT_SPI_NO_CS (1<<5) /*!< No chipselect */ +#define RT_SPI_3WIRE (1<<6) /*!< SI/SO pin shared */ +#define RT_SPI_READY (1<<7) /*!< Slave pulls low to pause */ + +#define RT_SPI_MODE_MASK (RT_SPI_CPHA | RT_SPI_CPOL | RT_SPI_MSB | RT_SPI_SLAVE | RT_SPI_CS_HIGH | RT_SPI_NO_CS | RT_SPI_3WIRE | RT_SPI_READY) + +#define RT_SPI_MODE_0 (0 | 0) /*!< CPOL = 0, CPHA = 0 */ +#define RT_SPI_MODE_1 (0 | RT_SPI_CPHA) /*!< CPOL = 0, CPHA = 1 */ +#define RT_SPI_MODE_2 (RT_SPI_CPOL | 0) /*!< CPOL = 1, CPHA = 0 */ +#define RT_SPI_MODE_3 (RT_SPI_CPOL | RT_SPI_CPHA) /*!< CPOL = 1, CPHA = 1 */ + +#define RT_SPI_BUS_MODE_SPI (1<<0) +#define RT_SPI_BUS_MODE_QSPI (1<<1) + +/** + * @brief SPI message structure + */ +struct rt_spi_message +{ + const void *send_buf; + void *recv_buf; + rt_size_t length; + struct rt_spi_message *next; + + unsigned cs_take : 1; + unsigned cs_release : 1; +}; + +/** + * @brief SPI configuration structure + */ +struct rt_spi_configuration +{ + rt_uint8_t mode; + rt_uint8_t data_width; +#ifdef RT_USING_DM + rt_uint8_t data_width_tx; + rt_uint8_t data_width_rx; +#else + rt_uint16_t reserved; +#endif + + rt_uint32_t max_hz; +}; + +struct rt_spi_ops; + +/** + * @brief SPI bus structure + */ +struct rt_spi_bus +{ + struct rt_device parent; + rt_uint8_t mode; + const struct rt_spi_ops *ops; + +#ifdef RT_USING_DM + rt_base_t *pins; + rt_bool_t slave; + int num_chipselect; +#endif /* RT_USING_DM */ + + struct rt_mutex lock; + struct rt_spi_device *owner; +}; + +/** + * @brief SPI operators + */ +struct rt_spi_ops +{ + rt_err_t (*configure)(struct rt_spi_device *device, struct rt_spi_configuration *configuration); + rt_ssize_t (*xfer)(struct rt_spi_device *device, struct rt_spi_message *message); +}; + +#ifdef RT_USING_DM +/** + * @brief SPI delay info + */ +struct rt_spi_delay +{ +#define RT_SPI_DELAY_UNIT_USECS 0 +#define RT_SPI_DELAY_UNIT_NSECS 1 +#define RT_SPI_DELAY_UNIT_SCK 2 + rt_uint16_t value; + rt_uint8_t unit; +}; +#endif /* RT_USING_DM */ + +/** + * @brief SPI Virtual BUS, one device must connected to a virtual BUS + */ +struct rt_spi_device +{ + struct rt_device parent; + struct rt_spi_bus *bus; + +#ifdef RT_USING_DM + const char *name; + const struct rt_spi_device_id *id; + const struct rt_ofw_node_id *ofw_id; + + rt_uint8_t chip_select; + struct rt_spi_delay cs_setup; + struct rt_spi_delay cs_hold; + struct rt_spi_delay cs_inactive; +#endif + + struct rt_spi_configuration config; + rt_base_t cs_pin; + void *user_data; +}; + +/** + * @brief QSPI message structure + */ +struct rt_qspi_message +{ + struct rt_spi_message parent; + + /* instruction stage */ + struct + { + rt_uint8_t content; + rt_uint8_t qspi_lines; + } instruction; + + /* address and alternate_bytes stage */ + struct + { + rt_uint32_t content; + rt_uint8_t size; + rt_uint8_t qspi_lines; + } address, alternate_bytes; + + /* dummy_cycles stage */ + rt_uint32_t dummy_cycles; + + /* number of lines in qspi data stage, the other configuration items are in parent */ + rt_uint8_t qspi_data_lines; +}; + +/** + * @brief QSPI configuration structure + */ +struct rt_qspi_configuration +{ + struct rt_spi_configuration parent; + /* The size of medium */ + rt_uint32_t medium_size; + /* double data rate mode */ + rt_uint8_t ddr_mode; + /* the data lines max width which QSPI bus supported, such as 1, 2, 4 */ + rt_uint8_t qspi_dl_width ; +}; + +/** + * @brief QSPI operators + */ +struct rt_qspi_device +{ + struct rt_spi_device parent; + + struct rt_qspi_configuration config; + + void (*enter_qspi_mode)(struct rt_qspi_device *device); + + void (*exit_qspi_mode)(struct rt_qspi_device *device); +}; + +#define SPI_DEVICE(dev) ((struct rt_spi_device *)(dev)) + +#ifdef RT_USING_DM +struct rt_spi_device_id +{ + char name[20]; + void *data; +}; + +struct rt_spi_driver +{ + struct rt_driver parent; + + const struct rt_spi_device_id *ids; + const struct rt_ofw_node_id *ofw_ids; + + rt_err_t (*probe)(struct rt_spi_device *device); + rt_err_t (*remove)(struct rt_spi_device *device); + rt_err_t (*shutdown)(struct rt_spi_device *device); +}; + +rt_err_t rt_spi_driver_register(struct rt_spi_driver *driver); +rt_err_t rt_spi_device_register(struct rt_spi_device *device); + +#define RT_SPI_DRIVER_EXPORT(driver) RT_DRIVER_EXPORT(driver, spi, BUILIN) +#endif /* RT_USING_DM */ + +/** + * @brief register a SPI bus + * + * @param bus the SPI bus + * @param name the name of SPI bus + * @param ops the operations of SPI bus + * + * @return rt_err_t error code + */ +rt_err_t rt_spi_bus_register(struct rt_spi_bus *bus, + const char *name, + const struct rt_spi_ops *ops); + + +/** + * @brief attach a device on SPI bus + * + * @param device the SPI device + * @param name the name of SPI device + * @param bus_name the name of SPI bus + * @param user_data the user data of SPI device + * + * @return rt_err_t error code + */ +rt_err_t rt_spi_bus_attach_device(struct rt_spi_device *device, + const char *name, + const char *bus_name, + void *user_data); + + +/** + * @brief attach a device on SPI bus with CS pin + * + * @param device the SPI device + * @param name the name of SPI device + * @param bus_name the name of SPI bus + * @param cs_pin the CS pin of SPI device + * @param user_data the user data of SPI device + * + * @return rt_err_t error code + */ +rt_err_t rt_spi_bus_attach_device_cspin(struct rt_spi_device *device, + const char *name, + const char *bus_name, + rt_base_t cs_pin, + void *user_data); + +/** + * @brief Reconfigure the SPI bus for the specified device. + * + * @param device: Pointer to the SPI device attached to the SPI bus. + * @retval RT_EOK if the SPI device was successfully released and the bus was configured. + * RT_EBUSY if the SPI bus is currently in use; the new configuration will take effect once the device releases the bus. + * Other return values indicate failure to configure the SPI bus due to various reasons. + * @note If the configuration of the SPI device has been updated and requires bus re-initialization, + * call this function directly. This function will reconfigure the SPI bus for the specified device. + * If this is the first time to initialize the SPI device, please call rt_spi_configure or rt_qspi_configure. + * This function is used to reconfigure the SPI bus when the SPI device is already in use. + * For further details, refer to: + * https://github.com/RT-Thread/rt-thread/pull/8528 + */ +rt_err_t rt_spi_bus_configure(struct rt_spi_device *device); + +/** + * @brief This function takes SPI bus. + * + * @param device the SPI device attached to SPI bus + * + * @return RT_EOK on taken SPI bus successfully. others on taken SPI bus failed. + */ +rt_err_t rt_spi_take_bus(struct rt_spi_device *device); + +/** + * @brief This function releases SPI bus. + * + * @param device the SPI device attached to SPI bus + * + * @return RT_EOK on release SPI bus successfully. + */ +rt_err_t rt_spi_release_bus(struct rt_spi_device *device); + +/** + * @brief This function take SPI device (takes CS of SPI device). + * + * @param device the SPI device attached to SPI bus + * + * @return RT_EOK on release SPI bus successfully. others on taken SPI bus failed. + */ +rt_err_t rt_spi_take(struct rt_spi_device *device); + +/** + * @brief This function releases SPI device (releases CS of SPI device). + * + * @param device the SPI device attached to SPI bus + * + * @return RT_EOK on release SPI device successfully. + */ +rt_err_t rt_spi_release(struct rt_spi_device *device); + +/** + * @brief This function can set configuration on SPI device. + * + * @param device: the SPI device attached to SPI bus + * @param cfg: the configuration pointer. + * + * @retval RT_EOK on release SPI device successfully. + * RT_EBUSY is not an error condition and the configuration will take effect once the device has the bus + * others on taken SPI bus failed. + */ +rt_err_t rt_spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *cfg); + + +/** + * @brief This function can send data then receive data from SPI device. + * + * @param device the SPI device attached to SPI bus + * @param send_buf the buffer to be transmitted to SPI device. + * @param send_length the number of data to be transmitted. + * @param recv_buf the buffer to be recivied from SPI device. + * @param recv_length the data to be recivied. + * + * @return rt_err_t error code + */ +rt_err_t rt_spi_send_then_recv(struct rt_spi_device *device, + const void *send_buf, + rt_size_t send_length, + void *recv_buf, + rt_size_t recv_length); + +/** + * @brief This function can send data then send data from SPI device. + * + * @param device the SPI device attached to SPI bus + * @param send_buf1 the buffer to be transmitted to SPI device. + * @param send_length1 the number of data to be transmitted. + * @param send_buf2 the buffer to be transmitted to SPI device. + * @param send_length2 the number of data to be transmitted. + * + * @return the status of transmit. + */ +rt_err_t rt_spi_send_then_send(struct rt_spi_device *device, + const void *send_buf1, + rt_size_t send_length1, + const void *send_buf2, + rt_size_t send_length2); + +/** + * @brief This function transmits data to SPI device. + * + * @param device the SPI device attached to SPI bus + * @param send_buf the buffer to be transmitted to SPI device. + * @param recv_buf the buffer to save received data from SPI device. + * @param length the length of transmitted data. + * + * @return the actual length of transmitted. + */ +rt_ssize_t rt_spi_transfer(struct rt_spi_device *device, + const void *send_buf, + void *recv_buf, + rt_size_t length); + +/** + * @brief The SPI device transmits 8 bytes of data + * + * @param device the SPI device attached to SPI bus + * @param senddata send data buffer + * @param recvdata receive data buffer + * + * @return rt_err_t error code + */ +rt_err_t rt_spi_sendrecv8(struct rt_spi_device *device, + rt_uint8_t senddata, + rt_uint8_t *recvdata); + +/** + * @brief The SPI device transmits 16 bytes of data + * + * @param device the SPI device attached to SPI bus + * @param senddata send data buffer + * @param recvdata receive data buffer + * + * @return rt_err_t error code + */ +rt_err_t rt_spi_sendrecv16(struct rt_spi_device *device, + rt_uint16_t senddata, + rt_uint16_t *recvdata); + +/** + * @brief This function transfers a message list to the SPI device. + * + * @param device the SPI device attached to SPI bus + * @param message the message list to be transmitted to SPI device + * + * @return RT_NULL if transmits message list successfully, + * SPI message which be transmitted failed. + */ +struct rt_spi_message *rt_spi_transfer_message(struct rt_spi_device *device, + struct rt_spi_message *message); + +/** + * @brief This function receives data from SPI device. + * + * @param device the SPI device attached to SPI bus + * @param recv_buf the buffer to be recivied from SPI device. + * @param length the data to be recivied. + * + * @return the actual length of received. +*/ +rt_inline rt_size_t rt_spi_recv(struct rt_spi_device *device, + void *recv_buf, + rt_size_t length) +{ + return rt_spi_transfer(device, RT_NULL, recv_buf, length); +} + +/** + * @brief This function sends data to SPI device. + * + * @param device the SPI device attached to SPI bus + * @param send_buf the buffer to be transmitted to SPI device. + * @param length the number of data to be transmitted. + * + * @return the actual length of send. + */ +rt_inline rt_size_t rt_spi_send(struct rt_spi_device *device, + const void *send_buf, + rt_size_t length) +{ + return rt_spi_transfer(device, send_buf, RT_NULL, length); +} + +/** + * @brief This function appends a message to the SPI message list. + * + * @param list the SPI message list header. + * @param message the message pointer to be appended to the message list. + */ +rt_inline void rt_spi_message_append(struct rt_spi_message *list, + struct rt_spi_message *message) +{ + RT_ASSERT(list != RT_NULL); + if (message == RT_NULL) + return; /* not append */ + + while (list->next != RT_NULL) + { + list = list->next; + } + + list->next = message; + message->next = RT_NULL; +} + +/** + * @brief This function can set configuration on QSPI device. + * + * @param device the QSPI device attached to QSPI bus. + * @param cfg the configuration pointer. + * + * @return the actual length of transmitted. + */ +rt_err_t rt_qspi_configure(struct rt_qspi_device *device, struct rt_qspi_configuration *cfg); + +/** + * @brief This function can register a SPI bus for QSPI mode. + * + * @param bus the SPI bus for QSPI mode. + * @param name The name of the spi bus. + * @param ops the SPI bus instance to be registered. + * + * @return the actual length of transmitted. + */ +rt_err_t rt_qspi_bus_register(struct rt_spi_bus *bus, const char *name, const struct rt_spi_ops *ops); + +/** + * @brief This function transmits data to QSPI device. + * + * @param device the QSPI device attached to QSPI bus. + * @param message the message pointer. + * + * @return the actual length of transmitted. + */ +rt_size_t rt_qspi_transfer_message(struct rt_qspi_device *device, struct rt_qspi_message *message); + +/** + * @brief This function can send data then receive data from QSPI device + * + * @param device the QSPI device attached to QSPI bus. + * @param send_buf the buffer to be transmitted to QSPI device. + * @param send_length the number of data to be transmitted. + * @param recv_buf the buffer to be recivied from QSPI device. + * @param recv_length the data to be recivied. + * + * @return the status of transmit. + */ +rt_err_t rt_qspi_send_then_recv(struct rt_qspi_device *device, const void *send_buf, rt_size_t send_length,void *recv_buf, rt_size_t recv_length); + +/** + * @brief This function can send data to QSPI device + * + * @param device the QSPI device attached to QSPI bus. + * @param send_buf the buffer to be transmitted to QSPI device. + * @param length the number of data to be transmitted. + * + * @return the status of transmit. + */ +rt_err_t rt_qspi_send(struct rt_qspi_device *device, const void *send_buf, rt_size_t length); + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif diff --git a/rt-thread/components/drivers/include/drivers/touch.h b/rt-thread/components/drivers/include/drivers/dev_touch.h similarity index 53% rename from rt-thread/components/drivers/include/drivers/touch.h rename to rt-thread/components/drivers/include/drivers/dev_touch.h index aa29749..ba01ae4 100644 --- a/rt-thread/components/drivers/include/drivers/touch.h +++ b/rt-thread/components/drivers/include/drivers/dev_touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,12 +8,117 @@ * 2019-05-20 tyustli the first version */ -#ifndef __TOUCH_H__ -#define __TOUCH_H__ +#ifndef __DEV_TOUCH_H__ +#define __DEV_TOUCH_H__ #include -#include "pin.h" +#include "dev_pin.h" +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup Touch Touch + * + * @brief Touch driver api + * + * Example + * @code {.c} + * #include + * #include "rtdevice.h" + * + * static rt_thread_t gt9147_thread = RT_NULL; + * static rt_sem_t gt9147_sem = RT_NULL; + * static rt_device_t dev = RT_NULL; + * static struct rt_touch_data *read_data; + * + * // 读取数据线程入口函数 + * static void gt9147_entry(void *parameter) + * { + * struct rt_touch_data *read_data; + * read_data = (struct rt_touch_data *)rt_malloc(sizeof(struct rt_touch_data) * 5); + * + * while (1) + * { + * // 请求信号量 + * rt_sem_take(gt9147_sem, RT_WAITING_FOREVER); + * // 读取五个点的触摸信息 + * if (rt_device_read(dev, 0, read_data, 5) == 5) + * { + * for (rt_uint8_t i = 0; i < 5; i++) + * { + * if (read_data[i].event == RT_TOUCH_EVENT_DOWN || read_data[i].event == RT_TOUCH_EVENT_MOVE) + * { + * rt_kprintf("%d %d %d %d %d\n", + * read_data[i].track_id, + * read_data[i].x_coordinate, + * read_data[i].y_coordinate, + * read_data[i].timestamp, + * read_data[i].width); + * } + * } + * } + * // 打开中断 + * rt_device_control(dev, RT_TOUCH_CTRL_ENABLE_INT, RT_NULL); + * } + * } + * + * // 接收回调函数 + * static rt_err_t rx_callback(rt_device_t dev, rt_size_t size) + * { + * // 关闭中断 + * rt_device_control(dev, RT_TOUCH_CTRL_DISABLE_INT, RT_NULL); + * // 释放信号量 + * rt_sem_release(gt9147_sem); + * return 0; + * } + * + * static int gt9147_sample(void) + * { + * // 查找 Touch 设备 + * dev = rt_device_find("touch"); + * + * if (dev == RT_NULL) + * { + * rt_kprintf("can't find device:%s\n", "touch"); + * return -1; + * } + * // 以中断的方式打开设备 + * if (rt_device_open(dev, RT_DEVICE_FLAG_INT_RX) != RT_EOK) + * { + * rt_kprintf("open device failed!"); + * return -1; + * } + * // 设置接收回调 + * rt_device_set_rx_indicate(dev, rx_callback); + * // 创建信号量 + * gt9147_sem = rt_sem_create("dsem", 0, RT_IPC_FLAG_PRIO); + * + * if (gt9147_sem == RT_NULL) + * { + * rt_kprintf("create dynamic semaphore failed.\n"); + * return -1; + * } + * // 创建读取数据线程 + * gt9147_thread = rt_thread_create("thread1", + * gt9147_entry, + * RT_NULL, + * THREAD_STACK_SIZE, + * THREAD_PRIORITY, + * THREAD_TIMESLICE); + * // 启动线程 + * if (gt9147_thread != RT_NULL) + * rt_thread_startup(gt9147_thread); + * + * return 0; + * } + * MSH_CMD_EXPORT(gt9147_sample, gt9147 sample); + * @endcode + * + * @ingroup Drivers + */ +/*! + * @addtogroup Touch + * @{ + */ #ifdef __cplusplus extern "C" { #endif @@ -53,6 +158,9 @@ extern "C" { #define RT_TOUCH_EVENT_DOWN (2) /* Touch down event */ #define RT_TOUCH_EVENT_MOVE (3) /* Touch move event */ +/** + * @brief Touch information +*/ struct rt_touch_info { rt_uint8_t type; /* The touch type */ @@ -62,6 +170,9 @@ struct rt_touch_info rt_int32_t range_y; /* Y coordinate range */ }; +/** + * @brief Touch configuration +*/ struct rt_touch_config { #ifdef RT_TOUCH_PIN_IRQ @@ -72,6 +183,9 @@ struct rt_touch_config }; typedef struct rt_touch_device *rt_touch_t; +/** + * @brief Touch device +*/ struct rt_touch_device { struct rt_device parent; /* The standard device */ @@ -82,6 +196,9 @@ struct rt_touch_device rt_err_t (*irq_handle)(rt_touch_t touch); /* Called when an interrupt is generated, registered by the driver */ }; +/** + * @brief Touch data +*/ struct rt_touch_data { rt_uint8_t event; /* The touch event of the data */ @@ -92,22 +209,40 @@ struct rt_touch_data rt_tick_t timestamp; /* The timestamp when the data was received */ }; +/** + * @brief Touch device operations +*/ struct rt_touch_ops { rt_size_t (*touch_readpoint)(struct rt_touch_device *touch, void *buf, rt_size_t touch_num); rt_err_t (*touch_control)(struct rt_touch_device *touch, int cmd, void *arg); }; +/** + * @brief register a touch device + * @param touch the touch device + * @param name the name of touch device + * @param flag the flag of touch device + * @param data the user data of touch device + * @return rt_err_t error code + */ int rt_hw_touch_register(rt_touch_t touch, const char *name, rt_uint32_t flag, void *data); -/* if you doesn't use pin device. you must call this function in your touch irq callback */ +/** + * @brief Touch irq handle + * @param touch the touch device + * + * @note If you doesn't use pin device. you must call this function in your touch irq callback + */ void rt_hw_touch_isr(rt_touch_t touch); #ifdef __cplusplus } #endif -#endif /* __TOUCH_H__ */ +/*! @}*/ + +#endif /* __DEV_TOUCH_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/watchdog.h b/rt-thread/components/drivers/include/drivers/dev_watchdog.h similarity index 94% rename from rt-thread/components/drivers/include/drivers/watchdog.h rename to rt-thread/components/drivers/include/drivers/dev_watchdog.h index e08d35d..4b5614f 100644 --- a/rt-thread/components/drivers/include/drivers/watchdog.h +++ b/rt-thread/components/drivers/include/drivers/dev_watchdog.h @@ -8,8 +8,8 @@ * 2012-09-12 heyuanjie87 first version. */ -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ +#ifndef __DEV_WATCHDOG_H__ +#define __DEV_WATCHDOG_H__ #include @@ -39,4 +39,4 @@ rt_err_t rt_hw_watchdog_register(rt_watchdog_t *wdt, rt_uint32_t flag, void *data); -#endif /* __WATCHDOG_H__ */ +#endif /* __DEV_WATCHDOG_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/dma.h b/rt-thread/components/drivers/include/drivers/dma.h new file mode 100644 index 0000000..3128c67 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/dma.h @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#ifndef __DMA_H__ +#define __DMA_H__ + +#include +#include +#include +#include + +#include +#include +#include + +struct rt_dma_chan; +struct rt_dma_controller_ops; + +enum rt_dma_transfer_direction +{ + RT_DMA_MEM_TO_MEM, + RT_DMA_MEM_TO_DEV, + RT_DMA_DEV_TO_MEM, + RT_DMA_DEV_TO_DEV, + + RT_DMA_DIR_MAX, +}; + +enum rt_dma_slave_buswidth +{ + RT_DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, + RT_DMA_SLAVE_BUSWIDTH_1_BYTE = 1, + RT_DMA_SLAVE_BUSWIDTH_2_BYTES = 2, + RT_DMA_SLAVE_BUSWIDTH_3_BYTES = 3, + RT_DMA_SLAVE_BUSWIDTH_4_BYTES = 4, + RT_DMA_SLAVE_BUSWIDTH_8_BYTES = 8, + RT_DMA_SLAVE_BUSWIDTH_16_BYTES = 16, + RT_DMA_SLAVE_BUSWIDTH_32_BYTES = 32, + RT_DMA_SLAVE_BUSWIDTH_64_BYTES = 64, + RT_DMA_SLAVE_BUSWIDTH_128_BYTES = 128, + + RT_DMA_SLAVE_BUSWIDTH_BYTES_MAX, +}; + +struct rt_dma_slave_config +{ + enum rt_dma_transfer_direction direction; + enum rt_dma_slave_buswidth src_addr_width; + enum rt_dma_slave_buswidth dst_addr_width; + + rt_ubase_t src_addr; + rt_ubase_t dst_addr; + + rt_uint32_t src_maxburst; + rt_uint32_t dst_maxburst; + rt_uint32_t src_port_window_size; + rt_uint32_t dst_port_window_size; +}; + +struct rt_dma_slave_transfer +{ + rt_ubase_t src_addr; + rt_ubase_t dst_addr; + + void *buffer; + rt_ubase_t dma_handle; + rt_size_t buffer_len; + rt_size_t period_len; +}; + +struct rt_dma_controller +{ + rt_list_t list; + + struct rt_device *dev; + + RT_BITMAP_DECLARE(dir_cap, RT_DMA_DIR_MAX); + const struct rt_dma_controller_ops *ops; + + rt_list_t channels_nodes; + struct rt_mutex mutex; +}; + +struct rt_dma_controller_ops +{ + struct rt_dma_chan *(*request_chan)(struct rt_dma_controller *ctrl, + struct rt_device *slave, void *fw_data); + rt_err_t (*release_chan)(struct rt_dma_chan *chan); + + rt_err_t (*start)(struct rt_dma_chan *chan); + rt_err_t (*stop)(struct rt_dma_chan *chan); + rt_err_t (*config)(struct rt_dma_chan *chan, struct rt_dma_slave_config *conf); + + rt_err_t (*prep_memcpy)(struct rt_dma_chan *chan, + rt_ubase_t dma_addr_src, rt_ubase_t dma_addr_dst, rt_size_t len); + + rt_err_t (*prep_cyclic)(struct rt_dma_chan *chan, + rt_ubase_t dma_buf_addr, rt_size_t buf_len, rt_size_t period_len, + enum rt_dma_transfer_direction dir); + + rt_err_t (*prep_single)(struct rt_dma_chan *chan, + rt_ubase_t dma_buf_addr, rt_size_t buf_len, + enum rt_dma_transfer_direction dir); +}; + +struct rt_dma_chan +{ + const char *name; + + struct rt_dma_controller *ctrl; + struct rt_device *slave; + + rt_list_t list; + rt_err_t conf_err; + rt_err_t prep_err; + struct rt_dma_slave_config conf; + struct rt_dma_slave_transfer transfer; + + void (*callback)(struct rt_dma_chan *chan, rt_size_t size); + + void *priv; +}; + +struct rt_dma_pool +{ + rt_region_t region; + + rt_list_t list; + + rt_ubase_t flags; + + rt_bitmap_t *map; + rt_size_t bits; + rt_ubase_t start; + + struct rt_device *dev; +}; + +struct rt_dma_map_ops +{ + void *(*alloc)(struct rt_device *dev, rt_size_t size, + rt_ubase_t *dma_handle, rt_ubase_t flags); + void (*free)(struct rt_device *dev, rt_size_t size, + void *cpu_addr, rt_ubase_t dma_handle, rt_ubase_t flags); + rt_err_t (*sync_out_data)(struct rt_device *dev, void *data, rt_size_t size, + rt_ubase_t *dma_handle, rt_ubase_t flags); + rt_err_t (*sync_in_data)(struct rt_device *dev, void *out_data, rt_size_t size, + rt_ubase_t dma_handle, rt_ubase_t flags); +}; + +rt_inline void rt_dma_controller_add_direction(struct rt_dma_controller *ctrl, + enum rt_dma_transfer_direction dir) +{ + RT_ASSERT(ctrl != RT_NULL); + RT_ASSERT(dir < RT_DMA_DIR_MAX); + + rt_bitmap_set_bit(ctrl->dir_cap, dir); +} + +rt_err_t rt_dma_controller_register(struct rt_dma_controller *ctrl); +rt_err_t rt_dma_controller_unregister(struct rt_dma_controller *ctrl); + +rt_err_t rt_dma_chan_start(struct rt_dma_chan *chan); +rt_err_t rt_dma_chan_stop(struct rt_dma_chan *chan); +rt_err_t rt_dma_chan_config(struct rt_dma_chan *chan, + struct rt_dma_slave_config *conf); +rt_err_t rt_dma_chan_done(struct rt_dma_chan *chan, rt_size_t size); + +rt_err_t rt_dma_prep_memcpy(struct rt_dma_chan *chan, + struct rt_dma_slave_transfer *transfer); +rt_err_t rt_dma_prep_cyclic(struct rt_dma_chan *chan, + struct rt_dma_slave_transfer *transfer); +rt_err_t rt_dma_prep_single(struct rt_dma_chan *chan, + struct rt_dma_slave_transfer *transfer); + +struct rt_dma_chan *rt_dma_chan_request(struct rt_device *dev, const char *name); +rt_err_t rt_dma_chan_release(struct rt_dma_chan *chan); + +#define RT_DMA_F_LINEAR RT_BIT(0) +#define RT_DMA_F_32BITS RT_BIT(1) +#define RT_DMA_F_NOCACHE RT_BIT(2) +#define RT_DMA_F_DEVICE RT_BIT(3) +#define RT_DMA_F_NOMAP RT_BIT(4) + +#define RT_DMA_PAGE_SIZE ARCH_PAGE_SIZE + +void *rt_dma_alloc(struct rt_device *dev, rt_size_t size, + rt_ubase_t *dma_handle, rt_ubase_t flags); + +void rt_dma_free(struct rt_device *dev, rt_size_t size, + void *cpu_addr, rt_ubase_t dma_handle, rt_ubase_t flags); + +rt_inline void *rt_dma_alloc_coherent(struct rt_device *dev, rt_size_t size, + rt_ubase_t *dma_handle) +{ + return rt_dma_alloc(dev, size, dma_handle, + RT_DMA_F_NOCACHE | RT_DMA_F_LINEAR); +} + +rt_inline void rt_dma_free_coherent(struct rt_device *dev, rt_size_t size, + void *cpu_addr, rt_ubase_t dma_handle) +{ + rt_dma_free(dev, size, cpu_addr, dma_handle, + RT_DMA_F_NOCACHE | RT_DMA_F_LINEAR); +} + +rt_err_t rt_dma_sync_out_data(struct rt_device *dev, void *data, rt_size_t size, + rt_ubase_t *dma_handle, rt_ubase_t flags); +rt_err_t rt_dma_sync_in_data(struct rt_device *dev, void *out_data, rt_size_t size, + rt_ubase_t dma_handle, rt_ubase_t flags); + +rt_inline rt_bool_t rt_dma_device_is_coherent(struct rt_device *dev) +{ + return rt_dm_dev_prop_read_bool(dev, "dma-coherent"); +} + +rt_inline void rt_dma_device_set_ops(struct rt_device *dev, + const struct rt_dma_map_ops *ops) +{ + dev->dma_ops = ops; +} + +struct rt_dma_pool *rt_dma_pool_install(rt_region_t *region); +rt_err_t rt_dma_pool_extract(rt_region_t *region_list, rt_size_t list_len, + rt_size_t cma_size, rt_size_t coherent_pool_size); + +#endif /* __DMA_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/gpt.h b/rt-thread/components/drivers/include/drivers/gpt.h deleted file mode 100644 index b887847..0000000 --- a/rt-thread/components/drivers/include/drivers/gpt.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-05-05 linzhenxing first version - */ -#ifndef __GPT_H -#define __GPT_H - -#include -#include - -typedef struct -{ - uint8_t b[16]; /* GUID 16 bytes*/ -} guid_t; - -#define MSDOS_MBR_SIGNATURE 0xaa55 -#define EFI_PMBR_OSTYPE_EFI 0xEF -#define EFI_PMBR_OSTYPE_EFI_GPT 0xEE - -#define GPT_MBR_PROTECTIVE 1 -#define GPT_MBR_HYBRID 2 - -#define GPT_HEADER_SIGNATURE 0x5452415020494645ULL -#define GPT_HEADER_REVISION_V1 0x00010000 -#define GPT_PRIMARY_PARTITION_TABLE_LBA 1 - -typedef guid_t gpt_guid_t __attribute__ ((aligned (4))); -#define EFI_GUID(a, b, c, d...) (gpt_guid_t){ { \ - (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \ - (b) & 0xff, ((b) >> 8) & 0xff, \ - (c) & 0xff, ((c) >> 8) & 0xff, d } } - -#define NULL_GUID \ - EFI_GUID(0x00000000, 0x0000, 0x0000,\ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00) -#define PARTITION_SYSTEM_GUID \ - EFI_GUID( 0xC12A7328, 0xF81F, 0x11d2, \ - 0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B) -#define LEGACY_MBR_PARTITION_GUID \ - EFI_GUID( 0x024DEE41, 0x33E7, 0x11d3, \ - 0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F) -#define PARTITION_MSFT_RESERVED_GUID \ - EFI_GUID( 0xE3C9E316, 0x0B5C, 0x4DB8, \ - 0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE) -#define PARTITION_BASIC_DATA_GUID \ - EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \ - 0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7) -#define PARTITION_LINUX_RAID_GUID \ - EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \ - 0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e) -#define PARTITION_LINUX_SWAP_GUID \ - EFI_GUID( 0x0657fd6d, 0xa4ab, 0x43c4, \ - 0x84, 0xe5, 0x09, 0x33, 0xc8, 0x4b, 0x4f, 0x4f) -#define PARTITION_LINUX_LVM_GUID \ - EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \ - 0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28) -#pragma pack(push, 1) -typedef struct _gpt_header -{ - uint64_t signature; - uint32_t revision; - uint32_t header_size; - uint32_t header_crc32; - uint32_t reserved1; - uint64_t start_lba; /*GPT head start sector*/ - uint64_t alternate_lba; /*GPT head alternate sector*/ - uint64_t first_usable_lba; - uint64_t last_usable_lba; - gpt_guid_t disk_guid; - uint64_t partition_entry_lba; - uint32_t num_partition_entries; - uint32_t sizeof_partition_entry; - uint32_t partition_entry_array_crc32; - - /* The rest of the logical block is reserved by UEFI and must be zero. - * EFI standard handles this by: - * - * uint8_t reserved2[ BlockSize - 92 ]; - */ -} gpt_header; - -typedef struct _gpt_entry_attributes -{ - uint64_t required_to_function:1; - uint64_t reserved:47; - uint64_t type_guid_specific:16; -} gpt_entry_attributes; - -typedef struct _gpt_entry -{ - gpt_guid_t partition_type_guid; - gpt_guid_t unique_partition_guid; - uint64_t starting_lba; - uint64_t ending_lba; - gpt_entry_attributes attributes; - uint16_t partition_name[72/sizeof(uint16_t)]; -} gpt_entry; - -typedef struct _gpt_mbr_record -{ - uint8_t boot_indicator; /* unused by EFI, set to 0x80 for bootable */ - uint8_t start_head; /* unused by EFI, pt start in CHS */ - uint8_t start_sector; /* unused by EFI, pt start in CHS */ - uint8_t start_track; - uint8_t os_type; /* EFI and legacy non-EFI OS types */ - uint8_t end_head; /* unused by EFI, pt end in CHS */ - uint8_t end_sector; /* unused by EFI, pt end in CHS */ - uint8_t end_track; /* unused by EFI, pt end in CHS */ - uint32_t starting_lba; /* used by EFI - start addr of the on disk pt */ - uint32_t size_in_lba; /* used by EFI - size of pt in LBA */ -} gpt_mbr_record; - - -typedef struct _legacy_mbr -{ - uint8_t boot_code[440]; - uint32_t unique_mbr_signature; - uint16_t unknown; - gpt_mbr_record partition_record[4]; - uint16_t signature; -} legacy_mbr; -#pragma pack(pop) - -int check_gpt(struct rt_mmcsd_card *card); -int gpt_get_partition_param(struct rt_mmcsd_card *card, struct dfs_partition *part, uint32_t pindex); -void gpt_free(void); -#endif /*__GPT_H*/ diff --git a/rt-thread/components/drivers/include/drivers/i2c.h b/rt-thread/components/drivers/include/drivers/i2c.h deleted file mode 100644 index 0473a1e..0000000 --- a/rt-thread/components/drivers/include/drivers/i2c.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-04-25 weety first version - * 2021-04-20 RiceChen added support for bus control api - */ - -#ifndef __I2C_H__ -#define __I2C_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define RT_I2C_WR 0x0000 -#define RT_I2C_RD (1u << 0) -#define RT_I2C_ADDR_10BIT (1u << 2) /* this is a ten bit chip address */ -#define RT_I2C_NO_START (1u << 4) -#define RT_I2C_IGNORE_NACK (1u << 5) -#define RT_I2C_NO_READ_ACK (1u << 6) /* when I2C reading, we do not ACK */ -#define RT_I2C_NO_STOP (1u << 7) - -struct rt_i2c_msg -{ - rt_uint16_t addr; - rt_uint16_t flags; - rt_uint16_t len; - rt_uint8_t *buf; -}; - -struct rt_i2c_bus_device; - -struct rt_i2c_bus_device_ops -{ - rt_ssize_t (*master_xfer)(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num); - rt_ssize_t (*slave_xfer)(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num); - rt_err_t (*i2c_bus_control)(struct rt_i2c_bus_device *bus, - int cmd, - void *args); -}; - -/*for i2c bus driver*/ -struct rt_i2c_bus_device -{ - struct rt_device parent; - const struct rt_i2c_bus_device_ops *ops; - rt_uint16_t flags; - struct rt_mutex lock; - rt_uint32_t timeout; - rt_uint32_t retries; - void *priv; -}; - -struct rt_i2c_client -{ -#ifdef RT_USING_DM - struct rt_device parent; - - const char *name; - const struct rt_i2c_device_id *id; - const struct rt_ofw_node_id *ofw_id; -#endif - struct rt_i2c_bus_device *bus; - rt_uint16_t client_addr; -}; - -#ifdef RT_USING_DM -struct rt_i2c_device_id -{ - char name[20]; - void *data; -}; - -struct rt_i2c_driver -{ - struct rt_driver parent; - - const struct rt_i2c_device_id *ids; - const struct rt_ofw_node_id *ofw_ids; - - rt_err_t (*probe)(struct rt_i2c_client *client); - rt_err_t (*remove)(struct rt_i2c_client *client); - rt_err_t (*shutdown)(struct rt_i2c_client *client); -}; - -rt_err_t rt_i2c_driver_register(struct rt_i2c_driver *driver); -rt_err_t rt_i2c_device_register(struct rt_i2c_client *client); - -#define RT_I2C_DRIVER_EXPORT(driver) RT_DRIVER_EXPORT(driver, i2c, BUILIN) -#endif /* RT_USING_DM */ - -rt_err_t rt_i2c_bus_device_register(struct rt_i2c_bus_device *bus, - const char *bus_name); -struct rt_i2c_bus_device *rt_i2c_bus_device_find(const char *bus_name); -rt_ssize_t rt_i2c_transfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num); -rt_err_t rt_i2c_control(struct rt_i2c_bus_device *bus, - int cmd, - void *args); -rt_ssize_t rt_i2c_master_send(struct rt_i2c_bus_device *bus, - rt_uint16_t addr, - rt_uint16_t flags, - const rt_uint8_t *buf, - rt_uint32_t count); -rt_ssize_t rt_i2c_master_recv(struct rt_i2c_bus_device *bus, - rt_uint16_t addr, - rt_uint16_t flags, - rt_uint8_t *buf, - rt_uint32_t count); - -rt_inline rt_err_t rt_i2c_bus_lock(struct rt_i2c_bus_device *bus, rt_tick_t timeout) -{ - return rt_mutex_take(&bus->lock, timeout); -} - -rt_inline rt_err_t rt_i2c_bus_unlock(struct rt_i2c_bus_device *bus) -{ - return rt_mutex_release(&bus->lock); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/rt-thread/components/drivers/include/drivers/i2c_dev.h b/rt-thread/components/drivers/include/drivers/i2c_dev.h deleted file mode 100644 index 6744fa1..0000000 --- a/rt-thread/components/drivers/include/drivers/i2c_dev.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-04-25 weety first version - * 2021-04-20 RiceChen added bus clock command - */ - -#ifndef __I2C_DEV_H__ -#define __I2C_DEV_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define RT_I2C_DEV_CTRL_10BIT (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x01) -#define RT_I2C_DEV_CTRL_ADDR (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x02) -#define RT_I2C_DEV_CTRL_TIMEOUT (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x03) -#define RT_I2C_DEV_CTRL_RW (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x04) -#define RT_I2C_DEV_CTRL_CLK (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x05) -#define RT_I2C_DEV_CTRL_UNLOCK (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x06) -#define RT_I2C_DEV_CTRL_GET_STATE (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x07) -#define RT_I2C_DEV_CTRL_GET_MODE (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x08) -#define RT_I2C_DEV_CTRL_GET_ERROR (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x09) - -struct rt_i2c_priv_data -{ - struct rt_i2c_msg *msgs; - rt_size_t number; -}; - -rt_err_t rt_i2c_bus_device_device_init(struct rt_i2c_bus_device *bus, - const char *name); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/rt-thread/components/drivers/include/drivers/iio.h b/rt-thread/components/drivers/include/drivers/iio.h new file mode 100644 index 0000000..c69f507 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/iio.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-3-08 GuEe-GUI the first version + */ + +#ifndef __IIO_H__ +#define __IIO_H__ + +void *rt_iio_channel_get_by_index(struct rt_device *dev, int index, int *out_channel); +void *rt_iio_channel_get_by_name(struct rt_device *dev, const char *name, int *out_channel); + +#endif /* __IIO_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/led.h b/rt-thread/components/drivers/include/drivers/led.h new file mode 100644 index 0000000..aeb80a6 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/led.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-3-08 GuEe-GUI the first version + */ + +#ifndef __LED_H__ +#define __LED_H__ + +#include +#include + +struct rt_led_ops; + +enum rt_led_state +{ + RT_LED_S_OFF, + RT_LED_S_ON, + RT_LED_S_TOGGLE, + RT_LED_S_BLINK, + + RT_LED_STATE_NR, +}; + +struct rt_led_device +{ + struct rt_device parent; + + const struct rt_led_ops *ops; + + struct rt_spinlock spinlock; + + void *sysdata; + void *priv; +}; + +struct rt_led_ops +{ + rt_err_t (*set_state)(struct rt_led_device *led, enum rt_led_state state); + rt_err_t (*get_state)(struct rt_led_device *led, enum rt_led_state *out_state); + rt_err_t (*set_period)(struct rt_led_device *led, rt_uint32_t period_ms); + rt_err_t (*set_brightness)(struct rt_led_device *led, rt_uint32_t brightness); +}; + +rt_err_t rt_hw_led_register(struct rt_led_device *led); +rt_err_t rt_hw_led_unregister(struct rt_led_device *led); + +rt_err_t rt_led_set_state(struct rt_led_device *led, enum rt_led_state state); +rt_err_t rt_led_get_state(struct rt_led_device *led, enum rt_led_state *out_state); +rt_err_t rt_led_set_period(struct rt_led_device *led, rt_uint32_t period_ms); +rt_err_t rt_led_set_brightness(struct rt_led_device *led, rt_uint32_t brightness); + +#endif /* __LED_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/mailbox.h b/rt-thread/components/drivers/include/drivers/mailbox.h new file mode 100644 index 0000000..954cd62 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/mailbox.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#ifndef __MAILBOX_H__ +#define __MAILBOX_H__ + +#include +#include + +struct rt_mbox_chan; +struct rt_mbox_client; +struct rt_mbox_controller_ops; + +struct rt_mbox_controller +{ + rt_list_t list; + + struct rt_device *dev; + + const struct rt_mbox_controller_ops *ops; + + rt_size_t num_chans; + struct rt_mbox_chan *chans; +}; + +struct rt_mbox_controller_ops +{ + rt_err_t (*request)(struct rt_mbox_chan *); + void (*release)(struct rt_mbox_chan *); + rt_err_t (*send)(struct rt_mbox_chan *, const void *data); + rt_bool_t (*peek)(struct rt_mbox_chan *); + int (*ofw_parse)(struct rt_mbox_controller *, struct rt_ofw_cell_args *); +}; + +struct rt_mbox_chan +{ + struct rt_mbox_controller *ctrl; + struct rt_mbox_client *client; + + void *data; + rt_bool_t complete; + struct rt_timer timer; + struct rt_spinlock lock; + + void *priv; +}; + +struct rt_mbox_client +{ + struct rt_device *dev; + + void (*rx_callback)(struct rt_mbox_client *, void *data); + void (*tx_prepare)(struct rt_mbox_client *, const void *data); + void (*tx_done)(struct rt_mbox_client *, const void *data, rt_err_t err); +}; + +rt_err_t rt_mbox_controller_register(struct rt_mbox_controller *ctrl); +rt_err_t rt_mbox_controller_unregister(struct rt_mbox_controller *ctrl); + +rt_err_t rt_mbox_send(struct rt_mbox_chan *chan, const void *data, + rt_uint32_t timeout_ms); +void rt_mbox_send_done(struct rt_mbox_chan *chan, rt_err_t err); +rt_bool_t rt_mbox_peek(struct rt_mbox_chan *chan); +rt_err_t rt_mbox_recv(struct rt_mbox_chan *chan, void *data); + +struct rt_mbox_chan *rt_mbox_request_by_index(struct rt_mbox_client *client, int index); +struct rt_mbox_chan *rt_mbox_request_by_name(struct rt_mbox_client *client, char *name); +rt_err_t rt_mbox_release(struct rt_mbox_chan *chan); + +#endif /* __MAILBOX_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/misc.h b/rt-thread/components/drivers/include/drivers/misc.h index aa2b715..ea962a2 100644 --- a/rt-thread/components/drivers/include/drivers/misc.h +++ b/rt-thread/components/drivers/include/drivers/misc.h @@ -12,6 +12,7 @@ #define __MISC_H__ #include +#include #ifdef ARCH_CPU_64BIT #define RT_BITS_PER_LONG 64 @@ -33,6 +34,15 @@ (((__x) - ((__d) / 2)) / (__d)); \ }) +#define __KEY_PLACEHOLDER_1 0, +#define ____KEY_ENABLED(__ignored, val, ...) val +#define ___KEY_ENABLED(arg1_or_junk) ____KEY_ENABLED(arg1_or_junk 1, 0) +#define __KEY_ENABLED(value) ___KEY_ENABLED(__KEY_PLACEHOLDER_##value) +#define RT_KEY_ENABLED(key) __KEY_ENABLED(key) + +#define RT_FIELD_PREP(mask, val) (((rt_uint64_t)(val) << (__rt_ffsl((mask)) - 1)) & (mask)) +#define RT_FIELD_GET(mask, val) (((val) & (mask)) >> (__rt_ffsl((mask)) - 1)) + #define RT_BIT(n) (1UL << (n)) #define RT_BIT_ULL(n) (1ULL << (n)) #define RT_BIT_MASK(nr) (1UL << ((nr) % RT_BITS_PER_LONG)) @@ -48,6 +58,19 @@ #define RT_ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) +#define rt_offsetof(s, field) ((rt_size_t)&((s *)0)->field) + +#define rt_err_ptr(err) ((void *)(rt_base_t)(err)) +#define rt_ptr_err(ptr) ((rt_err_t)(rt_base_t)(ptr)) +#define rt_is_err_value(ptr) ((rt_ubase_t)(void *)(ptr) >= (rt_ubase_t)-4095) +#define rt_is_err(ptr) rt_is_err_value(ptr) +#define rt_is_err_or_null(ptr) (!(ptr) || rt_is_err_value((rt_ubase_t)(ptr))) + +#define rt_upper_32_bits(n) ((rt_uint32_t)(((n) >> 16) >> 16)) +#define rt_lower_32_bits(n) ((rt_uint32_t)((n) & 0xffffffff)) +#define rt_upper_16_bits(n) ((rt_uint16_t)((n) >> 16)) +#define rt_lower_16_bits(n) ((rt_uint16_t)((n) & 0xffff)) + #define rt_min(x, y) \ ({ \ typeof(x) _x = (x); \ @@ -71,6 +94,13 @@ _x < _y ? _x: _y; \ }) +#define rt_max_t(type, x, y) \ +({ \ + type _x = (x); \ + type _y = (y); \ + _x > _y ? _x: _y; \ +}) + #define rt_clamp(val, lo, hi) rt_min((typeof(val))rt_max(val, lo), hi) #define rt_do_div(n, base) \ @@ -83,4 +113,34 @@ _rem; \ }) +#define rt_abs(x) \ +({ \ + long ret; \ + if (sizeof(x) == sizeof(long)) \ + { \ + long __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } \ + else \ + { \ + int __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } \ + ret; \ +}) + +#ifndef rt_ilog2 +rt_inline int rt_ilog2(rt_ubase_t v) +{ + int l = 0; + + while ((1UL << l) < v) + { + l++; + } + + return l; +} +#endif /* !rt_ilog2 */ + #endif /* __MISC_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/mmcsd_card.h b/rt-thread/components/drivers/include/drivers/mmcsd_card.h index 13173f1..6d86760 100644 --- a/rt-thread/components/drivers/include/drivers/mmcsd_card.h +++ b/rt-thread/components/drivers/include/drivers/mmcsd_card.h @@ -218,7 +218,7 @@ struct rt_mmcsd_card { struct rt_sdio_cccr cccr; /* common card info */ struct rt_sdio_cis cis; /* common tuple info */ struct rt_sdio_function *sdio_function[SDIO_MAX_FUNCTIONS + 1]; /* SDIO functions (devices) */ - rt_list_t blk_devices; /* for block device list */ + void *blk_dev; struct rt_mmc_ext_csd ext_csd; }; diff --git a/rt-thread/components/drivers/include/drivers/mmcsd_host.h b/rt-thread/components/drivers/include/drivers/mmcsd_host.h index 73c1b97..5632ee1 100644 --- a/rt-thread/components/drivers/include/drivers/mmcsd_host.h +++ b/rt-thread/components/drivers/include/drivers/mmcsd_host.h @@ -134,6 +134,7 @@ struct rt_mmcsd_host #define MMCSD_SUP_HS200_1V2 (1 << 10) #define MMCSD_SUP_HS200 (MMCSD_SUP_HS200_1V2 | MMCSD_SUP_HS200_1V8) /* hs200 sdr */ #define MMCSD_SUP_NONREMOVABLE (1 << 11) +#define controller_is_removable(host) (!(host->flags & MMCSD_SUP_NONREMOVABLE)) #define MMCSD_SUP_HS400_1V8 (1 << 12) #define MMCSD_SUP_HS400_1V2 (1 << 13) #define MMCSD_SUP_HS400 (MMCSD_SUP_HS400_1V2 | MMCSD_SUP_HS400_1V8) /* hs400 ddr */ diff --git a/rt-thread/components/drivers/include/drivers/nvme.h b/rt-thread/components/drivers/include/drivers/nvme.h new file mode 100644 index 0000000..1eca5d9 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/nvme.h @@ -0,0 +1,899 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#ifndef __NVME_H__ +#define __NVME_H__ + +#include +#include +#include + +#define NVME_RSVD(offset, bytes_size) rt_uint8_t __rsvd##offset[bytes_size] + +enum +{ + /* + * Generic Command Status: + */ + RT_NVME_SC_SUCCESS = 0x0, + RT_NVME_SC_INVALID_OPCODE = 0x1, + RT_NVME_SC_INVALID_FIELD = 0x2, + RT_NVME_SC_CMDID_CONFLICT = 0x3, + RT_NVME_SC_DATA_XFER_ERROR = 0x4, + RT_NVME_SC_POWER_LOSS = 0x5, + RT_NVME_SC_INTERNAL = 0x6, + RT_NVME_SC_ABORT_REQ = 0x7, + RT_NVME_SC_ABORT_QUEUE = 0x8, + RT_NVME_SC_FUSED_FAIL = 0x9, + RT_NVME_SC_FUSED_MISSING = 0xa, + RT_NVME_SC_INVALID_NS = 0xb, + RT_NVME_SC_CMD_SEQ_ERROR = 0xc, + RT_NVME_SC_SGL_INVALID_LAST = 0xd, + RT_NVME_SC_SGL_INVALID_COUNT = 0xe, + RT_NVME_SC_SGL_INVALID_DATA = 0xf, + RT_NVME_SC_SGL_INVALID_METADATA = 0x10, + RT_NVME_SC_SGL_INVALID_TYPE = 0x11, + RT_NVME_SC_CMB_INVALID_USE = 0x12, + RT_NVME_SC_PRP_INVALID_OFFSET = 0x13, + RT_NVME_SC_ATOMIC_WU_EXCEEDED = 0x14, + RT_NVME_SC_OP_DENIED = 0x15, + RT_NVME_SC_SGL_INVALID_OFFSET = 0x16, + RT_NVME_SC_RESERVED = 0x17, + RT_NVME_SC_HOST_ID_INCONSIST = 0x18, + RT_NVME_SC_KA_TIMEOUT_EXPIRED = 0x19, + RT_NVME_SC_KA_TIMEOUT_INVALID = 0x1a, + RT_NVME_SC_ABORTED_PREEMPT_ABORT = 0x1b, + RT_NVME_SC_SANITIZE_FAILED = 0x1c, + RT_NVME_SC_SANITIZE_IN_PROGRESS = 0x1d, + RT_NVME_SC_SGL_INVALID_GRANULARITY = 0x1e, + RT_NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1f, + RT_NVME_SC_NS_WRITE_PROTECTED = 0x20, + RT_NVME_SC_CMD_INTERRUPTED = 0x21, + RT_NVME_SC_TRANSIENT_TR_ERR = 0x22, + RT_NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24, + RT_NVME_SC_INVALID_IO_CMD_SET = 0x2c, + + RT_NVME_SC_LBA_RANGE = 0x80, + RT_NVME_SC_CAP_EXCEEDED = 0x81, + RT_NVME_SC_NS_NOT_READY = 0x82, + RT_NVME_SC_RESERVATION_CONFLICT = 0x83, + RT_NVME_SC_FORMAT_IN_PROGRESS = 0x84, + + /* + * Command Specific Status: + */ + RT_NVME_SC_CQ_INVALID = 0x100, + RT_NVME_SC_QID_INVALID = 0x101, + RT_NVME_SC_QUEUE_SIZE = 0x102, + RT_NVME_SC_ABORT_LIMIT = 0x103, + RT_NVME_SC_ABORT_MISSING = 0x104, + RT_NVME_SC_ASYNC_LIMIT = 0x105, + RT_NVME_SC_FIRMWARE_SLOT = 0x106, + RT_NVME_SC_FIRMWARE_IMAGE = 0x107, + RT_NVME_SC_INVALID_VECTOR = 0x108, + RT_NVME_SC_INVALID_LOG_PAGE = 0x109, + RT_NVME_SC_INVALID_FORMAT = 0x10a, + RT_NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, + RT_NVME_SC_INVALID_QUEUE = 0x10c, + RT_NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, + RT_NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, + RT_NVME_SC_FEATURE_NOT_PER_NS = 0x10f, + RT_NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, + RT_NVME_SC_FW_NEEDS_RESET = 0x111, + RT_NVME_SC_FW_NEEDS_MAX_TIME = 0x112, + RT_NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113, + RT_NVME_SC_OVERLAPPING_RANGE = 0x114, + RT_NVME_SC_NS_INSUFFICIENT_CAP = 0x115, + RT_NVME_SC_NS_ID_UNAVAILABLE = 0x116, + RT_NVME_SC_NS_ALREADY_ATTACHED = 0x118, + RT_NVME_SC_NS_IS_PRIVATE = 0x119, + RT_NVME_SC_NS_NOT_ATTACHED = 0x11a, + RT_NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, + RT_NVME_SC_CTRL_LIST_INVALID = 0x11c, + RT_NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d, + RT_NVME_SC_BP_WRITE_PROHIBITED = 0x11e, + RT_NVME_SC_CTRL_ID_INVALID = 0x11f, + RT_NVME_SC_SEC_CTRL_STATE_INVALID = 0x120, + RT_NVME_SC_CTRL_RES_NUM_INVALID = 0x121, + RT_NVME_SC_RES_ID_INVALID = 0x122, + RT_NVME_SC_PMR_SAN_PROHIBITED = 0x123, + RT_NVME_SC_ANA_GROUP_ID_INVALID = 0x124, + RT_NVME_SC_ANA_ATTACH_FAILED = 0x125, + + /* + * I/O Command Set Specific - NVM commands: + */ + RT_NVME_SC_BAD_ATTRIBUTES = 0x180, + RT_NVME_SC_INVALID_PI = 0x181, + RT_NVME_SC_READ_ONLY = 0x182, + RT_NVME_SC_ONCS_NOT_SUPPORTED = 0x183, + + /* + * I/O Command Set Specific - Fabrics commands: + */ + RT_NVME_SC_CONNECT_FORMAT = 0x180, + RT_NVME_SC_CONNECT_CTRL_BUSY = 0x181, + RT_NVME_SC_CONNECT_INVALID_PARAM = 0x182, + RT_NVME_SC_CONNECT_RESTART_DISC = 0x183, + RT_NVME_SC_CONNECT_INVALID_HOST = 0x184, + + RT_NVME_SC_DISCOVERY_RESTART = 0x190, + RT_NVME_SC_AUTH_REQUIRED = 0x191, + + /* + * I/O Command Set Specific - Zoned commands: + */ + RT_NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8, + RT_NVME_SC_ZONE_FULL = 0x1b9, + RT_NVME_SC_ZONE_READ_ONLY = 0x1ba, + RT_NVME_SC_ZONE_OFFLINE = 0x1bb, + RT_NVME_SC_ZONE_INVALID_WRITE = 0x1bc, + RT_NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd, + RT_NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be, + RT_NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf, + + /* + * Media and Data Integrity Errors: + */ + RT_NVME_SC_WRITE_FAULT = 0x280, + RT_NVME_SC_READ_ERROR = 0x281, + RT_NVME_SC_GUARD_CHECK = 0x282, + RT_NVME_SC_APPTAG_CHECK = 0x283, + RT_NVME_SC_REFTAG_CHECK = 0x284, + RT_NVME_SC_COMPARE_FAILED = 0x285, + RT_NVME_SC_ACCESS_DENIED = 0x286, + RT_NVME_SC_UNWRITTEN_BLOCK = 0x287, + + /* + * Path-related Errors: + */ + RT_NVME_SC_INTERNAL_PATH_ERROR = 0x300, + RT_NVME_SC_ANA_PERSISTENT_LOSS = 0x301, + RT_NVME_SC_ANA_INACCESSIBLE = 0x302, + RT_NVME_SC_ANA_TRANSITION = 0x303, + RT_NVME_SC_CTRL_PATH_ERROR = 0x360, + RT_NVME_SC_HOST_PATH_ERROR = 0x370, + RT_NVME_SC_HOST_ABORTED_CMD = 0x371, + + RT_NVME_SC_CRD = 0x1800, + RT_NVME_SC_MORE = 0x2000, + RT_NVME_SC_DNR = 0x4000, +}; + +/* Admin commands */ +enum +{ + RT_NVME_ADMIN_OPCODE_DELETE_SQ = 0x00, + RT_NVME_ADMIN_OPCODE_CREATE_SQ = 0x01, + RT_NVME_ADMIN_OPCODE_GET_LOG_PAGE = 0x02, + RT_NVME_ADMIN_OPCODE_DELETE_CQ = 0x04, + RT_NVME_ADMIN_OPCODE_CREATE_CQ = 0x05, + RT_NVME_ADMIN_OPCODE_IDENTIFY = 0x06, + RT_NVME_ADMIN_OPCODE_ABORT_CMD = 0x08, + RT_NVME_ADMIN_OPCODE_SET_FEATURES = 0x09, + RT_NVME_ADMIN_OPCODE_GET_FEATURES = 0x0a, + RT_NVME_ADMIN_OPCODE_ASYNC_EVENT = 0x0c, + RT_NVME_ADMIN_OPCODE_NS_MGMT = 0x0d, + RT_NVME_ADMIN_OPCODE_ACTIVATE_FW = 0x10, + RT_NVME_ADMIN_OPCODE_DOWNLOAD_FW = 0x11, + RT_NVME_ADMIN_OPCODE_DEV_SELF_TEST = 0x14, + RT_NVME_ADMIN_OPCODE_NS_ATTACH = 0x15, + RT_NVME_ADMIN_OPCODE_KEEP_ALIVE = 0x18, + RT_NVME_ADMIN_OPCODE_DIRECTIVE_SEND = 0x19, + RT_NVME_ADMIN_OPCODE_DIRECTIVE_RECV = 0x1a, + RT_NVME_ADMIN_OPCODE_VIRTUAL_MGMT = 0x1c, + RT_NVME_ADMIN_OPCODE_NVME_MI_SEND = 0x1d, + RT_NVME_ADMIN_OPCODE_NVME_MI_RECV = 0x1e, + RT_NVME_ADMIN_OPCODE_DBBUF = 0x7c, + RT_NVME_ADMIN_OPCODE_FORMAT_NVM = 0x80, + RT_NVME_ADMIN_OPCODE_SECURITY_SEND = 0x81, + RT_NVME_ADMIN_OPCODE_SECURITY_RECV = 0x82, + RT_NVME_ADMIN_OPCODE_SANITIZE_NVM = 0x84, + RT_NVME_ADMIN_OPCODE_GET_LBA_STATUS = 0x86, + RT_NVME_ADMIN_OPCODE_VENDOR_START = 0xc0, +}; + +/* I/O commands */ +enum +{ + RT_NVME_CMD_FLUSH = 0x00, + RT_NVME_CMD_WRITE = 0x01, + RT_NVME_CMD_READ = 0x02, + RT_NVME_CMD_WRITE_UNCOR = 0x04, + RT_NVME_CMD_COMPARE = 0x05, + RT_NVME_CMD_WRITE_ZEROES = 0x08, + RT_NVME_CMD_DSM = 0x09, + RT_NVME_CMD_VERIFY = 0x0c, + RT_NVME_CMD_RESV_REGISTER = 0x0d, + RT_NVME_CMD_RESV_REPORT = 0x0e, + RT_NVME_CMD_RESV_ACQUIRE = 0x11, + RT_NVME_CMD_RESV_RELEASE = 0x15, + RT_NVME_CMD_ZONE_MGMT_SEND = 0x79, + RT_NVME_CMD_ZONE_MGMT_RECV = 0x7a, + RT_NVME_CMD_ZONE_APPEND = 0x7d, + RT_NVME_CMD_VENDOR_START = 0x80, +}; + +enum +{ + RT_NVME_PSDT_PRP = 0x0, + RT_NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, + RT_NVME_PSDT_SGL_MPTR_SGL = 0x2, +}; + +/* Commands flags */ +enum +{ + RT_NVME_CMD_FLAGS_FUSE_SHIFT = 0x00, + RT_NVME_CMD_FLAGS_PSDT_SHIFT = 0x06, +}; + +struct rt_nvme_command_common +{ + rt_uint8_t opcode; + rt_uint8_t flags; + rt_uint16_t cmdid; + rt_le32_t nsid; + rt_le32_t cmd_dw2[2]; + rt_le64_t metadata; + rt_le64_t prp1; + rt_le64_t prp2; + rt_le32_t cmd_dw10[6]; +}; + +rt_packed(struct rt_nvme_sgl_desc +{ + rt_le64_t adddress; + rt_le32_t length; + rt_uint8_t reserved[3]; +#define SGL_DESC_TYPE_DATA_BLOCK 0x0 +#define SGL_DESC_TYPE_BIT_BUCKET 0x1 +#define SGL_DESC_TYPE_SEGMENT 0x2 +#define SGL_DESC_TYPE_LAST_SEGMENT 0x3 +#define SGL_DESC_TYPE_KEYED_DATA_BLOCK 0x4 +#define SGL_DESC_TYPE_VENDOR_SPECIFIC 0xf + rt_uint8_t sgl_identify; +}); + +struct rt_nvme_command_rw +{ + rt_uint8_t opcode; + rt_uint8_t flags; + rt_uint16_t cmdid; + rt_le32_t nsid; + NVME_RSVD(8, 8); + rt_le64_t metadata; + union + { + struct + { + rt_le64_t prp1; + rt_le64_t prp2; + }; + struct rt_nvme_sgl_desc sgl; + }; + rt_le64_t slba; + rt_le16_t length; + rt_le16_t control; + rt_le32_t dsmgmt; + rt_le32_t reftag; + rt_le16_t apptag; + rt_le16_t appmask; +}; + +enum +{ + RT_NVME_RW_LR = 1 << 15, + RT_NVME_RW_FUA = 1 << 14, + RT_NVME_RW_APPEND_PIREMAP = 1 << 9, + RT_NVME_RW_DSM_FREQ_UNSPEC = 0, + RT_NVME_RW_DSM_FREQ_TYPICAL = 1, + RT_NVME_RW_DSM_FREQ_RARE = 2, + RT_NVME_RW_DSM_FREQ_READS = 3, + RT_NVME_RW_DSM_FREQ_WRITES = 4, + RT_NVME_RW_DSM_FREQ_RW = 5, + RT_NVME_RW_DSM_FREQ_ONCE = 6, + RT_NVME_RW_DSM_FREQ_PREFETCH = 7, + RT_NVME_RW_DSM_FREQ_TEMP = 8, + RT_NVME_RW_DSM_LATENCY_NONE = 0 << 4, + RT_NVME_RW_DSM_LATENCY_IDLE = 1 << 4, + RT_NVME_RW_DSM_LATENCY_NORM = 2 << 4, + RT_NVME_RW_DSM_LATENCY_LOW = 3 << 4, + RT_NVME_RW_DSM_SEQ_REQ = 1 << 6, + RT_NVME_RW_DSM_COMPRESSED = 1 << 7, + RT_NVME_RW_PRINFO_PRCHK_REF = 1 << 10, + RT_NVME_RW_PRINFO_PRCHK_APP = 1 << 11, + RT_NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, + RT_NVME_RW_PRINFO_PRACT = 1 << 13, + RT_NVME_RW_DTYPE_STREAMS = 1 << 4, + RT_NVME_WZ_DEAC = 1 << 9, +}; + +enum +{ + RT_NVME_QUEUE_PHYS_CONTIG = (1 << 0), + RT_NVME_CQ_IRQ_ENABLED = (1 << 1), + RT_NVME_SQ_PRIO_URGENT = (0 << 1), + RT_NVME_SQ_PRIO_HIGH = (1 << 1), + RT_NVME_SQ_PRIO_MEDIUM = (2 << 1), + RT_NVME_SQ_PRIO_LOW = (3 << 1), + RT_NVME_FEAT_ARBITRATION = 0x01, + RT_NVME_FEAT_POWER_MGMT = 0x02, + RT_NVME_FEAT_LBA_RANGE = 0x03, + RT_NVME_FEAT_TEMP_THRESH = 0x04, + RT_NVME_FEAT_ERR_RECOVERY = 0x05, + RT_NVME_FEAT_VOLATILE_WC = 0x06, + RT_NVME_FEAT_NUM_QUEUES = 0x07, + RT_NVME_FEAT_IRQ_COALESCE = 0x08, + RT_NVME_FEAT_IRQ_CONFIG = 0x09, + RT_NVME_FEAT_WRITE_ATOMIC = 0x0a, + RT_NVME_FEAT_ASYNC_EVENT = 0x0b, + RT_NVME_FEAT_AUTO_PST = 0x0c, + RT_NVME_FEAT_SW_PROGRESS = 0x80, + RT_NVME_FEAT_HOST_ID = 0x81, + RT_NVME_FEAT_RESV_MASK = 0x82, + RT_NVME_FEAT_RESV_PERSIST = 0x83, + RT_NVME_LOG_ERROR = 0x01, + RT_NVME_LOG_SMART = 0x02, + RT_NVME_LOG_FW_SLOT = 0x03, + RT_NVME_LOG_RESERVATION = 0x80, + RT_NVME_FWACT_REPL = (0 << 3), + RT_NVME_FWACT_REPL_ACTV = (1 << 3), + RT_NVME_FWACT_ACTV = (2 << 3), +}; + +struct rt_nvme_command_identify +{ + rt_uint8_t opcode; + rt_uint8_t flags; + rt_uint16_t cmdid; + rt_le32_t nsid; + NVME_RSVD(8, 16); + rt_le64_t prp1; + rt_le64_t prp2; + rt_le32_t cns; + NVME_RSVD(64, 20); +}; + +struct rt_nvme_command_features +{ + rt_uint8_t opcode; + rt_uint8_t flags; + rt_uint16_t cmdid; + rt_le32_t nsid; + NVME_RSVD(8, 16); + rt_le64_t prp1; + rt_le64_t prp2; + rt_le32_t fid; + rt_le32_t dword11; + NVME_RSVD(68, 16); +}; + +struct rt_nvme_command_create_cq +{ + rt_uint8_t opcode; + rt_uint8_t flags; + rt_uint16_t cmdid; + NVME_RSVD(4, 20); + rt_le64_t prp1; + NVME_RSVD(32, 8); + rt_le16_t cqid; + rt_le16_t qsize; + rt_le16_t cq_flags; + rt_le16_t irq_vector; + NVME_RSVD(104, 16); +}; + +struct rt_nvme_command_create_sq +{ + rt_uint8_t opcode; + rt_uint8_t flags; + rt_uint16_t cmdid; + NVME_RSVD(4, 20); + rt_le64_t prp1; + NVME_RSVD(32, 8); + rt_le16_t sqid; + rt_le16_t qsize; + rt_le16_t sq_flags; + rt_le16_t cqid; + NVME_RSVD(104, 16); +}; + +struct rt_nvme_command_delete_queue +{ + rt_uint8_t opcode; + rt_uint8_t flags; + rt_uint16_t cmdid; + NVME_RSVD(4, 36); + rt_le16_t qid; + NVME_RSVD(42, 22); +}; + +struct rt_nvme_command_write_zeroes +{ + rt_uint8_t opcode; + rt_uint8_t flags; + rt_uint16_t cmdid; + rt_le32_t nsid; + NVME_RSVD(8, 8); + rt_le64_t metadata; + rt_le64_t prp1; + rt_le64_t prp2; + rt_le64_t slba; + rt_le16_t length; + rt_le16_t control; + rt_le32_t dsmgmt; + rt_le32_t reftag; + rt_le16_t apptag; + rt_le16_t appmask; +}; + +struct rt_nvme_command +{ + union + { + struct rt_nvme_command_common common; + struct rt_nvme_command_rw rw; + struct rt_nvme_command_identify identify; + struct rt_nvme_command_features features; + struct rt_nvme_command_create_cq create_cq; + struct rt_nvme_command_create_sq create_sq; + struct rt_nvme_command_delete_queue delete_queue; + struct rt_nvme_command_write_zeroes write_zeroes; + }; +}; + +struct rt_nvme_completion +{ + union + { + rt_le16_t u16; + rt_le32_t u32; + rt_le64_t u64; + } result; + rt_le16_t sq_head; /* How much of this queue may be reclaimed */ + rt_le16_t sq_id; /* Submission queue that generated this entry */ + rt_uint16_t cmdid; /* Which command completed */ + rt_le16_t status; /* Command status */ +}; + +enum +{ + RT_NVME_REG_CAP = 0x0000, /* Controller Capabilities */ + RT_NVME_REG_VS = 0x0008, /* Version */ + RT_NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ + RT_NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ + RT_NVME_REG_CC = 0x0014, /* Controller Configuration */ + RT_NVME_REG_CSTS = 0x001c, /* Controller Status */ + RT_NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ + RT_NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ + RT_NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ + RT_NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ + RT_NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ + RT_NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ + RT_NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */ + RT_NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */ + RT_NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer Location */ + RT_NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory Space Control */ + RT_NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */ + RT_NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */ + RT_NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */ + RT_NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */ + RT_NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity Buffer Size */ + RT_NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained Write Throughput */ + RT_NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ +}; + +#define RT_NVME_CAP_MQES(cap) ((cap) & 0xffff) +#define RT_NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) +#define RT_NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) +#define RT_NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) +#define RT_NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) + +#define RT_NVME_VS(major, minor) (((major) << 16) | ((minor) << 8)) + +#define RT_NVME_AQ_DEPTH 32 +#define RT_NVME_NR_AEN_COMMANDS 1 +#define RT_NVME_AQ_BLK_MQ_DEPTH (RT_NVME_AQ_DEPTH - RT_NVME_NR_AEN_COMMANDS) +#define RT_NVME_AQ_MQ_TAG_DEPTH (RT_NVME_AQ_BLK_MQ_DEPTH - 1) + +enum +{ + RT_NVME_CC_ENABLE = 1 << 0, + RT_NVME_CC_CSS_NVM = 0 << 4, + RT_NVME_CC_MPS_SHIFT = 7, + RT_NVME_CC_ARB_RR = 0 << 11, + RT_NVME_CC_ARB_WRRU = 1 << 11, + RT_NVME_CC_ARB_VS = 7 << 11, + RT_NVME_CC_SHN_NONE = 0 << 14, + RT_NVME_CC_SHN_NORMAL = 1 << 14, + RT_NVME_CC_SHN_ABRUPT = 2 << 14, + RT_NVME_CC_SHN_MASK = 3 << 14, + RT_NVME_CC_IOSQES = 6 << 16, + RT_NVME_CC_IOCQES = 4 << 20, + RT_NVME_CSTS_RDY = 1 << 0, + RT_NVME_CSTS_CFS = 1 << 1, + RT_NVME_CSTS_SHST_NORMAL = 0 << 2, + RT_NVME_CSTS_SHST_OCCUR = 1 << 2, + RT_NVME_CSTS_SHST_CMPLT = 2 << 2, + RT_NVME_CSTS_SHST_MASK = 3 << 2, +}; + +rt_packed(struct rt_nvme_id_power_state +{ + rt_le16_t mp; /* Maximum Power */ + NVME_RSVD(1, 1); + rt_uint8_t mxps_nops; /* Max Power Scale, Non-Operational State */ + rt_le32_t enlat; /* Entry Latency: microseconds */ + rt_le32_t exlat; /* Exit Latency: microseconds */ + rt_uint8_t rrt; /* Relative Read Throughput */ + rt_uint8_t rrl; /* Relative Read Latency */ + rt_uint8_t rwt; /* Relative Write Throughput */ + rt_uint8_t rwl; /* Relative Write Latency */ + rt_le16_t idlp; /* Idle Power */ + rt_uint8_t ips; /* Idle Power Scale */ + NVME_RSVD(19, 1); + rt_le16_t actp; /* Active Power */ + rt_uint8_t apw_aps; /* Active Power Workload, Active Power Scale */ + NVME_RSVD(23, 9); +}); + +rt_packed(struct rt_nvme_id_ctrl +{ + /* Controller Capabilities and Features */ + rt_le16_t vid; /* PCI Vendor ID */ + rt_le16_t ssvid; /* PCI Subsystem Vendor */ + char sn[20]; /* Serial Number */ + char mn[40]; /* Model Number */ + char fr[8]; /* Firmware Revision */ + rt_uint8_t rab; /* Recommended Arbitration Burst */ + rt_uint8_t ieee[3]; /* IEEE OUI Identifier */ + rt_uint8_t mic; /* Controller Multi-Path I/O and Namespace Sharing Capabilities */ + rt_uint8_t mdts; /* Maximum Data Transfer Size */ + rt_uint16_t cntlid; /* Controller ID */ + rt_uint32_t ver; /* Version */ + rt_uint32_t rtd3r; /* RTD3 Resume Latency */ + rt_uint32_t rtd3e; /* RTD3 Entry Latency */ + rt_uint32_t oaes; /* Optional Asynchronous Events Supported */ +#define RT_NVME_ID_CTRATT_ELBAS 15 /* Extended LBA Formats Supported */ +#define RT_NVME_ID_CTRATT_DNVMS 14 /* Delete NVM Set */ +#define RT_NVME_ID_CTRATT_DEG 13 /* Delete Endurance Group */ +#define RT_NVME_ID_CTRATT_VCM 12 /* Variable Capacity Management */ +#define RT_NVME_ID_CTRATT_FCM 11 /* Fixed Capacity Management */ +#define RT_NVME_ID_CTRATT_MDS 10 /* Multi-Domain Subsystem */ +#define RT_NVME_ID_CTRATT_UUIDL 9 /* UUID List */ +#define RT_NVME_ID_CTRATT_SQA 8 /* SQ Associations */ +#define RT_NVME_ID_CTRATT_NG 7 /* Namespace Granularity */ +#define RT_NVME_ID_CTRATT_TBKAS 6 /* Traffic Based Keep Alive Support */ +#define RT_NVME_ID_CTRATT_PLM 5 /* Predictable Latency Mode */ +#define RT_NVME_ID_CTRATT_EG 4 /* Endurance Groups */ +#define RT_NVME_ID_CTRATT_RRL 3 /* Read Recovery Levels */ +#define RT_NVME_ID_CTRATT_NVMS 2 /* NVM Sets */ +#define RT_NVME_ID_CTRATT_NOPSPM 1 /* Non-Operational Power State Permissive Mode */ +#define RT_NVME_ID_CTRATT_HIS 0 /* Host Identifier Support */ + rt_uint32_t ctratt; /* Controller Attributes */ + rt_uint16_t rrls; /* Read Recovery Levels Supported */ + NVME_RSVD(102, 9); + rt_uint8_t cntrltype; /* Controller Type */ + rt_uint8_t fguid[16]; /* FRU Globally Unique Identifier */ + rt_uint16_t crdt1; /* Command Retry Delay Time 1 */ + rt_uint16_t crdt2; /* Command Retry Delay Time 2 */ + rt_uint16_t crdt3; /* Command Retry Delay Time 3 */ + NVME_RSVD(134, 119); +#define RT_NVME_ID_NVMSR_NVMEE 1 /* NVMe Enclosure */ +#define RT_NVME_ID_NVMSR_NVMESD 0 /* NVMe Storage Device */ + rt_uint8_t nvmsr; /* NVM Subsystem Report */ + +#define RT_NVME_ID_VWCI_VWCRV 7 /* VPD Write Cycles Remaining Valid */ +#define RT_NVME_ID_VWCI_VWCR 0 /* VPD Write Cycles Remaining */ + rt_uint8_t vwci; /* VPD Write Cycle Information */ +#define RT_NVME_ID_MEC_PCIEME 1 /* PCIe Port Management Endpoint */ +#define RT_NVME_ID_MEC_SMBUSME 0 /* SMBus/I2C Port Management Endpoint */ + rt_uint8_t mec; /* Management Endpoint Capabilities */ + + /* Admin Command Set Attributes & Optional Controller Capabilities */ + rt_le16_t oacs; /* Optional Admin Command Support */ + rt_uint8_t acl; /* Abort Command Limit */ + rt_uint8_t aerl; /* Asynchronous Event Request Limit */ +#define RT_NVME_ID_FRMW_SMUD 5 /* Support Multiple Update Detection */ +#define RT_NVME_ID_FRMW_FAWR 4 /* Firmware Activation Without Reset */ +#define RT_NVME_ID_FRMW_NOFS 1 /* Number Of Firmware Slots */ +#define RT_NVME_ID_FRMW_FFSRO 0 /* First Firmware Slot Read Only */ + rt_uint8_t frmw; /* Firmware Updates */ + rt_uint8_t lpa; /* Log Page Attributes */ + rt_uint8_t elpe; /* Error Log Page Entries */ + rt_uint8_t npss; /* Number of Power States Support */ + rt_uint8_t avscc; /* Admin Vendor Specific Command Configuration */ + rt_uint8_t apsta; /* Autonomous Power State Transition Attributes */ + rt_le16_t wctemp; /* Warning Composite Temperature Threshold */ + rt_le16_t cctemp; /* Critical Composite Temperature Threshold */ + rt_uint16_t mtfa; /* Maximum Time for Firmware Activation */ + rt_uint32_t hmpre; /* Host Memory Buffer Preferred Size */ + rt_uint32_t hmmin; /* Host Memory Buffer Minimum Size */ + rt_uint8_t tnvmcap[16]; /* Total NVM Capacity */ + rt_uint8_t unvmcap[16]; /* Unallocated NVM Capacity */ +#define RT_NVME_ID_RPMBS_ASZ 24 /* Access Size */ +#define RT_NVME_ID_RPMBS_TSZ 16 /* Total Size */ +#define RT_NVME_ID_RPMBS_AM 3 /* Authentication Method */ +#define RT_NVME_ID_RPMBS_NORPMBU 2 /* Number of RPMB Units */ + rt_uint32_t rpmbs; /* Replay Protected Memory Block Support */ + rt_uint16_t edstt; /* Extended Device Self-test Time */ + rt_uint8_t dsto; /* Device Self-test Options */ + rt_uint8_t fwug; /* Firmware Update Granularity */ + rt_uint16_t kas; /* Keep Alive Support */ + rt_uint16_t hctma; /* Host Controlled Thermal Management Attributes */ + rt_uint16_t mntmt; /* Minimum Thermal Management Temperature */ + rt_uint16_t mxtmt; /* Maximum Thermal Management Temperature */ +#define RT_NVME_ID_SANICAP_NODMMAS 30 /* No-Deallocate Modifies Media After Sanitize */ +#define RT_NVME_ID_SANICAP_NDI 29 /* No-Deallocate Inhibited */ +#define RT_NVME_ID_SANICAP_OWS 2 /* Overwrite Support */ +#define RT_NVME_ID_SANICAP_BES 1 /* Block Erase Support */ +#define RT_NVME_ID_SANICAP_CES 0 /* Crypto Erase Support */ + rt_uint32_t sanicap; /* Sanitize Capabilities */ + rt_uint32_t hmminds; /* Host Memory Buffer Minimum Descriptor Entry Size */ + rt_uint16_t hmmaxd; /* Host Memory Maximum Descriptors Entries */ + rt_uint16_t nsetidmax; /* NVM Set Identifier Maximum */ + rt_uint16_t endgidmax; /* Endurance Group Identifier Maximum */ + rt_uint8_t anatt; /* ANA Transition Time */ + rt_uint8_t anacap; /* Asymmetric Namespace Access Capabilities */ + rt_uint32_t anagrpmax; /* ANA Group Identifier Maximum */ + rt_uint32_t nanagrpid; /* Number of ANA Group Identifiers */ + rt_uint32_t pels; /* Persistent Event Log Size */ + rt_uint16_t dmid; /* Domain Identifier */ + NVME_RSVD(358, 10); + rt_uint8_t megcap[16]; /* Max Endurance Group Capacity */ + NVME_RSVD(384, 128); + + /* NVM Command Set Attributes */ + rt_uint8_t sqes; /* Submission Queue Entry Size */ + rt_uint8_t cqes; /* Completion Queue Entry Size */ + rt_le16_t maxcmd; /* Maximum Outstanding Commands */ + rt_le32_t nn; /* Number of Namespaces */ + rt_le16_t oncs; /* Optional NVM Command Support */ + rt_le16_t fuses; /* Fused Operation Support */ + rt_uint8_t fna; /* Format NVM Attributes */ + rt_uint8_t vwc; /* Volatile Write Cache */ + rt_le16_t awun; /* Atomic Write Unit Normal */ + rt_le16_t awupf; /* Atomic Write Unit Power Fail */ + rt_uint8_t nvscc; /* I/O Command Set Vendor Specific Command Configuration */ + rt_uint8_t nwpc; /* Namespace Write Protection Capabilities */ + rt_le16_t acwu; /* Atomic Compare & Write Unit */ + rt_le16_t cdfs; /* Copy Descriptor Formats Supported */ +#define RT_NVME_ID_SGL_SUPPORT_MASK 0x3 + rt_le32_t sgls; /* SGL Support */ + rt_uint32_t mnan; /* Maximum Number of Allowed Namespaces */ + char maxdna[16]; /* Maximum Domain Namespace Attachments */ + rt_le32_t maxcna; /* Maximum I/O Controller Namespace Attachments */ + NVME_RSVD(564, 204); + rt_uint8_t subnqn[256]; /* NVM Subsystem NVMe Qualified Name */ + NVME_RSVD(1024, 768); + rt_le32_t ioccsz; /* I/O Queue Command Capsule Supported Size */ + rt_le32_t iorcsz; /* I/O Queue Response Capsule Supported Size */ + rt_le16_t icdoff; /* In Capsule Data Offset */ + rt_uint8_t ctrattr; /* Fabrics Controller Attributes */ + rt_uint8_t msdbd; /* Maximum SGL Data Block Descriptors */ + rt_le16_t ofcs; /* Optional Fabric Commands Support */ + rt_uint8_t dctype; + NVME_RSVD(1807, 241); + + /* Power State Descriptors */ + struct rt_nvme_id_power_state psd[32]; + + /* Vendor Specific */ + rt_uint8_t vs[1024]; +}); + +enum +{ + RT_NVME_CTRL_CMIC_MULTI_PORT = 1 << 0, + RT_NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1, + RT_NVME_CTRL_CMIC_ANA = 1 << 3, + RT_NVME_CTRL_ONCS_COMPARE = 1 << 0, + RT_NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, + RT_NVME_CTRL_ONCS_DSM = 1 << 2, + RT_NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, + RT_NVME_CTRL_ONCS_RESERVATIONS = 1 << 5, + RT_NVME_CTRL_ONCS_TIMESTAMP = 1 << 6, + RT_NVME_CTRL_VWC_PRESENT = 1 << 0, + RT_NVME_CTRL_OACS_SEC_SUPP = 1 << 0, + RT_NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3, + RT_NVME_CTRL_OACS_DIRECTIVES = 1 << 5, + RT_NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8, + RT_NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1, + RT_NVME_CTRL_CTRATT_128_ID = 1 << 0, + RT_NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1, + RT_NVME_CTRL_CTRATT_NVM_SETS = 1 << 2, + RT_NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3, + RT_NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4, + RT_NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5, + RT_NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7, + RT_NVME_CTRL_CTRATT_UUID_LIST = 1 << 9, +}; + +struct rt_nvme_lba_format +{ + rt_le16_t ms; /* Metadata size */ + rt_uint8_t ds; /* Data size */ + rt_uint8_t rp; /* Relative performance */ +}; + +rt_packed(struct rt_nvme_id_ns +{ + rt_le64_t nsze; /* Namespace size */ + rt_le64_t ncap; /* Namespace capacity */ + rt_le64_t nuse; /* Namespace utilization */ + rt_uint8_t nsfeat; /* Namespace features */ + rt_uint8_t nlbaf; /* Number of lba formats */ + rt_uint8_t flbas; /* Formatted lba size */ + rt_uint8_t mc; /* Metadata capabilities */ + rt_uint8_t dpc; /* End-to-end data protection capabilities */ + rt_uint8_t dps; /* End-to-end data protection type settings */ + rt_uint8_t nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */ + rt_uint8_t rescap; /* Reservation Capabilities */ + rt_uint8_t fpi; /* Format Progress Indicator */ + rt_uint8_t dlfeat; /* Deallocate Logical Block Features */ + rt_le16_t nawun; /* Namespace Atomic Write Unit Normal */ + rt_le16_t nawupf; /* Namespace Atomic Write Unit Power Fail */ + rt_le16_t nacwu; /* Namespace Atomic Compare & Write Unit */ + rt_le16_t nabsn; /* Namespace Atomic Boundary Size Normal */ + rt_le16_t nabo; /* Namespace Atomic Boundary Offset */ + rt_le16_t nabspf; /* Namespace Atomic Boundary Size Power Fail */ + rt_uint16_t noiob; /* Namespace Optimal IO Boundary */ + rt_le64_t nvmcap[2]; /* NVMe Capacity */ + rt_uint16_t npwg; /* Namespace Preferred Write Granularity */ + rt_uint16_t npwa; /* Namespace Preferred Write Alignment */ + rt_uint16_t npdg; /* Namespace Preferred Deallocate Granularity */ + rt_uint16_t npda; /* Namespace Preferred Deallocate Alignment */ + rt_uint16_t nows; /* Namespace Optimal Write Size */ + NVME_RSVD(118, 18); + rt_uint32_t anagrpid; /* ANA Group Identifier */ + NVME_RSVD(139, 3); + rt_uint8_t nsattr; /* Namespace Attributes */ + rt_uint16_t nvmsetid; /* NVMe Set Identifier */ + rt_uint16_t endgid; /* Endurance Group Identifier */ + rt_uint8_t nguid[16]; /* Namespace Globally Unique Identifier */ + rt_uint8_t eui64[8]; /* IEEE Extended Unique Identifier */ + + /* Logical Block Address Format */ + struct rt_nvme_lba_format lbaf[16]; + NVME_RSVD(171, 192); + + /* Vendor specific */ + rt_uint8_t vs[3712]; +}); + +enum +{ + RT_NVME_NS_FEAT_THIN = 1 << 0, + RT_NVME_NS_FLBAS_LBA_MASK = 0xf, + RT_NVME_NS_FLBAS_LBA_UMASK = 0x60, + RT_NVME_NS_FLBAS_LBA_SHIFT = 1, + RT_NVME_NS_FLBAS_META_EXT = 0x10, + RT_NVME_LBAF_RP_BEST = 0, + RT_NVME_LBAF_RP_BETTER = 1, + RT_NVME_LBAF_RP_GOOD = 2, + RT_NVME_LBAF_RP_DEGRADED = 3, + RT_NVME_NS_DPC_PI_LAST = 1 << 4, + RT_NVME_NS_DPC_PI_FIRST = 1 << 3, + RT_NVME_NS_DPC_PI_TYPE3 = 1 << 2, + RT_NVME_NS_DPC_PI_TYPE2 = 1 << 1, + RT_NVME_NS_DPC_PI_TYPE1 = 1 << 0, + RT_NVME_NS_DPS_PI_FIRST = 1 << 3, + RT_NVME_NS_DPS_PI_MASK = 0x7, + RT_NVME_NS_DPS_PI_TYPE1 = 1, + RT_NVME_NS_DPS_PI_TYPE2 = 2, + RT_NVME_NS_DPS_PI_TYPE3 = 3, +}; + +struct rt_nvme_ops; +struct rt_nvme_controller; + +/* + * An NVM Express queue. Each device has at least two (one for admin commands + * and one for I/O commands). + */ +struct rt_nvme_queue +{ + struct rt_nvme_controller *nvme; + struct rt_nvme_command *sq_cmds; + struct rt_nvme_completion *cq_entry; + + rt_ubase_t sq_cmds_phy; + rt_ubase_t cq_entry_phy; + + rt_uint32_t *doorbell; + rt_uint16_t qid; + rt_uint16_t depth; + rt_uint16_t sq_head; + rt_uint16_t sq_tail; + rt_uint16_t cq_head; + rt_uint16_t cq_phase; + + rt_err_t err; + struct rt_nvme_command *cmd; + + struct rt_completion done; + struct rt_spinlock lock; +}; + +struct rt_nvme_controller +{ + rt_list_t list; + struct rt_device *dev; + + int nvme_id; + char name[RT_NAME_MAX]; + + void *regs; + rt_uint64_t cap; + rt_uint32_t page_shift; + rt_uint32_t page_size; + rt_uint32_t queue_depth; + rt_uint32_t io_queue_max; + rt_uint32_t ctrl_config; + rt_uint32_t max_transfer_shift:8; + rt_uint32_t volatile_write_cache:8; + rt_uint32_t write_zeroes:1; + rt_uint32_t sgl_mode:2; + rt_uint32_t doorbell_stride; + rt_uint32_t *doorbell_tbl; + + const struct rt_nvme_ops *ops; + +#define RT_USING_NVME_QUEUE (1 + (RT_USING_NVME_IO_QUEUE * RT_CPUS_NR)) + int irqs_nr; + int irqs[RT_USING_NVME_QUEUE]; + union + { + struct + { + struct rt_nvme_queue admin_queue; + struct rt_nvme_queue io_queues[RT_USING_NVME_IO_QUEUE * RT_CPUS_NR]; + }; + struct rt_nvme_queue queue[RT_USING_NVME_QUEUE]; + }; + + volatile rt_atomic_t cmdid; + volatile rt_atomic_t ioqid[RT_CPUS_NR]; + + rt_list_t ns_nodes; +}; + +struct rt_nvme_device +{ + struct rt_blk_disk parent; + struct rt_nvme_controller *ctrl; + + rt_list_t list; + + rt_uint32_t nsid; + rt_uint32_t lba_shift; + struct rt_nvme_id_ns id; +}; +#define rt_disk_to_nvme_device(disk) rt_container_of(disk, struct rt_nvme_device, parent) + +struct rt_nvme_ops +{ + const char *name; + + /* Controller-specific NVM Express queue setup */ + rt_err_t (*setup_queue)(struct rt_nvme_queue *queue); + /* Controller-specific NVM Express queue cleanup */ + rt_err_t (*cleanup_queue)(struct rt_nvme_queue *queue); + /* Controller-specific NVM Express command submission */ + rt_err_t (*submit_cmd)(struct rt_nvme_queue *queue, struct rt_nvme_command *cmd); + /* Controller-specific NVM Express command completion */ + void (*complete_cmd)(struct rt_nvme_queue *queue, struct rt_nvme_command *cmd); +}; + +rt_err_t rt_nvme_controller_register(struct rt_nvme_controller *nvme); +rt_err_t rt_nvme_controller_unregister(struct rt_nvme_controller *nvme); + +#endif /* __NVME_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/ofw.h b/rt-thread/components/drivers/include/drivers/ofw.h index 7531dfe..3f23017 100644 --- a/rt-thread/components/drivers/include/drivers/ofw.h +++ b/rt-thread/components/drivers/include/drivers/ofw.h @@ -37,6 +37,7 @@ struct rt_ofw_node /* phandles range from 1 to 2^32-2 (0xfffffffe) */ rt_phandle phandle; + struct rt_device *dev; struct rt_ofw_prop *props; struct rt_ofw_node *parent; struct rt_ofw_node *child; @@ -376,9 +377,9 @@ rt_inline rt_bool_t rt_ofw_node_is_type(const struct rt_ofw_node *np, const char for (np = rt_ofw_find_node_by_type(RT_NULL, type); np; \ np = rt_ofw_find_node_by_type(np, type)) -#define rt_ofw_foreach_node_by_compatible(np, type, compatible) \ - for (np = rt_ofw_find_node_by_compatible(RT_NULL, type, compatible); np; \ - np = rt_ofw_find_node_by_compatible(np, type, compatible)) +#define rt_ofw_foreach_node_by_compatible(np, compatible) \ + for (np = rt_ofw_find_node_by_compatible(RT_NULL, compatible); np; \ + np = rt_ofw_find_node_by_compatible(np, compatible)) #define rt_ofw_foreach_node_by_ids_r(np, id, ids) \ for (np = rt_ofw_find_node_by_ids_r(RT_NULL, ids, id); \ diff --git a/rt-thread/components/drivers/include/drivers/ofw_fdt.h b/rt-thread/components/drivers/include/drivers/ofw_fdt.h index 4db4ece..7aeec71 100644 --- a/rt-thread/components/drivers/include/drivers/ofw_fdt.h +++ b/rt-thread/components/drivers/include/drivers/ofw_fdt.h @@ -70,6 +70,7 @@ rt_err_t rt_fdt_boot_dump(void); void rt_fdt_earlycon_output(const char *str); void rt_fdt_earlycon_kick(int why); rt_err_t rt_fdt_scan_chosen_stdout(void); +rt_err_t rt_fdt_bootargs_select(const char *key, int index, const char **out_result); rt_err_t rt_fdt_unflatten(void); struct rt_ofw_node *rt_fdt_unflatten_single(void *fdt); diff --git a/rt-thread/components/drivers/include/drivers/ofw_io.h b/rt-thread/components/drivers/include/drivers/ofw_io.h index 4ebfbe2..f458435 100644 --- a/rt-thread/components/drivers/include/drivers/ofw_io.h +++ b/rt-thread/components/drivers/include/drivers/ofw_io.h @@ -26,6 +26,27 @@ rt_err_t rt_ofw_get_address_by_name(struct rt_ofw_node *np, const char *name, int rt_ofw_get_address_array(struct rt_ofw_node *np, int nr, rt_uint64_t *out_regs); rt_uint64_t rt_ofw_translate_address(struct rt_ofw_node *np, const char *range_type, rt_uint64_t address); +rt_uint64_t rt_ofw_reverse_address(struct rt_ofw_node *np, const char *range_type, rt_uint64_t address); + +rt_inline rt_uint64_t rt_ofw_translate_dma2cpu(struct rt_ofw_node *np, rt_uint64_t address) +{ + rt_uint64_t bus_addr, cpu_addr; + + bus_addr = rt_ofw_reverse_address(np, "dma-ranges", address); + cpu_addr = rt_ofw_translate_address(np, "ranges", bus_addr); + + return cpu_addr != ~0ULL ? cpu_addr : address; +} + +rt_inline rt_uint64_t rt_ofw_translate_cpu2dma(struct rt_ofw_node *np, rt_uint64_t address) +{ + rt_uint64_t bus_addr, dma_addr; + + bus_addr = rt_ofw_reverse_address(np, "ranges", address); + dma_addr = rt_ofw_translate_address(np, "dma-ranges", bus_addr); + + return dma_addr != ~0ULL ? dma_addr : address; +} void *rt_ofw_iomap(struct rt_ofw_node *np, int index); void *rt_ofw_iomap_by_name(struct rt_ofw_node *np, const char *name); diff --git a/rt-thread/components/drivers/include/drivers/pci.h b/rt-thread/components/drivers/include/drivers/pci.h new file mode 100644 index 0000000..1ae4393 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/pci.h @@ -0,0 +1,604 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-08-25 GuEe-GUI first version + */ + +#ifndef __PCI_H__ +#define __PCI_H__ + +#include +#include +#include +#include +#include +#include +#include + +#include "../../pci/pci_ids.h" +#include "../../pci/pci_regs.h" + +#define RT_PCI_INTX_PIN_MAX 4 +#define RT_PCI_BAR_NR_MAX 6 +#define RT_PCI_DEVICE_MAX 32 +#define RT_PCI_FUNCTION_MAX 8 + +#define RT_PCI_FIND_CAP_TTL 48 + +/* + * The PCI interface treats multi-function devices as independent + * devices. The slot/function address of each device is encoded + * in a single byte as follows: + * + * 7:3 = slot + * 2:0 = function + */ +#define RT_PCI_DEVID(bus, devfn) ((((rt_uint16_t)(bus)) << 8) | (devfn)) +#define RT_PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) +#define RT_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) +#define RT_PCI_FUNC(devfn) ((devfn) & 0x07) + +#define PCIE_LINK_STATE_L0S RT_BIT(0) +#define PCIE_LINK_STATE_L1 RT_BIT(1) +#define PCIE_LINK_STATE_CLKPM RT_BIT(2) +#define PCIE_LINK_STATE_L1_1 RT_BIT(3) +#define PCIE_LINK_STATE_L1_2 RT_BIT(4) +#define PCIE_LINK_STATE_L1_1_PCIPM RT_BIT(5) +#define PCIE_LINK_STATE_L1_2_PCIPM RT_BIT(6) +#define PCIE_LINK_STATE_ALL \ +( \ + PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | \ + PCIE_LINK_STATE_CLKPM | \ + PCIE_LINK_STATE_L1_1 | PCIE_LINK_STATE_L1_2 | \ + PCIE_LINK_STATE_L1_1_PCIPM | PCIE_LINK_STATE_L1_2_PCIPM \ +) + +struct rt_pci_bus_region +{ + rt_uint64_t phy_addr; + rt_uint64_t cpu_addr; + rt_uint64_t size; + + rt_uint64_t bus_start; + +#define PCI_BUS_REGION_F_NONE 0xffffffff /* PCI no memory */ +#define PCI_BUS_REGION_F_MEM 0x00000000 /* PCI memory space */ +#define PCI_BUS_REGION_F_IO 0x00000001 /* PCI IO space */ +#define PCI_BUS_REGION_F_PREFETCH 0x00000008 /* Prefetchable PCI memory */ + rt_ubase_t flags; +}; + +struct rt_pci_bus_resource +{ + rt_ubase_t base; + rt_size_t size; + + rt_ubase_t flags; +}; + +/* + * PCI topology: + * + * +-----+-----+ +-------------+ PCI Bus 0 +------------+ PCI Bus 1 + * | RAM | CPU |---------| Host Bridge |--------+-----| PCI Bridge |-----+ + * +-----+-----+ +-------------+ | +------------+ | +-------------+ + * | +----| End Point 2 | + * +-------------+ +-------------+ | +-------------+ | +-------------+ + * | End Point 5 |----+ | End Point 0 |-------+ | End Point 3 |----+ + * +-------------+ | +-------------+ | +-------------+ | + * | | | + * +-------------+ | +-------------+ | +-------------+ | +-------------+ + * | End Point 6 |----+----| ISA Bridge |-------+-----| End Point 1 | +----| End Point 4 | + * +-------------+ +-------------+ | +-------------+ +-------------+ + * | + * +------+ +----------------+ | + * | Port |---------| CardBus Bridge |----+ + * +------+ +----------------+ + */ + +struct rt_pci_bus; + +struct rt_pci_device_id +{ +#define PCI_ANY_ID (~0) +#define RT_PCI_DEVICE_ID(vend, dev) \ + .vendor = (vend), \ + .device = (dev), \ + .subsystem_vendor = PCI_ANY_ID, \ + .subsystem_device = PCI_ANY_ID + +#define RT_PCI_DEVICE_CLASS(dev_class, dev_class_mask) \ + .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ + .subsystem_vendor = PCI_ANY_ID, \ + .subsystem_device = PCI_ANY_ID, \ + .class = (dev_class), .class_mask = (dev_class_mask), + + rt_uint32_t vendor, device; /* Vendor and device ID or PCI_ANY_ID */ + rt_uint32_t subsystem_vendor; /* Subsystem ID's or PCI_ANY_ID */ + rt_uint32_t subsystem_device; /* Subsystem ID's or PCI_ANY_ID */ + rt_uint32_t class, class_mask; /* (class, subclass, prog-if) triplet */ + + const void *data; +}; + +struct rt_pci_device +{ + struct rt_device parent; + const char *name; + + rt_list_t list; + struct rt_pci_bus *bus; + struct rt_pci_bus *subbus; /* In PCI-to-PCI bridge, 'End Point' or 'Port' is NULL */ + + const struct rt_pci_device_id *id; + + rt_uint32_t devfn; /* Encoded device & function index */ + rt_uint16_t vendor; + rt_uint16_t device; + rt_uint16_t subsystem_vendor; + rt_uint16_t subsystem_device; + rt_uint32_t class; /* 3 bytes: (base, sub, prog-if) */ + rt_uint8_t revision; + rt_uint8_t hdr_type; + rt_uint8_t max_latency; + rt_uint8_t min_grantl; + rt_uint8_t int_pin; + rt_uint8_t int_line; + rt_uint16_t exp_flags; + rt_uint32_t cfg_size; + + void *sysdata; + + int irq; + rt_uint8_t pin; + struct rt_pic *intx_pic; + + struct rt_pci_bus_resource resource[RT_PCI_BAR_NR_MAX]; + + rt_uint8_t pme_cap; + rt_uint8_t msi_cap; + rt_uint8_t msix_cap; + rt_uint8_t pcie_cap; + + rt_uint8_t busmaster:1; /* Is the bus master */ + rt_uint8_t multi_function:1; /* Multi-function device */ + rt_uint8_t ari_enabled:1; /* Alternative Routing-ID Interpretation */ + rt_uint8_t no_msi:1; /* May not use MSI */ + rt_uint8_t no_64bit_msi:1; /* May only use 32-bit MSIs */ + rt_uint8_t msi_enabled:1; /* MSI enable */ + rt_uint8_t msix_enabled:1; /* MSIx enable */ + rt_uint8_t broken_intx_masking:1; /* INTx masking can't be used */ + rt_uint8_t pme_support:5; /* Bitmask of states from which PME# can be generated */ + +#ifdef RT_PCI_MSI + void *msix_base; + struct rt_pic *msi_pic; + rt_list_t msi_desc_nodes; + struct rt_spinlock msi_lock; +#endif +}; + +struct rt_pci_host_bridge +{ + struct rt_device parent; + + rt_uint32_t domain; + + struct rt_pci_bus *root_bus; + const struct rt_pci_ops *ops; + const struct rt_pci_ops *child_ops; + + rt_uint32_t bus_range[2]; + rt_size_t bus_regions_nr; + struct rt_pci_bus_region *bus_regions; + rt_size_t dma_regions_nr; + struct rt_pci_bus_region *dma_regions; + + rt_uint8_t (*irq_slot)(struct rt_pci_device *pdev, rt_uint8_t *pinp); + int (*irq_map)(struct rt_pci_device *pdev, rt_uint8_t slot, rt_uint8_t pin); + + void *sysdata; + rt_uint8_t priv[0]; +}; +#define rt_device_to_pci_host_bridge(dev) rt_container_of(dev, struct rt_pci_host_bridge, parent) + +struct rt_pci_ops +{ + rt_err_t (*add)(struct rt_pci_bus *bus); + rt_err_t (*remove)(struct rt_pci_bus *bus); + + void *(*map)(struct rt_pci_bus *bus, rt_uint32_t devfn, int reg); + + rt_err_t (*read)(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, int width, rt_uint32_t *value); + rt_err_t (*write)(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, int width, rt_uint32_t value); +}; + +struct rt_pci_bus +{ + rt_list_t list; + rt_list_t children_nodes; + rt_list_t devices_nodes; + struct rt_pci_bus *parent; + + union + { + /* In PCI-to-PCI bridge, parent is not NULL */ + struct rt_pci_device *self; + /* In Host bridge, this is Root bus ('PCI Bus 0') */ + struct rt_pci_host_bridge *host_bridge; + }; + + const struct rt_pci_ops *ops; + + char name[48]; + char number; + struct rt_spinlock lock; + + void *sysdata; +}; + +struct rt_pci_driver +{ + struct rt_driver parent; + + const char *name; + const struct rt_pci_device_id *ids; + + rt_err_t (*probe)(struct rt_pci_device *pdev); + rt_err_t (*remove)(struct rt_pci_device *pdev); + rt_err_t (*shutdown)(struct rt_pci_device *pdev); +}; + +struct rt_pci_msix_entry +{ + int irq; + int index; +}; + +enum rt_pci_power +{ + RT_PCI_D0, + RT_PCI_D1, + RT_PCI_D2, + RT_PCI_D3HOT, + RT_PCI_D3COLD, + + RT_PCI_PME_MAX, +}; + +void rt_pci_pme_init(struct rt_pci_device *pdev); +void rt_pci_pme_active(struct rt_pci_device *pdev, rt_bool_t enable); +rt_err_t rt_pci_enable_wake(struct rt_pci_device *pci_dev, + enum rt_pci_power state, rt_bool_t enable); +rt_inline rt_bool_t rt_pci_pme_capable(struct rt_pci_device *pdev, + enum rt_pci_power state) +{ + if (!pdev->pme_cap) + { + return RT_FALSE; + } + + return !!(pdev->pme_support & (1 << state)); +} + +void rt_pci_msi_init(struct rt_pci_device *pdev); +void rt_pci_msix_init(struct rt_pci_device *pdev); + +void rt_pci_set_master(struct rt_pci_device *pdev); +void rt_pci_clear_master(struct rt_pci_device *pdev); + +struct rt_pci_host_bridge *rt_pci_host_bridge_alloc(rt_size_t priv_size); +rt_err_t rt_pci_host_bridge_free(struct rt_pci_host_bridge *); +rt_err_t rt_pci_host_bridge_init(struct rt_pci_host_bridge *host_bridge); +rt_err_t rt_pci_host_bridge_probe(struct rt_pci_host_bridge *host_bridge); + +struct rt_pci_device *rt_pci_alloc_device(struct rt_pci_bus *bus); +struct rt_pci_device *rt_pci_scan_single_device(struct rt_pci_bus *bus, rt_uint32_t devfn); +rt_err_t rt_pci_setup_device(struct rt_pci_device *pdev); +rt_size_t rt_pci_scan_slot(struct rt_pci_bus *bus, rt_uint32_t devfn); +rt_uint32_t rt_pci_scan_child_buses(struct rt_pci_bus *bus, rt_size_t buses); +rt_uint32_t rt_pci_scan_child_bus(struct rt_pci_bus *bus); + +rt_err_t rt_pci_host_bridge_register(struct rt_pci_host_bridge *host_bridge); +rt_err_t rt_pci_scan_root_bus_bridge(struct rt_pci_host_bridge *host_bridge); + +rt_err_t rt_pci_host_bridge_remove(struct rt_pci_host_bridge *host_bridge); +rt_err_t rt_pci_bus_remove(struct rt_pci_bus *bus); +rt_err_t rt_pci_device_remove(struct rt_pci_device *pdev); + +rt_uint32_t rt_pci_domain(struct rt_pci_device *pdev); + +rt_uint8_t rt_pci_bus_find_capability(struct rt_pci_bus *bus, rt_uint32_t devfn, int cap); +rt_uint8_t rt_pci_find_capability(struct rt_pci_device *pdev, int cap); +rt_uint8_t rt_pci_find_next_capability(struct rt_pci_device *pdev, rt_uint8_t pos, int cap); + +rt_uint16_t rt_pci_find_ext_capability(struct rt_pci_device *pdev, int cap); +rt_uint16_t rt_pci_find_ext_next_capability(struct rt_pci_device *pdev, rt_uint16_t pos, int cap); + +struct rt_pci_bus *rt_pci_find_root_bus(struct rt_pci_bus *bus); +struct rt_pci_host_bridge *rt_pci_find_host_bridge(struct rt_pci_bus *bus); + +rt_inline rt_uint16_t rt_pci_dev_id(struct rt_pci_device *pdev) +{ + return RT_PCI_DEVID(pdev->bus->number, pdev->devfn); +} + +rt_inline rt_bool_t rt_pci_is_root_bus(struct rt_pci_bus *bus) +{ + return bus->parent ? RT_FALSE : RT_TRUE; +} + +rt_inline rt_bool_t rt_pci_is_bridge(struct rt_pci_device *pdev) +{ + return pdev->hdr_type == PCIM_HDRTYPE_BRIDGE || + pdev->hdr_type == PCIM_HDRTYPE_CARDBUS; +} + +rt_inline rt_bool_t rt_pci_is_pcie(struct rt_pci_device *pdev) +{ + return !!pdev->pcie_cap; +} + +#define rt_pci_foreach_bridge(pdev, bus) \ + rt_list_for_each_entry(pdev, &bus->devices_nodes, list) \ + if (rt_pci_is_bridge(pdev)) + +rt_err_t rt_pci_bus_read_config_u8(struct rt_pci_bus *bus, + rt_uint32_t devfn, int pos, rt_uint8_t *value); +rt_err_t rt_pci_bus_read_config_u16(struct rt_pci_bus *bus, + rt_uint32_t devfn, int pos, rt_uint16_t *value); +rt_err_t rt_pci_bus_read_config_u32(struct rt_pci_bus *bus, + rt_uint32_t devfn, int pos, rt_uint32_t *value); + +rt_err_t rt_pci_bus_write_config_u8(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, rt_uint8_t value); +rt_err_t rt_pci_bus_write_config_u16(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, rt_uint16_t value); +rt_err_t rt_pci_bus_write_config_u32(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, rt_uint32_t value); + +rt_err_t rt_pci_bus_read_config_uxx(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, int width, rt_uint32_t *value); +rt_err_t rt_pci_bus_write_config_uxx(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, int width, rt_uint32_t value); + +rt_err_t rt_pci_bus_read_config_generic_u32(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, int width, rt_uint32_t *value); +rt_err_t rt_pci_bus_write_config_generic_u32(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, int width, rt_uint32_t value); + +rt_inline rt_err_t rt_pci_read_config_u8(const struct rt_pci_device *pdev, + int reg, rt_uint8_t *value) +{ + return rt_pci_bus_read_config_u8(pdev->bus, pdev->devfn, reg, value); +} + +rt_inline rt_err_t rt_pci_read_config_u16(const struct rt_pci_device *pdev, + int reg, rt_uint16_t *value) +{ + return rt_pci_bus_read_config_u16(pdev->bus, pdev->devfn, reg, value); +} + +rt_inline rt_err_t rt_pci_read_config_u32(const struct rt_pci_device *pdev, + int reg, rt_uint32_t *value) +{ + return rt_pci_bus_read_config_u32(pdev->bus, pdev->devfn, reg, value); +} + +rt_inline rt_err_t rt_pci_write_config_u8(const struct rt_pci_device *pdev, + int reg, rt_uint8_t value) +{ + return rt_pci_bus_write_config_u8(pdev->bus, pdev->devfn, reg, value); +} + +rt_inline rt_err_t rt_pci_write_config_u16(const struct rt_pci_device *pdev, + int reg, rt_uint16_t value) +{ + return rt_pci_bus_write_config_u16(pdev->bus, pdev->devfn, reg, value); +} + +rt_inline rt_err_t rt_pci_write_config_u32(const struct rt_pci_device *pdev, + int reg, rt_uint32_t value) +{ + return rt_pci_bus_write_config_u32(pdev->bus, pdev->devfn, reg, value); +} + +#ifdef RT_USING_OFW +int rt_pci_ofw_irq_parse_and_map(struct rt_pci_device *pdev, + rt_uint8_t slot, rt_uint8_t pin); + +rt_err_t rt_pci_ofw_parse_ranges(struct rt_ofw_node *dev_np, + struct rt_pci_host_bridge *host_bridge); + +rt_err_t rt_pci_ofw_host_bridge_init(struct rt_ofw_node *dev_np, + struct rt_pci_host_bridge *host_bridge); + +rt_err_t rt_pci_ofw_bus_init(struct rt_pci_bus *bus); +rt_err_t rt_pci_ofw_bus_free(struct rt_pci_bus *bus); +rt_err_t rt_pci_ofw_device_init(struct rt_pci_device *pdev); +rt_err_t rt_pci_ofw_device_free(struct rt_pci_device *pdev); +#else +rt_inline rt_err_t rt_pci_ofw_host_bridge_init(struct rt_ofw_node *dev_np, + struct rt_pci_host_bridge *host_bridge) +{ + return RT_EOK; +} +rt_inline rt_err_t rt_pci_ofw_bus_init(struct rt_pci_bus *bus) +{ + return RT_EOK; +} +rt_inline rt_err_t rt_pci_ofw_bus_free(struct rt_pci_bus *bus) +{ + return RT_EOK; +} +rt_inline rt_err_t rt_pci_ofw_device_init(struct rt_pci_device *pdev) +{ + return RT_EOK; +} +rt_inline rt_err_t rt_pci_ofw_device_free(struct rt_pci_device *pdev) +{ + return RT_EOK; +} +rt_inline int rt_pci_ofw_irq_parse_and_map(struct rt_pci_device *pdev, + rt_uint8_t slot, rt_uint8_t pin) +{ + return -1; +} +rt_inline rt_err_t rt_pci_ofw_parse_ranges(struct rt_ofw_node *dev_np, + struct rt_pci_host_bridge *host_bridge) +{ + return -RT_ENOSYS; +} +#endif /* RT_USING_OFW */ + +rt_inline void *rt_pci_iomap(struct rt_pci_device *pdev, int bar_idx) +{ + struct rt_pci_bus_resource *res = &pdev->resource[bar_idx]; + + RT_ASSERT(bar_idx < RT_ARRAY_SIZE(pdev->resource)); + + return rt_ioremap((void *)res->base, res->size); +} + +rt_uint8_t rt_pci_irq_intx(struct rt_pci_device *pdev, rt_uint8_t pin); +rt_uint8_t rt_pci_irq_slot(struct rt_pci_device *pdev, rt_uint8_t *pinp); + +void rt_pci_assign_irq(struct rt_pci_device *pdev); + +void rt_pci_intx(struct rt_pci_device *pdev, rt_bool_t enable); +rt_bool_t rt_pci_check_and_mask_intx(struct rt_pci_device *pdev); +rt_bool_t rt_pci_check_and_unmask_intx(struct rt_pci_device *pdev); + +void rt_pci_irq_mask(struct rt_pci_device *pdev); +void rt_pci_irq_unmask(struct rt_pci_device *pdev); + +#define RT_PCI_IRQ_F_LEGACY RT_BIT(0) /* Allow legacy interrupts */ +#define RT_PCI_IRQ_F_MSI RT_BIT(1) /* Allow MSI interrupts */ +#define RT_PCI_IRQ_F_MSIX RT_BIT(2) /* Allow MSI-X interrupts */ +#define RT_PCI_IRQ_F_AFFINITY RT_BIT(3) /* Auto-assign affinity */ +#define RT_PCI_IRQ_F_ALL_TYPES (RT_PCI_IRQ_F_LEGACY | RT_PCI_IRQ_F_MSI | RT_PCI_IRQ_F_MSIX) + +#ifdef RT_PCI_MSI +rt_ssize_t rt_pci_alloc_vector(struct rt_pci_device *pdev, int min, int max, + rt_uint32_t flags, RT_IRQ_AFFINITY_DECLARE((*affinities))); +void rt_pci_free_vector(struct rt_pci_device *pdev); + +rt_ssize_t rt_pci_msi_vector_count(struct rt_pci_device *pdev); +rt_err_t rt_pci_msi_disable(struct rt_pci_device *pdev); +rt_ssize_t rt_pci_msi_enable_range_affinity(struct rt_pci_device *pdev, + int min, int max, RT_IRQ_AFFINITY_DECLARE((*affinities))); + +rt_ssize_t rt_pci_msix_vector_count(struct rt_pci_device *pdev); +rt_err_t rt_pci_msix_disable(struct rt_pci_device *pdev); +rt_ssize_t rt_pci_msix_enable_range_affinity(struct rt_pci_device *pdev, + struct rt_pci_msix_entry *entries, int min, int max, + RT_IRQ_AFFINITY_DECLARE((*affinities))); +#else +rt_inline rt_ssize_t rt_pci_alloc_vector(struct rt_pci_device *pdev, int min, int max, + rt_uint32_t flags, RT_IRQ_AFFINITY_DECLARE((*affinities))) +{ + return -RT_ENOSYS; +} + +rt_inline void rt_pci_free_vector(struct rt_pci_device *pdev) +{ + return; +} + +rt_inline rt_ssize_t rt_pci_msi_vector_count(struct rt_pci_device *pdev) +{ + return 0; +} + +rt_inline rt_err_t rt_pci_msi_disable(struct rt_pci_device *pdev) +{ + return RT_EOK; +} + +rt_inline rt_ssize_t rt_pci_msi_enable_range_affinity(struct rt_pci_device *pdev, + int min, int max, RT_IRQ_AFFINITY_DECLARE((*affinities))) +{ + return -RT_ENOSYS; +} + +rt_inline rt_ssize_t rt_pci_msix_vector_count(struct rt_pci_device *pdev) +{ + return 0; +} + +rt_inline rt_err_t rt_pci_msix_disable(struct rt_pci_device *pdev) +{ + return RT_EOK; +} + +rt_inline rt_ssize_t rt_pci_msix_enable_range_affinity(struct rt_pci_device *pdev, + struct rt_pci_msix_entry *entries, int min, int max, + RT_IRQ_AFFINITY_DECLARE((*affinities))) +{ + return -RT_ENOSYS; +} +#endif /* RT_PCI_MSI */ + +rt_inline void rt_pci_msix_entry_index_linear(struct rt_pci_msix_entry *entries, + rt_size_t nvectors) +{ + for (int i = 0; i < nvectors; ++i) + { + entries[i].index = i; + } +} + +rt_inline rt_ssize_t rt_pci_msi_enable_range(struct rt_pci_device *pdev, + int min, int max) +{ + return rt_pci_msi_enable_range_affinity(pdev, min, max, RT_NULL); +} + +rt_inline rt_err_t rt_pci_msi_enable(struct rt_pci_device *pdev) +{ + rt_ssize_t res = rt_pci_msi_enable_range(pdev, 1, 1); + return res == 1 ? res : RT_EOK; +} + +rt_inline rt_ssize_t rt_pci_msix_enable_range(struct rt_pci_device *pdev, + struct rt_pci_msix_entry *entries, int min, int max) +{ + return rt_pci_msix_enable_range_affinity(pdev, entries, min, max, RT_NULL); +} + +rt_inline rt_ssize_t rt_pci_msix_enable(struct rt_pci_device *pdev, + struct rt_pci_msix_entry *entries, int count) +{ + return rt_pci_msix_enable_range(pdev, entries, count, count); +} + +rt_err_t rt_pci_region_setup(struct rt_pci_host_bridge *host_bridge); +struct rt_pci_bus_region *rt_pci_region_alloc(struct rt_pci_host_bridge *host_bridge, + void **out_addr, rt_size_t size, rt_ubase_t flags, rt_bool_t mem64); + +rt_err_t rt_pci_device_alloc_resource(struct rt_pci_host_bridge *host_bridge, + struct rt_pci_device *pdev); + +void rt_pci_enum_device(struct rt_pci_bus *bus, + rt_bool_t (callback(struct rt_pci_device *, void *)), void *data); + +const struct rt_pci_device_id *rt_pci_match_id(struct rt_pci_device *pdev, + const struct rt_pci_device_id *id); + +const struct rt_pci_device_id *rt_pci_match_ids(struct rt_pci_device *pdev, + const struct rt_pci_device_id *ids); + +rt_err_t rt_pci_driver_register(struct rt_pci_driver *pdrv); +rt_err_t rt_pci_device_register(struct rt_pci_device *pdev); +struct rt_pci_bus_resource *rt_pci_find_bar(struct rt_pci_device* pdev,rt_ubase_t flags,int index); +#define RT_PCI_DRIVER_EXPORT(driver) RT_DRIVER_EXPORT(driver, pci, BUILIN) + +extern struct rt_spinlock rt_pci_lock; + +#endif /* __PCI_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/pci_endpoint.h b/rt-thread/components/drivers/include/drivers/pci_endpoint.h new file mode 100644 index 0000000..c43c182 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/pci_endpoint.h @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-08-25 GuEe-GUI first version + */ + +#ifndef __PCI_ENDPOINT_H__ +#define __PCI_ENDPOINT_H__ + +#include + +enum rt_pci_ep_pin +{ + RT_PCI_EP_PIN_UNKNOWN, + RT_PCI_EP_PIN_INTA, + RT_PCI_EP_PIN_INTB, + RT_PCI_EP_PIN_INTC, + RT_PCI_EP_PIN_INTD, +}; + +enum rt_pci_ep_irq +{ + RT_PCI_EP_IRQ_UNKNOWN, + RT_PCI_EP_IRQ_LEGACY, + RT_PCI_EP_IRQ_MSI, + RT_PCI_EP_IRQ_MSIX, +}; + +struct rt_pci_ep_header +{ + rt_uint16_t vendor; + rt_uint16_t device; + rt_uint8_t revision; + rt_uint8_t progif; + rt_uint8_t subclass; + rt_uint8_t class_code; + rt_uint8_t cache_line_size; + rt_uint16_t subsystem_vendor; + rt_uint16_t subsystem_device; + + enum rt_pci_ep_pin intx; +}; + +struct rt_pci_ep_bar +{ + /* To PCI Bus */ + struct rt_pci_bus_resource bus; + /* To CPU */ + rt_ubase_t cpu_addr; +}; + +/* + * Type of MSI-X table, For more format detail, + * please read `components/drivers/include/drivers/pci_msi.h` + */ +struct rt_pci_ep_msix_tbl +{ + union + { + rt_uint64_t msg_addr; + struct + { + rt_uint32_t msg_addr_upper; + rt_uint32_t msg_addr_lower; + }; + }; + rt_uint32_t msg_data; + rt_uint32_t vector_ctrl; +}; + +struct rt_pci_ep_ops; +struct rt_pci_ep_mem; + +struct rt_pci_ep +{ + rt_list_t list; + const char *name; + + struct rt_ref ref; + + const struct rt_device *rc_dev; + const struct rt_pci_ep_ops *ops; + + rt_size_t mems_nr; + struct rt_pci_ep_mem *mems; + + rt_uint8_t max_functions; + RT_BITMAP_DECLARE(functions_map, 8); + rt_list_t epf_nodes; + struct rt_mutex lock; + + void *priv; +}; + +struct rt_pci_ep_mem +{ + rt_ubase_t cpu_addr; + rt_size_t size; + rt_size_t page_size; + + rt_bitmap_t *map; + rt_size_t bits; +}; + +struct rt_pci_epf +{ + rt_list_t list; + const char *name; + + struct rt_pci_ep_header *header; + struct rt_pci_ep_bar bar[PCI_STD_NUM_BARS]; + + rt_uint8_t msi_interrupts; + rt_uint16_t msix_interrupts; + rt_uint8_t func_no; + + struct rt_pci_ep *ep; +}; + +struct rt_pci_ep_ops +{ + rt_err_t (*write_header)(struct rt_pci_ep *ep, rt_uint8_t func_no, + struct rt_pci_ep_header *hdr); + + rt_err_t (*set_bar)(struct rt_pci_ep *ep, rt_uint8_t func_no, + struct rt_pci_ep_bar *bar, int bar_idx); + rt_err_t (*clear_bar)(struct rt_pci_ep *ep, rt_uint8_t func_no, + struct rt_pci_ep_bar *bar, int bar_idx); + + rt_err_t (*map_addr)(struct rt_pci_ep *ep, rt_uint8_t func_no, + rt_ubase_t addr, rt_uint64_t pci_addr, rt_size_t size); + rt_err_t (*unmap_addr)(struct rt_pci_ep *ep, rt_uint8_t func_no, rt_ubase_t addr); + + rt_err_t (*set_msi)(struct rt_pci_ep *ep, rt_uint8_t func_no, + unsigned irq_nr); + rt_err_t (*get_msi)(struct rt_pci_ep *ep, rt_uint8_t func_no, + unsigned *out_irq_nr); + + rt_err_t (*set_msix)(struct rt_pci_ep *ep, rt_uint8_t func_no, + unsigned irq_nr, int bar_idx, rt_off_t offset); + rt_err_t (*get_msix)(struct rt_pci_ep *ep, rt_uint8_t func_no, + unsigned *out_irq_nr); + + rt_err_t (*raise_irq)(struct rt_pci_ep *ep, rt_uint8_t func_no, + enum rt_pci_ep_irq type, unsigned irq); + + rt_err_t (*start)(struct rt_pci_ep *ep); + rt_err_t (*stop)(struct rt_pci_ep *ep); +}; + +rt_err_t rt_pci_ep_write_header(struct rt_pci_ep *ep, rt_uint8_t func_no, + struct rt_pci_ep_header *hdr); + +rt_err_t rt_pci_ep_set_bar(struct rt_pci_ep *ep, rt_uint8_t func_no, + struct rt_pci_ep_bar *bar, int bar_idx); +rt_err_t rt_pci_ep_clear_bar(struct rt_pci_ep *ep, rt_uint8_t func_no, + struct rt_pci_ep_bar *bar, int bar_idx); + +rt_err_t rt_pci_ep_map_addr(struct rt_pci_ep *ep, rt_uint8_t func_no, + rt_ubase_t addr, rt_uint64_t pci_addr, rt_size_t size); +rt_err_t rt_pci_ep_unmap_addr(struct rt_pci_ep *ep, rt_uint8_t func_no, + rt_ubase_t addr); + +rt_err_t rt_pci_ep_set_msi(struct rt_pci_ep *ep, rt_uint8_t func_no, + unsigned irq_nr); +rt_err_t rt_pci_ep_get_msi(struct rt_pci_ep *ep, rt_uint8_t func_no, + unsigned *out_irq_nr); + +rt_err_t rt_pci_ep_set_msix(struct rt_pci_ep *ep, rt_uint8_t func_no, + unsigned irq_nr, int bar_idx, rt_off_t offset); +rt_err_t rt_pci_ep_get_msix(struct rt_pci_ep *ep, rt_uint8_t func_no, + unsigned *out_irq_nr); + +rt_err_t rt_pci_ep_raise_irq(struct rt_pci_ep *ep, rt_uint8_t func_no, + enum rt_pci_ep_irq type, unsigned irq); + +rt_err_t rt_pci_ep_start(struct rt_pci_ep *ep); +rt_err_t rt_pci_ep_stop(struct rt_pci_ep *ep); + +rt_err_t rt_pci_ep_register(struct rt_pci_ep *ep); +rt_err_t rt_pci_ep_unregister(struct rt_pci_ep *ep); + +rt_err_t rt_pci_ep_mem_array_init(struct rt_pci_ep *ep, + struct rt_pci_ep_mem *mems, rt_size_t mems_nr); +rt_err_t rt_pci_ep_mem_init(struct rt_pci_ep *ep, + rt_ubase_t cpu_addr, rt_size_t size, rt_size_t page_size); + +void *rt_pci_ep_mem_alloc(struct rt_pci_ep *ep, + rt_ubase_t *out_cpu_addr, rt_size_t size); +void rt_pci_ep_mem_free(struct rt_pci_ep *ep, + void *vaddr, rt_ubase_t cpu_addr, rt_size_t size); + +rt_err_t rt_pci_ep_add_epf(struct rt_pci_ep *ep, struct rt_pci_epf *epf); +rt_err_t rt_pci_ep_remove_epf(struct rt_pci_ep *ep, struct rt_pci_epf *epf); + +struct rt_pci_ep *rt_pci_ep_get(const char *name); +void rt_pci_ep_put(struct rt_pci_ep *ep); + +#endif /* __PCI_ENDPOINT_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/pci_msi.h b/rt-thread/components/drivers/include/drivers/pci_msi.h new file mode 100644 index 0000000..b8238e6 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/pci_msi.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-08-25 GuEe-GUI first version + */ + +#ifndef __PCI_MSI_H__ +#define __PCI_MSI_H__ + +#include + +/* + * MSI Format: + * T0: 32-bit Address + * T1: 64-bit Address + * T2: 32-bit Address with Per-Vector Masking + * T3: 64-bit Address with Per-Vector Masking + * + * 31 16 15 8 7 0 + * +---------------------------+-----------------+---------------+ + * | Message Control | Next Capability | Capability ID | DW0 + * | | Pointer | (05h) | + * +---------------------------+-----------------+---------------+ + * | Message Address [31:0] | DW1 + * +-------------------------------------------------------------+ + * | Message Address [63:32] | DW2 (T1: only 64-bit) + * +---------------------------+---------------------------------+ + * | Reserved | Message Data | DW3 + * +---------------------------+---------------------------------+ + * | Mask Bits | DW4 (T2/T3: only with Per-Vector Masking) + * +-------------------------------------------------------------+ + * | Pending Bits | DW5 (T2/T3: only with Per-Vector Masking) + * +-------------------------------------------------------------+ + * + * MSI Message Control: + * + * 15 9 8 7 6 4 3 1 0 + * +----------------------+---+---+---------------+----------+---+ + * | Reserved | | | | | | + * +----------------------+---+---+---------------+----------+---+ + * ^ ^ ^ ^ ^ + * | | | | | + * | | | | +---- MSI Enable (RW) + * | | | +----------- Multiple Message Capable (RO, log2n, [n <= 5]) + * | | +------------------------- Multiple Message Enable (RW, log2n, [n <= 5]) + * | +----------------------------------- 64-bit Address Capable + * +--------------------------------------- Per-Vector Masking Capable + */ + +struct rt_pci_msi_conf +{ + rt_uint32_t mask; + rt_uint8_t mask_pos; + int default_irq; + + struct + { + rt_uint8_t is_masking:1; + rt_uint8_t is_64bit:1; + rt_uint8_t multi_msg_max:3; /* log2 num of messages allocated */ + rt_uint8_t multi_msg_use:3; /* log2 num of messages supported */ + } cap; +}; + +/* + * MSI-X Format: + * + * 31 16 15 8 7 0 + * +---------------------------+-----------------+---------------+ + * | Message Control | Next Capability | Capability ID | DW0 + * | | Pointer | (11h) | + * +---------------------------+-----------------+---+-----------+ + * | MSI-X Table Offset | Table BIR | DW1 (BIR: BAR Index Register) + * +-------------------------------------------------+-----------+ | + * | Pending Bit Array (PBA) Offset | PBA BIR | DW2 --------+ | + * +-------------------------------------------------+-----------+ | | + * | | + * MSI-X Message Control: | | + * | | + * 15 14 13 11 10 0 | | + * +---+---+----------+------------------------------------------+ | | + * | | | Reserved | Table Size in N-1 (RO) | | | + * +---+---+----------+------------------------------------------+ | | + * ^ ^ | | + * | | | | + * | +---- Function Mask (RW) | | + * +-------- MSI-X Enable (RW) | | + * | | + * MSI-X Table (BAR[Table BIR] + MSI-X Table Offset): | | + * | | + * DW3 DW2 DW1 DW0 | | + * +----------------+--------------+---------------+---------------+ <---------|-+ + * | Vector Control | Message Data | Upper Address | Lower Address | Entry 0 | + * +----------------+--------------+---------------+---------------+ | + * | Vector Control | Message Data | Upper Address | Lower Address | Entry 1 | + * +----------------+--------------+---------------+---------------+ | + * | ...... | ...... | ...... | ...... | | + * +----------------+--------------+---------------+---------------+ | + * | Vector Control | Message Data | Upper Address | Lower Address | Entry N-1 | + * +----------------+--------------+---------------+---------------+ | + * ^ | + * | | + * +---- Bit 0 is vector Mask Bit (R/W) | + * | + * MSI-X Pending Bit Array (BAR[PBA BIR] + Pending Bit Array Offset): | + * | + * DW1 DW0 | + * +-------------------------------+ <-----------------------------------------+ + * | Pending Bits 0 - 63 | QW 0 + * +-------------------------------+ + * | Pending Bits 64 - 127 | QW 1 + * +-------------------------------+ + * | ...... | + * +-------------------------------+ + * | Pending Bits | QW (N-1)/64 + * +-------------------------------+ + */ + +struct rt_pci_msix_conf +{ + int index; + + rt_uint32_t msg_ctrl; + void *table_base; +}; + +struct rt_pci_msi_msg +{ + rt_uint32_t address_lo; + rt_uint32_t address_hi; + rt_uint32_t data; +}; + +struct rt_pci_msi_desc +{ + rt_list_t list; + + int irq; + rt_size_t vector_used; + rt_size_t vector_count; + + union + { + /* For MSI-X */ + rt_bitmap_t *affinity; + /* For MSI */ + rt_bitmap_t **affinities; + }; + + struct rt_pci_device *pdev; + struct rt_pci_msi_msg msg; + + void *write_msi_msg_data; + void (*write_msi_msg)(struct rt_pci_msi_desc *, void *); + + rt_bool_t is_msix; + union + { + struct rt_pci_msi_conf msi; + struct rt_pci_msix_conf msix; + }; + + void *priv; +}; + +#define rt_pci_msi_first_desc(pdev) \ + (rt_list_isempty(&(pdev)->msi_desc_nodes) ? RT_NULL : \ + rt_list_first_entry(&(pdev)->msi_desc_nodes, struct rt_pci_msi_desc, list)) + +#define rt_pci_msi_for_each_desc(pdev, desc) \ + rt_list_for_each_entry(desc, &(pdev)->msi_desc_nodes, list) + +#define rt_pci_msix_table_size(flags) ((flags & PCIM_MSIXCTRL_TABLE_SIZE) + 1) + +rt_err_t rt_pci_msi_setup_irqs(struct rt_pci_device *pdev, int nvec, int type); + +void rt_pci_msi_shutdown(struct rt_pci_device *pdev); +void rt_pci_msix_shutdown(struct rt_pci_device *pdev); +void rt_pci_msi_free_irqs(struct rt_pci_device *pdev); +void rt_pci_msi_write_msg(struct rt_pci_msi_desc *desc, struct rt_pci_msi_msg *msg); + +void rt_pci_msi_mask_irq(struct rt_pic_irq *pirq); +void rt_pci_msi_unmask_irq(struct rt_pic_irq *pirq); + +#endif /* __PCI_MSI_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/phy.h b/rt-thread/components/drivers/include/drivers/phy.h index c51c494..a8dcd08 100644 --- a/rt-thread/components/drivers/include/drivers/phy.h +++ b/rt-thread/components/drivers/include/drivers/phy.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,18 +7,172 @@ * Date Author Notes * 2020-10-14 wangqiang the first version * 2022-08-17 xjy198903 add 1000M definition + * 2024-10-08 zhujiale add phy v2.0 */ - -#ifndef __PHY_H__ -#define __PHY_H__ - +#ifndef __NET_PHY_H__ +#define __NET_PHY_H__ #include +#include +#ifdef RT_USING_PHY_V2 +#include +#include +#include +#define RT_PHY_FIXED_ID 0xa5a55a5a +#define RT_PHY_NCSI_ID 0xbeefcafe + + +/* Indicates what features are supported by the interface. */ +#define RT_SUPPORTED_10baseT_Half (1 << 0) +#define RT_SUPPORTED_10baseT_Full (1 << 1) +#define RT_SUPPORTED_100baseT_Half (1 << 2) +#define RT_SUPPORTED_100baseT_Full (1 << 3) +#define RT_SUPPORTED_1000baseT_Half (1 << 4) +#define RT_SUPPORTED_1000baseT_Full (1 << 5) +#define RT_SUPPORTED_Autoneg (1 << 6) +#define RT_SUPPORTED_TP (1 << 7) +#define RT_SUPPORTED_AUI (1 << 8) +#define RT_SUPPORTED_MII (1 << 9) +#define RT_SUPPORTED_FIBRE (1 << 10) +#define RT_SUPPORTED_BNC (1 << 11) +#define RT_SUPPORTED_10000baseT_Full (1 << 12) +#define RT_SUPPORTED_Pause (1 << 13) +#define RT_SUPPORTED_Asym_Pause (1 << 14) +#define RT_SUPPORTED_2500baseX_Full (1 << 15) +#define RT_SUPPORTED_Backplane (1 << 16) +#define RT_SUPPORTED_1000baseKX_Full (1 << 17) +#define RT_SUPPORTED_10000baseKX4_Full (1 << 18) +#define RT_SUPPORTED_10000baseKR_Full (1 << 19) +#define RT_SUPPORTED_10000baseR_FEC (1 << 20) +#define RT_SUPPORTED_1000baseX_Half (1 << 21) +#define RT_SUPPORTED_1000baseX_Full (1 << 22) + +#define RT_PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */ +#define RT_PHY_DEFAULT_FEATURES (RT_SUPPORTED_Autoneg | RT_SUPPORTED_TP | RT_SUPPORTED_MII) + +#define RT_PHY_10BT_FEATURES (RT_SUPPORTED_10baseT_Half | RT_SUPPORTED_10baseT_Full) + +#define RT_PHY_100BT_FEATURES (RT_SUPPORTED_100baseT_Half | RT_SUPPORTED_100baseT_Full) + +#define RT_PHY_1000BT_FEATURES (RT_SUPPORTED_1000baseT_Half | RT_SUPPORTED_1000baseT_Full) + +#define RT_PHY_BASIC_FEATURES (RT_PHY_10BT_FEATURES | RT_PHY_100BT_FEATURES | RT_PHY_DEFAULT_FEATURES) + +#define RT_PHY_GBIT_FEATURES (RT_PHY_BASIC_FEATURES | RT_PHY_1000BT_FEATURES) + +#define RT_PHY_10G_FEATURES (RT_PHY_GBIT_FEATURES | RT_SUPPORTED_10000baseT_Full) +struct rt_phy_device +{ + struct rt_device parent; + struct mii_bus *bus; + struct rt_phy_driver *drv; + rt_uint32_t phy_id; + rt_uint32_t mmds; + int speed; + int duplex; + int link; + int port; + rt_uint32_t advertising; + rt_uint32_t supported; + rt_bool_t autoneg; + int pause; + rt_ubase_t addr; + rt_bool_t is_c45; + rt_uint32_t flags; + rt_phy_interface interface; + +#ifdef RT_USING_OFW + struct rt_ofw_node *node; +#endif + void *priv; +}; + +struct rt_phy_driver +{ + struct rt_driver parent; + char name[RT_NAME_MAX]; + rt_uint64_t uid; + rt_uint64_t mask; + rt_uint64_t mmds; + rt_uint32_t features; + + int (*probe)(struct rt_phy_device *phydev); + int (*config)(struct rt_phy_device *phydev); + int (*startup)(struct rt_phy_device *phydev); + int (*shutdown)(struct rt_phy_device *phydev); + int (*read)(struct rt_phy_device *phydev, int addr, int devad, int reg); + int (*write)(struct rt_phy_device *phydev, int addr, int devad, int reg, + rt_uint16_t val); + int (*read_mmd)(struct rt_phy_device *phydev, int devad, int reg); + int (*write_mmd)(struct rt_phy_device *phydev, int devad, int reg, + rt_uint16_t val); + + /* driver private data */ + void *data; +}; + +int rt_phy_read(struct rt_phy_device *phydev, int devad, int regnum); +int rt_phy_write(struct rt_phy_device *phydev, int devad, int regnum, rt_uint16_t val); +int rt_phy_read_mmd(struct rt_phy_device *phydev, int devad, int regnum); +int rt_phy_write_mmd(struct rt_phy_device *phydev, int devad, int regnum, rt_uint16_t val); +int rt_phy_reset(struct rt_phy_device *phydev); +int rt_phy_startup(struct rt_phy_device *phydev); +int rt_phy_config(struct rt_phy_device *phydev); +int rt_phy_shutdown(struct rt_phy_device *phydev); +int rt_phy_read_mmd(struct rt_phy_device *phydev, int devad, int regnum); +int rt_phy_set_supported(struct rt_phy_device *phydev, rt_uint32_t max_speed); + +void rt_phy_mmd_start_indirect(struct rt_phy_device *phydev, int devad, int regnum); + +rt_err_t rt_phy_device_register(struct rt_phy_device *pdev); +rt_err_t rt_phy_driver_register(struct rt_phy_driver *pdrv); +rt_err_t rt_ofw_get_phyid(struct rt_ofw_node *np,rt_uint32_t *id); + +struct rt_phy_device *rt_phy_device_create(struct mii_bus *bus, int addr, rt_uint32_t phy_id, rt_bool_t is_c45); +struct rt_phy_device *rt_phy_find_by_mask(struct mii_bus *bus, unsigned int phy_mask); +struct rt_phy_device *rt_ofw_create_phy(struct mii_bus *bus, struct rt_ofw_node *np, int phyaddr); +struct rt_phy_device *rt_phy_get_device(struct mii_bus *bus, struct rt_ofw_node *np, int addr, rt_phy_interface interface); + +#define RT_PHY_DEVICE_REGISTER(phy_dev) \ +static int rt_##phy_dev##_register(void) \ +{ \ + rt_phy_device_register(&phy_dev); \ + return 0; \ +} \ +INIT_PREV_EXPORT(rt_##phy_dev##_register); + +#define RT_PHY_DRIVER_REGISTER(phy_drv) \ +static int rt_##phy_drv##_register(void) \ +{ \ + rt_phy_driver_register(&phy_drv); \ + return 0; \ +} \ +INIT_PREV_EXPORT(rt_##phy_drv##_register); +#endif + +#ifdef RT_USING_PHY #ifdef __cplusplus extern "C" { #endif +struct rt_mdio_bus_ops +{ + rt_bool_t (*init)(void *bus, rt_uint32_t src_clock_hz); + rt_size_t (*read)(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size); + rt_size_t (*write)(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size); + rt_bool_t (*uninit)(void *bus); +}; + +struct rt_mdio_bus +{ + void *hw_obj; + char *name; + struct rt_mdio_bus_ops *ops; +}; + +typedef struct rt_mdio_bus rt_mdio_t; + /* Defines the PHY link speed. This is align with the speed for MAC. */ #define PHY_SPEED_10M 0U /* PHY 10M speed. */ #define PHY_SPEED_100M 1U /* PHY 100M speed. */ @@ -67,5 +221,5 @@ rt_err_t rt_hw_phy_register(struct rt_phy_device *phy, const char *name); #ifdef __cplusplus } #endif - -#endif /* __PHY_H__*/ +#endif +#endif diff --git a/rt-thread/components/drivers/include/drivers/phy_mdio.h b/rt-thread/components/drivers/include/drivers/phy_mdio.h deleted file mode 100644 index b7677d3..0000000 --- a/rt-thread/components/drivers/include/drivers/phy_mdio.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-10-14 wangqiang the first version - */ - -#ifndef __MDIO_H__ -#define __MDIO_H__ - -#include - -#ifdef __cplusplus -extern "C" -{ -#endif - - -struct rt_mdio_bus_ops -{ - rt_bool_t (*init)(void *bus, rt_uint32_t src_clock_hz); - rt_size_t (*read)(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size); - rt_size_t (*write)(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size); - rt_bool_t (*uninit)(void *bus); -}; - -struct rt_mdio_bus -{ - void *hw_obj; - char *name; - struct rt_mdio_bus_ops *ops; -}; - -typedef struct rt_mdio_bus rt_mdio_t; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/rt-thread/components/drivers/include/drivers/phye.h b/rt-thread/components/drivers/include/drivers/phye.h new file mode 100644 index 0000000..3776cde --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/phye.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#ifndef __PHYE_H__ +#define __PHYE_H__ + +#include +#include + +enum rt_phye_mode +{ + RT_PHYE_MODE_INVALID, + RT_PHYE_MODE_USB_HOST, + RT_PHYE_MODE_USB_HOST_LS, + RT_PHYE_MODE_USB_HOST_FS, + RT_PHYE_MODE_USB_HOST_HS, + RT_PHYE_MODE_USB_HOST_SS, + RT_PHYE_MODE_USB_DEVICE, + RT_PHYE_MODE_USB_DEVICE_LS, + RT_PHYE_MODE_USB_DEVICE_FS, + RT_PHYE_MODE_USB_DEVICE_HS, + RT_PHYE_MODE_USB_DEVICE_SS, + RT_PHYE_MODE_USB_OTG, + RT_PHYE_MODE_UFS_HS_A, + RT_PHYE_MODE_UFS_HS_B, + RT_PHYE_MODE_PCIE, + RT_PHYE_MODE_ETHERNET, + RT_PHYE_MODE_MIPI_DPHY, + RT_PHYE_MODE_SATA, + RT_PHYE_MODE_LVDS, + RT_PHYE_MODE_DP, + + RT_PHYE_MODE_MAX, + + /* PCIe */ + RT_PHYE_MODE_PCIE_RC = RT_PHYE_MODE_MAX, + RT_PHYE_MODE_PCIE_EP, + RT_PHYE_MODE_PCIE_BIFURCATION, +}; + +struct rt_phye_ops; + +struct rt_phye +{ + struct rt_device *dev; + + const struct rt_phye_ops *ops; + + int init_count; + int power_count; + struct rt_spinlock lock; +}; + +struct rt_phye_ops +{ + rt_err_t (*init)(struct rt_phye *phye); + rt_err_t (*exit)(struct rt_phye *phye); + rt_err_t (*reset)(struct rt_phye *phye); + rt_err_t (*power_on)(struct rt_phye *phye); + rt_err_t (*power_off)(struct rt_phye *phye); + rt_err_t (*set_mode)(struct rt_phye *phye, enum rt_phye_mode mode, int submode); + rt_err_t (*ofw_parse)(struct rt_phye *phye, struct rt_ofw_cell_args *phye_args); +}; + +rt_err_t rt_phye_register(struct rt_phye *phye); +rt_err_t rt_phye_unregister(struct rt_phye *phye); + +rt_err_t rt_phye_init(struct rt_phye *phye); +rt_err_t rt_phye_exit(struct rt_phye *phye); +rt_err_t rt_phye_reset(struct rt_phye *phye); +rt_err_t rt_phye_power_on(struct rt_phye *phye); +rt_err_t rt_phye_power_off(struct rt_phye *phye); +rt_err_t rt_phye_set_mode(struct rt_phye *phye, enum rt_phye_mode mode, int submode); + +rt_inline rt_err_t rt_phye_set_mode_simple(struct rt_phye *phye, enum rt_phye_mode mode) +{ + return rt_phye_set_mode(phye, mode, RT_PHYE_MODE_INVALID); +} + +struct rt_phye *rt_phye_get_by_index(struct rt_device *dev, int index); +struct rt_phye *rt_phye_get_by_name(struct rt_device *dev, const char *id); +void rt_phye_put(struct rt_phye *phye); + +#endif /* __PHYE_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/pic.h b/rt-thread/components/drivers/include/drivers/pic.h index fa1941a..c624d24 100644 --- a/rt-thread/components/drivers/include/drivers/pic.h +++ b/rt-thread/components/drivers/include/drivers/pic.h @@ -148,6 +148,7 @@ void rt_pic_default_name(struct rt_pic *pic); struct rt_pic *rt_pic_dynamic_cast(void *ptr); rt_err_t rt_pic_linear_irq(struct rt_pic *pic, rt_size_t irq_nr); +rt_err_t rt_pic_cancel_irq(struct rt_pic *pic); int rt_pic_config_ipi(struct rt_pic *pic, int ipi_index, int hwirq); int rt_pic_config_irq(struct rt_pic *pic, int irq_index, int hwirq); diff --git a/rt-thread/components/drivers/include/drivers/platform.h b/rt-thread/components/drivers/include/drivers/platform.h index 5dac676..c4a497d 100644 --- a/rt-thread/components/drivers/include/drivers/platform.h +++ b/rt-thread/components/drivers/include/drivers/platform.h @@ -12,10 +12,7 @@ #ifndef __PLATFORM_H__ #define __PLATFORM_H__ -#ifdef RT_USING_OFW #include -#endif - #include struct rt_platform_device @@ -25,10 +22,7 @@ struct rt_platform_device int dev_id; const char *name; - -#ifdef RT_USING_OFW const struct rt_ofw_node_id *id; -#endif void *priv; }; @@ -38,10 +32,7 @@ struct rt_platform_driver struct rt_driver parent; const char *name; - -#ifdef RT_USING_OFW const struct rt_ofw_node_id *ids; -#endif rt_err_t (*probe)(struct rt_platform_device *pdev); rt_err_t (*remove)(struct rt_platform_device *pdev); @@ -54,6 +45,7 @@ rt_err_t rt_platform_driver_register(struct rt_platform_driver *pdrv); rt_err_t rt_platform_device_register(struct rt_platform_device *pdev); rt_err_t rt_platform_ofw_device_probe_child(struct rt_ofw_node *np); +rt_err_t rt_platform_ofw_request(struct rt_ofw_node *np); rt_err_t rt_platform_ofw_free(struct rt_platform_device *pdev); #define RT_PLATFORM_DRIVER_EXPORT(driver) RT_DRIVER_EXPORT(driver, platform, BUILIN) diff --git a/rt-thread/components/drivers/include/drivers/pm.h b/rt-thread/components/drivers/include/drivers/pm.h index 45b3ae0..f625782 100644 --- a/rt-thread/components/drivers/include/drivers/pm.h +++ b/rt-thread/components/drivers/include/drivers/pm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,6 +10,7 @@ * 2019-04-28 Zero-Free improve PM mode and device ops interface * 2020-11-23 zhangsz update pm mode select * 2020-11-27 zhangsz update pm 2.0 + * 2024-07-04 wdfk-prog The device is registered and uninstalled by linked list */ #ifndef __PM_H__ @@ -134,15 +135,16 @@ struct rt_pm_ops struct rt_device_pm_ops { - int (*suspend)(const struct rt_device *device, rt_uint8_t mode); + rt_err_t (*suspend)(const struct rt_device *device, rt_uint8_t mode); void (*resume)(const struct rt_device *device, rt_uint8_t mode); - int (*frequency_change)(const struct rt_device *device, rt_uint8_t mode); + rt_err_t (*frequency_change)(const struct rt_device *device, rt_uint8_t mode); }; struct rt_device_pm { const struct rt_device *device; const struct rt_device_pm_ops *ops; + rt_slist_t list; }; struct rt_pm_module @@ -172,7 +174,7 @@ struct rt_pm rt_uint32_t sleep_status[PM_SLEEP_MODE_MAX - 1][(PM_MODULE_MAX_ID + 31) / 32]; /* the list of device, which has PM feature */ - rt_uint8_t device_pm_number; + rt_slist_t device_list; struct rt_device_pm *device_pm; /* if the mode has timer, the corresponding bit is 1*/ @@ -194,10 +196,10 @@ struct rt_pm_notify void *data; }; -void rt_pm_request(rt_uint8_t sleep_mode); -void rt_pm_release(rt_uint8_t sleep_mode); -void rt_pm_release_all(rt_uint8_t sleep_mode); -int rt_pm_run_enter(rt_uint8_t run_mode); +rt_err_t rt_pm_request(rt_uint8_t sleep_mode); +rt_err_t rt_pm_release(rt_uint8_t sleep_mode); +rt_err_t rt_pm_release_all(rt_uint8_t sleep_mode); +rt_err_t rt_pm_run_enter(rt_uint8_t run_mode); void rt_pm_device_register(struct rt_device *device, const struct rt_device_pm_ops *ops); void rt_pm_device_unregister(struct rt_device *device); @@ -208,22 +210,22 @@ void rt_pm_default_set(rt_uint8_t sleep_mode); void rt_system_pm_init(const struct rt_pm_ops *ops, rt_uint8_t timer_mask, void *user_data); -void rt_pm_module_request(uint8_t module_id, rt_uint8_t sleep_mode); -void rt_pm_module_release(uint8_t module_id, rt_uint8_t sleep_mode); -void rt_pm_module_release_all(uint8_t module_id, rt_uint8_t sleep_mode); +rt_err_t rt_pm_module_request(uint8_t module_id, rt_uint8_t sleep_mode); +rt_err_t rt_pm_module_release(uint8_t module_id, rt_uint8_t sleep_mode); +rt_err_t rt_pm_module_release_all(uint8_t module_id, rt_uint8_t sleep_mode); void rt_pm_module_delay_sleep(rt_uint8_t module_id, rt_tick_t timeout); rt_uint32_t rt_pm_module_get_status(void); rt_uint8_t rt_pm_get_sleep_mode(void); struct rt_pm *rt_pm_get_handle(void); /* sleep : request or release */ -void rt_pm_sleep_request(rt_uint16_t module_id, rt_uint8_t mode); -void rt_pm_sleep_release(rt_uint16_t module_id, rt_uint8_t mode); -void rt_pm_sleep_none_request(rt_uint16_t module_id); -void rt_pm_sleep_none_release(rt_uint16_t module_id); -void rt_pm_sleep_idle_request(rt_uint16_t module_id); -void rt_pm_sleep_idle_release(rt_uint16_t module_id); -void rt_pm_sleep_light_request(rt_uint16_t module_id); -void rt_pm_sleep_light_release(rt_uint16_t module_id); +rt_err_t rt_pm_sleep_request(rt_uint16_t module_id, rt_uint8_t mode); +rt_err_t rt_pm_sleep_release(rt_uint16_t module_id, rt_uint8_t mode); +rt_err_t rt_pm_sleep_none_request(rt_uint16_t module_id); +rt_err_t rt_pm_sleep_none_release(rt_uint16_t module_id); +rt_err_t rt_pm_sleep_idle_request(rt_uint16_t module_id); +rt_err_t rt_pm_sleep_idle_release(rt_uint16_t module_id); +rt_err_t rt_pm_sleep_light_request(rt_uint16_t module_id); +rt_err_t rt_pm_sleep_light_release(rt_uint16_t module_id); #endif /* __PM_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/regulator.h b/rt-thread/components/drivers/include/drivers/regulator.h new file mode 100644 index 0000000..d74fc64 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/regulator.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#ifndef __REGULATOR_H__ +#define __REGULATOR_H__ + +#include +#include +#include + +#include + +#define RT_REGULATOR_UVOLT_INVALID (((int)(RT_UINT32_MAX >> 1))) + +struct rt_regulator_param +{ + const char *name; + + int min_uvolt; /* In uV */ + int max_uvolt; /* In uV */ + int min_uamp; /* In uA */ + int max_uamp; /* In uA */ + int ramp_delay; /* In uV/usec */ + int enable_delay; /* In usec */ + int off_on_delay; /* In usec */ + + rt_uint32_t enable_active_high:1; + rt_uint32_t boot_on:1; /* Is enabled on boot */ + rt_uint32_t always_on:1; /* Must be enabled */ + rt_uint32_t soft_start:1; /* Ramp voltage slowly */ + rt_uint32_t pull_down:1; /* Pull down resistor when regulator off */ + rt_uint32_t over_current_protection:1; /* Auto disable on over current */ +}; + +struct rt_regulator_ops; + +struct rt_regulator_node +{ + rt_list_t list; + rt_list_t children_nodes; + + struct rt_device *dev; + struct rt_regulator_node *parent; + + const char *supply_name; + const struct rt_regulator_ops *ops; + + struct rt_ref ref; + rt_atomic_t enabled_count; + + const struct rt_regulator_param *param; + + rt_list_t notifier_nodes; + + void *priv; +}; + +/* + * NOTE: Power regulator control is dangerous work. We don't want non-internal + * consumer could access the power regulator tree without regulator's API. So + * we defined the `rt_regulator` member in core instead of here. + */ +struct rt_regulator; + +#define RT_REGULATOR_MODE_INVALID 0 +#define RT_REGULATOR_MODE_FAST RT_BIT(0) +#define RT_REGULATOR_MODE_NORMAL RT_BIT(1) +#define RT_REGULATOR_MODE_IDLE RT_BIT(2) +#define RT_REGULATOR_MODE_STANDBY RT_BIT(3) + +struct rt_regulator_ops +{ + rt_err_t (*enable)(struct rt_regulator_node *reg); + rt_err_t (*disable)(struct rt_regulator_node *reg); + rt_bool_t (*is_enabled)(struct rt_regulator_node *reg); + rt_err_t (*set_voltage)(struct rt_regulator_node *reg, int min_uvolt, int max_uvolt); + int (*get_voltage)(struct rt_regulator_node *reg); + rt_err_t (*set_mode)(struct rt_regulator_node *reg, rt_uint32_t mode); + rt_int32_t (*get_mode)(struct rt_regulator_node *reg); + rt_err_t (*set_ramp_delay)(struct rt_regulator_node *reg, int ramp); + rt_uint32_t (*enable_time)(struct rt_regulator_node *reg); +}; + +struct rt_regulator_notifier; + +#define RT_REGULATOR_MSG_ENABLE RT_BIT(0) +#define RT_REGULATOR_MSG_DISABLE RT_BIT(1) +#define RT_REGULATOR_MSG_VOLTAGE_CHANGE RT_BIT(2) +#define RT_REGULATOR_MSG_VOLTAGE_CHANGE_ERR RT_BIT(3) + +union rt_regulator_notifier_args +{ + struct + { + int old_uvolt; + int min_uvolt; + int max_uvolt; + }; +}; + +typedef rt_err_t (*rt_regulator_notifier_callback)(struct rt_regulator_notifier *notifier, + rt_ubase_t msg, void *data); + +struct rt_regulator_notifier +{ + rt_list_t list; + + struct rt_regulator *regulator; + rt_regulator_notifier_callback callback; + void *priv; +}; + +rt_err_t rt_regulator_register(struct rt_regulator_node *reg_np); +rt_err_t rt_regulator_unregister(struct rt_regulator_node *reg_np); + +rt_err_t rt_regulator_notifier_register(struct rt_regulator *reg, + struct rt_regulator_notifier *notifier); +rt_err_t rt_regulator_notifier_unregister(struct rt_regulator *reg, + struct rt_regulator_notifier *notifier); + +struct rt_regulator *rt_regulator_get(struct rt_device *dev, const char *id); +void rt_regulator_put(struct rt_regulator *reg); + +rt_err_t rt_regulator_enable(struct rt_regulator *reg); +rt_err_t rt_regulator_disable(struct rt_regulator *reg); +rt_bool_t rt_regulator_is_enabled(struct rt_regulator *reg); + +rt_bool_t rt_regulator_is_supported_voltage(struct rt_regulator *reg, int min_uvolt, int max_uvolt); +rt_err_t rt_regulator_set_voltage(struct rt_regulator *reg, int min_uvolt, int max_uvolt); +int rt_regulator_get_voltage(struct rt_regulator *reg); + +rt_err_t rt_regulator_set_mode(struct rt_regulator *reg, rt_uint32_t mode); +rt_int32_t rt_regulator_get_mode(struct rt_regulator *reg); + +rt_inline rt_err_t rt_regulator_set_voltage_triplet(struct rt_regulator *reg, + int min_uvolt, int target_uvolt, int max_uvolt) +{ + if (!rt_regulator_set_voltage(reg, target_uvolt, max_uvolt)) + { + return RT_EOK; + } + + return rt_regulator_set_voltage(reg, min_uvolt, max_uvolt); +} + +#endif /* __REGULATOR_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/reset.h b/rt-thread/components/drivers/include/drivers/reset.h new file mode 100644 index 0000000..6339fe9 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/reset.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-11-26 GuEe-GUI first version + */ + +#ifndef __RESET_H__ +#define __RESET_H__ + +#include +#include +#include + +#define RT_RESET_CONTROLLER_OBJ_NAME "RSTC" + +struct rt_reset_control_ops; + +struct rt_reset_controller +{ + struct rt_object parent; + + rt_list_t rstc_nodes; + + const char *name; + const struct rt_reset_control_ops *ops; + + struct rt_ofw_node *ofw_node; + void *priv; + + struct rt_spinlock spinlock; +}; + +struct rt_reset_control +{ + rt_list_t list; + + struct rt_reset_controller *rstcer; + + int id; + const char *con_id; + rt_bool_t is_array; + + void *priv; +}; + +struct rt_reset_control_ops +{ + /* + * rt_ofw_cell_args return: + * args[0] = rstc.id + */ + rt_err_t (*ofw_parse)(struct rt_reset_control *rstc, struct rt_ofw_cell_args *args); + /* API */ + rt_err_t (*reset)(struct rt_reset_control *rstc); + rt_err_t (*assert)(struct rt_reset_control *rstc); + rt_err_t (*deassert)(struct rt_reset_control *rstc); + int (*status)(struct rt_reset_control *rstc); +}; + +rt_err_t rt_reset_controller_register(struct rt_reset_controller *rstcer); +rt_err_t rt_reset_controller_unregister(struct rt_reset_controller *rstcer); + +rt_err_t rt_reset_control_reset(struct rt_reset_control *rstc); +rt_err_t rt_reset_control_assert(struct rt_reset_control *rstc); +rt_err_t rt_reset_control_deassert(struct rt_reset_control *rstc); +int rt_reset_control_status(struct rt_reset_control *rstc); + +rt_ssize_t rt_reset_control_get_count(struct rt_device *dev); +struct rt_reset_control *rt_reset_control_get_array(struct rt_device *dev); +struct rt_reset_control *rt_reset_control_get_by_index(struct rt_device *dev, int index); +struct rt_reset_control *rt_reset_control_get_by_name(struct rt_device *dev, const char *name); +void rt_reset_control_put(struct rt_reset_control *rstc); + +struct rt_reset_control *rt_ofw_get_reset_control_array(struct rt_ofw_node *np); +struct rt_reset_control *rt_ofw_get_reset_control_by_index(struct rt_ofw_node *np, int index); +struct rt_reset_control *rt_ofw_get_reset_control_by_name(struct rt_ofw_node *np, const char *name); + +#endif /* __RESET_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/rt_drv_pwm.h b/rt-thread/components/drivers/include/drivers/rt_drv_pwm.h deleted file mode 100644 index e9e1707..0000000 --- a/rt-thread/components/drivers/include/drivers/rt_drv_pwm.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-05-07 aozima the first version - * 2022-09-24 yuqi add phase and dead time configuration - */ - -#ifndef __DRV_PWM_H_INCLUDE__ -#define __DRV_PWM_H_INCLUDE__ - -#include - -#define PWM_CMD_ENABLE (RT_DEVICE_CTRL_BASE(PWM) + 0) -#define PWM_CMD_DISABLE (RT_DEVICE_CTRL_BASE(PWM) + 1) -#define PWM_CMD_SET (RT_DEVICE_CTRL_BASE(PWM) + 2) -#define PWM_CMD_GET (RT_DEVICE_CTRL_BASE(PWM) + 3) -#define PWMN_CMD_ENABLE (RT_DEVICE_CTRL_BASE(PWM) + 4) -#define PWMN_CMD_DISABLE (RT_DEVICE_CTRL_BASE(PWM) + 5) -#define PWM_CMD_SET_PERIOD (RT_DEVICE_CTRL_BASE(PWM) + 6) -#define PWM_CMD_SET_PULSE (RT_DEVICE_CTRL_BASE(PWM) + 7) -#define PWM_CMD_SET_DEAD_TIME (RT_DEVICE_CTRL_BASE(PWM) + 8) -#define PWM_CMD_SET_PHASE (RT_DEVICE_CTRL_BASE(PWM) + 9) -#define PWM_CMD_ENABLE_IRQ (RT_DEVICE_CTRL_BASE(PWM) + 10) -#define PWM_CMD_DISABLE_IRQ (RT_DEVICE_CTRL_BASE(PWM) + 11) - -struct rt_pwm_configuration -{ - rt_uint32_t channel; /* 0 ~ n or 0 ~ -n, which depends on specific MCU requirements */ - rt_uint32_t period; /* unit:ns 1ns~4.29s:1Ghz~0.23hz */ - rt_uint32_t pulse; /* unit:ns (pulse<=period) */ - rt_uint32_t dead_time; /* unit:ns */ - rt_uint32_t phase; /*unit: degree, 0~360, which is the phase of pwm output, */ - /* - * RT_TRUE : The channel of pwm is complememtary. - * RT_FALSE : The channel of pwm is nomal. - */ - rt_bool_t complementary; -}; - -struct rt_device_pwm; -struct rt_pwm_ops -{ - rt_err_t (*control)(struct rt_device_pwm *device, int cmd, void *arg); -}; - -struct rt_device_pwm -{ - struct rt_device parent; - const struct rt_pwm_ops *ops; -}; - -rt_err_t rt_device_pwm_register(struct rt_device_pwm *device, const char *name, const struct rt_pwm_ops *ops, const void *user_data); - -rt_err_t rt_pwm_enable(struct rt_device_pwm *device, int channel); -rt_err_t rt_pwm_disable(struct rt_device_pwm *device, int channel); -rt_err_t rt_pwm_set(struct rt_device_pwm *device, int channel, rt_uint32_t period, rt_uint32_t pulse); -rt_err_t rt_pwm_set_period(struct rt_device_pwm *device, int channel, rt_uint32_t period); -rt_err_t rt_pwm_set_pulse(struct rt_device_pwm *device, int channel, rt_uint32_t pulse); -rt_err_t rt_pwm_set_dead_time(struct rt_device_pwm *device, int channel, rt_uint32_t dead_time); -rt_err_t rt_pwm_set_phase(struct rt_device_pwm *device, int channel, rt_uint32_t phase); - -#endif /* __DRV_PWM_H_INCLUDE__ */ diff --git a/rt-thread/components/drivers/include/drivers/scsi.h b/rt-thread/components/drivers/include/drivers/scsi.h new file mode 100644 index 0000000..7b6baaf --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/scsi.h @@ -0,0 +1,461 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#ifndef __SCSI_H__ +#define __SCSI_H__ + +#include +#include +#include + +#define RT_SCSI_LUN_SHIFT 5 + +rt_packed(struct rt_scsi_unknow +{ + rt_uint8_t opcode; +}); + +rt_packed(struct rt_scsi_test_unit_ready +{ + rt_uint8_t opcode; + rt_uint8_t reserved[4]; + rt_uint8_t control; + rt_uint8_t pad[6]; /* To be ATAPI compatible */ +}); + +rt_packed(struct rt_scsi_inquiry +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-2 Reserved, 1 Obsolete Formerly CMDDT, 0 EVPD */ + rt_uint8_t page; /* Page code if EVPD=1 */ + rt_uint8_t reserved; + rt_uint8_t alloc_length; + rt_uint8_t control; + rt_uint8_t pad[6]; /* To be ATAPI compatible */ +}); + +rt_packed(struct rt_scsi_inquiry_data +{ +#define RT_SCSI_DEVTYPE_MASK 31 + rt_uint8_t devtype; +#define RT_SCSI_REMOVABLE_BIT 7 + rt_uint8_t rmb; + rt_uint8_t reserved[2]; + rt_uint8_t length; + rt_uint8_t reserved1[3]; + char vendor[8]; + char prodid[16]; + char prodrev[4]; +}); + +rt_packed(struct rt_scsi_request_sense +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-2 Reserved, 1 Obsolete, 0 SP */ + rt_uint8_t reserved[2]; + rt_uint8_t alloc_length; + rt_uint8_t control; + rt_uint8_t pad[6]; /* To be ATAPI compatible */ +}); + +rt_packed(struct rt_scsi_request_sense_data +{ + rt_uint8_t error_code; /* 7 Valid, 6-0 Err. code */ + rt_uint8_t segment_number; + rt_uint8_t sense_key; /* 7 FileMark, 6 EndOfMedia, 5 ILI, 4-0 sense key */ + rt_be32_t information; + rt_uint8_t additional_sense_length; + rt_be32_t cmd_specific_info; + rt_uint8_t additional_sense_code; + rt_uint8_t additional_sense_code_qualifier; + rt_uint8_t field_replaceable_unit_code; + rt_uint8_t sense_key_specific[3]; +}); + +rt_packed(struct rt_scsi_read_capacity10 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-1 Reserved, 0 Obsolete */ + rt_be32_t logical_block_addr; /* only if PMI=1 */ + rt_uint8_t reserved[2]; + rt_uint8_t pmi; + rt_uint8_t control; + rt_be16_t pad; /* To be ATAPI compatible */ +}); + +rt_packed(struct rt_scsi_read_capacity10_data +{ + rt_be32_t last_block; + rt_be32_t block_size; +}); + +rt_packed(struct rt_scsi_read_capacity16 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-5 Reserved, 4-0 SERVICE ACTION 0x10 */ + rt_be64_t logical_block_addr; /* only if PMI=1 */ + rt_be32_t alloc_len; + rt_uint8_t pmi; + rt_uint8_t control; +}); + +rt_packed(struct rt_scsi_read_capacity16_data +{ + rt_be64_t last_block; + rt_be32_t block_size; + rt_uint8_t pad[20]; +}); + +rt_packed(struct rt_scsi_read10 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-5 RDPROTECT, 4 DPO, 3 FUA, 2 RARC, 1 Obsolete, 0 Obsolete */ + rt_be32_t lba; + rt_uint8_t reserved; + rt_be16_t size; + rt_uint8_t reserved2; + rt_be16_t pad; +}); + +rt_packed(struct rt_scsi_read12 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-5 RDPROTECT, 4 DPO, 3 FUA, 2 RARC, 1 Obsolete, 0 Obsolete */ + rt_be32_t lba; + rt_be32_t size; + rt_uint8_t reserved; + rt_uint8_t control; +}); + +rt_packed(struct rt_scsi_read16 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-5 RDPROTECT, 4 DPO, 3 FUA, 2 RARC, 1 Obsolete, 0 DLD2 */ + rt_be64_t lba; + rt_be32_t size; + rt_uint8_t reserved; + rt_uint8_t control; +}); + +rt_packed(struct rt_scsi_write10 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-5 WRPROTECT, 4 DPO, 3 FUA, 2 Reserved, 1 Obsolete, 0 Obsolete */ + rt_be32_t lba; + rt_uint8_t reserved; + rt_be16_t size; + rt_uint8_t reserved2; + rt_be16_t pad; +}); + +rt_packed(struct rt_scsi_write12 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-5 WRPROTECT, 4 DPO, 3 FUA, 2 Reserved, 1 Obsolete, 0 Obsolete */ + rt_be32_t lba; + rt_be32_t size; + rt_uint8_t reserved; + rt_uint8_t control; +}); + +rt_packed(struct rt_scsi_write16 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-5 WRPROTECT, 4 DPO, 3 FUA, 2 Reserved, 1 Obsolete, 0 DLD2 */ + rt_be64_t lba; + rt_be32_t size; + rt_uint8_t reserved; + rt_uint8_t control; +}); + +rt_packed(struct rt_scsi_synchronize_cache10 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-3 Reserved, 2 Obsolete, 1 IMMED, 0 Obsolete */ + rt_be32_t lba; + rt_uint8_t reserved; + rt_be16_t size; + rt_uint8_t control; +}); + +rt_packed(struct rt_scsi_synchronize_cache16 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-3 Reserved, 2 Obsolete, 1 IMMED, 0 Obsolete */ + rt_be64_t lba; + rt_be32_t size; + rt_uint8_t reserved; + rt_uint8_t control; +}); + +#define RT_SCSI_UNMAP_SHIFT 3 + +rt_packed(struct rt_scsi_write_same10 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-5 WRPROTECT, 4 ANCHOR, 3 UNMAP, 2 Obsolete, 1 Obsolete, 0 Obsolete */ + rt_be32_t lba; + rt_uint8_t reserved; + rt_be16_t size; + rt_uint8_t control; +}); + +rt_packed(struct rt_scsi_write_same16 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-5 WRPROTECT, 4 ANCHOR, 3 UNMAP, 2 Obsolete, 1 Obsolete, 0 NDOB */ + rt_be64_t lba; + rt_be32_t size; + rt_uint8_t reserved; + rt_uint8_t control; +}); + +#define RT_SCSI_PF_SHIFT 4 +#define RT_SCSI_RTD_SHIFT 1 +#define RT_SCSI_SP_SHIFT 0 + +rt_packed(struct rt_scsi_mode_select6 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-5 Reserved, 4 PF, 3-2 Reserved, 1 RTD, 0 SP */ + rt_uint8_t reserved[2]; + rt_uint8_t param_list_len; + rt_uint8_t control; +}); + +rt_packed(struct rt_scsi_mode_select10 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-5 Reserved, 4 PF, 3-1 Reserved, 0 SP */ + rt_uint8_t reserved[5]; + rt_be16_t param_list_len; + rt_uint8_t control; +}); + +struct rt_scsi_mode_select_data +{ + rt_uint32_t length; + rt_uint16_t block_descriptor_length; + rt_uint8_t medium_type; + rt_uint8_t device_specific; + rt_uint8_t header_length; + rt_uint8_t longlba:1; +}; + +#define RT_SCSI_DBD_SHIFT 3 +#define RT_SCSI_LLBAA_SHIFT 4 +#define RT_SCSI_PC_SHIFT 6 +#define RT_SCSI_PAGE_CODE_SHIFT 0 + +rt_packed(struct rt_scsi_mode_sense6 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-4 Reserved, 3 DBD, 2-0 Reserved */ + rt_uint8_t page_control_code; + rt_uint8_t subpage_code; + rt_uint8_t allocation_len; + rt_uint8_t control; +}); + +rt_packed(struct rt_scsi_mode_sense10 +{ + rt_uint8_t opcode; + rt_uint8_t config; /* 7-5 Reserved, 4 LLBAA, 3 DBD, 2-0 Reserved */ + rt_uint8_t page_control_code; + rt_uint8_t subpage_code; + rt_uint8_t reserved[3]; + rt_be16_t allocation_len; + rt_uint8_t control; +}); + +#define RT_SCSI_CMD_TEST_UNIT_READY 0x00 +#define RT_SCSI_CMD_REQUEST_SENSE 0x03 +#define RT_SCSI_CMD_INQUIRY 0x12 +#define RT_SCSI_CMD_MODE_SELECT 0x15 +#define RT_SCSI_CMD_MODE_SENSE 0x1a +#define RT_SCSI_CMD_READ_CAPACITY10 0x25 +#define RT_SCSI_CMD_READ10 0x28 +#define RT_SCSI_CMD_WRITE10 0x2a +#define RT_SCSI_CMD_SYNCHRONIZE_CACHE10 0x35 +#define RT_SCSI_CMD_WRITE_SAME10 0x41 +#define RT_SCSI_CMD_MODE_SELECT10 0x55 +#define RT_SCSI_CMD_MODE_SENSE10 0x5a +#define RT_SCSI_CMD_READ16 0x88 +#define RT_SCSI_CMD_WRITE16 0x8a +#define RT_SCSI_CMD_SYNCHRONIZE_CACHE16 0x91 +#define RT_SCSI_CMD_WRITE_SAME16 0x93 +#define RT_SCSI_CMD_READ_CAPACITY16 0x9e +#define RT_SCSI_CMD_READ12 0xa8 +#define RT_SCSI_CMD_WRITE12 0xaa + +struct rt_scsi_cmd +{ + union + { + struct rt_scsi_unknow unknow; + struct rt_scsi_test_unit_ready test_unit_ready; + struct rt_scsi_inquiry inquiry; + struct rt_scsi_request_sense request_sense; + struct rt_scsi_read_capacity10 read_capacity10; + struct rt_scsi_read_capacity16 read_capacity16; + struct rt_scsi_read10 read10; + struct rt_scsi_read12 read12; + struct rt_scsi_read16 read16; + struct rt_scsi_write10 write10; + struct rt_scsi_write12 write12; + struct rt_scsi_write16 write16; + struct rt_scsi_synchronize_cache10 synchronize_cache10; + struct rt_scsi_synchronize_cache16 synchronize_cache16; + struct rt_scsi_write_same10 write_same10; + struct rt_scsi_write_same16 write_same16; + struct rt_scsi_mode_select6 mode_select6; + struct rt_scsi_mode_select10 mode_select10; + struct rt_scsi_mode_sense6 mode_sense6; + struct rt_scsi_mode_sense10 mode_sense10; + } op; + rt_size_t op_size; + + union + { + struct + { + struct rt_scsi_inquiry_data inquiry; + struct rt_scsi_request_sense_data request_sense; + struct rt_scsi_read_capacity10_data read_capacity10; + struct rt_scsi_read_capacity16_data read_capacity16; + }; + struct + { + void *ptr; + rt_size_t size; + }; + } data; +}; + +enum +{ + SCSI_DEVICE_TYPE_DIRECT = 0x00, /* DiskPeripheral (GenDisk) */ + SCSI_DEVICE_TYPE_SEQUENTIAL = 0x01, /* TapePeripheral */ + SCSI_DEVICE_TYPE_PRINTER = 0x02, /* PrinterPeripheral (GenPrinter) */ + SCSI_DEVICE_TYPE_PROCESSOR = 0x03, /* OtherPeripheral */ + SCSI_DEVICE_TYPE_WRITE_ONCE_READ_MULTIPLE = 0x04, /* WormPeripheral (GenWorm) */ + SCSI_DEVICE_TYPE_CDROM = 0x05, /* CdRomPeripheral (GenCdRom) */ + SCSI_DEVICE_TYPE_SCANNER = 0x06, /* ScannerPeripheral (GenScanner) */ + SCSI_DEVICE_TYPE_OPTICAL = 0x07, /* OpticalDiskPeripheral (GenOptical) */ + SCSI_DEVICE_TYPE_MEDIUM_CHANGER = 0x08, /* MediumChangerPeripheral (ScsiChanger) */ + SCSI_DEVICE_TYPE_COMMUNICATION = 0x09, /* CommunicationsPeripheral (ScsiNet) */ + SCSI_DEVICE_TYPE_ASC_PREPRESS_GRAPHICS10 = 0x0a, /* ASCPrePressGraphicsPeripheral (ScsiASCIT8) */ + SCSI_DEVICE_TYPE_ASC_PREPRESS_GRAPHICS11 = 0x0b, /* ASCPrePressGraphicsPeripheral (ScsiASCIT8) */ + SCSI_DEVICE_TYPE_ARRAY = 0x0c, /* ArrayPeripheral (ScsiArray) */ + SCSI_DEVICE_TYPE_ENCLOSURE = 0x0d, /* EnclosurePeripheral (ScsiEnclosure) */ + SCSI_DEVICE_TYPE_RBC = 0x0e, /* RBCPeripheral (ScsiRBC) */ + SCSI_DEVICE_TYPE_CARDREADER = 0x0f, /* CardReaderPeripheral (ScsiCardReader) */ + SCSI_DEVICE_TYPE_BRIDGE = 0x10, /* BridgePeripheral (ScsiBridge) */ + SCSI_DEVICE_TYPE_OTHER = 0x11, /* OtherPeripheral (ScsiOther) */ + SCSI_DEVICE_TYPE_MAX, +}; + +struct rt_scsi_ops; + +struct rt_scsi_host +{ + struct rt_device *dev; + + const struct rt_scsi_ops *ops; + + rt_size_t max_id; + rt_size_t max_lun; + + rt_list_t lun_nodes; +}; + +struct rt_scsi_device +{ + struct rt_scsi_host *host; + + rt_list_t list; + + rt_size_t id; + rt_size_t lun; + rt_uint32_t devtype; + rt_uint32_t removable; + rt_size_t last_block; + rt_size_t block_size; + + void *priv; +}; + +struct rt_scsi_ops +{ + rt_err_t (*reset)(struct rt_scsi_device *sdev); + rt_err_t (*transfer)(struct rt_scsi_device *sdev, struct rt_scsi_cmd *cmd); +}; + +rt_err_t rt_scsi_host_register(struct rt_scsi_host *scsi); +rt_err_t rt_scsi_host_unregister(struct rt_scsi_host *scsi); + +rt_inline rt_bool_t rt_scsi_cmd_is_write(struct rt_scsi_cmd *cmd) +{ + return cmd->op.write10.opcode == RT_SCSI_CMD_WRITE10 || + cmd->op.write12.opcode == RT_SCSI_CMD_WRITE16 || + cmd->op.write16.opcode == RT_SCSI_CMD_WRITE12; +} + +rt_err_t rt_scsi_request_sense(struct rt_scsi_device *sdev, + struct rt_scsi_request_sense_data *out_data); + +rt_err_t rt_scsi_test_unit_ready(struct rt_scsi_device *sdev); +rt_err_t rt_scsi_inquiry(struct rt_scsi_device *sdev, + struct rt_scsi_inquiry_data *out_data); + +rt_err_t rt_scsi_read_capacity10(struct rt_scsi_device *sdev, + struct rt_scsi_read_capacity10_data *out_data); +rt_err_t rt_scsi_read_capacity16(struct rt_scsi_device *sdev, + struct rt_scsi_read_capacity16_data *out_data); + +rt_err_t rt_scsi_read10(struct rt_scsi_device *sdev, + rt_off_t lba, void *buffer, rt_size_t size); +rt_err_t rt_scsi_read12(struct rt_scsi_device *sdev, + rt_off_t lba, void *buffer, rt_size_t size); +rt_err_t rt_scsi_read16(struct rt_scsi_device *sdev, + rt_off_t lba, void *buffer, rt_size_t size); + +rt_err_t rt_scsi_write10(struct rt_scsi_device *sdev, + rt_off_t lba, const void *buffer, rt_size_t size); +rt_err_t rt_scsi_write12(struct rt_scsi_device *sdev, + rt_off_t lba, const void *buffer, rt_size_t size); +rt_err_t rt_scsi_write16(struct rt_scsi_device *sdev, + rt_off_t lba, const void *buffer, rt_size_t size); + +rt_err_t rt_scsi_synchronize_cache10(struct rt_scsi_device *sdev, + rt_off_t lba, rt_size_t size); +rt_err_t rt_scsi_synchronize_cache16(struct rt_scsi_device *sdev, + rt_off_t lba, rt_size_t size); + +rt_err_t rt_scsi_write_same10(struct rt_scsi_device *sdev, + rt_off_t lba, rt_size_t size); +rt_err_t rt_scsi_write_same16(struct rt_scsi_device *sdev, + rt_off_t lba, rt_size_t size); + +rt_err_t rt_scsi_mode_select6(struct rt_scsi_device *sdev, + rt_uint8_t pf, rt_uint8_t sp, void *buffer, rt_size_t size, + struct rt_scsi_mode_select_data *data); +rt_err_t rt_scsi_mode_select10(struct rt_scsi_device *sdev, + rt_uint8_t pf, rt_uint8_t sp, void *buffer, rt_size_t size, + struct rt_scsi_mode_select_data *data); + +rt_err_t rt_scsi_mode_sense6(struct rt_scsi_device *sdev, + rt_uint8_t dbd, rt_uint8_t modepage, rt_uint8_t subpage, void *buffer, rt_size_t size, + struct rt_scsi_mode_select_data *data); +rt_err_t rt_scsi_mode_sense10(struct rt_scsi_device *sdev, + rt_uint8_t dbd, rt_uint8_t modepage, rt_uint8_t subpage, void *buffer, rt_size_t size, + struct rt_scsi_mode_select_data *data); + +#endif /* __SCSI_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/sensor.h b/rt-thread/components/drivers/include/drivers/sensor.h index 6c8b78e..ca1c84e 100644 --- a/rt-thread/components/drivers/include/drivers/sensor.h +++ b/rt-thread/components/drivers/include/drivers/sensor.h @@ -12,7 +12,7 @@ #define __SENSOR_H__ #include -#include "pin.h" +#include "dev_pin.h" #ifdef __cplusplus extern "C" { @@ -53,6 +53,9 @@ extern "C" { #define RT_SENSOR_CLASS_IAQ (19) /* IAQ sensor. */ #define RT_SENSOR_CLASS_ETOH (20) /* EtOH sensor. */ #define RT_SENSOR_CLASS_BP (21) /* Blood Pressure */ +#define RT_SENSOR_CLASS_VOLTAGE (22) /* Voltage sensor */ +#define RT_SENSOR_CLASS_CURRENT (23) /* Current sensor */ +#define RT_SENSOR_CLASS_POWER (24) /* Power sensor */ /* Sensor vendor types */ @@ -95,6 +98,9 @@ extern "C" { #define RT_SENSOR_UNIT_DD (17) /* Coordinates unit: DD */ #define RT_SENSOR_UNIT_MGM3 (18) /* Concentration unit: mg/m3 */ #define RT_SENSOR_UNIT_MMHG (19) /* Blood Pressure unit: mmHg */ +#define RT_SENSOR_UNIT_MV (20) /* Voltage unit: mV */ +#define RT_SENSOR_UNIT_MA (21) /* Current unit: mA */ +#define RT_SENSOR_UNIT_MW (22) /* Power unit: mW */ /* Sensor communication interface types */ #define RT_SENSOR_INTF_I2C (1 << 0) @@ -230,9 +236,12 @@ struct rt_sensor_data rt_uint32_t dust; /* Dust sensor. unit: ug/m3 */ rt_uint32_t eco2; /* eCO2 sensor. unit: ppm */ rt_uint32_t spo2; /* SpO2 sensor. unit: permillage */ - rt_uint32_t iaq; /* IAQ sensor. unit: 1 */ - rt_uint32_t etoh; /* EtOH sensor. unit: ppm */ + rt_uint32_t iaq; /* IAQ sensor. unit: 1 */ + rt_uint32_t etoh; /* EtOH sensor. unit: ppm */ struct sensor_bp bp; /* BloodPressure. unit: mmHg */ + float mv; /* Voltage sensor. unit: mv */ + float ma; /* Current sensor. unit: ma */ + float mw; /* Power sensor. unit: mw */ } data; }; diff --git a/rt-thread/components/drivers/include/drivers/sensor_v2.h b/rt-thread/components/drivers/include/drivers/sensor_v2.h index d90cef8..3cb00ca 100644 --- a/rt-thread/components/drivers/include/drivers/sensor_v2.h +++ b/rt-thread/components/drivers/include/drivers/sensor_v2.h @@ -13,7 +13,7 @@ #define __SENSOR_H__ #include -#include "pin.h" +#include "dev_pin.h" #ifdef __cplusplus extern "C" { diff --git a/rt-thread/components/drivers/include/drivers/serial_bypass.h b/rt-thread/components/drivers/include/drivers/serial_bypass.h new file mode 100644 index 0000000..890c894 --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/serial_bypass.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-11-20 zhujiale the first version + */ + +#ifndef __RTT_BYPASS_H__ +#define __RTT_BYPASS_H__ +#include +#include +#include +typedef rt_err_t(*bypass_function_t)(struct rt_serial_device* serial, char buf, void* data); + +#define RT_BYPASS_LEVEL_MAX 4 +#define RT_BYPASS_LEVEL_1 0 +#define RT_BYPASS_LEVEL_2 1 +#define RT_BYPASS_LEVEL_3 2 +#define RT_BYPASS_LEVEL_4 3 +#define RT_BYPASS_MAX_LEVEL 4 + +/*The protect level can be register but can not be unregister we should use it carefully*/ +#define RT_BYPASS_PROTECT_LEVEL_1 10 +#define RT_BYPASS_PROTECT_LEVEL_2 11 +#define RT_BYPASS_PROTECT_LEVEL_3 12 +#define RT_BYPASS_PROTECT_LEVEL_4 13 + +struct rt_serial_bypass_func { + /*The function pointer of the bypassed data processing*/ + bypass_function_t bypass; + /*The smaller the array of levels, the higher the priority of execution*/ + rt_uint8_t level; + rt_list_t node; + char name[RT_NAME_MAX]; + void* data; +}; + +struct rt_serial_bypass_head +{ + rt_list_t head; + struct rt_spinlock spinlock; +}; + +struct rt_serial_bypass { + struct rt_work work; + + struct rt_spinlock spinlock; + struct rt_workqueue* lower_workq; + struct rt_serial_bypass_head* upper_h; + struct rt_serial_bypass_head* lower_h; + rt_mutex_t mutex; + struct rt_ringbuffer* pipe; +}; + +int serial_bypass_list(int argc, char** argv); + +void rt_bypass_work_straight(struct rt_serial_device* serial); +void rt_bypass_putchar(struct rt_serial_device* serial, rt_uint8_t ch); +rt_size_t rt_bypass_getchar(struct rt_serial_device* serial, rt_uint8_t* ch); + +rt_err_t rt_bypass_upper_unregister(struct rt_serial_device* serial, rt_uint8_t level); +rt_err_t rt_bypass_lower_unregister(struct rt_serial_device* serial, rt_uint8_t level); + +rt_err_t rt_bypass_upper_register(struct rt_serial_device* serial, const char* name, rt_uint8_t level, bypass_function_t func, void* data); +rt_err_t rt_bypass_lower_register(struct rt_serial_device* serial, const char* name, rt_uint8_t level, bypass_function_t func, void* data); +#endif diff --git a/rt-thread/components/drivers/include/drivers/spi.h b/rt-thread/components/drivers/include/drivers/spi.h deleted file mode 100644 index b35c7b3..0000000 --- a/rt-thread/components/drivers/include/drivers/spi.h +++ /dev/null @@ -1,373 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-11-23 Bernard Add extern "C" - * 2020-06-13 armink fix the 3 wires issue - * 2022-09-01 liYony fix api rt_spi_sendrecv16 about MSB and LSB bug - */ - -#ifndef __SPI_H__ -#define __SPI_H__ - -#include -#include -#include - -#ifdef __cplusplus -extern "C"{ -#endif - -/** - * At CPOL=0 the base value of the clock is zero - * - For CPHA=0, data are captured on the clock's rising edge (low->high transition) - * and data are propagated on a falling edge (high->low clock transition). - * - For CPHA=1, data are captured on the clock's falling edge and data are - * propagated on a rising edge. - * At CPOL=1 the base value of the clock is one (inversion of CPOL=0) - * - For CPHA=0, data are captured on clock's falling edge and data are propagated - * on a rising edge. - * - For CPHA=1, data are captured on clock's rising edge and data are propagated - * on a falling edge. - */ -#define RT_SPI_CPHA (1<<0) /* bit[0]:CPHA, clock phase */ -#define RT_SPI_CPOL (1<<1) /* bit[1]:CPOL, clock polarity */ - -#define RT_SPI_LSB (0<<2) /* bit[2]: 0-LSB */ -#define RT_SPI_MSB (1<<2) /* bit[2]: 1-MSB */ - -#define RT_SPI_MASTER (0<<3) /* SPI master device */ -#define RT_SPI_SLAVE (1<<3) /* SPI slave device */ - -#define RT_SPI_CS_HIGH (1<<4) /* Chipselect active high */ -#define RT_SPI_NO_CS (1<<5) /* No chipselect */ -#define RT_SPI_3WIRE (1<<6) /* SI/SO pin shared */ -#define RT_SPI_READY (1<<7) /* Slave pulls low to pause */ - -#define RT_SPI_MODE_MASK (RT_SPI_CPHA | RT_SPI_CPOL | RT_SPI_MSB | RT_SPI_SLAVE | RT_SPI_CS_HIGH | RT_SPI_NO_CS | RT_SPI_3WIRE | RT_SPI_READY) - -#define RT_SPI_MODE_0 (0 | 0) /* CPOL = 0, CPHA = 0 */ -#define RT_SPI_MODE_1 (0 | RT_SPI_CPHA) /* CPOL = 0, CPHA = 1 */ -#define RT_SPI_MODE_2 (RT_SPI_CPOL | 0) /* CPOL = 1, CPHA = 0 */ -#define RT_SPI_MODE_3 (RT_SPI_CPOL | RT_SPI_CPHA) /* CPOL = 1, CPHA = 1 */ - -#define RT_SPI_BUS_MODE_SPI (1<<0) -#define RT_SPI_BUS_MODE_QSPI (1<<1) - -/** - * SPI message structure - */ -struct rt_spi_message -{ - const void *send_buf; - void *recv_buf; - rt_size_t length; - struct rt_spi_message *next; - - unsigned cs_take : 1; - unsigned cs_release : 1; -}; - -/** - * SPI configuration structure - */ -struct rt_spi_configuration -{ - rt_uint8_t mode; - rt_uint8_t data_width; - rt_uint16_t reserved; - - rt_uint32_t max_hz; -}; - -struct rt_spi_ops; -struct rt_spi_bus -{ - struct rt_device parent; - rt_uint8_t mode; - const struct rt_spi_ops *ops; - - struct rt_mutex lock; - struct rt_spi_device *owner; -}; - -/** - * SPI operators - */ -struct rt_spi_ops -{ - rt_err_t (*configure)(struct rt_spi_device *device, struct rt_spi_configuration *configuration); - rt_ssize_t (*xfer)(struct rt_spi_device *device, struct rt_spi_message *message); -}; - -/** - * SPI Virtual BUS, one device must connected to a virtual BUS - */ -struct rt_spi_device -{ - struct rt_device parent; - struct rt_spi_bus *bus; - - struct rt_spi_configuration config; - rt_base_t cs_pin; - void *user_data; -}; - -struct rt_qspi_message -{ - struct rt_spi_message parent; - - /* instruction stage */ - struct - { - rt_uint8_t content; - rt_uint8_t qspi_lines; - } instruction; - - /* address and alternate_bytes stage */ - struct - { - rt_uint32_t content; - rt_uint8_t size; - rt_uint8_t qspi_lines; - } address, alternate_bytes; - - /* dummy_cycles stage */ - rt_uint32_t dummy_cycles; - - /* number of lines in qspi data stage, the other configuration items are in parent */ - rt_uint8_t qspi_data_lines; -}; - -struct rt_qspi_configuration -{ - struct rt_spi_configuration parent; - /* The size of medium */ - rt_uint32_t medium_size; - /* double data rate mode */ - rt_uint8_t ddr_mode; - /* the data lines max width which QSPI bus supported, such as 1, 2, 4 */ - rt_uint8_t qspi_dl_width ; -}; - -struct rt_qspi_device -{ - struct rt_spi_device parent; - - struct rt_qspi_configuration config; - - void (*enter_qspi_mode)(struct rt_qspi_device *device); - - void (*exit_qspi_mode)(struct rt_qspi_device *device); -}; - -#define SPI_DEVICE(dev) ((struct rt_spi_device *)(dev)) - -/* register a SPI bus */ -rt_err_t rt_spi_bus_register(struct rt_spi_bus *bus, - const char *name, - const struct rt_spi_ops *ops); - -/* attach a device on SPI bus */ -rt_err_t rt_spi_bus_attach_device(struct rt_spi_device *device, - const char *name, - const char *bus_name, - void *user_data); - -/* attach a device on SPI bus with CS pin */ -rt_err_t rt_spi_bus_attach_device_cspin(struct rt_spi_device *device, - const char *name, - const char *bus_name, - rt_base_t cs_pin, - void *user_data); - -/* re-configure SPI bus */ -rt_err_t rt_spi_bus_configure(struct rt_spi_device *device); - -/** - * This function takes SPI bus. - * - * @param device the SPI device attached to SPI bus - * - * @return RT_EOK on taken SPI bus successfully. others on taken SPI bus failed. - */ -rt_err_t rt_spi_take_bus(struct rt_spi_device *device); - -/** - * This function releases SPI bus. - * - * @param device the SPI device attached to SPI bus - * - * @return RT_EOK on release SPI bus successfully. - */ -rt_err_t rt_spi_release_bus(struct rt_spi_device *device); - -/** - * This function take SPI device (takes CS of SPI device). - * - * @param device the SPI device attached to SPI bus - * - * @return RT_EOK on release SPI bus successfully. others on taken SPI bus failed. - */ -rt_err_t rt_spi_take(struct rt_spi_device *device); - -/** - * This function releases SPI device (releases CS of SPI device). - * - * @param device the SPI device attached to SPI bus - * - * @return RT_EOK on release SPI device successfully. - */ -rt_err_t rt_spi_release(struct rt_spi_device *device); - -/* set configuration on SPI device */ -rt_err_t rt_spi_configure(struct rt_spi_device *device, - struct rt_spi_configuration *cfg); - -/* send data then receive data from SPI device */ -rt_err_t rt_spi_send_then_recv(struct rt_spi_device *device, - const void *send_buf, - rt_size_t send_length, - void *recv_buf, - rt_size_t recv_length); - -rt_err_t rt_spi_send_then_send(struct rt_spi_device *device, - const void *send_buf1, - rt_size_t send_length1, - const void *send_buf2, - rt_size_t send_length2); - -/** - * This function transmits data to SPI device. - * - * @param device the SPI device attached to SPI bus - * @param send_buf the buffer to be transmitted to SPI device. - * @param recv_buf the buffer to save received data from SPI device. - * @param length the length of transmitted data. - * - * @return the actual length of transmitted. - */ -rt_ssize_t rt_spi_transfer(struct rt_spi_device *device, - const void *send_buf, - void *recv_buf, - rt_size_t length); - -rt_err_t rt_spi_sendrecv8(struct rt_spi_device *device, - rt_uint8_t senddata, - rt_uint8_t *recvdata); - -rt_err_t rt_spi_sendrecv16(struct rt_spi_device *device, - rt_uint16_t senddata, - rt_uint16_t *recvdata); - -/** - * This function transfers a message list to the SPI device. - * - * @param device the SPI device attached to SPI bus - * @param message the message list to be transmitted to SPI device - * - * @return RT_NULL if transmits message list successfully, - * SPI message which be transmitted failed. - */ -struct rt_spi_message *rt_spi_transfer_message(struct rt_spi_device *device, - struct rt_spi_message *message); - -rt_inline rt_size_t rt_spi_recv(struct rt_spi_device *device, - void *recv_buf, - rt_size_t length) -{ - return rt_spi_transfer(device, RT_NULL, recv_buf, length); -} - -rt_inline rt_size_t rt_spi_send(struct rt_spi_device *device, - const void *send_buf, - rt_size_t length) -{ - return rt_spi_transfer(device, send_buf, RT_NULL, length); -} - -/** - * This function appends a message to the SPI message list. - * - * @param list the SPI message list header. - * @param message the message pointer to be appended to the message list. - */ -rt_inline void rt_spi_message_append(struct rt_spi_message *list, - struct rt_spi_message *message) -{ - RT_ASSERT(list != RT_NULL); - if (message == RT_NULL) - return; /* not append */ - - while (list->next != RT_NULL) - { - list = list->next; - } - - list->next = message; - message->next = RT_NULL; -} - -/** - * This function can set configuration on QSPI device. - * - * @param device the QSPI device attached to QSPI bus. - * @param cfg the configuration pointer. - * - * @return the actual length of transmitted. - */ -rt_err_t rt_qspi_configure(struct rt_qspi_device *device, struct rt_qspi_configuration *cfg); - -/** - * This function can register a SPI bus for QSPI mode. - * - * @param bus the SPI bus for QSPI mode. - * @param name The name of the spi bus. - * @param ops the SPI bus instance to be registered. - * - * @return the actual length of transmitted. - */ -rt_err_t rt_qspi_bus_register(struct rt_spi_bus *bus, const char *name, const struct rt_spi_ops *ops); - -/** - * This function transmits data to QSPI device. - * - * @param device the QSPI device attached to QSPI bus. - * @param message the message pointer. - * - * @return the actual length of transmitted. - */ -rt_size_t rt_qspi_transfer_message(struct rt_qspi_device *device, struct rt_qspi_message *message); - -/** - * This function can send data then receive data from QSPI device - * - * @param device the QSPI device attached to QSPI bus. - * @param send_buf the buffer to be transmitted to QSPI device. - * @param send_length the number of data to be transmitted. - * @param recv_buf the buffer to be recivied from QSPI device. - * @param recv_length the data to be recivied. - * - * @return the status of transmit. - */ -rt_err_t rt_qspi_send_then_recv(struct rt_qspi_device *device, const void *send_buf, rt_size_t send_length,void *recv_buf, rt_size_t recv_length); - -/** - * This function can send data to QSPI device - * - * @param device the QSPI device attached to QSPI bus. - * @param send_buf the buffer to be transmitted to QSPI device. - * @param send_length the number of data to be transmitted. - * - * @return the status of transmit. - */ -rt_err_t rt_qspi_send(struct rt_qspi_device *device, const void *send_buf, rt_size_t length); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/rt-thread/components/drivers/include/drivers/syscon.h b/rt-thread/components/drivers/include/drivers/syscon.h new file mode 100644 index 0000000..15bb98b --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/syscon.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#ifndef __SYSCON_H__ +#define __SYSCON_H__ + +#include + +struct rt_syscon +{ + rt_list_t list; + + struct rt_ofw_node *np; + + void *iomem_base; + rt_size_t iomem_size; + struct rt_spinlock rw_lock; +}; + +rt_err_t rt_syscon_read(struct rt_syscon *syscon, rt_off_t offset, rt_uint32_t *out_val); +rt_err_t rt_syscon_write(struct rt_syscon *syscon, rt_off_t offset, rt_uint32_t val); +rt_err_t rt_syscon_update_bits(struct rt_syscon *syscon, rt_off_t offset, rt_uint32_t mask, rt_uint32_t val); + +struct rt_syscon *rt_syscon_find_by_ofw_node(struct rt_ofw_node *np); +struct rt_syscon *rt_syscon_find_by_ofw_compatible(const char *compatible); +struct rt_syscon *rt_syscon_find_by_ofw_phandle(struct rt_ofw_node *np, const char *propname); + +#endif /* __SYSCON_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/thermal.h b/rt-thread/components/drivers/include/drivers/thermal.h new file mode 100644 index 0000000..0770c5c --- /dev/null +++ b/rt-thread/components/drivers/include/drivers/thermal.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-3-08 GuEe-GUI the first version + */ + +#ifndef __THERMAL_H__ +#define __THERMAL_H__ + +#include +#include + +/* No upper/lower limit requirement */ +#define RT_THERMAL_NO_LIMIT ((rt_uint32_t)THERMAL_NO_LIMIT) +#define RT_THERMAL_TEMP_INVALID (-274000) + +struct rt_thermal_zone_ops; +struct rt_thermal_cooling_device; +struct rt_thermal_cooling_device_ops; +struct rt_thermal_cooling_governor; + +enum rt_thermal_trip_type +{ + RT_THERMAL_TRIP_ACTIVE = 0, + RT_THERMAL_TRIP_PASSIVE, + RT_THERMAL_TRIP_HOT, + RT_THERMAL_TRIP_CRITICAL, + + RT_THERMAL_TRIP_TYPE_MAX, +}; + +struct rt_thermal_trip +{ + /* Temperature value in millidegree celsius */ + int temperature; + /* Relative hysteresis in millidegree celsius */ + int hysteresis; + enum rt_thermal_trip_type type; + + void *priv; +}; + +struct rt_thermal_zone_params +{ + /* Sustainable power (heat) that this thermal zone can dissipate in mW */ + int sustainable_power; + /* Slope of a linear temperature adjustment curve */ + int slope; + /* Offset of a linear temperature adjustment curve */ + int offset; +}; + +struct rt_thermal_cooling_cell +{ + struct rt_thermal_cooling_device *cooling_devices; + + rt_uint32_t level_range[2]; +}; + +struct rt_thermal_cooling_map +{ + rt_uint32_t contribution; + + rt_size_t cells_nr; + struct rt_thermal_cooling_cell *cells; + struct rt_thermal_trip *trips; +}; + +struct rt_thermal_zone_device +{ + struct rt_device parent; + + int zone_id; + const struct rt_thermal_zone_ops *ops; + + rt_bool_t trips_free; + rt_size_t trips_nr; + struct rt_thermal_trip *trips; + struct rt_thermal_zone_params params; + + rt_bool_t enabled; + rt_bool_t cooling; + int temperature; + int last_temperature; + int prev_low_trip; + int prev_high_trip; + + rt_list_t notifier_nodes; + struct rt_spinlock nodes_lock; + + rt_size_t cooling_maps_nr; + struct rt_thermal_cooling_map *cooling_maps; + + rt_tick_t passive_delay, polling_delay; + struct rt_work poller; + + struct rt_mutex mutex; + + void *priv; +}; + +struct rt_thermal_zone_ops +{ + rt_err_t (*get_temp)(struct rt_thermal_zone_device *zdev, int *out_temp); + rt_err_t (*set_trips)(struct rt_thermal_zone_device *zdev, int low_temp, int high_temp); + rt_err_t (*set_trip_temp)(struct rt_thermal_zone_device *zdev, int trip_id, int temp); + rt_err_t (*set_trip_hyst)(struct rt_thermal_zone_device *zdev, int trip_id, int hyst); + void (*hot)(struct rt_thermal_zone_device *zdev); + void (*critical)(struct rt_thermal_zone_device *zdev); +}; + +/* + * We don't want to make a temperature control system + * that is finer than an air conditioner's temperature control, + * just ensure get a reliable heat dissipation under high-load task + * or when the SoC temperature is too high. + */ +struct rt_thermal_cooling_device +{ + struct rt_device parent; + + const struct rt_thermal_cooling_device_ops *ops; + + /* The cooling capacity indicator */ + rt_ubase_t max_level; + rt_list_t governor_node; + struct rt_thermal_cooling_governor *gov; + + void *priv; +}; + +struct rt_thermal_cooling_device_ops +{ + rt_err_t (*bind)(struct rt_thermal_cooling_device *cdev, struct rt_thermal_zone_device *zdev); + rt_err_t (*unbind)(struct rt_thermal_cooling_device *cdev, struct rt_thermal_zone_device *zdev); + rt_err_t (*get_max_level)(struct rt_thermal_cooling_device *cdev, rt_ubase_t *out_level); + rt_err_t (*get_cur_level)(struct rt_thermal_cooling_device *cdev, rt_ubase_t *out_level); + rt_err_t (*set_cur_level)(struct rt_thermal_cooling_device *cdev, rt_ubase_t level); +}; + +struct rt_thermal_cooling_governor +{ + rt_list_t list; + + const char *name; + rt_list_t cdev_nodes; + + void (*tuning)(struct rt_thermal_zone_device *zdev, + int map_idx, int cell_idx, rt_ubase_t *level); +}; + +struct rt_thermal_notifier; + +#define RT_THERMAL_MSG_EVENT_UNSPECIFIED RT_BIT(0) /* Unspecified event */ +#define RT_THERMAL_MSG_EVENT_TEMP_SAMPLE RT_BIT(1) /* New Temperature sample */ +#define RT_THERMAL_MSG_TRIP_VIOLATED RT_BIT(2) /* TRIP Point violation */ +#define RT_THERMAL_MSG_TRIP_CHANGED RT_BIT(3) /* TRIP Point temperature changed */ +#define RT_THERMAL_MSG_DEVICE_DOWN RT_BIT(4) /* Thermal device is down */ +#define RT_THERMAL_MSG_DEVICE_UP RT_BIT(5) /* Thermal device is up after a down event */ +#define RT_THERMAL_MSG_DEVICE_POWER_CAPABILITY_CHANGED RT_BIT(6) /* Power capability changed */ +#define RT_THERMAL_MSG_TABLE_CHANGED RT_BIT(7) /* Thermal table(s) changed */ +#define RT_THERMAL_MSG_EVENT_KEEP_ALIVE RT_BIT(8) /* Request for user space handler to respond */ + +typedef rt_err_t (*rt_thermal_notifier_callback)(struct rt_thermal_notifier *notifier, + rt_ubase_t msg); + +struct rt_thermal_notifier +{ + rt_list_t list; + + struct rt_thermal_zone_device *zdev; + rt_thermal_notifier_callback callback; + void *priv; +}; + +rt_err_t rt_thermal_zone_device_register(struct rt_thermal_zone_device *zdev); +rt_err_t rt_thermal_zone_device_unregister(struct rt_thermal_zone_device *zdev); + +rt_err_t rt_thermal_cooling_device_register(struct rt_thermal_cooling_device *cdev); +rt_err_t rt_thermal_cooling_device_unregister(struct rt_thermal_cooling_device *cdev); + +rt_err_t rt_thermal_cooling_governor_register(struct rt_thermal_cooling_governor *gov); +rt_err_t rt_thermal_cooling_governor_unregister(struct rt_thermal_cooling_governor *gov); + +rt_err_t rt_thermal_cooling_device_change_governor(struct rt_thermal_cooling_device *cdev, + const char *name); + +rt_err_t rt_thermal_zone_notifier_register(struct rt_thermal_zone_device *zdev, + struct rt_thermal_notifier *notifier); +rt_err_t rt_thermal_zone_notifier_unregister(struct rt_thermal_zone_device *zdev, + struct rt_thermal_notifier *notifier); + +void rt_thermal_zone_device_update(struct rt_thermal_zone_device *zdev, rt_ubase_t msg); +void rt_thermal_cooling_device_kick(struct rt_thermal_zone_device *zdev); + +rt_err_t rt_thermal_zone_set_trip(struct rt_thermal_zone_device *zdev, int trip_id, + const struct rt_thermal_trip *trip); +rt_err_t rt_thermal_zone_get_trip(struct rt_thermal_zone_device *zdev, int trip_id, + struct rt_thermal_trip *out_trip); + +#endif /* __THERMAL_H__ */ diff --git a/rt-thread/components/drivers/include/drivers/wlan.h b/rt-thread/components/drivers/include/drivers/wlan.h index 9468518..4a1ab5b 100644 --- a/rt-thread/components/drivers/include/drivers/wlan.h +++ b/rt-thread/components/drivers/include/drivers/wlan.h @@ -12,10 +12,10 @@ #define __WLAN_H__ #include -#include -#include -#include -#include -#include +#include +#include +#include +#include +#include #endif diff --git a/rt-thread/components/drivers/include/dt-bindings/phye/phye.h b/rt-thread/components/drivers/include/dt-bindings/phye/phye.h new file mode 100644 index 0000000..54a9cce --- /dev/null +++ b/rt-thread/components/drivers/include/dt-bindings/phye/phye.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DT_BINDINGS_PHYE_H__ +#define __DT_BINDINGS_PHYE_H__ + +#define PHY_NONE 0 +#define PHY_TYPE_SATA 1 +#define PHY_TYPE_PCIE 2 +#define PHY_TYPE_USB2 3 +#define PHY_TYPE_USB3 4 +#define PHY_TYPE_UFS 5 +#define PHY_TYPE_DP 6 +#define PHY_TYPE_XPCS 7 +#define PHY_TYPE_SGMII 8 +#define PHY_TYPE_QSGMII 9 +#define PHY_TYPE_DPHY 10 +#define PHY_TYPE_CPHY 11 +#define PHY_TYPE_USXGMII 12 + +#endif /* __DT_BINDINGS_PHYE_H__ */ diff --git a/rt-thread/components/drivers/include/dt-bindings/thermal/thermal.h b/rt-thread/components/drivers/include/dt-bindings/thermal/thermal.h new file mode 100644 index 0000000..60414cf --- /dev/null +++ b/rt-thread/components/drivers/include/dt-bindings/thermal/thermal.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DT_BINDINGS_THERMAL_THERMAL_H__ +#define __DT_BINDINGS_THERMAL_THERMAL_H__ + +/* On cooling devices upper and lower limits */ +#define THERMAL_NO_LIMIT (~0) + +#endif /* __DT_BINDINGS_THERMAL_THERMAL_H__ */ diff --git a/rt-thread/components/drivers/include/ipc/completion.h b/rt-thread/components/drivers/include/ipc/completion.h index 30f4acf..25581f6 100644 --- a/rt-thread/components/drivers/include/ipc/completion.h +++ b/rt-thread/components/drivers/include/ipc/completion.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2024-04-28 Shell Add new wait_flags() & wakeup_by_errno() API + * 2024-10-24 yekai Add C++ support */ #ifndef COMPLETION_H_ #define COMPLETION_H_ @@ -14,9 +15,9 @@ #include /** - * Completion - A tiny & rapid IPC primitive for resource-constrained scenarios + * RT-Completion - A Tiny(resource-constrained) & Rapid(lockless) IPC Primitive * - * It's an IPC using one CPU word with the encoding: + * It's an IPC using one pointer word with the encoding: * * BIT | MAX-1 ----------------- 1 | 0 | * CONTENT | suspended_thread & ~1 | completed flag | @@ -30,12 +31,25 @@ struct rt_completion #define RT_COMPLETION_INIT(comp) {0} +#ifdef __cplusplus +extern "C" { +#endif + void rt_completion_init(struct rt_completion *completion); rt_err_t rt_completion_wait(struct rt_completion *completion, rt_int32_t timeout); +rt_err_t rt_completion_wait_noisr(struct rt_completion *completion, + rt_int32_t timeout); rt_err_t rt_completion_wait_flags(struct rt_completion *completion, rt_int32_t timeout, int suspend_flag); +rt_err_t rt_completion_wait_flags_noisr(struct rt_completion *completion, + rt_int32_t timeout, int suspend_flag); void rt_completion_done(struct rt_completion *completion); rt_err_t rt_completion_wakeup(struct rt_completion *completion); rt_err_t rt_completion_wakeup_by_errno(struct rt_completion *completion, rt_err_t error); + +#ifdef __cplusplus +} +#endif + #endif diff --git a/rt-thread/components/drivers/include/ipc/workqueue.h b/rt-thread/components/drivers/include/ipc/workqueue.h index e05a7ab..8d0c986 100644 --- a/rt-thread/components/drivers/include/ipc/workqueue.h +++ b/rt-thread/components/drivers/include/ipc/workqueue.h @@ -13,6 +13,7 @@ #include #include +#include "completion.h" #ifdef __cplusplus extern "C" { @@ -42,6 +43,7 @@ struct rt_workqueue struct rt_semaphore sem; rt_thread_t work_thread; struct rt_spinlock spinlock; + struct rt_completion wakeup_completion; }; struct rt_work @@ -52,7 +54,7 @@ struct rt_work void *work_data; rt_uint16_t flags; rt_uint16_t type; - struct rt_timer timer; + rt_tick_t timeout_tick; struct rt_workqueue *workqueue; }; diff --git a/rt-thread/components/drivers/include/rtdevice.h b/rt-thread/components/drivers/include/rtdevice.h index 5b080fc..fd4d316 100644 --- a/rt-thread/components/drivers/include/rtdevice.h +++ b/rt-thread/components/drivers/include/rtdevice.h @@ -45,6 +45,34 @@ extern "C" { #include "drivers/core/power_domain.h" #include "drivers/platform.h" +#ifdef RT_USING_ATA +#ifdef RT_ATA_AHCI +#include "drivers/ahci.h" +#endif /* RT_ATA_AHCI */ +#endif /* RT_USING_ATA */ + +#ifdef RT_USING_LED +#include "drivers/led.h" +#endif + +#ifdef RT_USING_MBOX +#include "drivers/mailbox.h" +#endif /* RT_USING_MBOX */ + +#ifdef RT_USING_BLK +#include "drivers/blk.h" +#endif /* RT_USING_BLK */ + +#ifdef RT_USING_DMA +#include "drivers/dma.h" +#endif /* RT_USING_DMA */ + +#include "drivers/iio.h" + +#ifdef RT_USING_NVME +#include "drivers/nvme.h" +#endif /* RT_USING_NVME */ + #ifdef RT_USING_OFW #include "drivers/ofw.h" #include "drivers/ofw_fdt.h" @@ -53,20 +81,54 @@ extern "C" { #include "drivers/ofw_raw.h" #endif /* RT_USING_OFW */ +#ifdef RT_USING_PHYE +#include "drivers/phye.h" +#endif /* RT_USING_PHYE */ + #ifdef RT_USING_PIC #include "drivers/pic.h" -#endif +#endif /* RT_USING_PIC */ + +#ifdef RT_USING_PCI +#include "drivers/pci.h" +#ifdef RT_PCI_MSI +#include "drivers/pci_msi.h" +#endif /* RT_PCI_MSI */ +#ifdef RT_PCI_ENDPOINT +#include "drivers/pci_endpoint.h" +#endif /* RT_PCI_ENDPOINT */ +#endif /* RT_USING_PCI */ + +#ifdef RT_USING_REGULATOR +#include "drivers/regulator.h" +#endif /* RT_USING_REGULATOR */ + +#ifdef RT_USING_RESET +#include "drivers/reset.h" +#endif /* RT_USING_RESET */ + +#ifdef RT_USING_SCSI +#include "drivers/scsi.h" +#endif /* RT_USING_SCSI */ + +#ifdef RT_MFD_SYSCON +#include "drivers/syscon.h" +#endif /* RT_MFD_SYSCON */ + +#ifdef RT_USING_THERMAL +#include "drivers/thermal.h" +#endif /* RT_USING_THERMAL */ #endif /* RT_USING_DM */ #ifdef RT_USING_RTC -#include "drivers/rtc.h" +#include "drivers/dev_rtc.h" #ifdef RT_USING_ALARM -#include "drivers/alarm.h" -#endif +#include "drivers/dev_alarm.h" +#endif /* RT_USING_ALARM */ #endif /* RT_USING_RTC */ #ifdef RT_USING_SPI -#include "drivers/spi.h" +#include "drivers/dev_spi.h" #endif /* RT_USING_SPI */ #ifdef RT_USING_MTD_NOR @@ -87,43 +149,44 @@ extern "C" { #ifdef RT_USING_SERIAL #ifdef RT_USING_SERIAL_V2 -#include "drivers/serial_v2.h" +#include "drivers/dev_serial_v2.h" #else -#include "drivers/serial.h" +#include "drivers/dev_serial.h" +#ifdef RT_USING_SERIAL_BYPASS +#include "drivers/serial_bypass.h" +#endif /* RT_USING_SERIAL_BYPASS */ #endif #endif /* RT_USING_SERIAL */ #ifdef RT_USING_I2C -#include "drivers/i2c.h" -#include "drivers/i2c_dev.h" +#include "drivers/dev_i2c.h" #ifdef RT_USING_I2C_BITOPS -#include "drivers/i2c-bit-ops.h" +#include "drivers/dev_i2c_bit_ops.h" #endif /* RT_USING_I2C_BITOPS */ #ifdef RT_USING_DM -#include "drivers/i2c_dm.h" +#include "drivers/dev_i2c_dm.h" #endif /* RT_USING_DM */ #endif /* RT_USING_I2C */ #ifdef RT_USING_PHY #include "drivers/phy.h" -#include "drivers/phy_mdio.h" #endif /* RT_USING_PHY */ #ifdef RT_USING_SDIO -#include "drivers/mmcsd_core.h" -#include "drivers/sd.h" -#include "drivers/sdio.h" +#include "drivers/dev_mmcsd_core.h" +#include "drivers/dev_sd.h" +#include "drivers/dev_sdio.h" #endif /* RT_USING_SDIO */ #ifdef RT_USING_WDT -#include "drivers/watchdog.h" +#include "drivers/dev_watchdog.h" #endif /* RT_USING_WDT */ #ifdef RT_USING_PIN -#include "drivers/pin.h" +#include "drivers/dev_pin.h" #endif /* RT_USING_PIN */ #ifdef RT_USING_SENSOR @@ -135,7 +198,7 @@ extern "C" { #endif /* RT_USING_SENSOR */ #ifdef RT_USING_CAN -#include "drivers/can.h" +#include "drivers/dev_can.h" #endif /* RT_USING_CAN */ #ifdef RT_USING_HWTIMER @@ -143,7 +206,7 @@ extern "C" { #endif /* RT_USING_HWTIMER */ #ifdef RT_USING_AUDIO -#include "drivers/audio.h" +#include "drivers/dev_audio.h" #endif /* RT_USING_AUDIO */ #ifdef RT_USING_CPUTIME @@ -159,7 +222,7 @@ extern "C" { #endif /* RT_USING_DAC */ #ifdef RT_USING_PWM -#include "drivers/rt_drv_pwm.h" +#include "drivers/dev_pwm.h" #endif /* RT_USING_PWM */ #ifdef RT_USING_PM @@ -191,7 +254,7 @@ extern "C" { #endif /* RT_USING_INPUT_CAPTURE */ #ifdef RT_USING_TOUCH -#include "drivers/touch.h" +#include "drivers/dev_touch.h" #endif #ifdef RT_USING_DEV_BUS diff --git a/rt-thread/components/drivers/ipc/completion_comm.c b/rt-thread/components/drivers/ipc/completion_comm.c index 6828714..67c00b4 100644 --- a/rt-thread/components/drivers/ipc/completion_comm.c +++ b/rt-thread/components/drivers/ipc/completion_comm.c @@ -35,6 +35,28 @@ rt_err_t rt_completion_wakeup(struct rt_completion *completion) return rt_completion_wakeup_by_errno(completion, -1); } +/** + * @brief This is same as rt_completion_wait(), except that this API is NOT + * ISR-safe (you can NOT call completion_done() on isr routine). + * + * @param completion is a pointer to a completion object. + * + * @param timeout is a timeout period (unit: OS ticks). If the completion is unavailable, the thread will wait for + * the completion done up to the amount of time specified by the argument. + * NOTE: Generally, we use the macro RT_WAITING_FOREVER to set this parameter, which means that when the + * completion is unavailable, the thread will be waitting forever. + * + * @return Return the operation status. ONLY when the return value is RT_EOK, the operation is successful. + * If the return value is any other values, it means that the completion wait failed. + * + * @warning This function can ONLY be called in the thread context. It MUST NOT be called in interrupt context. + */ +rt_err_t rt_completion_wait_noisr(struct rt_completion *completion, + rt_int32_t timeout) +{ + return rt_completion_wait_flags_noisr(completion, timeout, RT_UNINTERRUPTIBLE); +} + /** * @brief This function will wait for a completion, if the completion is unavailable, the thread shall wait for * the completion up to a specified time. diff --git a/rt-thread/components/drivers/ipc/completion_mp.c b/rt-thread/components/drivers/ipc/completion_mp.c index 21627e0..38ffc6f 100644 --- a/rt-thread/components/drivers/ipc/completion_mp.c +++ b/rt-thread/components/drivers/ipc/completion_mp.c @@ -65,11 +65,10 @@ void rt_completion_init(struct rt_completion *completion) RTM_EXPORT(rt_completion_init); /** - * @brief This function will wait for a completion, if the completion is unavailable, the thread shall wait for - * the completion up to a specified time. + * @brief This is same as rt_completion_wait_flags(), except that this API is NOT + * ISR-safe (you can NOT call completion_done() on isr routine). * * @param completion is a pointer to a completion object. - * * @param timeout is a timeout period (unit: OS ticks). If the completion is unavailable, the thread will wait for * the completion done up to the amount of time specified by the argument. * NOTE: Generally, we use the macro RT_WAITING_FOREVER to set this parameter, which means that when the @@ -81,8 +80,8 @@ RTM_EXPORT(rt_completion_init); * * @warning This function can ONLY be called in the thread context. It MUST NOT be called in interrupt context. */ -rt_err_t rt_completion_wait_flags(struct rt_completion *completion, - rt_int32_t timeout, int suspend_flag) +rt_err_t rt_completion_wait_flags_noisr(struct rt_completion *completion, + rt_int32_t timeout, int suspend_flag) { rt_err_t result = -RT_ERROR; rt_thread_t thread; @@ -159,6 +158,33 @@ rt_err_t rt_completion_wait_flags(struct rt_completion *completion, return result; } +/** + * @brief This function will wait for a completion, if the completion is unavailable, the thread shall wait for + * the completion up to a specified time. + * + * @param completion is a pointer to a completion object. + * @param timeout is a timeout period (unit: OS ticks). If the completion is unavailable, the thread will wait for + * the completion done up to the amount of time specified by the argument. + * NOTE: Generally, we use the macro RT_WAITING_FOREVER to set this parameter, which means that when the + * completion is unavailable, the thread will be waitting forever. + * @param suspend_flag suspend flags. See rt_thread_suspend_with_flag() + * + * @return Return the operation status. ONLY when the return value is RT_EOK, the operation is successful. + * If the return value is any other values, it means that the completion wait failed. + * + * @warning This function can ONLY be called in the thread context. It MUST NOT be called in interrupt context. + */ +rt_err_t rt_completion_wait_flags(struct rt_completion *completion, + rt_int32_t timeout, int suspend_flag) +{ + rt_err_t error; + rt_ubase_t level; + level = rt_hw_local_irq_disable(); + error = rt_completion_wait_flags_noisr(completion, timeout, suspend_flag); + rt_hw_local_irq_enable(level); + return error; +} + static rt_base_t _wait_until_update(struct rt_completion *completion, rt_base_t expected) { rt_base_t current_value; diff --git a/rt-thread/components/drivers/ipc/completion_up.c b/rt-thread/components/drivers/ipc/completion_up.c index 5c8e546..8c3bbbf 100644 --- a/rt-thread/components/drivers/ipc/completion_up.c +++ b/rt-thread/components/drivers/ipc/completion_up.c @@ -148,6 +148,28 @@ __exit: return result; } +/** + * @brief This is same as rt_completion_wait_flags(), except that this API is NOT + * ISR-safe (you can NOT call completion_done() on isr routine). + * + * @param completion is a pointer to a completion object. + * @param timeout is a timeout period (unit: OS ticks). If the completion is unavailable, the thread will wait for + * the completion done up to the amount of time specified by the argument. + * NOTE: Generally, we use the macro RT_WAITING_FOREVER to set this parameter, which means that when the + * completion is unavailable, the thread will be waitting forever. + * @param suspend_flag suspend flags. See rt_thread_suspend_with_flag() + * + * @return Return the operation status. ONLY when the return value is RT_EOK, the operation is successful. + * If the return value is any other values, it means that the completion wait failed. + * + * @warning This function can ONLY be called in the thread context. It MUST NOT be called in interrupt context. + */ +rt_err_t rt_completion_wait_flags_noisr(struct rt_completion *completion, + rt_int32_t timeout, int suspend_flag) +{ + return rt_completion_wait_flags(completion, timeout, suspend_flag); +} + /** * @brief This function indicates a completion has done and wakeup the thread * and update its errno. No update is applied if it's a negative value. diff --git a/rt-thread/components/drivers/ipc/workqueue.c b/rt-thread/components/drivers/ipc/workqueue.c index fb3657b..30b779e 100644 --- a/rt-thread/components/drivers/ipc/workqueue.c +++ b/rt-thread/components/drivers/ipc/workqueue.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,6 +10,7 @@ * 2021-08-14 Jackistang add comments for function interface * 2022-01-16 Meco Man add rt_work_urgent() * 2023-09-15 xqyjlj perf rt_hw_interrupt_disable/enable + * 2024-12-21 yuqingli delete timer, using list */ #include @@ -17,8 +18,6 @@ #ifdef RT_USING_HEAP -static void _delayed_work_timeout_handler(void *parameter); - rt_inline rt_err_t _workqueue_work_completion(struct rt_workqueue *queue) { rt_err_t result; @@ -50,38 +49,61 @@ rt_inline rt_err_t _workqueue_work_completion(struct rt_workqueue *queue) static void _workqueue_thread_entry(void *parameter) { - rt_base_t level; - struct rt_work *work; + rt_base_t level; + struct rt_work *work; struct rt_workqueue *queue; + rt_tick_t current_tick; + rt_int32_t delay_tick; + void (*work_func)(struct rt_work *work, void *work_data); + void *work_data; - queue = (struct rt_workqueue *) parameter; + queue = (struct rt_workqueue *)parameter; RT_ASSERT(queue != RT_NULL); while (1) { level = rt_spin_lock_irqsave(&(queue->spinlock)); + + /* timer check */ + current_tick = rt_tick_get(); + delay_tick = RT_WAITING_FOREVER; + while (!rt_list_isempty(&(queue->delayed_list))) + { + work = rt_list_entry(queue->delayed_list.next, struct rt_work, list); + if ((current_tick - work->timeout_tick) < RT_TICK_MAX / 2) + { + rt_list_remove(&(work->list)); + rt_list_insert_after(queue->work_list.prev, &(work->list)); + work->flags &= ~RT_WORK_STATE_SUBMITTING; + work->flags |= RT_WORK_STATE_PENDING; + } + else + { + delay_tick = work->timeout_tick - current_tick; + break; + } + } + if (rt_list_isempty(&(queue->work_list))) { - /* no software timer exist, suspend self. */ - rt_thread_suspend_with_flag(rt_thread_self(), RT_UNINTERRUPTIBLE); - - /* release lock after suspend so we will not lost any wakeups */ rt_spin_unlock_irqrestore(&(queue->spinlock), level); - - rt_schedule(); + /* wait for work completion */ + rt_completion_wait(&(queue->wakeup_completion), delay_tick); continue; } /* we have work to do with. */ work = rt_list_entry(queue->work_list.next, struct rt_work, list); rt_list_remove(&(work->list)); - queue->work_current = work; - work->flags &= ~RT_WORK_STATE_PENDING; - work->workqueue = RT_NULL; + queue->work_current = work; + work->flags &= ~RT_WORK_STATE_PENDING; + work->workqueue = RT_NULL; + work_func = work->work_func; + work_data = work->work_data; rt_spin_unlock_irqrestore(&(queue->spinlock), level); /* do work */ - work->work_func(work, work->work_data); + work_func(work, work_data); /* clean current work */ queue->work_current = RT_NULL; @@ -93,52 +115,52 @@ static void _workqueue_thread_entry(void *parameter) static rt_err_t _workqueue_submit_work(struct rt_workqueue *queue, struct rt_work *work, rt_tick_t ticks) { - rt_base_t level; - rt_err_t err = RT_EOK; + rt_base_t level; + rt_err_t err = RT_EOK; + struct rt_work *work_tmp; + rt_list_t *list_tmp; level = rt_spin_lock_irqsave(&(queue->spinlock)); - /* remove list */ rt_list_remove(&(work->list)); - work->flags &= ~RT_WORK_STATE_PENDING; + work->flags = 0; if (ticks == 0) { rt_list_insert_after(queue->work_list.prev, &(work->list)); - work->flags |= RT_WORK_STATE_PENDING; - work->workqueue = queue; + work->flags |= RT_WORK_STATE_PENDING; + work->workqueue = queue; - /* whether the workqueue is doing work */ - if (queue->work_current == RT_NULL) - { - /* resume work thread, and do a re-schedule if succeed */ - rt_thread_resume(queue->work_thread); - } + rt_completion_done(&(queue->wakeup_completion)); + err = RT_EOK; } else if (ticks < RT_TICK_MAX / 2) { - /* Timer started */ - if (work->flags & RT_WORK_STATE_SUBMITTING) - { - rt_timer_control(&work->timer, RT_TIMER_CTRL_SET_TIME, &ticks); - } - else - { - rt_timer_init(&(work->timer), "work", _delayed_work_timeout_handler, - work, ticks, RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_SOFT_TIMER); - work->flags |= RT_WORK_STATE_SUBMITTING; - } - work->workqueue = queue; /* insert delay work list */ - rt_list_insert_after(queue->delayed_list.prev, &(work->list)); + work->flags |= RT_WORK_STATE_SUBMITTING; + work->workqueue = queue; + work->timeout_tick = rt_tick_get() + ticks; - err = rt_timer_start(&(work->timer)); + list_tmp = &(queue->delayed_list); + for (work_tmp = rt_list_entry(list_tmp->next, struct rt_work, list); + &work_tmp->list != list_tmp; + work_tmp = rt_list_entry(work_tmp->list.next, struct rt_work, list)) + { + if ((work_tmp->timeout_tick - work->timeout_tick) < RT_TICK_MAX / 2) + { + list_tmp = &(work_tmp->list); + break; + } + } + rt_list_insert_before(list_tmp, &(work->list)); + + rt_completion_done(&(queue->wakeup_completion)); + err = RT_EOK; } else { - err = - RT_ERROR; + err = -RT_ERROR; } - rt_spin_unlock_irqrestore(&(queue->spinlock), level); return err; } @@ -146,61 +168,17 @@ static rt_err_t _workqueue_submit_work(struct rt_workqueue *queue, static rt_err_t _workqueue_cancel_work(struct rt_workqueue *queue, struct rt_work *work) { rt_base_t level; - rt_err_t err; + rt_err_t err; level = rt_spin_lock_irqsave(&(queue->spinlock)); rt_list_remove(&(work->list)); - work->flags &= ~RT_WORK_STATE_PENDING; - /* Timer started */ - if (work->flags & RT_WORK_STATE_SUBMITTING) - { - if ((err = rt_timer_stop(&(work->timer))) != RT_EOK) - { - goto exit; - } - rt_timer_detach(&(work->timer)); - work->flags &= ~RT_WORK_STATE_SUBMITTING; - } - err = queue->work_current != work ? RT_EOK : -RT_EBUSY; + work->flags = 0; + err = queue->work_current != work ? RT_EOK : -RT_EBUSY; work->workqueue = RT_NULL; -exit: rt_spin_unlock_irqrestore(&(queue->spinlock), level); return err; } -static void _delayed_work_timeout_handler(void *parameter) -{ - struct rt_work *work; - struct rt_workqueue *queue; - rt_base_t level; - - work = (struct rt_work *)parameter; - queue = work->workqueue; - - RT_ASSERT(work->flags & RT_WORK_STATE_SUBMITTING); - RT_ASSERT(queue != RT_NULL); - - level = rt_spin_lock_irqsave(&(queue->spinlock)); - rt_timer_detach(&(work->timer)); - work->flags &= ~RT_WORK_STATE_SUBMITTING; - /* remove delay list */ - rt_list_remove(&(work->list)); - /* insert work queue */ - if (queue->work_current != work) - { - rt_list_insert_after(queue->work_list.prev, &(work->list)); - work->flags |= RT_WORK_STATE_PENDING; - } - /* whether the workqueue is doing work */ - if (queue->work_current == RT_NULL) - { - /* resume work thread, and do a re-schedule if succeed */ - rt_thread_resume(queue->work_thread); - } - - rt_spin_unlock_irqrestore(&(queue->spinlock), level); -} - /** * @brief Initialize a work item, binding with a callback function. * @@ -221,8 +199,8 @@ void rt_work_init(struct rt_work *work, work->work_func = work_func; work->work_data = work_data; work->workqueue = RT_NULL; - work->flags = 0; - work->type = 0; + work->flags = 0; + work->type = 0; } /** @@ -248,6 +226,7 @@ struct rt_workqueue *rt_workqueue_create(const char *name, rt_uint16_t stack_siz rt_list_init(&(queue->delayed_list)); queue->work_current = RT_NULL; rt_sem_init(&(queue->sem), "wqueue", 0, RT_IPC_FLAG_FIFO); + rt_completion_init(&(queue->wakeup_completion)); /* create the work thread */ queue->work_thread = rt_thread_create(name, _workqueue_thread_entry, queue, stack_size, priority, 10); @@ -292,7 +271,6 @@ rt_err_t rt_workqueue_destroy(struct rt_workqueue *queue) * @param work is a pointer to the work item object. * * @return RT_EOK Success. - * -RT_EBUSY This work item is executing. */ rt_err_t rt_workqueue_dowork(struct rt_workqueue *queue, struct rt_work *work) { @@ -314,7 +292,6 @@ rt_err_t rt_workqueue_dowork(struct rt_workqueue *queue, struct rt_work *work) * NOTE: The max timeout tick should be no more than (RT_TICK_MAX/2 - 1) * * @return RT_EOK Success. - * -RT_EBUSY This work item is executing. * -RT_ERROR The ticks parameter is invalid. */ rt_err_t rt_workqueue_submit_work(struct rt_workqueue *queue, struct rt_work *work, rt_tick_t ticks) @@ -346,14 +323,10 @@ rt_err_t rt_workqueue_urgent_work(struct rt_workqueue *queue, struct rt_work *wo /* NOTE: the work MUST be initialized firstly */ rt_list_remove(&(work->list)); rt_list_insert_after(&queue->work_list, &(work->list)); - /* whether the workqueue is doing work */ - if (queue->work_current == RT_NULL) - { - /* resume work thread, and do a re-schedule if succeed */ - rt_thread_resume(queue->work_thread); - } + rt_completion_done(&(queue->wakeup_completion)); rt_spin_unlock_irqrestore(&(queue->spinlock), level); + return RT_EOK; } @@ -448,7 +421,6 @@ static struct rt_workqueue *sys_workq; /* system work queue */ * NOTE: The max timeout tick should be no more than (RT_TICK_MAX/2 - 1) * * @return RT_EOK Success. - * -RT_EBUSY This work item is executing. * -RT_ERROR The ticks parameter is invalid. */ rt_err_t rt_work_submit(struct rt_work *work, rt_tick_t ticks) diff --git a/rt-thread/components/drivers/led/Kconfig b/rt-thread/components/drivers/led/Kconfig new file mode 100644 index 0000000..462aa0b --- /dev/null +++ b/rt-thread/components/drivers/led/Kconfig @@ -0,0 +1,15 @@ +menuconfig RT_USING_LED + bool "Using Light Emitting Diode (LED) device drivers" + depends on RT_USING_DM + default n + +config RT_LED_GPIO + bool "GPIO connected LEDs Support" + depends on RT_USING_LED + depends on RT_USING_PINCTRL + depends on RT_USING_OFW + default n + +if RT_USING_LED + osource "$(SOC_DM_LED_DIR)/Kconfig" +endif diff --git a/rt-thread/components/drivers/led/SConscript b/rt-thread/components/drivers/led/SConscript new file mode 100644 index 0000000..276ca0b --- /dev/null +++ b/rt-thread/components/drivers/led/SConscript @@ -0,0 +1,18 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_DM', 'RT_USING_LED']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] + +src = ['led.c'] + +if GetDepend(['RT_LED_GPIO']): + src += ['led-gpio.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/led/led-gpio.c b/rt-thread/components/drivers/led/led-gpio.c new file mode 100644 index 0000000..0b6bd68 --- /dev/null +++ b/rt-thread/components/drivers/led/led-gpio.c @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-3-08 GuEe-GUI the first version + */ + +#include +#include + +#define DBG_TAG "led.gpio" +#define DBG_LVL DBG_INFO +#include + +struct gpio_led +{ + struct rt_led_device parent; + + rt_base_t pin; + rt_uint8_t active_val; +}; + +#define raw_to_gpio_led(raw) rt_container_of(raw, struct gpio_led, parent); + +static rt_err_t gpio_led_set_state(struct rt_led_device *led, enum rt_led_state state) +{ + rt_err_t err = RT_EOK; + struct gpio_led *gled = raw_to_gpio_led(led); + + rt_pin_mode(gled->pin, PIN_MODE_OUTPUT); + + switch (state) + { + case RT_LED_S_OFF: + rt_pin_write(gled->pin, !gled->active_val); + break; + + case RT_LED_S_ON: + rt_pin_write(gled->pin, gled->active_val); + break; + + case RT_LED_S_TOGGLE: + err = led->ops->get_state(led, &state); + + if (!err) + { + err = led->ops->set_state(led, state == RT_LED_S_OFF ? RT_LED_S_ON : RT_LED_S_OFF); + } + break; + + default: + return -RT_ENOSYS; + } + + return err; +} + +static rt_err_t gpio_led_get_state(struct rt_led_device *led, enum rt_led_state *out_state) +{ + struct gpio_led *gled = raw_to_gpio_led(led); + + switch (rt_pin_read(gled->pin)) + { + case PIN_LOW: + *out_state = RT_LED_S_OFF; + break; + + case PIN_HIGH: + *out_state = RT_LED_S_ON; + break; + + default: + return -RT_ERROR; + } + + return RT_EOK; +} + +const static struct rt_led_ops gpio_led_ops = +{ + .set_state = gpio_led_set_state, + .get_state = gpio_led_get_state, +}; + +static rt_err_t ofw_append_gpio_led(struct rt_ofw_node *np) +{ + rt_err_t err; + enum rt_led_state led_state = RT_LED_S_OFF; + const char *propname, *state, *trigger; + struct gpio_led *gled = rt_malloc(sizeof(*gled)); + + if (!gled) + { + return -RT_ENOMEM; + } + + gled->pin = rt_ofw_get_named_pin(np, RT_NULL, 0, RT_NULL, &gled->active_val); + + if (gled->pin < 0) + { + err = gled->pin; + + goto _fail; + } + + gled->parent.ops = &gpio_led_ops; + + if ((err = rt_hw_led_register(&gled->parent))) + { + goto _fail; + } + + if (!rt_ofw_prop_read_string(np, "default-state", &state)) + { + if (!rt_strcmp(state, "on")) + { + led_state = RT_LED_S_ON; + } + } + + if ((propname = rt_ofw_get_prop_fuzzy_name(np, "default-trigger$"))) + { + if (!rt_ofw_prop_read_string(np, propname, &trigger)) + { + if (!rt_strcmp(trigger, "heartbeat") || + !rt_strcmp(trigger, "timer")) + { + led_state = RT_LED_S_BLINK; + } + } + } + + rt_led_set_state(&gled->parent, led_state); + + rt_ofw_data(np) = &gled->parent; + + return RT_EOK; + +_fail: + rt_free(gled); + + return err; +} + +static rt_err_t gpio_led_probe(struct rt_platform_device *pdev) +{ + rt_bool_t pinctrl_apply = RT_FALSE; + struct rt_ofw_node *led_np, *np = pdev->parent.ofw_node; + + if (rt_ofw_prop_read_bool(np, "pinctrl-0")) + { + pinctrl_apply = RT_TRUE; + rt_pin_ctrl_confs_apply_by_name(&pdev->parent, RT_NULL); + } + + rt_ofw_foreach_available_child_node(np, led_np) + { + rt_err_t err = ofw_append_gpio_led(led_np); + + if (err == -RT_ENOMEM) + { + rt_ofw_node_put(led_np); + + return err; + } + else if (err) + { + LOG_E("%s: create LED fail", rt_ofw_node_full_name(led_np)); + continue; + } + + if (!pinctrl_apply) + { + struct rt_device dev_tmp; + + dev_tmp.ofw_node = led_np; + rt_pin_ctrl_confs_apply_by_name(&dev_tmp, RT_NULL); + } + } + + return RT_EOK; +} + +static rt_err_t gpio_led_remove(struct rt_platform_device *pdev) +{ + struct gpio_led *gled; + struct rt_led_device *led_dev; + struct rt_ofw_node *led_np, *np = pdev->parent.ofw_node; + + rt_ofw_foreach_available_child_node(np, led_np) + { + led_dev = rt_ofw_data(led_np); + + if (!led_dev) + { + continue; + } + + gled = rt_container_of(led_dev, struct gpio_led, parent); + + rt_ofw_data(led_np) = RT_NULL; + + rt_hw_led_unregister(&gled->parent); + + rt_free(gled); + } + + return RT_EOK; +} + +static const struct rt_ofw_node_id gpio_led_ofw_ids[] = +{ + { .compatible = "gpio-leds" }, + { /* sentinel */ } +}; + +static struct rt_platform_driver gpio_led_driver = +{ + .name = "led-gpio", + .ids = gpio_led_ofw_ids, + + .probe = gpio_led_probe, + .remove = gpio_led_remove, +}; +RT_PLATFORM_DRIVER_EXPORT(gpio_led_driver); diff --git a/rt-thread/components/drivers/led/led.c b/rt-thread/components/drivers/led/led.c new file mode 100644 index 0000000..611a16d --- /dev/null +++ b/rt-thread/components/drivers/led/led.c @@ -0,0 +1,349 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-3-08 GuEe-GUI the first version + */ + +#include + +#define DBG_TAG "rtdm.led" +#define DBG_LVL DBG_INFO +#include + +#include +#include + +struct blink_timer +{ + rt_bool_t toggle; + rt_bool_t enabled; + struct rt_timer timer; +}; + +static struct rt_dm_ida led_ida = RT_DM_IDA_INIT(LED); + +static const char * const _led_states[] = +{ + [RT_LED_S_OFF] = "off", + [RT_LED_S_ON] = "on", + [RT_LED_S_TOGGLE] = "toggle", + [RT_LED_S_BLINK] = "blink", +}; + +static rt_ssize_t _led_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + rt_ssize_t res; + rt_size_t state_len; + enum rt_led_state state; + struct rt_led_device *led = rt_container_of(dev, struct rt_led_device, parent); + + if ((res = rt_led_get_state(led, &state))) + { + return res; + } + + state_len = rt_strlen(_led_states[state]); + + if (pos < state_len) + { + size = rt_min_t(rt_size_t, size, size - pos); + ((char *)buffer)[size - 1] = '\0'; + rt_strncpy(buffer, &_led_states[state][pos], size); + + return size; + } + else + { + return 0; + } +} + +static rt_ssize_t _led_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + rt_uint32_t brightness = 0; + const char *value = buffer; + struct rt_led_device *led = rt_container_of(dev, struct rt_led_device, parent); + + for (int i = 0; i < RT_ARRAY_SIZE(_led_states); ++i) + { + if (!rt_strncpy((char *)_led_states[i], buffer, size)) + { + return rt_led_set_state(led, i) ? : size; + } + } + + while (*value) + { + if (*value < '0' || *value > '9') + { + return -RT_EINVAL; + } + + brightness *= 10; + brightness += *value - '0'; + + ++value; + } + + rt_led_set_brightness(led, brightness); + + return size; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops _led_ops = +{ + .read = _led_read, + .write = _led_write, +}; +#endif + +static void _led_blink_timerout(void *param) +{ + struct rt_led_device *led = param; + struct blink_timer *btimer = led->sysdata; + + if (btimer->toggle) + { + led->ops->set_state(led, RT_LED_S_OFF); + } + else + { + led->ops->set_state(led, RT_LED_S_ON); + } + + btimer->toggle = !btimer->toggle; +} + +rt_err_t rt_hw_led_register(struct rt_led_device *led) +{ + rt_err_t err; + int device_id; + const char *dev_name; + struct blink_timer *btimer = RT_NULL; + + if (!led || !led->ops) + { + return -RT_EINVAL; + } + + if ((device_id = rt_dm_ida_alloc(&led_ida)) < 0) + { + return -RT_EFULL; + } + + rt_dm_dev_set_name(&led->parent, "led%u", device_id); + dev_name = rt_dm_dev_get_name(&led->parent); + + led->sysdata = RT_NULL; + rt_spin_lock_init(&led->spinlock); + + if (!led->ops->set_period && led->ops->set_state) + { + btimer = rt_malloc(sizeof(*btimer)); + + if (!btimer) + { + LOG_E("%s create blink timer failed", dev_name); + + err = -RT_ENOMEM; + goto _fail; + } + + led->sysdata = btimer; + + btimer->toggle = RT_FALSE; + btimer->enabled = RT_FALSE; + rt_timer_init(&btimer->timer, dev_name, _led_blink_timerout, led, + rt_tick_from_millisecond(500), RT_TIMER_FLAG_PERIODIC); + } + + led->parent.type = RT_Device_Class_Char; +#ifdef RT_USING_DEVICE_OPS + led->parent.ops = &_led_ops; +#else + led->parent.read = _led_read; + led->parent.write = _led_write; +#endif + led->parent.master_id = led_ida.master_id; + led->parent.device_id = device_id; + + if ((err = rt_device_register(&led->parent, dev_name, RT_DEVICE_FLAG_RDWR))) + { + goto _fail; + } + + return RT_EOK; + +_fail: + rt_dm_ida_free(&led_ida, device_id); + + if (btimer) + { + rt_timer_detach(&btimer->timer); + rt_free(btimer); + + led->sysdata = RT_NULL; + } + + return err; +} + +rt_err_t rt_hw_led_unregister(struct rt_led_device *led) +{ + if (!led) + { + return -RT_EINVAL; + } + + rt_led_set_state(led, RT_LED_S_OFF); + + if (led->sysdata) + { + struct blink_timer *btimer = led->sysdata; + + rt_timer_detach(&btimer->timer); + + rt_free(btimer); + } + + rt_dm_ida_free(&led_ida, led->parent.device_id); + + rt_device_unregister(&led->parent); + + return RT_EOK; +} + +rt_err_t rt_led_set_state(struct rt_led_device *led, enum rt_led_state state) +{ + rt_err_t err; + struct blink_timer *btimer; + + if (!led) + { + return -RT_EINVAL; + } + + if (!led->ops->set_state) + { + return -RT_ENOSYS; + } + + rt_spin_lock(&led->spinlock); + + btimer = led->sysdata; + + if (btimer && btimer->enabled) + { + rt_timer_stop(&btimer->timer); + } + + err = led->ops->set_state(led, state); + + if (state == RT_LED_S_BLINK) + { + if (err == -RT_ENOSYS && btimer && !btimer->enabled) + { + btimer->enabled = RT_TRUE; + rt_timer_start(&btimer->timer); + } + } + else if (btimer && btimer->enabled) + { + if (err) + { + rt_timer_start(&btimer->timer); + } + else + { + btimer->enabled = RT_FALSE; + } + } + + rt_spin_unlock(&led->spinlock); + + return err; +} + +rt_err_t rt_led_get_state(struct rt_led_device *led, enum rt_led_state *out_state) +{ + rt_err_t err; + + if (!led || !out_state) + { + return -RT_EINVAL; + } + + if (!led->ops->get_state) + { + return -RT_ENOSYS; + } + + rt_spin_lock(&led->spinlock); + + err = led->ops->get_state(led, out_state); + + rt_spin_unlock(&led->spinlock); + + return err; +} + +rt_err_t rt_led_set_period(struct rt_led_device *led, rt_uint32_t period_ms) +{ + rt_err_t err; + + if (!led) + { + return -RT_EINVAL; + } + + if (!led->ops->set_period && !led->sysdata) + { + return -RT_ENOSYS; + } + + rt_spin_lock(&led->spinlock); + + if (led->ops->set_period) + { + err = led->ops->set_period(led, period_ms); + } + else + { + struct blink_timer *btimer = led->sysdata; + rt_tick_t tick = rt_tick_from_millisecond(period_ms); + + err = rt_timer_control(&btimer->timer, RT_TIMER_CTRL_SET_TIME, &tick); + } + + rt_spin_unlock(&led->spinlock); + + return err; +} + +rt_err_t rt_led_set_brightness(struct rt_led_device *led, rt_uint32_t brightness) +{ + rt_err_t err; + + if (!led) + { + return -RT_EINVAL; + } + + if (!led->ops->set_brightness) + { + return -RT_ENOSYS; + } + + rt_spin_lock(&led->spinlock); + + err = led->ops->set_brightness(led, brightness); + + rt_spin_unlock(&led->spinlock); + + return err; +} diff --git a/rt-thread/components/drivers/mailbox/Kconfig b/rt-thread/components/drivers/mailbox/Kconfig new file mode 100644 index 0000000..9531d3a --- /dev/null +++ b/rt-thread/components/drivers/mailbox/Kconfig @@ -0,0 +1,14 @@ +menuconfig RT_USING_MBOX + bool "Using Hardware Mailbox device drivers" + depends on RT_USING_DM + depends on RT_USING_OFW + default n + +config RT_MBOX_PIC + bool "RT-Thread PIC Mailbox" + depends on RT_USING_MBOX + default y + +if RT_USING_MBOX + osource "$(SOC_DM_MBOX_DIR)/Kconfig" +endif diff --git a/rt-thread/components/drivers/mailbox/SConscript b/rt-thread/components/drivers/mailbox/SConscript new file mode 100644 index 0000000..f26a44b --- /dev/null +++ b/rt-thread/components/drivers/mailbox/SConscript @@ -0,0 +1,18 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_MBOX']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] + +src = ['mailbox.c'] + +if GetDepend(['RT_MBOX_PIC']): + src += ['mailbox-pic.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/mailbox/mailbox-pic.c b/rt-thread/components/drivers/mailbox/mailbox-pic.c new file mode 100644 index 0000000..dbc90f0 --- /dev/null +++ b/rt-thread/components/drivers/mailbox/mailbox-pic.c @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#include +#include + +#define DBG_TAG "mailbox.pic" +#define DBG_LVL DBG_INFO +#include + +/* + * RT-Thread PIC Mailbox device driver + * + * The mailbox device(s) may be instantiated in one of three equivalent way: + * + * Device Tree node, eg.: + * + * interrupt-controller@0 { + * interrupt-controller; + * #interrupt-cells = <1>; + * }; + * + * pic_mailbox@10000 { + * compatible = "rt-thread,pic-mailbox"; + * reg = <0x10000 0x100>; + * position = <0>; + * interrupts = <34>; + * peer-interrupts = <35>; + * uid = <0>; + * #mbox-cells = <1>; + * }; + */ + +#define MAILBOX_IMASK 0x00 +#define MAILBOX_ISTATE 0x04 +#define MAILBOX_MSG(n) (0x08 + (n) * 4) + +struct pic_mbox +{ + struct rt_mbox_controller parent; + + void *regs; + void *peer_regs; + + int position; + int chans_nr; + int irq; + int peer_hwirq; + struct rt_pic *pic; + + struct rt_spinlock lock; +}; + +#define raw_to_pic_mbox(raw) rt_container_of(raw, struct pic_mbox, parent) + +static rt_err_t pic_mbox_request(struct rt_mbox_chan *chan) +{ + int index = chan - chan->ctrl->chans; + struct pic_mbox *pic_mbox = raw_to_pic_mbox(chan->ctrl); + + HWREG32(pic_mbox->regs + MAILBOX_IMASK) &= ~RT_BIT(index); + HWREG32(pic_mbox->regs + MAILBOX_ISTATE) = 0; + + return RT_EOK; +} + +static void pic_mbox_release(struct rt_mbox_chan *chan) +{ + int index = chan - chan->ctrl->chans; + struct pic_mbox *pic_mbox = raw_to_pic_mbox(chan->ctrl); + + HWREG32(pic_mbox->regs + MAILBOX_IMASK) |= RT_BIT(index); +} + +static rt_err_t pic_mbox_send(struct rt_mbox_chan *chan, const void *data) +{ + rt_ubase_t level; + int index = chan - chan->ctrl->chans; + struct pic_mbox *pic_mbox = raw_to_pic_mbox(chan->ctrl); + + while (HWREG32(pic_mbox->peer_regs + MAILBOX_ISTATE) & RT_BIT(index)) + { + rt_thread_yield(); + } + + if (HWREG32(pic_mbox->peer_regs + MAILBOX_IMASK) & RT_BIT(index)) + { + return -RT_ERROR; + } + + level = rt_spin_lock_irqsave(&pic_mbox->lock); + + HWREG32(pic_mbox->regs + MAILBOX_MSG(index)) = *(rt_uint32_t *)data; + HWREG32(pic_mbox->peer_regs + MAILBOX_ISTATE) |= RT_BIT(index); + rt_hw_wmb(); + + rt_pic_irq_set_state_raw(pic_mbox->pic, pic_mbox->peer_hwirq, + RT_IRQ_STATE_PENDING, RT_TRUE); + + rt_spin_unlock_irqrestore(&pic_mbox->lock, level); + + return RT_EOK; +} + +static const struct rt_mbox_controller_ops pic_mbox_ops = +{ + .request = pic_mbox_request, + .release = pic_mbox_release, + .send = pic_mbox_send, +}; + +static void pic_mbox_isr(int irqno, void *param) +{ + rt_uint32_t isr; + struct pic_mbox *pic_mbox = param; + + isr = HWREG32(pic_mbox->regs + MAILBOX_ISTATE); + + for (int idx = 0; idx < 32; ++idx) + { + rt_uint32_t msg; + + if (!(RT_BIT(idx) & isr)) + { + continue; + } + + rt_hw_rmb(); + msg = HWREG32(pic_mbox->peer_regs + MAILBOX_MSG(idx)); + + rt_mbox_recv(&pic_mbox->parent.chans[idx], &msg); + } + + HWREG32(pic_mbox->regs + MAILBOX_ISTATE) &= ~isr; +} + +static void pic_mbox_free_resource(struct pic_mbox *pic_mbox) +{ + if (pic_mbox->regs && pic_mbox->peer_regs) + { + if (pic_mbox->peer_regs > pic_mbox->regs) + { + rt_iounmap(pic_mbox->regs); + } + else + { + rt_iounmap(pic_mbox->peer_regs); + } + } + + rt_free(pic_mbox); +} + +static rt_err_t pic_mbox_probe(struct rt_platform_device *pdev) +{ + rt_err_t err; + rt_uint64_t size; + rt_uint32_t value; + char dev_name[RT_NAME_MAX]; + struct rt_ofw_node *pic_np; + struct rt_device *dev = &pdev->parent; + struct pic_mbox *pic_mbox = rt_calloc(1, sizeof(*pic_mbox)); + + if (!pic_mbox) + { + return -RT_ENOMEM; + } + + if ((err = rt_dm_dev_get_address(dev, 0, RT_NULL, &size))) + { + goto _fail; + } + + if ((err = rt_dm_dev_prop_read_u32(dev, "position", &value))) + { + goto _fail; + } + + if (!value) + { + pic_mbox->regs = rt_dm_dev_iomap(dev, 0); + + if (!pic_mbox->regs) + { + goto _fail; + } + + pic_mbox->peer_regs = pic_mbox->regs + size / 2; + + /* Init by the captain */ + HWREG32(pic_mbox->regs + MAILBOX_IMASK) = 0xffffffff; + HWREG32(pic_mbox->regs + MAILBOX_ISTATE) = 0; + HWREG32(pic_mbox->peer_regs + MAILBOX_IMASK) = 0xffffffff; + HWREG32(pic_mbox->peer_regs + MAILBOX_ISTATE) = 0; + } + else + { + pic_mbox->peer_regs = rt_dm_dev_iomap(dev, 0); + + if (!pic_mbox->peer_regs) + { + goto _fail; + } + + pic_mbox->regs = pic_mbox->peer_regs + size / 2; + } + + pic_mbox->irq = rt_dm_dev_get_irq(dev, 0); + + if (pic_mbox->irq < 0) + { + err = pic_mbox->irq; + + goto _fail; + } + + if ((err = rt_dm_dev_prop_read_u32(dev, "peer-interrupts", &value))) + { + goto _fail; + } + pic_mbox->peer_hwirq = value; + + if ((err = rt_dm_dev_prop_read_u32(dev, "uid", &value))) + { + goto _fail; + } + + if (!(pic_np = rt_ofw_find_irq_parent(dev->ofw_node, RT_NULL))) + { + goto _fail; + } + pic_mbox->pic = rt_ofw_data(pic_np); + rt_ofw_node_put(pic_np); + + rt_spin_lock_init(&pic_mbox->lock); + + pic_mbox->parent.dev = dev; + pic_mbox->parent.num_chans = 32; + pic_mbox->parent.ops = &pic_mbox_ops; + + if ((err = rt_mbox_controller_register(&pic_mbox->parent))) + { + goto _fail; + } + + rt_snprintf(dev_name, sizeof(dev_name), "pic-mbox%d", value); + rt_hw_interrupt_install(pic_mbox->irq, pic_mbox_isr, pic_mbox, dev_name); + rt_hw_interrupt_umask(pic_mbox->irq); + + return RT_EOK; + +_fail: + pic_mbox_free_resource(pic_mbox); + + return err; +} + +static rt_err_t pic_mbox_remove(struct rt_platform_device *pdev) +{ + struct pic_mbox *pic_mbox = pdev->parent.user_data; + + rt_pic_detach_irq(pic_mbox->irq, pic_mbox); + + rt_mbox_controller_unregister(&pic_mbox->parent); + + pic_mbox_free_resource(pic_mbox); + + return RT_EOK; +} + +static const struct rt_ofw_node_id pic_mbox_ofw_ids[] = +{ + { .compatible = "rt-thread,pic-mailbox" }, + { /* sentinel */ } +}; + +static struct rt_platform_driver pic_mbox_driver = +{ + .name = "mailbox-pic", + .ids = pic_mbox_ofw_ids, + + .probe = pic_mbox_probe, + .remove = pic_mbox_remove, +}; +RT_PLATFORM_DRIVER_EXPORT(pic_mbox_driver); diff --git a/rt-thread/components/drivers/mailbox/mailbox.c b/rt-thread/components/drivers/mailbox/mailbox.c new file mode 100644 index 0000000..5e94241 --- /dev/null +++ b/rt-thread/components/drivers/mailbox/mailbox.c @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#include +#include + +#define DBG_TAG "rtdm.mailbox" +#define DBG_LVL DBG_INFO +#include + +#include +#include +#include +#include + +static struct rt_spinlock mbox_ops_lock = {}; +static rt_list_t mbox_nodes = RT_LIST_OBJECT_INIT(mbox_nodes); + +static void mbox_chan_timeout(void *param); + +rt_err_t rt_mbox_controller_register(struct rt_mbox_controller *ctrl) +{ + int len; + struct rt_mbox_chan *chan; + char timer_name[RT_NAME_MAX]; + + if (!ctrl || !ctrl->dev || !ctrl->ops || !ctrl->num_chans) + { + return -RT_EINVAL; + } + + ctrl->chans = rt_calloc(ctrl->num_chans, sizeof(struct rt_mbox_chan)); + + if (!ctrl->chans) + { + return -RT_ENOMEM; + } + + len = rt_snprintf(timer_name, sizeof(timer_name), "%s-", + rt_dm_dev_get_name(ctrl->dev)); + + RT_ASSERT(len < sizeof(timer_name)); + + chan = &ctrl->chans[0]; + + for (int i = 0; i < ctrl->num_chans; ++i, ++chan) + { + chan->ctrl = ctrl; + rt_spin_lock_init(&chan->lock); + + rt_snprintf(&timer_name[len], sizeof(timer_name) - len, "%d", i); + rt_timer_init(&chan->timer, timer_name, mbox_chan_timeout, chan, + 0, RT_TIMER_FLAG_ONE_SHOT); + } + + rt_list_init(&ctrl->list); + rt_dm_dev_bind_fwdata(ctrl->dev, RT_NULL, ctrl); + + rt_spin_lock(&mbox_ops_lock); + + rt_list_insert_after(&mbox_nodes, &ctrl->list); + + rt_spin_unlock(&mbox_ops_lock); + + return RT_EOK; +} + +rt_err_t rt_mbox_controller_unregister(struct rt_mbox_controller *ctrl) +{ + struct rt_mbox_chan *chan; + + if (!ctrl) + { + return -RT_EINVAL; + } + + rt_spin_lock(&mbox_ops_lock); + + rt_dm_dev_unbind_fwdata(ctrl->dev, RT_NULL); + rt_list_remove(&ctrl->list); + + rt_spin_unlock(&mbox_ops_lock); + + chan = &ctrl->chans[0]; + + for (int i = ctrl->num_chans - 1; i >= 0; --i, ++chan) + { + rt_mbox_release(&ctrl->chans[i]); + } + + rt_free(ctrl->chans); + + return RT_EOK; +} + +rt_err_t rt_mbox_send(struct rt_mbox_chan *chan, const void *data, + rt_uint32_t timeout_ms) +{ + rt_err_t err; + rt_ubase_t level; + rt_bool_t timer_go = RT_FALSE; + struct rt_mbox_client *client; + struct rt_mbox_controller *ctrl; + + if (!chan || !data) + { + return -RT_EINVAL; + } + + ctrl = chan->ctrl; + client = chan->client; + + level = rt_spin_lock_irqsave(&chan->lock); + + if (client->tx_prepare) + { + client->tx_prepare(client, data); + } + + chan->complete = RT_FALSE; + err = ctrl->ops->send(chan, data); + + if (!err) + { + chan->data = (void *)data; + + if (timeout_ms != RT_WAITING_FOREVER) + { + rt_tick_t tick = rt_tick_from_millisecond(timeout_ms); + + rt_timer_control(&chan->timer, RT_TIMER_CTRL_SET_TIME, &tick); + + timer_go = RT_TRUE; + } + } + else + { + chan->complete = RT_TRUE; + } + + rt_spin_unlock_irqrestore(&chan->lock, level); + + if (timer_go) + { + rt_timer_start(&chan->timer); + } + + return err; +} + +void rt_mbox_send_done(struct rt_mbox_chan *chan, rt_err_t err) +{ + void *data; + rt_ubase_t level; + + level = rt_spin_lock_irqsave(&chan->lock); + + data = chan->data; + chan->data = RT_NULL; + + rt_spin_unlock_irqrestore(&chan->lock, level); + + if (chan->client->tx_done) + { + chan->client->tx_done(chan->client, data, err); + } + + chan->complete = RT_TRUE; +} + +static void mbox_chan_timeout(void *param) +{ + rt_err_t err = RT_EOK; + struct rt_mbox_chan *chan = param; + + if (!chan->complete) + { + err = -RT_ETIMEOUT; + } + + rt_mbox_send_done(chan, err); +} + +rt_bool_t rt_mbox_peek(struct rt_mbox_chan *chan) +{ + if (chan && chan->ctrl->ops->peek) + { + return chan->ctrl->ops->peek(chan); + } + + return RT_FALSE; +} + +rt_err_t rt_mbox_recv(struct rt_mbox_chan *chan, void *data) +{ + if (!chan || !data) + { + return -RT_EINVAL; + } + + if (chan->client->rx_callback) + { + chan->client->rx_callback(chan->client, data); + } + + return RT_EOK; +} + +static int mbox_controller_ofw_parse_default(struct rt_mbox_controller *ctrl, + struct rt_ofw_cell_args *args) +{ + if (args->args_count != 1) + { + return -RT_EINVAL; + } + + return args->args[0]; +} + +struct rt_mbox_chan *rt_mbox_request_by_index(struct rt_mbox_client *client, int index) +{ + rt_err_t err; + struct rt_ofw_cell_args args; + struct rt_ofw_node *np, *ctrl_np; + struct rt_mbox_controller *ctrl; + struct rt_mbox_chan *chan = RT_NULL; + + if (!client && index < 0) + { + return rt_err_ptr(-RT_EINVAL); + } + + np = client->dev->ofw_node; + + rt_spin_lock(&mbox_ops_lock); + + err = rt_ofw_parse_phandle_cells(np, "mboxes", "#mbox-cells", index, &args); + + if (err) + { + chan = rt_err_ptr(err); + goto _out_lock; + } + + ctrl_np = args.data; + + if (!rt_ofw_data(ctrl_np)) + { + rt_spin_unlock(&mbox_ops_lock); + + rt_platform_ofw_request(ctrl_np); + + rt_spin_lock(&mbox_ops_lock); + } + + ctrl = rt_ofw_data(ctrl_np); + rt_ofw_node_put(ctrl_np); + + if (ctrl) + { + int index; + + if (ctrl->ops->ofw_parse) + { + index = ctrl->ops->ofw_parse(ctrl, &args); + } + else + { + index = mbox_controller_ofw_parse_default(ctrl, &args); + } + + if (index >= 0) + { + chan = &ctrl->chans[index]; + } + else + { + LOG_E("Parse chan from %s error = %s", + rt_dm_dev_get_name(ctrl->dev), rt_strerror(index)); + + chan = rt_err_ptr(index); + goto _out_lock; + } + + if (ctrl->ops->request) + { + rt_err_t err = ctrl->ops->request(chan); + + if (err) + { + LOG_E("Request chan[%d] from %s error = %s", + index, rt_dm_dev_get_name(ctrl->dev), rt_strerror(err)); + + rt_mbox_release(chan); + chan = rt_err_ptr(err); + } + } + + chan->client = client; + } + else + { + chan = rt_err_ptr(-RT_ENOSYS); + } + +_out_lock: + rt_spin_unlock(&mbox_ops_lock); + + return chan; +} + +struct rt_mbox_chan *rt_mbox_request_by_name(struct rt_mbox_client *client, char *name) +{ + int index; + struct rt_ofw_node *np; + + if (!client || !name) + { + return rt_err_ptr(-RT_EINVAL); + } + + np = client->dev->ofw_node; + index = rt_ofw_prop_index_of_string(np, "mbox-names", name); + + if (index < 0) + { + return RT_NULL; + } + + return rt_mbox_request_by_index(client, index); +} + +rt_err_t rt_mbox_release(struct rt_mbox_chan *chan) +{ + if (chan) + { + chan->ctrl->ops->release(chan); + } + else + { + return -RT_EINVAL; + } + + return RT_EOK; +} diff --git a/rt-thread/components/drivers/mfd/Kconfig b/rt-thread/components/drivers/mfd/Kconfig new file mode 100644 index 0000000..0b12ca4 --- /dev/null +++ b/rt-thread/components/drivers/mfd/Kconfig @@ -0,0 +1,10 @@ +menuconfig RT_USING_MFD + bool "Using Multifunction device drivers" + depends on RT_USING_DM + default n + +config RT_MFD_SYSCON + bool "System Controller Register R/W" + depends on RT_USING_MFD + depends on RT_USING_OFW + default y diff --git a/rt-thread/components/drivers/mfd/SConscript b/rt-thread/components/drivers/mfd/SConscript new file mode 100644 index 0000000..f952f68 --- /dev/null +++ b/rt-thread/components/drivers/mfd/SConscript @@ -0,0 +1,17 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_MFD']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] +src = [] + +if GetDepend(['RT_MFD_SYSCON']): + src += ['mfd-syscon.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/mfd/mfd-syscon.c b/rt-thread/components/drivers/mfd/mfd-syscon.c new file mode 100644 index 0000000..1778906 --- /dev/null +++ b/rt-thread/components/drivers/mfd/mfd-syscon.c @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include + +#include +#include +#include +#include +#include + +static struct rt_spinlock _syscon_nodes_lock = { 0 }; +static rt_list_t _syscon_nodes = RT_LIST_OBJECT_INIT(_syscon_nodes); + +rt_err_t rt_syscon_read(struct rt_syscon *syscon, rt_off_t offset, rt_uint32_t *out_val) +{ + if (offset < syscon->iomem_size) + { + rt_ubase_t level = rt_spin_lock_irqsave(&syscon->rw_lock); + + *out_val = HWREG32(syscon->iomem_base + offset); + + rt_spin_unlock_irqrestore(&syscon->rw_lock, level); + + return RT_EOK; + } + else + { + return -RT_EINVAL; + } +} + +rt_err_t rt_syscon_write(struct rt_syscon *syscon, rt_off_t offset, rt_uint32_t val) +{ + if (offset < syscon->iomem_size) + { + rt_ubase_t level = rt_spin_lock_irqsave(&syscon->rw_lock); + + HWREG32(syscon->iomem_base + offset) = val; + + rt_spin_unlock_irqrestore(&syscon->rw_lock, level); + + return RT_EOK; + } + else + { + return -RT_EINVAL; + } +} + +rt_err_t rt_syscon_update_bits(struct rt_syscon *syscon, rt_off_t offset, rt_uint32_t mask, rt_uint32_t val) +{ + rt_err_t err; + rt_ubase_t level = rt_spin_lock_irqsave(&syscon->rw_lock); + + if (offset < syscon->iomem_size) + { + rt_uint32_t old_val = HWREG32(syscon->iomem_base + offset); + + old_val &= ~mask; + + HWREG32(syscon->iomem_base + offset) = old_val | val; + + err = RT_EOK; + } + else + { + err = -RT_EINVAL; + } + + rt_spin_unlock_irqrestore(&syscon->rw_lock, level); + + return err; +} + +static rt_err_t syscon_probe(struct rt_platform_device *pdev); + +struct rt_syscon *rt_syscon_find_by_ofw_node(struct rt_ofw_node *np) +{ + rt_ubase_t level; + struct rt_syscon *syscon = RT_NULL, *syscon_tmp; + struct rt_platform_device syscon_pdev; + + if (!np) + { + goto _exit; + } + + level = rt_spin_lock_irqsave(&_syscon_nodes_lock); + + /* ofw_data is not safety */ + rt_list_for_each_entry(syscon_tmp, &_syscon_nodes, list) + { + if (syscon_tmp->np == np) + { + syscon = syscon_tmp; + break; + } + } + + rt_spin_unlock_irqrestore(&_syscon_nodes_lock, level); + + if (syscon) + { + goto _exit; + } + + /* Not found, try probe this node */ + if (!rt_ofw_node_is_compatible(np, "syscon") && + !rt_ofw_node_is_compatible(np, "simple-mfd")) + { + goto _exit; + } + + syscon_pdev.parent.ofw_node = np; + + if (!syscon_probe(&syscon_pdev)) + { + syscon = rt_ofw_data(np); + } + +_exit: + return syscon; +} + +struct rt_syscon *rt_syscon_find_by_ofw_compatible(const char *compatible) +{ + struct rt_syscon *syscon = RT_NULL; + struct rt_ofw_node *syscon_np = rt_ofw_find_node_by_compatible(RT_NULL, compatible); + + if (syscon_np) + { + syscon = rt_syscon_find_by_ofw_node(syscon_np); + + rt_ofw_node_put(syscon_np); + } + + return syscon; +} + +struct rt_syscon *rt_syscon_find_by_ofw_phandle(struct rt_ofw_node *np, const char *propname) +{ + struct rt_syscon *syscon = RT_NULL; + struct rt_ofw_node *syscon_np = rt_ofw_parse_phandle(np, propname, 0); + + if (syscon_np) + { + syscon = rt_syscon_find_by_ofw_node(syscon_np); + + rt_ofw_node_put(syscon_np); + } + + return syscon; +} + +static rt_err_t syscon_probe(struct rt_platform_device *pdev) +{ + rt_err_t err; + rt_ubase_t level; + struct rt_ofw_node *np; + rt_uint64_t iomem_range[2]; + struct rt_syscon *syscon = rt_calloc(1, sizeof(*syscon)); + + if (!syscon) + { + return -RT_ENOMEM; + } + + np = pdev->parent.ofw_node; + + if ((err = rt_ofw_get_address(np, 0, &iomem_range[0], &iomem_range[1]))) + { + goto _fail; + } + + syscon->iomem_size = (rt_size_t)iomem_range[1]; + syscon->iomem_base = rt_ioremap((void *)iomem_range[0], syscon->iomem_size); + + if (!syscon->iomem_base) + { + goto _fail; + } + + rt_list_init(&syscon->list); + level = rt_spin_lock_irqsave(&_syscon_nodes_lock); + rt_list_insert_after(&_syscon_nodes, &syscon->list); + rt_spin_unlock_irqrestore(&_syscon_nodes_lock, level); + + rt_spin_lock_init(&syscon->rw_lock); + + pdev->parent.user_data = syscon; + + syscon->np = pdev->parent.ofw_node; + rt_ofw_data(np) = syscon; + + return RT_EOK; + +_fail: + rt_free(syscon); + + return err; +} + +static rt_err_t syscon_remove(struct rt_platform_device *pdev) +{ + struct rt_syscon *syscon = pdev->parent.user_data; + + rt_iounmap(syscon->iomem_base); + + rt_free(syscon); + + return RT_EOK; +} + +static const struct rt_ofw_node_id syscon_ofw_ids[] = +{ + { .compatible = "syscon" }, + { /* sentinel */ } +}; + +static struct rt_platform_driver syscon_driver = +{ + .name = "mfd-syscon", + .ids = syscon_ofw_ids, + + .probe = syscon_probe, + .remove = syscon_remove, +}; + +static int syscon_drv_register(void) +{ + rt_platform_driver_register(&syscon_driver); + + return 0; +} +INIT_SUBSYS_EXPORT(syscon_drv_register); diff --git a/rt-thread/components/drivers/misc/rt_random.c b/rt-thread/components/drivers/misc/rt_random.c index da6b312..9f4be20 100644 --- a/rt-thread/components/drivers/misc/rt_random.c +++ b/rt-thread/components/drivers/misc/rt_random.c @@ -46,7 +46,7 @@ static rt_ssize_t random_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_si static rt_ssize_t random_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) { - ssize_t ret = sizeof(seed); + ssize_t ret = sizeof(seed) < size ? sizeof(seed) : size; rt_memcpy(&seed, buffer, ret); return ret; } @@ -137,7 +137,7 @@ static rt_ssize_t random_uread(rt_device_t dev, rt_off_t pos, void *buffer, rt_s static rt_ssize_t random_uwrite(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) { - ssize_t ret = sizeof(useed); + ssize_t ret = sizeof(useed) < size ? sizeof(useed) : size; rt_memcpy(&useed, buffer, ret); return ret; } diff --git a/rt-thread/components/drivers/nvme/Kconfig b/rt-thread/components/drivers/nvme/Kconfig new file mode 100644 index 0000000..83c731c --- /dev/null +++ b/rt-thread/components/drivers/nvme/Kconfig @@ -0,0 +1,23 @@ +menuconfig RT_USING_NVME + bool "Using Non-Volatile Memory Express (NVME) device drivers" + depends on RT_USING_DM + depends on RT_USING_BLK + depends on RT_USING_DMA + default n + +config RT_USING_NVME_IO_QUEUE + int "Number of I/O Command queue" + depends on RT_USING_NVME + default 2 if RT_THREAD_PRIORITY_8 + default 4 if RT_THREAD_PRIORITY_32 + default 8 if RT_THREAD_PRIORITY_256 + +config RT_NVME_PCI + bool "NVME support on PCI bus" + depends on RT_USING_NVME + depends on RT_USING_PCI + default y + +if RT_USING_NVME + osource "$(SOC_DM_NVME_DIR)/Kconfig" +endif diff --git a/rt-thread/components/drivers/nvme/SConscript b/rt-thread/components/drivers/nvme/SConscript new file mode 100644 index 0000000..6fc699b --- /dev/null +++ b/rt-thread/components/drivers/nvme/SConscript @@ -0,0 +1,18 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_NVME']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] + +src = ['nvme.c'] + +if GetDepend(['RT_NVME_PCI']): + src += ['nvme-pci.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/nvme/nvme-pci.c b/rt-thread/components/drivers/nvme/nvme-pci.c new file mode 100644 index 0000000..d73260f --- /dev/null +++ b/rt-thread/components/drivers/nvme/nvme-pci.c @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include + +#define NVME_REG_BAR 0 + +struct pci_nvme_quirk +{ + const struct rt_nvme_ops *ops; +}; + +struct pci_nvme_controller +{ + struct rt_nvme_controller parent; + const struct pci_nvme_quirk *quirk; + + rt_bool_t is_msi; + struct rt_pci_msix_entry msix_entries[RT_USING_NVME_QUEUE]; +}; + +static const struct rt_nvme_ops pci_nvme_std_ops = +{ + .name = "PCI", +}; + +static rt_err_t pci_nvme_probe(struct rt_pci_device *pdev) +{ + rt_err_t err; + rt_ssize_t msi_nr; + struct rt_nvme_controller *nvme; + struct pci_nvme_controller *pci_nvme = rt_calloc(1, sizeof(*pci_nvme)); + const struct pci_nvme_quirk *quirk = pdev->id->data; + + if (!pci_nvme) + { + return -RT_ENOMEM; + } + + pci_nvme->quirk = quirk; + nvme = &pci_nvme->parent; + nvme->dev = &pdev->parent; + nvme->regs = rt_pci_iomap(pdev, NVME_REG_BAR); + + if (!nvme->regs) + { + err = -RT_EIO; + goto _fail; + } + + nvme->ops = quirk && quirk->ops ? quirk->ops : &pci_nvme_std_ops; + + if ((msi_nr = rt_pci_msix_vector_count(pdev)) <= 0) + { + msi_nr = rt_pci_msi_vector_count(pdev); + } + if (msi_nr > 0) + { + nvme->irqs_nr = RT_ARRAY_SIZE(pci_nvme->msix_entries); + nvme->irqs_nr = rt_min_t(rt_size_t, msi_nr, nvme->irqs_nr); + } + + if (nvme->irqs_nr > 0) + { + rt_pci_msix_entry_index_linear(pci_nvme->msix_entries, nvme->irqs_nr); + + if (rt_pci_msix_enable(pdev, pci_nvme->msix_entries, nvme->irqs_nr) > 0) + { + pci_nvme->is_msi = RT_TRUE; + + for (int i = 0; i < nvme->irqs_nr; ++i) + { + nvme->irqs[i] = pci_nvme->msix_entries[i].irq; + } + } + } + + if (!pci_nvme->is_msi) + { + nvme->irqs_nr = 1; + nvme->irqs[0] = pdev->irq; + rt_pci_irq_unmask(pdev); + } + + rt_pci_set_master(pdev); + + if ((err = rt_nvme_controller_register(nvme))) + { + goto _disable; + } + + pdev->parent.user_data = pci_nvme; + + return RT_EOK; + +_disable: + if (pci_nvme->is_msi) + { + rt_pci_msix_disable(pdev); + } + else + { + rt_pci_irq_mask(pdev); + } + rt_pci_clear_master(pdev); + rt_iounmap(nvme->regs); + +_fail: + rt_free(pci_nvme); + + return err; +} + +static rt_err_t pci_nvme_remove(struct rt_pci_device *pdev) +{ + struct rt_nvme_controller *nvme; + struct pci_nvme_controller *pci_nvme = pdev->parent.user_data; + + nvme = &pci_nvme->parent; + + rt_nvme_controller_unregister(nvme); + + if (pci_nvme->is_msi) + { + rt_pci_msix_disable(pdev); + } + else + { + /* INTx is shared, don't mask all */ + rt_hw_interrupt_umask(pdev->irq); + rt_pci_irq_mask(pdev); + } + + rt_pci_clear_master(pdev); + + rt_iounmap(nvme->regs); + rt_free(pci_nvme); + + return RT_EOK; +} + +static rt_err_t pci_nvme_shutdown(struct rt_pci_device *pdev) +{ + return pci_nvme_remove(pdev); +} + +static const struct rt_pci_device_id pci_nvme_ids[] = +{ + { RT_PCI_DEVICE_ID(PCI_VENDOR_ID_REDHAT, 0x0010) }, + { RT_PCI_DEVICE_CLASS(PCIS_STORAGE_EXPRESS, ~0) }, + { /* sentinel */ } +}; + +static struct rt_pci_driver pci_nvme_driver = +{ + .name = "nvme-pci", + + .ids = pci_nvme_ids, + .probe = pci_nvme_probe, + .remove = pci_nvme_remove, + .shutdown = pci_nvme_shutdown, +}; +RT_PCI_DRIVER_EXPORT(pci_nvme_driver); diff --git a/rt-thread/components/drivers/nvme/nvme.c b/rt-thread/components/drivers/nvme/nvme.c new file mode 100644 index 0000000..dc00714 --- /dev/null +++ b/rt-thread/components/drivers/nvme/nvme.c @@ -0,0 +1,1302 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "rtdm.nvme" +#define DBG_LVL DBG_INFO +#include + +static struct rt_dm_ida nvme_controller_ida = RT_DM_IDA_INIT(CUSTOM); +static struct rt_dm_ida nvme_ida = RT_DM_IDA_INIT(NVME); + +static struct rt_spinlock nvme_lock = {}; +static rt_list_t nvme_nodes = RT_LIST_OBJECT_INIT(nvme_nodes); + +rt_inline rt_uint32_t nvme_readl(struct rt_nvme_controller *nvme, int offset) +{ + return HWREG32(nvme->regs + offset); +} + +rt_inline void nvme_writel(struct rt_nvme_controller *nvme, int offset, rt_uint32_t value) +{ + HWREG32(nvme->regs + offset) = value; +} + +rt_inline rt_uint64_t nvme_readq(struct rt_nvme_controller *nvme, int offset) +{ + rt_uint32_t lo32, hi32; + + lo32 = HWREG32(nvme->regs + offset); + hi32 = HWREG32(nvme->regs + offset + 4); + + return ((rt_uint64_t)hi32 << 32) + lo32; +} + +rt_inline void nvme_writeq(struct rt_nvme_controller *nvme, int offset, rt_uint64_t value) +{ + nvme_writel(nvme, offset, (rt_uint32_t)(value & 0xffffffff)); + nvme_writel(nvme, offset + 4, (rt_uint32_t)(value >> 32)); +} + +static rt_err_t nvme_poll_csts(struct rt_nvme_controller *nvme, + rt_uint32_t mask, rt_uint32_t value) +{ + rt_tick_t timeout; + + timeout = rt_tick_from_millisecond(RT_NVME_CAP_TIMEOUT(nvme->cap) * 500); + timeout += rt_tick_get(); + + do { + if ((nvme_readl(nvme, RT_NVME_REG_CSTS) & mask) == value) + { + return RT_EOK; + } + + rt_hw_cpu_relax(); + } while (rt_tick_get() < timeout); + + return -RT_ETIMEOUT; +} + +static rt_err_t nvme_enable_ctrl(struct rt_nvme_controller *nvme) +{ + nvme->ctrl_config &= ~RT_NVME_CC_SHN_MASK; + nvme->ctrl_config |= RT_NVME_CC_ENABLE; + nvme_writel(nvme, RT_NVME_REG_CC, nvme->ctrl_config); + + return nvme_poll_csts(nvme, RT_NVME_CSTS_RDY, RT_NVME_CSTS_RDY); +} + +static rt_err_t nvme_disable_ctrl(struct rt_nvme_controller *nvme) +{ + nvme->ctrl_config &= ~RT_NVME_CC_SHN_MASK; + nvme->ctrl_config &= ~RT_NVME_CC_ENABLE; + nvme_writel(nvme, RT_NVME_REG_CC, nvme->ctrl_config); + + return nvme_poll_csts(nvme, RT_NVME_CSTS_RDY, 0); +} + +static rt_err_t nvme_shutdown_ctrl(struct rt_nvme_controller *nvme) +{ + nvme->ctrl_config &= ~RT_NVME_CC_SHN_MASK; + nvme->ctrl_config |= RT_NVME_CC_SHN_NORMAL; + nvme_writel(nvme, RT_NVME_REG_CC, nvme->ctrl_config); + + return nvme_poll_csts(nvme, RT_NVME_CSTS_SHST_MASK, RT_NVME_CSTS_SHST_CMPLT); +} + +rt_inline rt_le16_t nvme_next_cmdid(struct rt_nvme_controller *nvme) +{ + return rt_cpu_to_le16((rt_uint16_t)rt_atomic_add(&nvme->cmdid, 1)); +} + +static rt_err_t nvme_submit_cmd(struct rt_nvme_queue *queue, + struct rt_nvme_command *cmd) +{ + rt_ubase_t level; + rt_err_t err = RT_EOK; + rt_uint16_t tail, head; + struct rt_nvme_controller *nvme = queue->nvme; + +_retry: + level = rt_spin_lock_irqsave(&queue->lock); + + tail = queue->sq_tail; + head = queue->cq_head; + + if (tail + 1 == head) + { + /* IO queue is full, waiting for the last IO command to complete. */ + rt_spin_unlock_irqrestore(&queue->lock, level); + + rt_thread_yield(); + + goto _retry; + } + + cmd->common.cmdid = nvme_next_cmdid(nvme); + rt_memcpy(&queue->sq_cmds[tail], cmd, sizeof(*cmd)); + + if (nvme->ops->submit_cmd) + { + if ((err = nvme->ops->submit_cmd(queue, cmd))) + { + return err; + } + } + + if (++tail == queue->depth) + { + tail = 0; + } + HWREG32(queue->doorbell) = tail; + queue->sq_tail = tail; + + queue->cmd = cmd; + queue->err = RT_EOK; + + rt_spin_unlock_irqrestore(&queue->lock, level); + + err = rt_completion_wait(&queue->done, + rt_tick_from_millisecond(queue->qid != 0 ? RT_WAITING_FOREVER : 60)); + + return err ? : queue->err; +} + +static rt_err_t nvme_set_features_simple(struct rt_nvme_controller *nvme, + rt_uint32_t fid, rt_uint32_t dword11) +{ + struct rt_nvme_command cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.features.opcode = RT_NVME_ADMIN_OPCODE_SET_FEATURES; + cmd.features.fid = rt_cpu_to_le32(fid); + cmd.features.dword11 = rt_cpu_to_le32(dword11); + + return nvme_submit_cmd(&nvme->admin_queue, &cmd); +} + +static rt_err_t nvme_submit_io_cmd(struct rt_nvme_controller *nvme, + struct rt_nvme_command *cmd) +{ + rt_uint16_t qid; + + qid = rt_atomic_add(&nvme->ioqid[rt_hw_cpu_id()], RT_CPUS_NR); + qid %= nvme->io_queue_max; + + return nvme_submit_cmd(&nvme->io_queues[qid], cmd); +} + +/* + * PRP Mode: + * + * |63 n+1|n 0| + * +----------------------------------------+----------+---+---+ + * | Page Base Address | Offset | 0 | 0 | + * +----------------------------------------+----------+---+---+ + * | + * v + * Host Physical Pages + * +----------------------------+ + * +--------------+----------+ | Page k | + * | PRP Entry1 | Offset +---------->+----------------------------+ + * +--------------+----------+ | Page k + 1 | + * +----------------------------+ + * ... + * +----------------------------+ + * +--------------+----------+ | Page k + m | + * | PRP Entry2 | 0 +---------->+----------------------------+ + * +--------------+----------+ | Page k + m + 1 | + * +----------------------------+ + * PRP List (In PRP Entry2): + * + * |63 n+1|n 0| + * +----------------------------------------+------------------+ + * | Page Base Address k | 0h | + * +----------------------------------------+------------------+ + * | Page Base Address k + 1 | 0h | + * +----------------------------------------+------------------+ + * | ... | + * +----------------------------------------+------------------+ + * | Page Base Address k + m | 0h | + * +----------------------------------------+------------------+ + * | Page Base Address k + m + 1 | 0h | + * +----------------------------------------+------------------+ + * + * SGL Mode: + * +----- Non-transport + * LBA / + * +---------------+---------------+-------/-------+---------------+ + * | 3KB | 4KB | 2KB | 4KB | + * +-------+-------+-------+-------+---------------+--------+------+ + * | +-------------------------+ | + * | | | + * | +--------------------|------+ + * | | | + * +-------v-------+ +-------v-------+ +-------v-------+ + * | A MEM BLOCK | | B MEM BLOCK | | C MEM BLOCK | + * +-------^-------+ +-------^-------+ +-------^-------+ + * | | | + * +----------------+ | | + * | | | + * Segment(0) | | | + * +----------+----------+ | | | + * | Address: A +--+ | | + * +----------+----------+ | | + * | Type: 0h | Len: 3KB | | | + * +----------+----------+ | | + * | Address: Segment(1) +--+ | | + * +----------+----------+ | | | + * | Type: 2h | Len: 48 | | | | + * +----------+----------+ | | | + * | | | + * +------------------------+ | | + * | | | + * v | | + * Segment(1) | | + * +----------+----------+ | | + * | Address: B +------+ | + * +----------+----------+ | + * | Type: 0h | Len: 4KB | | + * +----------+----------+ | + * | Address: | | + * +----------+----------+ | + * | Type: 1h | Len: 2KB | | + * +----------+----------+ | + * | Address: Segment(2) +--+ | + * +----------+----------+ | | + * | Type: 0h | Len: 16 | | | + * +----------+----------+ | | + * | | + * +------------------------+ | + * | | + * v | + * Segment(2) | + * +----------+----------+ | + * | Address: C +---------------------------+ + * +----------+----------+ + * | Type: 0h | Len: 4KB | + * +----------+----------+ + */ + +static rt_ssize_t nvme_blk_rw(struct rt_nvme_device *ndev, rt_off_t slba, + rt_ubase_t buffer_dma, rt_size_t lbas, rt_uint8_t opcode) +{ + rt_err_t err; + rt_uint16_t max_lbas; + rt_uint32_t lba_shift; + rt_size_t tlbas; + rt_ssize_t data_length; + struct rt_nvme_command cmd; + struct rt_nvme_controller *nvme = ndev->ctrl; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.rw.opcode = opcode; + cmd.rw.flags = nvme->sgl_mode << RT_NVME_CMD_FLAGS_PSDT_SHIFT; + cmd.rw.nsid = rt_cpu_to_le32(ndev->nsid); + + tlbas = lbas; + lba_shift = ndev->lba_shift; + max_lbas = 1 << (nvme->max_transfer_shift - lba_shift); + + if (nvme->sgl_mode) + { + while ((rt_ssize_t)lbas > 0) + { + if (lbas < max_lbas) + { + max_lbas = (rt_uint16_t)lbas; + } + + data_length = max_lbas << lba_shift; + + cmd.rw.sgl.adddress = rt_cpu_to_le64(buffer_dma); + cmd.rw.sgl.length = rt_cpu_to_le32(data_length); + cmd.rw.sgl.sgl_identify = SGL_DESC_TYPE_DATA_BLOCK; + cmd.rw.slba = rt_cpu_to_le16(slba); + cmd.rw.length = rt_cpu_to_le16(max_lbas - 1); + + if ((err = nvme_submit_io_cmd(nvme, &cmd))) + { + tlbas -= lbas; + break; + } + + lbas -= max_lbas; + slba += max_lbas; + buffer_dma += data_length; + } + } + else + { + void *prp_list = RT_NULL; + rt_size_t prp_list_size = 0, page_size; + + page_size = nvme->page_size; + + while ((rt_ssize_t)lbas > 0) + { + rt_uint64_t prp2_addr, dma_addr; + rt_ssize_t remain_length, page_offset; + + if (lbas < max_lbas) + { + max_lbas = (rt_uint16_t)lbas; + } + + /* + * PRP transfer: + * 1. data_length <= 4KB: + * prp1 = buffer_dma + * prp2 = 0 + * + * 2. 4KB < data_length <= 8KB: + * prp1 = buffer_dma + * prp2 = buffer_dma + * + * 3. 8KB < data_length: + * prp1 = buffer_dma(0, 4k) + * prp2 = buffer_dma(4k, ~) + */ + dma_addr = buffer_dma; + page_offset = buffer_dma & (page_size - 1); + data_length = max_lbas << lba_shift; + remain_length = data_length - (page_size - page_offset); + + do { + rt_size_t prps_per_page, prps, pages; + rt_uint64_t *prp_list_ptr, prp_list_dma; + + if (remain_length <= 0) + { + prp2_addr = 0; + break; + } + + if (remain_length) + { + dma_addr += (page_size - page_offset); + } + + if (remain_length <= page_size) + { + prp2_addr = dma_addr; + break; + } + + prps_per_page = page_size / sizeof(rt_uint64_t); + prps = RT_DIV_ROUND_UP(remain_length, page_size); + pages = RT_DIV_ROUND_UP(prps - 1, prps_per_page - 1); + + if (prps > prp_list_size) + { + if (prp_list) + { + rt_free_align(prp_list); + } + + prp_list = rt_malloc_align(pages * page_size, page_size); + + if (!prp_list) + { + LOG_D("No memory to create a PRP List"); + /* Ask user to try again */ + return tlbas - lbas; + } + + prp_list_size = pages * (prps_per_page - 1) + 1; + } + prp_list_ptr = prp_list; + prp_list_dma = (rt_uint64_t)rt_kmem_v2p(prp_list_ptr); + + prp2_addr = prp_list_dma; + + for (int i = 0; prps; --prps, ++i) + { + /* End of the entry, fill the next entry addr if remain */ + if ((i == (prps_per_page - 1)) && prps > 1) + { + prp_list_dma += page_size; + *prp_list_ptr = rt_cpu_to_le64(prp_list_dma); + + /* Start to fill the next PRP */ + i = 0; + } + + *prp_list_ptr = rt_cpu_to_le64(dma_addr); + dma_addr += page_size; + } + + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, prp_list_ptr, prp_list_size); + } while (0); + + cmd.rw.prp1 = rt_cpu_to_le64(buffer_dma); + cmd.rw.prp2 = rt_cpu_to_le64(prp2_addr); + cmd.rw.slba = rt_cpu_to_le16(slba); + cmd.rw.length = rt_cpu_to_le16(max_lbas - 1); + + if ((err = nvme_submit_io_cmd(nvme, &cmd))) + { + tlbas -= lbas; + break; + } + + lbas -= max_lbas; + slba += max_lbas; + buffer_dma += data_length; + } + + if (prp_list) + { + rt_free_align(prp_list); + } + } + + return tlbas; +} + +static rt_ssize_t nvme_blk_read(struct rt_blk_disk *disk, rt_off_t sector, + void *buffer, rt_size_t sector_count) +{ + rt_ssize_t res; + rt_uint32_t page_bits; + rt_size_t buffer_size; + rt_ubase_t buffer_dma; + void *temp_buffer = RT_NULL; + struct rt_nvme_device *ndev = rt_disk_to_nvme_device(disk); + struct rt_nvme_controller *nvme = ndev->ctrl; + + buffer_size = (1 << ndev->lba_shift) * sector_count; + buffer_dma = (rt_ubase_t)rt_kmem_v2p(buffer); + + if ((nvme->sgl_mode && (buffer_dma & RT_GENMASK(1, 0))) || + (!nvme->sgl_mode && (buffer_dma & ARCH_PAGE_MASK))) + { + LOG_D("DMA PRP direct %s buffer MUST 4-bytes or page aligned", "read"); + + page_bits = rt_page_bits(buffer_size); + temp_buffer = rt_pages_alloc(page_bits); + + if (!temp_buffer) + { + return -RT_ENOMEM; + } + + buffer_dma = (rt_ubase_t)rt_kmem_v2p(temp_buffer); + } + + res = nvme_blk_rw(ndev, sector, buffer_dma, sector_count, RT_NVME_CMD_READ); + + if (res > 0) + { + if (res != sector_count) + { + /* + * Don't always aim for optimization, checking for equality + * is much faster than multiplication calculation. + */ + buffer_size = res * (1 << ndev->lba_shift); + } + + if (temp_buffer) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, temp_buffer, buffer_size); + rt_memcpy(buffer, temp_buffer, buffer_size); + } + else + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, buffer, buffer_size); + } + } + + if (temp_buffer) + { + rt_pages_free(temp_buffer, page_bits); + } + + return res; +} + +static rt_ssize_t nvme_blk_write(struct rt_blk_disk *disk, rt_off_t sector, + const void *buffer, rt_size_t sector_count) +{ + rt_ssize_t res; + rt_uint32_t page_bits; + rt_size_t buffer_size; + rt_ubase_t buffer_dma; + void *temp_buffer = RT_NULL; + struct rt_nvme_device *ndev = rt_disk_to_nvme_device(disk); + struct rt_nvme_controller *nvme = ndev->ctrl; + + buffer_size = (1 << ndev->lba_shift) * sector_count; + buffer_dma = (rt_ubase_t)rt_kmem_v2p((void *)buffer); + + if ((nvme->sgl_mode && (buffer_dma & RT_GENMASK(1, 0))) || + (!nvme->sgl_mode && (buffer_dma & ARCH_PAGE_MASK))) + { + LOG_D("DMA PRP direct %s buffer MUST 4-bytes or page aligned", "write"); + + page_bits = rt_page_bits(buffer_size); + temp_buffer = rt_pages_alloc(page_bits); + + if (!temp_buffer) + { + return -RT_ENOMEM; + } + + buffer_dma = (rt_ubase_t)rt_kmem_v2p(temp_buffer); + + rt_memcpy(temp_buffer, buffer, buffer_size); + buffer = temp_buffer; + } + + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)buffer, buffer_size); + + res = nvme_blk_rw(ndev, sector, buffer_dma, sector_count, RT_NVME_CMD_WRITE); + + if (temp_buffer) + { + rt_pages_free(temp_buffer, page_bits); + } + + return res; +} + +static rt_err_t nvme_blk_getgeome(struct rt_blk_disk *disk, + struct rt_device_blk_geometry *geometry) +{ + struct rt_nvme_device *ndev = rt_disk_to_nvme_device(disk); + + geometry->bytes_per_sector = 1 << ndev->lba_shift; + geometry->block_size = 1 << ndev->lba_shift; + geometry->sector_count = rt_le64_to_cpu(ndev->id.nsze); + + return RT_EOK; +} + +static rt_err_t nvme_blk_sync(struct rt_blk_disk *disk) +{ + struct rt_nvme_command cmd; + struct rt_nvme_device *ndev = rt_disk_to_nvme_device(disk); + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.common.opcode = RT_NVME_CMD_FLUSH; + cmd.common.nsid = rt_cpu_to_le32(ndev->nsid); + + return nvme_submit_io_cmd(ndev->ctrl, &cmd); +} + +static rt_err_t nvme_blk_erase(struct rt_blk_disk *disk) +{ + rt_err_t err = RT_EOK; + rt_ssize_t slba, lbas, max_lbas; + struct rt_nvme_command cmd; + struct rt_nvme_device *ndev = rt_disk_to_nvme_device(disk); + struct rt_nvme_controller *nvme = ndev->ctrl; + + if (!nvme->write_zeroes) + { + return -RT_ENOSYS; + } + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.write_zeroes.opcode = RT_NVME_CMD_WRITE_ZEROES; + cmd.write_zeroes.nsid = rt_cpu_to_le32(ndev->nsid); + + slba = 0; + lbas = rt_le64_to_cpu(ndev->id.nsze); + max_lbas = 1 << (nvme->max_transfer_shift - ndev->lba_shift); + + while ((rt_ssize_t)lbas > 0) + { + if (lbas < max_lbas) + { + max_lbas = (rt_uint16_t)lbas; + } + + cmd.write_zeroes.slba = rt_cpu_to_le16(slba); + cmd.write_zeroes.length = rt_cpu_to_le16(max_lbas - 1); + + if ((err = nvme_submit_io_cmd(nvme, &cmd))) + { + break; + } + + lbas -= max_lbas; + slba += max_lbas; + } + + return err; +} + +static rt_err_t nvme_blk_autorefresh(struct rt_blk_disk *disk, rt_bool_t is_auto) +{ + struct rt_nvme_device *ndev = rt_disk_to_nvme_device(disk); + struct rt_nvme_controller *nvme = ndev->ctrl; + + if (nvme->volatile_write_cache & RT_NVME_CTRL_VWC_PRESENT) + { + return nvme_set_features_simple(nvme, RT_NVME_FEAT_VOLATILE_WC, !!is_auto); + } + else if (!is_auto) + { + return RT_EOK; + } + + return -RT_ENOSYS; +} + +static const struct rt_blk_disk_ops nvme_blk_ops = +{ + .read = nvme_blk_read, + .write = nvme_blk_write, + .getgeome = nvme_blk_getgeome, + .sync = nvme_blk_sync, + .erase = nvme_blk_erase, + .autorefresh = nvme_blk_autorefresh, +}; + +static void nvme_queue_isr(int irqno, void *param) +{ + rt_ubase_t level; + rt_uint16_t head, phase, status; + struct rt_nvme_queue *queue = param; + struct rt_nvme_controller *nvme = queue->nvme; + + level = rt_spin_lock_irqsave(&queue->lock); + + head = queue->cq_head; + phase = queue->cq_phase; + status = HWREG16(&queue->cq_entry[head].status); + status = rt_le16_to_cpu(status); + + if ((status & 0x01) == phase) + { + if ((status >> 1)) + { + queue->err = -RT_EIO; + goto _end_cmd; + } + + if (nvme->ops->complete_cmd) + { + nvme->ops->complete_cmd(queue, queue->cmd); + } + + _end_cmd: + if (++head == queue->depth) + { + head = 0; + phase = !phase; + } + + HWREG32(queue->doorbell + nvme->doorbell_stride) = head; + queue->cq_head = head; + queue->cq_phase = phase; + + rt_completion_done(&queue->done); + } + + rt_spin_unlock_irqrestore(&queue->lock, level); +} + +static rt_err_t nvme_identify(struct rt_nvme_controller *nvme, + rt_uint32_t nsid, rt_uint32_t cns, void *data) +{ + rt_err_t err; + rt_uint32_t page_size = nvme->page_size; + rt_ubase_t data_phy = (rt_ubase_t)rt_kmem_v2p(data); + int offset = data_phy & (page_size - 1); + struct rt_nvme_command cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.identify.opcode = RT_NVME_ADMIN_OPCODE_IDENTIFY; + cmd.identify.nsid = rt_cpu_to_le32(nsid); + cmd.identify.prp1 = rt_cpu_to_le64(data_phy); + + if (sizeof(struct rt_nvme_id_ctrl) <= page_size - offset) + { + cmd.identify.prp2 = 0; + } + else + { + data_phy += (page_size - offset); + cmd.identify.prp2 = rt_cpu_to_le64(data_phy); + } + cmd.identify.cns = rt_cpu_to_le32(cns); + + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, data, sizeof(struct rt_nvme_id_ctrl)); + + if (!(err = nvme_submit_cmd(&nvme->admin_queue, &cmd))) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, data, sizeof(struct rt_nvme_id_ctrl)); + } + + return err; +} + +static rt_err_t nvme_attach_queue(struct rt_nvme_queue *queue, rt_uint8_t opcode) +{ + struct rt_nvme_command cmd; + struct rt_nvme_controller *nvme = queue->nvme; + rt_uint16_t flags = RT_NVME_QUEUE_PHYS_CONTIG; + + rt_memset(&cmd, 0, sizeof(cmd)); + + if (opcode == RT_NVME_ADMIN_OPCODE_CREATE_CQ) + { + cmd.create_cq.opcode = opcode; + cmd.create_cq.prp1 = rt_cpu_to_le64(queue->cq_entry_phy); + cmd.create_cq.cqid = rt_cpu_to_le16(queue->qid); + cmd.create_cq.qsize = rt_cpu_to_le16(queue->depth - 1); + cmd.create_cq.cq_flags = rt_cpu_to_le16(flags | RT_NVME_CQ_IRQ_ENABLED); + cmd.create_cq.irq_vector = rt_cpu_to_le16(nvme->irqs_nr > 1 ? queue->qid : 0); + } + else if (opcode == RT_NVME_ADMIN_OPCODE_CREATE_SQ) + { + cmd.create_sq.opcode = opcode; + cmd.create_sq.prp1 = rt_cpu_to_le64(queue->sq_cmds_phy); + cmd.create_sq.sqid = rt_cpu_to_le16(queue->qid); + cmd.create_sq.qsize = rt_cpu_to_le16(queue->depth - 1); + cmd.create_sq.sq_flags = rt_cpu_to_le16(flags | RT_NVME_SQ_PRIO_MEDIUM); + cmd.create_sq.cqid = rt_cpu_to_le16(queue->qid); + } + else + { + LOG_E("What the fuck opcode = %x", opcode); + RT_ASSERT(0); + } + + return nvme_submit_cmd(&nvme->admin_queue, &cmd); +} + +rt_inline rt_err_t nvme_attach_queue_sq(struct rt_nvme_queue *queue) +{ + return nvme_attach_queue(queue, RT_NVME_ADMIN_OPCODE_CREATE_SQ); +} + +rt_inline rt_err_t nvme_attach_queue_cq(struct rt_nvme_queue *queue) +{ + return nvme_attach_queue(queue, RT_NVME_ADMIN_OPCODE_CREATE_CQ); +} + +static rt_err_t nvme_detach_queue(struct rt_nvme_queue *queue, + rt_uint8_t opcode) +{ + struct rt_nvme_command cmd; + struct rt_nvme_controller *nvme = queue->nvme; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.delete_queue.opcode = opcode; + cmd.delete_queue.qid = rt_cpu_to_le16(queue->qid); + + return nvme_submit_cmd(&nvme->admin_queue, &cmd); +} + +rt_inline rt_ubase_t nvme_queue_dma_flags(void) +{ + return RT_DMA_F_NOCACHE | RT_DMA_F_LINEAR; +} + +static void nvme_free_queue(struct rt_nvme_queue *queue) +{ + rt_ubase_t dma_flags; + struct rt_nvme_controller *nvme = queue->nvme; + + if (nvme->ops->cleanup_queue) + { + rt_err_t err; + + if (!(err = nvme->ops->cleanup_queue(queue))) + { + LOG_W("Cleanup[%s] queue error = %s", nvme->ops->name, rt_strerror(err)); + } + } + + dma_flags = nvme_queue_dma_flags(); + + if (queue->sq_cmds) + { + rt_dma_free(nvme->dev, sizeof(*queue->sq_cmds) * queue->depth, + queue->sq_cmds, queue->sq_cmds_phy, dma_flags); + } + + if (queue->cq_entry) + { + rt_dma_free(nvme->dev, sizeof(*queue->cq_entry) * queue->depth, + queue->cq_entry, queue->cq_entry_phy, dma_flags); + } +} + +static struct rt_nvme_queue *nvme_alloc_queue(struct rt_nvme_controller *nvme, + int qid, int depth) +{ + rt_err_t err; + rt_ubase_t dma_flags; + struct rt_nvme_queue *queue = &nvme->queue[qid]; + + rt_memset(queue, 0, sizeof(*queue)); + + queue->nvme = nvme; + queue->doorbell = &nvme->doorbell_tbl[qid * 2 * nvme->doorbell_stride]; + queue->qid = qid; + queue->depth = depth; + queue->cq_head = 0; + queue->cq_phase = 1; + rt_completion_init(&queue->done); + rt_spin_lock_init(&queue->lock); + + dma_flags = nvme_queue_dma_flags(); + + /* struct rt_nvme_command */ + queue->sq_cmds = rt_dma_alloc(nvme->dev, + sizeof(*queue->sq_cmds) * depth, &queue->sq_cmds_phy, dma_flags); + + if (!queue->sq_cmds) + { + err = -RT_ENOMEM; + goto _fail; + } + + /* struct rt_nvme_completion */ + queue->cq_entry = rt_dma_alloc(nvme->dev, + sizeof(*queue->cq_entry) * depth, &queue->cq_entry_phy, dma_flags); + + if (!queue->cq_entry) + { + err = -RT_ENOMEM; + goto _fail; + } + + rt_memset(queue->sq_cmds, 0, sizeof(struct rt_nvme_command) * depth); + rt_memset(queue->cq_entry, 0, sizeof(struct rt_nvme_completion) * depth); + + if (nvme->ops->setup_queue) + { + if (!(err = nvme->ops->setup_queue(queue))) + { + LOG_E("Setup[%s] queue error = %s", nvme->ops->name, rt_strerror(err)); + + goto _fail; + } + } + + return queue; + +_fail: + nvme_free_queue(queue); + + return rt_err_ptr(err); +} + +static rt_err_t nvme_configure_admin_queue(struct rt_nvme_controller *nvme) +{ + rt_err_t err; + int irq; + char name[RT_NAME_MAX]; + rt_uint32_t aqa; + rt_uint32_t page_shift = ARCH_PAGE_SHIFT; + rt_uint32_t page_min = RT_NVME_CAP_MPSMIN(nvme->cap) + 12; + rt_uint32_t page_max = RT_NVME_CAP_MPSMAX(nvme->cap) + 12; + struct rt_nvme_queue *admin_queue; + + if (page_shift < page_min) + { + LOG_E("Device %s page size (%u) %s than host (%u)", + "minimum", 1 << page_min, "larger", 1 << page_shift); + return -RT_EINVAL; + } + + if (page_shift > page_max) + { + LOG_W("Device %s page size (%u) %s than host (%u)", + "maximum", 1 << page_max, "smaller", 1 << page_shift); + page_shift = page_max; + } + + if ((err = nvme_disable_ctrl(nvme))) + { + return err; + } + + admin_queue = nvme_alloc_queue(nvme, 0, RT_NVME_AQ_DEPTH); + + if (rt_is_err(admin_queue)) + { + return rt_ptr_err(admin_queue); + } + + aqa = admin_queue->depth - 1; + aqa |= aqa << 16; + + nvme->page_shift = page_shift; + nvme->page_size = 1U << page_shift; + + nvme->ctrl_config = RT_NVME_CC_CSS_NVM; + nvme->ctrl_config |= (page_shift - 12) << RT_NVME_CC_MPS_SHIFT; + nvme->ctrl_config |= RT_NVME_CC_ARB_RR | RT_NVME_CC_SHN_NONE; + nvme->ctrl_config |= RT_NVME_CC_IOSQES | RT_NVME_CC_IOCQES; + + nvme_writel(nvme, RT_NVME_REG_AQA, aqa); + nvme_writeq(nvme, RT_NVME_REG_ASQ, admin_queue->sq_cmds_phy); + nvme_writeq(nvme, RT_NVME_REG_ACQ, admin_queue->cq_entry_phy); + + if ((err = nvme_enable_ctrl(nvme))) + { + nvme_free_queue(admin_queue); + + return err; + } + + irq = nvme->irqs[0]; + + rt_snprintf(name, RT_NAME_MAX, "%s-admin-queue", nvme->name); + + rt_hw_interrupt_install(irq, nvme_queue_isr, &nvme->admin_queue, name); + rt_hw_interrupt_umask(irq); + + return RT_EOK; +} + +static rt_err_t nvme_setup_io_queues(struct rt_nvme_controller *nvme) +{ + rt_err_t err; + rt_uint32_t value; + int irq, cpuid = 0; + char name[RT_NAME_MAX]; + rt_bool_t affinity_fixup = RT_FALSE; + RT_IRQ_AFFINITY_DECLARE(affinity) = { 0 }; + struct rt_nvme_queue *queue; + + nvme->io_queue_max = nvme->irqs_nr > 1 ? nvme->irqs_nr - 1 : 1; + value = (nvme->io_queue_max - 1) | ((nvme->io_queue_max - 1) << 16); + + if ((err = nvme_set_features_simple(nvme, RT_NVME_FEAT_NUM_QUEUES, value))) + { + return err; + } + + for (int i = 0, q_idx = 1; i < nvme->io_queue_max; ++i, ++q_idx) + { + queue = nvme_alloc_queue(nvme, q_idx, nvme->queue_depth); + + if (!queue) + { + return -RT_ENOMEM; + } + + if ((err = nvme_attach_queue_cq(queue)) || + (err = nvme_attach_queue_sq(queue))) + { + return err; + } + } + + for (int i = 0, irq_idx = 1; i < nvme->io_queue_max; ++i, ++irq_idx) + { + irq = nvme->irqs[irq_idx % nvme->irqs_nr]; + + rt_snprintf(name, RT_NAME_MAX, "%s-io-queue%d", nvme->name, i); + + if (!affinity_fixup) + { + RT_IRQ_AFFINITY_SET(affinity, cpuid % RT_CPUS_NR); + if (rt_pic_irq_set_affinity(irq, affinity)) + { + /* Fixup in secondary CPU startup */ + affinity_fixup = RT_TRUE; + } + RT_IRQ_AFFINITY_CLEAR(affinity, cpuid++ % RT_CPUS_NR); + } + + rt_hw_interrupt_install(irq, nvme_queue_isr, &nvme->io_queues[i], name); + rt_hw_interrupt_umask(irq); + } + + return RT_EOK; +} + +static void nvme_remove_io_queues(struct rt_nvme_controller *nvme) +{ + int irq; + struct rt_nvme_queue *queue; + + for (int i = 0, irq_idx = 1; i < nvme->io_queue_max; ++i, ++irq_idx) + { + queue = &nvme->io_queues[i]; + + nvme_detach_queue(queue, RT_NVME_ADMIN_OPCODE_DELETE_SQ); + nvme_detach_queue(queue, RT_NVME_ADMIN_OPCODE_DELETE_CQ); + nvme_free_queue(queue); + + irq = nvme->irqs[irq_idx % nvme->irqs_nr]; + + rt_hw_interrupt_mask(irq); + rt_pic_detach_irq(irq, queue); + } +} + +static void nvme_remove_admin_queues(struct rt_nvme_controller *nvme) +{ + int irq = nvme->irqs[0]; + + rt_hw_interrupt_mask(irq); + rt_pic_detach_irq(irq, &nvme->admin_queue); + + nvme_free_queue(&nvme->admin_queue); +} + +static void nvme_remove_devices(struct rt_nvme_controller *nvme) +{ + struct rt_nvme_device *ndev, *next_ndev; + + rt_list_for_each_entry_safe(ndev, next_ndev, &nvme->ns_nodes, list) + { + rt_list_remove(&ndev->list); + + rt_hw_blk_disk_unregister(&ndev->parent); + rt_free(ndev); + } +} + +static rt_err_t nvme_scan_device(struct rt_nvme_controller *nvme, + rt_size_t number_of_ns) +{ + rt_err_t err = RT_EOK; + rt_uint32_t lbaf; + struct rt_nvme_id_ns *id = RT_NULL; + + if (!(id = rt_malloc_align(sizeof(*id), nvme->page_size))) + { + return -RT_ENOMEM; + } + + /* NVME Namespace is start with "1" */ + for (rt_uint32_t nsid = 1; nsid <= number_of_ns; ++nsid) + { + struct rt_nvme_device *ndev = rt_calloc(1, sizeof(*ndev)); + + if (!ndev) + { + err = -RT_ENOMEM; + goto _free_res; + } + + rt_memset(id, 0, sizeof(*id)); + if ((err = nvme_identify(nvme, nsid, 0, id))) + { + goto _free_res; + } + + if (!id->nsze) + { + continue; + } + + ndev->ctrl = nvme; + + rt_memcpy(&ndev->id, id, sizeof(ndev->id)); + lbaf = id->flbas & RT_NVME_NS_FLBAS_LBA_MASK; + lbaf |= ((id->flbas & RT_NVME_NS_FLBAS_LBA_UMASK) >> RT_NVME_NS_FLBAS_LBA_SHIFT); + + ndev->nsid = nsid; + ndev->lba_shift = id->lbaf[lbaf].ds; + + ndev->parent.ida = &nvme_ida; + ndev->parent.parallel_io = RT_TRUE; + ndev->parent.ops = &nvme_blk_ops; + ndev->parent.max_partitions = RT_BLK_PARTITION_MAX; + rt_dm_dev_set_name(&ndev->parent.parent, "%sn%u", nvme->name, nsid); + + if ((err = rt_hw_blk_disk_register(&ndev->parent))) + { + goto _free_res; + } + + rt_list_init(&ndev->list); + rt_list_insert_before(&nvme->ns_nodes, &ndev->list); + } + +_free_res: + rt_free_align(id); + + return err; +} + +rt_inline rt_size_t strip_len(const char *str, rt_size_t max_len) +{ + rt_size_t size = 0; + + for (int i = 0; *str && i < max_len; ++i, ++str) + { + if (*str != ' ') + { + size = i + 1; + } + } + + return size; +} + +rt_err_t rt_nvme_controller_register(struct rt_nvme_controller *nvme) +{ + rt_err_t err; + struct rt_nvme_id_ctrl *ctrl = RT_NULL; + + if (!nvme || !nvme->ops) + { + return -RT_EINVAL; + } + + if (nvme_readl(nvme, RT_NVME_REG_CSTS) == (rt_uint32_t)-1) + { + LOG_E("Out of memory"); + + return -RT_EINVAL; + } + + if ((nvme->nvme_id = rt_dm_ida_alloc(&nvme_controller_ida)) < 0) + { + return -RT_EFULL; + } + + rt_snprintf(nvme->name, RT_NAME_MAX, "nvme%u", nvme->nvme_id); + + nvme->cap = nvme_readq(nvme, RT_NVME_REG_CAP); + nvme->queue_depth = RT_NVME_CAP_MQES(nvme->cap) + 1; + nvme->doorbell_stride = 1 << RT_NVME_CAP_STRIDE(nvme->cap); + nvme->doorbell_tbl = nvme->regs + RT_NVME_REG_DBS; + + if ((err = nvme_configure_admin_queue(nvme))) + { + LOG_E("Configure admin queue error = %s", rt_strerror(err)); + goto _free_admin_queue; + } + + if ((err = nvme_setup_io_queues(nvme))) + { + LOG_E("Unable to setup I/O queues error = %s", rt_strerror(err)); + goto _free_admin_queue; + } + + if (!(ctrl = rt_malloc_align(sizeof(*ctrl), nvme->page_size))) + { + err = -RT_ENOMEM; + goto _fail; + } + + if ((err = nvme_identify(nvme, 0, 1, ctrl))) + { + goto _fail; + } + + if (ctrl->mdts) + { + nvme->max_transfer_shift = ctrl->mdts + (RT_NVME_CAP_MPSMIN(nvme->cap) + 12); + } + else + { + /* 1MB is recommended. */ + nvme->max_transfer_shift = 20; + } + nvme->volatile_write_cache = ctrl->vwc; + nvme->write_zeroes = !!(rt_le64_to_cpu(ctrl->oncs) & RT_NVME_CTRL_ONCS_WRITE_ZEROES); + + if ((rt_le32_to_cpu(ctrl->sgls) & RT_NVME_ID_SGL_SUPPORT_MASK)) + { + nvme->sgl_mode = RT_NVME_PSDT_SGL_MPTR_SGL; + } + + LOG_I("NVM Express v%d.%d (%s, %-*.s, %-*.s)", + nvme_readl(nvme, RT_NVME_REG_VS) >> 16, + nvme_readl(nvme, RT_NVME_REG_VS) & 0xff, + nvme->ops->name, + strip_len(ctrl->mn, sizeof(ctrl->mn)), ctrl->mn, + strip_len(ctrl->fr, sizeof(ctrl->fr)), ctrl->fr); + + rt_list_init(&nvme->ns_nodes); + if ((err = nvme_scan_device(nvme, rt_le32_to_cpu(ctrl->nn)))) + { + goto _fail; + } + + rt_free_align(ctrl); + + rt_spin_lock(&nvme_lock); + rt_list_insert_after(&nvme_nodes, &nvme->list); + rt_spin_unlock(&nvme_lock); + + return RT_EOK; + +_fail: + if (ctrl) + { + rt_free_align(ctrl); + } + nvme_remove_devices(nvme); + nvme_remove_io_queues(nvme); +_free_admin_queue: + nvme_remove_admin_queues(nvme); + + rt_dm_ida_free(&nvme_controller_ida, nvme->nvme_id); + + return err; +} + +rt_err_t rt_nvme_controller_unregister(struct rt_nvme_controller *nvme) +{ + rt_err_t err; + + if (!nvme) + { + return -RT_EINVAL; + } + + rt_spin_lock(&nvme_lock); + rt_list_remove(&nvme->list); + rt_spin_unlock(&nvme_lock); + + nvme_remove_devices(nvme); + nvme_remove_io_queues(nvme); + nvme_remove_admin_queues(nvme); + + rt_dm_ida_free(&nvme_controller_ida, nvme->nvme_id); + + if (!(err = nvme_shutdown_ctrl(nvme))) + { + err = nvme_disable_ctrl(nvme); + } + else + { + LOG_E("%s: shutdown error = %s", nvme->name, rt_strerror(err)); + } + + return err; +} + +/* + * NVME's IO queue should be Per-CPU, fixup the affinity after the secondary CPU + * startup, this stage can make sure the affinity setting success as possible. + */ +static int nvme_queue_affinify_fixup(void) +{ + int cpuid = rt_hw_cpu_id(); + struct rt_nvme_controller *nvme; + RT_IRQ_AFFINITY_DECLARE(affinity) = { 0 }; + RT_IRQ_AFFINITY_DECLARE(current_affinity) = { 0 }; + + RT_IRQ_AFFINITY_SET(affinity, cpuid); + + rt_hw_spin_lock(&nvme_lock.lock); + rt_list_for_each_entry(nvme, &nvme_nodes, list) + { + for (int i = cpuid % RT_CPUS_NR; i < nvme->io_queue_max; i += RT_CPUS_NR) + { + int irq = nvme->irqs[i]; + + if (!rt_pic_irq_get_affinity(irq, current_affinity) && + !rt_bitmap_test_bit(current_affinity, cpuid)) + { + rt_ubase_t level = rt_hw_interrupt_disable(); + + rt_pic_irq_set_affinity(irq, affinity); + + rt_hw_interrupt_enable(level); + } + } + } + rt_hw_spin_unlock(&nvme_lock.lock); + + return 0; +} +INIT_SECONDARY_CPU_EXPORT(nvme_queue_affinify_fixup); diff --git a/rt-thread/components/drivers/ofw/base.c b/rt-thread/components/drivers/ofw/base.c index c2d2f8f..78a2e9f 100644 --- a/rt-thread/components/drivers/ofw/base.c +++ b/rt-thread/components/drivers/ofw/base.c @@ -333,8 +333,6 @@ static int ofw_prop_index_of_string(struct rt_ofw_prop *prop, const char *string static rt_int32_t ofw_strcasecmp(const char *cs, const char *ct) { - extern rt_int32_t strcasecmp(const char *cs, const char *ct); - return rt_strcasecmp(cs, ct); } @@ -1412,7 +1410,7 @@ struct rt_ofw_node *rt_ofw_append_child(struct rt_ofw_node *parent, const char * } } - return np; + return rt_ofw_node_get(np); } rt_err_t rt_ofw_append_prop(struct rt_ofw_node *np, const char *name, int length, void *value) diff --git a/rt-thread/components/drivers/ofw/fdt.c b/rt-thread/components/drivers/ofw/fdt.c index 419f392..cca4cdd 100644 --- a/rt-thread/components/drivers/ofw/fdt.c +++ b/rt-thread/components/drivers/ofw/fdt.c @@ -37,6 +37,12 @@ static rt_phandle _phandle_max; static rt_size_t _root_size_cells; static rt_size_t _root_addr_cells; +#ifdef ARCH_CPU_64BIT +#define MIN_BIT 16 +#else +#define MIN_BIT 8 +#endif + const char *rt_fdt_node_name(const char *full_name) { const char *node_name = strrchr(full_name, '/'); @@ -85,15 +91,15 @@ rt_uint64_t rt_fdt_translate_address(void *fdt, int nodeoffset, rt_uint64_t addr if (parent >= 0) { - ranges = fdt_getprop(fdt, nodeoffset, "ranges", &length); + ranges = fdt_getprop(fdt, parent, "ranges", &length); } if (ranges && length > 0) { - local.addr_cells = fdt_address_cells(fdt, nodeoffset); - local.size_cells = fdt_size_cells(fdt, nodeoffset); - cpu.addr_cells = fdt_io_addr_cells(fdt, nodeoffset); - cpu.size_cells = fdt_io_size_cells(fdt, nodeoffset); + local.addr_cells = fdt_address_cells(fdt, parent); + local.size_cells = fdt_size_cells(fdt, parent); + cpu.addr_cells = fdt_io_addr_cells(fdt, parent); + cpu.size_cells = fdt_io_size_cells(fdt, parent); group_len = local.addr_cells + cpu.addr_cells + local.size_cells; @@ -105,7 +111,7 @@ rt_uint64_t rt_fdt_translate_address(void *fdt, int nodeoffset, rt_uint64_t addr if (local.addr <= address && local.addr + local.size > address) { - ret += address - cpu.addr; + ret = address - local.addr + cpu.addr; break; } @@ -247,9 +253,9 @@ static rt_err_t fdt_reserved_memory_reg(int nodeoffset, const char *uname) rt_bool_t is_nomap = fdt_getprop(_fdt, nodeoffset, "no-map", RT_NULL) ? RT_TRUE : RT_FALSE; base = rt_fdt_translate_address(_fdt, nodeoffset, base); - rt_memblock_reserve_memory(uname, base, base + size, is_nomap); - len -= t_len; + rt_memblock_reserve_memory(fdt_get_name(_fdt, nodeoffset, RT_NULL), + base, base + size, is_nomap); } } } @@ -358,11 +364,11 @@ static rt_err_t fdt_scan_memory(void) if (!err) { - LOG_I("Memory node(%d) ranges: %p - %p%s", no, base, base + size, ""); + LOG_I("Memory node(%d) ranges: 0x%.*lx - 0x%.*lx%s", no, MIN_BIT, base, MIN_BIT, base + size, ""); } else { - LOG_W("Memory node(%d) ranges: %p - %p%s", no, base, base + size, " unable to record"); + LOG_W("Memory node(%d) ranges: 0x%.*lx - 0x%.*lx%s", no, MIN_BIT, base, MIN_BIT, base + size, " unable to record"); } } } @@ -793,6 +799,55 @@ rt_err_t rt_fdt_scan_chosen_stdout(void) return err; } +rt_err_t rt_fdt_bootargs_select(const char *key, int index, const char **out_result) +{ + rt_err_t err; + + if (key && index >= 0 && out_result) + { + int offset = fdt_path_offset(_fdt, "/chosen"); + + if (offset >= 0) + { + int len, key_len = rt_strlen(key); + const char *bootargs = fdt_getprop(_fdt, offset, "bootargs", &len), *end; + + end = bootargs + len; + err = -RT_EEMPTY; + + for (int i = 0; bootargs < end; ++i) + { + bootargs = rt_strstr(bootargs, key); + + if (!bootargs) + { + break; + } + + bootargs += key_len; + + if (i == index) + { + *out_result = bootargs; + + err = -RT_EOK; + break; + } + } + } + else + { + err = -RT_ERROR; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + static void system_node_init_flag(struct rt_ofw_node *np) { if (np) diff --git a/rt-thread/components/drivers/ofw/io.c b/rt-thread/components/drivers/ofw/io.c index d9065c0..b0a7526 100644 --- a/rt-thread/components/drivers/ofw/io.c +++ b/rt-thread/components/drivers/ofw/io.c @@ -407,6 +407,75 @@ rt_uint64_t rt_ofw_translate_address(struct rt_ofw_node *np, const char *range_t return cpu_addr; } +rt_uint64_t rt_ofw_reverse_address(struct rt_ofw_node *np, const char *range_type, rt_uint64_t address) +{ + rt_uint64_t bus_addr = address; + + if (!range_type) + { + range_type = "ranges"; + } + + rt_ofw_foreach_parent_node(np) + { + rt_ssize_t len; + struct rt_ofw_prop *prop; + struct bus_ranges *ranges = RT_NULL; + + prop = rt_ofw_get_prop(np, range_type, &len); + + if (!prop || !len) + { + continue; + } + + for (int i = 0; i < RT_ARRAY_SIZE(_bus_ranges); ++i) + { + if (!_bus_ranges[i]) + { + break; + } + + if (_bus_ranges[i]->np == np) + { + ranges = _bus_ranges[i]; + break; + } + } + + if (!ranges) + { + ranges = ofw_bus_ranges(np, prop); + } + + if (ranges) + { + for (int i = 0; i < ranges->nr; ++i) + { + rt_uint64_t parent_addr = ranges->parent_addr[i]; + rt_uint64_t child_size = ranges->child_size[i]; + + if (address >= parent_addr && address < parent_addr + child_size) + { + bus_addr = ranges->child_addr[i] + (address - parent_addr); + + break; + } + } + } + else + { + bus_addr = ~0ULL; + } + + rt_ofw_node_put(np); + + break; + } + + return bus_addr; +} + #ifdef ARCH_CPU_64BIT #define ofw_address_cpu_cast(np, address) (void *)(address) #else diff --git a/rt-thread/components/drivers/ofw/ofw.c b/rt-thread/components/drivers/ofw/ofw.c index d09fb4e..76389f3 100644 --- a/rt-thread/components/drivers/ofw/ofw.c +++ b/rt-thread/components/drivers/ofw/ofw.c @@ -69,6 +69,12 @@ struct ofw_obj_cmp_list static const struct ofw_obj_cmp_list ofw_obj_cmp_list[] = { +#ifdef RT_USING_CLK + { "#clock-cells", RT_CLK_NODE_OBJ_NAME, sizeof(struct rt_clk_node) }, +#endif +#ifdef RT_USING_RESET + { "#reset-cells", RT_RESET_CONTROLLER_OBJ_NAME, sizeof(struct rt_reset_controller) }, +#endif { "#power-domain-cells", RT_POWER_DOMAIN_PROXY_OBJ_NAME, sizeof(struct rt_dm_power_domain_proxy) }, { "#power-domain-cells", RT_POWER_DOMAIN_OBJ_NAME, sizeof(struct rt_dm_power_domain) }, }; @@ -103,14 +109,14 @@ static struct rt_object *ofw_parse_object(struct rt_ofw_node *np, const char *ce { item = &ofw_obj_cmp_list[i]; - if (!rt_strcmp(item->cells_name, cells_name)) - { - ret_obj = obj; - break; - } - if (!rt_strncmp(item->obj_name, obj->name, RT_NAME_MAX)) { + if (!rt_strcmp(item->cells_name, cells_name)) + { + ret_obj = obj; + break; + } + obj = (struct rt_object *)((rt_ubase_t)obj + item->obj_size); break; } @@ -134,7 +140,7 @@ struct rt_object *rt_ofw_parse_object(struct rt_ofw_node *np, const char *obj_na if (np && (test_obj = rt_ofw_data(np)) && cells_name) { /* The composite object is rare, so we try to find this object as much as possible at once. */ - if (obj_name && rt_strcmp(test_obj->name, obj_name)) + if (obj_name && !rt_strcmp(test_obj->name, obj_name)) { obj = test_obj; } @@ -386,6 +392,11 @@ const char *rt_ofw_bootargs_select(const char *key, int index) { *(char *)ch++ = '\0'; } + if (*ch == '\0') + { + /* space in the end */ + --bootargs_nr; + } --ch; } @@ -636,7 +647,14 @@ void rt_ofw_node_dump_dts(struct rt_ofw_node *np, rt_bool_t sibling_too) struct fdt_info *header = (struct fdt_info *)np->name; struct fdt_reserve_entry *rsvmap = header->rsvmap; - rt_kprintf("/dts-v%x/;\n\n", fdt_version(header->fdt)); + /* + * Shall be present to identify the file as a version 1 DTS + * (dts files without this tag will be treated by dtc + * as being in the obsolete version 0, which uses + * a different format for integers in addition to + * other small but incompatible changes). + */ + rt_kprintf("/dts-v1/;\n\n"); for (int i = header->rsvmap_nr - 1; i >= 0; --i) { diff --git a/rt-thread/components/drivers/pci/Kconfig b/rt-thread/components/drivers/pci/Kconfig new file mode 100644 index 0000000..f25fce6 --- /dev/null +++ b/rt-thread/components/drivers/pci/Kconfig @@ -0,0 +1,49 @@ +menuconfig RT_USING_PCI + bool "Using Peripheral Component Interconnect Express (PCIe/PCI)" + depends on RT_USING_DM + depends on RT_USING_PIC + select RT_USING_ADT + select RT_USING_ADT_BITMAP + default n + +config RT_PCI_MSI + bool "PCI MSI/MSI-X" + depends on RT_USING_PCI + default y + +config RT_PCI_ENDPOINT + bool "PCI Endpoint" + depends on RT_USING_PCI + select RT_USING_ADT_REF + default n + +config RT_PCI_SYS_64BIT + bool "PCI System 64bit" + depends on RT_USING_PCI + depends on ARCH_CPU_64BIT + default y + +config RT_PCI_CACHE_LINE_SIZE + int "PCI Cache line size" + depends on RT_USING_PCI + default 8 if ARCH_CPU_64BIT + default 4 + +config RT_PCI_LOCKLESS + bool "PCI Lock less in options" + depends on RT_USING_PCI + default n + +if RT_USING_PCI + +comment "PCI Device Drivers" + +config RT_PCI_ECAM + bool "PCIe ECAM" + depends on RT_USING_PCI + default y + help + PCIe Express Enhanced Configuration Access Mechanism + +rsource "host/Kconfig" +endif diff --git a/rt-thread/components/drivers/pci/SConscript b/rt-thread/components/drivers/pci/SConscript new file mode 100644 index 0000000..dfe3797 --- /dev/null +++ b/rt-thread/components/drivers/pci/SConscript @@ -0,0 +1,28 @@ +from building import * + +objs = [] + +if not GetDepend(['RT_USING_PCI']): + Return('objs') + +cwd = GetCurrentDir() +list = os.listdir(cwd) +CPPPATH = [cwd + '/../include'] + +src = ['access.c', 'host-bridge.c', 'irq.c', 'pci.c', 'pme.c', 'probe.c'] + +if GetDepend(['RT_USING_OFW']): + src += ['ofw.c'] + +if GetDepend(['RT_PCI_ECAM']): + src += ['ecam.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +objs = objs + group + +Return('objs') diff --git a/rt-thread/components/drivers/pci/access.c b/rt-thread/components/drivers/pci/access.c new file mode 100644 index 0000000..7b026c8 --- /dev/null +++ b/rt-thread/components/drivers/pci/access.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#include +#include + +#include + +struct rt_spinlock rt_pci_lock = { 0 }; + +#ifdef RT_PCI_LOCKLESS +#define pci_lock_config(l) do { (void)(l); } while (0) +#define pci_unlock_config(l) do { (void)(l); } while (0) +#else +#define pci_lock_config(l) l = rt_spin_lock_irqsave(&rt_pci_lock) +#define pci_unlock_config(l) rt_spin_unlock_irqrestore(&rt_pci_lock, l) +#endif + +#define PCI_OPS_READ(name, type) \ +rt_err_t rt_pci_bus_read_config_##name(struct rt_pci_bus *bus, rt_uint32_t devfn, int reg, type *value) \ +{ \ + rt_err_t err; \ + rt_ubase_t level; \ + rt_uint32_t data = 0; \ + pci_lock_config(level); \ + err = bus->ops->read(bus, devfn, reg, sizeof(type), &data); \ + *value = err ? (type)(~0) : (type)data; \ + pci_unlock_config(level); \ + return err; \ +} + +#define PCI_OPS_WRITE(name, type) \ +rt_err_t rt_pci_bus_write_config_##name(struct rt_pci_bus *bus, rt_uint32_t devfn, int reg, type value) \ +{ \ + rt_err_t err; \ + rt_ubase_t level; \ + pci_lock_config(level); \ + err = bus->ops->write(bus, devfn, reg, sizeof(type), value); \ + pci_unlock_config(level); \ + return err; \ +} + +#define PCI_OPS(name, type) \ + PCI_OPS_READ(name, type) \ + PCI_OPS_WRITE(name, type) + +PCI_OPS(u8, rt_uint8_t) +PCI_OPS(u16, rt_uint16_t) +PCI_OPS(u32, rt_uint32_t) + +#undef PCI_OP_WRITE +#undef PCI_OP_READ +#undef PCI_OPS + +rt_err_t rt_pci_bus_read_config_uxx(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, int width, rt_uint32_t *value) +{ + void *base; + + if ((base = bus->ops->map(bus, devfn, reg))) + { + if (width == 1) + { + *value = HWREG8(base); + } + else if (width == 2) + { + *value = HWREG16(base); + } + else + { + *value = HWREG32(base); + } + + return RT_EOK; + } + + return -RT_ERROR; +} + +rt_err_t rt_pci_bus_write_config_uxx(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, int width, rt_uint32_t value) +{ + void *base; + + if ((base = bus->ops->map(bus, devfn, reg))) + { + if (width == 1) + { + HWREG8(base) = value; + } + else if (width == 2) + { + HWREG16(base) = value; + } + else + { + HWREG32(base) = value; + } + + return RT_EOK; + } + + return -RT_ERROR; +} + +rt_err_t rt_pci_bus_read_config_generic_u32(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, int width, rt_uint32_t *value) +{ + void *base; + + if ((base = bus->ops->map(bus, devfn, reg))) + { + *value = HWREG32(base); + + if (width <= 2) + { + *value = (*value >> (8 * (reg & 3))) & ((1 << (width * 8)) - 1); + } + + return RT_EOK; + } + + return -RT_ERROR; +} + +rt_err_t rt_pci_bus_write_config_generic_u32(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, int width, rt_uint32_t value) +{ + void *base; + + if ((base = bus->ops->map(bus, devfn, reg & ~0x3))) + { + if (width == 4) + { + HWREG32(base) = value; + } + else + { + rt_uint32_t mask, tmp; + + mask = ~(((1 << (width * 8)) - 1) << ((reg & 0x3) * 8)); + tmp = HWREG32(base) & mask; + tmp |= value << ((reg & 0x3) * 8); + HWREG32(base) = tmp; + } + + return RT_EOK; + } + + return -RT_ERROR; +} diff --git a/rt-thread/components/drivers/pci/ecam.c b/rt-thread/components/drivers/pci/ecam.c new file mode 100644 index 0000000..f5813f3 --- /dev/null +++ b/rt-thread/components/drivers/pci/ecam.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#include +#include + +#define DBG_TAG "pci.ecam" +#define DBG_LVL DBG_INFO +#include + +#include "ecam.h" + +struct pci_ecam_config_window *pci_ecam_create(struct rt_pci_host_bridge *host_bridge, + const struct pci_ecam_ops *ops) +{ + struct pci_ecam_config_window *conf_win = rt_calloc(1, sizeof(*conf_win)); + + if (!conf_win) + { + return RT_NULL; + } + + conf_win->bus_range = host_bridge->bus_range; + conf_win->bus_shift = ops->bus_shift; + conf_win->ops = ops; + + host_bridge->ops = (const struct rt_pci_ops *)&ops->pci_ops; + + return conf_win; +} + +void *pci_ecam_map(struct rt_pci_bus *bus, rt_uint32_t devfn, int where) +{ + struct pci_ecam_config_window *conf_win = bus->sysdata; + const struct pci_ecam_ops *eops = conf_win->ops; + void *win = conf_win->win, *map; + rt_uint32_t busn = bus->number, bus_shift = eops->bus_shift, devfn_shift = bus_shift - 8; + + busn -= conf_win->bus_range[0]; + + if (bus_shift) + { + rt_uint32_t bus_offset = (busn & PCIE_ECAM_BUS_MASK) << bus_shift; + rt_uint32_t devfn_offset = (devfn & PCIE_ECAM_DEVFN_MASK) << devfn_shift; + + where &= PCIE_ECAM_REG_MASK; + map = win + (bus_offset | devfn_offset | where); + } + else + { + map = win + PCIE_ECAM_OFFSET(busn, devfn, where); + } + + return map; +} + +const struct pci_ecam_ops pci_generic_ecam_ops = +{ + .pci_ops = + { + .map = pci_ecam_map, + .read = rt_pci_bus_read_config_uxx, + .write = rt_pci_bus_write_config_uxx, + } +}; diff --git a/rt-thread/components/drivers/pci/ecam.h b/rt-thread/components/drivers/pci/ecam.h new file mode 100644 index 0000000..98fa3eb --- /dev/null +++ b/rt-thread/components/drivers/pci/ecam.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#ifndef __RT_PCI_ECAM_H__ +#define __RT_PCI_ECAM_H__ + +#include +#include +#include +#include + +/* + * Memory address shift values for the byte-level address that + * can be used when accessing the PCI Express Configuration Space. + */ + +/* + * Enhanced Configuration Access Mechanism (ECAM) + * + * See PCI Express Base Specification, Revision 5.0, Version 1.0, + * Section 7.2.2, Table 7-1, p. 677. + */ +#define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */ +#define PCIE_ECAM_DEVFN_SHIFT 12 /* Device and Function number */ + +#define PCIE_ECAM_BUS_MASK 0xff +#define PCIE_ECAM_DEVFN_MASK 0xff +#define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */ + +#define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT) +#define PCIE_ECAM_DEVFN(x) (((x) & PCIE_ECAM_DEVFN_MASK) << PCIE_ECAM_DEVFN_SHIFT) +#define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK) + +#define PCIE_ECAM_OFFSET(bus, devfn, where) \ + (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEVFN(devfn) | PCIE_ECAM_REG(where)) + +struct pci_ecam_ops +{ + rt_uint32_t bus_shift; + const struct rt_pci_ops pci_ops; +}; + +struct pci_ecam_config_window +{ + rt_uint32_t *bus_range; + rt_uint32_t bus_shift; + + void *win; + void *priv; + const struct pci_ecam_ops *ops; +}; + +/* Default ECAM ops */ +extern const struct pci_ecam_ops pci_generic_ecam_ops; + +void *pci_ecam_map(struct rt_pci_bus *bus, rt_uint32_t devfn, int where); +struct pci_ecam_config_window *pci_ecam_create(struct rt_pci_host_bridge *host_bridge, + const struct pci_ecam_ops *ops); +rt_err_t pci_host_common_probe(struct rt_platform_device *pdev); +rt_err_t pci_host_common_remove(struct rt_platform_device *pdev); + +#endif /* __RT_PCI_ECAM_H__ */ diff --git a/rt-thread/components/drivers/pci/endpoint/SConscript b/rt-thread/components/drivers/pci/endpoint/SConscript new file mode 100644 index 0000000..9b76a96 --- /dev/null +++ b/rt-thread/components/drivers/pci/endpoint/SConscript @@ -0,0 +1,15 @@ +from building import * + +group = [] + +if not GetDepend(['RT_PCI_ENDPOINT']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../../include'] + +src = ['endpoint.c', 'mem.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/pci/endpoint/endpoint.c b/rt-thread/components/drivers/pci/endpoint/endpoint.c new file mode 100644 index 0000000..3783f4e --- /dev/null +++ b/rt-thread/components/drivers/pci/endpoint/endpoint.c @@ -0,0 +1,504 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-08-25 GuEe-GUI first version + */ + +#include + +#define DBG_TAG "pci.ep" +#define DBG_LVL DBG_INFO +#include + +static rt_list_t _ep_nodes = RT_LIST_OBJECT_INIT(_ep_nodes); +static struct rt_spinlock _ep_lock = { 0 }; + +rt_err_t rt_pci_ep_write_header(struct rt_pci_ep *ep, rt_uint8_t func_no, + struct rt_pci_ep_header *hdr) +{ + rt_err_t err; + + if (ep && ep->ops && hdr && func_no < ep->max_functions) + { + if (ep->ops->write_header) + { + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + err = ep->ops->write_header(ep, func_no, hdr); + rt_mutex_release(&ep->lock); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_ep_set_bar(struct rt_pci_ep *ep, rt_uint8_t func_no, + struct rt_pci_ep_bar *bar, int bar_idx) +{ + rt_err_t err = RT_EOK; + + if (ep && ep->ops && func_no < ep->max_functions && bar && + bar_idx < PCI_STD_NUM_BARS) + { + struct rt_pci_bus_resource *bus_bar = &bar->bus; + + if (bar_idx == (PCI_STD_NUM_BARS - 1) && + (bus_bar->flags & PCIM_BAR_MEM_TYPE_64)) + { + err = -RT_EINVAL; + LOG_E("%s: Set BAR[%d] can't not 64bit", ep->name, bar_idx); + } + + if (rt_upper_32_bits(bus_bar->size) && + !(bus_bar->flags & PCIM_BAR_MEM_TYPE_64)) + { + err = -RT_EINVAL; + LOG_E("%s: Set BAR[%d] size is no support 64bit", ep->name, bar_idx); + } + + if ((bus_bar->flags & PCIM_BAR_SPACE_IO) && + (bus_bar->flags & PCIM_BAR_IO_MASK)) + { + err = -RT_EINVAL; + LOG_E("%s: Set BAR[%d] io flags is invalid", ep->name, bar_idx); + } + + if (!err) + { + if (ep->ops->set_bar) + { + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + err = ep->ops->set_bar(ep, func_no, bar, bar_idx); + rt_mutex_release(&ep->lock); + } + else + { + err = -RT_ENOSYS; + } + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_ep_clear_bar(struct rt_pci_ep *ep, rt_uint8_t func_no, + struct rt_pci_ep_bar *bar, int bar_idx) +{ + rt_err_t err; + + if (ep && ep->ops && func_no < ep->max_functions && bar && + bar_idx < PCI_STD_NUM_BARS) + { + if (ep->ops->clear_bar) + { + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + err = ep->ops->clear_bar(ep, func_no, bar, bar_idx); + rt_mutex_release(&ep->lock); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_ep_map_addr(struct rt_pci_ep *ep, rt_uint8_t func_no, + rt_ubase_t addr, rt_uint64_t pci_addr, rt_size_t size) +{ + rt_err_t err; + + if (ep && ep->ops && func_no < ep->max_functions && size) + { + if (ep->ops->map_addr) + { + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + err = ep->ops->map_addr(ep, func_no, addr, pci_addr, size); + rt_mutex_release(&ep->lock); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_ep_unmap_addr(struct rt_pci_ep *ep, rt_uint8_t func_no, + rt_ubase_t addr) +{ + rt_err_t err; + + if (ep && ep->ops && func_no < ep->max_functions) + { + if (ep->ops->unmap_addr) + { + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + err = ep->ops->unmap_addr(ep, func_no, addr); + rt_mutex_release(&ep->lock); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_ep_set_msi(struct rt_pci_ep *ep, rt_uint8_t func_no, + unsigned irq_nr) +{ + rt_err_t err; + + if (ep && ep->ops && func_no < ep->max_functions) + { + if (ep->ops->set_msix) + { + err = -RT_EINVAL; + + for (int log2 = 0; log2 < 5; ++log2) + { + if (irq_nr <= (1 << log2)) + { + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + err = ep->ops->set_msi(ep, func_no, log2); + rt_mutex_release(&ep->lock); + } + } + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_ep_get_msi(struct rt_pci_ep *ep, rt_uint8_t func_no, + unsigned *out_irq_nr) +{ + rt_err_t err; + + if (ep && ep->ops && func_no < ep->max_functions && out_irq_nr) + { + if (ep->ops->get_msi) + { + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + err = ep->ops->get_msi(ep, func_no, out_irq_nr); + rt_mutex_release(&ep->lock); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_ep_set_msix(struct rt_pci_ep *ep, rt_uint8_t func_no, + unsigned irq_nr, int bar_idx, rt_off_t offset) +{ + rt_err_t err; + + if (ep && ep->ops && func_no < ep->max_functions && irq_nr < 2048 && + bar_idx < PCI_STD_NUM_BARS) + { + if (ep->ops->set_msix) + { + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + err = ep->ops->set_msix(ep, func_no, irq_nr, bar_idx, offset); + rt_mutex_release(&ep->lock); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_ep_get_msix(struct rt_pci_ep *ep, rt_uint8_t func_no, + unsigned *out_irq_nr) +{ + rt_err_t err; + + if (ep && ep->ops && func_no < ep->max_functions && out_irq_nr) + { + if (ep->ops->get_msix) + { + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + err = ep->ops->get_msix(ep, func_no, out_irq_nr); + rt_mutex_release(&ep->lock); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_ep_raise_irq(struct rt_pci_ep *ep, rt_uint8_t func_no, + enum rt_pci_ep_irq type, unsigned irq) +{ + rt_err_t err; + + if (ep && ep->ops && func_no < ep->max_functions) + { + if (ep->ops->raise_irq) + { + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + err = ep->ops->raise_irq(ep, func_no, type, irq); + rt_mutex_release(&ep->lock); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_ep_start(struct rt_pci_ep *ep) +{ + rt_err_t err; + + if (ep && ep->ops) + { + if (ep->ops->start) + { + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + err = ep->ops->start(ep); + rt_mutex_release(&ep->lock); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_ep_stop(struct rt_pci_ep *ep) +{ + rt_err_t err; + + if (ep && ep->ops) + { + if (ep->ops->stop) + { + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + err = ep->ops->stop(ep); + rt_mutex_release(&ep->lock); + } + else + { + err = -RT_ENOSYS; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_ep_register(struct rt_pci_ep *ep) +{ + rt_ubase_t level; + + if (!ep || !ep->ops) + { + return -RT_EINVAL; + } + + rt_list_init(&ep->list); + rt_ref_init(&ep->ref); + + rt_list_init(&ep->epf_nodes); + rt_mutex_init(&ep->lock, ep->name, RT_IPC_FLAG_PRIO); + + level = rt_spin_lock_irqsave(&_ep_lock); + rt_list_insert_before(&_ep_nodes, &ep->list); + rt_spin_unlock_irqrestore(&_ep_lock, level); + + return RT_EOK; +} + +rt_err_t rt_pci_ep_unregister(struct rt_pci_ep *ep) +{ + rt_ubase_t level; + rt_err_t err = RT_EOK; + + if (!ep) + { + return -RT_EINVAL; + } + + level = rt_spin_lock_irqsave(&_ep_lock); + + if (rt_ref_read(&ep->ref) > 1) + { + err = -RT_EBUSY; + } + else + { + rt_list_remove(&ep->list); + rt_mutex_detach(&ep->lock); + } + + rt_spin_unlock_irqrestore(&_ep_lock, level); + + return err; +} + +rt_err_t rt_pci_ep_add_epf(struct rt_pci_ep *ep, struct rt_pci_epf *epf) +{ + rt_err_t err = RT_EOK; + + if (!ep || !epf || !epf->name) + { + return -RT_EINVAL; + } + + if (epf->func_no > ep->max_functions - 1) + { + LOG_E("%s function No(%d) > %s max function No(%d - 1)", + epf->name, epf->func_no, ep->name, ep->max_functions); + + return -RT_EINVAL; + } + + epf->ep = ep; + rt_list_init(&epf->list); + + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + + if (!rt_bitmap_test_bit(ep->functions_map, epf->func_no)) + { + rt_bitmap_set_bit(ep->functions_map, epf->func_no); + rt_list_insert_before(&ep->epf_nodes, &epf->list); + } + else + { + err = -RT_EINVAL; + LOG_E("%s function No(%d) is repeating", epf->name, epf->func_no); + } + + rt_mutex_release(&ep->lock); + + return err; +} + +rt_err_t rt_pci_ep_remove_epf(struct rt_pci_ep *ep, struct rt_pci_epf *epf) +{ + if (!ep || !epf) + { + return -RT_EINVAL; + } + + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + rt_bitmap_clear_bit(ep->functions_map, epf->func_no); + rt_list_remove(&epf->list); + rt_mutex_release(&ep->lock); + + return RT_EOK; +} + +struct rt_pci_ep *rt_pci_ep_get(const char *name) +{ + rt_ubase_t level; + struct rt_pci_ep *ep = RT_NULL, *ep_tmp; + + level = rt_spin_lock_irqsave(&_ep_lock); + + rt_list_for_each_entry(ep_tmp, &_ep_nodes, list) + { + if (!name || !rt_strcmp(ep_tmp->name, name)) + { + ep = ep_tmp; + rt_ref_get(&ep->ref); + break; + } + } + + rt_spin_unlock_irqrestore(&_ep_lock, level); + + return ep; +} + +static void pci_ep_release(struct rt_ref *ref) +{ + struct rt_pci_ep *ep = rt_container_of(ref, struct rt_pci_ep, ref); + + rt_pci_ep_unregister(ep); +} + +void rt_pci_ep_put(struct rt_pci_ep *ep) +{ + if (ep) + { + rt_ref_put(&ep->ref, &pci_ep_release); + } +} diff --git a/rt-thread/components/drivers/pci/endpoint/mem.c b/rt-thread/components/drivers/pci/endpoint/mem.c new file mode 100644 index 0000000..297db16 --- /dev/null +++ b/rt-thread/components/drivers/pci/endpoint/mem.c @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-08-25 GuEe-GUI first version + */ + +#include + +#define DBG_TAG "pci.ep.mem" +#define DBG_LVL DBG_INFO +#include + +rt_err_t rt_pci_ep_mem_array_init(struct rt_pci_ep *ep, + struct rt_pci_ep_mem *mems, rt_size_t mems_nr) +{ + rt_size_t idx; + rt_err_t err = RT_EOK; + + if (!ep || !mems) + { + return -RT_EINVAL; + } + + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + + ep->mems_nr = mems_nr; + ep->mems = rt_calloc(mems_nr, sizeof(*ep->mems)); + + if (!ep->mems) + { + return -RT_ENOMEM; + } + + for (idx = 0; idx < mems_nr; ++idx) + { + struct rt_pci_ep_mem *mem = &ep->mems[idx]; + + mem->cpu_addr = mems->cpu_addr; + mem->size = mems->size; + mem->page_size = mems->page_size; + mem->bits = mems->size / mems->page_size; + mem->map = rt_calloc(RT_BITMAP_LEN(mem->bits), sizeof(*mem->map)); + + if (!mem->map) + { + err = -RT_ENOMEM; + goto _out_lock; + } + } + +_out_lock: + if (err) + { + while (idx --> 0) + { + rt_free(ep->mems[idx].map); + } + rt_free(ep->mems); + + ep->mems_nr = 0; + ep->mems = RT_NULL; + } + + rt_mutex_release(&ep->lock); + + return err; +} + +rt_err_t rt_pci_ep_mem_init(struct rt_pci_ep *ep, + rt_ubase_t cpu_addr, rt_size_t size, rt_size_t page_size) +{ + struct rt_pci_ep_mem mem; + + if (!ep) + { + return -RT_EINVAL; + } + + mem.cpu_addr = cpu_addr; + mem.size = size; + mem.page_size = page_size; + + return rt_pci_ep_mem_array_init(ep, &mem, 1); +} + +static rt_ubase_t bitmap_region_alloc(struct rt_pci_ep_mem *mem, rt_size_t size) +{ + rt_size_t bit, next_bit, end_bit, max_bits; + + size /= mem->page_size; + max_bits = mem->bits - size; + + rt_bitmap_for_each_clear_bit(mem->map, bit, max_bits) + { + end_bit = bit + size; + + for (next_bit = bit + 1; next_bit < end_bit; ++next_bit) + { + if (rt_bitmap_test_bit(mem->map, next_bit)) + { + bit = next_bit; + goto _next; + } + } + + if (next_bit == end_bit) + { + while (next_bit --> bit) + { + rt_bitmap_set_bit(mem->map, next_bit); + } + + return mem->cpu_addr + bit * mem->page_size; + } + _next: + } + + return ~0ULL; +} + +static void bitmap_region_free(struct rt_pci_ep_mem *mem, + rt_ubase_t cpu_addr, rt_size_t size) +{ + rt_size_t bit = (cpu_addr - mem->cpu_addr) / mem->page_size, end_bit; + + size /= mem->page_size; + end_bit = bit + size; + + for (; bit < end_bit; ++bit) + { + rt_bitmap_clear_bit(mem->map, bit); + } +} + +void *rt_pci_ep_mem_alloc(struct rt_pci_ep *ep, + rt_ubase_t *out_cpu_addr, rt_size_t size) +{ + void *vaddr = RT_NULL; + + if (!ep || !out_cpu_addr) + { + return vaddr; + } + + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + + for (rt_size_t idx = 0; idx < ep->mems_nr; ++idx) + { + rt_ubase_t cpu_addr; + struct rt_pci_ep_mem *mem = &ep->mems[idx]; + + cpu_addr = bitmap_region_alloc(mem, size); + + if (cpu_addr != ~0ULL) + { + vaddr = rt_ioremap((void *)cpu_addr, size); + + if (!vaddr) + { + bitmap_region_free(mem, cpu_addr, size); + + /* Try next memory */ + continue; + } + + *out_cpu_addr = cpu_addr; + break; + } + } + + rt_mutex_release(&ep->lock); + + return vaddr; +} + +void rt_pci_ep_mem_free(struct rt_pci_ep *ep, + void *vaddr, rt_ubase_t cpu_addr, rt_size_t size) +{ + if (!ep || !vaddr || !size) + { + return; + } + + rt_mutex_take(&ep->lock, RT_WAITING_FOREVER); + + for (rt_size_t idx = 0; idx < ep->mems_nr; ++idx) + { + struct rt_pci_ep_mem *mem = &ep->mems[idx]; + + if (mem->cpu_addr > cpu_addr && + mem->cpu_addr + mem->size >= cpu_addr + size) + { + rt_iounmap(mem); + bitmap_region_free(mem, cpu_addr, size); + + break; + } + } + + rt_mutex_release(&ep->lock); +} diff --git a/rt-thread/components/drivers/pci/host-bridge.c b/rt-thread/components/drivers/pci/host-bridge.c new file mode 100644 index 0000000..ada7ef6 --- /dev/null +++ b/rt-thread/components/drivers/pci/host-bridge.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#include + +#include +#include + +#ifdef RT_USING_PM +struct host_bridge_pm_status +{ + rt_uint8_t mode; + rt_bool_t enable; +}; + +static const enum rt_pci_power system_pci_pm_mode[] = +{ + [PM_SLEEP_MODE_NONE] = RT_PCI_D0, + [PM_SLEEP_MODE_IDLE] = RT_PCI_D3HOT, + [PM_SLEEP_MODE_LIGHT] = RT_PCI_D1, + [PM_SLEEP_MODE_DEEP] = RT_PCI_D1, + [PM_SLEEP_MODE_STANDBY] = RT_PCI_D2, + [PM_SLEEP_MODE_SHUTDOWN] = RT_PCI_D3COLD, +}; + +static rt_bool_t pci_device_pm_ops(struct rt_pci_device *pdev, void *data) +{ + struct host_bridge_pm_status *status = data; + + rt_pci_enable_wake(pdev, system_pci_pm_mode[status->mode], status->enable); + + /* To find all devices, always return false */ + return RT_FALSE; +} + +static rt_err_t host_bridge_pm_suspend(const struct rt_device *device, rt_uint8_t mode) +{ + struct host_bridge_pm_status status; + struct rt_pci_device *pdev = rt_container_of(device, struct rt_pci_device, parent); + + status.mode = mode; + status.enable = RT_FALSE; + rt_pci_enum_device(pdev->bus, pci_device_pm_ops, &status); + + return RT_EOK; +} + +static void host_bridge_pm_resume(const struct rt_device *device, rt_uint8_t mode) +{ + struct host_bridge_pm_status status; + struct rt_pci_device *pdev = rt_container_of(device, struct rt_pci_device, parent); + + status.mode = mode; + status.enable = RT_TRUE; + rt_pci_enum_device(pdev->bus, pci_device_pm_ops, &status); +} + +static const struct rt_device_pm_ops host_bridge_pm_ops = +{ + .suspend = host_bridge_pm_suspend, + .resume = host_bridge_pm_resume, +}; +#endif /* RT_USING_PM */ + +static void host_bridge_free(struct rt_pci_device *pdev) +{ +#ifdef RT_USING_PM + rt_pm_device_unregister(&pdev->parent); +#endif +} + +static rt_err_t host_bridge_probe(struct rt_pci_device *pdev) +{ + rt_err_t err = RT_EOK; + + rt_pci_set_master(pdev); + +#ifdef RT_USING_PM + rt_pm_device_register(&pdev->parent, &host_bridge_pm_ops); +#endif + + return err; +} + +static rt_err_t host_bridge_remove(struct rt_pci_device *pdev) +{ + host_bridge_free(pdev); + rt_pci_clear_master(pdev); + + return RT_EOK; +} + +static rt_err_t host_bridge_shutdown(struct rt_pci_device *pdev) +{ + host_bridge_free(pdev); + + return RT_EOK; +} + +static const struct rt_pci_device_id host_bridge_pci_ids[] = +{ + /* PCI host bridges */ + { RT_PCI_DEVICE_ID(PCI_VENDOR_ID_REDHAT, 0x0008) }, + /* Any PCI-Express port */ + { RT_PCI_DEVICE_CLASS(PCIS_BRIDGE_PCI_NORMAL, ~0) }, + /* PCI-to-PCI bridge */ + { RT_PCI_DEVICE_CLASS(PCIS_BRIDGE_PCI_SUBTRACTIVE, ~0) }, + /* Any Root Complex Event Collector */ + { RT_PCI_DEVICE_CLASS(((PCIS_SYSTEM_RCEC << 8) | 0x00), ~0) }, + { /* sentinel */ } +}; + +static struct rt_pci_driver host_bridge_driver = +{ + .name = "host-bridge", + + .ids = host_bridge_pci_ids, + .probe = host_bridge_probe, + .remove = host_bridge_remove, + .shutdown = host_bridge_shutdown, +}; +RT_PCI_DRIVER_EXPORT(host_bridge_driver); diff --git a/rt-thread/components/drivers/pci/host/Kconfig b/rt-thread/components/drivers/pci/host/Kconfig new file mode 100644 index 0000000..221c997 --- /dev/null +++ b/rt-thread/components/drivers/pci/host/Kconfig @@ -0,0 +1,12 @@ +config RT_PCI_HOST_COMMON + bool "Common PCI host controller" + depends on RT_PCI_ECAM + default y + +config RT_PCI_HOST_GENERIC + bool "Generic PCI host controller" + depends on RT_PCI_ECAM + select RT_PCI_HOST_COMMON + default y + +rsource "dw/Kconfig" diff --git a/rt-thread/components/drivers/pci/host/SConscript b/rt-thread/components/drivers/pci/host/SConscript new file mode 100644 index 0000000..91555f8 --- /dev/null +++ b/rt-thread/components/drivers/pci/host/SConscript @@ -0,0 +1,25 @@ +from building import * + +objs = [] + +cwd = GetCurrentDir() +list = os.listdir(cwd) +CPPPATH = [cwd + '/../../include'] + +src = [] + +if GetDepend(['RT_PCI_HOST_COMMON']): + src += ['pci-host-common.c'] + +if GetDepend(['RT_PCI_HOST_GENERIC']): + src += ['pci-host-generic.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +objs = objs + group + +Return('objs') diff --git a/rt-thread/components/drivers/pci/host/dw/Kconfig b/rt-thread/components/drivers/pci/host/dw/Kconfig new file mode 100644 index 0000000..e76011b --- /dev/null +++ b/rt-thread/components/drivers/pci/host/dw/Kconfig @@ -0,0 +1,13 @@ +config RT_PCI_DW + bool "DesignWare-based PCIe" + depends on RT_MFD_SYSCON + depends on RT_USING_DMA + default n + +config RT_PCI_DW_HOST + bool + depends on RT_PCI_DW + +config RT_PCI_DW_EP + bool + depends on RT_PCI_DW diff --git a/rt-thread/components/drivers/pci/host/dw/SConscript b/rt-thread/components/drivers/pci/host/dw/SConscript new file mode 100644 index 0000000..ca6c031 --- /dev/null +++ b/rt-thread/components/drivers/pci/host/dw/SConscript @@ -0,0 +1,21 @@ +from building import * + +group = [] + +if not GetDepend(['RT_PCI_DW']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../../../include'] + +src = ['pcie-dw.c', 'pcie-dw_platfrom.c'] + +if GetDepend(['RT_PCI_DW_HOST']): + src += ['pcie-dw_host.c'] + +if GetDepend(['RT_PCI_DW_EP']): + src += ['pcie-dw_ep.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/pci/host/dw/pcie-dw.c b/rt-thread/components/drivers/pci/host/dw/pcie-dw.c new file mode 100644 index 0000000..2cca6f1 --- /dev/null +++ b/rt-thread/components/drivers/pci/host/dw/pcie-dw.c @@ -0,0 +1,645 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#define DBG_TAG "pcie.dw" +#define DBG_LVL DBG_INFO +#include + +#include "pcie-dw.h" + +static rt_uint8_t __dw_pcie_find_next_cap(struct dw_pcie *pci, + rt_uint8_t cap_ptr, rt_uint8_t cap) +{ + rt_uint16_t reg; + rt_uint8_t cap_id, next_cap_ptr; + + if (!cap_ptr) + { + return 0; + } + + reg = dw_pcie_readw_dbi(pci, cap_ptr); + cap_id = (reg & 0x00ff); + + if (cap_id > PCIY_MAX) + { + return 0; + } + + if (cap_id == cap) + { + return cap_ptr; + } + + next_cap_ptr = (reg & 0xff00) >> 8; + return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); +} + +rt_uint8_t dw_pcie_find_capability(struct dw_pcie *pci, rt_uint8_t cap) +{ + rt_uint16_t reg; + rt_uint8_t next_cap_ptr; + + reg = dw_pcie_readw_dbi(pci, PCIR_CAP_PTR); + next_cap_ptr = (reg & 0x00ff); + + return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); +} + +static rt_uint16_t dw_pcie_find_next_ext_capability(struct dw_pcie *pci, + rt_uint16_t start, rt_uint8_t cap) +{ + rt_uint32_t header; + int ttl, pos = PCI_REGMAX + 1; + + /* minimum 8 bytes per capability */ + ttl = ((PCIE_REGMAX + 1) - (PCI_REGMAX + 1)) / 8; + + if (start) + { + pos = start; + } + + header = dw_pcie_readl_dbi(pci, pos); + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + { + return 0; + } + + while (ttl-- > 0) + { + if (PCI_EXTCAP_ID(header) == cap && pos != start) + { + return pos; + } + + pos = PCI_EXTCAP_NEXTPTR(header); + + if (pos < PCI_REGMAX + 1) + { + break; + } + + header = dw_pcie_readl_dbi(pci, pos); + } + + return 0; +} + +rt_uint16_t dw_pcie_find_ext_capability(struct dw_pcie *pci, rt_uint8_t cap) +{ + return dw_pcie_find_next_ext_capability(pci, 0, cap); +} + +rt_err_t dw_pcie_read(void *addr, rt_size_t size, rt_uint32_t *out_val) +{ + /* Check aligned */ + if ((rt_ubase_t)addr & ((rt_ubase_t)size - 1)) + { + *out_val = 0; + return -RT_EINVAL; + } + + if (size == 4) + { + *out_val = HWREG32(addr); + } + else if (size == 2) + { + *out_val = HWREG16(addr); + } + else if (size == 1) + { + *out_val = HWREG8(addr); + } + else + { + *out_val = 0; + return -RT_EINVAL; + } + + return RT_EOK; +} + +rt_err_t dw_pcie_write(void *addr, rt_size_t size, rt_uint32_t val) +{ + /* Check aligned */ + if ((rt_ubase_t)addr & ((rt_ubase_t)size - 1)) + { + return -RT_EINVAL; + } + + if (size == 4) + { + HWREG32(addr) = val; + } + else if (size == 2) + { + HWREG16(addr) = val; + } + else if (size == 1) + { + HWREG8(addr) = val; + } + else + { + return -RT_EINVAL; + } + + return RT_EOK; +} + +rt_uint32_t dw_pcie_read_dbi(struct dw_pcie *pci, rt_uint32_t reg, rt_size_t size) +{ + rt_err_t err; + rt_uint32_t val = 0; + + if (pci->ops->read_dbi) + { + return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); + } + + if ((err = dw_pcie_read(pci->dbi_base + reg, size, &val))) + { + LOG_E("Read DBI address error = %s", rt_strerror(err)); + } + + return val; +} + +void dw_pcie_write_dbi(struct dw_pcie *pci, rt_uint32_t reg, rt_size_t size, rt_uint32_t val) +{ + rt_err_t err; + + if (pci->ops->write_dbi) + { + pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); + return; + } + + if ((err = dw_pcie_write(pci->dbi_base + reg, size, val))) + { + LOG_E("Write DBI address error = %s", rt_strerror(err)); + } +} + +void dw_pcie_write_dbi2(struct dw_pcie *pci, rt_uint32_t reg, rt_size_t size, rt_uint32_t val) +{ + rt_err_t err; + + if (pci->ops && pci->ops->write_dbi2) + { + pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); + return; + } + + if ((err = dw_pcie_write(pci->dbi_base2 + reg, size, val))) + { + LOG_E("Write DBI2 address error = %s", rt_strerror(err)); + } +} + +rt_uint32_t dw_pcie_readl_atu(struct dw_pcie *pci, rt_uint32_t reg) +{ + rt_err_t err; + rt_uint32_t val = 0; + + if (pci->ops->read_dbi) + { + return pci->ops->read_dbi(pci, pci->atu_base, reg, 4); + } + + if ((err = dw_pcie_read(pci->atu_base + reg, 4, &val))) + { + LOG_E("Read ATU address error = %s", rt_strerror(err)); + } + + return val; +} + +void dw_pcie_writel_atu(struct dw_pcie *pci, rt_uint32_t reg, rt_uint32_t val) +{ + rt_err_t err; + + if (pci->ops->write_dbi) + { + pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val); + return; + } + + if ((err = dw_pcie_write(pci->atu_base + reg, 4, val))) + { + LOG_E("Write ATU address error = %s", rt_strerror(err)); + } +} + +static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, rt_uint8_t func_no, + int index, int type, rt_uint64_t cpu_addr, rt_uint64_t pci_addr, rt_size_t size) +{ + rt_uint64_t limit_addr = cpu_addr + size - 1; + + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, + rt_lower_32_bits(cpu_addr)); + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, + rt_upper_32_bits(cpu_addr)); + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_LIMIT, + rt_lower_32_bits(limit_addr)); + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT, + rt_upper_32_bits(limit_addr)); + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, + rt_lower_32_bits(pci_addr)); + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, + rt_upper_32_bits(pci_addr)); + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, + type | PCIE_ATU_FUNC_NUM(func_no)); + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, + PCIE_ATU_ENABLE); + + /* + * Make sure ATU enable takes effect before any subsequent config + * and I/O accesses. + */ + for (int retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; ++retries) + { + if (dw_pcie_readl_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2) & PCIE_ATU_ENABLE) + { + return; + } + + rt_thread_mdelay(LINK_WAIT_IATU); + } + + LOG_E("Outbound iATU is not being enabled"); +} + +static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, rt_uint8_t func_no, + int index, int type, rt_uint64_t cpu_addr, rt_uint64_t pci_addr, rt_size_t size) +{ + if (pci->ops->cpu_addr_fixup) + { + cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); + } + + if (pci->iatu_unroll_enabled & DWC_IATU_UNROLL_EN) + { + dw_pcie_prog_outbound_atu_unroll(pci, func_no, + index, type, cpu_addr, pci_addr, size); + + return; + } + + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | index); + dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE, rt_lower_32_bits(cpu_addr)); + dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE, rt_upper_32_bits(cpu_addr)); + dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT, rt_lower_32_bits(cpu_addr + size - 1)); + dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, rt_lower_32_bits(pci_addr)); + dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, rt_upper_32_bits(pci_addr)); + dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type | PCIE_ATU_FUNC_NUM(func_no)); + dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE); + + /* + * Make sure ATU enable takes effect before any subsequent config + * and I/O accesses. + */ + for (int retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; ++retries) + { + if (dw_pcie_readl_dbi(pci, PCIE_ATU_CR2) & PCIE_ATU_ENABLE) + { + return; + } + + rt_thread_mdelay(LINK_WAIT_IATU); + } + + LOG_E("Outbound iATU is not being enabled"); +} + +void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, + int index, int type, rt_uint64_t cpu_addr, rt_uint64_t pci_addr, rt_size_t size) +{ + __dw_pcie_prog_outbound_atu(pci, 0, index, type, cpu_addr, pci_addr, size); +} + +void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, rt_uint8_t func_no, + int index, int type, rt_uint64_t cpu_addr, rt_uint64_t pci_addr, rt_size_t size) +{ + __dw_pcie_prog_outbound_atu(pci, func_no, index, type, cpu_addr, pci_addr, size); +} + +static rt_err_t dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, + rt_uint8_t func_no, int index, int bar, rt_uint64_t cpu_addr, + enum dw_pcie_aspace_type aspace_type) +{ + int type; + + dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, + rt_lower_32_bits(cpu_addr)); + dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, + rt_upper_32_bits(cpu_addr)); + + switch (aspace_type) + { + case DW_PCIE_ASPACE_MEM: + type = PCIE_ATU_TYPE_MEM; + break; + + case DW_PCIE_ASPACE_IO: + type = PCIE_ATU_TYPE_IO; + break; + + default: + return -RT_EINVAL; + } + + dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, + type | PCIE_ATU_FUNC_NUM(func_no)); + dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, + PCIE_ATU_FUNC_NUM_MATCH_EN | PCIE_ATU_ENABLE | + PCIE_ATU_BAR_MODE_ENABLE | (bar << 8)); + + /* + * Make sure ATU enable takes effect before any subsequent config + * and I/O accesses. + */ + for (int retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; ++retries) + { + if (dw_pcie_readl_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2) & PCIE_ATU_ENABLE) + { + return RT_EOK; + } + + rt_thread_mdelay(LINK_WAIT_IATU); + } + + LOG_E("Inbound iATU is not being enabled"); + + return -RT_EBUSY; +} + +rt_err_t dw_pcie_prog_inbound_atu(struct dw_pcie *pci, + rt_uint8_t func_no, int index, int bar, rt_uint64_t cpu_addr, + enum dw_pcie_aspace_type aspace_type) +{ + int type; + + if (pci->iatu_unroll_enabled & DWC_IATU_UNROLL_EN) + { + return dw_pcie_prog_inbound_atu_unroll(pci, func_no, + index, bar, cpu_addr, aspace_type); + } + + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND | index); + dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, rt_lower_32_bits(cpu_addr)); + dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, rt_upper_32_bits(cpu_addr)); + + switch (aspace_type) + { + case DW_PCIE_ASPACE_MEM: + type = PCIE_ATU_TYPE_MEM; + break; + + case DW_PCIE_ASPACE_IO: + type = PCIE_ATU_TYPE_IO; + break; + + default: + return -RT_EINVAL; + } + + dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type | PCIE_ATU_FUNC_NUM(func_no)); + dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE | + PCIE_ATU_FUNC_NUM_MATCH_EN | PCIE_ATU_BAR_MODE_ENABLE | (bar << 8)); + + /* + * Make sure ATU enable takes effect before any subsequent config + * and I/O accesses. + */ + for (int retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; ++retries) + { + if (dw_pcie_readl_dbi(pci, PCIE_ATU_CR2) & PCIE_ATU_ENABLE) + { + return RT_EOK; + } + + rt_thread_mdelay(LINK_WAIT_IATU); + } + + LOG_E("Inbound iATU is not being enabled"); + + return -RT_EBUSY; +} + +void dw_pcie_disable_atu(struct dw_pcie *pci, int index, enum dw_pcie_region_type type) +{ + rt_uint32_t region; + + switch (type) + { + case DW_PCIE_REGION_INBOUND: + region = PCIE_ATU_REGION_INBOUND; + break; + + case DW_PCIE_REGION_OUTBOUND: + region = PCIE_ATU_REGION_OUTBOUND; + break; + + default: + return; + } + + if (pci->iatu_unroll_enabled) + { + if (region == PCIE_ATU_REGION_INBOUND) + { + dw_pcie_writel_ib_unroll(pci, index, + PCIE_ATU_UNR_REGION_CTRL2, ~(rt_uint32_t)PCIE_ATU_ENABLE); + } + else + { + dw_pcie_writel_ob_unroll(pci, index, + PCIE_ATU_UNR_REGION_CTRL2, ~(rt_uint32_t)PCIE_ATU_ENABLE); + } + } + else + { + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index); + dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(rt_uint32_t)PCIE_ATU_ENABLE); + } +} + +rt_err_t dw_pcie_wait_for_link(struct dw_pcie *pci) +{ + /* Check if the link is up or not */ + for (int retries = 0; retries < LINK_WAIT_MAX_RETRIES; ++retries) + { + if (dw_pcie_link_up(pci)) + { + LOG_I("%s: Link up", rt_dm_dev_get_name(pci->dev)); + + return RT_EOK; + } + + rt_hw_us_delay((LINK_WAIT_USLEEP_MIN + LINK_WAIT_USLEEP_MAX) >> 1); + } + + LOG_I("PHY link never came up"); + + return -RT_ETIMEOUT; +} + +rt_bool_t dw_pcie_link_up(struct dw_pcie *pci) +{ + rt_uint32_t val; + + if (pci->ops->link_up) + { + return pci->ops->link_up(pci); + } + + val = HWREG32(pci->dbi_base + PCIE_PORT_DEBUG1); + + return (val & PCIE_PORT_DEBUG1_LINK_UP) && (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)); +} + +void dw_pcie_upconfig_setup(struct dw_pcie *pci) +{ + rt_uint32_t val; + + val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL); + val |= PORT_MLTI_UPCFG_SUPPORT; + dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val); +} + +static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, rt_uint32_t link_gen) +{ + rt_uint32_t cap, ctrl2, link_speed; + rt_uint8_t offset = dw_pcie_find_capability(pci, PCIY_EXPRESS); + + cap = dw_pcie_readl_dbi(pci, offset + PCIER_LINK_CAP); + ctrl2 = dw_pcie_readl_dbi(pci, offset + PCIER_LINK_CTL2); + ctrl2 &= ~PCIEM_LNKCTL2_TLS; + + switch (link_gen) + { + case 1: link_speed = PCIEM_LNKCTL2_TLS_2_5GT; break; + case 2: link_speed = PCIEM_LNKCTL2_TLS_5_0GT; break; + case 3: link_speed = PCIEM_LNKCTL2_TLS_8_0GT; break; + case 4: link_speed = PCIEM_LNKCTL2_TLS_16_0GT; break; + default: + /* Use hardware capability */ + link_speed = RT_FIELD_GET(PCIEM_LINK_CAP_MAX_SPEED, cap); + ctrl2 &= ~PCIEM_LNKCTL2_HASD; + break; + } + + dw_pcie_writel_dbi(pci, offset + PCIER_LINK_CTL2, ctrl2 | link_speed); + + cap &= ~((rt_uint32_t)PCIEM_LINK_CAP_MAX_SPEED); + dw_pcie_writel_dbi(pci, offset + PCIER_LINK_CAP, cap | link_speed); +} + +void dw_pcie_setup(struct dw_pcie *pci) +{ + rt_uint32_t val; + struct rt_device *dev = pci->dev; + + if (pci->version >= 0x480a || (!pci->version && dw_pcie_iatu_unroll_enabled(pci))) + { + pci->iatu_unroll_enabled |= DWC_IATU_UNROLL_EN; + + if (!pci->atu_base) + { + pci->atu_base = rt_dm_dev_iomap_by_name(dev, "atu"); + } + + if (!pci->atu_base) + { + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + } + } + + LOG_D("iATU unroll is %sabled", pci->iatu_unroll_enabled & DWC_IATU_UNROLL_EN ? "en" : "dis"); + + if (pci->link_gen > 0) + { + dw_pcie_link_set_max_speed(pci, pci->link_gen); + } + + /* Configure Gen1 N_FTS */ + if (pci->fts_number[0]) + { + val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); + val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK); + val |= PORT_AFR_N_FTS(pci->fts_number[0]); + val |= PORT_AFR_CC_N_FTS(pci->fts_number[0]); + dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); + } + + /* Configure Gen2+ N_FTS */ + if (pci->fts_number[1]) + { + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_N_FTS_MASK; + val |= pci->fts_number[1]; + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + } + + val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); + val &= ~PORT_LINK_FAST_LINK_MODE; + val |= PORT_LINK_DLL_LINK_EN; + dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); + + if (rt_dm_dev_prop_read_bool(dev, "snps,enable-cdm-check")) + { + val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); + val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | PCIE_PL_CHK_REG_CHK_REG_START; + dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); + } + + rt_dm_dev_prop_read_u32(dev, "num-lanes", &pci->num_lanes); + + if (!pci->num_lanes) + { + LOG_D("Using h/w default number of lanes"); + return; + } + + /* Set the number of lanes */ + val &= ~PORT_LINK_FAST_LINK_MODE; + val &= ~PORT_LINK_MODE_MASK; + switch (pci->num_lanes) + { + case 1: val |= PORT_LINK_MODE_1_LANES; break; + case 2: val |= PORT_LINK_MODE_2_LANES; break; + case 4: val |= PORT_LINK_MODE_4_LANES; break; + case 8: val |= PORT_LINK_MODE_8_LANES; break; + default: + LOG_E("Invail num-lanes = %d", pci->num_lanes); + return; + } + dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); + + /* Set link width speed control register */ + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_LINK_WIDTH_MASK; + switch (pci->num_lanes) + { + case 1: val |= PORT_LOGIC_LINK_WIDTH_1_LANES; break; + case 2: val |= PORT_LOGIC_LINK_WIDTH_2_LANES; break; + case 4: val |= PORT_LOGIC_LINK_WIDTH_4_LANES; break; + case 8: val |= PORT_LOGIC_LINK_WIDTH_8_LANES; break; + } + val |= pci->user_speed; + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); +} diff --git a/rt-thread/components/drivers/pci/host/dw/pcie-dw.h b/rt-thread/components/drivers/pci/host/dw/pcie-dw.h new file mode 100644 index 0000000..0a1183f --- /dev/null +++ b/rt-thread/components/drivers/pci/host/dw/pcie-dw.h @@ -0,0 +1,440 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#ifndef __PCIE_DESIGNWARE_H__ +#define __PCIE_DESIGNWARE_H__ + +#include +#include + +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 + +/* Parameters for the waiting for iATU enabled routine */ +#define LINK_WAIT_MAX_IATU_RETRIES 5 +#define LINK_WAIT_IATU 9 + +/* Synopsys-specific PCIe configuration registers */ +#define PCIE_PORT_AFR 0x70c +#define PORT_AFR_N_FTS_MASK RT_GENMASK(15, 8) +#define PORT_AFR_N_FTS(n) RT_FIELD_PREP(PORT_AFR_N_FTS_MASK, n) +#define PORT_AFR_CC_N_FTS_MASK RT_GENMASK(23, 16) +#define PORT_AFR_CC_N_FTS(n) RT_FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, n) +#define PORT_AFR_ENTER_ASPM RT_BIT(30) +#define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24 +#define PORT_AFR_L0S_ENTRANCE_LAT_MASK RT_GENMASK(26, 24) +#define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27 +#define PORT_AFR_L1_ENTRANCE_LAT_MASK RT_GENMASK(29, 27) + +#define PCIE_PORT_LINK_CONTROL 0x710 +#define PORT_LINK_LPBK_ENABLE RT_BIT(2) +#define PORT_LINK_DLL_LINK_EN RT_BIT(5) +#define PORT_LINK_FAST_LINK_MODE RT_BIT(7) +#define PORT_LINK_MODE_MASK RT_GENMASK(21, 16) +#define PORT_LINK_MODE(n) RT_FIELD_PREP(PORT_LINK_MODE_MASK, n) +#define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1) +#define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3) +#define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7) +#define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf) + +#define PCIE_PORT_DEBUG0 0x728 +#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f +#define PORT_LOGIC_LTSSM_STATE_L0 0x11 +#define PCIE_PORT_DEBUG1 0x72c +#define PCIE_PORT_DEBUG1_LINK_UP RT_BIT(4) +#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING RT_BIT(29) + +#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c +#define PORT_LOGIC_N_FTS_MASK RT_GENMASK(7, 0) +#define PORT_LOGIC_SPEED_CHANGE RT_BIT(17) +#define PORT_LOGIC_LINK_WIDTH_MASK RT_GENMASK(12, 8) +#define PORT_LOGIC_LINK_WIDTH(n) RT_FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n) +#define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1) +#define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2) +#define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4) +#define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8) + +#define PCIE_MSI_ADDR_LO 0x820 +#define PCIE_MSI_ADDR_HI 0x824 +#define PCIE_MSI_INTR0_ENABLE 0x828 +#define PCIE_MSI_INTR0_MASK 0x82c +#define PCIE_MSI_INTR0_STATUS 0x830 + +#define PCIE_PORT_MULTI_LANE_CTRL 0x8c0 +#define PORT_MLTI_UPCFG_SUPPORT RT_BIT(7) + +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND RT_BIT(31) +#define PCIE_ATU_REGION_OUTBOUND 0 +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM 0x0 +#define PCIE_ATU_TYPE_IO 0x2 +#define PCIE_ATU_TYPE_CFG0 0x4 +#define PCIE_ATU_TYPE_CFG1 0x5 +#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE RT_BIT(31) +#define PCIE_ATU_BAR_MODE_ENABLE RT_BIT(30) +#define PCIE_ATU_FUNC_NUM_MATCH_EN RT_BIT(19) +#define PCIE_ATU_LOWER_BASE 0x90c +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS(x) RT_FIELD_PREP(RT_GENMASK(31, 24), x) +#define PCIE_ATU_DEV(x) RT_FIELD_PREP(RT_GENMASK(23, 19), x) +#define PCIE_ATU_FUNC(x) RT_FIELD_PREP(RT_GENMASK(18, 16), x) +#define PCIE_ATU_UPPER_TARGET 0x91c + +#define PCIE_MISC_CONTROL_1_OFF 0x8bc +#define PCIE_DBI_RO_WR_EN RT_BIT(0) + +#define PCIE_MSIX_DOORBELL 0x948 +#define PCIE_MSIX_DOORBELL_PF_SHIFT 24 + +#define PCIE_PL_CHK_REG_CONTROL_STATUS 0xb20 +#define PCIE_PL_CHK_REG_CHK_REG_START RT_BIT(0) +#define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS RT_BIT(1) +#define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR RT_BIT(16) +#define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR RT_BIT(17) +#define PCIE_PL_CHK_REG_CHK_REG_COMPLETE RT_BIT(18) + +#define PCIE_PL_CHK_REG_ERR_ADDR 0xb28 + +/* + * iATU Unroll-specific register definitions + * From 4.80 core version the address translation will be made by unroll + */ +#define PCIE_ATU_UNR_REGION_CTRL1 0x00 +#define PCIE_ATU_UNR_REGION_CTRL2 0x04 +#define PCIE_ATU_UNR_LOWER_BASE 0x08 +#define PCIE_ATU_UNR_UPPER_BASE 0x0C +#define PCIE_ATU_UNR_LOWER_LIMIT 0x10 +#define PCIE_ATU_UNR_LOWER_TARGET 0x14 +#define PCIE_ATU_UNR_UPPER_TARGET 0x18 +#define PCIE_ATU_UNR_UPPER_LIMIT 0x20 + +/* + * The default address offset between dbi_base and atu_base. Root controller + * drivers are not required to initialize atu_base if the offset matches this + * default; the driver core automatically derives atu_base from dbi_base using + * this offset, if atu_base not set. + */ +#define DEFAULT_DBI_ATU_OFFSET (0x3 << 20) + +/* Register address builder */ +#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9) +#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) (((region) << 9) | RT_BIT(8)) + +#define MAX_MSI_IRQS 256 +#define MAX_MSI_IRQS_PER_CTRL 32 +#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL) +#define MSI_REG_CTRL_BLOCK_SIZE 12 +#define MSI_DEF_NUM_VECTORS 32 + +/* Maximum number of inbound/outbound iATUs */ +#define MAX_IATU_IN 256 +#define MAX_IATU_OUT 256 + +#define DWC_IATU_UNROLL_EN RT_BIT(0) +#define DWC_IATU_IOCFG_SHARED RT_BIT(1) + +struct dw_pcie_host_ops; +struct dw_pcie_ep_ops; +struct dw_pcie_ops; + +enum dw_pcie_region_type +{ + DW_PCIE_REGION_UNKNOWN, + DW_PCIE_REGION_INBOUND, + DW_PCIE_REGION_OUTBOUND, +}; + +enum dw_pcie_device_mode +{ + DW_PCIE_UNKNOWN_TYPE, + DW_PCIE_EP_TYPE, + DW_PCIE_LEG_EP_TYPE, + DW_PCIE_RC_TYPE, +}; + +enum dw_pcie_aspace_type +{ + DW_PCIE_ASPACE_UNKNOWN, + DW_PCIE_ASPACE_MEM, + DW_PCIE_ASPACE_IO, +}; + +struct dw_pcie_port +{ + void *cfg0_base; + rt_uint64_t cfg0_addr; + rt_uint64_t cfg0_size; + + rt_ubase_t io_addr; + rt_ubase_t io_bus_addr; + rt_size_t io_size; + + const struct dw_pcie_host_ops *ops; + + int sys_irq; + int msi_irq; + struct rt_pic *irq_pic; + struct rt_pic *msi_pic; + + void *msi_data; + rt_ubase_t msi_data_phy; + + rt_uint32_t irq_count; + rt_uint32_t irq_mask[MAX_MSI_CTRLS]; + + struct rt_pci_host_bridge *bridge; + const struct rt_pci_ops *bridge_child_ops; + + struct rt_spinlock lock; + RT_BITMAP_DECLARE(msi_map, MAX_MSI_IRQS); +}; + +struct dw_pcie_host_ops +{ + rt_err_t (*host_init)(struct dw_pcie_port *port); + rt_err_t (*msi_host_init)(struct dw_pcie_port *port); + void (*set_irq_count)(struct dw_pcie_port *port); +}; + +struct dw_pcie_ep_func +{ + rt_list_t list; + + rt_uint8_t func_no; + rt_uint8_t msi_cap; /* MSI capability offset */ + rt_uint8_t msix_cap; /* MSI-X capability offset */ +}; + +struct dw_pcie_ep +{ + struct rt_pci_ep *epc; + struct rt_pci_ep_bar *epc_bar[PCI_STD_NUM_BARS]; + + rt_list_t func_nodes; + + const struct dw_pcie_ep_ops *ops; + + rt_uint64_t aspace; + rt_uint64_t aspace_size; + rt_size_t page_size; + + rt_uint8_t bar_to_atu[PCI_STD_NUM_BARS]; + rt_ubase_t *outbound_addr; + + rt_bitmap_t *ib_window_map; + rt_bitmap_t *ob_window_map; + rt_uint32_t num_ib_windows; + rt_uint32_t num_ob_windows; + + void *msi_mem; + rt_ubase_t msi_mem_phy; +}; + +struct dw_pcie_ep_ops +{ + rt_err_t (*ep_init)(struct dw_pcie_ep *ep); + rt_err_t (*raise_irq)(struct dw_pcie_ep *ep, rt_uint8_t func_no, enum rt_pci_ep_irq type, unsigned irq); + rt_off_t (*func_select)(struct dw_pcie_ep *ep, rt_uint8_t func_no); +}; + +struct dw_pcie +{ + struct rt_device *dev; + + void *dbi_base; + void *dbi_base2; + void *atu_base; + + rt_uint32_t version; + rt_uint32_t num_viewport; + rt_uint32_t num_lanes; + rt_uint32_t link_gen; + rt_uint32_t user_speed; + rt_uint8_t iatu_unroll_enabled; /* Internal Address Translation Unit */ + rt_uint8_t fts_number[2]; /* Fast Training Sequences */ + + struct dw_pcie_port port; + struct dw_pcie_ep endpoint; + const struct dw_pcie_ops *ops; + + void *priv; +}; + +struct dw_pcie_ops +{ + rt_uint64_t (*cpu_addr_fixup)(struct dw_pcie *pcie, rt_uint64_t cpu_addr); + rt_uint32_t (*read_dbi)(struct dw_pcie *pcie, void *base, rt_uint32_t reg, rt_size_t size); + void (*write_dbi)(struct dw_pcie *pcie, void *base, rt_uint32_t reg, rt_size_t size, rt_uint32_t val); + void (*write_dbi2)(struct dw_pcie *pcie, void *base, rt_uint32_t reg, rt_size_t size, rt_uint32_t val); + rt_bool_t (*link_up)(struct dw_pcie *pcie); + rt_err_t (*start_link)(struct dw_pcie *pcie); + void (*stop_link)(struct dw_pcie *pcie); +}; + +#define to_dw_pcie_from_port(ptr) rt_container_of((ptr), struct dw_pcie, port) +#define to_dw_pcie_from_endpoint(ptr) rt_container_of((ptr), struct dw_pcie, endpoint) + +#ifdef RT_PCI_DW_HOST +#undef RT_PCI_DW_HOST +#define RT_PCI_DW_HOST 1 +#define HOST_API +#define HOST_RET(...) ; +#else +#define HOST_API rt_inline +#define HOST_RET(...) { return __VA_ARGS__; } +#endif + +#ifdef RT_PCI_DW_EP +#undef RT_PCI_DW_EP +#define RT_PCI_DW_EP 1 +#define EP_API +#define EP_RET(...) ; +#else +#define EP_API rt_inline +#define EP_RET(...) { return __VA_ARGS__; } +#endif + +rt_uint8_t dw_pcie_find_capability(struct dw_pcie *pci, rt_uint8_t cap); +rt_uint16_t dw_pcie_find_ext_capability(struct dw_pcie *pci, rt_uint8_t cap); + +rt_err_t dw_pcie_read(void *addr, rt_size_t size, rt_uint32_t *out_val); +rt_err_t dw_pcie_write(void *addr, rt_size_t size, rt_uint32_t val); + +rt_uint32_t dw_pcie_read_dbi(struct dw_pcie *pci, rt_uint32_t reg, rt_size_t size); +void dw_pcie_write_dbi(struct dw_pcie *pci, rt_uint32_t reg, rt_size_t size, rt_uint32_t val); +void dw_pcie_write_dbi2(struct dw_pcie *pci, rt_uint32_t reg, rt_size_t size, rt_uint32_t val); +rt_uint32_t dw_pcie_readl_atu(struct dw_pcie *pci, rt_uint32_t reg); +void dw_pcie_writel_atu(struct dw_pcie *pci, rt_uint32_t reg, rt_uint32_t val); +rt_bool_t dw_pcie_link_up(struct dw_pcie *pci); +void dw_pcie_upconfig_setup(struct dw_pcie *pci); +rt_err_t dw_pcie_wait_for_link(struct dw_pcie *pci); +void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, rt_uint64_t cpu_addr, rt_uint64_t pci_addr, rt_size_t size); +void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, rt_uint8_t func_no, int index, int type, rt_uint64_t cpu_addr, rt_uint64_t pci_addr, rt_size_t size); +rt_err_t dw_pcie_prog_inbound_atu(struct dw_pcie *pci, rt_uint8_t func_no, int index, int bar, rt_uint64_t cpu_addr, enum dw_pcie_aspace_type aspace_type); +void dw_pcie_disable_atu(struct dw_pcie *pci, int index, enum dw_pcie_region_type type); +void dw_pcie_setup(struct dw_pcie *pci); + +rt_inline void dw_pcie_writel_dbi(struct dw_pcie *pci, rt_uint32_t reg, rt_uint32_t val) +{ + dw_pcie_write_dbi(pci, reg, 0x4, val); +} + +rt_inline rt_uint32_t dw_pcie_readl_dbi(struct dw_pcie *pci, rt_uint32_t reg) +{ + return dw_pcie_read_dbi(pci, reg, 0x4); +} + +rt_inline void dw_pcie_writew_dbi(struct dw_pcie *pci, rt_uint32_t reg, rt_uint16_t val) +{ + dw_pcie_write_dbi(pci, reg, 0x2, val); +} + +rt_inline rt_uint16_t dw_pcie_readw_dbi(struct dw_pcie *pci, rt_uint32_t reg) +{ + return dw_pcie_read_dbi(pci, reg, 0x2); +} + +rt_inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, rt_uint32_t reg, rt_uint8_t val) +{ + dw_pcie_write_dbi(pci, reg, 0x1, val); +} + +rt_inline rt_uint8_t dw_pcie_readb_dbi(struct dw_pcie *pci, rt_uint32_t reg) +{ + return dw_pcie_read_dbi(pci, reg, 0x1); +} + +rt_inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, rt_uint32_t reg, rt_uint32_t val) +{ + dw_pcie_write_dbi2(pci, reg, 0x4, val); +} + +rt_inline void dw_pcie_dbi_ro_writable_enable(struct dw_pcie *pci, rt_bool_t enable) +{ + const rt_uint32_t reg = PCIE_MISC_CONTROL_1_OFF; + + if (enable) + { + dw_pcie_writel_dbi(pci, reg, dw_pcie_readl_dbi(pci, reg) | PCIE_DBI_RO_WR_EN); + } + else + { + dw_pcie_writel_dbi(pci, reg, dw_pcie_readl_dbi(pci, reg) & ~PCIE_DBI_RO_WR_EN); + } +} + +rt_inline rt_uint8_t dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) +{ + return dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) == 0xffffffff ? 1 : 0; +} + +rt_inline rt_uint32_t dw_pcie_readl_ob_unroll(struct dw_pcie *pci, + rt_uint32_t index, rt_uint32_t reg) +{ + return dw_pcie_readl_atu(pci, PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index) + reg); +} + +rt_inline void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, + rt_uint32_t index, rt_uint32_t reg, rt_uint32_t val) +{ + dw_pcie_writel_atu(pci, PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index) + reg, val); +} + +rt_inline rt_uint32_t dw_pcie_readl_ib_unroll(struct dw_pcie *pci, + rt_uint32_t index, rt_uint32_t reg) +{ + return dw_pcie_readl_atu(pci, PCIE_GET_ATU_INB_UNR_REG_OFFSET(index) + reg); +} + +rt_inline void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, + rt_uint32_t index, rt_uint32_t reg, rt_uint32_t val) +{ + dw_pcie_writel_atu(pci, reg + PCIE_GET_ATU_INB_UNR_REG_OFFSET(index), val); +} + +HOST_API rt_err_t dw_handle_msi_irq(struct dw_pcie_port *port) HOST_RET(-RT_ENOSYS) +HOST_API void dw_pcie_msi_init(struct dw_pcie_port *port) HOST_RET() +HOST_API void dw_pcie_free_msi(struct dw_pcie_port *port) HOST_RET() + +HOST_API void dw_pcie_setup_rc(struct dw_pcie_port *port) HOST_RET() + +HOST_API rt_err_t dw_pcie_host_init(struct dw_pcie_port *port) HOST_RET(-RT_ENOSYS) +HOST_API void dw_pcie_host_deinit(struct dw_pcie_port *port) HOST_RET() + +HOST_API void dw_pcie_host_free(struct dw_pcie_port *port) HOST_RET() + +HOST_API void *dw_pcie_own_conf_map(struct rt_pci_bus *bus, rt_uint32_t devfn, int reg) HOST_RET(RT_NULL) + +EP_API rt_err_t dw_pcie_ep_init(struct dw_pcie_ep *ep) EP_RET(-RT_ENOSYS) +EP_API rt_err_t dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) EP_RET(-RT_ENOSYS) +EP_API void dw_pcie_ep_exit(struct dw_pcie_ep *ep) EP_RET() + +EP_API rt_err_t dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, rt_uint8_t func_no) EP_RET(-RT_ENOSYS) +EP_API rt_err_t dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, rt_uint8_t func_no, unsigned irq) EP_RET(-RT_ENOSYS) +EP_API rt_err_t dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, rt_uint8_t func_no, unsigned irq) EP_RET(-RT_ENOSYS) +EP_API rt_err_t dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, rt_uint8_t func_no, unsigned irq) EP_RET(-RT_ENOSYS) + +EP_API void dw_pcie_ep_reset_bar(struct dw_pcie *pci, int bar_idx) EP_RET() + +EP_API rt_err_t dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, rt_uint8_t func_no, + int bar_idx, rt_ubase_t cpu_addr, enum dw_pcie_aspace_type aspace_type) EP_RET(-RT_ENOSYS) +EP_API rt_err_t dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, rt_uint8_t func_no, + rt_ubase_t phys_addr, rt_uint64_t pci_addr, rt_size_t size) EP_RET(-RT_ENOSYS) + +EP_API struct dw_pcie_ep_func *dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, rt_uint8_t func_no) EP_RET(RT_NULL) + +#endif /* __PCIE_DESIGNWARE_H__ */ diff --git a/rt-thread/components/drivers/pci/host/dw/pcie-dw_ep.c b/rt-thread/components/drivers/pci/host/dw/pcie-dw_ep.c new file mode 100644 index 0000000..b52f6b5 --- /dev/null +++ b/rt-thread/components/drivers/pci/host/dw/pcie-dw_ep.c @@ -0,0 +1,863 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#define DBG_TAG "pcie.dw-ep" +#define DBG_LVL DBG_INFO +#include + +#include "pcie-dw.h" + +struct dw_pcie_ep_func *dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, rt_uint8_t func_no) +{ + struct dw_pcie_ep_func *ep_func; + + rt_list_for_each_entry(ep_func, &ep->func_nodes, list) + { + if (ep_func->func_no == func_no) + { + return ep_func; + } + } + + return RT_NULL; +} + +static rt_uint8_t dw_pcie_ep_func_select(struct dw_pcie_ep *ep, rt_uint8_t func_no) +{ + rt_uint8_t func_offset = 0; + + if (ep->ops->func_select) + { + func_offset = ep->ops->func_select(ep, func_no); + } + + return func_offset; +} + +static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, rt_uint8_t func_no, + int bar_idx, int flags) +{ + rt_uint32_t reg; + rt_uint8_t func_offset = 0; + struct dw_pcie_ep *ep = &pci->endpoint; + + func_offset = dw_pcie_ep_func_select(ep, func_no); + reg = func_offset + PCIR_BAR(bar_idx); + + dw_pcie_dbi_ro_writable_enable(pci, RT_TRUE); + + dw_pcie_writel_dbi2(pci, reg, 0x0); + dw_pcie_writel_dbi(pci, reg, 0x0); + + if (flags & PCIM_BAR_MEM_TYPE_64) + { + dw_pcie_writel_dbi2(pci, reg + 4, 0x0); + dw_pcie_writel_dbi(pci, reg + 4, 0x0); + } + + dw_pcie_dbi_ro_writable_enable(pci, RT_FALSE); +} + +void dw_pcie_ep_reset_bar(struct dw_pcie *pci, int bar_idx) +{ + rt_uint8_t func_no, funcs = pci->endpoint.epc->max_functions; + + for (func_no = 0; func_no < funcs; ++func_no) + { + __dw_pcie_ep_reset_bar(pci, func_no, bar_idx, 0); + } +} + +static rt_uint8_t __dw_pcie_ep_find_next_cap(struct dw_pcie_ep *ep, rt_uint8_t func_no, + rt_uint8_t cap_ptr, rt_uint8_t cap) +{ + rt_uint16_t reg; + rt_uint8_t func_offset = 0, cap_id, next_cap_ptr; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + if (!cap_ptr) + { + return 0; + } + + func_offset = dw_pcie_ep_func_select(ep, func_no); + reg = dw_pcie_readw_dbi(pci, func_offset + cap_ptr); + cap_id = (reg & 0x00ff); + + if (cap_id > PCIY_MAX) + { + return 0; + } + + if (cap_id == cap) + { + return cap_ptr; + } + + next_cap_ptr = (reg & 0xff00) >> 8; + return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap); +} + +static rt_uint8_t dw_pcie_ep_find_capability(struct dw_pcie_ep *ep, rt_uint8_t func_no, + rt_uint8_t cap) +{ + rt_uint16_t reg; + rt_uint8_t func_offset = 0, next_cap_ptr; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + func_offset = dw_pcie_ep_func_select(ep, func_no); + reg = dw_pcie_readw_dbi(pci, func_offset + PCIR_CAP_PTR); + next_cap_ptr = reg & 0x00ff; + + return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap); +} + +rt_err_t dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, rt_uint8_t func_no, + int bar_idx, rt_ubase_t cpu_addr, enum dw_pcie_aspace_type aspace_type) +{ + rt_err_t err; + rt_uint32_t free_win; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + free_win = rt_bitmap_next_clear_bit(ep->ib_window_map, 0, ep->num_ib_windows); + if (free_win >= ep->num_ib_windows) + { + LOG_E("No free inbound window"); + return -RT_EEMPTY; + } + + err = dw_pcie_prog_inbound_atu(pci, func_no, free_win, bar_idx, cpu_addr, aspace_type); + if (err) + { + LOG_E("Failed to program IB window error = %s", rt_strerror(err)); + return err; + } + + ep->bar_to_atu[bar_idx] = free_win; + rt_bitmap_set_bit(ep->ib_window_map, free_win); + + return RT_EOK; +} + +rt_err_t dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, rt_uint8_t func_no, + rt_ubase_t phys_addr, rt_uint64_t pci_addr, rt_size_t size) +{ + rt_uint32_t free_win; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + free_win = rt_bitmap_next_clear_bit(ep->ob_window_map, 0, ep->num_ob_windows); + if (free_win >= ep->num_ob_windows) + { + LOG_E("No free outbound window"); + return -RT_EEMPTY; + } + + dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM, + phys_addr, pci_addr, size); + + ep->outbound_addr[free_win] = phys_addr; + rt_bitmap_set_bit(ep->ob_window_map, free_win); + + return RT_EOK; +} + +static rt_err_t dw_pcie_ep_write_header(struct rt_pci_ep *epc, rt_uint8_t func_no, + struct rt_pci_ep_header *hdr) +{ + rt_uint8_t func_offset = 0; + struct dw_pcie_ep *ep = epc->priv; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + func_offset = dw_pcie_ep_func_select(ep, func_no); + + dw_pcie_dbi_ro_writable_enable(pci, RT_TRUE); + + dw_pcie_writew_dbi(pci, func_offset + PCIR_VENDOR, hdr->vendor); + dw_pcie_writew_dbi(pci, func_offset + PCIR_DEVICE, hdr->device); + dw_pcie_writeb_dbi(pci, func_offset + PCIR_REVID, hdr->revision); + dw_pcie_writeb_dbi(pci, func_offset + PCIR_PROGIF, hdr->progif); + dw_pcie_writew_dbi(pci, func_offset + PCIR_SUBCLASS, hdr->subclass | hdr->class_code << 8); + dw_pcie_writeb_dbi(pci, func_offset + PCIR_CACHELNSZ, hdr->cache_line_size); + dw_pcie_writew_dbi(pci, func_offset + PCIR_SUBVEND_0, hdr->subsystem_vendor); + dw_pcie_writew_dbi(pci, func_offset + PCIR_SUBDEV_0, hdr->subsystem_device); + dw_pcie_writeb_dbi(pci, func_offset + PCIR_INTPIN, hdr->intx); + + dw_pcie_dbi_ro_writable_enable(pci, RT_FALSE); + + return 0; +} + +static rt_err_t dw_pcie_ep_clear_bar(struct rt_pci_ep *epc, rt_uint8_t func_no, + struct rt_pci_ep_bar *bar, int bar_idx) +{ + rt_uint32_t atu_index; + struct dw_pcie_ep *ep = epc->priv; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + atu_index = ep->bar_to_atu[bar_idx]; + __dw_pcie_ep_reset_bar(pci, func_no, bar_idx, ep->epc_bar[bar_idx]->bus.flags); + + dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND); + rt_bitmap_clear_bit(ep->ib_window_map, atu_index); + ep->epc_bar[bar_idx] = RT_NULL; + + return RT_EOK; +} + +static rt_err_t dw_pcie_ep_set_bar(struct rt_pci_ep *epc, rt_uint8_t func_no, + struct rt_pci_ep_bar *bar, int bar_idx) +{ + rt_err_t err; + rt_uint32_t reg; + rt_uint8_t func_offset = 0; + rt_size_t size = bar->bus.size; + rt_ubase_t flags = bar->bus.flags; + enum dw_pcie_aspace_type aspace_type; + struct dw_pcie_ep *ep = epc->priv; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + func_offset = dw_pcie_ep_func_select(ep, func_no); + reg = PCIR_BAR(bar_idx) + func_offset; + + if (!(flags & PCIM_BAR_SPACE)) + { + aspace_type = DW_PCIE_ASPACE_MEM; + } + else + { + aspace_type = DW_PCIE_ASPACE_IO; + } + + err = dw_pcie_ep_inbound_atu(ep, func_no, bar_idx, bar->bus.base, aspace_type); + if (err) + { + return err; + } + + dw_pcie_dbi_ro_writable_enable(pci, RT_TRUE); + + dw_pcie_writel_dbi2(pci, reg, rt_lower_32_bits(size - 1)); + dw_pcie_writel_dbi(pci, reg, flags); + + if (flags & PCIM_BAR_MEM_TYPE_64) + { + dw_pcie_writel_dbi2(pci, reg + 4, rt_upper_32_bits(size - 1)); + dw_pcie_writel_dbi(pci, reg + 4, 0); + } + + ep->epc_bar[bar_idx] = bar; + dw_pcie_dbi_ro_writable_enable(pci, RT_FALSE); + + return 0; +} + +static rt_err_t dw_pcie_find_index(struct dw_pcie_ep *ep, + rt_ubase_t addr, rt_uint32_t *atu_index) +{ + for (rt_uint32_t index = 0; index < ep->num_ob_windows; ++index) + { + if (ep->outbound_addr[index] != addr) + { + continue; + } + + *atu_index = index; + + return RT_EOK; + } + + return -RT_EINVAL; +} + +static rt_err_t dw_pcie_ep_unmap_addr(struct rt_pci_ep *epc, rt_uint8_t func_no, + rt_ubase_t addr) +{ + rt_err_t err; + rt_uint32_t atu_index; + struct dw_pcie_ep *ep = epc->priv; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + if ((err = dw_pcie_find_index(ep, addr, &atu_index))) + { + return err; + } + + dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND); + rt_bitmap_clear_bit(ep->ob_window_map, atu_index); + + return RT_EOK; +} + +static rt_err_t dw_pcie_ep_map_addr(struct rt_pci_ep *epc, rt_uint8_t func_no, + rt_ubase_t addr, rt_uint64_t pci_addr, rt_size_t size) +{ + rt_err_t err; + struct dw_pcie_ep *ep = epc->priv; + + err = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size); + if (err) + { + LOG_E("Failed to enable address error = %s", rt_strerror(err)); + return err; + } + + return RT_EOK; +} + +static rt_err_t dw_pcie_ep_set_msi(struct rt_pci_ep *epc, rt_uint8_t func_no, + unsigned irq_nr) +{ + rt_uint32_t val, reg; + rt_uint8_t func_offset = 0; + struct dw_pcie_ep_func *ep_func; + struct dw_pcie_ep *ep = epc->priv; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); + if (!ep_func || !ep_func->msi_cap) + { + return -RT_EINVAL; + } + + func_offset = dw_pcie_ep_func_select(ep, func_no); + reg = ep_func->msi_cap + func_offset + PCIR_MSI_CTRL; + + val = dw_pcie_readw_dbi(pci, reg); + val &= ~PCIM_MSICTRL_MMC_MASK; + val |= (irq_nr << 1) & PCIM_MSICTRL_MMC_MASK; + + dw_pcie_dbi_ro_writable_enable(pci, RT_TRUE); + dw_pcie_writew_dbi(pci, reg, val); + dw_pcie_dbi_ro_writable_enable(pci, RT_FALSE); + + return RT_EOK; +} + +static rt_err_t dw_pcie_ep_get_msi(struct rt_pci_ep *epc, rt_uint8_t func_no, + unsigned *out_irq_nr) +{ + rt_uint32_t val, reg; + rt_uint8_t func_offset = 0; + struct dw_pcie_ep *ep = epc->priv; + struct dw_pcie_ep_func *ep_func; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); + if (!ep_func || !ep_func->msi_cap) + { + return -RT_EINVAL; + } + + func_offset = dw_pcie_ep_func_select(ep, func_no); + reg = ep_func->msi_cap + func_offset + PCIR_MSI_CTRL; + + val = dw_pcie_readw_dbi(pci, reg); + if (!(val & PCIM_MSICTRL_MSI_ENABLE)) + { + return -RT_EINVAL; + } + + *out_irq_nr = (val & PCIM_MSICTRL_MME_MASK) >> 4; + + return RT_EOK; +} + +static rt_err_t dw_pcie_ep_set_msix(struct rt_pci_ep *epc, rt_uint8_t func_no, + unsigned irq_nr, int bar_idx, rt_off_t offset) +{ + rt_uint32_t val, reg; + rt_uint8_t func_offset = 0; + struct dw_pcie_ep_func *ep_func; + struct dw_pcie_ep *ep = epc->priv; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); + if (!ep_func || !ep_func->msix_cap) + { + return -RT_EINVAL; + } + + dw_pcie_dbi_ro_writable_enable(pci, RT_TRUE); + + func_offset = dw_pcie_ep_func_select(ep, func_no); + reg = ep_func->msix_cap + func_offset + PCIR_MSIX_CTRL; + + val = dw_pcie_readw_dbi(pci, reg); + val &= ~PCIM_MSIXCTRL_TABLE_SIZE; + val |= irq_nr; + dw_pcie_writew_dbi(pci, reg, val); + + reg = ep_func->msix_cap + func_offset + PCIR_MSIX_TABLE; + val = offset | bar_idx; + dw_pcie_writel_dbi(pci, reg, val); + + reg = ep_func->msix_cap + func_offset + PCIR_MSIX_PBA; + val = (offset + (irq_nr * PCIM_MSIX_ENTRY_SIZE)) | bar_idx; + dw_pcie_writel_dbi(pci, reg, val); + + dw_pcie_dbi_ro_writable_enable(pci, RT_FALSE); + + return RT_EOK; +} + +static rt_err_t dw_pcie_ep_get_msix(struct rt_pci_ep *epc, rt_uint8_t func_no, + unsigned *out_irq_nr) +{ + rt_uint32_t val, reg; + rt_uint8_t func_offset = 0; + struct dw_pcie_ep_func *ep_func; + struct dw_pcie_ep *ep = epc->priv; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); + if (!ep_func || !ep_func->msix_cap) + { + return -RT_EINVAL; + } + + func_offset = dw_pcie_ep_func_select(ep, func_no); + reg = ep_func->msix_cap + func_offset + PCIR_MSIX_CTRL; + + val = dw_pcie_readw_dbi(pci, reg); + if (!(val & PCIM_MSIXCTRL_MSIX_ENABLE)) + { + return -RT_EINVAL; + } + + *out_irq_nr = val & PCIM_MSIXCTRL_TABLE_SIZE; + + return RT_EOK; +} + +static rt_err_t dw_pcie_ep_raise_irq(struct rt_pci_ep *epc, rt_uint8_t func_no, + enum rt_pci_ep_irq type, unsigned irq) +{ + struct dw_pcie_ep *ep = epc->priv; + + if (!ep->ops->raise_irq) + { + return -RT_ENOSYS; + } + + return ep->ops->raise_irq(ep, func_no, type, irq); +} + +static rt_err_t dw_pcie_ep_stop(struct rt_pci_ep *epc) +{ + struct dw_pcie_ep *ep = epc->priv; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + if (pci->ops->stop_link) + { + pci->ops->stop_link(pci); + } + + return RT_EOK; +} + +static rt_err_t dw_pcie_ep_start(struct rt_pci_ep *epc) +{ + struct dw_pcie_ep *ep = epc->priv; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + if (pci->ops->start_link) + { + return pci->ops->start_link(pci); + } + + return RT_EOK; +} + +static const struct rt_pci_ep_ops dw_pcie_ep_ops = +{ + .write_header = dw_pcie_ep_write_header, + .set_bar = dw_pcie_ep_set_bar, + .clear_bar = dw_pcie_ep_clear_bar, + .map_addr = dw_pcie_ep_map_addr, + .unmap_addr = dw_pcie_ep_unmap_addr, + .set_msi = dw_pcie_ep_set_msi, + .get_msi = dw_pcie_ep_get_msi, + .set_msix = dw_pcie_ep_set_msix, + .get_msix = dw_pcie_ep_get_msix, + .raise_irq = dw_pcie_ep_raise_irq, + .start = dw_pcie_ep_start, + .stop = dw_pcie_ep_stop, +}; + +rt_err_t dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, rt_uint8_t func_no) +{ + LOG_E("EP cannot trigger legacy IRQs"); + + return -RT_EINVAL; +} + +rt_err_t dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, rt_uint8_t func_no, + unsigned irq) +{ + rt_err_t err; + rt_off_t aligned_offset; + rt_uint8_t func_offset = 0; + rt_uint64_t msg_addr; + rt_uint16_t msg_ctrl, msg_data; + rt_uint32_t msg_addr_lower, msg_addr_upper, reg; + struct rt_pci_ep *epc = ep->epc; + struct dw_pcie_ep_func *ep_func; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); + if (!ep_func || !ep_func->msi_cap) + { + return -RT_EINVAL; + } + + func_offset = dw_pcie_ep_func_select(ep, func_no); + + /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */ + reg = ep_func->msi_cap + func_offset + PCIR_MSI_CTRL; + msg_ctrl = dw_pcie_readw_dbi(pci, reg); + reg = ep_func->msi_cap + func_offset + PCIR_MSI_ADDR; + msg_addr_lower = dw_pcie_readl_dbi(pci, reg); + + if (!!(msg_ctrl & PCIM_MSICTRL_64BIT)) + { + reg = ep_func->msi_cap + func_offset + PCIR_MSI_ADDR_HIGH; + msg_addr_upper = dw_pcie_readl_dbi(pci, reg); + reg = ep_func->msi_cap + func_offset + PCIR_MSI_DATA_64BIT; + msg_data = dw_pcie_readw_dbi(pci, reg); + } + else + { + msg_addr_upper = 0; + reg = ep_func->msi_cap + func_offset + PCIR_MSI_DATA; + msg_data = dw_pcie_readw_dbi(pci, reg); + } + + aligned_offset = msg_addr_lower & (ep->page_size - 1); + msg_addr = ((rt_uint64_t)msg_addr_upper << 32) | (msg_addr_lower & ~aligned_offset); + + if ((err = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phy, msg_addr, ep->page_size))) + { + return err; + } + + HWREG32(ep->msi_mem + aligned_offset) = msg_data | (irq - 1); + dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phy); + + return RT_EOK; +} + +rt_err_t dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, rt_uint8_t func_no, + unsigned irq) +{ + rt_uint32_t msg_data; + struct dw_pcie_ep_func *ep_func; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); + if (!ep_func || !ep_func->msix_cap) + { + return -RT_EINVAL; + } + + msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) | (irq - 1); + dw_pcie_writel_dbi(pci, PCIE_MSIX_DOORBELL, msg_data); + + return RT_EOK; +} + +rt_err_t dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, rt_uint8_t func_no, + unsigned irq) +{ + rt_err_t err; + int bar_idx; + rt_uint64_t msg_addr; + rt_uint32_t tbl_offset; + rt_off_t aligned_offset; + rt_uint8_t func_offset = 0; + rt_uint32_t reg, msg_data, vec_ctrl; + struct rt_pci_ep *epc = ep->epc; + struct rt_pci_ep_msix_tbl *msix_tbl; + struct dw_pcie_ep_func *ep_func; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); + if (!ep_func || !ep_func->msix_cap) + { + return -RT_EINVAL; + } + + func_offset = dw_pcie_ep_func_select(ep, func_no); + reg = ep_func->msix_cap + func_offset + PCIR_MSIX_TABLE; + + tbl_offset = dw_pcie_readl_dbi(pci, reg); + bar_idx = (tbl_offset & PCIM_MSIX_BIR_MASK); + tbl_offset &= PCIM_MSIX_TABLE_OFFSET; + + msix_tbl = (void *)ep->epc_bar[bar_idx]->cpu_addr + tbl_offset; + msg_addr = msix_tbl[(irq - 1)].msg_addr; + msg_data = msix_tbl[(irq - 1)].msg_data; + vec_ctrl = msix_tbl[(irq - 1)].vector_ctrl; + + if (vec_ctrl & PCIM_MSIX_ENTRYVECTOR_CTRL_MASK) + { + return -RT_EINVAL; + } + + aligned_offset = msg_addr & (ep->page_size - 1); + + if ((err = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phy, msg_addr, ep->page_size))) + { + return err; + } + + HWREG32(ep->msi_mem + aligned_offset) = msg_data; + dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phy); + + return RT_EOK; +} + +void dw_pcie_ep_exit(struct dw_pcie_ep *ep) +{ + struct rt_pci_ep *epc = ep->epc; + + if (ep->msi_mem) + { + rt_pci_ep_mem_free(epc, ep->msi_mem, ep->msi_mem_phy, ep->page_size); + } + + if (!rt_list_isempty(&ep->func_nodes)) + { + struct dw_pcie_ep_func *ep_func, *ep_func_next; + + rt_list_for_each_entry_safe(ep_func, ep_func_next, &ep->func_nodes, list) + { + rt_list_remove(&ep_func->list); + rt_free(ep_func); + } + } + + if (ep->ib_window_map) + { + rt_free(ep->ib_window_map); + } + + if (ep->ob_window_map) + { + rt_free(ep->ob_window_map); + } + + if (ep->outbound_addr) + { + rt_free(ep->outbound_addr); + } + + if (epc) + { + rt_free(epc); + } +} + +static rt_uint32_t dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) +{ + rt_uint32_t header; + int pos = (PCI_REGMAX + 1); + + while (pos) + { + header = dw_pcie_readl_dbi(pci, pos); + + if (PCI_EXTCAP_ID(header) == cap) + { + return pos; + } + + if (!(pos = PCI_EXTCAP_NEXTPTR(header))) + { + break; + } + } + + return 0; +} + +rt_err_t dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) +{ + rt_off_t offset; + rt_size_t bar_nr; + rt_uint32_t reg; + rt_uint8_t hdr_type; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + hdr_type = dw_pcie_readb_dbi(pci, PCIR_HDRTYPE) & PCIM_HDRTYPE; + if (hdr_type != PCIM_HDRTYPE_NORMAL) + { + LOG_E("PCIe controller is not set to EP mode hdr_type = %x", hdr_type); + return -RT_EIO; + } + + offset = dw_pcie_ep_find_ext_capability(pci, PCIZ_RESIZE_BAR); + + dw_pcie_dbi_ro_writable_enable(pci, RT_TRUE); + + if (offset) + { + reg = dw_pcie_readl_dbi(pci, offset + PCIM_REBAR_CTRL); + bar_nr = (reg & PCIM_REBAR_CTRL_NBAR_MASK) >> PCIM_REBAR_CTRL_NBAR_SHIFT; + + for (int i = 0; i < bar_nr; ++i, offset += PCIM_REBAR_CTRL) + { + dw_pcie_writel_dbi(pci, offset + PCIM_REBAR_CAP, 0x0); + } + } + + dw_pcie_setup(pci); + dw_pcie_dbi_ro_writable_enable(pci, RT_FALSE); + + return RT_EOK; +} + +rt_err_t dw_pcie_ep_init(struct dw_pcie_ep *ep) +{ + rt_err_t err; + struct rt_pci_ep *epc = RT_NULL; + struct dw_pcie_ep_func *ep_func; + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + struct rt_device *dev = pci->dev; + + rt_list_init(&ep->func_nodes); + + if (!pci->dbi_base || !pci->dbi_base2) + { + LOG_E("dbi_base/dbi_base2 is not populated"); + return -RT_EINVAL; + } + + if ((err = rt_dm_dev_prop_read_u32(dev, "num-ib-windows", &ep->num_ib_windows))) + { + LOG_E("Unable to read 'num-ib-windows' property"); + return err; + } + + if (ep->num_ib_windows > MAX_IATU_IN) + { + LOG_E("Invalid 'num-ib-windows'"); + return -RT_EINVAL; + } + + if ((err = rt_dm_dev_prop_read_u32(dev, "num-ob-windows", &ep->num_ob_windows))) + { + LOG_E("Unable to read 'num-ob-windows' property"); + return err; + } + + if (ep->num_ob_windows > MAX_IATU_OUT) + { + LOG_E("Invalid 'num-ob-windows'"); + return -RT_EINVAL; + } + + ep->ib_window_map = rt_calloc(RT_BITMAP_LEN(ep->num_ib_windows), sizeof(rt_bitmap_t)); + if (!ep->ib_window_map) + { + return -RT_ENOMEM; + } + + ep->ob_window_map = rt_calloc(RT_BITMAP_LEN(ep->num_ob_windows), sizeof(rt_bitmap_t)); + if (!ep->ob_window_map) + { + err = -RT_ENOMEM; + goto _fail; + } + + ep->outbound_addr = rt_calloc(ep->num_ob_windows, sizeof(rt_ubase_t)); + if (!ep->outbound_addr) + { + err = -RT_ENOMEM; + goto _fail; + } + + if (pci->link_gen < 1) + { + pci->link_gen = -1; + rt_dm_dev_prop_read_u32(dev, "max-link-speed", &pci->link_gen); + } + + epc = rt_calloc(1, sizeof(*epc)); + if (!epc) + { + err = -RT_ENOMEM; + goto _fail; + } + + epc->name = rt_dm_dev_get_name(dev); + epc->rc_dev = dev; + epc->ops = &dw_pcie_ep_ops; + epc->priv = ep; + + if ((err = rt_pci_ep_register(epc))) + { + goto _fail; + } + ep->epc = epc; + + if (rt_dm_dev_prop_read_u8(dev, "max-functions", &epc->max_functions)) + { + epc->max_functions = 1; + } + + for (rt_uint8_t func_no = 0; func_no < epc->max_functions; ++func_no) + { + ep_func = rt_calloc(1, sizeof(*ep_func)); + + if (!ep_func) + { + err = -RT_ENOMEM; + goto _fail; + } + + ep_func->func_no = func_no; + ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no, PCIY_MSI); + ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no, PCIY_MSIX); + + rt_list_init(&ep_func->list); + rt_list_insert_after(&ep->func_nodes, &ep_func->list); + } + + if (ep->ops->ep_init) + { + ep->ops->ep_init(ep); + } + + if ((err = rt_pci_ep_mem_init(epc, ep->aspace, ep->aspace_size, ep->page_size))) + { + goto _fail; + } + + ep->msi_mem = rt_pci_ep_mem_alloc(epc, &ep->msi_mem_phy, ep->page_size); + + if (!ep->msi_mem) + { + LOG_E("Failed to reserve memory for MSI/MSI-X"); + err = -RT_ENOMEM; + goto _fail; + } + + if ((err = dw_pcie_ep_init_complete(ep))) + { + goto _fail; + } + + return RT_EOK; + +_fail: + dw_pcie_ep_exit(ep); + + return err; +} diff --git a/rt-thread/components/drivers/pci/host/dw/pcie-dw_host.c b/rt-thread/components/drivers/pci/host/dw/pcie-dw_host.c new file mode 100644 index 0000000..05a3dc7 --- /dev/null +++ b/rt-thread/components/drivers/pci/host/dw/pcie-dw_host.c @@ -0,0 +1,644 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#define DBG_TAG "pcie.dw-host" +#define DBG_LVL DBG_INFO +#include + +#include "pcie-dw.h" + +static void dw_pcie_irq_ack(struct rt_pic_irq *pirq) +{ + int hwirq = pirq->hwirq; + rt_uint32_t res, bit, ctrl; + struct dw_pcie_port *port = pirq->pic->priv_data; + struct dw_pcie *pci = to_dw_pcie_from_port(port); + + ctrl = hwirq / MAX_MSI_IRQS_PER_CTRL; + res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; + bit = hwirq % MAX_MSI_IRQS_PER_CTRL; + + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, RT_BIT(bit)); +} + +static void dw_pcie_irq_mask(struct rt_pic_irq *pirq) +{ + rt_ubase_t level; + int hwirq = pirq->hwirq; + rt_uint32_t res, bit, ctrl; + struct dw_pcie_port *port = pirq->pic->priv_data; + struct dw_pcie *pci = to_dw_pcie_from_port(port); + + rt_pci_msi_mask_irq(pirq); + + level = rt_spin_lock_irqsave(&port->lock); + + ctrl = hwirq / MAX_MSI_IRQS_PER_CTRL; + res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; + bit = hwirq % MAX_MSI_IRQS_PER_CTRL; + + port->irq_mask[ctrl] |= RT_BIT(bit); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, port->irq_mask[ctrl]); + + rt_spin_unlock_irqrestore(&port->lock, level); +} + +static void dw_pcie_irq_unmask(struct rt_pic_irq *pirq) +{ + rt_ubase_t level; + int hwirq = pirq->hwirq; + rt_uint32_t res, bit, ctrl; + struct dw_pcie_port *port = pirq->pic->priv_data; + struct dw_pcie *pci = to_dw_pcie_from_port(port); + + rt_pci_msi_unmask_irq(pirq); + + level = rt_spin_lock_irqsave(&port->lock); + + ctrl = hwirq / MAX_MSI_IRQS_PER_CTRL; + res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; + bit = hwirq % MAX_MSI_IRQS_PER_CTRL; + + port->irq_mask[ctrl] &= ~RT_BIT(bit); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, port->irq_mask[ctrl]); + + rt_spin_unlock_irqrestore(&port->lock, level); +} + +static void dw_pcie_compose_msi_msg(struct rt_pic_irq *pirq, struct rt_pci_msi_msg *msg) +{ + rt_uint64_t msi_target; + struct dw_pcie_port *port = pirq->pic->priv_data; + + msi_target = (rt_uint64_t)port->msi_data_phy; + + msg->address_lo = rt_lower_32_bits(msi_target); + msg->address_hi = rt_upper_32_bits(msi_target); + + msg->data = pirq->hwirq; +} + +static int dw_pcie_irq_alloc_msi(struct rt_pic *pic, struct rt_pci_msi_desc *msi_desc) +{ + rt_ubase_t level; + int irq, hwirq; + struct rt_pic_irq *pirq; + struct dw_pcie_port *port = pic->priv_data; + + level = rt_spin_lock_irqsave(&port->lock); + hwirq = rt_bitmap_next_clear_bit(port->msi_map, 0, port->irq_count); + + if (hwirq >= port->irq_count) + { + irq = -RT_EEMPTY; + goto _out_lock; + } + + pirq = rt_pic_find_irq(pic, hwirq); + + irq = rt_pic_config_irq(pic, hwirq, hwirq); + pirq->mode = RT_IRQ_MODE_EDGE_RISING; + + rt_bitmap_set_bit(port->msi_map, hwirq); + +_out_lock: + rt_spin_unlock_irqrestore(&port->lock, level); + + return irq; +} + +static void dw_pcie_irq_free_msi(struct rt_pic *pic, int irq) +{ + rt_ubase_t level; + struct rt_pic_irq *pirq; + struct dw_pcie_port *port = pic->priv_data; + + pirq = rt_pic_find_pirq(pic, irq); + + if (!pirq) + { + return; + } + + level = rt_spin_lock_irqsave(&port->lock); + rt_bitmap_clear_bit(port->msi_map, pirq->hwirq); + rt_spin_unlock_irqrestore(&port->lock, level); +} + +const static struct rt_pic_ops dw_pci_msi_ops = +{ + .name = "DWPCI-MSI", + .irq_ack = dw_pcie_irq_ack, + .irq_mask = dw_pcie_irq_mask, + .irq_unmask = dw_pcie_irq_unmask, + .irq_compose_msi_msg = dw_pcie_compose_msi_msg, + .irq_alloc_msi = dw_pcie_irq_alloc_msi, + .irq_free_msi = dw_pcie_irq_free_msi, + .flags = RT_PIC_F_IRQ_ROUTING, +}; + +/* MSI int handler */ +rt_err_t dw_handle_msi_irq(struct dw_pcie_port *port) +{ + rt_err_t err; + int i, pos; + rt_bitmap_t status; + rt_uint32_t num_ctrls; + struct rt_pic_irq *pirq; + struct dw_pcie *pci = to_dw_pcie_from_port(port); + struct rt_pic *msi_pic = port->msi_pic; + + err = -RT_EEMPTY; + num_ctrls = RT_DIV_ROUND_UP(port->irq_count, MAX_MSI_IRQS_PER_CTRL); + + for (i = 0; i < num_ctrls; ++i) + { + status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + + (i * MSI_REG_CTRL_BLOCK_SIZE)); + + if (!status) + { + continue; + } + + err = RT_EOK; + + rt_bitmap_for_each_set_bit(&status, pos, MAX_MSI_IRQS_PER_CTRL) + { + pirq = rt_pic_find_irq(msi_pic, pos + i * MAX_MSI_IRQS_PER_CTRL); + + dw_pcie_irq_ack(pirq); + + rt_pic_handle_isr(pirq); + } + } + + return err; +} + +static void dw_pcie_msi_isr(int irqno, void *param) +{ + struct dw_pcie_port *port = param; + + dw_handle_msi_irq(port); +} + +void dw_pcie_free_msi(struct dw_pcie_port *port) +{ + if (port->msi_irq >= 0) + { + rt_hw_interrupt_mask(port->msi_irq); + rt_pic_detach_irq(port->msi_irq, port); + } + + if (port->msi_data) + { + struct dw_pcie *pci = to_dw_pcie_from_port(port); + + rt_dma_free_coherent(pci->dev, sizeof(rt_uint64_t), port->msi_data, + port->msi_data_phy); + } +} + +void dw_pcie_msi_init(struct dw_pcie_port *port) +{ +#ifdef RT_PCI_MSI + struct dw_pcie *pci = to_dw_pcie_from_port(port); + rt_uint64_t msi_target = (rt_uint64_t)port->msi_data_phy; + + /* Program the msi_data_phy */ + dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, rt_lower_32_bits(msi_target)); + dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, rt_upper_32_bits(msi_target)); +#endif +} + +static const struct rt_pci_ops dw_child_pcie_ops; +static const struct rt_pci_ops dw_pcie_ops; + +rt_err_t dw_pcie_host_init(struct dw_pcie_port *port) +{ + rt_err_t err; + struct dw_pcie *pci = to_dw_pcie_from_port(port); + struct rt_device *dev = pci->dev; + struct rt_pci_host_bridge *bridge; + + rt_spin_lock_init(&port->lock); + + rt_dm_dev_get_address_by_name(dev, "config", &port->cfg0_addr, &port->cfg0_size); + + if (port->cfg0_addr) + { + port->cfg0_base = rt_ioremap((void *)port->cfg0_addr, port->cfg0_size); + + if (!port->cfg0_base) + { + return -RT_EIO; + } + } + else if (!port->cfg0_base) + { + LOG_E("Missing 'config' reg space"); + } + + if (!(bridge = rt_pci_host_bridge_alloc(0))) + { + return -RT_ENOMEM; + } + + bridge->parent.ofw_node = dev->ofw_node; + + if ((err = rt_pci_host_bridge_init(bridge))) + { + goto _err_free_bridge; + } + + port->bridge = bridge; + + for (int i = 0; i < bridge->bus_regions_nr; ++i) + { + struct rt_pci_bus_region *region = &bridge->bus_regions[i]; + + switch (region->flags) + { + case PCI_BUS_REGION_F_IO: + port->io_addr = region->cpu_addr; + port->io_bus_addr = region->phy_addr; + port->io_size = region->size; + break; + + case PCI_BUS_REGION_F_NONE: + port->cfg0_size = region->size; + port->cfg0_addr = region->cpu_addr; + + if (!pci->dbi_base) + { + pci->dbi_base = rt_ioremap((void *)port->cfg0_addr, port->cfg0_size); + + if (!pci->dbi_base) + { + LOG_E("Error with ioremap"); + return -RT_ENOMEM; + } + } + break; + + default: + break; + } + } + + if (!port->cfg0_base && port->cfg0_addr) + { + port->cfg0_base = rt_ioremap((void *)port->cfg0_addr, port->cfg0_size); + + if (!port->cfg0_base) + { + return -RT_ENOMEM; + } + } + + if (rt_dm_dev_prop_read_u32(dev, "num-viewport", &pci->num_viewport)) + { + pci->num_viewport = 2; + } + + if (pci->link_gen < 1) + { + pci->link_gen = -1; + rt_dm_dev_prop_read_u32(dev, "max-link-speed", &pci->link_gen); + } + + /* + * If a specific SoC driver needs to change the default number of vectors, + * it needs to implement the set_irq_count callback. + */ + if (!port->ops->set_irq_count) + { + port->irq_count = MSI_DEF_NUM_VECTORS; + } + else + { + port->ops->set_irq_count(port); + + if (port->irq_count > MAX_MSI_IRQS || port->irq_count == 0) + { + LOG_E("Invalid count of irq = %d", port->irq_count); + + return -RT_EINVAL; + } + } + + if (!port->ops->msi_host_init) + { + port->msi_pic = rt_calloc(1, sizeof(*port->msi_pic)); + + if (!port->msi_pic) + { + return -RT_ENOMEM; + } + + port->msi_pic->priv_data = port; + port->msi_pic->ops = &dw_pci_msi_ops; + rt_pic_linear_irq(port->msi_pic, port->irq_count); + rt_pic_user_extends(port->msi_pic); + + if (port->msi_irq) + { + rt_hw_interrupt_install(port->msi_irq, dw_pcie_msi_isr, port, "dwc-pci-msi"); + rt_hw_interrupt_umask(port->msi_irq); + } + + port->msi_data = rt_dma_alloc_coherent(pci->dev, sizeof(rt_uint64_t), + &port->msi_data_phy); + + if (!port->msi_data) + { + err = -RT_ENOMEM; + goto _err_free_msi; + } + } + else + { + if ((err = port->ops->msi_host_init(port))) + { + return err; + } + } + + /* Set default bus ops */ + bridge->ops = &dw_pcie_ops; + bridge->child_ops = &dw_child_pcie_ops; + + if (port->ops->host_init && (err = port->ops->host_init(port))) + { + goto _err_free_msi; + } + + bridge->sysdata = port; + + if ((err = rt_pci_host_bridge_probe(bridge))) + { + goto _err_free_msi; + } + + return RT_EOK; + +_err_free_msi: + if (!port->ops->msi_host_init) + { + dw_pcie_free_msi(port); + + rt_pic_cancel_irq(port->msi_pic); + rt_free(port->msi_pic); + port->msi_pic = RT_NULL; + } + +_err_free_bridge: + rt_pci_host_bridge_free(bridge); + port->bridge = RT_NULL; + + return err; +} + +void dw_pcie_host_deinit(struct dw_pcie_port *port) +{ + if (!port->ops->msi_host_init) + { + dw_pcie_free_msi(port); + } +} + +void dw_pcie_host_free(struct dw_pcie_port *port) +{ + if (!port->ops->msi_host_init) + { + dw_pcie_free_msi(port); + + rt_pic_cancel_irq(port->msi_pic); + rt_free(port->msi_pic); + } + + if (port->bridge) + { + rt_pci_host_bridge_free(port->bridge); + } +} + +static void *dw_pcie_other_conf_map(struct rt_pci_bus *bus, rt_uint32_t devfn, int reg) +{ + int type; + rt_uint32_t busdev; + struct dw_pcie_port *port = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_port(port); + + /* + * Checking whether the link is up here is a last line of defense + * against platforms that forward errors on the system bus as + * SError upon PCI configuration transactions issued when the link is down. + * This check is racy by definition and does not stop the system from + * triggering an SError if the link goes down after this check is performed. + */ + if (!dw_pcie_link_up(pci)) + { + return RT_NULL; + } + + busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(RT_PCI_SLOT(devfn)) | + PCIE_ATU_FUNC(RT_PCI_FUNC(devfn)); + + if (rt_pci_is_root_bus(bus->parent)) + { + type = PCIE_ATU_TYPE_CFG0; + } + else + { + type = PCIE_ATU_TYPE_CFG1; + } + + dw_pcie_prog_outbound_atu(pci, 0, type, port->cfg0_addr, busdev, port->cfg0_size); + + return port->cfg0_base + reg; +} + +static rt_err_t dw_pcie_other_read_conf(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, int width, rt_uint32_t *value) +{ + rt_err_t err; + struct dw_pcie_port *port = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_port(port); + + err = rt_pci_bus_read_config_uxx(bus, devfn, reg, width, value); + + if (!err && (pci->iatu_unroll_enabled & DWC_IATU_IOCFG_SHARED)) + { + dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, + port->io_addr, port->io_bus_addr, port->io_size); + } + + return err; +} + +static rt_err_t dw_pcie_other_write_conf(struct rt_pci_bus *bus, + rt_uint32_t devfn, int reg, int width, rt_uint32_t value) +{ + rt_err_t err; + struct dw_pcie_port *port = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_port(port); + + err = rt_pci_bus_write_config_uxx(bus, devfn, reg, width, value); + + if (!err && (pci->iatu_unroll_enabled & DWC_IATU_IOCFG_SHARED)) + { + dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, + port->io_addr, port->io_bus_addr, port->io_size); + } + + return err; +} + +static const struct rt_pci_ops dw_child_pcie_ops = +{ + .map = dw_pcie_other_conf_map, + .read = dw_pcie_other_read_conf, + .write = dw_pcie_other_write_conf, +}; + +void *dw_pcie_own_conf_map(struct rt_pci_bus *bus, rt_uint32_t devfn, int reg) +{ + struct dw_pcie_port *port = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_port(port); + + if (RT_PCI_SLOT(devfn) > 0) + { + return RT_NULL; + } + + return pci->dbi_base + reg; +} + +static const struct rt_pci_ops dw_pcie_ops = +{ + .map = dw_pcie_own_conf_map, + .read = rt_pci_bus_read_config_uxx, + .write = rt_pci_bus_write_config_uxx, +}; + +void dw_pcie_setup_rc(struct dw_pcie_port *port) +{ + rt_uint32_t val, num_ctrls; + struct dw_pcie *pci = to_dw_pcie_from_port(port); + + /* + * Enable DBI read-only registers for writing/updating configuration. + * Write permission gets disabled towards the end of this function. + */ + dw_pcie_dbi_ro_writable_enable(pci, RT_TRUE); + + dw_pcie_setup(pci); + + if (!port->ops->msi_host_init) + { + num_ctrls = RT_DIV_ROUND_UP(port->irq_count, MAX_MSI_IRQS_PER_CTRL); + + /* Initialize IRQ Status array */ + for (int ctrl = 0; ctrl < num_ctrls; ++ctrl) + { + port->irq_mask[ctrl] = ~0; + + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), port->irq_mask[ctrl]); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), ~0); + } + } + + /* Setup RC BARs */ + dw_pcie_writel_dbi(pci, PCIR_BAR(0), PCIM_BAR_MEM_TYPE_64); + dw_pcie_writel_dbi(pci, PCIR_BAR(1), PCIM_BAR_MEM_TYPE_32); + + /* Setup interrupt pins */ + val = dw_pcie_readl_dbi(pci, PCIR_INTLINE); + val &= 0xffff00ff; + val |= 0x00000100; + dw_pcie_writel_dbi(pci, PCIR_INTLINE, val); + + /* Setup bus numbers */ + val = dw_pcie_readl_dbi(pci, PCIR_PRIBUS_1); + val &= 0xff000000; + val |= 0x00ff0100; + dw_pcie_writel_dbi(pci, PCIR_PRIBUS_1, val); + + /* Setup command register */ + val = dw_pcie_readl_dbi(pci, PCIR_COMMAND); + val &= 0xffff0000; + val |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_SERRESPEN; + dw_pcie_writel_dbi(pci, PCIR_COMMAND, val); + + /* + * If the platform provides its own child bus config accesses, it means + * the platform uses its own address translation component rather than + * ATU, so we should not program the ATU here. + */ + if (pci->port.bridge->child_ops == &dw_child_pcie_ops) + { + int atu_idx = 0; + struct rt_pci_host_bridge *bridge = port->bridge; + + /* Get last memory resource entry */ + for (int i = 0; i < bridge->bus_regions_nr; ++i) + { + struct rt_pci_bus_region *region = &bridge->bus_regions[i]; + + if (region->flags != PCI_BUS_REGION_F_MEM) + { + continue; + } + + if (pci->num_viewport <= ++atu_idx) + { + break; + } + + dw_pcie_prog_outbound_atu(pci, atu_idx, + PCIE_ATU_TYPE_MEM, region->cpu_addr, + region->phy_addr, region->size); + } + + if (port->io_size) + { + if (pci->num_viewport > ++atu_idx) + { + dw_pcie_prog_outbound_atu(pci, atu_idx, + PCIE_ATU_TYPE_IO, port->io_addr, + port->io_bus_addr, port->io_size); + } + else + { + pci->iatu_unroll_enabled |= DWC_IATU_IOCFG_SHARED; + } + } + + if (pci->num_viewport <= atu_idx) + { + LOG_W("Resources exceed number of ATU entries (%d)", pci->num_viewport); + } + } + + dw_pcie_writel_dbi(pci, PCIR_BAR(0), 0); + + /* Program correct class for RC */ + dw_pcie_writew_dbi(pci, PCIR_SUBCLASS, PCIS_BRIDGE_PCI); + + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val |= PORT_LOGIC_SPEED_CHANGE; + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + + dw_pcie_dbi_ro_writable_enable(pci, RT_FALSE); +} diff --git a/rt-thread/components/drivers/pci/host/dw/pcie-dw_platfrom.c b/rt-thread/components/drivers/pci/host/dw/pcie-dw_platfrom.c new file mode 100644 index 0000000..878ac41 --- /dev/null +++ b/rt-thread/components/drivers/pci/host/dw/pcie-dw_platfrom.c @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#include +#include + +#define DBG_TAG "pcie.dw.platfrom" +#define DBG_LVL DBG_INFO +#include + +#include "pcie-dw.h" + +struct dw_dw_platform_pcie_soc_data +{ + enum dw_pcie_device_mode mode; +}; + +struct dw_platform_pcie +{ + struct dw_pcie *pci; + struct rt_syscon *regmap; + const struct dw_dw_platform_pcie_soc_data *soc_data; +}; + +static rt_err_t dw_platform_pcie_host_init(struct dw_pcie_port *port) +{ + struct dw_pcie *pci = to_dw_pcie_from_port(port); + + dw_pcie_setup_rc(port); + dw_pcie_wait_for_link(pci); + dw_pcie_msi_init(port); + + return RT_EOK; +} + +static void dw_platform_set_irq_count(struct dw_pcie_port *pp) +{ + pp->irq_count = MAX_MSI_IRQS; +} + +static const struct dw_pcie_host_ops dw_platform_pcie_host_ops = +{ + .host_init = dw_platform_pcie_host_init, + .set_irq_count = dw_platform_set_irq_count, +}; + +static rt_err_t dw_platform_pcie_establish_link(struct dw_pcie *pci) +{ + return RT_EOK; +} + +static const struct dw_pcie_ops dw_platform_pcie_ops = +{ + .start_link = dw_platform_pcie_establish_link, +}; + +static rt_err_t dw_platform_pcie_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_endpoint(ep); + + for (int bar = 0; bar < PCI_STD_NUM_BARS; ++bar) + { + dw_pcie_ep_reset_bar(pci, bar); + } + + return RT_EOK; +} + +static rt_err_t dw_platform_pcie_ep_raise_irq(struct dw_pcie_ep *ep, + rt_uint8_t func_no, enum rt_pci_ep_irq type, unsigned irq) +{ + switch (type) + { + case RT_PCI_EP_IRQ_LEGACY: + return dw_pcie_ep_raise_legacy_irq(ep, func_no); + + case RT_PCI_EP_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, irq); + + case RT_PCI_EP_IRQ_MSIX: + return dw_pcie_ep_raise_msix_irq(ep, func_no, irq); + + default: + LOG_E("Unknown IRQ type = %d", type); + } + + return RT_EOK; +} + +static const struct dw_pcie_ep_ops dw_platform_pcie_ep_ops = +{ + .ep_init = dw_platform_pcie_ep_init, + .raise_irq = dw_platform_pcie_ep_raise_irq, +}; + +static rt_err_t dw_platform_add_pcie_port(struct dw_platform_pcie *plat_pcie, + struct rt_device *dev) +{ + rt_err_t err; + struct dw_pcie *pci = plat_pcie->pci; + struct dw_pcie_port *port = &pci->port; + + port->sys_irq = rt_dm_dev_get_irq(dev, 1); + + if (port->sys_irq < 0) + { + return port->sys_irq; + } + +#ifdef RT_PCI_MSI + port->msi_irq = rt_dm_dev_get_irq(dev, 0); + + if (port->msi_irq < 0) + { + return port->msi_irq; + } +#endif + + port->ops = &dw_platform_pcie_host_ops; + + if ((err = dw_pcie_host_init(port))) + { + LOG_E("Failed to initialize host"); + return err; + } + + return RT_EOK; +} + +static rt_err_t dw_platform_add_pcie_ep(struct dw_platform_pcie *plat_pcie, + struct rt_device *dev) +{ + rt_err_t err; + struct dw_pcie *pci = plat_pcie->pci; + struct dw_pcie_ep *ep = &pci->endpoint; + + pci->dbi_base2 = rt_dm_dev_iomap_by_name(dev, "dbi2"); + + if (!pci->dbi_base2) + { + return -RT_EIO; + } + + err = rt_dm_dev_get_address_by_name(dev, "addr_space", &ep->aspace, &ep->aspace_size); + + if (err) + { + rt_iounmap(pci->dbi_base2); + return err; + } + + ep->ops = &dw_platform_pcie_ep_ops; + + if ((err = dw_pcie_ep_init(ep))) + { + LOG_E("Failed to initialize endpoint"); + return err; + } + + return RT_EOK; +} + +static rt_err_t dw_platform_pcie_probe(struct rt_platform_device *pdev) +{ + rt_err_t err; + struct dw_pcie *pci = RT_NULL; + struct dw_platform_pcie *plat_pcie; + struct rt_device *dev = &pdev->parent; + + if (!(plat_pcie = rt_calloc(1, sizeof(*plat_pcie)))) + { + return -RT_ENOMEM; + } + + if (!(pci = rt_calloc(1, sizeof(*pci)))) + { + err = -RT_ENOMEM; + goto _fail; + } + + plat_pcie->pci = pci; + plat_pcie->soc_data = pdev->id->data; + + pci->dev = dev; + pci->ops = &dw_platform_pcie_ops; + pci->dbi_base = rt_dm_dev_iomap_by_name(dev, "dbi"); + + if (!pci->dbi_base) + { + err = -RT_EIO; + goto _fail; + } + + dev->user_data = plat_pcie; + + switch (plat_pcie->soc_data->mode) + { + case DW_PCIE_RC_TYPE: + if (!RT_KEY_ENABLED(RT_PCI_DW_HOST)) + { + err = -RT_ENOSYS; + goto _fail; + } + + if ((err = dw_platform_add_pcie_port(plat_pcie, dev))) + { + goto _fail; + } + break; + + case DW_PCIE_EP_TYPE: + if (!RT_KEY_ENABLED(RT_PCI_DW_EP)) + { + err = -RT_ENOSYS; + goto _fail; + } + + if ((err = dw_platform_add_pcie_ep(plat_pcie, dev))) + { + goto _fail; + } + break; + + default: + LOG_E("Invalid device type %d", plat_pcie->soc_data->mode); + err = -RT_EINVAL; + goto _fail; + } + + return RT_EOK; + +_fail: + if (pci) + { + if (pci->dbi_base) + { + rt_iounmap(pci->dbi_base); + } + + rt_free(pci); + } + + rt_free(plat_pcie); + + return err; +} + +static rt_err_t dw_platform_pcie_remove(struct rt_platform_device *pdev) +{ + struct dw_platform_pcie *plat_pcie = pdev->parent.user_data; + + rt_pci_host_bridge_remove(plat_pcie->pci->port.bridge); + dw_pcie_host_free(&plat_pcie->pci->port); + + rt_iounmap(plat_pcie->pci->dbi_base); + rt_free(plat_pcie->pci); + + rt_free(plat_pcie); + + return RT_EOK; +} + +static const struct dw_dw_platform_pcie_soc_data dw_platform_pcie_rc_soc_data = +{ + .mode = DW_PCIE_RC_TYPE, +}; + +static const struct dw_dw_platform_pcie_soc_data dw_platform_pcie_ep_soc_data = +{ + .mode = DW_PCIE_EP_TYPE, +}; + +static const struct rt_ofw_node_id dw_platform_pcie_ofw_ids[] = +{ + { .compatible = "snps,dw-pcie", .data = &dw_platform_pcie_rc_soc_data }, + { .compatible = "snps,dw-pcie-ep", .data = &dw_platform_pcie_ep_soc_data }, + { /* sentinel */ } +}; + +static struct rt_platform_driver dw_platform_pcie_driver = +{ + .name = "dw-pcie", + .ids = dw_platform_pcie_ofw_ids, + + .probe = dw_platform_pcie_probe, + .remove = dw_platform_pcie_remove, +}; +RT_PLATFORM_DRIVER_EXPORT(dw_platform_pcie_driver); diff --git a/rt-thread/components/drivers/pci/host/pci-host-common.c b/rt-thread/components/drivers/pci/host/pci-host-common.c new file mode 100644 index 0000000..776c020 --- /dev/null +++ b/rt-thread/components/drivers/pci/host/pci-host-common.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#include + +#include "../ecam.h" + +rt_err_t pci_host_common_probe(struct rt_platform_device *pdev) +{ + void *base; + rt_err_t err; + struct rt_device *dev = &pdev->parent; + struct pci_ecam_config_window *conf_win; + struct rt_pci_host_bridge *host_bridge = rt_pci_host_bridge_alloc(0); + + if (!host_bridge) + { + return -RT_ENOMEM; + } + + if (!(base = rt_dm_dev_iomap(dev, 0))) + { + err = -RT_EIO; + goto _fail; + } + + host_bridge->parent.ofw_node = dev->ofw_node; + + if ((err = rt_pci_host_bridge_init(host_bridge))) + { + goto _fail; + } + + host_bridge->sysdata = conf_win = pci_ecam_create(host_bridge, + (const struct pci_ecam_ops *)pdev->id->data); + + if (!conf_win) + { + err = -RT_ENOMEM; + goto _fail; + } + + conf_win->win = base; + conf_win->priv = host_bridge; + + if ((err = rt_pci_host_bridge_probe(host_bridge))) + { + goto _fail; + } + + dev->user_data = host_bridge; + + return RT_EOK; + +_fail: + if (base) + { + rt_iounmap(base); + } + rt_pci_host_bridge_free(host_bridge); + + return err; +} + +rt_err_t pci_host_common_remove(struct rt_platform_device *pdev) +{ + struct pci_ecam_config_window *conf_win; + struct rt_pci_host_bridge *host_bridge = pdev->parent.user_data; + + rt_pci_host_bridge_remove(host_bridge); + + conf_win = host_bridge->sysdata; + + rt_iounmap(conf_win->win); + rt_pci_host_bridge_free(host_bridge); + + return RT_EOK; +} diff --git a/rt-thread/components/drivers/pci/host/pci-host-generic.c b/rt-thread/components/drivers/pci/host/pci-host-generic.c new file mode 100644 index 0000000..7496d52 --- /dev/null +++ b/rt-thread/components/drivers/pci/host/pci-host-generic.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#include + +#include "../ecam.h" + +static const struct pci_ecam_ops gen_pci_cfg_cam_bus_ops = +{ + .bus_shift = 16, + .pci_ops = + { + .map = pci_ecam_map, + .read = rt_pci_bus_read_config_uxx, + .write = rt_pci_bus_write_config_uxx, + } +}; + +static void *pci_dw_ecam_map_bus(struct rt_pci_bus *bus, rt_uint32_t devfn, int where) +{ + struct pci_ecam_config_window *conf_win = bus->sysdata; + + if (bus->number == conf_win->bus_range[0] && RT_PCI_SLOT(devfn) > 0) + { + return RT_NULL; + } + + return pci_ecam_map(bus, devfn, where); +} + +static const struct pci_ecam_ops pci_dw_ecam_bus_ops = +{ + .pci_ops = + { + .map = pci_dw_ecam_map_bus, + .read = rt_pci_bus_read_config_uxx, + .write = rt_pci_bus_write_config_uxx, + } +}; + +static const struct rt_ofw_node_id gen_pci_ofw_ids[] = +{ + { .compatible = "pci-host-cam-generic", .data = &gen_pci_cfg_cam_bus_ops }, + { .compatible = "pci-host-ecam-generic", .data = &pci_generic_ecam_ops }, + { .compatible = "marvell,armada8k-pcie-ecam", .data = &pci_dw_ecam_bus_ops }, + { .compatible = "socionext,synquacer-pcie-ecam", .data = &pci_dw_ecam_bus_ops }, + { .compatible = "snps,dw-pcie-ecam", .data = &pci_dw_ecam_bus_ops }, + { /* sentinel */ } +}; + +static struct rt_platform_driver gen_pci_driver = +{ + .name = "pci-host-generic", + .ids = gen_pci_ofw_ids, + + .probe = pci_host_common_probe, + .remove = pci_host_common_remove, +}; +RT_PLATFORM_DRIVER_EXPORT(gen_pci_driver); diff --git a/rt-thread/components/drivers/pci/irq.c b/rt-thread/components/drivers/pci/irq.c new file mode 100644 index 0000000..c7bd1a8 --- /dev/null +++ b/rt-thread/components/drivers/pci/irq.c @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-11-07 GuEe-GUI first version + */ + +#include + +#define DBG_TAG "pci.irq" +#define DBG_LVL DBG_INFO +#include + +#include + +void rt_pci_assign_irq(struct rt_pci_device *pdev) +{ + int irq = 0; + rt_uint8_t pin, slot = -1; + struct rt_pci_host_bridge *host_bridge = rt_pci_find_host_bridge(pdev->bus); + + if (!host_bridge->irq_map) + { + LOG_D("PCI-Device<%s> runtime IRQ mapping not provided by platform", + rt_dm_dev_get_name(&pdev->parent)); + + return; + } + + /* Must try the swizzle when interrupt line passes through a P2P bridge */ + rt_pci_read_config_u8(pdev, PCIR_INTPIN, &pin); + + if (pin > RT_PCI_INTX_PIN_MAX) + { + pin = 1; + } + + if (pin) + { + if (host_bridge->irq_slot) + { + slot = host_bridge->irq_slot(pdev, &pin); + } + + /* Map IRQ */ + if ((irq = host_bridge->irq_map(pdev, slot, pin)) == -1) + { + irq = 0; + } + } + pdev->irq = irq; + + LOG_D("PCI-Device<%s> assign IRQ: got %d", rt_dm_dev_get_name(&pdev->parent), pdev->irq); + + /* Save IRQ */ + rt_pci_write_config_u8(pdev, PCIR_INTLINE, irq); +} diff --git a/rt-thread/components/drivers/pci/msi/SConscript b/rt-thread/components/drivers/pci/msi/SConscript new file mode 100644 index 0000000..4def41c --- /dev/null +++ b/rt-thread/components/drivers/pci/msi/SConscript @@ -0,0 +1,15 @@ +from building import * + +group = [] + +if not GetDepend(['RT_PCI_MSI']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../../include'] + +src = ['device.c', 'irq.c', 'msi.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/pci/msi/device.c b/rt-thread/components/drivers/pci/msi/device.c new file mode 100644 index 0000000..36d0d0d --- /dev/null +++ b/rt-thread/components/drivers/pci/msi/device.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#include + +void rt_pci_msi_init(struct rt_pci_device *pdev) +{ + if (pdev && (pdev->msi_cap = rt_pci_find_capability(pdev, PCIY_MSI))) + { + rt_uint16_t ctrl; + + rt_pci_read_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, &ctrl); + + if (ctrl & PCIM_MSICTRL_MSI_ENABLE) + { + rt_pci_write_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, ctrl & ~PCIM_MSICTRL_MSI_ENABLE); + } + + if (!(ctrl & PCIM_MSICTRL_64BIT)) + { + pdev->no_64bit_msi = RT_TRUE; + } + } +} + +void rt_pci_msix_init(struct rt_pci_device *pdev) +{ + if (pdev && (pdev->msix_cap = rt_pci_find_capability(pdev, PCIY_MSIX))) + { + rt_uint16_t ctrl; + + rt_pci_read_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, &ctrl); + + if (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) + { + rt_pci_write_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE); + } + } +} diff --git a/rt-thread/components/drivers/pci/msi/irq.c b/rt-thread/components/drivers/pci/msi/irq.c new file mode 100644 index 0000000..8e81e5d --- /dev/null +++ b/rt-thread/components/drivers/pci/msi/irq.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#include + +#define DBG_TAG "pci.msi.irq" +#define DBG_LVL DBG_INFO +#include + +static struct rt_spinlock msi_irq_map_lock = {}; +static RT_BITMAP_DECLARE(msi_irq_map, MAX_HANDLERS) = {}; + +rt_err_t rt_pci_msi_setup_irqs(struct rt_pci_device *pdev, int nvec, int type) +{ + int irq, index = 0, irq_nr = 0; + rt_err_t err = RT_EOK; + struct rt_pic_irq *pirq; + struct rt_pic *msi_pic; + struct rt_pci_msi_desc *desc; + + if (!pdev) + { + return -RT_EINVAL; + } + + msi_pic = pdev->msi_pic; + + if (type == PCIY_MSI) + { + int last_irq = -1, irq_idx; + rt_size_t irq_nr; + + desc = rt_pci_msi_first_desc(pdev); + irq_nr = 1 << desc->msi.cap.multi_msg_use; + + rt_hw_spin_lock(&msi_irq_map_lock.lock); + + _retry: + for (int i = 0; i < irq_nr; ++i) + { + if ((irq = msi_pic->ops->irq_alloc_msi(msi_pic, desc)) < 0) + { + err = irq; + + LOG_E("Setup %s[%d] IRQ error = %s", "MSI", i, rt_strerror(err)); + + break; + } + + if (last_irq >= 0 && last_irq + 1 != irq) + { + for (int idx = 0; idx < i; ++i, --last_irq) + { + rt_bitmap_set_bit(msi_irq_map, last_irq); + } + + last_irq = irq; + goto _retry; + } + + last_irq = irq; + } + + if (!err) + { + /* Get the first irq */ + desc->irq = irq - (irq_nr - 1); + } + + rt_bitmap_for_each_set_bit(msi_irq_map, irq_idx, MAX_HANDLERS) + { + msi_pic->ops->irq_free_msi(msi_pic, irq_idx); + + /* Free bit so the next user doesn't need to bzero */ + rt_bitmap_clear_bit(msi_irq_map, irq_idx); + } + + rt_hw_spin_unlock(&msi_irq_map_lock.lock); + + if (!err) + { + for (int idx = 0; idx < nvec; ++idx) + { + pirq = rt_pic_find_pirq(msi_pic, irq + idx); + pirq->msi_desc = desc; + + msi_pic->ops->irq_compose_msi_msg(pirq, &desc->msg); + + rt_pci_msi_write_msg(desc, &desc->msg); + } + } + } + else if (type == PCIY_MSIX) + { + rt_pci_msi_for_each_desc(pdev, desc) + { + if ((irq = msi_pic->ops->irq_alloc_msi(msi_pic, desc)) < 0) + { + err = irq; + + LOG_E("Setup %s[%d] IRQ error = %s", "MSI-X", + desc->msix.index, rt_strerror(err)); + + break; + } + + desc->irq = irq; + pirq = rt_pic_find_pirq(msi_pic, irq); + pirq->msi_desc = desc; + + msi_pic->ops->irq_compose_msi_msg(pirq, &desc->msg); + + rt_pci_msi_write_msg(desc, &desc->msg); + + ++irq_nr; + } + + if (err) + { + rt_pci_msi_for_each_desc(pdev, desc) + { + if (index >= irq_nr) + { + break; + } + + msi_pic->ops->irq_free_msi(msi_pic, desc->irq); + + ++index; + } + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} diff --git a/rt-thread/components/drivers/pci/msi/msi.c b/rt-thread/components/drivers/pci/msi/msi.c new file mode 100644 index 0000000..eb0d578 --- /dev/null +++ b/rt-thread/components/drivers/pci/msi/msi.c @@ -0,0 +1,949 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-11-07 GuEe-GUI first version + */ + +#include +#include + +#define DBG_TAG "pci.msi" +#define DBG_LVL DBG_INFO +#include + +/* PCI has 2048 max IRQs in MSI-X */ +static RT_IRQ_AFFINITY_DECLARE(msi_affinity_default[2048]) rt_section(".bss.noclean.pci.msi"); + +rt_inline void spin_lock(struct rt_spinlock *lock) +{ + rt_hw_spin_lock(&lock->lock); +} + +rt_inline void spin_unlock(struct rt_spinlock *lock) +{ + rt_hw_spin_unlock(&lock->lock); +} + +rt_inline void *msix_table_base(struct rt_pci_msix_conf *msix) +{ + return msix->table_base + msix->index * PCIM_MSIX_ENTRY_SIZE; +} + +rt_inline void *msix_vector_ctrl_base(struct rt_pci_msix_conf *msix) +{ + return msix_table_base(msix) + PCIM_MSIX_ENTRY_VECTOR_CTRL; +} + +rt_inline void msix_write_vector_ctrl(struct rt_pci_msix_conf *msix, + rt_uint32_t ctrl) +{ + void *vc_addr = msix_vector_ctrl_base(msix); + + HWREG32(vc_addr) = ctrl; +} + +rt_inline void msix_mask(struct rt_pci_msix_conf *msix) +{ + msix->msg_ctrl |= PCIM_MSIX_ENTRYVECTOR_CTRL_MASK; + msix_write_vector_ctrl(msix, msix->msg_ctrl); + + /* Flush write to device */ + HWREG32(msix->table_base); +} + +static void msix_update_ctrl(struct rt_pci_device *pdev, + rt_uint16_t clear, rt_uint16_t set) +{ + rt_uint16_t msgctl; + + rt_pci_read_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, &msgctl); + msgctl &= ~clear; + msgctl |= set; + rt_pci_write_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, msgctl); +} + +rt_inline void msix_unmask(struct rt_pci_msix_conf *msix) +{ + msix->msg_ctrl &= ~PCIM_MSIX_ENTRYVECTOR_CTRL_MASK; + msix_write_vector_ctrl(msix, msix->msg_ctrl); +} + +rt_inline rt_uint32_t msi_multi_mask(struct rt_pci_msi_conf *msi) +{ + if (msi->cap.multi_msg_max >= 5) + { + return 0xffffffff; + } + + return (1 << (1 << msi->cap.multi_msg_max)) - 1; +} + +static void msi_write_mask(struct rt_pci_msi_conf *msi, + rt_uint32_t clear, rt_uint32_t set, struct rt_pci_device *pdev) +{ + if (msi->cap.is_masking) + { + rt_ubase_t level = rt_spin_lock_irqsave(&pdev->msi_lock); + + msi->mask &= ~clear; + msi->mask |= set; + rt_pci_write_config_u32(pdev, msi->mask_pos, msi->mask); + + rt_spin_unlock_irqrestore(&pdev->msi_lock, level); + } +} + +rt_inline void msi_mask(struct rt_pci_msi_conf *msi, + rt_uint32_t mask, struct rt_pci_device *pdev) +{ + msi_write_mask(msi, 0, mask, pdev); +} + +rt_inline void msi_unmask(struct rt_pci_msi_conf *msi, + rt_uint32_t mask, struct rt_pci_device *pdev) +{ + msi_write_mask(msi, mask, 0, pdev); +} + +static void msi_write_enable(struct rt_pci_device *pdev, rt_bool_t enable) +{ + rt_uint16_t msgctl; + + rt_pci_read_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, &msgctl); + + msgctl &= ~PCIM_MSICTRL_MSI_ENABLE; + + if (enable) + { + msgctl |= PCIM_MSICTRL_MSI_ENABLE; + } + + rt_pci_write_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, msgctl); +} + +static void msi_affinity_init(struct rt_pci_msi_desc *desc, int msi_index, + rt_bitmap_t *cpumasks) +{ + int irq; + struct rt_pic_irq *pirq; + struct rt_pci_device *pdev = desc->pdev; + struct rt_pic *msi_pic = pdev->msi_pic; + + irq = desc->irq + desc->is_msix ? 0 : msi_index; + pirq = rt_pic_find_pirq(msi_pic, irq); + + /* Save affinity */ + if (desc->is_msix) + { + desc->affinity = pirq->affinity; + } + else + { + desc->affinities[msi_index] = pirq->affinity; + } + + if ((void *)cpumasks > (void *)msi_affinity_default && + (void *)cpumasks < (void *)msi_affinity_default + sizeof(msi_affinity_default)) + { + rt_uint64_t data_address; + + /* Get MSI/MSI-X write data adddress */ + data_address = desc->msg.address_hi; + data_address <<= 32; + data_address |= desc->msg.address_lo; + + /* Prepare affinity */ + cpumasks = pirq->affinity; + + rt_numa_memory_affinity(data_address, cpumasks); + } + else if (rt_bitmap_next_set_bit(cpumasks, 0, RT_CPUS_NR) >= RT_CPUS_NR) + { + /* No affinity info found, give up */ + return; + } + + if (!rt_pic_irq_set_affinity(irq, cpumasks)) + { + if (msi_pic->ops->irq_write_msi_msg) + { + msi_pic->ops->irq_write_msi_msg(pirq, &desc->msg); + } + } +} + +void rt_pci_msi_shutdown(struct rt_pci_device *pdev) +{ + struct rt_pci_msi_desc *desc; + + if (!pdev) + { + return; + } + + msi_write_enable(pdev, RT_FALSE); + rt_pci_intx(pdev, RT_TRUE); + + if ((desc = rt_pci_msi_first_desc(pdev))) + { + msi_unmask(&desc->msi, msi_multi_mask(&desc->msi), pdev); + } + + /* Restore pdev->irq to its default pin-assertion IRQ */ + pdev->irq = desc->msi.default_irq; + pdev->msi_enabled = RT_FALSE; +} + +void rt_pci_msix_shutdown(struct rt_pci_device *pdev) +{ + struct rt_pci_msi_desc *desc; + + if (!pdev) + { + return; + } + + rt_pci_msi_for_each_desc(pdev, desc) + { + msix_mask(&desc->msix); + } + + msix_update_ctrl(pdev, PCIM_MSIXCTRL_MSIX_ENABLE, 0); + + rt_pci_intx(pdev, RT_TRUE); + pdev->msix_enabled = RT_FALSE; +} + +void rt_pci_msi_free_irqs(struct rt_pci_device *pdev) +{ + struct rt_pci_msi_desc *desc, *last_desc = RT_NULL; + + if (!pdev) + { + return; + } + + if (pdev->msix_base) + { + rt_iounmap(pdev->msix_base); + pdev->msix_base = RT_NULL; + } + + rt_pci_msi_for_each_desc(pdev, desc) + { + /* To safety */ + if (last_desc) + { + rt_list_remove(&last_desc->list); + rt_free(last_desc); + } + last_desc = desc; + } + + /* The last one */ + if (last_desc) + { + rt_list_remove(&last_desc->list); + rt_free(last_desc); + } +} + +void rt_pci_msi_write_msg(struct rt_pci_msi_desc *desc, struct rt_pci_msi_msg *msg) +{ + struct rt_pci_device *pdev = desc->pdev; + + if (desc->is_msix) + { + void *msix_entry; + rt_bool_t unmasked; + rt_uint32_t msgctl; + struct rt_pci_msix_conf *msix = &desc->msix; + + msgctl = msix->msg_ctrl; + unmasked = !(msgctl & PCIM_MSIX_ENTRYVECTOR_CTRL_MASK); + msix_entry = msix_table_base(msix); + + if (unmasked) + { + msix_write_vector_ctrl(msix, msgctl | PCIM_MSIX_ENTRYVECTOR_CTRL_MASK); + } + + HWREG32(msix_entry + PCIM_MSIX_ENTRY_LOWER_ADDR) = msg->address_lo; + HWREG32(msix_entry + PCIM_MSIX_ENTRY_UPPER_ADDR) = msg->address_hi; + HWREG32(msix_entry + PCIM_MSIX_ENTRY_DATA) = msg->data; + + if (unmasked) + { + msix_write_vector_ctrl(msix, msgctl); + } + + /* Ensure that the writes are visible in the device */ + HWREG32(msix_entry + PCIM_MSIX_ENTRY_DATA); + } + else + { + rt_uint16_t msgctl; + int pos = pdev->msi_cap; + struct rt_pci_msi_conf *msi = &desc->msi; + + rt_pci_read_config_u16(pdev, pos + PCIR_MSI_CTRL, &msgctl); + msgctl &= ~PCIM_MSICTRL_MME_MASK; + msgctl |= msi->cap.multi_msg_use << PCIM_MSICTRL_MME_SHIFT; + rt_pci_write_config_u16(pdev, pos + PCIR_MSI_CTRL, msgctl); + + rt_pci_write_config_u32(pdev, pos + PCIR_MSI_ADDR, msg->address_lo); + + /* + * The value stored in this field is related to the processor system, + * the processor will initialize this field + * when the PCIe device is initialized, and the rules for filling + * in this field are not the same for different processors. + * If the Multiple Message Enable field is not 0b000 (multiple IRQs), + * the PCIe device can send different interrupt requests + * by changing the low data in the Message Data field + */ + if (msi->cap.is_64bit) + { + rt_pci_write_config_u32(pdev, pos + PCIR_MSI_ADDR_HIGH, msg->address_hi); + rt_pci_write_config_u16(pdev, pos + PCIR_MSI_DATA_64BIT, msg->data); + } + else + { + rt_pci_write_config_u16(pdev, pos + PCIR_MSI_DATA, msg->data); + } + + /* Ensure that the writes are visible in the device */ + rt_pci_read_config_u16(pdev, pos + PCIR_MSI_CTRL, &msgctl); + } + + desc->msg = *msg; + + if (desc->write_msi_msg) + { + desc->write_msi_msg(desc, desc->write_msi_msg_data); + } +} + +void rt_pci_msi_mask_irq(struct rt_pic_irq *pirq) +{ + struct rt_pci_msi_desc *desc; + + if (pirq && (desc = pirq->msi_desc)) + { + if (desc->is_msix) + { + msix_mask(&desc->msix); + } + else + { + msi_mask(&desc->msi, RT_BIT(pirq->irq - desc->irq), desc->pdev); + } + } +} + +void rt_pci_msi_unmask_irq(struct rt_pic_irq *pirq) +{ + struct rt_pci_msi_desc *desc; + + if (pirq && (desc = pirq->msi_desc)) + { + if (desc->is_msix) + { + msix_unmask(&desc->msix); + } + else + { + msi_unmask(&desc->msi, RT_BIT(pirq->irq - desc->irq), desc->pdev); + } + } +} + +rt_ssize_t rt_pci_alloc_vector(struct rt_pci_device *pdev, int min, int max, + rt_uint32_t flags, RT_IRQ_AFFINITY_DECLARE((*affinities))) +{ + rt_ssize_t res = -RT_ENOSYS; + + if (!pdev || min > max) + { + return -RT_EINVAL; + } + + if (flags & RT_PCI_IRQ_F_AFFINITY) + { + if (!affinities) + { + affinities = msi_affinity_default; + } + } + else + { + affinities = RT_NULL; + } + + if (flags & RT_PCI_IRQ_F_MSIX) + { + res = rt_pci_msix_enable_range_affinity(pdev, RT_NULL, min, max, affinities); + + if (res > 0) + { + return res; + } + } + + if (flags & RT_PCI_IRQ_F_MSI) + { + res = rt_pci_msi_enable_range_affinity(pdev, min, max, affinities); + + if (res > 0) + { + return res; + } + } + + if (flags & RT_PCI_IRQ_F_LEGACY) + { + if (min == 1 && pdev->irq >= 0) + { + if (affinities) + { + int cpuid; + RT_IRQ_AFFINITY_DECLARE(old_affinity); + + /* INTx is shared, we should update it */ + rt_pic_irq_get_affinity(pdev->irq, old_affinity); + + rt_bitmap_for_each_set_bit(affinities[0], cpuid, RT_CPUS_NR) + { + RT_IRQ_AFFINITY_SET(old_affinity, cpuid); + } + + rt_pic_irq_set_affinity(pdev->irq, old_affinity); + } + + rt_pci_intx(pdev, RT_TRUE); + + return min; + } + } + + return res; +} + +void rt_pci_free_vector(struct rt_pci_device *pdev) +{ + if (!pdev) + { + return; + } + + rt_pci_msi_disable(pdev); + rt_pci_msix_disable(pdev); + rt_pci_irq_mask(pdev); +} + +static rt_err_t msi_verify_entries(struct rt_pci_device *pdev) +{ + if (pdev->no_64bit_msi) + { + struct rt_pci_msi_desc *desc; + + rt_pci_msi_for_each_desc(pdev, desc) + { + if (desc->msg.address_hi) + { + LOG_D("%s: Arch assigned 64-bit MSI address %08x%08x" + "but device only supports 32 bits", + rt_dm_dev_get_name(&pdev->parent), + desc->msg.address_hi, desc->msg.address_lo); + + return -RT_EIO; + } + } + } + + return RT_EOK; +} + +static rt_err_t msi_insert_desc(struct rt_pci_device *pdev, + struct rt_pci_msi_desc *init_desc) +{ + rt_size_t msi_affinity_ptr_size = 0; + struct rt_pci_msi_desc *msi_desc; + + if (!init_desc->is_msix) + { + msi_affinity_ptr_size += sizeof(msi_desc->affinities[0]) * 32; + } + + msi_desc = rt_calloc(1, sizeof(*msi_desc) + msi_affinity_ptr_size); + + if (!msi_desc) + { + return -RT_ENOMEM; + } + + rt_memcpy(msi_desc, init_desc, sizeof(*msi_desc)); + + if (!init_desc->is_msix) + { + msi_desc->affinities = (void *)msi_desc + sizeof(*msi_desc); + } + + msi_desc->pdev = pdev; + rt_list_init(&msi_desc->list); + rt_list_insert_before(&pdev->msi_desc_nodes, &msi_desc->list); + + return RT_EOK; +} + +rt_ssize_t rt_pci_msi_vector_count(struct rt_pci_device *pdev) +{ + rt_uint16_t msgctl; + + if (!pdev) + { + return -RT_EINVAL; + } + + if (!pdev->msi_cap) + { + return -RT_EINVAL; + } + + rt_pci_read_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, &msgctl); + + return 1 << ((msgctl & PCIM_MSICTRL_MMC_MASK) >> 1); +} + +rt_err_t rt_pci_msi_disable(struct rt_pci_device *pdev) +{ + if (!pdev) + { + return -RT_EINVAL; + } + + if (!pdev->msi_enabled) + { + return -RT_EINVAL; + } + + spin_lock(&pdev->msi_lock); + + rt_pci_msi_shutdown(pdev); + rt_pci_msi_free_irqs(pdev); + + spin_unlock(&pdev->msi_lock); + + return RT_EOK; +} + +static rt_err_t msi_setup_msi_desc(struct rt_pci_device *pdev, int nvec) +{ + rt_uint16_t msgctl; + struct rt_pci_msi_desc desc; + + rt_memset(&desc, 0, sizeof(desc)); + + desc.vector_used = nvec; + desc.vector_count = rt_pci_msi_vector_count(pdev); + desc.is_msix = RT_FALSE; + + rt_pci_read_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, &msgctl); + + desc.msi.cap.is_64bit = !!(msgctl & PCIM_MSICTRL_64BIT); + desc.msi.cap.is_masking = !!(msgctl & PCIM_MSICTRL_VECTOR); + desc.msi.cap.multi_msg_max = (msgctl & PCIM_MSICTRL_MMC_MASK) >> 1; + + for (int log2 = 0; log2 < 5; ++log2) + { + if (nvec <= (1 << log2)) + { + desc.msi.cap.multi_msg_use = log2; + break; + } + } + + if (desc.msi.cap.is_64bit) + { + desc.msi.mask_pos = pdev->msi_cap + PCIR_MSI_MASK_64BIT; + } + else + { + desc.msi.mask_pos = pdev->msi_cap + PCIR_MSI_MASK; + } + + /* Save pdev->irq for its default pin-assertion IRQ */ + desc.msi.default_irq = pdev->irq; + + if (desc.msi.cap.is_masking) + { + /* Get the old mask status */ + rt_pci_read_config_u32(pdev, desc.msi.mask_pos, &desc.msi.mask); + } + + return msi_insert_desc(pdev, &desc); +} + +static rt_ssize_t msi_capability_init(struct rt_pci_device *pdev, + int nvec, RT_IRQ_AFFINITY_DECLARE((*affinities))) +{ + rt_err_t err; + struct rt_pci_msi_desc *desc; + + msi_write_enable(pdev, RT_FALSE); + + spin_lock(&pdev->msi_lock); + + if (!(err = msi_setup_msi_desc(pdev, nvec))) + { + /* All MSIs are unmasked by default; mask them all */ + desc = rt_pci_msi_first_desc(pdev); + msi_mask(&desc->msi, msi_multi_mask(&desc->msi), pdev); + + if (!(err = rt_pci_msi_setup_irqs(pdev, nvec, PCIY_MSI))) + { + err = msi_verify_entries(pdev); + } + + if (err) + { + msi_unmask(&desc->msi, msi_multi_mask(&desc->msi), pdev); + } + } + + spin_unlock(&pdev->msi_lock); + + if (err) + { + rt_pci_msi_free_irqs(pdev); + + LOG_E("%s: Setup %s interrupts(%d) error = %s", + rt_dm_dev_get_name(&pdev->parent), "MSI", nvec, rt_strerror(err)); + + return err; + } + + if (affinities) + { + for (int idx = 0; idx < nvec; ++idx) + { + msi_affinity_init(desc, idx, affinities[idx]); + } + } + + /* Disable INTX */ + rt_pci_intx(pdev, RT_FALSE); + + /* Set MSI enabled bits */ + msi_write_enable(pdev, RT_TRUE); + + pdev->irq = desc->irq; + + pdev->msi_enabled = RT_TRUE; + + return nvec; +} + +rt_ssize_t rt_pci_msi_enable_range_affinity(struct rt_pci_device *pdev, + int min, int max, RT_IRQ_AFFINITY_DECLARE((*affinities))) +{ + int nvec = max; + rt_size_t entries_nr; + + if (!pdev || min > max) + { + return -RT_EINVAL; + } + + if (pdev->no_msi) + { + return -RT_ENOSYS; + } + + if (!pdev->msi_pic) + { + return -RT_ENOSYS; + } + + if (pdev->msi_enabled) + { + LOG_W("%s: MSI is enabled", rt_dm_dev_get_name(&pdev->parent)); + + return -RT_EINVAL; + } + + entries_nr = rt_pci_msi_vector_count(pdev); + + if (entries_nr < 0) + { + return entries_nr; + } + + if (nvec > entries_nr) + { + return -RT_EEMPTY; + } + + return msi_capability_init(pdev, nvec, affinities); +} + +rt_ssize_t rt_pci_msix_vector_count(struct rt_pci_device *pdev) +{ + rt_uint16_t msgctl; + + if (!pdev) + { + return -RT_EINVAL; + } + + if (!pdev->msix_cap) + { + return -RT_EINVAL; + } + + rt_pci_read_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, &msgctl); + + return rt_pci_msix_table_size(msgctl); +} + +rt_err_t rt_pci_msix_disable(struct rt_pci_device *pdev) +{ + if (!pdev) + { + return -RT_EINVAL; + } + + if (!pdev->msix_enabled) + { + return -RT_EINVAL; + } + + spin_lock(&pdev->msi_lock); + + rt_pci_msix_shutdown(pdev); + rt_pci_msi_free_irqs(pdev); + + spin_unlock(&pdev->msi_lock); + + return RT_EOK; +} + +static void *msix_table_remap(struct rt_pci_device *pdev, rt_size_t entries_nr) +{ + rt_uint8_t bir; + rt_uint32_t table_offset; + rt_ubase_t table_base_phys; + + rt_pci_read_config_u32(pdev, pdev->msix_cap + PCIR_MSIX_TABLE, &table_offset); + bir = (rt_uint8_t)(table_offset & PCIM_MSIX_BIR_MASK); + + if (pdev->resource[bir].flags & PCI_BUS_REGION_F_NONE) + { + LOG_E("%s: BAR[bir = %d] is invalid", rt_dm_dev_get_name(&pdev->parent), bir); + + return RT_NULL; + } + + table_base_phys = pdev->resource[bir].base + (table_offset & ~PCIM_MSIX_BIR_MASK); + + return rt_ioremap((void *)table_base_phys, entries_nr * PCIM_MSIX_ENTRY_SIZE); +} + +static rt_err_t msix_setup_msi_descs(struct rt_pci_device *pdev, + void *table_base, struct rt_pci_msix_entry *entries, int nvec) +{ + rt_err_t err; + struct rt_pci_msi_desc desc; + + rt_memset(&desc, 0, sizeof(desc)); + + desc.vector_used = 1; + desc.vector_count = rt_pci_msix_vector_count(pdev); + + desc.is_msix = RT_TRUE; + desc.msix.table_base = table_base; + + for (int i = 0; i < nvec; ++i) + { + void *table_entry; + int index = entries ? entries[i].index : i; + + desc.msix.index = index; + table_entry = msix_table_base(&desc.msix); + + desc.msix.msg_ctrl = HWREG32(table_entry + PCIM_MSIX_ENTRY_VECTOR_CTRL); + + if ((err = msi_insert_desc(pdev, &desc))) + { + break; + } + } + + return err; +} + +static rt_ssize_t msix_capability_init(struct rt_pci_device *pdev, + struct rt_pci_msix_entry *entries, int nvec, + RT_IRQ_AFFINITY_DECLARE((*affinities))) +{ + rt_err_t err; + rt_uint16_t msgctl; + rt_size_t table_size; + void *table_base, *table_entry; + struct rt_pci_msi_desc *desc; + struct rt_pci_msix_entry *entry; + + /* + * Some devices require MSI-X to be enabled before the MSI-X + * registers can be accessed. + * Mask all the vectors to prevent interrupts coming in before + * they're fully set up. + */ + msix_update_ctrl(pdev, 0, PCIM_MSIXCTRL_FUNCTION_MASK | PCIM_MSIXCTRL_MSIX_ENABLE); + + rt_pci_read_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, &msgctl); + /* Request & Map MSI-X table region */ + table_size = rt_pci_msix_table_size(msgctl); + table_base = msix_table_remap(pdev, table_size); + + if (!table_base) + { + LOG_E("%s: Remap MSI-X table fail", rt_dm_dev_get_name(&pdev->parent)); + + err = -RT_ENOMEM; + goto _out_disbale_msix; + } + + pdev->msix_base = table_base; + + spin_lock(&pdev->msi_lock); + + if (!(err = msix_setup_msi_descs(pdev, table_base, entries, nvec))) + { + if (!(err = rt_pci_msi_setup_irqs(pdev, nvec, PCIY_MSIX))) + { + /* Check if all MSI entries honor device restrictions */ + err = msi_verify_entries(pdev); + } + } + + spin_unlock(&pdev->msi_lock); + + if (err) + { + rt_pci_msi_free_irqs(pdev); + + LOG_E("%s: Setup %s interrupts(%d) error = %s", + rt_dm_dev_get_name(&pdev->parent), "MSI-X", nvec, rt_strerror(err)); + + goto _out_disbale_msix; + } + + entry = entries; + rt_pci_msi_for_each_desc(pdev, desc) + { + if (affinities) + { + msi_affinity_init(desc, desc->msix.index, affinities[entry->index]); + } + + entry->irq = desc->irq; + ++entry; + } + + /* Disable INTX */ + rt_pci_intx(pdev, RT_FALSE); + + /* Maske all table entries */ + table_entry = table_base; + for (int i = 0; i < table_size; ++i, table_entry += PCIM_MSIX_ENTRY_SIZE) + { + HWREG32(table_entry + PCIM_MSIX_ENTRY_VECTOR_CTRL) = PCIM_MSIX_ENTRYVECTOR_CTRL_MASK; + } + msix_update_ctrl(pdev, PCIM_MSIXCTRL_FUNCTION_MASK, 0); + + pdev->msix_enabled = RT_TRUE; + + return nvec; + +_out_disbale_msix: + msix_update_ctrl(pdev, PCIM_MSIXCTRL_FUNCTION_MASK | PCIM_MSIXCTRL_MSIX_ENABLE, 0); + + return err; +} + +rt_ssize_t rt_pci_msix_enable_range_affinity(struct rt_pci_device *pdev, + struct rt_pci_msix_entry *entries, int min, int max, + RT_IRQ_AFFINITY_DECLARE((*affinities))) +{ + int nvec = max; + rt_size_t entries_nr; + + if (!pdev || min > max) + { + return -RT_EINVAL; + } + + if (pdev->no_msi) + { + return -RT_ENOSYS; + } + + if (!pdev->msi_pic) + { + return -RT_ENOSYS; + } + + if (pdev->msix_enabled) + { + LOG_W("%s: MSI-X is enabled", rt_dm_dev_get_name(&pdev->parent)); + + return -RT_EINVAL; + } + + entries_nr = rt_pci_msix_vector_count(pdev); + + if (entries_nr < 0) + { + return entries_nr; + } + + if (nvec > entries_nr) + { + return -RT_EEMPTY; + } + + if (!entries) + { + return 0; + } + + /* Check if entries is valid */ + for (int i = 0; i < nvec; ++i) + { + struct rt_pci_msix_entry *target = &entries[i]; + + if (target->index >= entries_nr) + { + return -RT_EINVAL; + } + + for (int j = i + 1; j < nvec; ++j) + { + /* Check duplicate */ + if (target->index == entries[j].index) + { + LOG_E("%s: msix entry[%d].index = entry[%d].index", + rt_dm_dev_get_name(&pdev->parent), i, j); + + return -RT_EINVAL; + } + } + } + + return msix_capability_init(pdev, entries, nvec, affinities); +} diff --git a/rt-thread/components/drivers/pci/ofw.c b/rt-thread/components/drivers/pci/ofw.c new file mode 100644 index 0000000..0207e7a --- /dev/null +++ b/rt-thread/components/drivers/pci/ofw.c @@ -0,0 +1,609 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#include +#include + +#define DBG_TAG "pci.ofw" +#define DBG_LVL DBG_INFO +#include + +#include +#include +#include +#include +#include + +static rt_err_t pci_ofw_irq_parse(struct rt_pci_device *pdev, struct rt_ofw_cell_args *out_irq) +{ + rt_err_t err = RT_EOK; + rt_uint8_t pin; + fdt32_t map_addr[4]; + struct rt_pci_device *p2pdev; + struct rt_ofw_node *dev_np, *p2pnode = RT_NULL; + + /* Parse device tree if dev have a device node */ + dev_np = pdev->parent.ofw_node; + + if (dev_np) + { + err = rt_ofw_parse_irq_cells(dev_np, 0, out_irq); + + if (err) + { + return err; + } + } + + /* Assume #interrupt-cells is 1 */ + if ((err = rt_pci_read_config_u8(pdev, PCIR_INTPIN, &pin))) + { + goto _err; + } + + /* No pin, exit with no error message. */ + if (pin == 0) + { + return -RT_ENOSYS; + } + + /* Try local interrupt-map in the device node */ + if (rt_ofw_prop_read_raw(dev_np, "interrupt-map", RT_NULL)) + { + pin = rt_pci_irq_intx(pdev, pin); + p2pnode = dev_np; + } + + /* Walk up the PCI tree */ + while (!p2pnode) + { + p2pdev = pdev->bus->self; + + /* Is the root bus -> host bridge */ + if (rt_pci_is_root_bus(pdev->bus)) + { + struct rt_pci_host_bridge *host_bridge = pdev->bus->host_bridge; + + p2pnode = host_bridge->parent.ofw_node; + + if (!p2pnode) + { + err = -RT_EINVAL; + + goto _err; + } + } + else + { + /* Is P2P bridge */ + p2pnode = p2pdev->parent.ofw_node; + } + + if (p2pnode) + { + break; + } + + /* Try get INTx in P2P */ + pin = rt_pci_irq_intx(pdev, pin); + pdev = p2pdev; + } + + /* For more format detail, please read `components/drivers/ofw/irq.c:ofw_parse_irq_map` */ + out_irq->data = map_addr; + out_irq->args_count = 2; + out_irq->args[0] = 3; + out_irq->args[1] = 1; + + /* In addr cells */ + map_addr[0] = cpu_to_fdt32((pdev->bus->number << 16) | (pdev->devfn << 8)); + map_addr[1] = cpu_to_fdt32(0); + map_addr[2] = cpu_to_fdt32(0); + /* In pin cells */ + map_addr[3] = cpu_to_fdt32(pin); + + err = rt_ofw_parse_irq_map(p2pnode, out_irq); + +_err: + if (err == -RT_EEMPTY) + { + LOG_W("PCI-Device<%s> no interrupt-map found, INTx interrupts not available", + rt_dm_dev_get_name(&pdev->parent)); + LOG_W("PCI-Device<%s> possibly some PCI slots don't have level triggered interrupts capability", + rt_dm_dev_get_name(&pdev->parent)); + } + else if (err && err != -RT_ENOSYS) + { + LOG_E("PCI-Device<%s> irq parse failed with err = %s", + rt_dm_dev_get_name(&pdev->parent), rt_strerror(err)); + } + + return err; +} + +int rt_pci_ofw_irq_parse_and_map(struct rt_pci_device *pdev, + rt_uint8_t slot, rt_uint8_t pin) +{ + int irq = -1; + rt_err_t status; + struct rt_ofw_cell_args irq_args; + + if (!pdev) + { + goto _end; + } + + status = pci_ofw_irq_parse(pdev, &irq_args); + + if (status) + { + goto _end; + } + + irq = rt_ofw_map_irq(&irq_args); + + if (irq >= 0) + { + pdev->intx_pic = rt_pic_dynamic_cast(rt_ofw_data(irq_args.data)); + } + +_end: + return irq; +} + +static rt_err_t pci_ofw_parse_ranges(struct rt_ofw_node *dev_np, const char *propname, + int phy_addr_cells, int phy_size_cells, int cpu_addr_cells, + struct rt_pci_bus_region **out_regions, rt_size_t *out_regions_nr) +{ + const fdt32_t *cell; + rt_ssize_t total_cells; + int groups, space_code; + rt_uint32_t phy_addr[3]; + rt_uint64_t cpu_addr, phy_addr_size; + + *out_regions = RT_NULL; + *out_regions_nr = 0; + cell = rt_ofw_prop_read_raw(dev_np, propname, &total_cells); + + if (!cell) + { + return -RT_EEMPTY; + } + + groups = total_cells / sizeof(*cell) / (phy_addr_cells + phy_size_cells + cpu_addr_cells); + *out_regions = rt_malloc(groups * sizeof(struct rt_pci_bus_region)); + + if (!*out_regions) + { + return -RT_ENOMEM; + } + + for (int i = 0; i < groups; ++i) + { + /* + * ranges: + * phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr + * phys.low cell: llllllll llllllll llllllll llllllll + * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh + * + * n: relocatable region flag (doesn't play a role here) + * p: prefetchable (cacheable) region flag + * t: aliased address flag (doesn't play a role here) + * ss: space code + * 00: configuration space + * 01: I/O space + * 10: 32 bit memory space + * 11: 64 bit memory space + * bbbbbbbb: The PCI bus number + * ddddd: The device number + * fff: The function number. Used for multifunction PCI devices. + * rrrrrrrr: Register number; used for configuration cycles. + */ + + for (int j = 0; j < phy_addr_cells; ++j) + { + phy_addr[j] = rt_fdt_read_number(cell++, 1); + } + + space_code = (phy_addr[0] >> 24) & 0x3; + + cpu_addr = rt_fdt_read_number(cell, cpu_addr_cells); + cell += cpu_addr_cells; + phy_addr_size = rt_fdt_read_number(cell, phy_size_cells); + cell += phy_size_cells; + + (*out_regions)[i].phy_addr = ((rt_uint64_t)phy_addr[1] << 32) | phy_addr[2]; + (*out_regions)[i].cpu_addr = cpu_addr; + (*out_regions)[i].size = phy_addr_size; + + (*out_regions)[i].bus_start = (*out_regions)[i].phy_addr; + + if (space_code & 2) + { + (*out_regions)[i].flags = phy_addr[0] & (1U << 30) ? + PCI_BUS_REGION_F_PREFETCH : PCI_BUS_REGION_F_MEM; + } + else if (space_code & 1) + { + (*out_regions)[i].flags = PCI_BUS_REGION_F_IO; + } + else + { + (*out_regions)[i].flags = PCI_BUS_REGION_F_NONE; + } + + ++*out_regions_nr; + } + + return RT_EOK; +} + +rt_err_t rt_pci_ofw_parse_ranges(struct rt_ofw_node *dev_np, + struct rt_pci_host_bridge *host_bridge) +{ + rt_err_t err; + int phy_addr_cells = -1, phy_size_cells = -1, cpu_addr_cells; + + if (!dev_np || !host_bridge) + { + return -RT_EINVAL; + } + + cpu_addr_cells = rt_ofw_io_addr_cells(dev_np); + rt_ofw_prop_read_s32(dev_np, "#address-cells", &phy_addr_cells); + rt_ofw_prop_read_s32(dev_np, "#size-cells", &phy_size_cells); + + if (phy_addr_cells != 3 || phy_size_cells < 1 || cpu_addr_cells < 1) + { + return -RT_EINVAL; + } + + if (pci_ofw_parse_ranges(dev_np, "ranges", + phy_addr_cells, phy_size_cells, cpu_addr_cells, + &host_bridge->bus_regions, &host_bridge->bus_regions_nr)) + { + return -RT_EINVAL; + } + + if ((err = rt_pci_region_setup(host_bridge))) + { + rt_free(host_bridge->bus_regions); + host_bridge->bus_regions_nr = 0; + + return err; + } + + err = pci_ofw_parse_ranges(dev_np, "dma-ranges", + phy_addr_cells, phy_size_cells, cpu_addr_cells, + &host_bridge->dma_regions, &host_bridge->dma_regions_nr); + + if (err != -RT_EEMPTY) + { + rt_free(host_bridge->bus_regions); + host_bridge->bus_regions_nr = 0; + + LOG_E("%s: Read dma-ranges error = %s", rt_ofw_node_full_name(dev_np), + rt_strerror(err)); + + return err; + } + + return RT_EOK; +} + +rt_err_t rt_pci_ofw_host_bridge_init(struct rt_ofw_node *dev_np, + struct rt_pci_host_bridge *host_bridge) +{ + rt_err_t err; + const char *propname; + + if (!dev_np || !host_bridge) + { + return -RT_EINVAL; + } + + host_bridge->irq_slot = rt_pci_irq_slot; + host_bridge->irq_map = rt_pci_ofw_irq_parse_and_map; + + if (rt_ofw_prop_read_u32_array_index(dev_np, "bus-range", 0, 2, host_bridge->bus_range) < 0) + { + return -RT_EIO; + } + + propname = rt_ofw_get_prop_fuzzy_name(dev_np, ",pci-domain$"); + rt_ofw_prop_read_u32(dev_np, propname, &host_bridge->domain); + + err = rt_pci_ofw_parse_ranges(dev_np, host_bridge); + + return err; +} + +rt_err_t rt_pci_ofw_bus_init(struct rt_pci_bus *bus) +{ + rt_err_t err = RT_EOK; + + return err; +} + +rt_err_t rt_pci_ofw_bus_free(struct rt_pci_bus *bus) +{ + rt_err_t err = RT_EOK; + + return err; +} + +/* + * RID (Requester ID) is formatted such that: + * Bits [15:8] are the Bus number. + * Bits [7:3] are the Device number. + * Bits [2:0] are the Function number. + * + * msi-map: Maps a Requester ID to an MSI controller and associated + * msi-specifier data. The property is an arbitrary number of tuples of + * (rid-base,msi-controller,msi-base,length), where: + * + * - rid-base is a single cell describing the first RID matched by the entry. + * + * - msi-controller is a single phandle to an MSI controller + * + * - msi-base is an msi-specifier describing the msi-specifier produced for + * the first RID matched by the entry. + * + * - length is a single cell describing how many consecutive RIDs are matched + * following the rid-base. + * + * Any RID r in the interval [rid-base, rid-base + length) is associated with + * the listed msi-controller, with the msi-specifier (r - rid-base + msi-base). + * + * msi-map-mask: A mask to be applied to each Requester ID prior to being mapped + * to an msi-specifier per the msi-map property. + * + * msi-parent: Describes the MSI parent of the root complex itself. Where + * the root complex and MSI controller do not pass sideband data with MSI + * writes, this property may be used to describe the MSI controller(s) + * used by PCI devices under the root complex, if defined as such in the + * binding for the root complex. + * + * / { + * #address-cells = <1>; + * #size-cells = <1>; + * + * msi_a: msi-controller@a { + * reg = <0xa 0x1>; + * msi-controller; + * #msi-cells = <1>; + * }; + * + * msi_b: msi-controller@b { + * reg = <0xb 0x1>; + * msi-controller; + * #msi-cells = <1>; + * }; + * + * msi_c: msi-controller@c { + * reg = <0xc 0x1>; + * msi-controller; + * #msi-cells = <1>; + * }; + * + * Example (1) + * =========== + * pci: pci@f { + * reg = <0xf 0x1>; + * device_type = "pci"; + * + * // The sideband data provided to the MSI controller is + * // the RID, identity-mapped. + * msi-map = <0x0 &msi_a 0x0 0x10000>; + * }; + * + * Example (2) + * =========== + * pci: pci@ff { + * reg = <0xff 0x1>; + * device_type = "pci"; + * + * // The sideband data provided to the MSI controller is + * // the RID, masked to only the device and function bits. + * msi-map = <0x0 &msi_a 0x0 0x100>; + * msi-map-mask = <0xff> + * }; + * + * Example (3) + * =========== + * pci: pci@fff { + * reg = <0xfff 0x1>; + * device_type = "pci"; + * + * // The sideband data provided to the MSI controller is + * // the RID, but the high bit of the bus number is ignored. + * msi-map = <0x0000 &msi_a 0x0000 0x8000>, + * <0x8000 &msi_a 0x0000 0x8000>; + * }; + * + * Example (4) + * =========== + * pci: pci@f { + * reg = <0xf 0x1>; + * device_type = "pci"; + * + * // The sideband data provided to the MSI controller is + * // the RID, but the high bit of the bus number is negated. + * msi-map = <0x0000 &msi 0x8000 0x8000>, + * <0x8000 &msi 0x0000 0x8000>; + * }; + * + * Example (5) + * =========== + * pci: pci@f { + * reg = <0xf 0x1>; + * device_type = "pci"; + * + * // The sideband data provided to MSI controller a is the + * // RID, but the high bit of the bus number is negated. + * // The sideband data provided to MSI controller b is the + * // RID, identity-mapped. + * // MSI controller c is not addressable. + * msi-map = <0x0000 &msi_a 0x8000 0x08000>, + * <0x8000 &msi_a 0x0000 0x08000>, + * <0x0000 &msi_b 0x0000 0x10000>; + * }; + * }; + */ +static void ofw_msi_pic_init(struct rt_pci_device *pdev) +{ +#ifdef RT_PCI_MSI + rt_uint32_t rid; + struct rt_pci_host_bridge *bridge; + struct rt_ofw_node *np, *msi_ic_np = RT_NULL; + + /* + * NOTE: Typically, a device's RID is equal to the PCI device's ID. + * However, in complex bus management scenarios such as servers and PCs, + * the RID needs to be associated with DMA. In these cases, + * the RID should be equal to the DMA alias assigned to the + * PCI device by the system bus. + */ + rid = rt_pci_dev_id(pdev); + + bridge = rt_pci_find_host_bridge(pdev->bus); + RT_ASSERT(bridge != RT_NULL); + + np = bridge->parent.ofw_node; + + if (!(msi_ic_np = rt_ofw_parse_phandle(np, "msi-parent", 0))) + { + rt_ofw_map_id(np, rid, "msi-map", "msi-map-mask", &msi_ic_np, RT_NULL); + } + + if (!msi_ic_np) + { + LOG_W("%s: MSI PIC not found", rt_dm_dev_get_name(&pdev->parent)); + + return; + } + + pdev->msi_pic = rt_pic_dynamic_cast(rt_ofw_data(msi_ic_np)); + + if (!pdev->msi_pic) + { + LOG_W("%s: '%s' not supported", rt_dm_dev_get_name(&pdev->parent), "msi-parent"); + + goto _out_put_msi_parent_node; + } + + if (!pdev->msi_pic->ops->irq_compose_msi_msg) + { + LOG_E("%s: MSI pic MUST implemented %s", + rt_ofw_node_full_name(msi_ic_np), "irq_compose_msi_msg"); + RT_ASSERT(0); + } + + if (!pdev->msi_pic->ops->irq_alloc_msi) + { + LOG_E("%s: MSI pic MUST implemented %s", + rt_ofw_node_full_name(msi_ic_np), "irq_alloc_msi"); + RT_ASSERT(0); + } + + if (!pdev->msi_pic->ops->irq_free_msi) + { + LOG_E("%s: MSI pic MUST implemented %s", + rt_ofw_node_full_name(msi_ic_np), "irq_free_msi"); + RT_ASSERT(0); + } + +_out_put_msi_parent_node: + rt_ofw_node_put(msi_ic_np); +#endif +} + +static rt_int32_t ofw_pci_devfn(struct rt_ofw_node *np) +{ + rt_int32_t res; + rt_uint32_t reg[5]; + + res = rt_ofw_prop_read_u32_array_index(np, "reg", 0, RT_ARRAY_SIZE(reg), reg); + + return res > 0 ? ((reg[0] >> 8) & 0xff) : res; +} + +static struct rt_ofw_node *ofw_find_device(struct rt_ofw_node *np, rt_uint32_t devfn) +{ + struct rt_ofw_node *dev_np, *mfd_np; + + rt_ofw_foreach_child_node(np, dev_np) + { + if (ofw_pci_devfn(dev_np) == devfn) + { + return dev_np; + } + + if (rt_ofw_node_tag_equ(dev_np, "multifunc-device")) + { + rt_ofw_foreach_child_node(dev_np, mfd_np) + { + if (ofw_pci_devfn(mfd_np) == devfn) + { + rt_ofw_node_put(dev_np); + + return mfd_np; + } + } + } + } + + return RT_NULL; +} + +rt_err_t rt_pci_ofw_device_init(struct rt_pci_device *pdev) +{ + struct rt_ofw_node *np = RT_NULL; + + if (!pdev) + { + return -RT_EINVAL; + } + + ofw_msi_pic_init(pdev); + + if (rt_pci_is_root_bus(pdev->bus) || !pdev->bus->self) + { + struct rt_pci_host_bridge *host_bridge; + + host_bridge = rt_pci_find_host_bridge(pdev->bus); + RT_ASSERT(host_bridge != RT_NULL); + + np = host_bridge->parent.ofw_node; + } + else + { + np = pdev->bus->self->parent.ofw_node; + } + + if (np) + { + pdev->parent.ofw_node = ofw_find_device(np, pdev->devfn); + } + + return RT_EOK; +} + +rt_err_t rt_pci_ofw_device_free(struct rt_pci_device *pdev) +{ + if (!pdev) + { + return -RT_EINVAL; + } + + rt_ofw_node_put(pdev->parent.ofw_node); + + return RT_EOK; +} diff --git a/rt-thread/components/drivers/pci/pci.c b/rt-thread/components/drivers/pci/pci.c new file mode 100644 index 0000000..369856e --- /dev/null +++ b/rt-thread/components/drivers/pci/pci.c @@ -0,0 +1,1018 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#include +#include + +#define DBG_TAG "rtdm.pci" +#define DBG_LVL DBG_INFO +#include + +#include +#include +#include + +rt_inline void spin_lock(struct rt_spinlock *spinlock) +{ + rt_hw_spin_lock(&spinlock->lock); +} + +rt_inline void spin_unlock(struct rt_spinlock *spinlock) +{ + rt_hw_spin_unlock(&spinlock->lock); +} + +rt_uint32_t rt_pci_domain(struct rt_pci_device *pdev) +{ + struct rt_pci_host_bridge *host_bridge; + + if (!pdev) + { + return RT_UINT32_MAX; + } + + if ((host_bridge = rt_pci_find_host_bridge(pdev->bus))) + { + return host_bridge->domain; + } + + return RT_UINT32_MAX; +} + +static rt_uint8_t pci_find_next_cap_ttl(struct rt_pci_bus *bus, + rt_uint32_t devfn, rt_uint8_t pos, int cap, int *ttl) +{ + rt_uint8_t ret = 0, id; + rt_uint16_t ent; + + rt_pci_bus_read_config_u8(bus, devfn, pos, &pos); + + while ((*ttl)--) + { + if (pos < 0x40) + { + break; + } + + pos &= ~3; + rt_pci_bus_read_config_u16(bus, devfn, pos, &ent); + + id = ent & 0xff; + if (id == 0xff) + { + break; + } + if (id == cap) + { + ret = pos; + break; + } + pos = (ent >> 8); + } + + return ret; +} + +static rt_uint8_t pci_find_next_cap(struct rt_pci_bus *bus, + rt_uint32_t devfn, rt_uint8_t pos, int cap) +{ + int ttl = RT_PCI_FIND_CAP_TTL; + + return pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); +} + +static rt_uint8_t pci_bus_find_cap_start(struct rt_pci_bus *bus, + rt_uint32_t devfn, rt_uint8_t hdr_type) +{ + rt_uint8_t res = 0; + rt_uint16_t status; + + rt_pci_bus_read_config_u16(bus, devfn, PCIR_STATUS, &status); + + if (status & PCIM_STATUS_CAPPRESENT) + { + switch (hdr_type) + { + case PCIM_HDRTYPE_NORMAL: + case PCIM_HDRTYPE_BRIDGE: + res = PCIR_CAP_PTR; + break; + + case PCIM_HDRTYPE_CARDBUS: + res = PCIR_CAP_PTR_2; + break; + } + } + + return res; +} + +rt_uint8_t rt_pci_bus_find_capability(struct rt_pci_bus *bus, rt_uint32_t devfn, int cap) +{ + rt_uint8_t hdr_type, ret = RT_UINT8_MAX; + + if (bus) + { + rt_pci_bus_read_config_u8(bus, devfn, PCIR_HDRTYPE, &hdr_type); + + ret = pci_bus_find_cap_start(bus, devfn, hdr_type & PCIM_HDRTYPE); + + if (ret) + { + ret = pci_find_next_cap(bus, devfn, ret, cap); + } + } + + return ret; +} + +rt_uint8_t rt_pci_find_capability(struct rt_pci_device *pdev, int cap) +{ + rt_uint8_t res = RT_UINT8_MAX; + + if (pdev) + { + res = pci_bus_find_cap_start(pdev->bus, pdev->devfn, pdev->hdr_type); + + if (res) + { + res = pci_find_next_cap(pdev->bus, pdev->devfn, res, cap); + } + } + + return res; +} + +rt_uint8_t rt_pci_find_next_capability(struct rt_pci_device *pdev, rt_uint8_t pos, int cap) +{ + rt_uint8_t res = RT_UINT8_MAX; + + if (pdev) + { + res = pci_find_next_cap(pdev->bus, pdev->devfn, pos + PCICAP_NEXTPTR, cap); + } + + return res; +} + +rt_uint16_t rt_pci_find_ext_capability(struct rt_pci_device *pdev, int cap) +{ + return rt_pci_find_ext_next_capability(pdev, 0, cap); +} + +rt_uint16_t rt_pci_find_ext_next_capability(struct rt_pci_device *pdev, rt_uint16_t pos, int cap) +{ + int ttl; + rt_uint32_t header; + rt_uint16_t start = pos; + + /* minimum 8 bytes per capability */ + ttl = ((PCIE_REGMAX + 1) - (PCI_REGMAX + 1)) / 8; + + if (pdev->cfg_size <= PCI_REGMAX + 1) + { + return 0; + } + + if (!pos) + { + pos = PCI_REGMAX + 1; + } + + if (rt_pci_read_config_u32(pdev, pos, &header)) + { + return 0; + } + + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + { + return 0; + } + + while (ttl-- > 0) + { + if (PCI_EXTCAP_ID(header) == cap && pos != start) + { + return pos; + } + + pos = PCI_EXTCAP_NEXTPTR(header); + + if (pos < PCI_REGMAX + 1) + { + break; + } + + if (rt_pci_read_config_u32(pdev, pos, &header)) + { + break; + } + } + + return 0; +} + +static void pci_set_master(struct rt_pci_device *pdev, rt_bool_t enable) +{ + rt_uint16_t old_cmd, cmd; + + rt_pci_read_config_u16(pdev, PCIR_COMMAND, &old_cmd); + + if (enable) + { + cmd = old_cmd | PCIM_CMD_BUSMASTEREN; + } + else + { + cmd = old_cmd & ~PCIM_CMD_BUSMASTEREN; + } + + if (cmd != old_cmd) + { + rt_pci_write_config_u16(pdev, PCIR_COMMAND, cmd); + } + + pdev->busmaster = !!enable; +} + +void rt_pci_set_master(struct rt_pci_device *pdev) +{ + if (pdev) + { + pci_set_master(pdev, RT_TRUE); + } +} + +void rt_pci_clear_master(struct rt_pci_device *pdev) +{ + if (pdev) + { + pci_set_master(pdev, RT_FALSE); + } +} + +void rt_pci_intx(struct rt_pci_device *pdev, rt_bool_t enable) +{ + rt_uint16_t pci_command, new; + + if (!pdev) + { + return; + } + + rt_pci_read_config_u16(pdev, PCIR_COMMAND, &pci_command); + + if (enable) + { + new = pci_command & ~PCIM_CMD_INTxDIS; + } + else + { + new = pci_command | PCIM_CMD_INTxDIS; + } + + if (new != pci_command) + { + rt_pci_write_config_u16(pdev, PCIR_COMMAND, new); + } +} + +static rt_bool_t pci_check_and_set_intx_mask(struct rt_pci_device *pdev, rt_bool_t mask) +{ + rt_ubase_t level; + rt_bool_t irq_pending; + rt_bool_t res = RT_TRUE; + rt_uint16_t origcmd, newcmd; + rt_uint32_t cmd_status_dword; + struct rt_pci_bus *bus = pdev->bus; + + level = rt_spin_lock_irqsave(&rt_pci_lock); + + bus->ops->read(bus, pdev->devfn, PCIR_COMMAND, 4, &cmd_status_dword); + + irq_pending = (cmd_status_dword >> 16) & PCIM_STATUS_INTxSTATE; + + /* + * Check interrupt status register to see whether our device + * triggered the interrupt (when masking) or the next IRQ is + * already pending (when unmasking). + */ + if (mask != irq_pending) + { + res = RT_FALSE; + } + else + { + origcmd = cmd_status_dword; + newcmd = origcmd & ~PCIM_CMD_INTxDIS; + + if (mask) + { + newcmd |= PCIM_CMD_INTxDIS; + } + if (newcmd != origcmd) + { + bus->ops->write(bus, pdev->devfn, PCIR_COMMAND, 2, newcmd); + } + } + + rt_spin_unlock_irqrestore(&rt_pci_lock, level); + + return res; +} + +rt_bool_t rt_pci_check_and_mask_intx(struct rt_pci_device *pdev) +{ + rt_bool_t res = RT_FALSE; + + if (pdev) + { + res = pci_check_and_set_intx_mask(pdev, RT_TRUE); + } + + return res; +} + +rt_bool_t rt_pci_check_and_unmask_intx(struct rt_pci_device *pdev) +{ + rt_bool_t res = RT_FALSE; + + if (pdev) + { + res = pci_check_and_set_intx_mask(pdev, RT_FALSE); + } + + return res; +} + +void rt_pci_irq_mask(struct rt_pci_device *pdev) +{ + if (pdev) + { + rt_bool_t unused; + struct rt_pic_irq *pirq; + + rt_pci_intx(pdev, RT_FALSE); + + pirq = rt_pic_find_pirq(pdev->intx_pic, pdev->irq); + RT_ASSERT(pirq != RT_NULL); + + rt_hw_spin_lock(&pirq->rw_lock.lock); + unused = rt_list_isempty(&pirq->isr.list); + rt_hw_spin_unlock(&pirq->rw_lock.lock); + + if (unused) + { + rt_hw_interrupt_mask(pdev->irq); + } + } +} + +void rt_pci_irq_unmask(struct rt_pci_device *pdev) +{ + if (pdev) + { + rt_hw_interrupt_umask(pdev->irq); + rt_pci_intx(pdev, RT_TRUE); + } +} + +struct rt_pci_bus *rt_pci_find_root_bus(struct rt_pci_bus *bus) +{ + if (!bus) + { + return RT_NULL; + } + + while (bus->parent) + { + bus = bus->parent; + } + + return bus; +} + +struct rt_pci_host_bridge *rt_pci_find_host_bridge(struct rt_pci_bus *bus) +{ + if (!bus) + { + return RT_NULL; + } + + if ((bus = rt_pci_find_root_bus(bus))) + { + return rt_container_of(bus->host_bridge, struct rt_pci_host_bridge, parent); + } + + return RT_NULL; +} + +rt_uint8_t rt_pci_irq_intx(struct rt_pci_device *pdev, rt_uint8_t pin) +{ + int slot = 0; + + if (!pdev->ari_enabled) + { + slot = RT_PCI_SLOT(pdev->devfn); + } + + return (((pin - 1) + slot) % 4) + 1; +} + +rt_uint8_t rt_pci_irq_slot(struct rt_pci_device *pdev, rt_uint8_t *pinp) +{ + rt_uint8_t pin = *pinp; + + while (!rt_pci_is_root_bus(pdev->bus)) + { + pin = rt_pci_irq_intx(pdev, pin); + pdev = pdev->bus->self; + } + + *pinp = pin; + + return RT_PCI_SLOT(pdev->devfn); +} + +rt_err_t rt_pci_region_setup(struct rt_pci_host_bridge *host_bridge) +{ + rt_err_t err = host_bridge->bus_regions_nr == 0 ? -RT_EEMPTY : RT_EOK; + + for (int i = 0; i < host_bridge->bus_regions_nr; ++i) + { + struct rt_pci_bus_region *region = &host_bridge->bus_regions[i]; + /* + * Avoid allocating PCI resources from address 0 -- this is illegal + * according to PCI 2.1 and moreover. Use a reasonable starting value of + * 0x1000 instead if the bus start address is below 0x1000. + */ + region->bus_start = rt_max_t(rt_size_t, 0x1000, region->phy_addr); + + LOG_I("Bus %s region(%d):", + region->flags == PCI_BUS_REGION_F_MEM ? "Memory" : + (region->flags == PCI_BUS_REGION_F_PREFETCH ? "Prefetchable Mem" : + (region->flags == PCI_BUS_REGION_F_IO ? "I/O" : "Unknown")), i); + LOG_I(" cpu: [%p, %p]", region->cpu_addr, (region->cpu_addr + region->size - 1)); + LOG_I(" physical: [%p, %p]", region->phy_addr, (region->phy_addr + region->size - 1)); + } + + return err; +} + +struct rt_pci_bus_region *rt_pci_region_alloc(struct rt_pci_host_bridge *host_bridge, + void **out_addr, rt_size_t size, rt_ubase_t flags, rt_bool_t mem64) +{ + struct rt_pci_bus_region *bus_region, *region = RT_NULL; + + bus_region = &host_bridge->bus_regions[0]; + + for (int i = 0; i < host_bridge->bus_regions_nr; ++i, ++bus_region) + { + if (bus_region->flags == flags && bus_region->size > 0) + { + void *addr; + + region = bus_region; + addr = (void *)(((region->bus_start - 1) | (size - 1)) + 1); + + if ((rt_uint64_t)addr - region->phy_addr + size <= region->size) + { + rt_bool_t addr64 = !!rt_upper_32_bits((rt_ubase_t)addr); + + if (mem64) + { + if (!addr64) + { + region = RT_NULL; + + /* Try again */ + continue; + } + } + else if (addr64) + { + region = RT_NULL; + + /* Try again */ + continue; + } + + region->bus_start = ((rt_uint64_t)addr + size); + *out_addr = addr; + } + + break; + } + } + + if (!region && mem64) + { + /* Retry */ + region = rt_pci_region_alloc(host_bridge, out_addr, size, flags, RT_FALSE); + } + + return region; +} + +rt_err_t rt_pci_device_alloc_resource(struct rt_pci_host_bridge *host_bridge, + struct rt_pci_device *pdev) +{ + rt_err_t err = RT_EOK; + rt_size_t size; + rt_ubase_t addr = 0; + rt_uint32_t cfg; + rt_size_t bars_nr; + rt_uint8_t hdr_type; + rt_bool_t prefetch = RT_FALSE; + rt_uint16_t class, command = 0; + + for (int i = 0; i < host_bridge->bus_regions_nr; ++i) + { + if (host_bridge->bus_regions[i].flags == PCI_BUS_REGION_F_PREFETCH) + { + prefetch = RT_TRUE; + break; + } + } + + rt_pci_read_config_u16(pdev, PCIR_COMMAND, &command); + command = (command & ~(PCIM_CMD_PORTEN | PCIM_CMD_MEMEN)) | PCIM_CMD_BUSMASTEREN; + rt_pci_read_config_u8(pdev, PCIR_HDRTYPE, &hdr_type); + + if (pdev->hdr_type != hdr_type) + { + LOG_W("%s may not initialized", rt_dm_dev_get_name(&pdev->parent)); + } + + switch (hdr_type) + { + case PCIM_HDRTYPE_NORMAL: + bars_nr = PCI_STD_NUM_BARS; + break; + + case PCIM_HDRTYPE_BRIDGE: + bars_nr = 2; + break; + + case PCIM_HDRTYPE_CARDBUS: + bars_nr = 0; + break; + + default: + bars_nr = 0; + break; + } + + for (int i = 0; i < bars_nr; ++i) + { + rt_ubase_t flags; + rt_ubase_t bar_base; + rt_bool_t mem64 = RT_FALSE; + struct rt_pci_bus_region *region; + + cfg = 0; + bar_base = PCIR_BAR(i); + + rt_pci_write_config_u32(pdev, bar_base, RT_UINT32_MAX); + rt_pci_read_config_u32(pdev, bar_base, &cfg); + + if (!cfg) + { + continue; + } + else if (cfg == RT_UINT32_MAX) + { + rt_pci_write_config_u32(pdev, bar_base, 0UL); + continue; + } + + if (cfg & PCIM_BAR_SPACE) + { + mem64 = RT_FALSE; + flags = PCI_BUS_REGION_F_IO; + + size = cfg & PCIM_BAR_IO_MASK; + size &= ~(size - 1); + } + else + { + /* memory */ + if ((cfg & PCIM_BAR_MEM_TYPE_MASK) == PCIM_BAR_MEM_TYPE_64) + { + /* 64bits */ + rt_uint32_t cfg64; + rt_uint64_t bar64; + + mem64 = RT_TRUE; + + rt_pci_write_config_u32(pdev, bar_base + sizeof(rt_uint32_t), RT_UINT32_MAX); + rt_pci_read_config_u32(pdev, bar_base + sizeof(rt_uint32_t), &cfg64); + + bar64 = ((rt_uint64_t)cfg64 << 32) | cfg; + + size = ~(bar64 & PCIM_BAR_MEM_MASK) + 1; + } + else + { + /* 32bits */ + mem64 = RT_FALSE; + size = (rt_uint32_t)(~(cfg & PCIM_BAR_MEM_MASK) + 1); + } + + if (prefetch && (cfg & PCIM_BAR_MEM_PREFETCH)) + { + flags = PCI_BUS_REGION_F_PREFETCH; + } + else + { + flags = PCI_BUS_REGION_F_MEM; + } + } + + region = rt_pci_region_alloc(host_bridge, (void **)&addr, size, flags, mem64); + + if (region) + { + rt_pci_write_config_u32(pdev, bar_base, addr); + + if (mem64) + { + bar_base += sizeof(rt_uint32_t); + #ifdef RT_PCI_SYS_64BIT + rt_pci_write_config_u32(pdev, bar_base, (rt_uint32_t)(addr >> 32)); + #else + /* + * If we are a 64-bit decoder then increment to the upper 32 bits + * of the bar and force it to locate in the lower 4GB of memory. + */ + rt_pci_write_config_u32(pdev, bar_base, 0UL); + #endif + } + + pdev->resource[i].size = size; + pdev->resource[i].base = region->cpu_addr + (addr - region->phy_addr); + pdev->resource[i].flags = flags; + + if (mem64) + { + ++i; + pdev->resource[i].flags = PCI_BUS_REGION_F_NONE; + } + } + else + { + err = -RT_ERROR; + LOG_W("%s alloc bar(%d) address fail", rt_dm_dev_get_name(&pdev->parent), i); + } + + command |= (cfg & PCIM_BAR_SPACE) ? PCIM_CMD_PORTEN : PCIM_CMD_MEMEN; + } + + if (hdr_type == PCIM_HDRTYPE_NORMAL || hdr_type == PCIM_HDRTYPE_BRIDGE) + { + int rom_addr = (hdr_type == PCIM_HDRTYPE_NORMAL) ? PCIR_BIOS : PCIR_BIOS_1; + + rt_pci_write_config_u32(pdev, rom_addr, 0xfffffffe); + rt_pci_read_config_u32(pdev, rom_addr, &cfg); + + if (cfg) + { + size = -(cfg & ~1); + + if (rt_pci_region_alloc(host_bridge, (void **)&addr, size, PCI_BUS_REGION_F_MEM, RT_FALSE)) + { + rt_pci_write_config_u32(pdev, rom_addr, addr); + } + command |= PCIM_CMD_MEMEN; + } + } + + rt_pci_read_config_u16(pdev, PCIR_SUBCLASS, &class); + + if (class == PCIS_DISPLAY_VGA) + { + command |= PCIM_CMD_PORTEN; + } + + rt_pci_write_config_u16(pdev, PCIR_COMMAND, command); + rt_pci_write_config_u8(pdev, PCIR_CACHELNSZ, RT_PCI_CACHE_LINE_SIZE); + rt_pci_write_config_u8(pdev, PCIR_LATTIMER, 0x80); + + return err; +} + +struct rt_pci_bus_resource *rt_pci_find_bar(struct rt_pci_device* pdev,rt_ubase_t flags,int index) +{ + for (int i = 0; i < RT_PCI_BAR_NR_MAX; i++) + { + if (pdev->resource[i].flags == flags) + { + index--; + if (index == 0) + return &pdev->resource[i]; + } + } + return RT_NULL; +} + +void rt_pci_enum_device(struct rt_pci_bus *bus, + rt_bool_t (callback(struct rt_pci_device *, void *)), void *data) +{ + rt_bool_t is_end = RT_FALSE; + struct rt_spinlock *lock; + struct rt_pci_bus *parent; + struct rt_pci_device *pdev, *last_pdev = RT_NULL; + + /* Walk tree */ + while (bus && !is_end) + { + /* Goto bottom */ + for (;;) + { + lock = &bus->lock; + + spin_lock(lock); + if (rt_list_isempty(&bus->children_nodes)) + { + parent = bus->parent; + break; + } + bus = rt_list_entry(&bus->children_nodes, struct rt_pci_bus, list); + spin_unlock(lock); + } + + rt_list_for_each_entry(pdev, &bus->devices_nodes, list) + { + if (last_pdev) + { + spin_unlock(lock); + + if (callback(last_pdev, data)) + { + spin_lock(lock); + --last_pdev->parent.ref_count; + + is_end = RT_TRUE; + break; + } + + spin_lock(lock); + --last_pdev->parent.ref_count; + } + ++pdev->parent.ref_count; + last_pdev = pdev; + } + + if (!is_end && last_pdev) + { + spin_unlock(lock); + + if (callback(last_pdev, data)) + { + is_end = RT_TRUE; + } + + spin_lock(lock); + --last_pdev->parent.ref_count; + } + last_pdev = RT_NULL; + spin_unlock(lock); + + /* Up a level or goto next */ + while (!is_end) + { + lock = &bus->lock; + + if (!parent) + { + /* Root bus, is end */ + bus = RT_NULL; + break; + } + + spin_lock(lock); + if (bus->list.next != &parent->children_nodes) + { + /* Has next sibling */ + bus = rt_list_entry(bus->list.next, struct rt_pci_bus, list); + spin_unlock(lock); + break; + } + + /* All device on this buss' parent */ + rt_list_for_each_entry(pdev, &parent->devices_nodes, list) + { + if (last_pdev) + { + spin_unlock(lock); + + if (callback(last_pdev, data)) + { + spin_lock(lock); + --last_pdev->parent.ref_count; + + is_end = RT_TRUE; + break; + } + + spin_lock(lock); + --last_pdev->parent.ref_count; + } + ++pdev->parent.ref_count; + last_pdev = pdev; + } + + if (!is_end && last_pdev) + { + spin_unlock(lock); + + if (callback(last_pdev, data)) + { + is_end = RT_TRUE; + } + + spin_lock(lock); + --last_pdev->parent.ref_count; + } + last_pdev = RT_NULL; + + bus = parent; + parent = parent->parent; + spin_unlock(lock); + } + } +} + +const struct rt_pci_device_id *rt_pci_match_id(struct rt_pci_device *pdev, + const struct rt_pci_device_id *id) +{ + if ((id->vendor == PCI_ANY_ID || id->vendor == pdev->vendor) && + (id->device == PCI_ANY_ID || id->device == pdev->device) && + (id->subsystem_vendor == PCI_ANY_ID || id->subsystem_vendor == pdev->subsystem_vendor) && + (id->subsystem_device == PCI_ANY_ID || id->subsystem_device == pdev->subsystem_device) && + !((id->class ^ pdev->class) & id->class_mask)) + { + return id; + } + + return RT_NULL; +} + +const struct rt_pci_device_id *rt_pci_match_ids(struct rt_pci_device *pdev, + const struct rt_pci_device_id *ids) +{ + while (ids->vendor || ids->subsystem_vendor || ids->class_mask) + { + if (rt_pci_match_id(pdev, ids)) + { + return ids; + } + + ++ids; + } + + return RT_NULL; +} + +static struct rt_bus pci_bus; + +rt_err_t rt_pci_driver_register(struct rt_pci_driver *pdrv) +{ + RT_ASSERT(pdrv != RT_NULL); + + pdrv->parent.bus = &pci_bus; +#if RT_NAME_MAX > 0 + rt_strcpy(pdrv->parent.parent.name, pdrv->name); +#else + pdrv->parent.parent.name = pdrv->name; +#endif + + return rt_driver_register(&pdrv->parent); +} + +rt_err_t rt_pci_device_register(struct rt_pci_device *pdev) +{ + rt_err_t err; + RT_ASSERT(pdev != RT_NULL); + + if ((err = rt_bus_add_device(&pci_bus, &pdev->parent))) + { + return err; + } + + return RT_EOK; +} + +static rt_bool_t pci_match(rt_driver_t drv, rt_device_t dev) +{ + rt_bool_t match = RT_FALSE; + struct rt_pci_driver *pdrv = rt_container_of(drv, struct rt_pci_driver, parent); + struct rt_pci_device *pdev = rt_container_of(dev, struct rt_pci_device, parent); + + if (pdrv->name && pdev->name) + { + match = rt_strcmp(pdrv->name, pdev->name) ? RT_FALSE : RT_TRUE; + } + + if (!match) + { + pdev->id = rt_pci_match_ids(pdev, pdrv->ids); + + match = pdev->id ? RT_TRUE : RT_FALSE; + } + + return match; +} + +static rt_err_t pci_probe(rt_device_t dev) +{ + rt_err_t err = RT_EOK; + struct rt_pci_driver *pdrv = rt_container_of(dev->drv, struct rt_pci_driver, parent); + struct rt_pci_device *pdev = rt_container_of(dev, struct rt_pci_device, parent); + + rt_pci_assign_irq(pdev); + rt_pci_enable_wake(pdev, RT_PCI_D0, RT_TRUE); + + err = pdrv->probe(pdev); + + if (err) + { + rt_pci_enable_wake(pdev, RT_PCI_D0, RT_FALSE); + } + + return err; +} + +static rt_err_t pci_remove(rt_device_t dev) +{ + rt_err_t err = RT_EOK; + struct rt_pci_bus *bus; + struct rt_pci_driver *pdrv = rt_container_of(dev->drv, struct rt_pci_driver, parent); + struct rt_pci_device *pdev = rt_container_of(dev, struct rt_pci_device, parent); + + if (pdrv && pdrv->remove) + { + if ((err = pdrv->remove(pdev))) + { + return err; + } + } + + rt_pci_enable_wake(pdev, RT_PCI_D0, RT_FALSE); + + bus = pdev->bus; + rt_pci_device_remove(pdev); + /* Just try to remove */ + rt_pci_bus_remove(bus); + + return err; +} + +static rt_err_t pci_shutdown(rt_device_t dev) +{ + struct rt_pci_bus *bus; + struct rt_pci_driver *pdrv = rt_container_of(dev->drv, struct rt_pci_driver, parent); + struct rt_pci_device *pdev = rt_container_of(dev, struct rt_pci_device, parent); + + if (pdrv && pdrv->shutdown) + { + pdrv->shutdown(pdev); + } + + rt_pci_enable_wake(pdev, RT_PCI_D0, RT_FALSE); + + bus = pdev->bus; + rt_pci_device_remove(pdev); + /* Just try to remove */ + rt_pci_bus_remove(bus); + + return RT_EOK; +} + +static struct rt_bus pci_bus = +{ + .name = "pci", + .match = pci_match, + .probe = pci_probe, + .remove = pci_remove, + .shutdown = pci_shutdown, +}; + +static int pci_bus_init(void) +{ + rt_bus_register(&pci_bus); + + return 0; +} +INIT_CORE_EXPORT(pci_bus_init); diff --git a/rt-thread/components/drivers/pci/pci_ids.h b/rt-thread/components/drivers/pci/pci_ids.h new file mode 100644 index 0000000..2dab735 --- /dev/null +++ b/rt-thread/components/drivers/pci/pci_ids.h @@ -0,0 +1,272 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __PCI_IDS_H__ +#define __PCI_IDS_H__ + +#define PCI_VENDOR_ID_LOONGSON 0x0014 +#define PCI_VENDOR_ID_TTTECH 0x0357 +#define PCI_VENDOR_ID_DYNALINK 0x0675 +#define PCI_VENDOR_ID_UBIQUITI 0x0777 +#define PCI_VENDOR_ID_BERKOM 0x0871 +#define PCI_VENDOR_ID_COMPAQ 0x0e11 +#define PCI_VENDOR_ID_NCR 0x1000 +#define PCI_VENDOR_ID_ATI 0x1002 +#define PCI_VENDOR_ID_VLSI 0x1004 +#define PCI_VENDOR_ID_ADL 0x1005 +#define PCI_VENDOR_ID_NS 0x100b +#define PCI_VENDOR_ID_TSENG 0x100c +#define PCI_VENDOR_ID_WEITEK 0x100e +#define PCI_VENDOR_ID_DEC 0x1011 +#define PCI_VENDOR_ID_CIRRUS 0x1013 +#define PCI_VENDOR_ID_IBM 0x1014 +#define PCI_VENDOR_ID_UNISYS 0x1018 +#define PCI_VENDOR_ID_COMPEX2 0x101a +#define PCI_VENDOR_ID_WD 0x101c +#define PCI_VENDOR_ID_AMI 0x101e +#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_VENDOR_ID_TRIDENT 0x1023 +#define PCI_VENDOR_ID_AI 0x1025 +#define PCI_VENDOR_ID_DELL 0x1028 +#define PCI_VENDOR_ID_MATROX 0x102b +#define PCI_VENDOR_ID_MOBILITY_ELECTRONICS 0x14f2 +#define PCI_VENDOR_ID_CT 0x102c +#define PCI_VENDOR_ID_MIRO 0x1031 +#define PCI_VENDOR_ID_NEC 0x1033 +#define PCI_VENDOR_ID_FD 0x1036 +#define PCI_VENDOR_ID_SI 0x1039 +#define PCI_VENDOR_ID_HP 0x103c +#define PCI_VENDOR_ID_PCTECH 0x1042 +#define PCI_VENDOR_ID_ASUSTEK 0x1043 +#define PCI_VENDOR_ID_DPT 0x1044 +#define PCI_VENDOR_ID_OPTI 0x1045 +#define PCI_VENDOR_ID_ELSA 0x1048 +#define PCI_VENDOR_ID_STMICRO 0x104a +#define PCI_VENDOR_ID_BUSLOGIC 0x104b +#define PCI_VENDOR_ID_TI 0x104c +#define PCI_VENDOR_ID_SONY 0x104d +#define PCI_VENDOR_ID_ANIGMA 0x1051 +#define PCI_VENDOR_ID_EFAR 0x1055 +#define PCI_VENDOR_ID_MOTOROLA 0x1057 +#define PCI_VENDOR_ID_PROMISE 0x105a +#define PCI_VENDOR_ID_FOXCONN 0x105b +#define PCI_VENDOR_ID_UMC 0x1060 +#define PCI_VENDOR_ID_PICOPOWER 0x1066 +#define PCI_VENDOR_ID_MYLEX 0x1069 +#define PCI_VENDOR_ID_APPLE 0x106b +#define PCI_VENDOR_ID_YAMAHA 0x1073 +#define PCI_VENDOR_ID_QLOGIC 0x1077 +#define PCI_VENDOR_ID_CYRIX 0x1078 +#define PCI_VENDOR_ID_CONTAQ 0x1080 +#define PCI_VENDOR_ID_OLICOM 0x108d +#define PCI_VENDOR_ID_SUN 0x108e +#define PCI_VENDOR_ID_NI 0x1093 +#define PCI_VENDOR_ID_CMD 0x1095 +#define PCI_VENDOR_ID_BROOKTREE 0x109e +#define PCI_VENDOR_ID_SGI 0x10a9 +#define PCI_VENDOR_ID_WINBOND 0x10ad +#define PCI_VENDOR_ID_PLX 0x10b5 +#define PCI_VENDOR_ID_MADGE 0x10b6 +#define PCI_VENDOR_ID_3COM 0x10b7 +#define PCI_VENDOR_ID_AL 0x10b9 +#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 +#define PCI_VENDOR_ID_TCONRAD 0x10da +#define PCI_VENDOR_ID_ROHM 0x10db +#define PCI_VENDOR_ID_NVIDIA 0x10de +#define PCI_VENDOR_ID_IMS 0x10e0 +#define PCI_VENDOR_ID_AMCC 0x10e8 +#define PCI_VENDOR_ID_INTERG 0x10ea +#define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_VENDOR_ID_XILINX 0x10ee +#define PCI_VENDOR_ID_INIT 0x1101 +#define PCI_VENDOR_ID_CREATIVE 0x1102 +#define PCI_VENDOR_ID_ECTIVA PCI_VENDOR_ID_CREATIVE +#define PCI_VENDOR_ID_TTI 0x1103 +#define PCI_VENDOR_ID_SIGMA 0x1105 +#define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_VENDOR_ID_SIEMENS 0x110a +#define PCI_VENDOR_ID_VORTEX 0x1119 +#define PCI_VENDOR_ID_EF 0x111a +#define PCI_VENDOR_ID_IDT 0x111d +#define PCI_VENDOR_ID_FORE 0x1127 +#define PCI_VENDOR_ID_PHILIPS 0x1131 +#define PCI_VENDOR_ID_EICON 0x1133 +#define PCI_VENDOR_ID_CISCO 0x1137 +#define PCI_VENDOR_ID_ZIATECH 0x1138 +#define PCI_VENDOR_ID_SYSKONNECT 0x1148 +#define PCI_VENDOR_ID_DIGI 0x114f +#define PCI_VENDOR_ID_XIRCOM 0x115d +#define PCI_VENDOR_ID_SERVERWORKS 0x1166 +#define PCI_VENDOR_ID_ALTERA 0x1172 +#define PCI_VENDOR_ID_SBE 0x1176 +#define PCI_VENDOR_ID_TOSHIBA 0x1179 +#define PCI_VENDOR_ID_TOSHIBA_2 0x102f +#define PCI_VENDOR_ID_ATTO 0x117c +#define PCI_VENDOR_ID_RICOH 0x1180 +#define PCI_VENDOR_ID_DLINK 0x1186 +#define PCI_VENDOR_ID_ARTOP 0x1191 +#define PCI_VENDOR_ID_ZEITNET 0x1193 +#define PCI_VENDOR_ID_FUJITSU_ME 0x119e +#define PCI_VENDOR_ID_MARVELL 0x11ab +#define PCI_VENDOR_ID_V3 0x11b0 +#define PCI_VENDOR_ID_ATT 0x11c1 +#define PCI_VENDOR_ID_SPECIALIX 0x11cb +#define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4 +#define PCI_VENDOR_ID_ZORAN 0x11de +#define PCI_VENDOR_ID_COMPEX 0x11f6 +#define PCI_VENDOR_ID_PMC_Sierra 0x11f8 +#define PCI_VENDOR_ID_RP 0x11fe +#define PCI_VENDOR_ID_CYCLADES 0x120e +#define PCI_VENDOR_ID_ESSENTIAL 0x120f +#define PCI_VENDOR_ID_O2 0x1217 +#define PCI_VENDOR_ID_3DFX 0x121a +#define PCI_VENDOR_ID_QEMU 0x1234 +#define PCI_VENDOR_ID_AVM 0x1244 +#define PCI_VENDOR_ID_STALLION 0x124d +#define PCI_VENDOR_ID_ESS 0x125d +#define PCI_VENDOR_ID_SATSAGEM 0x1267 +#define PCI_VENDOR_ID_ENSONIQ 0x1274 +#define PCI_VENDOR_ID_TRANSMETA 0x1279 +#define PCI_VENDOR_ID_ROCKWELL 0x127a +#define PCI_VENDOR_ID_ITE 0x1283 +#define PCI_VENDOR_ID_ALTEON 0x12ae +#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 +#define PCI_VENDOR_ID_PERICOM 0x12d8 +#define PCI_VENDOR_ID_AUREAL 0x12eb +#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8 +#define PCI_VENDOR_ID_ESDGMBH 0x12fe +#define PCI_VENDOR_ID_CB 0x1307 +#define PCI_VENDOR_ID_SIIG 0x131f +#define PCI_VENDOR_ID_RADISYS 0x1331 +#define PCI_VENDOR_ID_MICRO_MEMORY 0x1332 +#define PCI_VENDOR_ID_DOMEX 0x134a +#define PCI_VENDOR_ID_INTASHIELD 0x135a +#define PCI_VENDOR_ID_QUATECH 0x135c +#define PCI_VENDOR_ID_SEALEVEL 0x135e +#define PCI_VENDOR_ID_HYPERCOPE 0x1365 +#define PCI_VENDOR_ID_DIGIGRAM 0x1369 +#define PCI_VENDOR_ID_KAWASAKI 0x136b +#define PCI_VENDOR_ID_CNET 0x1371 +#define PCI_VENDOR_ID_LMC 0x1376 +#define PCI_VENDOR_ID_NETGEAR 0x1385 +#define PCI_VENDOR_ID_APPLICOM 0x1389 +#define PCI_VENDOR_ID_MOXA 0x1393 +#define PCI_VENDOR_ID_CCD 0x1397 +#define PCI_VENDOR_ID_EXAR 0x13a8 +#define PCI_VENDOR_ID_MICROGATE 0x13c0 +#define PCI_VENDOR_ID_3WARE 0x13c1 +#define PCI_VENDOR_ID_IOMEGA 0x13ca +#define PCI_VENDOR_ID_ABOCOM 0x13d1 +#define PCI_VENDOR_ID_SUNDANCE 0x13f0 +#define PCI_VENDOR_ID_CMEDIA 0x13f6 +#define PCI_VENDOR_ID_ADVANTECH 0x13fe +#define PCI_VENDOR_ID_MEILHAUS 0x1402 +#define PCI_VENDOR_ID_LAVA 0x1407 +#define PCI_VENDOR_ID_TIMEDIA 0x1409 +#define PCI_VENDOR_ID_ICE 0x1412 +#define PCI_VENDOR_ID_MICROSOFT 0x1414 +#define PCI_VENDOR_ID_OXSEMI 0x1415 +#define PCI_VENDOR_ID_CHELSIO 0x1425 +#define PCI_VENDOR_ID_ADLINK 0x144a +#define PCI_VENDOR_ID_SAMSUNG 0x144d +#define PCI_VENDOR_ID_GIGABYTE 0x1458 +#define PCI_VENDOR_ID_AMBIT 0x1468 +#define PCI_VENDOR_ID_MYRICOM 0x14c1 +#define PCI_VENDOR_ID_MEDIATEK 0x14c3 +#define PCI_VENDOR_ID_TITAN 0x14d2 +#define PCI_VENDOR_ID_PANACOM 0x14d4 +#define PCI_VENDOR_ID_SIPACKETS 0x14d9 +#define PCI_VENDOR_ID_AFAVLAB 0x14db +#define PCI_VENDOR_ID_AMPLICON 0x14dc +#define PCI_VENDOR_ID_BCM_GVC 0x14a4 +#define PCI_VENDOR_ID_TOPIC 0x151f +#define PCI_VENDOR_ID_MAINPINE 0x1522 +#define PCI_VENDOR_ID_SYBA 0x1592 +#define PCI_VENDOR_ID_MORETON 0x15aa +#define PCI_VENDOR_ID_VMWARE 0x15ad +#define PCI_VENDOR_ID_ZOLTRIX 0x15b0 +#define PCI_VENDOR_ID_MELLANOX 0x15b3 +#define PCI_VENDOR_ID_DFI 0x15bd +#define PCI_VENDOR_ID_QUICKNET 0x15e2 +#define PCI_VENDOR_ID_PDC 0x15e9 +#define PCI_VENDOR_ID_FARSITE 0x1619 +#define PCI_VENDOR_ID_ARIMA 0x161f +#define PCI_VENDOR_ID_BROCADE 0x1657 +#define PCI_VENDOR_ID_SIBYTE 0x166d +#define PCI_VENDOR_ID_ATHEROS 0x168c +#define PCI_VENDOR_ID_NETCELL 0x169c +#define PCI_VENDOR_ID_CENATEK 0x16ca +#define PCI_VENDOR_ID_SYNOPSYS 0x16c3 +#define PCI_VENDOR_ID_USR 0x16ec +#define PCI_VENDOR_ID_VITESSE 0x1725 +#define PCI_VENDOR_ID_LINKSYS 0x1737 +#define PCI_VENDOR_ID_ALTIMA 0x173b +#define PCI_VENDOR_ID_CAVIUM 0x177d +#define PCI_VENDOR_ID_TECHWELL 0x1797 +#define PCI_VENDOR_ID_BELKIN 0x1799 +#define PCI_VENDOR_ID_RDC 0x17f3 +#define PCI_VENDOR_ID_GLI 0x17a0 +#define PCI_VENDOR_ID_LENOVO 0x17aa +#define PCI_VENDOR_ID_QCOM 0x17cb +#define PCI_VENDOR_ID_CDNS 0x17cd +#define PCI_VENDOR_ID_ARECA 0x17d3 +#define PCI_VENDOR_ID_S2IO 0x17d5 +#define PCI_VENDOR_ID_SITECOM 0x182d +#define PCI_VENDOR_ID_TOPSPIN 0x1867 +#define PCI_VENDOR_ID_COMMTECH 0x18f7 +#define PCI_VENDOR_ID_SILAN 0x1904 +#define PCI_VENDOR_ID_RENESAS 0x1912 +#define PCI_VENDOR_ID_SOLARFLARE 0x1924 +#define PCI_VENDOR_ID_TDI 0x192e +#define PCI_VENDOR_ID_FREESCALE 0x1957 +#define PCI_VENDOR_ID_NXP PCI_VENDOR_ID_FREESCALE +#define PCI_VENDOR_ID_PASEMI 0x1959 +#define PCI_VENDOR_ID_ATTANSIC 0x1969 +#define PCI_VENDOR_ID_JMICRON 0x197b +#define PCI_VENDOR_ID_KORENIX 0x1982 +#define PCI_VENDOR_ID_HUAWEI 0x19e5 +#define PCI_VENDOR_ID_NETRONOME 0x19ee +#define PCI_VENDOR_ID_QMI 0x1a32 +#define PCI_VENDOR_ID_AZWAVE 0x1a3b +#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 +#define PCI_VENDOR_ID_ASMEDIA 0x1b21 +#define PCI_VENDOR_ID_REDHAT 0x1b36 +#define PCI_VENDOR_ID_SILICOM_DENMARK 0x1c2c +#define PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS 0x1c36 +#define PCI_VENDOR_ID_CIRCUITCO 0x1cc8 +#define PCI_VENDOR_ID_AMAZON 0x1d0f +#define PCI_VENDOR_ID_ZHAOXIN 0x1d17 +#define PCI_VENDOR_ID_HYGON 0x1d94 +#define PCI_VENDOR_ID_FUNGIBLE 0x1dad +#define PCI_VENDOR_ID_HXT 0x1dbf +#define PCI_VENDOR_ID_TEKRAM 0x1de1 +#define PCI_VENDOR_ID_TEHUTI 0x1fc9 +#define PCI_VENDOR_ID_SUNIX 0x1fd4 +#define PCI_VENDOR_ID_HINT 0x3388 +#define PCI_VENDOR_ID_3DLABS 0x3d3d +#define PCI_VENDOR_ID_NETXEN 0x4040 +#define PCI_VENDOR_ID_AKS 0x416c +#define PCI_VENDOR_ID_ACCESSIO 0x494f +#define PCI_VENDOR_ID_S3 0x5333 +#define PCI_VENDOR_ID_DUNORD 0x5544 +#define PCI_VENDOR_ID_DCI 0x6666 +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_VENDOR_ID_SCALEMP 0x8686 +#define PCI_VENDOR_ID_COMPUTONE 0x8e0e +#define PCI_VENDOR_ID_KTI 0x8e2e +#define PCI_VENDOR_ID_ADAPTEC 0x9004 +#define PCI_VENDOR_ID_ADAPTEC2 0x9005 +#define PCI_VENDOR_ID_HOLTEK 0x9412 +#define PCI_VENDOR_ID_NETMOS 0x9710 +#define PCI_VENDOR_ID_3COM_2 0xa727 +#define PCI_VENDOR_ID_DIGIUM 0xd161 +#define PCI_VENDOR_ID_TIGERJET 0xe159 +#define PCI_VENDOR_ID_XILINX_RME 0xea60 +#define PCI_VENDOR_ID_XEN 0x5853 +#define PCI_VENDOR_ID_OCZ 0x1b85 +#define PCI_VENDOR_ID_NCUBE 0x10ff + +#endif /* __PCI_IDS_H__ */ diff --git a/rt-thread/components/drivers/pci/pci_regs.h b/rt-thread/components/drivers/pci/pci_regs.h new file mode 100644 index 0000000..5a8822c --- /dev/null +++ b/rt-thread/components/drivers/pci/pci_regs.h @@ -0,0 +1,1090 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __PCI_REGS_H__ +#define __PCI_REGS_H__ + +#include + +/* + * PCI standard defines + * Copyright 1994, Drew Eckhardt + * Copyright 1997--1999 Martin Mares + * + * For more information, please consult the following manuals (look at + * http://www.pcisig.com/ for how to get them): + * + * PCI BIOS Specification + * PCI Local Bus Specification + * PCI to PCI Bridge Specification + * PCI System Design Guide + * + * For HyperTransport information, please consult the following manuals + * from http://www.hypertransport.org : + * + * The HyperTransport I/O Link Specification + * + * Mean of prefix: + * + * PCIM_xxx: mask to locate subfield in register + * PCIR_xxx: config register offset + * PCIC_xxx: device class + * PCIS_xxx: device subclass + * PCIP_xxx: device programming interface + * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) + * PCID_xxx: device ID + * PCIY_xxx: capability identification number + * PCIZ_xxx: extended capability identification number + */ + +/* some PCI bus constants */ +#define PCI_DOMAINMAX 65535 /* highest supported domain number */ +#define PCI_BUSMAX 255 /* highest supported bus number */ +#define PCI_SLOTMAX 31 /* highest supported slot number */ +#define PCI_FUNCMAX 7 /* highest supported function number */ +#define PCI_REGMAX 255 /* highest supported config register addr */ +#define PCIE_REGMAX 4095 /* highest supported config register addr */ +#define PCI_MAXHDRTYPE 2 +#define PCI_STD_HEADER_SIZEOF 64 +#define PCI_STD_NUM_BARS 6 /* number of standard BARs */ + +/* PCI config header registers for all devices */ + +#define PCIR_DEVVENDOR 0x00 +#define PCIR_VENDOR 0x00 +#define PCIR_DEVICE 0x02 +#define PCIR_COMMAND 0x04 +#define PCIM_CMD_PORTEN 0x0001 +#define PCIM_CMD_MEMEN 0x0002 +#define PCIM_CMD_BUSMASTEREN 0x0004 +#define PCIM_CMD_SPECIALEN 0x0008 +#define PCIM_CMD_MWRICEN 0x0010 +#define PCIM_CMD_PERRESPEN 0x0040 +#define PCIM_CMD_SERRESPEN 0x0100 +#define PCIM_CMD_BACKTOBACK 0x0200 +#define PCIM_CMD_INTxDIS 0x0400 +#define PCIR_STATUS 0x06 +#define PCIM_STATUS_INTxSTATE 0x0008 +#define PCIM_STATUS_CAPPRESENT 0x0010 +#define PCIM_STATUS_66CAPABLE 0x0020 +#define PCIM_STATUS_BACKTOBACK 0x0080 +#define PCIM_STATUS_MDPERR 0x0100 +#define PCIM_STATUS_SEL_FAST 0x0000 +#define PCIM_STATUS_SEL_MEDIMUM 0x0200 +#define PCIM_STATUS_SEL_SLOW 0x0400 +#define PCIM_STATUS_SEL_MASK 0x0600 +#define PCIM_STATUS_STABORT 0x0800 +#define PCIM_STATUS_RTABORT 0x1000 +#define PCIM_STATUS_RMABORT 0x2000 +#define PCIM_STATUS_SERR 0x4000 +#define PCIM_STATUS_PERR 0x8000 +#define PCIR_REVID 0x08 +#define PCIR_PROGIF 0x09 +#define PCIR_SUBCLASS 0x0a +#define PCIR_CLASS 0x0b +#define PCIR_CACHELNSZ 0x0c +#define PCIR_LATTIMER 0x0d +#define PCIR_HDRTYPE 0x0e +#define PCIM_HDRTYPE 0x7f +#define PCIM_HDRTYPE_NORMAL 0x00 +#define PCIM_HDRTYPE_BRIDGE 0x01 +#define PCIM_HDRTYPE_CARDBUS 0x02 +#define PCIM_MFDEV 0x80 +#define PCIR_BIST 0x0f + +/* PCI Spec rev 2.2: 0FFFFh is an invalid value for Vendor ID. */ +#define PCIV_INVALID 0xffff + +/* Capability Register Offsets */ + +#define PCICAP_ID 0x0 +#define PCICAP_NEXTPTR 0x1 + +/* Capability Identification Numbers */ + +#define PCIY_PMG 0x01 /* PCI Power Management */ +#define PCIY_AGP 0x02 /* AGP */ +#define PCIY_VPD 0x03 /* Vital Product Data */ +#define PCIY_SLOTID 0x04 /* Slot Identification */ +#define PCIY_MSI 0x05 /* Message Signaled Interrupts */ +#define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ +#define PCIY_PCIX 0x07 /* PCI-X */ +#define PCIY_HT 0x08 /* HyperTransport */ +#define PCIY_VENDOR 0x09 /* Vendor Unique */ +#define PCIY_DEBUG 0x0a /* Debug port */ +#define PCIY_CRES 0x0b /* CompactPCI central resource control */ +#define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ +#define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ +#define PCIY_AGP8X 0x0e /* AGP 8x */ +#define PCIY_SECDEV 0x0f /* Secure Device */ +#define PCIY_EXPRESS 0x10 /* PCI Express */ +#define PCIY_MSIX 0x11 /* MSI-X */ +#define PCIY_SATA 0x12 /* SATA */ +#define PCIY_PCIAF 0x13 /* PCI Advanced Features */ +#define PCIY_EA 0x14 /* PCI Extended Allocation */ +#define PCIY_FPB 0x15 /* Flattening Portal Bridge */ +#define PCIY_MAX PCIY_FPB + +/* Extended Capability Register Fields */ + +#define PCIR_EXTCAP 0x100 +#define PCIM_EXTCAP_ID 0x0000ffff +#define PCIM_EXTCAP_VER 0x000f0000 +#define PCIM_EXTCAP_NEXTPTR 0xfff00000 +#define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID) +#define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16) +#define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20) + +/* Extended Capability Identification Numbers */ + +#define PCIZ_AER 0x0001 /* Advanced Error Reporting */ +#define PCIZ_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */ +#define PCIZ_SERNUM 0x0003 /* Device Serial Number */ +#define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ +#define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ +#define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ +#define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ +#define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */ +#define PCIZ_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */ +#define PCIZ_RCRB 0x000a /* RCRB Header */ +#define PCIZ_VENDOR 0x000b /* Vendor Unique */ +#define PCIZ_CAC 0x000c /* Configuration Access Correction -- obsolete */ +#define PCIZ_ACS 0x000d /* Access Control Services */ +#define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ +#define PCIZ_ATS 0x000f /* Address Translation Services */ +#define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ +#define PCIZ_MRIOV 0x0011 /* Multiple Root IO Virtualization */ +#define PCIZ_MULTICAST 0x0012 /* Multicast */ +#define PCIZ_PAGE_REQ 0x0013 /* Page Request */ +#define PCIZ_AMD 0x0014 /* Reserved for AMD */ +#define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */ +#define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */ +#define PCIZ_TPH_REQ 0x0017 /* TPH Requester */ +#define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */ +#define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */ +#define PCIZ_PMUX 0x001a /* Protocol Multiplexing */ +#define PCIZ_PASID 0x001b /* Process Address Space ID */ +#define PCIZ_LN_REQ 0x001c /* LN Requester */ +#define PCIZ_DPC 0x001d /* Downstream Port Containment */ +#define PCIZ_L1PM 0x001e /* L1 PM Substates */ +#define PCIZ_PTM 0x001f /* Precision Time Measurement */ +#define PCIZ_M_PCIE 0x0020 /* PCIe over M-PHY */ +#define PCIZ_FRS 0x0021 /* FRS Queuing */ +#define PCIZ_RTR 0x0022 /* Readiness Time Reporting */ +#define PCIZ_DVSEC 0x0023 /* Designated Vendor-Specific */ +#define PCIZ_VF_REBAR 0x0024 /* VF Resizable BAR */ +#define PCIZ_DLNK 0x0025 /* Data Link Feature */ +#define PCIZ_16GT 0x0026 /* Physical Layer 16.0 GT/s */ +#define PCIZ_LMR 0x0027 /* Lane Margining at Receiver */ +#define PCIZ_HIER_ID 0x0028 /* Hierarchy ID */ +#define PCIZ_NPEM 0x0029 /* Native PCIe Enclosure Management */ +#define PCIZ_PL32 0x002a /* Physical Layer 32.0 GT/s */ +#define PCIZ_AP 0x002b /* Alternate Protocol */ +#define PCIZ_SFI 0x002c /* System Firmware Intermediary */ + +/* Resizable BARs */ +#define PCIM_REBAR_CAP 4 /* Capability register */ +#define PCIM_REBAR_CAP_SIZES 0x00fffff0 /* Supported BAR sizes */ +#define PCIM_REBAR_CTRL 8 /* Control register */ +#define PCIM_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */ +#define PCIM_REBAR_CTRL_NBAR_MASK 0x000000e0 +#define PCIM_REBAR_CTRL_NBAR_SHIFT 5 /* Shift for # of BARs */ +#define PCIM_REBAR_CTRL_BAR_SIZE 0x00001f00 /* BAR size */ +#define PCIM_REBAR_CTRL_BAR_SHIFT 8 /* Shift for BAR size */ + +/* config registers for header type 0 devices */ + +#define PCIR_BARS 0x10 +#define PCIR_BAR(x) (PCIR_BARS + (x) * 4) +#define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) +#define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) +#define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) +#define PCIM_BAR_SPACE 0x01 /* 0 = memory, 1 = I/O */ +#define PCIM_BAR_SPACE_IO 0x01 +#define PCIM_BAR_SPACE_MEMORY 0x00 +#define PCIM_BAR_MEM_TYPE_MASK 0x06 +#define PCIM_BAR_MEM_TYPE_32 0x00 /* 32 bit address */ +#define PCIM_BAR_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ +#define PCIM_BAR_MEM_TYPE_64 0x04 /* 64 bit address */ +#define PCIM_BAR_MEM_PREFETCH 0x08 /* prefetchable? */ +#define PCIM_BAR_MEM_MASK (~0x0fUL) +#define PCIM_BAR_IO_MASK (~0x03UL) +#define PCIR_CIS 0x28 +#define PCIM_CIS_ASI_MASK 0x00000007 +#define PCIM_CIS_ASI_CONFIG 0 +#define PCIM_CIS_ASI_BAR0 1 +#define PCIM_CIS_ASI_BAR1 2 +#define PCIM_CIS_ASI_BAR2 3 +#define PCIM_CIS_ASI_BAR3 4 +#define PCIM_CIS_ASI_BAR4 5 +#define PCIM_CIS_ASI_BAR5 6 +#define PCIM_CIS_ASI_ROM 7 +#define PCIM_CIS_ADDR_MASK 0x0ffffff8 +#define PCIM_CIS_ROM_MASK 0xf0000000 +#define PCIM_CIS_CONFIG_MASK 0xff +#define PCIR_SUBVEND_0 0x2c +#define PCIR_SUBDEV_0 0x2e +#define PCIR_BIOS 0x30 +#define PCIM_BIOS_ENABLE 0x01 +#define PCIM_BIOS_ADDR_MASK 0xfffff800 +#define PCIR_CAP_PTR 0x34 +#define PCIR_INTLINE 0x3c +#define PCIR_INTPIN 0x3d +#define PCIR_MINGNT 0x3e +#define PCIR_MAXLAT 0x3f + +/* config registers for header type 1 (PCI-to-PCI bridge) devices */ + +#define PCIR_MAX_BAR_1 1 +#define PCIR_SECSTAT_1 0x1e + +#define PCIR_PRIBUS_1 0x18 +#define PCIR_SECBUS_1 0x19 +#define PCIR_SUBBUS_1 0x1a +#define PCIR_SECLAT_1 0x1b + +#define PCIR_IOBASEL_1 0x1c +#define PCIR_IOLIMITL_1 0x1d +#define PCIR_IOBASEH_1 0x30 +#define PCIR_IOLIMITH_1 0x32 +#define PCIM_BRIO_16 0x0 +#define PCIM_BRIO_32 0x1 +#define PCIM_BRIO_MASK 0xf + +#define PCIR_MEMBASE_1 0x20 +#define PCIR_MEMLIMIT_1 0x22 + +#define PCIR_PMBASEL_1 0x24 +#define PCIR_PMLIMITL_1 0x26 +#define PCIR_PMBASEH_1 0x28 +#define PCIR_PMLIMITH_1 0x2c +#define PCIM_BRPM_32 0x0 +#define PCIM_BRPM_64 0x1 +#define PCIM_BRPM_MASK 0xf + +#define PCIR_BIOS_1 0x38 +#define PCIR_BRIDGECTL_1 0x3e + +#define PCI_PPBMEMBASE(h, l) ((((rt_uint64_t)(h) << 32) + ((l) << 16)) & ~0xfffff) +#define PCI_PPBMEMLIMIT(h, l) ((((rt_uint64_t)(h) << 32) + ((l) << 16)) | 0xfffff) +#define PCI_PPBIOBASE(h, l) ((((h) << 16) + ((l) << 8)) & ~0xfff) +#define PCI_PPBIOLIMIT(h, l) ((((h) << 16) + ((l) << 8)) | 0xfff) + +/* config registers for header t ype 2 (CardBus) devices */ + +#define PCIR_MAX_BAR_2 0 +#define PCIR_CAP_PTR_2 0x14 +#define PCIR_SECSTAT_2 0x16 + +#define PCIR_PRIBUS_2 0x18 +#define PCIR_SECBUS_2 0x19 +#define PCIR_SUBBUS_2 0x1a +#define PCIR_SECLAT_2 0x1b + +#define PCIR_MEMBASE0_2 0x1c +#define PCIR_MEMLIMIT0_2 0x20 +#define PCIR_MEMBASE1_2 0x24 +#define PCIR_MEMLIMIT1_2 0x28 +#define PCIR_IOBASE0_2 0x2c +#define PCIR_IOLIMIT0_2 0x30 +#define PCIR_IOBASE1_2 0x34 +#define PCIR_IOLIMIT1_2 0x38 +#define PCIM_CBBIO_16 0x0 +#define PCIM_CBBIO_32 0x1 +#define PCIM_CBBIO_MASK 0x3 + +#define PCIR_BRIDGECTL_2 0x3e + +#define PCIR_SUBVEND_2 0x40 +#define PCIR_SUBDEV_2 0x42 + +#define PCIR_PCCARDIF_2 0x44 + +#define PCI_CBBMEMBASE(l) ((l) & ~0xfffff) +#define PCI_CBBMEMLIMIT(l) ((l) | 0xfffff) +#define PCI_CBBIOBASE(l) ((l) & ~0x3) +#define PCI_CBBIOLIMIT(l) ((l) | 0x3) + +/* PCI device class, subclass and programming interface definitions */ +#define PCIC_NOT_DEFINED 0x0000 +#define PCIS_NOT_DEFINED_VGA 0x0001 + +#define PCIC_STORAGE 0x01 +#define PCIS_STORAGE_SCSI 0x0100 +#define PCIS_STORAGE_IDE 0x0101 +#define PCIS_STORAGE_FLOPPY 0x0102 +#define PCIS_STORAGE_IPI 0x0103 +#define PCIS_STORAGE_RAID 0x0104 +#define PCIS_STORAGE_SATA 0x0106 +#define PCIS_STORAGE_SATA_AHCI 0x010601 +#define PCIS_STORAGE_SAS 0x0107 +#define PCIS_STORAGE_EXPRESS 0x010802 +#define PCIS_STORAGE_OTHER 0x0180 + +#define PCIC_NETWORK 0x02 +#define PCIS_NETWORK_ETHERNET 0x0200 +#define PCIS_NETWORK_TOKEN_RING 0x0201 +#define PCIS_NETWORK_FDDI 0x0202 +#define PCIS_NETWORK_ATM 0x0203 +#define PCIS_NETWORK_OTHER 0x0280 + +#define PCIC_DISPLAY 0x03 +#define PCIS_DISPLAY_VGA 0x0300 +#define PCIS_DISPLAY_XGA 0x0301 +#define PCIS_DISPLAY_3D 0x0302 +#define PCIS_DISPLAY_OTHER 0x0380 + +#define PCIC_MULTIMEDIA 0x04 +#define PCIS_MULTIMEDIA_VIDEO 0x0400 +#define PCIS_MULTIMEDIA_AUDIO 0x0401 +#define PCIS_MULTIMEDIA_PHONE 0x0402 +#define PCIS_MULTIMEDIA_HD_AUDIO 0x0403 +#define PCIS_MULTIMEDIA_OTHER 0x0480 + +#define PCIC_MEMORY 0x05 +#define PCIS_MEMORY_RAM 0x0500 +#define PCIS_MEMORY_FLASH 0x0501 +#define PCIS_MEMORY_CXL 0x0502 +#define PCIS_MEMORY_OTHER 0x0580 + +#define PCIC_BRIDGE 0x06 +#define PCIS_BRIDGE_HOST 0x0600 +#define PCIS_BRIDGE_ISA 0x0601 +#define PCIS_BRIDGE_EISA 0x0602 +#define PCIS_BRIDGE_MC 0x0603 +#define PCIS_BRIDGE_PCI 0x0604 +#define PCIS_BRIDGE_PCI_NORMAL 0x060400 +#define PCIS_BRIDGE_PCI_SUBTRACTIVE 0x060401 +#define PCIS_BRIDGE_PCMCIA 0x0605 +#define PCIS_BRIDGE_NUBUS 0x0606 +#define PCIS_BRIDGE_CARDBUS 0x0607 +#define PCIS_BRIDGE_RACEWAY 0x0608 +#define PCIS_BRIDGE_OTHER 0x0680 + +#define PCIC_COMMUNICATION 0x07 +#define PCIS_COMMUNICATION_SERIAL 0x0700 +#define PCIS_COMMUNICATION_PARALLEL 0x0701 +#define PCIS_COMMUNICATION_MULTISERIAL 0x0702 +#define PCIS_COMMUNICATION_MODEM 0x0703 +#define PCIS_COMMUNICATION_OTHER 0x0780 + +#define PCIC_SYSTEM 0x08 +#define PCIS_SYSTEM_PIC 0x0800 +#define PCIS_SYSTEM_PIC_IOAPIC 0x080010 +#define PCIS_SYSTEM_PIC_IOXAPIC 0x080020 +#define PCIS_SYSTEM_DMA 0x0801 +#define PCIS_SYSTEM_TIMER 0x0802 +#define PCIS_SYSTEM_RTC 0x0803 +#define PCIS_SYSTEM_PCI_HOTPLUG 0x0804 +#define PCIS_SYSTEM_SDHCI 0x0805 +#define PCIS_SYSTEM_RCEC 0x0807 +#define PCIS_SYSTEM_OTHER 0x0880 + +#define PCIC_INPUT 0x09 +#define PCIS_INPUT_KEYBOARD 0x0900 +#define PCIS_INPUT_PEN 0x0901 +#define PCIS_INPUT_MOUSE 0x0902 +#define PCIS_INPUT_SCANNER 0x0903 +#define PCIS_INPUT_GAMEPORT 0x0904 +#define PCIS_INPUT_OTHER 0x0980 + +#define PCIC_DOCKING 0x0a +#define PCIS_DOCKING_GENERIC 0x0a00 +#define PCIS_DOCKING_OTHER 0x0a80 + +#define PCIC_PROCESSOR 0x0b +#define PCIS_PROCESSOR_386 0x0b00 +#define PCIS_PROCESSOR_486 0x0b01 +#define PCIS_PROCESSOR_PENTIUM 0x0b02 +#define PCIS_PROCESSOR_ALPHA 0x0b10 +#define PCIS_PROCESSOR_POWERPC 0x0b20 +#define PCIS_PROCESSOR_MIPS 0x0b30 +#define PCIS_PROCESSOR_CO 0x0b40 + +#define PCIC_SERIAL 0x0c +#define PCIS_SERIAL_FIREWIRE 0x0c00 +#define PCIS_SERIAL_FIREWIRE_OHCI 0x0c0010 +#define PCIS_SERIAL_ACCESS 0x0c01 +#define PCIS_SERIAL_SSA 0x0c02 +#define PCIS_SERIAL_USB 0x0c03 +#define PCIS_SERIAL_USB_UHCI 0x0c0300 +#define PCIS_SERIAL_USB_OHCI 0x0c0310 +#define PCIS_SERIAL_USB_EHCI 0x0c0320 +#define PCIS_SERIAL_USB_XHCI 0x0c0330 +#define PCIS_SERIAL_USB_DEVICE 0x0c03fe +#define PCIS_SERIAL_FIBER 0x0c04 +#define PCIS_SERIAL_SMBUS 0x0c05 +#define PCIS_SERIAL_IPMI 0x0c07 +#define PCIS_SERIAL_IPMI_SMIC 0x0c0700 +#define PCIS_SERIAL_IPMI_KCS 0x0c0701 +#define PCIS_SERIAL_IPMI_BT 0x0c0702 + +#define PCIC_WIRELESS 0x0d +#define PCIS_WIRELESS_RF_CONTROLLER 0x0d10 +#define PCIS_WIRELESS_WHCI 0x0d1010 + +#define PCIC_INTELLIGENT 0x0e +#define PCIS_INTELLIGENT_I2O 0x0e00 + +#define PCIC_SATELLITE 0x0f +#define PCIS_SATELLITE_TV 0x0f00 +#define PCIS_SATELLITE_AUDIO 0x0f01 +#define PCIS_SATELLITE_VOICE 0x0f03 +#define PCIS_SATELLITE_DATA 0x0f04 + +#define PCIC_CRYPT 0x10 +#define PCIS_CRYPT_NETWORK 0x1000 +#define PCIS_CRYPT_ENTERTAINMENT 0x1001 +#define PCIS_CRYPT_OTHER 0x1080 + +#define PCIC_SIGNAL_PROCESSING 0x11 +#define PCIS_SP_DPIO 0x1100 +#define PCIS_SP_OTHER 0x1180 + +#define PCIS_OTHERS 0xff + +/* Bridge Control Values. */ +#define PCIB_BCR_PERR_ENABLE 0x0001 +#define PCIB_BCR_SERR_ENABLE 0x0002 +#define PCIB_BCR_ISA_ENABLE 0x0004 +#define PCIB_BCR_VGA_ENABLE 0x0008 +#define PCIB_BCR_MASTER_ABORT_MODE 0x0020 +#define PCIB_BCR_SECBUS_RESET 0x0040 +#define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 +#define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 +#define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 +#define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 +#define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 + +#define CBB_BCR_PERR_ENABLE 0x0001 +#define CBB_BCR_SERR_ENABLE 0x0002 +#define CBB_BCR_ISA_ENABLE 0x0004 +#define CBB_BCR_VGA_ENABLE 0x0008 +#define CBB_BCR_MASTER_ABORT_MODE 0x0020 +#define CBB_BCR_CARDBUS_RESET 0x0040 +#define CBB_BCR_IREQ_INT_ENABLE 0x0080 +#define CBB_BCR_PREFETCH_0_ENABLE 0x0100 +#define CBB_BCR_PREFETCH_1_ENABLE 0x0200 +#define CBB_BCR_WRITE_POSTING_ENABLE 0x0400 + +/* PCI power manangement */ +#define PCIR_POWER_CAP 0x2 +#define PCIM_PCAP_SPEC 0x0007 +#define PCIM_PCAP_PMEREQCLK 0x0008 +#define PCIM_PCAP_DEVSPECINIT 0x0020 +#define PCIM_PCAP_AUXPWR_0 0x0000 +#define PCIM_PCAP_AUXPWR_55 0x0040 +#define PCIM_PCAP_AUXPWR_100 0x0080 +#define PCIM_PCAP_AUXPWR_160 0x00c0 +#define PCIM_PCAP_AUXPWR_220 0x0100 +#define PCIM_PCAP_AUXPWR_270 0x0140 +#define PCIM_PCAP_AUXPWR_320 0x0180 +#define PCIM_PCAP_AUXPWR_375 0x01c0 +#define PCIM_PCAP_AUXPWRMASK 0x01c0 +#define PCIM_PCAP_D1SUPP 0x0200 +#define PCIM_PCAP_D2SUPP 0x0400 +#define PCIM_PCAP_PMEMASK 0xf800 +#define PCIM_PCAP_D0PME 0x0800 +#define PCIM_PCAP_D1PME 0x1000 +#define PCIM_PCAP_D2PME 0x2000 +#define PCIM_PCAP_D3PME_HOT 0x4000 +#define PCIM_PCAP_D3PME_COLD 0x8000 + +#define PCIR_POWER_STATUS 0x4 +#define PCIM_PSTAT_D0 0x0000 +#define PCIM_PSTAT_D1 0x0001 +#define PCIM_PSTAT_D2 0x0002 +#define PCIM_PSTAT_D3 0x0003 +#define PCIM_PSTAT_DMASK 0x0003 +#define PCIM_PSTAT_NOSOFTRESET 0x0008 +#define PCIM_PSTAT_PMEENABLE 0x0100 +#define PCIM_PSTAT_D0POWER 0x0000 +#define PCIM_PSTAT_D1POWER 0x0200 +#define PCIM_PSTAT_D2POWER 0x0400 +#define PCIM_PSTAT_D3POWER 0x0600 +#define PCIM_PSTAT_D0HEAT 0x0800 +#define PCIM_PSTAT_D1HEAT 0x0a00 +#define PCIM_PSTAT_D2HEAT 0x0c00 +#define PCIM_PSTAT_D3HEAT 0x0e00 +#define PCIM_PSTAT_DATASELMASK 0x1e00 +#define PCIM_PSTAT_DATAUNKN 0x0000 +#define PCIM_PSTAT_DATADIV10 0x2000 +#define PCIM_PSTAT_DATADIV100 0x4000 +#define PCIM_PSTAT_DATADIV1000 0x6000 +#define PCIM_PSTAT_DATADIVMASK 0x6000 +#define PCIM_PSTAT_PME 0x8000 + +#define PCIR_POWER_BSE 0x6 +#define PCIM_PMCSR_BSE_D3B3 0x00 +#define PCIM_PMCSR_BSE_D3B2 0x40 +#define PCIM_PMCSR_BSE_BPCCE 0x80 + +#define PCIR_POWER_DATA 0x7 + +/* VPD capability registers */ +#define PCIR_VPD_ADDR 0x2 +#define PCIR_VPD_DATA 0x4 + +/* PCI Message Signalled Interrupts (MSI) */ +#define PCIR_MSI_CTRL 0x2 +#define PCIM_MSICTRL_VECTOR 0x0100 +#define PCIM_MSICTRL_64BIT 0x0080 +#define PCIM_MSICTRL_MME_MASK 0x0070 +#define PCIM_MSICTRL_MME_SHIFT 0x4 +#define PCIM_MSICTRL_MME_1 0x0000 +#define PCIM_MSICTRL_MME_2 0x0010 +#define PCIM_MSICTRL_MME_4 0x0020 +#define PCIM_MSICTRL_MME_8 0x0030 +#define PCIM_MSICTRL_MME_16 0x0040 +#define PCIM_MSICTRL_MME_32 0x0050 +#define PCIM_MSICTRL_MMC_MASK 0x000e +#define PCIM_MSICTRL_MMC_SHIFT 0x1 +#define PCIM_MSICTRL_MMC_1 0x0000 +#define PCIM_MSICTRL_MMC_2 0x0002 +#define PCIM_MSICTRL_MMC_4 0x0004 +#define PCIM_MSICTRL_MMC_8 0x0006 +#define PCIM_MSICTRL_MMC_16 0x0008 +#define PCIM_MSICTRL_MMC_32 0x000a +#define PCIM_MSICTRL_MSI_ENABLE 0x0001 +#define PCIR_MSI_ADDR 0x4 +#define PCIR_MSI_ADDR_HIGH 0x8 +#define PCIR_MSI_DATA 0x8 +#define PCIR_MSI_DATA_64BIT 0xc +#define PCIR_MSI_MASK 0xc +#define PCIR_MSI_MASK_64BIT 0x10 +#define PCIR_MSI_PENDING 0x14 + +/* PCI Enhanced Allocation registers */ +#define PCIR_EA_NUM_ENT 2 /* Number of Capability Entries */ +#define PCIM_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */ +#define PCIR_EA_FIRST_ENT 4 /* First EA Entry in List */ +#define PCIR_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */ +#define PCIM_EA_ES 0x00000007 /* Entry Size */ +#define PCIM_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ +#define PCIM_EA_BEI_OFFSET 4 +/* 0-5 map to BARs 0-5 respectively */ +#define PCIM_EA_BEI_BAR_0 0 +#define PCIM_EA_BEI_BAR_5 5 +#define PCIM_EA_BEI_BAR(x) (((x) >> PCIM_EA_BEI_OFFSET) & 0xf) +#define PCIM_EA_BEI_BRIDGE 0x6 /* Resource behind bridge */ +#define PCIM_EA_BEI_ENI 0x7 /* Equivalent Not Indicated */ +#define PCIM_EA_BEI_ROM 0x8 /* Expansion ROM */ +/* 9-14 map to VF BARs 0-5 respectively */ +#define PCIM_EA_BEI_VF_BAR_0 9 +#define PCIM_EA_BEI_VF_BAR_5 14 +#define PCIM_EA_BEI_RESERVED 0xf /* Reserved - Treat like ENI */ +#define PCIM_EA_PP 0x0000ff00 /* Primary Properties */ +#define PCIM_EA_PP_OFFSET 8 +#define PCIM_EA_SP_OFFSET 16 +#define PCIM_EA_SP 0x00ff0000 /* Secondary Properties */ +#define PCIM_EA_P_MEM 0x00 /* Non-Prefetch Memory */ +#define PCIM_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */ +#define PCIM_EA_P_IO 0x02 /* I/O Space */ +#define PCIM_EA_P_VF_MEM_PREFETCH 0x03 /* VF Prefetchable Memory */ +#define PCIM_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */ +#define PCIM_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */ +#define PCIM_EA_P_BRIDGE_MEM_PREFETCH 0x06 /* Bridge Prefetchable Memory */ +#define PCIM_EA_P_BRIDGE_IO 0x07 /* Bridge I/O Space */ +/* 0x08-0xfc reserved */ +#define PCIM_EA_P_MEM_RESERVED 0xfd /* Reserved Memory */ +#define PCIM_EA_P_IO_RESERVED 0xfe /* Reserved I/O Space */ +#define PCIM_EA_P_UNAVAILABLE 0xff /* Entry Unavailable */ +#define PCIM_EA_WRITABLE 0x40000000 /* Writable: 1 = RW, 0 = HwInit */ +#define PCIM_EA_ENABLE 0x80000000 /* Enable for this entry */ +#define PCIM_EA_BASE 4 /* Base Address Offset */ +#define PCIM_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */ +/* bit 0 is reserved */ +#define PCIM_EA_IS_64 0x00000002 /* 64-bit field flag */ +#define PCIM_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ +/* Bridge config register */ +#define PCIM_EA_SEC_NR(reg) ((reg) & 0xff) +#define PCIM_EA_SUB_NR(reg) (((reg) >> 8) & 0xff) + +/* PCI-X definitions */ + +/* For header type 0 devices */ +#define PCIXR_COMMAND 0x2 +#define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ +#define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ +#define PCIXM_COMMAND_MAX_READ_512 0x0000 +#define PCIXM_COMMAND_MAX_READ_1024 0x0004 +#define PCIXM_COMMAND_MAX_READ_2048 0x0008 +#define PCIXM_COMMAND_MAX_READ_4096 0x000c +#define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ +#define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 +#define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 +#define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 +#define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 +#define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 +#define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 +#define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 +#define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 +#define PCIXM_COMMAND_VERSION 0x3000 +#define PCIXR_STATUS 0x4 +#define PCIXM_STATUS_DEVFN 0x000000ff +#define PCIXM_STATUS_BUS 0x0000ff00 +#define PCIXM_STATUS_64BIT 0x00010000 +#define PCIXM_STATUS_133CAP 0x00020000 +#define PCIXM_STATUS_SC_DISCARDED 0x00040000 +#define PCIXM_STATUS_UNEXP_SC 0x00080000 +#define PCIXM_STATUS_COMPLEX_DEV 0x00100000 +#define PCIXM_STATUS_MAX_READ 0x00600000 +#define PCIXM_STATUS_MAX_READ_512 0x00000000 +#define PCIXM_STATUS_MAX_READ_1024 0x00200000 +#define PCIXM_STATUS_MAX_READ_2048 0x00400000 +#define PCIXM_STATUS_MAX_READ_4096 0x00600000 +#define PCIXM_STATUS_MAX_SPLITS 0x03800000 +#define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 +#define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 +#define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 +#define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 +#define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 +#define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 +#define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 +#define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 +#define PCIXM_STATUS_MAX_CUM_READ 0x1c000000 +#define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 +#define PCIXM_STATUS_266CAP 0x40000000 +#define PCIXM_STATUS_533CAP 0x80000000 + +/* For header type 1 devices (PCI-X bridges) */ +#define PCIXR_SEC_STATUS 0x2 +#define PCIXM_SEC_STATUS_64BIT 0x0001 +#define PCIXM_SEC_STATUS_133CAP 0x0002 +#define PCIXM_SEC_STATUS_SC_DISC 0x0004 +#define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 +#define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 +#define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 +#define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 +#define PCIXM_SEC_STATUS_VERSION 0x3000 +#define PCIXM_SEC_STATUS_266CAP 0x4000 +#define PCIXM_SEC_STATUS_533CAP 0x8000 +#define PCIXR_BRIDGE_STATUS 0x4 +#define PCIXM_BRIDGE_STATUS_DEVFN 0x000000ff +#define PCIXM_BRIDGE_STATUS_BUS 0x0000ff00 +#define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 +#define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 +#define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 +#define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 +#define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 +#define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 +#define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 +#define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 +#define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 + +/* HT (HyperTransport) Capability definitions */ +#define PCIR_HT_COMMAND 0x2 +#define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ +#define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ +#define PCIM_HTCAP_HOST 0x2000 /* 001xx */ +#define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ +#define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ +#define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ +#define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ +#define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ +#define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ +#define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ +#define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ +#define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ +#define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ +#define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ +#define PCIM_HTCAP_GEN3 0xd000 /* 11010 */ +#define PCIM_HTCAP_FLE 0xd800 /* 11011 */ +#define PCIM_HTCAP_PM 0xe000 /* 11100 */ +#define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */ + +/* HT MSI Mapping Capability definitions. */ +#define PCIM_HTCMD_MSI_ENABLE 0x0001 +#define PCIM_HTCMD_MSI_FIXED 0x0002 +#define PCIR_HTMSI_ADDRESS_LO 0x4 +#define PCIR_HTMSI_ADDRESS_HI 0x8 + +/* PCI Vendor capability definitions */ +#define PCIR_VENDOR_LENGTH 0x2 +#define PCIR_VENDOR_DATA 0x3 + +/* PCI Device capability definitions */ +#define PCIR_DEVICE_LENGTH 0x2 + +/* PCI EHCI Debug Port definitions */ +#define PCIR_DEBUG_PORT 0x2 +#define PCIM_DEBUG_PORT_OFFSET 0x1fff +#define PCIM_DEBUG_PORT_BAR 0xe000 + +/* PCI-PCI Bridge Subvendor definitions */ +#define PCIR_SUBVENDCAP_ID 0x4 +#define PCIR_SUBVENDCAP 0x4 +#define PCIR_SUBDEVCAP 0x6 + +/* PCI Express definitions */ +#define PCIER_FLAGS 0x2 +#define PCIEM_FLAGS_VERSION 0x000f +#define PCIEM_FLAGS_TYPE 0x00f0 +#define PCIEM_TYPE_ENDPOINT 0x0000 +#define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 +#define PCIEM_TYPE_ROOT_PORT 0x0040 +#define PCIEM_TYPE_UPSTREAM_PORT 0x0050 +#define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 +#define PCIEM_TYPE_PCI_BRIDGE 0x0070 +#define PCIEM_TYPE_PCIE_BRIDGE 0x0080 +#define PCIEM_TYPE_ROOT_INT_EP 0x0090 +#define PCIEM_TYPE_ROOT_EC 0x00a0 +#define PCIEM_FLAGS_SLOT 0x0100 +#define PCIEM_FLAGS_IRQ 0x3e00 +#define PCIER_DEVICE_CAP 0x4 +#define PCIEM_CAP_MAX_PAYLOAD 0x00000007 +#define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 +#define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 +#define PCIEM_CAP_L0S_LATENCY 0x000001c0 +#define PCIEM_CAP_L1_LATENCY 0x00000e00 +#define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 +#define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 +#define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 +#define PCIEM_CAP_FLR 0x10000000 +#define PCIER_DEVICE_CTL 0x8 +#define PCIEM_CTL_COR_ENABLE 0x0001 +#define PCIEM_CTL_NFER_ENABLE 0x0002 +#define PCIEM_CTL_FER_ENABLE 0x0004 +#define PCIEM_CTL_URR_ENABLE 0x0008 +#define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 +#define PCIEM_CTL_MAX_PAYLOAD 0x00e0 +#define PCIEM_CTL_EXT_TAG_FIELD 0x0100 +#define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 +#define PCIEM_CTL_AUX_POWER_PM 0x0400 +#define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 +#define PCIEM_CTL_MAX_READ_REQUEST 0x7000 +#define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ +#define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ +#define PCIER_DEVICE_STA 0xa +#define PCIEM_STA_CORRECTABLE_ERROR 0x0001 +#define PCIEM_STA_NON_FATAL_ERROR 0x0002 +#define PCIEM_STA_FATAL_ERROR 0x0004 +#define PCIEM_STA_UNSUPPORTED_REQ 0x0008 +#define PCIEM_STA_AUX_POWER 0x0010 +#define PCIEM_STA_TRANSACTION_PND 0x0020 +#define PCIER_LINK_CAP 0xc +#define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f +#define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 +#define PCIEM_LINK_CAP_ASPM 0x00000c00 +#define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 +#define PCIEM_LINK_CAP_L1_EXIT 0x00038000 +#define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 +#define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 +#define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 +#define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 +#define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 +#define PCIEM_LINK_CAP_PORT 0xff000000 +#define PCIER_LINK_CTL 0x10 +#define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 +#define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 +#define PCIEM_LINK_CTL_ASPMC_L1 0x0002 +#define PCIEM_LINK_CTL_ASPMC 0x0003 +#define PCIEM_LINK_CTL_RCB 0x0008 +#define PCIEM_LINK_CTL_LINK_DIS 0x0010 +#define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 +#define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 +#define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 +#define PCIEM_LINK_CTL_ECPM 0x0100 +#define PCIEM_LINK_CTL_HAWD 0x0200 +#define PCIEM_LINK_CTL_LBMIE 0x0400 +#define PCIEM_LINK_CTL_LABIE 0x0800 +#define PCIER_LINK_STA 0x12 +#define PCIEM_LINK_STA_SPEED 0x000f +#define PCIEM_LINK_STA_WIDTH 0x03f0 +#define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 +#define PCIEM_LINK_STA_TRAINING 0x0800 +#define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 +#define PCIEM_LINK_STA_DL_ACTIVE 0x2000 +#define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 +#define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 +#define PCIER_SLOT_CAP 0x14 +#define PCIEM_SLOT_CAP_APB 0x00000001 +#define PCIEM_SLOT_CAP_PCP 0x00000002 +#define PCIEM_SLOT_CAP_MRLSP 0x00000004 +#define PCIEM_SLOT_CAP_AIP 0x00000008 +#define PCIEM_SLOT_CAP_PIP 0x00000010 +#define PCIEM_SLOT_CAP_HPS 0x00000020 +#define PCIEM_SLOT_CAP_HPC 0x00000040 +#define PCIEM_SLOT_CAP_SPLV 0x00007f80 +#define PCIEM_SLOT_CAP_SPLS 0x00018000 +#define PCIEM_SLOT_CAP_EIP 0x00020000 +#define PCIEM_SLOT_CAP_NCCS 0x00040000 +#define PCIEM_SLOT_CAP_PSN 0xfff80000 +#define PCIER_SLOT_CTL 0x18 +#define PCIEM_SLOT_CTL_ABPE 0x0001 +#define PCIEM_SLOT_CTL_PFDE 0x0002 +#define PCIEM_SLOT_CTL_MRLSCE 0x0004 +#define PCIEM_SLOT_CTL_PDCE 0x0008 +#define PCIEM_SLOT_CTL_CCIE 0x0010 +#define PCIEM_SLOT_CTL_HPIE 0x0020 +#define PCIEM_SLOT_CTL_AIC 0x00c0 +#define PCIEM_SLOT_CTL_AI_ON 0x0040 +#define PCIEM_SLOT_CTL_AI_BLINK 0x0080 +#define PCIEM_SLOT_CTL_AI_OFF 0x00c0 +#define PCIEM_SLOT_CTL_PIC 0x0300 +#define PCIEM_SLOT_CTL_PI_ON 0x0100 +#define PCIEM_SLOT_CTL_PI_BLINK 0x0200 +#define PCIEM_SLOT_CTL_PI_OFF 0x0300 +#define PCIEM_SLOT_CTL_PCC 0x0400 +#define PCIEM_SLOT_CTL_PC_ON 0x0000 +#define PCIEM_SLOT_CTL_PC_OFF 0x0400 +#define PCIEM_SLOT_CTL_EIC 0x0800 +#define PCIEM_SLOT_CTL_DLLSCE 0x1000 +#define PCIER_SLOT_STA 0x1a +#define PCIEM_SLOT_STA_ABP 0x0001 +#define PCIEM_SLOT_STA_PFD 0x0002 +#define PCIEM_SLOT_STA_MRLSC 0x0004 +#define PCIEM_SLOT_STA_PDC 0x0008 +#define PCIEM_SLOT_STA_CC 0x0010 +#define PCIEM_SLOT_STA_MRLSS 0x0020 +#define PCIEM_SLOT_STA_PDS 0x0040 +#define PCIEM_SLOT_STA_EIS 0x0080 +#define PCIEM_SLOT_STA_DLLSC 0x0100 +#define PCIER_ROOT_CTL 0x1c +#define PCIEM_ROOT_CTL_SERR_CORR 0x0001 +#define PCIEM_ROOT_CTL_SERR_NONFATAL 0x0002 +#define PCIEM_ROOT_CTL_SERR_FATAL 0x0004 +#define PCIEM_ROOT_CTL_PME 0x0008 +#define PCIEM_ROOT_CTL_CRS_VIS 0x0010 +#define PCIER_ROOT_CAP 0x1e +#define PCIEM_ROOT_CAP_CRS_VIS 0x0001 +#define PCIER_ROOT_STA 0x20 +#define PCIEM_ROOT_STA_PME_REQID_MASK 0x0000ffff +#define PCIEM_ROOT_STA_PME_STATUS 0x00010000 +#define PCIEM_ROOT_STA_PME_PEND 0x00020000 +#define PCIER_DEVICE_CAP2 0x24 +#define PCIEM_CAP2_COMP_TIMO_RANGES 0x0000000f +#define PCIEM_CAP2_COMP_TIMO_RANGE_A 0x00000001 +#define PCIEM_CAP2_COMP_TIMO_RANGE_B 0x00000002 +#define PCIEM_CAP2_COMP_TIMO_RANGE_C 0x00000004 +#define PCIEM_CAP2_COMP_TIMO_RANGE_D 0x00000008 +#define PCIEM_CAP2_COMP_TIMO_DISABLE 0x00000010 +#define PCIEM_CAP2_ARI 0x00000020 +#define PCIER_DEVICE_CTL2 0x28 +#define PCIEM_CTL2_COMP_TIMO_VAL 0x000f +#define PCIEM_CTL2_COMP_TIMO_50MS 0x0000 +#define PCIEM_CTL2_COMP_TIMO_100US 0x0001 +#define PCIEM_CTL2_COMP_TIMO_10MS 0x0002 +#define PCIEM_CTL2_COMP_TIMO_55MS 0x0005 +#define PCIEM_CTL2_COMP_TIMO_210MS 0x0006 +#define PCIEM_CTL2_COMP_TIMO_900MS 0x0009 +#define PCIEM_CTL2_COMP_TIMO_3500MS 0x000a +#define PCIEM_CTL2_COMP_TIMO_13S 0x000d +#define PCIEM_CTL2_COMP_TIMO_64S 0x000e +#define PCIEM_CTL2_COMP_TIMO_DISABLE 0x0010 +#define PCIEM_CTL2_ARI 0x0020 +#define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 +#define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 +#define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 +#define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 +#define PCIEM_CTL2_LTR_ENABLE 0x0400 +#define PCIEM_CTL2_OBFF 0x6000 +#define PCIEM_OBFF_DISABLE 0x0000 +#define PCIEM_OBFF_MSGA_ENABLE 0x2000 +#define PCIEM_OBFF_MSGB_ENABLE 0x4000 +#define PCIEM_OBFF_WAKE_ENABLE 0x6000 +#define PCIEM_CTL2_END2END_TLP 0x8000 +#define PCIER_DEVICE_STA2 0x2a +#define PCIER_LINK_CAP2 0x2c +#define PCIER_LINK_CTL2 0x30 +#define PCIEM_LNKCTL2_TLS 0x000f +#define PCIEM_LNKCTL2_TLS_2_5GT 0x0001 +#define PCIEM_LNKCTL2_TLS_5_0GT 0x0002 +#define PCIEM_LNKCTL2_TLS_8_0GT 0x0003 +#define PCIEM_LNKCTL2_TLS_16_0GT 0x0004 +#define PCIEM_LNKCTL2_TLS_32_0GT 0x0005 +#define PCIEM_LNKCTL2_TLS_64_0GT 0x0006 +#define PCIEM_LNKCTL2_ENTER_COMP 0x0010 +#define PCIEM_LNKCTL2_TX_MARGIN 0x0380 +#define PCIEM_LNKCTL2_HASD 0x0020 +#define PCIER_LINK_STA2 0x32 +#define PCIER_SLOT_CAP2 0x34 +#define PCIER_SLOT_CTL2 0x38 +#define PCIER_SLOT_STA2 0x3a + +/* MSI-X definitions */ +#define PCIR_MSIX_CTRL 0x2 +#define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 +#define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 +#define PCIM_MSIXCTRL_TABLE_SIZE 0x07ff +#define PCIR_MSIX_TABLE 0x4 +#define PCIR_MSIX_PBA 0x8 +#define PCIM_MSIX_BIR_MASK 0x7 +#define PCIM_MSIX_TABLE_OFFSET 0xfffffff8 +#define PCIM_MSIX_BIR_BAR_10 0 +#define PCIM_MSIX_BIR_BAR_14 1 +#define PCIM_MSIX_BIR_BAR_18 2 +#define PCIM_MSIX_BIR_BAR_1C 3 +#define PCIM_MSIX_BIR_BAR_20 4 +#define PCIM_MSIX_BIR_BAR_24 5 +#define PCIM_MSIX_ENTRY_SIZE 16 +#define PCIM_MSIX_ENTRY_LOWER_ADDR 0x0 /* Message Address */ +#define PCIM_MSIX_ENTRY_UPPER_ADDR 0x4 /* Message Upper Address */ +#define PCIM_MSIX_ENTRY_DATA 0x8 /* Message Data */ +#define PCIM_MSIX_ENTRY_VECTOR_CTRL 0xc /* Vector Control */ +#define PCIM_MSIX_ENTRYVECTOR_CTRL_MASK 0x1 + +/* PCI Advanced Features definitions */ +#define PCIR_PCIAF_CAP 0x3 +#define PCIM_PCIAFCAP_TP 0x01 +#define PCIM_PCIAFCAP_FLR 0x02 +#define PCIR_PCIAF_CTRL 0x4 +#define PCIR_PCIAFCTRL_FLR 0x01 +#define PCIR_PCIAF_STATUS 0x5 +#define PCIR_PCIAFSTATUS_TP 0x01 + +/* Advanced Error Reporting */ +#define PCIR_AER_UC_STATUS 0x04 +#define PCIM_AER_UC_TRAINING_ERROR 0x00000001 +#define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 +#define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020 +#define PCIM_AER_UC_POISONED_TLP 0x00001000 +#define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 +#define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 +#define PCIM_AER_UC_COMPLETER_ABORT 0x00008000 +#define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000 +#define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000 +#define PCIM_AER_UC_MALFORMED_TLP 0x00040000 +#define PCIM_AER_UC_ECRC_ERROR 0x00080000 +#define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 +#define PCIM_AER_UC_ACS_VIOLATION 0x00200000 +#define PCIM_AER_UC_INTERNAL_ERROR 0x00400000 +#define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000 +#define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000 +#define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000 +#define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ +#define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ +#define PCIR_AER_COR_STATUS 0x10 +#define PCIM_AER_COR_RECEIVER_ERROR 0x00000001 +#define PCIM_AER_COR_BAD_TLP 0x00000040 +#define PCIM_AER_COR_BAD_DLLP 0x00000080 +#define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 +#define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 +#define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 +#define PCIM_AER_COR_INTERNAL_ERROR 0x00004000 +#define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000 +#define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ +#define PCIR_AER_CAP_CONTROL 0x18 +#define PCIM_AER_FIRST_ERROR_PTR 0x0000001f +#define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020 +#define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 +#define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 +#define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 +#define PCIM_AER_MULT_HDR_CAPABLE 0x00000200 +#define PCIM_AER_MULT_HDR_ENABLE 0x00000400 +#define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800 +#define PCIR_AER_HEADER_LOG 0x1c +#define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ +#define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 +#define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002 +#define PCIM_AER_ROOTERR_F_ENABLE 0x00000004 +#define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */ +#define PCIM_AER_ROOTERR_COR_ERR 0x00000001 +#define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002 +#define PCIM_AER_ROOTERR_UC_ERR 0x00000004 +#define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008 +#define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010 +#define PCIM_AER_ROOTERR_NF_ERR 0x00000020 +#define PCIM_AER_ROOTERR_F_ERR 0x00000040 +#define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 +#define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ +#define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ +#define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */ + +/* Virtual Channel definitions */ +#define PCIR_VC_CAP1 0x04 +#define PCIM_VC_CAP1_EXT_COUNT 0x00000007 +#define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070 +#define PCIR_VC_CAP2 0x08 +#define PCIR_VC_CONTROL 0x0c +#define PCIR_VC_STATUS 0x0e +#define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0c) +#define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0c) +#define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0c) + +/* Serial Number definitions */ +#define PCIR_SERIAL_LOW 0x04 +#define PCIR_SERIAL_HIGH 0x08 + +/* SR-IOV definitions */ +#define PCIR_SRIOV_CTL 0x08 +#define PCIM_SRIOV_VF_EN 0x01 +#define PCIM_SRIOV_VF_MSE 0x08 /* Memory space enable. */ +#define PCIM_SRIOV_ARI_EN 0x10 +#define PCIR_SRIOV_TOTAL_VFS 0x0e +#define PCIR_SRIOV_NUM_VFS 0x10 +#define PCIR_SRIOV_VF_OFF 0x14 +#define PCIR_SRIOV_VF_STRIDE 0x16 +#define PCIR_SRIOV_VF_DID 0x1a +#define PCIR_SRIOV_PAGE_CAP 0x1c +#define PCIR_SRIOV_PAGE_SIZE 0x20 + +#define PCI_SRIOV_BASE_PAGE_SHIFT 12 + +#define PCIR_SRIOV_BARS 0x24 +#define PCIR_SRIOV_BAR(x) (PCIR_SRIOV_BARS + (x) * 4) + +/* Extended Capability Vendor-Specific definitions */ +#define PCIR_VSEC_HEADER 0x04 +#define PCIR_VSEC_ID(hdr) ((hdr) & 0xffff) +#define PCIR_VSEC_REV(hdr) (((hdr) & 0xf0000) >> 16) +#define PCIR_VSEC_LENGTH(hdr) (((hdr) & 0xfff00000) >> 20) +#define PCIR_VSEC_DATA 0x08 + +/* ASPM L1 PM Substates */ +#define PCIR_L1SS_CAP 0x04 /* Capabilities Register */ +#define PCIM_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */ +#define PCIM_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */ +#define PCIM_L1SS_CAP_ASPM_L1_2 0x00000004 /* ASPM L1.2 Supported */ +#define PCIM_L1SS_CAP_ASPM_L1_1 0x00000008 /* ASPM L1.1 Supported */ +#define PCIM_L1SS_CAP_L1_PM_SS 0x00000010 /* L1 PM Substates Supported */ +#define PCIM_L1SS_CAP_CM_RESTORE_TIME 0x0000ff00 /* Port Common_Mode_Restore_Time */ +#define PCIM_L1SS_CAP_P_PWR_ON_SCALE 0x00030000 /* Port T_POWER_ON scale */ +#define PCIM_L1SS_CAP_P_PWR_ON_VALUE 0x00f80000 /* Port T_POWER_ON value */ +#define PCIR_L1SS_CTL1 0x08 /* Control 1 Register */ +#define PCIM_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */ +#define PCIM_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */ +#define PCIM_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */ +#define PCIM_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */ +#define PCIM_L1SS_CTL1_L1_2_MASK 0x00000005 +#define PCIM_L1SS_CTL1_L1SS_MASK 0x0000000f +#define PCIM_L1SS_CTL1_CM_RESTORE_TIME 0x0000ff00 /* Common_Mode_Restore_Time */ +#define PCIM_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */ +#define PCIM_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ +#define PCIR_L1SS_CTL2 0x0c /* Control 2 Register */ +#define PCIM_L1SS_CTL2_T_PWR_ON_SCALE 0x00000003 /* T_POWER_ON Scale */ +#define PCIM_L1SS_CTL2_T_PWR_ON_VALUE 0x000000f8 /* T_POWER_ON Value */ + +/* Alternative Routing-ID Interpretation */ +#define PCIR_ARI_CAP 0x04 /* Capabilities Register */ +#define PCIM_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ +#define PCIM_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ +#define PCIM_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ +#define PCIR_ARI_CTRL 0x06 /* ARI Control Register */ +#define PCIM_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ +#define PCIM_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ +#define PCIM_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ +#define PCIR_EXT_CAP_ARI_SIZEOF 8 + +/* + * PCI Express Firmware Interface definitions + */ +#define PCI_OSC_STATUS 0 +#define PCI_OSC_SUPPORT 1 +#define PCIM_OSC_SUPPORT_EXT_PCI_CONF 0x01 /* Extended PCI Config Space */ +#define PCIM_OSC_SUPPORT_ASPM 0x02 /* Active State Power Management */ +#define PCIM_OSC_SUPPORT_CPMC 0x04 /* Clock Power Management Cap */ +#define PCIM_OSC_SUPPORT_SEG_GROUP 0x08 /* PCI Segment Groups supported */ +#define PCIM_OSC_SUPPORT_MSI 0x10 /* MSI signalling supported */ +#define PCI_OSC_CTL 2 +#define PCIM_OSC_CTL_PCIE_HP 0x01 /* PCIe Native Hot Plug */ +#define PCIM_OSC_CTL_SHPC_HP 0x02 /* SHPC Native Hot Plug */ +#define PCIM_OSC_CTL_PCIE_PME 0x04 /* PCIe Native Power Mgt Events */ +#define PCIM_OSC_CTL_PCIE_AER 0x08 /* PCIe Advanced Error Reporting */ +#define PCIM_OSC_CTL_PCIE_CAP_STRUCT 0x10 /* Various Capability Structures */ + +#endif /* __PCI_REGS_H__ */ diff --git a/rt-thread/components/drivers/pci/pme.c b/rt-thread/components/drivers/pci/pme.c new file mode 100644 index 0000000..b4278d3 --- /dev/null +++ b/rt-thread/components/drivers/pci/pme.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#include +#include + +#define DBG_TAG "pci.pme" +#define DBG_LVL DBG_INFO +#include + +/* + * Power Management Capability Register: + * + * 31 27 26 25 24 22 21 20 19 18 16 15 8 7 0 + * +---------+---+---+--------+---+---+---+------+-----------+----------------+ + * | | | | | | | | | | Capabilitiy ID | + * +---------+---+---+--------+---+---+---+------+-----------+----------------+ + * ^ ^ ^ ^ ^ ^ ^ ^ ^ + * | | | | | | | | | + * | | | | | | | | +---- Next Capabilitiy Pointer + * | | | | | | | +------------- Version + * | | | | | | +------------------- PME Clock + * | | | | | +----------------------- Immediate Readiness on Return to D0 + * | | | | +--------------------------- Device Specifiic Initializtion + * | | | +--------------------------------- Aux Current + * | | +---------------------------------------- D1 Support + * | +-------------------------------------------- D2 Support + * +--------------------------------------------------- PME Support + */ + +void rt_pci_pme_init(struct rt_pci_device *pdev) +{ + rt_uint16_t pmc; + + if (!pdev || !(pdev->pme_cap = rt_pci_find_capability(pdev, PCIY_PMG))) + { + return; + } + + rt_pci_read_config_u16(pdev, pdev->pme_cap + PCIR_POWER_CAP, &pmc); + + if ((pmc & PCIM_PCAP_SPEC) > 3) + { + LOG_E("%s: Unsupported PME CAP regs spec %u", + rt_dm_dev_get_name(&pdev->parent), pmc & PCIM_PCAP_SPEC); + + return; + } + + pmc &= PCIM_PCAP_PMEMASK; + + if (pmc) + { + pdev->pme_support = RT_FIELD_GET(PCIM_PCAP_PMEMASK, pmc); + + rt_pci_pme_active(pdev, RT_FALSE); + } +} + +rt_err_t rt_pci_enable_wake(struct rt_pci_device *pdev, + enum rt_pci_power state, rt_bool_t enable) +{ + if (!pdev || state >= RT_PCI_PME_MAX) + { + return -RT_EINVAL; + } + + if (enable) + { + if (rt_pci_pme_capable(pdev, state) || + rt_pci_pme_capable(pdev, RT_PCI_D3COLD)) + { + rt_pci_pme_active(pdev, RT_EOK); + } + } + else + { + rt_pci_pme_active(pdev, RT_FALSE); + } + + return RT_EOK; +} + +static void pci_pme_active(struct rt_pci_device *pdev, rt_bool_t enable) +{ + rt_uint16_t pmcsr; + + if (!pdev->pme_support) + { + return; + } + + rt_pci_read_config_u16(pdev, pdev->pme_cap + PCIR_POWER_STATUS, &pmcsr); + /* Clear PME_Status by writing 1 to it and enable PME# */ + pmcsr |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; + + if (!enable) + { + pmcsr &= ~PCIM_PSTAT_PMEENABLE; + } + + rt_pci_write_config_u16(pdev, pdev->pme_cap + PCIR_POWER_STATUS, pmcsr); +} + +void rt_pci_pme_active(struct rt_pci_device *pdev, rt_bool_t enable) +{ + if (!pdev) + { + return; + } + + pci_pme_active(pdev, enable); + rt_dm_power_domain_attach(&pdev->parent, enable); +} diff --git a/rt-thread/components/drivers/pci/probe.c b/rt-thread/components/drivers/pci/probe.c new file mode 100644 index 0000000..fc15eaa --- /dev/null +++ b/rt-thread/components/drivers/pci/probe.c @@ -0,0 +1,926 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#include + +#define DBG_TAG "pci.probe" +#define DBG_LVL DBG_INFO +#include + +#include +#include + +rt_inline void spin_lock(struct rt_spinlock *spinlock) +{ + rt_hw_spin_lock(&spinlock->lock); +} + +rt_inline void spin_unlock(struct rt_spinlock *spinlock) +{ + rt_hw_spin_unlock(&spinlock->lock); +} + +struct rt_pci_host_bridge *rt_pci_host_bridge_alloc(rt_size_t priv_size) +{ + struct rt_pci_host_bridge *bridge = rt_calloc(1, sizeof(*bridge) + priv_size); + + return bridge; +} + +rt_err_t rt_pci_host_bridge_free(struct rt_pci_host_bridge *bridge) +{ + if (!bridge) + { + return -RT_EINVAL; + } + + if (bridge->bus_regions) + { + rt_free(bridge->bus_regions); + } + + if (bridge->dma_regions) + { + rt_free(bridge->dma_regions); + } + + rt_free(bridge); + + return RT_EOK; +} + +rt_err_t rt_pci_host_bridge_init(struct rt_pci_host_bridge *host_bridge) +{ + rt_err_t err = RT_EOK; + + if (host_bridge->parent.ofw_node) + { + err = rt_pci_ofw_host_bridge_init(host_bridge->parent.ofw_node, host_bridge); + } + + return err; +} + +struct rt_pci_device *rt_pci_alloc_device(struct rt_pci_bus *bus) +{ + struct rt_pci_device *pdev = rt_calloc(1, sizeof(*pdev)); + + if (!pdev) + { + return RT_NULL; + } + + rt_list_init(&pdev->list); + pdev->bus = bus; + + if (bus) + { + spin_lock(&bus->lock); + rt_list_insert_before(&bus->devices_nodes, &pdev->list); + spin_unlock(&bus->lock); + } + + pdev->subsystem_vendor = PCI_ANY_ID; + pdev->subsystem_device = PCI_ANY_ID; + + pdev->irq = -1; + + for (int i = 0; i < RT_ARRAY_SIZE(pdev->resource); ++i) + { + pdev->resource[i].flags = PCI_BUS_REGION_F_NONE; + } + +#ifdef RT_PCI_MSI + rt_list_init(&pdev->msi_desc_nodes); + rt_spin_lock_init(&pdev->msi_lock); +#endif + + return pdev; +} + +struct rt_pci_device *rt_pci_scan_single_device(struct rt_pci_bus *bus, rt_uint32_t devfn) +{ + rt_err_t err; + struct rt_pci_device *pdev = RT_NULL; + rt_uint16_t vendor = PCI_ANY_ID, device = PCI_ANY_ID; + + if (!bus) + { + goto _end; + } + + err = rt_pci_bus_read_config_u16(bus, devfn, PCIR_VENDOR, &vendor); + rt_pci_bus_read_config_u16(bus, devfn, PCIR_DEVICE, &device); + + if (vendor == (typeof(vendor))PCI_ANY_ID || + vendor == (typeof(vendor))0x0000 || err) + { + goto _end; + } + + if (!(pdev = rt_pci_alloc_device(bus))) + { + goto _end; + } + + pdev->devfn = devfn; + pdev->vendor = vendor; + pdev->device = device; + + rt_dm_dev_set_name(&pdev->parent, "%04x:%02x:%02x.%u", + rt_pci_domain(pdev), pdev->bus->number, + RT_PCI_SLOT(pdev->devfn), RT_PCI_FUNC(pdev->devfn)); + + if (rt_pci_setup_device(pdev)) + { + rt_free(pdev); + pdev = RT_NULL; + + goto _end; + } + + rt_pci_device_register(pdev); + +_end: + return pdev; +} + +static rt_bool_t pci_intx_mask_broken(struct rt_pci_device *pdev) +{ + rt_bool_t res = RT_FALSE; + rt_uint16_t orig, toggle, new; + + rt_pci_read_config_u16(pdev, PCIR_COMMAND, &orig); + toggle = orig ^ PCIM_CMD_INTxDIS; + rt_pci_write_config_u16(pdev, PCIR_COMMAND, toggle); + rt_pci_read_config_u16(pdev, PCIR_COMMAND, &new); + + rt_pci_write_config_u16(pdev, PCIR_COMMAND, orig); + + if (new != toggle) + { + res = RT_TRUE; + } + + return res; +} + +static void pci_read_irq(struct rt_pci_device *pdev) +{ + rt_uint8_t irq = 0; + + rt_pci_read_config_u8(pdev, PCIR_INTPIN, &irq); + pdev->pin = irq; + + if (irq) + { + rt_pci_read_config_u8(pdev, PCIR_INTLINE, &irq); + } + pdev->irq = irq; +} + +static void pcie_set_port_type(struct rt_pci_device *pdev) +{ + int pos; + + if (!(pos = rt_pci_find_capability(pdev, PCIY_EXPRESS))) + { + return; + } + + pdev->pcie_cap = pos; +} + +static void pci_configure_ari(struct rt_pci_device *pdev) +{ + rt_uint32_t cap, ctl2_ari; + struct rt_pci_device *bridge; + + if (!rt_pci_is_pcie(pdev) || pdev->devfn) + { + return; + } + + bridge = pdev->bus->self; + + if (rt_pci_is_root_bus(pdev->bus) || !bridge) + { + return; + } + + rt_pci_read_config_u32(bridge, bridge->pcie_cap + PCIER_DEVICE_CAP2, &cap); + if (!(cap & PCIEM_CAP2_ARI)) + { + return; + } + + rt_pci_read_config_u32(bridge, bridge->pcie_cap + PCIER_DEVICE_CTL2, &ctl2_ari); + + if (rt_pci_find_ext_capability(pdev, PCIZ_ARI)) + { + ctl2_ari |= PCIEM_CTL2_ARI; + bridge->ari_enabled = RT_TRUE; + } + else + { + ctl2_ari &= ~PCIEM_CTL2_ARI; + bridge->ari_enabled = RT_FALSE; + } + + rt_pci_write_config_u32(bridge, bridge->pcie_cap + PCIER_DEVICE_CTL2, ctl2_ari); +} + +static rt_uint16_t pci_cfg_space_size_ext(struct rt_pci_device *pdev) +{ + rt_uint32_t status; + + if (rt_pci_read_config_u32(pdev, PCI_REGMAX + 1, &status)) + { + return PCI_REGMAX + 1; + } + + return PCIE_REGMAX + 1; +} + +static rt_uint16_t pci_cfg_space_size(struct rt_pci_device *pdev) +{ + int pos; + rt_uint32_t status; + rt_uint16_t class = pdev->class >> 8; + + if (class == PCIS_BRIDGE_HOST) + { + return pci_cfg_space_size_ext(pdev); + } + + if (rt_pci_is_pcie(pdev)) + { + return pci_cfg_space_size_ext(pdev); + } + + pos = rt_pci_find_capability(pdev, PCIY_PCIX); + if (!pos) + { + return PCI_REGMAX + 1; + } + + rt_pci_read_config_u32(pdev, pos + PCIXR_STATUS, &status); + if (status & (PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) + { + return pci_cfg_space_size_ext(pdev); + } + + return PCI_REGMAX + 1; +} + +static void pci_init_capabilities(struct rt_pci_device *pdev) +{ + rt_pci_pme_init(pdev); + +#ifdef RT_PCI_MSI + rt_pci_msi_init(pdev); /* Disable MSI */ + rt_pci_msix_init(pdev); /* Disable MSI-X */ +#endif + + pcie_set_port_type(pdev); + pdev->cfg_size = pci_cfg_space_size(pdev); + pci_configure_ari(pdev); + + pdev->no_msi = RT_FALSE; + pdev->msi_enabled = RT_FALSE; + pdev->msix_enabled = RT_FALSE; +} + +rt_err_t rt_pci_setup_device(struct rt_pci_device *pdev) +{ + rt_uint8_t pos; + rt_uint32_t class = 0; + struct rt_pci_host_bridge *host_bridge; + + if (!pdev) + { + return -RT_EINVAL; + } + + if (!(host_bridge = rt_pci_find_host_bridge(pdev->bus))) + { + return -RT_EINVAL; + } + + rt_pci_ofw_device_init(pdev); + + rt_pci_read_config_u32(pdev, PCIR_REVID, &class); + + pdev->revision = class & 0xff; + pdev->class = class >> 8; /* Upper 3 bytes */ + rt_pci_read_config_u8(pdev, PCIR_HDRTYPE, &pdev->hdr_type); + + /* Clear errors left from system firmware */ + rt_pci_write_config_u16(pdev, PCIR_STATUS, 0xffff); + + if (pdev->hdr_type & 0x80) + { + pdev->multi_function = RT_TRUE; + } + pdev->hdr_type &= PCIM_HDRTYPE; + + if (pci_intx_mask_broken(pdev)) + { + pdev->broken_intx_masking = RT_TRUE; + } + + rt_dm_dev_set_name(&pdev->parent, "%04x:%02x:%02x.%u", rt_pci_domain(pdev), + pdev->bus->number, RT_PCI_SLOT(pdev->devfn), RT_PCI_FUNC(pdev->devfn)); + + switch (pdev->hdr_type) + { + case PCIM_HDRTYPE_NORMAL: + if (class == PCIS_BRIDGE_PCI) + { + goto error; + } + pci_read_irq(pdev); + rt_pci_device_alloc_resource(host_bridge, pdev); + rt_pci_read_config_u16(pdev, PCIR_SUBVEND_0, &pdev->subsystem_vendor); + rt_pci_read_config_u16(pdev, PCIR_SUBDEV_0, &pdev->subsystem_device); + break; + + case PCIM_HDRTYPE_BRIDGE: + pci_read_irq(pdev); + rt_pci_device_alloc_resource(host_bridge, pdev); + pos = rt_pci_find_capability(pdev, PCIY_SUBVENDOR); + if (pos) + { + rt_pci_read_config_u16(pdev, PCIR_SUBVENDCAP, &pdev->subsystem_vendor); + rt_pci_read_config_u16(pdev, PCIR_SUBDEVCAP, &pdev->subsystem_device); + } + break; + + case PCIM_HDRTYPE_CARDBUS: + if (class != PCIS_BRIDGE_CARDBUS) + { + goto error; + } + pci_read_irq(pdev); + rt_pci_device_alloc_resource(host_bridge, pdev); + rt_pci_read_config_u16(pdev, PCIR_SUBVEND_2, &pdev->subsystem_vendor); + rt_pci_read_config_u16(pdev, PCIR_SUBDEV_2, &pdev->subsystem_device); + break; + + default: + LOG_E("Ignoring device unknown header type %02x", pdev->hdr_type); + return -RT_EIO; + + error: + LOG_E("Ignoring class %08x (doesn't match header type %02x)", pdev->class, pdev->hdr_type); + pdev->class = PCIC_NOT_DEFINED << 8; + } + + pci_init_capabilities(pdev); + + if (rt_pci_is_pcie(pdev)) + { + rt_pci_read_config_u16(pdev, pdev->pcie_cap + PCIER_FLAGS, &pdev->exp_flags); + } + + return RT_EOK; +} + +static struct rt_pci_bus *pci_alloc_bus(struct rt_pci_bus *parent); + +static rt_err_t pci_child_bus_init(struct rt_pci_bus *bus, rt_uint32_t bus_no, + struct rt_pci_host_bridge *host_bridge, struct rt_pci_device *pdev) +{ + rt_err_t err; + struct rt_pci_bus *parent_bus = bus->parent; + + bus->sysdata = parent_bus->sysdata; + bus->self = pdev; + bus->ops = host_bridge->child_ops ? : parent_bus->ops; + + bus->number = bus_no; + rt_sprintf(bus->name, "%04x:%02x", host_bridge->domain, bus_no); + + rt_pci_ofw_bus_init(bus); + + if (bus->ops->add) + { + if ((err = bus->ops->add(bus))) + { + rt_pci_ofw_bus_free(bus); + + LOG_E("PCI-Bus<%s> add bus failed with err = %s", + bus->name, rt_strerror(err)); + + return err; + } + } + + return RT_EOK; +} + +static rt_bool_t pci_ea_fixed_busnrs(struct rt_pci_device *pdev, + rt_uint8_t *sec, rt_uint8_t *sub) +{ + int pos, offset; + rt_uint32_t dw; + rt_uint8_t ea_sec, ea_sub; + + pos = rt_pci_find_capability(pdev, PCIY_EA); + if (!pos) + { + return RT_FALSE; + } + + offset = pos + PCIR_EA_FIRST_ENT; + rt_pci_read_config_u32(pdev, offset, &dw); + ea_sec = PCIM_EA_SEC_NR(dw); + ea_sub = PCIM_EA_SUB_NR(dw); + if (ea_sec == 0 || ea_sub < ea_sec) + { + return RT_FALSE; + } + + *sec = ea_sec; + *sub = ea_sub; + + return RT_TRUE; +} + +static void pcie_fixup_link(struct rt_pci_device *pdev) +{ + int pos = pdev->pcie_cap; + rt_uint16_t exp_lnkctl, exp_lnkctl2, exp_lnksta; + rt_uint16_t exp_type = pdev->exp_flags & PCIEM_FLAGS_TYPE; + + if ((pdev->exp_flags & PCIEM_FLAGS_VERSION) < 2) + { + return; + } + + if (exp_type != PCIEM_TYPE_ROOT_PORT && + exp_type != PCIEM_TYPE_DOWNSTREAM_PORT && + exp_type != PCIEM_TYPE_PCIE_BRIDGE) + { + return; + } + + rt_pci_read_config_u16(pdev, pos + PCIER_LINK_CTL, &exp_lnkctl); + rt_pci_read_config_u16(pdev, pos + PCIER_LINK_CTL2, &exp_lnkctl2); + + rt_pci_write_config_u16(pdev, pos + PCIER_LINK_CTL2, + (exp_lnkctl2 & ~PCIEM_LNKCTL2_TLS) | PCIEM_LNKCTL2_TLS_2_5GT); + rt_pci_write_config_u16(pdev, pos + PCIER_LINK_CTL, + exp_lnkctl | PCIEM_LINK_CTL_RETRAIN_LINK); + + for (int i = 0; i < 20; ++i) + { + rt_pci_read_config_u16(pdev, pos + PCIER_LINK_STA, &exp_lnksta); + + if (!!(exp_lnksta & PCIEM_LINK_STA_DL_ACTIVE)) + { + goto _status_sync; + } + + rt_thread_mdelay(10); + } + + /* Fail, restore */ + rt_pci_write_config_u16(pdev, pos + PCIER_LINK_CTL2, exp_lnkctl2); + rt_pci_write_config_u16(pdev, pos + PCIER_LINK_CTL, + exp_lnkctl | PCIEM_LINK_CTL_RETRAIN_LINK); + +_status_sync: + /* Wait a while for success or failure */ + rt_thread_mdelay(100); +} + +static rt_uint32_t pci_scan_bridge_extend(struct rt_pci_bus *bus, struct rt_pci_device *pdev, + rt_uint32_t bus_no_start, rt_uint32_t buses, rt_bool_t reconfigured) +{ + rt_bool_t fixed_buses; + rt_uint8_t fixed_sub, fixed_sec; + rt_uint8_t primary, secondary, subordinate; + rt_uint32_t value, bus_no = bus_no_start; + struct rt_pci_bus *next_bus; + struct rt_pci_host_bridge *host_bridge; + + /* We not supported init CardBus, it always used in the PC servers. */ + if (pdev->hdr_type == PCIM_HDRTYPE_CARDBUS) + { + LOG_E("CardBus is not supported in system"); + + goto _end; + } + + rt_pci_read_config_u32(pdev, PCIR_PRIBUS_1, &value); + primary = value & 0xff; + secondary = (value >> 8) & 0xff; + subordinate = (value >> 16) & 0xff; + + if (primary == bus->number && bus->number > secondary && secondary > subordinate) + { + if (!reconfigured) + { + goto _end; + } + + LOG_I("Bridge configuration: primary(%02x) secondary(%02x) subordinate(%02x)", + primary, secondary, subordinate); + } + + if (pdev->pcie_cap) + { + pcie_fixup_link(pdev); + } + + ++bus_no; + /* Count of subordinate */ + buses -= !!buses; + + host_bridge = rt_pci_find_host_bridge(bus); + RT_ASSERT(host_bridge != RT_NULL); + + /* Clear errors */ + rt_pci_write_config_u16(pdev, PCIR_STATUS, RT_UINT16_MAX); + + fixed_buses = pci_ea_fixed_busnrs(pdev, &fixed_sec, &fixed_sub); + + if (!(next_bus = pci_alloc_bus(bus))) + { + goto _end; + } + + /* Clear bus info */ + rt_pci_write_config_u32(pdev, PCIR_PRIBUS_1, value & ~0xffffff); + + if (!(next_bus = pci_alloc_bus(bus))) + { + LOG_E("Alloc bus(%02x) fail", bus_no); + goto _end; + } + + if (pci_child_bus_init(next_bus, bus_no, host_bridge, pdev)) + { + goto _end; + } + + /* Fill primary, secondary */ + value = (buses & 0xff000000) | (bus->number << 0) | (next_bus->number << 8); + rt_pci_write_config_u32(pdev, PCIR_PRIBUS_1, value); + + bus_no = rt_pci_scan_child_buses(next_bus, buses); + + /* Fill subordinate */ + value |= next_bus->number + rt_list_len(&next_bus->children_nodes); + rt_pci_write_config_u32(pdev, PCIR_PRIBUS_1, value); + + if (fixed_buses) + { + bus_no = fixed_sub; + } + rt_pci_write_config_u8(pdev, PCIR_SUBBUS_1, bus_no); + +_end: + return bus_no; +} + +rt_uint32_t rt_pci_scan_bridge(struct rt_pci_bus *bus, struct rt_pci_device *pdev, + rt_uint32_t bus_no_start, rt_bool_t reconfigured) +{ + if (!bus || !pdev) + { + return RT_UINT32_MAX; + } + + return pci_scan_bridge_extend(bus, pdev, bus_no_start, 0, reconfigured); +} + +rt_inline rt_bool_t only_one_child(struct rt_pci_bus *bus) +{ + struct rt_pci_device *pdev; + + if (rt_pci_is_root_bus(bus)) + { + return RT_FALSE; + } + + pdev = bus->self; + + if (rt_pci_is_pcie(pdev)) + { + rt_uint16_t exp_type = pdev->exp_flags & PCIEM_FLAGS_TYPE; + + if (exp_type == PCIEM_TYPE_ROOT_PORT || + exp_type == PCIEM_TYPE_DOWNSTREAM_PORT || + exp_type == PCIEM_TYPE_PCIE_BRIDGE) + { + return RT_TRUE; + } + } + + return RT_FALSE; +} + +static int next_fn(struct rt_pci_bus *bus, struct rt_pci_device *pdev, int fn) +{ + if (!rt_pci_is_root_bus(bus) && bus->self->ari_enabled) + { + int pos, next_fn; + rt_uint16_t cap = 0; + + if (!pdev) + { + return -RT_EINVAL; + } + + pos = rt_pci_find_ext_capability(pdev, PCIZ_ARI); + + if (!pos) + { + return -RT_EINVAL; + } + + rt_pci_read_config_u16(pdev, pos + PCIR_ARI_CAP, &cap); + next_fn = PCIM_ARI_CAP_NFN(cap); + + if (next_fn <= fn) + { + return -RT_EINVAL; + } + + return next_fn; + } + + if (fn >= RT_PCI_FUNCTION_MAX - 1) + { + return -RT_EINVAL; + } + + if (pdev && !pdev->multi_function) + { + return -RT_EINVAL; + } + + return fn + 1; +} + +rt_size_t rt_pci_scan_slot(struct rt_pci_bus *bus, rt_uint32_t devfn) +{ + rt_size_t nr = 0; + struct rt_pci_device *pdev = RT_NULL; + + if (!bus) + { + return nr; + } + + if (devfn > 0 && only_one_child(bus)) + { + return nr; + } + + for (int func = 0; func >= 0; func = next_fn(bus, pdev, func)) + { + pdev = rt_pci_scan_single_device(bus, devfn + func); + + if (pdev) + { + ++nr; + + if (func > 0) + { + pdev->multi_function = RT_TRUE; + } + } + else if (func == 0) + { + break; + } + } + + return nr; +} + +rt_uint32_t rt_pci_scan_child_buses(struct rt_pci_bus *bus, rt_size_t buses) +{ + rt_uint32_t bus_no; + struct rt_pci_device *pdev = RT_NULL; + + if (!bus) + { + bus_no = RT_UINT32_MAX; + + goto _end; + } + + bus_no = bus->number; + + for (rt_uint32_t devfn = 0; + devfn < RT_PCI_DEVFN(RT_PCI_DEVICE_MAX - 1, RT_PCI_FUNCTION_MAX - 1); + devfn += RT_PCI_FUNCTION_MAX) + { + rt_pci_scan_slot(bus, devfn); + } + + rt_pci_foreach_bridge(pdev, bus) + { + int offset; + + bus_no = pci_scan_bridge_extend(bus, pdev, bus_no, buses, RT_TRUE); + offset = bus_no - bus->number; + + if (buses > offset) + { + buses -= offset; + } + else + { + break; + } + } + +_end: + return bus_no; +} + +rt_uint32_t rt_pci_scan_child_bus(struct rt_pci_bus *bus) +{ + return rt_pci_scan_child_buses(bus, 0); +} + +static struct rt_pci_bus *pci_alloc_bus(struct rt_pci_bus *parent) +{ + struct rt_pci_bus *bus = rt_calloc(1, sizeof(*bus)); + + if (!bus) + { + return RT_NULL; + } + + bus->parent = parent; + + rt_list_init(&bus->list); + rt_list_init(&bus->children_nodes); + rt_list_init(&bus->devices_nodes); + + rt_spin_lock_init(&bus->lock); + + return bus; +} + +rt_err_t rt_pci_host_bridge_register(struct rt_pci_host_bridge *host_bridge) +{ + struct rt_pci_bus *bus = pci_alloc_bus(RT_NULL); + + if (!bus) + { + return -RT_ENOMEM; + } + + host_bridge->root_bus = bus; + + bus->sysdata = host_bridge->sysdata; + bus->host_bridge = host_bridge; + bus->ops = host_bridge->ops; + + bus->number = host_bridge->bus_range[0]; + rt_sprintf(bus->name, "%04x:%02x", host_bridge->domain, bus->number); + + if (bus->ops->add) + { + rt_err_t err = bus->ops->add(bus); + + if (err) + { + LOG_E("PCI-Bus<%s> add bus failed with err = %s", bus->name, rt_strerror(err)); + } + } + + return RT_EOK; +} + +rt_err_t rt_pci_scan_root_bus_bridge(struct rt_pci_host_bridge *host_bridge) +{ + rt_err_t err; + + if ((err = rt_pci_host_bridge_register(host_bridge))) + { + return err; + } + + rt_pci_scan_child_bus(host_bridge->root_bus); + + return err; +} + +rt_err_t rt_pci_host_bridge_probe(struct rt_pci_host_bridge *host_bridge) +{ + rt_err_t err; + + err = rt_pci_scan_root_bus_bridge(host_bridge); + + return err; +} + +static rt_bool_t pci_remove_bus_device(struct rt_pci_device *pdev, void *data) +{ + /* Bus will free if this is the last device */ + rt_bus_remove_device(&pdev->parent); + + /* To find all devices, always return false */ + return RT_FALSE; +} + +rt_err_t rt_pci_host_bridge_remove(struct rt_pci_host_bridge *host_bridge) +{ + rt_err_t err = RT_EOK; + + if (host_bridge && host_bridge->root_bus) + { + rt_pci_enum_device(host_bridge->root_bus, pci_remove_bus_device, RT_NULL); + host_bridge->root_bus = RT_NULL; + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_bus_remove(struct rt_pci_bus *bus) +{ + rt_err_t err = RT_EOK; + + if (bus) + { + spin_lock(&bus->lock); + + if (rt_list_isempty(&bus->children_nodes) && + rt_list_isempty(&bus->devices_nodes)) + { + rt_list_remove(&bus->list); + spin_unlock(&bus->lock); + + if (bus->ops->remove) + { + bus->ops->remove(bus); + } + + rt_pci_ofw_bus_free(bus); + rt_free(bus); + } + else + { + spin_unlock(&bus->lock); + + err = -RT_EBUSY; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_pci_device_remove(struct rt_pci_device *pdev) +{ + rt_err_t err = RT_EOK; + + if (pdev) + { + struct rt_pci_bus *bus = pdev->bus; + + spin_lock(&bus->lock); + + while (pdev->parent.ref_count > 1) + { + spin_unlock(&bus->lock); + + rt_thread_yield(); + + spin_lock(&bus->lock); + } + rt_list_remove(&pdev->list); + + spin_unlock(&bus->lock); + + rt_free(pdev); + } + else + { + err = -RT_EINVAL; + } + + return err; +} diff --git a/rt-thread/components/drivers/phy/Kconfig b/rt-thread/components/drivers/phy/Kconfig index bb88a41..92dcba8 100644 --- a/rt-thread/components/drivers/phy/Kconfig +++ b/rt-thread/components/drivers/phy/Kconfig @@ -1,3 +1,8 @@ config RT_USING_PHY bool "Using ethernet phy device drivers" default n + +config RT_USING_PHY_V2 + bool "Using phy device and mii bus v2" + depends on !RT_USING_PHY + default n diff --git a/rt-thread/components/drivers/phy/SConscript b/rt-thread/components/drivers/phy/SConscript index 5b6effc..ba227c7 100644 --- a/rt-thread/components/drivers/phy/SConscript +++ b/rt-thread/components/drivers/phy/SConscript @@ -1,8 +1,18 @@ from building import * cwd = GetCurrentDir() +CPPPATH = [cwd, cwd + '/../include'] src = Glob('*.c') -CPPPATH = [cwd + '/../include'] -group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_PHY'], CPPPATH = CPPPATH) +if GetDepend('RT_USING_OFW') == False: + SrcRemove(src, ['ofw.c']) + +if GetDepend('RT_USING_PHY_V2') == False: + SrcRemove(src, ['general.c','mdio.c','ofw.c']) + +if GetDepend('RT_USING_PHY_V2') == False: + if GetDepend('RT_USING_PHY') == False: + SrcRemove(src, ['phy.c']) + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/rt-thread/components/drivers/phy/general.c b/rt-thread/components/drivers/phy/general.c new file mode 100644 index 0000000..969c38c --- /dev/null +++ b/rt-thread/components/drivers/phy/general.c @@ -0,0 +1,349 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-10-08 zhujiale the first version + */ +#include +#include +#include "general_phy.h" +#define DBG_TAG "rtdm.phy" +#define DBG_LVL DBG_INFO +#include + +static int __genphy_set_adv(int adv,int advertise) +{ + adv &= ~(RT_ADVERTISE_ALL | RT_ADVERTISE_100BASE4 | RT_ADVERTISE_PAUSE_CAP | + RT_ADVERTISE_PAUSE_ASYM); + if (advertise & RT_ADVERTISED__10baseT_Half) + adv |= RT_ADVERTISE_10HALF; + if (advertise & RT_ADVERTISED__10baseT_Full) + adv |= RT_ADVERTISE_10FULL; + if (advertise & RT_ADVERTISED__100baseT_Half) + adv |= RT_ADVERTISE_100HALF; + if (advertise & RT_ADVERTISED__100baseT_Full) + adv |= RT_ADVERTISE_100FULL; + if (advertise & RT_ADVERTISED__Pause) + adv |= RT_ADVERTISE_PAUSE_CAP; + if (advertise & RT_ADVERTISED__Asym_Pause) + adv |= RT_ADVERTISE_PAUSE_ASYM; + if (advertise & RT_ADVERTISED__1000baseX_Half) + adv |= RT_ADVERTISE_1000XHALF; + if (advertise & RT_ADVERTISED__1000baseX_Full) + adv |= RT_ADVERTISE_1000XFULL; + + return adv; +} +static int __genphy_config_advert(struct rt_phy_device *phydev) +{ + rt_uint32_t advertise; + int oldadv, adv, bmsr; + int err, changed = 0; + + phydev->advertising &= phydev->supported; + advertise = phydev->advertising; + + adv = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_ADVERTISE); + oldadv = adv; + + if (adv < 0) + return adv; + + adv = __genphy_set_adv(adv, advertise); + + if (adv != oldadv) + { + err = rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_ADVERTISE, adv); + + if (err < 0) + return err; + changed = 1; + } + + bmsr = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_BMSR); + if (bmsr < 0) + return bmsr; + + if (!(bmsr & RT_BMSR_ESTATEN)) + return changed; + + adv = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_CTRL1000); + oldadv = adv; + + if (adv < 0) + return adv; + + adv &= ~(RT_ADVERTISE_1000FULL | RT_ADVERTISE_1000HALF); + + if (phydev->supported & (RT_SUPPORTED_1000baseT_Half | + RT_SUPPORTED_1000baseT_Full)) + { + if (advertise & RT_SUPPORTED_1000baseT_Half) + adv |= RT_ADVERTISE_1000HALF; + if (advertise & RT_SUPPORTED_1000baseT_Full) + adv |= RT_ADVERTISE_1000FULL; + } + + if (adv != oldadv) + changed = 1; + + err = rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_CTRL1000, adv); + if (err < 0) + return err; + + return changed; +} + +int __genphy_restart_aneg(struct rt_phy_device *phydev) +{ + int ctl; + + ctl = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_BMCR); + + if (ctl < 0) + return ctl; + + ctl |= (RT_BMCR_ANENABLE | RT_BMCR_ANRESTART); + + ctl &= ~(RT_BMCR_ISOLATE); + + ctl = rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_BMCR, ctl); + + return ctl; +} + +int rt_genphy_config_aneg(struct rt_phy_device *phydev) +{ + int result; + int err; + int ctl = RT_BMCR_ANRESTART; + if (phydev->autoneg != AUTONEG_ENABLE) + { + phydev->pause = 0; + + if (phydev->speed == SPEED_1000) + ctl |= RT_BMCR_SPEED1000; + else if (phydev->speed == SPEED_100) + ctl |= RT_BMCR_SPEED100; + + if (phydev->duplex == DUPLEX_FULL) + ctl |= RT_BMCR_FULLDPLX; + + err = rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_BMCR, ctl); + + return err; + } + + result = __genphy_config_advert(phydev); + + if (result < 0) + return result; + + if (result == 0) + { + int ctl = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_BMCR); + + if (ctl < 0) + return ctl; + + if (!(ctl & RT_BMCR_ANENABLE) || (ctl & RT_BMCR_ISOLATE)) + result = 1; + } + + if (result > 0) + result = __genphy_restart_aneg(phydev); + + return result; +} + +int rt_genphy_update_link(struct rt_phy_device *phydev) +{ + unsigned int mii_reg; + + mii_reg = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_BMSR); + + if (phydev->link && mii_reg & RT_BMSR_LSTATUS) + return 0; + + if ((phydev->autoneg == AUTONEG_ENABLE) && + !(mii_reg & RT_BMSR_ANEGCOMPLETE)) + { + int i = 0; + rt_kprintf("Waiting for PHY auto negotiation to complete"); + while (!(mii_reg & RT_BMSR_ANEGCOMPLETE)) + { + + if (i > (RT_PHY_ANEG_TIMEOUT)) + { + LOG_E(" TIMEOUT !\n"); + phydev->link = 0; + return -ETIMEDOUT; + } + + mii_reg = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_BMSR); + + rt_thread_delay(100); + } + LOG_D(" done\n"); + phydev->link = 1; + } else { + mii_reg = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_BMSR); + + if (mii_reg & RT_BMSR_LSTATUS) + phydev->link = 1; + else + phydev->link = 0; + } + + return 0; +} + +static void __genphy_auto_neg(struct rt_phy_device *phydev,int mii_reg) +{ + rt_uint32_t lpa = 0; + int gblpa = 0; + rt_uint32_t estatus = 0; + + if (phydev->supported & (RT_SUPPORTED_1000baseT_Full | + RT_SUPPORTED_1000baseT_Half)) + { + + gblpa = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_STAT1000); + if (gblpa < 0) + { + LOG_D("Could not read RT_MII_STAT1000. Ignoring gigabit capability\n"); + gblpa = 0; + } + gblpa &= rt_phy_read(phydev, + RT_MDIO_DEVAD_NONE, RT_MII_CTRL1000) << 2; + } + + phydev->speed = SPEED_10; + phydev->duplex = DUPLEX_HALF; + + if (gblpa & (RT_PHY_1000BTSR_1000FD | RT_PHY_1000BTSR_1000HD)) + { + phydev->speed = SPEED_1000; + + if (gblpa & RT_PHY_1000BTSR_1000FD) + phydev->duplex = DUPLEX_FULL; + + return ; + } + + lpa = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_ADVERTISE); + lpa &= rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_LPA); + + if (lpa & (RT_LINK_PARTNER__100FULL | RT_LINK_PARTNER__100HALF)) + { + phydev->speed = SPEED_100; + + if (lpa & RT_LINK_PARTNER__100FULL) + phydev->duplex = DUPLEX_FULL; + + } else if (lpa & RT_LINK_PARTNER__10FULL) + { + phydev->duplex = DUPLEX_FULL; + } + + if ((mii_reg & RT_BMSR_ESTATEN) && !(mii_reg & RT_BMSR_ERCAP)) + estatus = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, + RT_MII_ESTATUS); + + if (estatus & (RT_SUPORT_1000B_XFULL | RT_SUPORT_1000B_XHALF | + RT_SUPORT_1000B_TFULL | RT_SUPORT_1000B_THALF)) + { + phydev->speed = SPEED_1000; + if (estatus & (RT_SUPORT_1000B_XFULL | RT_SUPORT_1000B_TFULL)) + phydev->duplex = DUPLEX_FULL; + } +} +int rt_genphy_parse_link(struct rt_phy_device *phydev) +{ + int mii_reg = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_BMSR); + + if (phydev->autoneg == AUTONEG_ENABLE) + { + __genphy_auto_neg(phydev, mii_reg); + } else { + rt_uint32_t bmcr = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_BMCR); + + phydev->speed = SPEED_10; + phydev->duplex = DUPLEX_HALF; + + if (bmcr & RT_BMCR_FULLDPLX) + phydev->duplex = DUPLEX_FULL; + + if (bmcr & RT_BMCR_SPEED1000) + phydev->speed = SPEED_1000; + else if (bmcr & RT_BMCR_SPEED100) + phydev->speed = SPEED_100; + } + + return 0; +} + +int rt_genphy_config(struct rt_phy_device *phydev) +{ + int val; + rt_uint32_t features; + + features = (RT_SUPPORTED_TP | RT_SUPPORTED_MII + | RT_SUPPORTED_AUI | RT_SUPPORTED_FIBRE | + RT_SUPPORTED_BNC); + + val = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_BMSR); + + if (val < 0) + return val; + + if (val & RT_BMSR_ANEGCAPABLE) + features |= RT_SUPPORTED_Autoneg; + + if (val & RT_BMSR_100FULL) + features |= RT_SUPPORTED_100baseT_Full; + if (val & RT_BMSR_100HALF) + features |= RT_SUPPORTED_100baseT_Half; + if (val & RT_BMSR_10FULL) + features |= RT_SUPPORTED_10baseT_Full; + if (val & RT_BMSR_10HALF) + features |= RT_SUPPORTED_10baseT_Half; + + if (val & RT_BMSR_ESTATEN) + { + val = rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_ESTATUS); + + if (val < 0) + return val; + + if (val & RT_SUPORT_1000B_TFULL) + features |= RT_SUPPORTED_1000baseT_Full; + if (val & RT_SUPORT_1000B_THALF) + features |= RT_SUPPORTED_1000baseT_Half; + if (val & RT_SUPORT_1000B_XFULL) + features |= RT_SUPPORTED_1000baseX_Full; + if (val & RT_SUPORT_1000B_XHALF) + features |= RT_SUPPORTED_1000baseX_Half; + } + + phydev->supported &= features; + phydev->advertising &= features; + + rt_genphy_config_aneg(phydev); + + return 0; +} + +int rt_genphy_startup(struct rt_phy_device *phydev) +{ + int ret; + + ret = rt_genphy_update_link(phydev); + if (ret) + return ret; + + return rt_genphy_parse_link(phydev); +} diff --git a/rt-thread/components/drivers/phy/general_phy.h b/rt-thread/components/drivers/phy/general_phy.h new file mode 100644 index 0000000..37acb3e --- /dev/null +++ b/rt-thread/components/drivers/phy/general_phy.h @@ -0,0 +1,143 @@ + +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-10-08 zhujiale the first version + */ +#ifndef __PHY_GENERAL_H__ +#define __PHY_GENERAL_H__ +/* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */ +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_10000 10000 +/* Advertisement control register. */ +#define RT_ADVERTISE_SLCT 0x001f /* Selector bits */ +#define RT_ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define RT_ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define RT_ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ +#define RT_ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define RT_ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ +#define RT_ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define RT_ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ +#define RT_ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define RT_ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ +#define RT_ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define RT_ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ +#define RT_ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ +#define RT_ADVERTISE_RESV 0x1000 /* Unused... */ +#define RT_ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define RT_ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define RT_ADVERTISE_NPAGE 0x8000 /* Next page bit */ + +#define RT_ADVERTISE_FULL (RT_ADVERTISE_100FULL | RT_ADVERTISE_10FULL | \ + RT_ADVERTISE_CSMA) +#define RT_ADVERTISE_ALL (RT_ADVERTISE_10HALF | RT_ADVERTISE_10FULL | \ + RT_ADVERTISE_100HALF | RT_ADVERTISE_100FULL) + +/* Indicates what features are advertised by the interface. */ +#define RT_ADVERTISED__10baseT_Half (1 << 0) +#define RT_ADVERTISED__10baseT_Full (1 << 1) +#define RT_ADVERTISED__100baseT_Half (1 << 2) +#define RT_ADVERTISED__100baseT_Full (1 << 3) +#define RT_ADVERTISED__1000baseT_Half (1 << 4) +#define RT_ADVERTISED__1000baseT_Full (1 << 5) +#define RT_ADVERTISED__Autoneg (1 << 6) +#define RT_ADVERTISED__TP (1 << 7) +#define RT_ADVERTISED__AUI (1 << 8) +#define RT_ADVERTISED__MII (1 << 9) +#define RT_ADVERTISED__FIBRE (1 << 10) +#define RT_ADVERTISED__BNC (1 << 11) +#define RT_ADVERTISED__10000baseT_Full (1 << 12) +#define RT_ADVERTISED__Pause (1 << 13) +#define RT_ADVERTISED__Asym_Pause (1 << 14) +#define RT_ADVERTISED__2500baseX_Full (1 << 15) +#define RT_ADVERTISED__Backplane (1 << 16) +#define RT_ADVERTISED__1000baseKX_Full (1 << 17) +#define RT_ADVERTISED__10000baseKX4_Full (1 << 18) +#define RT_ADVERTISED__10000baseKR_Full (1 << 19) +#define RT_ADVERTISED__10000baseR_FEC (1 << 20) +#define RT_ADVERTISED__1000baseX_Half (1 << 21) +#define RT_ADVERTISED__1000baseX_Full (1 << 22) + +/* Basic mode status register. */ +#define RT_BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define RT_BMSR_JCD 0x0002 /* Jabber detected */ +#define RT_BMSR_LSTATUS 0x0004 /* Link status */ +#define RT_BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define RT_BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define RT_BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define RT_BMSR_RESV 0x00c0 /* Unused... */ +#define RT_BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define RT_BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ +#define RT_BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ +#define RT_BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define RT_BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define RT_BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define RT_BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define RT_BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ +/* 1000BASE-T Control register */ +#define RT_ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ +#define RT_ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ +#define CTL1000_AS_MASTER 0x0800 +#define CTL1000_ENABLE_MASTER 0x1000 + +/* Duplex, half or full. */ +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 + +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 +#define RT_PHY_1000BTSR_MSCF 0x8000 +#define RT_PHY_1000BTSR_MSCR 0x4000 +#define RT_PHY_1000BTSR_LRS 0x2000 +#define RT_PHY_1000BTSR_RRS 0x1000 +#define RT_PHY_1000BTSR_1000FD 0x0800 +#define RT_PHY_1000BTSR_1000HD 0x0400 + +/* Link partner ability register. */ +#define RT_LINK_PARTNER__SLCT 0x001f /* Same as advertise selector */ +#define RT_LINK_PARTNER__10HALF 0x0020 /* Can do 10mbps half-duplex */ +#define RT_LINK_PARTNER__1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ +#define RT_LINK_PARTNER__10FULL 0x0040 /* Can do 10mbps full-duplex */ +#define RT_LINK_PARTNER__1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ +#define RT_LINK_PARTNER__100HALF 0x0080 /* Can do 100mbps half-duplex */ +#define RT_LINK_PARTNER__1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ +#define RT_LINK_PARTNER__100FULL 0x0100 /* Can do 100mbps full-duplex */ +#define RT_LINK_PARTNER__1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/ +#define RT_LINK_PARTNER__100BASE4 0x0200 /* Can do 100mbps 4k packets */ +#define RT_LINK_PARTNER__PAUSE_CAP 0x0400 /* Can pause */ +#define RT_LINK_PARTNER__PAUSE_ASYM 0x0800 /* Can pause asymetrically */ +#define RT_LINK_PARTNER__RESV 0x1000 /* Unused... */ +#define RT_LINK_PARTNER__RFAULT 0x2000 /* Link partner faulted */ +#define RT_LINK_PARTNER__LPACK 0x4000 /* Link partner acked us */ +#define RT_LINK_PARTNER__NPAGE 0x8000 /* Next page bit */ + +#define RT_LINK_PARTNER__DUPLEX (RT_LINK_PARTNER__10FULL | RT_LINK_PARTNER__100FULL) +#define RT_LINK_PARTNER__100 (RT_LINK_PARTNER__100FULL | RT_LINK_PARTNER__100HALF | RT_LINK_PARTNER__100BASE4) +/* Expansion register for auto-negotiation. */ +#define RT_EXPANSION_REG_NWAY 0x0001 /* Can do N-way auto-nego */ +#define RT_EXPANSION_REG_LCWP 0x0002 /* Got new RX page code word */ +#define RT_EXPANSION_REG_ENABLENPAGE 0x0004 /* This enables npage words */ +#define RT_EXPANSION_REG_NPCAPABLE 0x0008 /* Link partner supports npage */ +#define RT_EXPANSION_REG_MFAULTS 0x0010 /* Multiple faults detected */ +#define RT_EXPANSION_REG_RESV 0xffe0 /* Unused... */ + +#define RT_SUPORT_1000B_XFULL 0x8000 /* Can do 1000BX Full */ +#define RT_SUPORT_1000B_XHALF 0x4000 /* Can do 1000BX Half */ +#define RT_SUPORT_1000B_TFULL 0x2000 /* Can do 1000BT Full */ +#define RT_SUPORT_1000B_THALF 0x1000 /* Can do 1000BT Half */ +#define RT_PHY_ANEG_TIMEOUT 4000 +struct rt_phy_device; + +int rt_genphy_parse_link(struct rt_phy_device *phydev); +int rt_genphy_config_aneg(struct rt_phy_device *phydev); +int rt_genphy_update_link(struct rt_phy_device *phydev); +int rt_genphy_startup(struct rt_phy_device *phydev); +int rt_genphy_config(struct rt_phy_device *phydev); +#endif diff --git a/rt-thread/components/drivers/phy/mdio.c b/rt-thread/components/drivers/phy/mdio.c new file mode 100644 index 0000000..7f9be35 --- /dev/null +++ b/rt-thread/components/drivers/phy/mdio.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-10-08 zhujiale the first version + */ +#include "mdio.h" + +static struct rt_list_node mdio_list; + +struct mii_bus *rt_mdio_get_bus_by_name(const char *busname) +{ + struct rt_list_node *entry; + struct mii_bus *bus; + + if (!busname) + { + rt_kprintf("NULL bus name!\n"); + return RT_NULL; + } + + rt_list_for_each(entry, &mdio_list) + { + bus = rt_container_of(entry, struct mii_bus, node); + if (!strcmp(bus->name, busname)) + return bus; + } + + return RT_NULL; +} + +struct mii_bus *rt_mdio_alloc(void) +{ + struct mii_bus *mii; + mii = rt_malloc(sizeof(struct mii_bus)); + if (!mii) + return RT_NULL; + + rt_list_init(&mii->node); + return mii; +} + +rt_err_t rt_mdio_register(struct mii_bus *bus) +{ + if (!bus) + return -RT_ERROR; + + if(rt_mdio_get_bus_by_name(bus->name)) + { + rt_kprintf("mdio bus %s already exist!\n", bus->name); + return -RT_ERROR; + } + + rt_list_insert_before(&mdio_list, &bus->node); + return RT_EOK; +} + +rt_err_t rt_mdio_unregister(struct mii_bus *bus) +{ + if (!bus) + return -RT_ERROR; + + rt_list_remove(&bus->node); + return RT_EOK; +} + +static int mdio_init(void) +{ + rt_list_init(&mdio_list); + return 0; +} +INIT_CORE_EXPORT(mdio_init); diff --git a/rt-thread/components/drivers/phy/mdio.h b/rt-thread/components/drivers/phy/mdio.h new file mode 100644 index 0000000..89e98d4 --- /dev/null +++ b/rt-thread/components/drivers/phy/mdio.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-10-08 zhujiale the first version + */ +#ifndef __PHY_MDIO_H__ +#define __PHY_MDIO_H__ +#include +#include + +#define RT_MDIO_DEVAD_NONE (-1) +#define RT_MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/ + * Physical Medium Dependent */ +#define RT_MDIO_MMD_WIS 2 /* WAN Interface Sublayer */ +#define RT_MDIO_MMD_PCS 3 /* Physical Coding Sublayer */ +#define RT_MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */ +#define RT_MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */ +#define RT_MDIO_MMD_TC 6 /* Transmission Convergence */ +#define RT_MDIO_MMD_AN 7 /* Auto-Negotiation */ +#define RT_MDIO_MMD_C22EXT 29 /* Clause 22 extension */ +#define RT_MDIO_MMD_VEND1 30 /* Vendor specific 1 */ +#define RT_MDIO_MMD_VEND2 31 /* Vendor specific 2 */ + +#define RT_MII_BMCR 0x00 /* Basic mode control register */ +#define RT_MII_BMSR 0x01 /* Basic mode status register */ +#define RT_MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define RT_MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define RT_MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define RT_MII_LPA 0x05 /* Link partner ability reg */ +#define RT_MII_EXPANSION 0x06 /* Expansion register */ +#define RT_MII_CTRL1000 0x09 /* 1000BASE-T control */ +#define RT_MII_STAT1000 0x0a /* 1000BASE-T status */ +#define RT_MII_MMD_CTRL 0x0d /* MMD Access Control Register */ +#define RT_MII_MMD_DATA 0x0e /* MMD Access Data Register */ +#define RT_MII_ESTATUS 0x0f /* Extended Status */ +#define RT_MII_DCOUNTER 0x12 /* Disconnect counter */ +#define RT_MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define RT_MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ +#define RT_MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define RT_MII_SREVISION 0x16 /* Silicon revision */ +#define RT_MII_RESV1 0x17 /* Reserved... */ +#define RT_MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define RT_MII_PHYADDR 0x19 /* PHY address */ +#define RT_MII_RESV2 0x1a /* Reserved... */ +#define RT_MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define RT_MII_NCONFIG 0x1c /* Network interface config */ + +/* Basic mode control register. */ +#define RT_BMCR_RESV 0x003f /* Unused... */ +#define RT_BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define RT_BMCR_CTST 0x0080 /* Collision test */ +#define RT_BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define RT_BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define RT_BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */ +#define RT_BMCR_PDOWN 0x0800 /* Enable low power state */ +#define RT_BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define RT_BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define RT_BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define RT_BMCR_RESET 0x8000 /* Reset to default state */ +#define RT_BMCR_SPEED10 0x0000 /* Select 10Mbps */ + +#define RT_MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ +#define RT_MII_MMD_CTRL_ADDR 0x0000 /* Address */ +#define RT_MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ +#define RT_MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ +#define RT_MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ + + +#define RT_PHY_MAX 32 + +struct mii_bus +{ + struct rt_list_node node; + char name[RT_NAME_MAX]; + void* priv; + int (*read)(struct mii_bus* bus, int addr, int devad, int reg); + int (*write)(struct mii_bus* bus, int addr, int devad, int reg, rt_uint16_t val); + /** @read_c45: Perform a C45 read transfer on the bus */ + int (*read_c45)(struct mii_bus* bus, int addr, int devad, int reg); + /** @write_c45: Perform a C45 write transfer on the bus */ + int (*write_c45)(struct mii_bus* bus, int addr, int devad, int reg, rt_uint16_t val); + int (*reset)(struct mii_bus* bus); + struct rt_phy_device* phymap[RT_PHY_MAX]; + rt_uint32_t phy_mask; + int reset_delay_us; + int reset_post_delay_us; +}; + +rt_err_t rt_mdio_register(struct mii_bus* bus); +rt_err_t rt_mdio_unregister(struct mii_bus* bus); + +struct mii_bus* rt_mdio_get_bus_by_name(const char* busname); +struct mii_bus* rt_mdio_alloc(void); +#endif diff --git a/rt-thread/components/drivers/phy/ofw.c b/rt-thread/components/drivers/phy/ofw.c new file mode 100644 index 0000000..316bbc2 --- /dev/null +++ b/rt-thread/components/drivers/phy/ofw.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-09-25 zhujiale the first version + */ +#include +#include +#include +#define DBG_TAG "rtdm.phy" +#define DBG_LVL DBG_INFO +#include +#include "ofw.h" + +static const char* const rt_phy_modes[] = +{ + [RT_PHY_INTERFACE_MODE_NA] = "", + [RT_PHY_INTERFACE_MODE_INTERNAL] = "internal", + [RT_PHY_INTERFACE_MODE_MII] = "mii", + [RT_PHY_INTERFACE_MODE_GMII] = "gmii", + [RT_PHY_INTERFACE_MODE_SGMII] = "sgmii", + [RT_PHY_INTERFACE_MODE_TBI] = "tbi", + [RT_PHY_INTERFACE_MODE_REVMII] = "rev-mii", + [RT_PHY_INTERFACE_MODE_RMII] = "rmii", + [RT_PHY_INTERFACE_MODE_REVRMII] = "rev-rmii", + [RT_PHY_INTERFACE_MODE_RGMII] = "rgmii", + [RT_PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", + [RT_PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", + [RT_PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", + [RT_PHY_INTERFACE_MODE_RTBI] = "rtbi", + [RT_PHY_INTERFACE_MODE_SMII] = "smii", + [RT_PHY_INTERFACE_MODE_XGMII] = "xgmii", + [RT_PHY_INTERFACE_MODE_XLGMII] = "xlgmii", + [RT_PHY_INTERFACE_MODE_MOCA] = "moca", + [RT_PHY_INTERFACE_MODE_PSGMII] = "psgmii", + [RT_PHY_INTERFACE_MODE_QSGMII] = "qsgmii", + [RT_PHY_INTERFACE_MODE_TRGMII] = "trgmii", + [RT_PHY_INTERFACE_MODE_1000BASEX] = "1000base-x", + [RT_PHY_INTERFACE_MODE_1000BASEKX] = "1000base-kx", + [RT_PHY_INTERFACE_MODE_2500BASEX] = "2500base-x", + [RT_PHY_INTERFACE_MODE_5GBASER] = "5gbase-r", + [RT_PHY_INTERFACE_MODE_RXAUI] = "rxaui", + [RT_PHY_INTERFACE_MODE_XAUI] = "xaui", + [RT_PHY_INTERFACE_MODE_10GBASER] = "10gbase-r", + [RT_PHY_INTERFACE_MODE_25GBASER] = "25gbase-r", + [RT_PHY_INTERFACE_MODE_USXGMII] = "usxgmii", + [RT_PHY_INTERFACE_MODE_10GKR] = "10gbase-kr", + [RT_PHY_INTERFACE_MODE_100BASEX] = "100base-x", + [RT_PHY_INTERFACE_MODE_QUSGMII] = "qusgmii", + [RT_PHY_INTERFACE_MODE_MAX] = "", +}; + +static rt_err_t _get_interface_by_name(const char *name, rt_phy_interface *interface) +{ + for (int i = 0; i < RT_PHY_INTERFACE_MODE_MAX; i++) + { + if (!strcmp(name, rt_phy_modes[i])) + { + *interface = i; + return RT_EOK; + } + } + return -RT_ERROR; +} + +rt_err_t rt_ofw_get_interface(struct rt_ofw_node *np, rt_phy_interface *interface) +{ + const char *phy_mode = RT_NULL; + + if (rt_ofw_prop_read_string(np, "phy-mode", &phy_mode)) + rt_ofw_prop_read_string(np, "phy-connection-type", &phy_mode); + if (!phy_mode) + return -RT_ERROR; + + return _get_interface_by_name(phy_mode, interface); +} + +rt_err_t rt_ofw_get_mac_addr_by_name(struct rt_ofw_node *np, const char *name, rt_uint8_t *addr) +{ + rt_ssize_t len; + const void *p; + p = rt_ofw_prop_read_raw(np, name, &len); + if (p) + { + rt_memcpy(addr, p, len); + return RT_EOK; + } + + return -RT_ERROR; +} + +rt_err_t rt_ofw_get_mac_addr(struct rt_ofw_node *np, rt_uint8_t *addr) +{ + if (!rt_ofw_get_mac_addr_by_name(np, "mac-address", addr)) + return RT_EOK; + + if (!rt_ofw_get_mac_addr_by_name(np, "local-mac-address", addr)) + return RT_EOK; + + if (!rt_ofw_get_mac_addr_by_name(np, "address", addr)) + return RT_EOK; + + return -RT_ERROR; +} + +rt_err_t rt_ofw_get_phyid(struct rt_ofw_node *np,rt_uint32_t *id) +{ + const char *phy_id; + unsigned int upper, lower; + int ret; + + ret = rt_ofw_prop_read_string(np,"compatible",&phy_id); + if (ret) + return ret; + + ret = rt_sscanf(phy_id,"ethernet-phy-id%4x.%4x",&upper, &lower); + if(ret != 2) + return -RT_ERROR; + + *id = ((upper & 0xffff) << 16) | (lower & 0xffff); + return RT_EOK; + +} +struct rt_phy_device *rt_ofw_create_phy(struct mii_bus *bus,struct rt_ofw_node *np,int phyaddr) +{ + struct rt_phy_device *dev = RT_NULL; + struct rt_ofw_node *phy_node; + int ret; + rt_uint32_t id = 0xffff; + + phy_node = rt_ofw_parse_phandle(np, "phy-handle", 0); + if (!phy_node) + { + LOG_D("Failed to find phy-handle"); + return RT_NULL; + } + + ret = rt_ofw_get_phyid(np, &id); + if (ret) + { + LOG_D("Failed to read eth PHY id, err: %d\n", ret); + return RT_NULL; + } + + LOG_D("Found a PHY id: 0x%x\n", id); + + dev = rt_phy_device_create(bus, phyaddr, id, RT_FALSE); + + if(dev) + dev->node = phy_node; + + return dev; +} diff --git a/rt-thread/components/drivers/phy/ofw.h b/rt-thread/components/drivers/phy/ofw.h new file mode 100644 index 0000000..d846aa4 --- /dev/null +++ b/rt-thread/components/drivers/phy/ofw.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-09-25 zhujiale the first version + */ +#ifndef __NET_OFW_H__ +#define __NET_OFW_H__ +#include +#include +typedef enum +{ + RT_PHY_INTERFACE_MODE_NA, + RT_PHY_INTERFACE_MODE_INTERNAL, + RT_PHY_INTERFACE_MODE_MII, + RT_PHY_INTERFACE_MODE_GMII, + RT_PHY_INTERFACE_MODE_SGMII, + RT_PHY_INTERFACE_MODE_TBI, + RT_PHY_INTERFACE_MODE_REVMII, + RT_PHY_INTERFACE_MODE_RMII, + RT_PHY_INTERFACE_MODE_REVRMII, + RT_PHY_INTERFACE_MODE_RGMII, + RT_PHY_INTERFACE_MODE_RGMII_ID, + RT_PHY_INTERFACE_MODE_RGMII_RXID, + RT_PHY_INTERFACE_MODE_RGMII_TXID, + RT_PHY_INTERFACE_MODE_RTBI, + RT_PHY_INTERFACE_MODE_SMII, + RT_PHY_INTERFACE_MODE_XGMII, + RT_PHY_INTERFACE_MODE_XLGMII, + RT_PHY_INTERFACE_MODE_MOCA, + RT_PHY_INTERFACE_MODE_PSGMII, + RT_PHY_INTERFACE_MODE_QSGMII, + RT_PHY_INTERFACE_MODE_TRGMII, + RT_PHY_INTERFACE_MODE_100BASEX, + RT_PHY_INTERFACE_MODE_1000BASEX, + RT_PHY_INTERFACE_MODE_2500BASEX, + RT_PHY_INTERFACE_MODE_5GBASER, + RT_PHY_INTERFACE_MODE_RXAUI, + RT_PHY_INTERFACE_MODE_XAUI, + /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */ + RT_PHY_INTERFACE_MODE_10GBASER, + RT_PHY_INTERFACE_MODE_25GBASER, + RT_PHY_INTERFACE_MODE_USXGMII, + /* 10GBASE-KR - with Clause 73 AN */ + RT_PHY_INTERFACE_MODE_10GKR, + RT_PHY_INTERFACE_MODE_QUSGMII, + RT_PHY_INTERFACE_MODE_1000BASEKX, + RT_PHY_INTERFACE_MODE_MAX, +} rt_phy_interface; + +rt_err_t rt_ofw_get_mac_addr(struct rt_ofw_node *np, rt_uint8_t *addr); +rt_err_t rt_ofw_get_mac_addr_by_name(struct rt_ofw_node *np, const char *name, rt_uint8_t *addr); +rt_err_t rt_ofw_get_interface(struct rt_ofw_node *np, rt_phy_interface *interface); + +#endif diff --git a/rt-thread/components/drivers/phy/phy.c b/rt-thread/components/drivers/phy/phy.c index 363b483..47c35c2 100644 --- a/rt-thread/components/drivers/phy/phy.c +++ b/rt-thread/components/drivers/phy/phy.c @@ -1,22 +1,21 @@ - /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2020-09-27 wangqiang first version + * Date Author Notes + * 2020-09-27 wangqiang first version + * 2024-10-08 zhujiale add phy v2.0 */ #include #include -#include #include - -#define DBG_TAG "PHY" +#define DBG_TAG "rtdm.phy" #define DBG_LVL DBG_INFO #include +#ifdef RT_USING_PHY static rt_ssize_t phy_device_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t count) { @@ -74,3 +73,503 @@ rt_err_t rt_hw_phy_register(struct rt_phy_device *phy, const char *name) return ret; } +#endif + +#ifdef RT_USING_PHY_V2 +int rt_phy_set_supported(struct rt_phy_device *phydev, rt_uint32_t max_speed) +{ + phydev->supported &= RT_PHY_DEFAULT_FEATURES; + + switch (max_speed) + { + default: + return -ENOTSUP; + case SPEED_1000: + phydev->supported |= RT_PHY_1000BT_FEATURES; + case SPEED_100: + phydev->supported |= RT_PHY_100BT_FEATURES; + case SPEED_10: + phydev->supported |= RT_PHY_10BT_FEATURES; + } + + return 0; +} + +int rt_phy_read(struct rt_phy_device *phydev, int devad, int regnum) +{ + struct mii_bus *bus = phydev->bus; + if(phydev->is_c45) + { + if(bus->read_c45) + return bus->read_c45(bus, phydev->addr, devad, regnum); + } + + if( bus && bus->read ) + return bus->read(bus, phydev->addr, devad, regnum); + + LOG_D("no read function\n"); + return -1; +} + +int rt_phy_write(struct rt_phy_device *phydev, int devad, int regnum, rt_uint16_t val) +{ + struct mii_bus *bus = phydev->bus; + if(phydev->is_c45) + { + if(bus->write_c45) + return bus->write_c45(bus, phydev->addr, devad, regnum, val); + } + if( bus && bus->write ) + return bus->write(bus, phydev->addr, devad, regnum, val); + + LOG_D("no write function\n"); + return -1; +} + +int rt_phy_startup(struct rt_phy_device *phydev) +{ + if(!phydev->drv) + { + LOG_D("PHY device hace no driver\n"); + return -1; + } + + if (phydev->drv->startup) + return phydev->drv->startup(phydev); + + LOG_D("phy startup err\n"); + return -1; +} + +int rt_phy_config(struct rt_phy_device *phydev) +{ + if(!phydev->drv) + { + LOG_D("PHY device hace no driver\n"); + return -1; + } + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + LOG_D("no config function\n"); + return -1; +} + +int rt_phy_shutdown(struct rt_phy_device *phydev) +{ + if(!phydev->drv) + { + LOG_D("PHY device hace no driver\n"); + return -1; + } + + if (phydev->drv->shutdown) + phydev->drv->shutdown(phydev); + + LOG_D("no shutdown function\n"); + return -1; +} + +void rt_phy_mmd_start_indirect(struct rt_phy_device *phydev, int devad, int regnum) +{ + /* Write the desired MMD Devad */ + rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_MMD_DATA, regnum); + + /* Select the Function : DATA with no post increment */ + rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_MMD_CTRL, + (devad | RT_MII_MMD_CTRL_NOINCR)); +} + +int rt_phy_read_mmd(struct rt_phy_device *phydev, int devad, int regnum) +{ + struct rt_phy_driver *drv = phydev->drv; + + if (regnum > (rt_uint16_t)~0 || devad > 32 || !drv) + return -EINVAL; + + if (drv->read_mmd) + return drv->read_mmd(phydev, devad, regnum); + + if ((drv->features & RT_PHY_10G_FEATURES) == RT_PHY_10G_FEATURES || + devad == RT_MDIO_DEVAD_NONE || !devad) + return rt_phy_read(phydev, devad, regnum); + + rt_phy_mmd_start_indirect(phydev, devad, regnum); + + return rt_phy_read(phydev, RT_MDIO_DEVAD_NONE, RT_MII_MMD_DATA); +} + +int rt_phy_write_mmd(struct rt_phy_device *phydev, int devad, int regnum, rt_uint16_t val) +{ + struct rt_phy_driver *drv = phydev->drv; + + if (regnum > (rt_uint16_t)~0 || devad > 32 || !drv) + return -EINVAL; + + if (drv->write_mmd) + return drv->write_mmd(phydev, devad, regnum, val); + + if ((drv->features & RT_PHY_10G_FEATURES) == RT_PHY_10G_FEATURES || + devad == RT_MDIO_DEVAD_NONE || !devad) + return rt_phy_write(phydev, devad, regnum, val); + + rt_phy_mmd_start_indirect(phydev, devad, regnum); + + return rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_MMD_DATA, val); +} + +int rt_phy_reset(struct rt_phy_device *phydev) +{ + int reg; + int timeout = 500; + int devad = RT_MDIO_DEVAD_NONE; + + if (phydev->flags & RT_PHY_FLAG_BROKEN_RESET) + return 0; + + if (rt_phy_write(phydev, devad, RT_MII_BMCR, RT_BMCR_RESET) < 0) + { + LOG_D("PHY reset failed\n"); + return -1; + } + + reg = rt_phy_read(phydev, devad, RT_MII_BMCR); + while ((reg & RT_BMCR_RESET) && timeout--) + { + reg = rt_phy_read(phydev, devad, RT_MII_BMCR); + + if (reg < 0) + { + LOG_D("PHY status read failed\n"); + return -1; + } + rt_thread_mdelay(1); + } + + if (reg & RT_BMCR_RESET) + { + LOG_D("PHY reset timed out\n"); + return -1; + } + + return 0; +} + +static struct rt_bus rt_phy_bus; + +/** + * @brief create a phy device + * + * Creates a new PHY device based on the given bus, address, PHY ID, and whether Clause 45 is supported. + * + * @param bus the pointer to the bus + * @param addr PHY device address + * @param phy_id PHY device id + * @param is_c45 if suport Clause 45 + * + * @return if create success return the phy device pointer,else return RT_NULL + */ +struct rt_phy_device *rt_phy_device_create(struct mii_bus *bus, int addr, + rt_uint32_t phy_id, rt_bool_t is_c45) +{ + struct rt_phy_device *dev = rt_malloc(sizeof(struct rt_phy_device)); + + if (!dev) + { + LOG_E("Failed to allocate PHY device for %s:%d\n", + bus ? bus->name : "(null bus)", addr); + return RT_NULL; + } + + memset(dev, 0, sizeof(*dev)); + + dev->duplex = -1; + dev->link = 0; + dev->interface = RT_PHY_INTERFACE_MODE_NA; +#ifdef RT_USING_OFW + dev->node = RT_NULL; +#endif + dev->autoneg = RT_TRUE; + + dev->addr = addr; + dev->phy_id = phy_id; + dev->is_c45 = is_c45; + dev->bus = bus; + + if(rt_phy_device_register(dev)) + { + LOG_D("register phy device filed") + } + + if (addr >= 0 && addr < RT_PHY_MAX && phy_id != RT_PHY_FIXED_ID && + phy_id != RT_PHY_NCSI_ID) + bus->phymap[addr] = dev; + + return dev; +} + +/** + * @brief get phy id + * + * get phy id by read the register 2 and 3 of PHY device, + * Register of the MII management interface stipulates that + * register 2 contains thehigh 16 bits of the PHY’s identifier + * the register 3 contains the low 16 bits of the PHY’s identifier + * + * @param bus MII bus pointer + * @param addr PHY device address + * @param devad dev addr if be set to zero it means c22 mode,else it means c45 mode + * @param phy_id the phy id which will be read + * + * @return if read success return 0,else return -RT_EIO + */ +static int get_phy_id(struct mii_bus *bus, int addr, int devad, rt_uint32_t *phy_id) +{ + int phy_reg; + + phy_reg = bus->read(bus, addr, devad, RT_MII_PHYSID1); + + if (phy_reg < 0) + return -RT_EIO; + + *phy_id = (phy_reg & 0xffff) << 16; + + phy_reg = bus->read(bus, addr, devad, RT_MII_PHYSID2); + + if (phy_reg < 0) + return -RT_EIO; + + *phy_id |= (phy_reg & 0xffff); + + return 0; +} + +/** + * @brief create phy device by mask + * + * @param bus MII bus pointer + * @param phy_mask the mask which phy addr corresponding will be set 1 + * @param devad dev addr if be set to zero it means c22 mode,else it means c45 mode + * + * @return if create success return the phy device pointer,if create fail return NULL + */ +static struct rt_phy_device *create_phy_by_mask(struct mii_bus *bus, unsigned int phy_mask,int devad) +{ + rt_uint32_t id = 0xffffffff; + rt_bool_t is_c45; + + while (phy_mask) + { + int addr = __rt_ffs(phy_mask) - 1; + int r = get_phy_id(bus, addr, devad, &id); + + if (r == 0 && id == 0) + { + phy_mask &= ~(1 << addr); + continue; + } + + if (r == 0 && (id & 0x1fffffff) != 0x1fffffff) + { + is_c45 = (devad == RT_MDIO_DEVAD_NONE) ? RT_FALSE : RT_TRUE; + return rt_phy_device_create(bus, addr, id, is_c45); + } + + } + return RT_NULL; +} + +/** + * @brief create phy device by mask + * + * it will create phy device by c22 mode or c45 mode + * + * @param bus mii bus pointer + * @param phy_mask PHY mask it depend on the phy addr, the phy addr corresponding will be set 1 + * + * @return if create success return the phy device pointer,if create fail return NULL + */ +static struct rt_phy_device *rt_phydev_create_by_mask(struct mii_bus *bus, unsigned int phy_mask) +{ + struct rt_phy_device *phy; + /* + *The bit of devad is dev addr which is the new features in c45 + *so if devad equal to zero it means it is c22 mode ,and if not + *equal to zero it means it is c45 mode,which include PMD/PMA , + *WIS ,PCS,PHY XS,PHY XS .... + */ + int devad[] = { + /* Clause-22 */ + RT_MDIO_DEVAD_NONE, + /* Clause-45 */ + RT_MDIO_MMD_PMAPMD, + RT_MDIO_MMD_WIS, + RT_MDIO_MMD_PCS, + RT_MDIO_MMD_PHYXS, + RT_MDIO_MMD_VEND1, + }; + + for (int i = 0; i < sizeof(devad)/sizeof(devad[0]); i++) + { + phy = create_phy_by_mask(bus, phy_mask, devad[i]); + if(phy) + return phy; + } + + return RT_NULL; +} + +struct rt_phy_device *rt_phy_find_by_mask(struct mii_bus *bus, unsigned int phy_mask) +{ + struct rt_phy_device *phy; + unsigned int mask = phy_mask; + unsigned int addr; + if (bus->reset) + { + bus->reset(bus); + + rt_thread_mdelay(15); + } + + while (mask) + { + /* + *Whichever bit of the mask is the 1, + *which bit is the addr as the array subscript to search + *such as mask = 1110 ,this loop will search for subscript + *1,2,3,if the array subscript is not null then return it, + *if the array subscript is null then continue to search + */ + addr = __rt_ffs(mask) - 1; + + if (bus->phymap[addr]) + return bus->phymap[addr]; + + mask &= ~(1U << addr); + } + /*ifcan't find phy device, create a new phy device*/ + phy = rt_phydev_create_by_mask(bus, phy_mask); + + return phy; + +} + +/** + * @brief get phy device by given mii bus, node and address + * @param bus MII bus pointer + * @param np the dtb node of device which need to get phy device + * @param addr address of phy device + * @param interface interface of phy device + * + * @return phy device pointer or NULL if not found + */ +struct rt_phy_device *rt_phy_get_device(struct mii_bus *bus,struct rt_ofw_node *np, int addr,rt_phy_interface interface) +{ + struct rt_phy_device *phy = RT_NULL; + unsigned int phy_mask = addr? 1 << addr:0xffffffff; + +#ifdef RT_USING_OFW + if(np) + phy = rt_ofw_create_phy(bus,np,addr); +#endif + if(!phy) + phy = rt_phy_find_by_mask(bus,phy_mask); + + if(phy) + { + rt_phy_reset(phy); + phy->interface = interface; + return phy; + } + + LOG_D("PHY device get failed"); + return RT_NULL; +} + +static struct rt_phy_driver genphy = { + .uid = 0xffffffff, + .mask = 0xffffffff, + .name = "Generic PHY", + .features = RT_PHY_GBIT_FEATURES | RT_SUPPORTED_MII | + RT_SUPPORTED_AUI | RT_SUPPORTED_FIBRE | + RT_SUPPORTED_BNC, + .config = rt_genphy_config, + .startup = rt_genphy_startup, +}; +RT_PHY_DRIVER_REGISTER(genphy); + +rt_err_t rt_phy_device_register(struct rt_phy_device *pdev) +{ + rt_err_t err; + RT_ASSERT(pdev != RT_NULL); + err = rt_bus_add_device(&rt_phy_bus, &pdev->parent); + if (err) + { + return err; + } + if(!pdev->drv) + pdev->drv = &genphy; + + return RT_EOK; +} + +rt_err_t rt_phy_driver_register(struct rt_phy_driver *pdrv) +{ + RT_ASSERT(pdrv != RT_NULL); + + pdrv->parent.bus = &rt_phy_bus; +#if RT_NAME_MAX > 0 + rt_strcpy(pdrv->parent.parent.name, pdrv->name); +#else + pdrv->parent.parent.name = pdrv->name; +#endif + + return rt_driver_register(&pdrv->parent); +} + +static rt_bool_t phy_match(rt_driver_t drv, rt_device_t dev) +{ + struct rt_phy_device *pdev = rt_container_of(dev, struct rt_phy_device, parent); + struct rt_phy_driver *pdrv = rt_container_of(drv, struct rt_phy_driver, parent); + if ((pdrv->uid & pdrv->mask) == (pdev->phy_id & pdrv->mask)) + return RT_TRUE; + + return RT_FALSE; + +} + +static rt_err_t phy_probe(rt_device_t dev) +{ + rt_err_t err = RT_EOK; + struct rt_phy_driver *pdrv = rt_container_of(dev->drv, struct rt_phy_driver, parent); + struct rt_phy_device *pdev = rt_container_of(dev, struct rt_phy_device, parent); + pdev->drv = pdrv; + pdev->advertising = pdev->drv->features; + pdev->supported = pdev->drv->features; + + pdev->mmds = pdev->drv->mmds; + if(pdrv->probe) + err = pdrv->probe(pdev); + + return err; +} + +static struct rt_bus rt_phy_bus = +{ + .name = "phy", + .match = phy_match, + .probe = phy_probe, +}; + +static int rt_phy_bus_init(void) +{ + rt_bus_register(&rt_phy_bus); + + return 0; +} +INIT_CORE_EXPORT(rt_phy_bus_init); +#endif diff --git a/rt-thread/components/drivers/phye/Kconfig b/rt-thread/components/drivers/phye/Kconfig new file mode 100644 index 0000000..c6672ee --- /dev/null +++ b/rt-thread/components/drivers/phye/Kconfig @@ -0,0 +1,11 @@ +menuconfig RT_USING_PHYE + bool "Using External Port Physical Layer (PHY) device drivers" + depends on RT_USING_DM + default n + help + This framework will be of use only to devices that use + external PHY (PHY functionality is not embedded within the controller). + +if RT_USING_PHYE + osource "$(SOC_DM_PHYE_DIR)/Kconfig" +endif diff --git a/rt-thread/components/drivers/phye/SConscript b/rt-thread/components/drivers/phye/SConscript new file mode 100644 index 0000000..23deafe --- /dev/null +++ b/rt-thread/components/drivers/phye/SConscript @@ -0,0 +1,15 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_PHYE']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] + +src = ['phye.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/phye/phye.c b/rt-thread/components/drivers/phye/phye.c new file mode 100644 index 0000000..7dc6709 --- /dev/null +++ b/rt-thread/components/drivers/phye/phye.c @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 GuEe-GUI first version + */ + +#define DBG_TAG "rtdm.phye" +#define DBG_LVL DBG_INFO +#include + +#include +#include + +rt_err_t rt_phye_register(struct rt_phye *phye) +{ + rt_err_t err; + + if (phye && phye->dev && phye->ops) + { + err = RT_EOK; + + rt_spin_lock_init(&phye->lock); + rt_dm_dev_bind_fwdata(phye->dev, RT_NULL, phye); + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_phye_unregister(struct rt_phye *phye) +{ + rt_err_t err; + + if (phye) + { + err = RT_EOK; + + rt_spin_lock(&phye->lock); + + if (phye->dev->ref_count) + { + err = -RT_EBUSY; + LOG_E("%s is busy in unregister", rt_dm_dev_get_name(phye->dev)); + } + + rt_dm_dev_unbind_fwdata(phye->dev, RT_NULL); + + rt_spin_unlock(&phye->lock); + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t rt_phye_init(struct rt_phye *phye) +{ + rt_err_t err; + + if (!phye) + { + return RT_EOK; + } + + err = RT_EOK; + + rt_spin_lock(&phye->lock); + + if (phye->init_count == 0 && phye->ops->init) + { + if ((err = phye->ops->init(phye))) + { + goto _out_lock; + } + } + ++phye->init_count; + +_out_lock: + rt_spin_unlock(&phye->lock); + + return err; +} + +rt_err_t rt_phye_exit(struct rt_phye *phye) +{ + rt_err_t err; + + if (!phye) + { + return RT_EOK; + } + + err = RT_EOK; + + rt_spin_lock(&phye->lock); + + if (phye->init_count == 1 && phye->ops->exit) + { + if ((err = phye->ops->exit(phye))) + { + goto _out_lock; + } + } + if (phye->init_count) + { + --phye->init_count; + } + +_out_lock: + rt_spin_unlock(&phye->lock); + + return err; +} + +rt_err_t rt_phye_reset(struct rt_phye *phye) +{ + rt_err_t err; + + if (!phye) + { + return RT_EOK; + } + + err = RT_EOK; + + rt_spin_lock(&phye->lock); + + if (phye->ops->reset) + { + err = phye->ops->reset(phye); + } + + rt_spin_unlock(&phye->lock); + + return err; +} + +rt_err_t rt_phye_power_on(struct rt_phye *phye) +{ + rt_err_t err; + + if (!phye) + { + return RT_EOK; + } + + err = RT_EOK; + + rt_spin_lock(&phye->lock); + + if (phye->power_count == 0 && phye->ops->power_on) + { + if ((err = phye->ops->power_on(phye))) + { + goto _out_lock; + } + } + ++phye->power_count; + +_out_lock: + rt_spin_unlock(&phye->lock); + + return err; +} + +rt_err_t rt_phye_power_off(struct rt_phye *phye) +{ + rt_err_t err; + + if (!phye) + { + return RT_EOK; + } + + err = RT_EOK; + + rt_spin_lock(&phye->lock); + + if (phye->power_count == 1 && phye->ops->power_off) + { + if ((err = phye->ops->power_off(phye))) + { + goto _out_lock; + } + } + if (phye->power_count) + { + --phye->power_count; + } + +_out_lock: + rt_spin_unlock(&phye->lock); + + return err; +} + +rt_err_t rt_phye_set_mode(struct rt_phye *phye, enum rt_phye_mode mode, int submode) +{ + rt_err_t err; + + if (!phye) + { + return RT_EOK; + } + + if (mode < RT_PHYE_MODE_MAX && + (submode == RT_PHYE_MODE_INVALID || submode >= RT_PHYE_MODE_MAX)) + { + err = RT_EOK; + + rt_spin_lock(&phye->lock); + + if (phye->ops->set_mode) + { + err = phye->ops->set_mode(phye, mode, submode); + } + + rt_spin_unlock(&phye->lock); + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +static struct rt_phye *ofw_phye_get_by_index(struct rt_ofw_node *np, int index) +{ + struct rt_phye *phye = RT_NULL; +#ifdef RT_USING_OFW + rt_err_t err; + struct rt_ofw_node *phye_np; + struct rt_ofw_cell_args phye_args; + + if (!rt_ofw_parse_phandle_cells(np, "phys", "#phy-cells", index, &phye_args)) + { + phye_np = phye_args.data; + + if (!rt_ofw_data(phye_np)) + { + rt_platform_ofw_request(phye_np); + } + + phye = rt_ofw_data(phye_np); + rt_ofw_node_put(phye_np); + + if (phye && phye->ops->ofw_parse) + { + if ((err = phye->ops->ofw_parse(phye, &phye_args))) + { + phye = rt_err_ptr(err); + } + } + } +#endif /* RT_USING_OFW */ + return phye; +} + +struct rt_phye *rt_phye_get_by_index(struct rt_device *dev, int index) +{ + struct rt_phye *phye = RT_NULL; + + if (!dev || index < 0) + { + return rt_err_ptr(-RT_EINVAL); + } + + if (dev->ofw_node) + { + phye = ofw_phye_get_by_index(dev->ofw_node, index); + } + + if (!rt_is_err_or_null(phye)) + { + rt_spin_lock(&phye->lock); + ++phye->dev->ref_count; + rt_spin_unlock(&phye->lock); + } + + return phye; +} + +struct rt_phye *rt_phye_get_by_name(struct rt_device *dev, const char *id) +{ + int index; + + if (!dev || !id) + { + return rt_err_ptr(-RT_EINVAL); + } + + index = rt_dm_dev_prop_index_of_string(dev, "phy-names", id); + + if (index >= 0) + { + return rt_phye_get_by_index(dev, index); + } + + return RT_NULL; +} + +void rt_phye_put(struct rt_phye *phye) +{ + if (phye) + { + rt_spin_lock(&phye->lock); + --phye->dev->ref_count; + rt_spin_unlock(&phye->lock); + } +} diff --git a/rt-thread/components/drivers/pic/Kconfig b/rt-thread/components/drivers/pic/Kconfig index 16c1410..3cf00c0 100644 --- a/rt-thread/components/drivers/pic/Kconfig +++ b/rt-thread/components/drivers/pic/Kconfig @@ -1,12 +1,14 @@ menuconfig RT_USING_PIC bool "Using Programmable Interrupt Controller (PIC)" - select RT_USING_BITMAP + select RT_USING_ADT + select RT_USING_ADT_BITMAP depends on RT_USING_DM default n config RT_USING_PIC_STATISTICS bool "Enable ISR execution time statistics" depends on RT_USING_PIC + depends on RT_USING_KTIME depends on RT_USING_INTERRUPT_INFO default n @@ -22,12 +24,31 @@ config RT_PIC_ARM_GIC select RT_USING_OFW default n +config RT_PIC_ARM_GIC_V2M + bool "ARM GIC V2M" if RT_PIC_ARM_GIC && RT_PCI_MSI + depends on RT_USING_OFW + default n + config RT_PIC_ARM_GIC_V3 bool "ARM GICv3" depends on RT_USING_PIC select RT_USING_OFW default n +config RT_PIC_ARM_GIC_V3_ITS + bool "ARM GICv3 ITS (Interrupt Translation Service)" if RT_PIC_ARM_GIC_V3 && RT_PCI_MSI + depends on RT_USING_OFW + select RT_USING_ADT_REF + default n + +config RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX + int "IRQ maximum used" + depends on RT_PIC_ARM_GIC_V3_ITS + default 127 if ARCH_CPU_64BIT + default 63 + help + Recommended to be based on the bit length (full bits) of maximum usage. + config RT_PIC_ARM_GIC_MAX_NR int depends on RT_USING_PIC diff --git a/rt-thread/components/drivers/pic/SConscript b/rt-thread/components/drivers/pic/SConscript index e820792..53cb66e 100644 --- a/rt-thread/components/drivers/pic/SConscript +++ b/rt-thread/components/drivers/pic/SConscript @@ -16,9 +16,15 @@ if GetDepend(['RT_PIC_ARM_GIC']) or GetDepend(['RT_PIC_ARM_GIC_V3']): if GetDepend(['RT_PIC_ARM_GIC']): src += ['pic-gicv2.c'] +if GetDepend(['RT_PIC_ARM_GIC_V2M']): + src += ['pic-gicv2m.c'] + if GetDepend(['RT_PIC_ARM_GIC_V3']): src += ['pic-gicv3.c'] +if GetDepend(['RT_PIC_ARM_GIC_V3_ITS']): + src += ['pic-gicv3-its.c'] + group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/rt-thread/components/drivers/pic/pic-gic-common.c b/rt-thread/components/drivers/pic/pic-gic-common.c index 07e5f0b..5c6dc03 100644 --- a/rt-thread/components/drivers/pic/pic-gic-common.c +++ b/rt-thread/components/drivers/pic/pic-gic-common.c @@ -71,8 +71,9 @@ void gic_common_sgi_config(void *base, void *data, int irq_base) pirq = rt_pic_find_ipi(data, ipi); \ pirq->mode = RT_IRQ_MODE_EDGE_RISING; \ - DECLARE_GIC_IPI(RT_SCHEDULE_IPI, 0); - DECLARE_GIC_IPI(RT_STOP_IPI, 1); + DECLARE_GIC_IPI(RT_SCHEDULE_IPI, RT_SCHEDULE_IPI); + DECLARE_GIC_IPI(RT_STOP_IPI, RT_STOP_IPI); + DECLARE_GIC_IPI(RT_SMP_CALL_IPI, RT_SMP_CALL_IPI); #undef DECLARE_GIC_IPI } diff --git a/rt-thread/components/drivers/pic/pic-gic-common.h b/rt-thread/components/drivers/pic/pic-gic-common.h index 46841e8..d78e068 100644 --- a/rt-thread/components/drivers/pic/pic-gic-common.h +++ b/rt-thread/components/drivers/pic/pic-gic-common.h @@ -8,10 +8,14 @@ * 2023-01-30 GuEe-GUI first version */ -#ifndef __IRQ_GIC_COMMON_H__ -#define __IRQ_GIC_COMMON_H__ +#ifndef __PIC_GIC_COMMON_H__ +#define __PIC_GIC_COMMON_H__ #include + +#ifdef RT_PCI_MSI +#include +#endif #include #define GIC_SGI_NR 16 @@ -52,4 +56,4 @@ rt_err_t gicv2m_ofw_probe(struct rt_ofw_node *ic_np, const struct rt_ofw_node_id rt_err_t gicv3_its_ofw_probe(struct rt_ofw_node *ic_np, const struct rt_ofw_node_id *id); #endif -#endif /* __IRQ_GIC_COMMON_H__ */ +#endif /* __PIC_GIC_COMMON_H__ */ diff --git a/rt-thread/components/drivers/pic/pic-gicv2.c b/rt-thread/components/drivers/pic/pic-gicv2.c index adce046..dbfd443 100644 --- a/rt-thread/components/drivers/pic/pic-gicv2.c +++ b/rt-thread/components/drivers/pic/pic-gicv2.c @@ -83,6 +83,11 @@ static void gicv2_dist_init(struct gicv2 *gic) LOG_D("Max irq = %d", gic->max_irq); + if (gic->skip_init) + { + return; + } + HWREG32(base + GIC_DIST_CTRL) = GICD_DISABLE; /* Set all global (unused) interrupts to this CPU only. */ @@ -128,6 +133,8 @@ static void gicv2_cpu_init(struct gicv2 *gic) #ifdef ARCH_SUPPORT_HYP _gicv2_eoi_mode_ns = RT_TRUE; +#else + _gicv2_eoi_mode_ns = !!rt_ofw_bootargs_select("pic.gicv2_eoimode", 0); #endif if (_gicv2_eoi_mode_ns) @@ -618,6 +625,8 @@ static rt_err_t gicv2_ofw_init(struct rt_ofw_node *np, const struct rt_ofw_node_ break; } + gic->skip_init = rt_ofw_prop_read_bool(np, "skip-init"); + gic_common_init_quirk_ofw(np, _gicv2_quirks, gic); gicv2_init(gic); diff --git a/rt-thread/components/drivers/pic/pic-gicv2.h b/rt-thread/components/drivers/pic/pic-gicv2.h index 69f9651..5fa9f2a 100644 --- a/rt-thread/components/drivers/pic/pic-gicv2.h +++ b/rt-thread/components/drivers/pic/pic-gicv2.h @@ -78,6 +78,8 @@ struct gicv2 rt_size_t hyp_size; void *vcpu_base; rt_size_t vcpu_size; + + rt_bool_t skip_init; }; #endif /* __IRQ_GICV2_H__ */ diff --git a/rt-thread/components/drivers/pic/pic-gicv2m.c b/rt-thread/components/drivers/pic/pic-gicv2m.c new file mode 100644 index 0000000..ae60137 --- /dev/null +++ b/rt-thread/components/drivers/pic/pic-gicv2m.c @@ -0,0 +1,378 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-11-07 GuEe-GUI first version + */ + +#include +#include +#include + +#define DBG_TAG "pic.gicv2m" +#define DBG_LVL DBG_INFO +#include + +#include +#include +#include "pic-gic-common.h" + +/* +* MSI_TYPER: +* [31:26] Reserved +* [25:16] lowest SPI assigned to MSI +* [15:10] Reserved +* [9:0] Numer of SPIs assigned to MSI +*/ +#define V2M_MSI_TYPER 0x008 +#define V2M_MSI_TYPER_BASE_SHIFT 16 +#define V2M_MSI_TYPER_BASE_MASK 0x3ff +#define V2M_MSI_TYPER_NUM_MASK 0x3ff +#define V2M_MSI_SETSPI_NS 0x040 +#define V2M_MIN_SPI 32 +#define V2M_MAX_SPI 1019 +#define V2M_MSI_IIDR 0xfcc + +#define V2M_MSI_TYPER_BASE_SPI(x) (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK) +#define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK) + +/* APM X-Gene with GICv2m MSI_IIDR register value */ +#define XGENE_GICV2M_MSI_IIDR 0x06000170 +/* Broadcom NS2 GICv2m MSI_IIDR register value */ +#define BCM_NS2_GICV2M_MSI_IIDR 0x0000013f + +/* List of flags for specific v2m implementation */ +#define GICV2M_NEEDS_SPI_OFFSET 0x00000001 +#define GICV2M_GRAVITON_ADDRESS_ONLY 0x00000002 + +struct gicv2m +{ + struct rt_pic parent; + + void *base; + void *base_phy; + rt_uint32_t spi_start; /* The SPI number that MSIs start */ + rt_uint32_t spis_nr; /* The number of SPIs for MSIs */ + rt_uint32_t spi_offset; /* Offset to be subtracted from SPI number */ + + rt_bitmap_t *vectors; /* MSI vector bitmap */ + rt_uint32_t flags; /* Flags for v2m's specific implementation */ + + void *gic; + struct rt_spinlock lock; +}; + +#define raw_to_gicv2m(raw) rt_container_of(raw, struct gicv2m, parent) + +static rt_ubase_t gicv2m_get_msi_addr(struct gicv2m *v2m, int hwirq) +{ + rt_ubase_t addr; + + if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) + { + addr = (rt_ubase_t)v2m->base_phy | ((hwirq - 32) << 3); + } + else + { + addr = (rt_ubase_t)v2m->base_phy + V2M_MSI_SETSPI_NS; + } + + return addr; +} + +static rt_bool_t is_msi_spi_valid(rt_uint32_t base, rt_uint32_t num) +{ + if (base < V2M_MIN_SPI) + { + LOG_E("Invalid MSI base SPI (base: %u)", base); + + return RT_FALSE; + } + else if ((num == 0) || (base + num > V2M_MAX_SPI)) + { + LOG_E("Number of SPIs (%u) exceed maximum (%u)", num, V2M_MAX_SPI - V2M_MIN_SPI + 1); + + return RT_FALSE; + } + + return RT_TRUE; +} + +static void gicv2m_irq_mask(struct rt_pic_irq *pirq) +{ + rt_pci_msi_mask_irq(pirq); + rt_pic_irq_parent_mask(pirq); +} + +static void gicv2m_irq_unmask(struct rt_pic_irq *pirq) +{ + rt_pci_msi_unmask_irq(pirq); + rt_pic_irq_parent_unmask(pirq); +} + +static void gicv2m_compose_msi_msg(struct rt_pic_irq *pirq, struct rt_pci_msi_msg *msg) +{ + rt_ubase_t addr; + struct gicv2m *v2m = raw_to_gicv2m(pirq->pic); + + addr = gicv2m_get_msi_addr(v2m, pirq->hwirq); + + msg->address_hi = rt_upper_32_bits(addr); + msg->address_lo = rt_lower_32_bits(addr); + + if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) + { + msg->data = 0; + } + else + { + msg->data = pirq->hwirq; + } + + if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET) + { + msg->data -= v2m->spi_offset; + } +} + +static int gicv2m_irq_alloc_msi(struct rt_pic *pic, struct rt_pci_msi_desc *msi_desc) +{ + rt_ubase_t level; + int irq, parent_irq, hwirq, hwirq_index; + struct rt_pic_irq *pirq; + struct gicv2m *v2m = raw_to_gicv2m(pic); + struct rt_pic *ppic = v2m->gic; + + level = rt_spin_lock_irqsave(&v2m->lock); + hwirq_index = rt_bitmap_next_clear_bit(v2m->vectors, 0, v2m->spis_nr); + + if (hwirq_index >= v2m->spis_nr) + { + irq = -RT_EEMPTY; + goto _out_lock; + } + + hwirq = v2m->spi_start + v2m->spi_offset + hwirq_index; + + parent_irq = ppic->ops->irq_map(ppic, hwirq, RT_IRQ_MODE_EDGE_RISING); + if (parent_irq < 0) + { + irq = parent_irq; + goto _out_lock; + } + + irq = rt_pic_config_irq(pic, hwirq_index, hwirq); + if (irq < 0) + { + goto _out_lock; + } + pirq = rt_pic_find_irq(pic, hwirq_index); + + pirq->mode = RT_IRQ_MODE_EDGE_RISING; + rt_pic_cascade(pirq, parent_irq); + + rt_bitmap_set_bit(v2m->vectors, hwirq_index); + +_out_lock: + rt_spin_unlock_irqrestore(&v2m->lock, level); + + return irq; +} + +static void gicv2m_irq_free_msi(struct rt_pic *pic, int irq) +{ + rt_ubase_t level; + struct rt_pic_irq *pirq; + struct gicv2m *v2m = raw_to_gicv2m(pic); + + pirq = rt_pic_find_pirq(pic, irq); + + if (!pirq) + { + return; + } + + rt_pic_uncascade(pirq); + + level = rt_spin_lock_irqsave(&v2m->lock); + rt_bitmap_clear_bit(v2m->vectors, pirq->hwirq - (v2m->spi_start + v2m->spi_offset)); + rt_spin_unlock_irqrestore(&v2m->lock, level); +} + +static rt_err_t gicv2m_irq_set_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t state) +{ + struct gicv2m *v2m = raw_to_gicv2m(pic); + struct rt_pic *ppic = v2m->gic; + + return ppic->ops->irq_set_state(ppic, hwirq, type, state); +} + +static rt_err_t gicv2m_irq_get_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t *out_state) +{ + struct gicv2m *v2m = raw_to_gicv2m(pic); + struct rt_pic *ppic = v2m->gic; + + return ppic->ops->irq_get_state(ppic, hwirq, type, out_state); +} + +const static struct rt_pic_ops gicv2m_ops = +{ + .name = "GICv2m", + .irq_ack = rt_pic_irq_parent_ack, + .irq_mask = gicv2m_irq_mask, + .irq_unmask = gicv2m_irq_unmask, + .irq_eoi = rt_pic_irq_parent_eoi, + .irq_set_priority = rt_pic_irq_parent_set_priority, + .irq_set_affinity = rt_pic_irq_parent_set_affinity, + .irq_compose_msi_msg = gicv2m_compose_msi_msg, + .irq_alloc_msi = gicv2m_irq_alloc_msi, + .irq_free_msi = gicv2m_irq_free_msi, + .irq_set_state = gicv2m_irq_set_state, + .irq_get_state = gicv2m_irq_get_state, + .flags = RT_PIC_F_IRQ_ROUTING, +}; + +static const struct rt_ofw_node_id gicv2m_ofw_match[] = +{ + { .compatible = "arm,gic-v2m-frame" }, + { /* sentinel */ } +}; + +rt_err_t gicv2m_ofw_probe(struct rt_ofw_node *np, const struct rt_ofw_node_id *id) +{ + rt_err_t err = RT_EOK; + struct rt_ofw_node *v2m_np; + + rt_ofw_foreach_available_child_node(np, v2m_np) + { + struct gicv2m *v2m; + rt_size_t bitmap_size; + rt_uint32_t spi_start = 0, spis_nr = 0; + + if (!rt_ofw_node_match(v2m_np, gicv2m_ofw_match)) + { + continue; + } + + if (!rt_ofw_prop_read_bool(v2m_np, "msi-controller")) + { + continue; + } + + if (!(v2m = rt_malloc(sizeof(*v2m)))) + { + rt_ofw_node_put(v2m_np); + + err = -RT_ENOMEM; + break; + } + + v2m->base = rt_ofw_iomap(v2m_np, 0); + + if (!v2m->base) + { + LOG_E("%s: IO map failed", rt_ofw_node_full_name(v2m_np)); + continue; + } + + v2m->base_phy = rt_kmem_v2p(v2m->base); + v2m->flags = 0; + + if (!rt_ofw_prop_read_u32(v2m_np, "arm,msi-base-spi", &spi_start) && + !rt_ofw_prop_read_u32(v2m_np, "arm,msi-num-spis", &spis_nr)) + { + LOG_I("DT overriding V2M MSI_TYPER (base:%u, num:%u)", spi_start, spis_nr); + } + + if (spi_start && spis_nr) + { + v2m->spi_start = spi_start; + v2m->spis_nr = spis_nr; + } + else + { + rt_uint32_t typer; + + /* Graviton should always have explicit spi_start/spis_nr */ + if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) + { + goto _fail; + } + typer = HWREG32(v2m->base + V2M_MSI_TYPER); + + v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer); + v2m->spis_nr = V2M_MSI_TYPER_NUM_SPI(typer); + } + + if (!is_msi_spi_valid(v2m->spi_start, v2m->spis_nr)) + { + goto _fail; + } + + /* + * APM X-Gene GICv2m implementation has an erratum where + * the MSI data needs to be the offset from the spi_start + * in order to trigger the correct MSI interrupt. This is + * different from the standard GICv2m implementation where + * the MSI data is the absolute value within the range from + * spi_start to (spi_start + num_spis). + * + * Broadcom NS2 GICv2m implementation has an erratum where the MSI data + * is 'spi_number - 32' + * + * Reading that register fails on the Graviton implementation + */ + if (!(v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)) + { + switch (HWREG32(v2m->base + V2M_MSI_IIDR)) + { + case XGENE_GICV2M_MSI_IIDR: + v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; + v2m->spi_offset = v2m->spi_start; + break; + + case BCM_NS2_GICV2M_MSI_IIDR: + v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; + v2m->spi_offset = 32; + break; + } + } + + bitmap_size = RT_BITMAP_LEN(v2m->spis_nr) * sizeof(rt_bitmap_t); + + if (!(v2m->vectors = rt_calloc(1, bitmap_size))) + { + err = -RT_ENOMEM; + goto _fail; + } + + rt_spin_lock_init(&v2m->lock); + + v2m->parent.priv_data = v2m; + v2m->parent.ops = &gicv2m_ops; + v2m->gic = rt_ofw_data(np); + + rt_pic_linear_irq(&v2m->parent, v2m->spis_nr); + rt_pic_user_extends(&v2m->parent); + + rt_ofw_data(v2m_np) = &v2m->parent; + rt_ofw_node_set_flag(v2m_np, RT_OFW_F_READLY); + + continue; + + _fail: + rt_iounmap(v2m->base); + rt_free(v2m); + + if (err) + { + rt_ofw_node_put(v2m_np); + break; + } + } + + return err; +} diff --git a/rt-thread/components/drivers/pic/pic-gicv3-its.c b/rt-thread/components/drivers/pic/pic-gicv3-its.c new file mode 100644 index 0000000..f0772d9 --- /dev/null +++ b/rt-thread/components/drivers/pic/pic-gicv3-its.c @@ -0,0 +1,1584 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-01-30 GuEe-GUI first version + */ + +#include +#include +#include + +#define DBG_TAG "pic.gicv3-its" +#define DBG_LVL DBG_INFO +#include + +#include +#include +#include +#include +#include "pic-gicv3.h" +#include "pic-gic-common.h" + +#define ITS_CMD_QUEUE_SIZE (64 * SIZE_KB) +#define ITS_CMD_QUEUE_ALIGN (64 * SIZE_KB) +#define ITS_CMD_QUEUE_NR (ITS_CMD_QUEUE_SIZE / sizeof(struct its_command)) + +#define ITS_ITT_ALIGN (256 * SIZE_KB) + +#define ITS_LPI_CONFIG_TABLE_ALIGN (64 * SIZE_KB) +#define ITS_LPI_CONFIG_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI +#define ITS_LPI_CONFIG_PROP_SHIFT 2 +#define ITS_LPI_CONFIG_PROP_MASK RT_GENMASK(7, ITS_LPI_CONFIG_PROP_SHIFT) +#define ITS_LPI_PENDING_TABLE_ALIGN (64 * SIZE_KB) + +#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING RT_BIT(0) +#define RDIST_FLAGS_RD_TABLES_PREALLOCATED RT_BIT(1) +#define RDIST_FLAGS_FORCE_NON_SHAREABLE RT_BIT(2) + +#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING RT_BIT(0) +#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 RT_BIT(1) +#define ITS_FLAGS_FORCE_NON_SHAREABLE RT_BIT(2) + +#define RD_LOCAL_LPI_ENABLED RT_BIT(0) +#define RD_LOCAL_PENDTABLE_PREALLOCATED RT_BIT(1) +#define RD_LOCAL_MEMRESERVE_DONE RT_BIT(2) + +struct its_command +{ + union + { + rt_le64_t code_raw[4]; + rt_uint64_t code[4]; + }; +}; + +struct its_table +{ + void *base; + rt_uint64_t val; + rt_uint32_t size_bits; + rt_uint32_t page_size; + union + { + struct + { + rt_uint32_t itt_entries; + rt_uint32_t lvl2_bits; + }; + }; +}; + +struct its_collection +{ + rt_uint64_t target_address; + rt_uint16_t id; +}; + +struct gicv3_its; + +struct its_map +{ + rt_list_t list; + struct rt_ref ref; + struct gicv3_its *its; + + int device_id; + int lpi_base; + int cpu_id; + + void *itt; + void *lvl2_dte; +}; + +struct gicv3_its +{ + struct rt_pic parent; + rt_list_t list; + + void *base; + void *base_phy; + + void *cmd_base; + rt_ubase_t cmd_idx; + rt_uint32_t flags; + struct rt_spinlock cmd_lock; + + struct its_table tbls[GITS_BASER_NR_REGS]; + struct its_collection collections[RT_CPUS_NR]; + + struct gicv3 *gic; + struct rt_ofw_node *np; +}; + +#define raw_to_gicv3_its(raw) rt_container_of(raw, struct gicv3_its, parent) + +static rt_size_t lpi_nr; +static rt_uint32_t lpi_id_bits; +static void *lpi_table; +static void *lpi_pending_table; +static rt_bitmap_t *lpis_vectors = RT_NULL; +static struct rt_spinlock lpis_lock = {}, map_lock = {}; +static rt_list_t its_nodes = RT_LIST_OBJECT_INIT(its_nodes); +static rt_list_t map_nodes = RT_LIST_OBJECT_INIT(map_nodes); + +rt_inline rt_uint64_t its_readq(struct gicv3_its *its, int off) +{ + return HWREG32(its->base + off) | + (rt_uint64_t)HWREG32(its->base + off + 4) << 32; +} + +rt_inline void its_writeq(struct gicv3_its *its, int off, rt_uint64_t value) +{ + HWREG32(its->base + off) = (rt_uint32_t)value; + HWREG32(its->base + off + 4) = (rt_uint32_t)(value >> 32); +} + +rt_inline rt_uint32_t its_readl(struct gicv3_its *its, int off) +{ + return HWREG32(its->base + off); +} + +rt_inline void its_writel(struct gicv3_its *its, int off, rt_uint32_t value) +{ + HWREG32(its->base + off) = value; +} + +rt_inline rt_uint32_t its_pirq_event_id(struct gicv3_its *its, struct rt_pic_irq *pirq) +{ + return pirq->hwirq - 8192; +} + +rt_inline rt_uint32_t its_pirq_device_id(struct gicv3_its *its, struct rt_pic_irq *pirq) +{ + struct its_map *map = pirq->msi_desc->priv; + + return map->device_id; +} + +rt_inline rt_size_t its_device_id_bits(struct gicv3_its *its) +{ + return RT_FIELD_GET(GITS_TYPER_DEVBITS, HWREG64(its->base + GITS_TYPER)) + 1; +} + +rt_inline void *lpi_base_config(int index) +{ + return &((rt_uint8_t *)lpi_table)[index - 8192]; +} + +static void its_mask_encode(rt_uint64_t *raw_code, rt_uint64_t val, int h, int l) +{ + rt_uint64_t mask = RT_GENMASK_ULL(h, l); + *raw_code &= ~mask; + *raw_code |= (val << l) & mask; +} + +rt_inline void its_encode_cmd(struct its_command *cmd, rt_uint8_t cmd_nr) +{ + its_mask_encode(&cmd->code[0], cmd_nr, 7, 0); +} + +rt_inline void its_encode_valid(struct its_command *cmd, rt_bool_t valid) +{ + its_mask_encode(&cmd->code[2], !!valid, 63, 63); +} + +rt_inline void its_encode_phys_id(struct its_command *cmd, rt_uint32_t phys_id) +{ + its_mask_encode(&cmd->code[1], phys_id, 63, 32); +} + +rt_inline void its_encode_size(struct its_command *cmd, rt_uint8_t size) +{ + its_mask_encode(&cmd->code[1], size, 4, 0); +} + +rt_inline void its_encode_itt(struct its_command *cmd, rt_uint64_t itt_addr) +{ + its_mask_encode(&cmd->code[2], itt_addr >> 8, 51, 8); +} + +rt_inline void its_encode_target(struct its_command *cmd, rt_uint64_t target_addr) +{ + its_mask_encode(&cmd->code[2], target_addr >> 16, 51, 16); +} + +rt_inline void its_encode_device_id(struct its_command *cmd, rt_uint32_t device_id) +{ + its_mask_encode(&cmd->code[0], device_id, 63, 32); +} + +rt_inline void its_encode_event_id(struct its_command *cmd, rt_uint32_t event_id) +{ + its_mask_encode(&cmd->code[1], event_id, 31, 0); +} + +rt_inline void its_encode_collection(struct its_command *cmd, rt_uint16_t collection_id) +{ + its_mask_encode(&cmd->code[2], collection_id, 15, 0); +} + +static struct its_table *its_baser_type(struct gicv3_its *its, int type) +{ + for (int i = 0; i < RT_ARRAY_SIZE(its->tbls); ++i) + { + if (GITS_BASER_TYPE(its->tbls[i].val) == type) + { + return &its->tbls[i]; + } + } + + return RT_NULL; +} + +static struct its_command *its_cmd_alloc(struct gicv3_its *its) +{ + struct its_command *cmd = RT_NULL; + + for (rt_uint32_t count = 0; count <= 10000; ++count) + { + if ((its->cmd_idx + 1) % ITS_CMD_QUEUE_NR != its_readl(its, GITS_CREADR) / sizeof(*cmd)) + { + struct its_command *cmds = its->cmd_base; + + cmd = &cmds[its->cmd_idx++]; + its->cmd_idx %= ITS_CMD_QUEUE_NR; + + rt_memset(cmd, 0, sizeof(*cmd)); + + break; + } + + rt_hw_us_delay(10); + } + + return cmd; +} + +static rt_err_t its_cmd_submit_raw(struct gicv3_its *its, struct its_command *cmd) +{ + rt_uint64_t cwriter; + rt_bool_t retry = RT_FALSE; + + cwriter = (void *)(cmd + 1) - its->cmd_base; + rt_hw_rmb(); + +#ifdef ARCH_CPU_BIG_ENDIAN + cmd->code_raw[0] = rt_cpu_to_le64(cmd->code[0]); + cmd->code_raw[1] = rt_cpu_to_le64(cmd->code[1]); + cmd->code_raw[2] = rt_cpu_to_le64(cmd->code[2]); + cmd->code_raw[3] = rt_cpu_to_le64(cmd->code[3]); +#endif /* ARCH_CPU_BIG_ENDIAN */ + + /* Make sure the commands written to memory are observable by the ITS */ + if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, cmd, sizeof(*cmd)); + } + else + { + rt_hw_wmb(); + } + + its_writel(its, GITS_CWRITER, cwriter); + + for (rt_uint32_t count = 0; count < 10000; ++count) + { + if (its_readl(its, GITS_CREADR) == cwriter) + { + return RT_EOK; + } + + /* Stalled */ + if (!retry && its_readl(its, GITS_CREADR) & 1) + { + /* Retry */ + its_writel(its, GITS_CWRITER, cwriter); + retry = RT_TRUE; + } + else if (retry) + { + LOG_E("Retry command 0x%02x fail", cmd->code[0] & 0xff); + + return -RT_EIO; + } + + rt_hw_us_delay(10); + } + + return -RT_ETIMEOUT; +} + +static rt_err_t its_cmd_submit_nomap(struct gicv3_its *its, struct its_command *cmd, + int cpu_id, rt_bool_t sync) +{ + rt_err_t err; + struct its_command *hw_cmd; + + rt_hw_spin_lock(&its->cmd_lock.lock); + + if (!(hw_cmd = its_cmd_alloc(its))) + { + err = -RT_EBUSY; + goto _out_lock; + } + + rt_memcpy(hw_cmd, cmd, sizeof(*hw_cmd)); + + if ((err = its_cmd_submit_raw(its, hw_cmd))) + { + goto _out_lock; + } + + if (sync) + { + if (!(hw_cmd = its_cmd_alloc(its))) + { + err = -RT_EBUSY; + goto _out_lock; + } + + its_encode_cmd(hw_cmd, GITS_CMD_SYNC); + its_encode_target(hw_cmd, its->collections[cpu_id].target_address); + + err = its_cmd_submit_raw(its, hw_cmd); + } + +_out_lock: + rt_hw_spin_unlock(&its->cmd_lock.lock); + + return err; +} + +static rt_err_t its_cmd_submit(struct gicv3_its *its, struct its_command *cmd, + struct its_map *map, rt_bool_t sync) +{ + return its_cmd_submit_nomap(its, cmd, map->cpu_id, sync); +} + +static rt_err_t lpi_flush_config(struct gicv3_its *its, rt_uint8_t *conf, + struct rt_pic_irq *pirq) +{ + struct its_command cmd; + struct its_map *map = pirq->msi_desc->priv; + + if (its->gic->redist_flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) + { + /* Clean D-cache under command */ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, conf, sizeof(*conf)); + } + else + { + /* DSB inner shareable, store */ + rt_hw_wmb(); + } + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_INV); + its_encode_device_id(&cmd, its_pirq_device_id(its, pirq)); + its_encode_event_id(&cmd, its_pirq_event_id(its, pirq)); + + return its_cmd_submit(its, &cmd, map, RT_FALSE); +} + +rt_inline void *gicr_rd_base_percpu(struct gicv3 *gic) +{ + return gic->redist_regions[rt_hw_cpu_id()].base; +} + +rt_inline void *gicr_rd_base(struct gicv3_its *its) +{ + return its->gic->redist_percpu_base[rt_hw_cpu_id()]; +} + +rt_inline rt_uint64_t *gicr_rd_flags(struct gicv3_its *its) +{ + return &its->gic->redist_percpu_flags[rt_hw_cpu_id()]; +} + +static rt_bool_t gicr_supports_plpis(struct gicv3_its *its) +{ + return !!(HWREG64(gicr_rd_base(its) + GICR_TYPER) & GICR_TYPER_PLPIS); +} + +static rt_err_t redist_disable_lpis(struct gicv3_its *its) +{ + void *gicr = gicr_rd_base(its); + rt_uint64_t timeout = 1000000L, val; + + if (!gicr_supports_plpis(its)) + { + LOG_E("CPU#%d: LPIs not supported", rt_hw_cpu_id()); + return -RT_ENOSYS; + } + + val = HWREG32(gicr + GICR_CTLR); + if (!(val & GICR_CTLR_ENABLE_LPIS)) + { + return RT_EOK; + } + + /* + * If coming via a CPU hotplug event, we don't need to disable + * LPIs before trying to re-enable them. They are already + * configured and all is well in the world. + * + * If running with preallocated tables, there is nothing to do. + */ + if ((*gicr_rd_flags(its) & RD_LOCAL_LPI_ENABLED) || + (its->gic->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED)) + { + return RT_EOK; + } + + /* From that point on, we only try to do some damage control */ + LOG_W("CPU%d: Booted with LPIs enabled, memory probably corrupted", rt_hw_cpu_id()); + + /* Disable LPIs */ + val &= ~GICR_CTLR_ENABLE_LPIS; + HWREG32(gicr + GICR_CTLR) = val; + + /* Make sure any change to GICR_CTLR is observable by the GIC */ + rt_hw_barrier(dsb, sy); + + /* + * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs + * from 1 to 0 before programming GICR_PEND{PROP}BASER registers. + * Error out if we time out waiting for RWP to clear. + */ + while (HWREG32(gicr + GICR_CTLR) & GICR_CTLR_RWP) + { + if (!timeout) + { + LOG_E("CPU#%d: Timeout while disabling LPIs", rt_hw_cpu_id()); + + return -RT_ETIMEOUT; + } + + rt_hw_us_delay(1); + --timeout; + } + + /* + * After it has been written to 1, it is IMPLEMENTATION + * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be + * cleared to 0. Error out if clearing the bit failed. + */ + if (HWREG32(gicr + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) + { + LOG_E("CPU#%d: Failed to disable LPIs", rt_hw_cpu_id()); + + return -RT_EBUSY; + } + + return RT_EOK; +} + +static void gicv3_its_cpu_init_lpis(struct gicv3_its *its) +{ + void *gicr; + rt_ubase_t paddr; + rt_uint64_t val, tmp; + + if (*gicr_rd_flags(its) & RD_LOCAL_LPI_ENABLED) + { + return; + } + + gicr = gicr_rd_base(its); + + val = HWREG32(gicr + GICR_CTLR); + + if ((its->gic->redist_flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) && + (val & GICR_CTLR_ENABLE_LPIS)) + { + *gicr_rd_flags(its) |= RD_LOCAL_PENDTABLE_PREALLOCATED; + + goto _out; + } + + paddr = (rt_ubase_t)rt_kmem_v2p(lpi_pending_table); + + /* Set PROPBASE */ + val = ((rt_ubase_t)rt_kmem_v2p(lpi_table) | + GITS_CBASER_InnerShareable | + GITS_CBASER_RaWaWb | + ((lpi_id_bits - 1) & GICR_PROPBASER_IDBITS_MASK)); + + HWREG64(gicr + GICR_PROPBASER) = val; + tmp = HWREG64(gicr + GICR_PROPBASER); + + if (its->gic->redist_flags & RDIST_FLAGS_FORCE_NON_SHAREABLE) + { + tmp &= ~GICR_PBASER_SHARE_MASK_ALL; + } + + if ((tmp ^ val) & GICR_PBASER_SHARE_MASK_ALL) + { + if (!(tmp & GICR_PBASER_SHARE_MASK_ALL)) + { + /* + * The HW reports non-shareable, + * we must remove the cacheability attributes as well. + */ + val &= ~(GICR_PBASER_SHARE_MASK_ALL | GICR_PBASER_INNER_MASK_ALL); + val |= GICR_PBASER_nC; + HWREG64(gicr + GICR_PROPBASER) = val; + } + + if (!rt_hw_cpu_id()) + { + LOG_I("Using cache flushing for LPI property table"); + } + its->gic->redist_flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; + } + + val = (paddr | GICR_PBASER_InnerShareable | GICR_PBASER_RaWaWb); + + HWREG64(gicr + GICR_PENDBASER) = val; + tmp = HWREG64(gicr + GICR_PENDBASER); + + if (its->gic->redist_flags & RDIST_FLAGS_FORCE_NON_SHAREABLE) + { + tmp &= ~GICR_PBASER_SHARE_MASK_ALL; + } + + if (!(tmp & GICR_PBASER_SHARE_MASK_ALL)) + { + /* + * The HW reports non-shareable, we must remove the + * cacheability attributes as well. + */ + val &= ~(GICR_PBASER_SHARE_MASK_ALL | GICR_PBASER_INNER_MASK_ALL); + val |= GICR_PBASER_nC; + HWREG64(gicr + GICR_PENDBASER) = val; + } + + /* Enable LPIs */ + val = HWREG32(gicr + GICR_CTLR); + val |= GICR_CTLR_ENABLE_LPIS; + HWREG32(gicr + GICR_CTLR) = val; + + rt_hw_barrier(dsb, sy); + +_out: + *gicr_rd_flags(its) |= RD_LOCAL_LPI_ENABLED; +} + +static void gicv3_its_cpu_init_collection(struct gicv3_its *its) +{ + rt_uint64_t target; + int cpu_id = rt_hw_cpu_id(); + struct its_command cmd; + struct its_collection *collection; + + if (HWREG64(its->base + GITS_TYPER) & GITS_TYPER_PTA) + { + target = (rt_uint64_t)rt_kmem_v2p(gicr_rd_base(its)); + } + else + { + /* Linear by GICR processor number */ + target = HWREG64(gicr_rd_base(its) + GICR_TYPER); + target = GICR_TYPER_CPU_NO(target) << 16; + } + + collection = &its->collections[cpu_id]; + collection->target_address = target; + collection->id = cpu_id; + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_MAPC); + its_encode_collection(&cmd, collection->id); + its_encode_target(&cmd, target); + its_encode_valid(&cmd, RT_TRUE); + its_cmd_submit_nomap(its, &cmd, cpu_id, RT_TRUE); + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_INVALL); + its_encode_collection(&cmd, collection->id); + its_cmd_submit_nomap(its, &cmd, cpu_id, RT_TRUE); +} + +static rt_err_t gicv3_its_irq_init(struct rt_pic *pic) +{ + rt_err_t err; + struct gicv3_its *its = raw_to_gicv3_its(pic); + + if ((err = redist_disable_lpis(its))) + { + return err; + } + + gicv3_its_cpu_init_lpis(its); + gicv3_its_cpu_init_collection(its); + + return RT_EOK; +} + +static void gicv3_its_irq_mask(struct rt_pic_irq *pirq) +{ + rt_uint8_t *conf = lpi_base_config(pirq->hwirq); + struct gicv3_its *its = raw_to_gicv3_its(pirq->pic); + + *conf &= ~GITS_LPI_CFG_ENABLED; + lpi_flush_config(its, conf, pirq); + + rt_pci_msi_mask_irq(pirq); +} + +static void gicv3_its_irq_unmask(struct rt_pic_irq *pirq) +{ + rt_uint8_t *conf = lpi_base_config(pirq->hwirq); + struct gicv3_its *its = raw_to_gicv3_its(pirq->pic); + + *conf |= GITS_LPI_CFG_ENABLED; + lpi_flush_config(its, conf, pirq); + + rt_pci_msi_unmask_irq(pirq); +} + +static rt_err_t gicv3_its_irq_set_priority(struct rt_pic_irq *pirq, rt_uint32_t priority) +{ + rt_uint8_t *conf = lpi_base_config(pirq->hwirq); + struct gicv3_its *its = raw_to_gicv3_its(pirq->pic); + + *conf = (priority << ITS_LPI_CONFIG_PROP_SHIFT) | (*conf & (~ITS_LPI_CONFIG_PROP_MASK)); + + return lpi_flush_config(its, conf, pirq); +} + +static rt_err_t gicv3_its_irq_set_affinity(struct rt_pic_irq *pirq, rt_bitmap_t *affinity) +{ + int cpu_id; + rt_err_t err; + struct its_map *map; + struct its_command cmd; + struct its_collection *collection; + struct gicv3_its *its = raw_to_gicv3_its(pirq->pic); + + map = pirq->msi_desc->priv; + cpu_id = rt_bitmap_next_set_bit(affinity, 0, RT_CPUS_NR); + collection = &its->collections[cpu_id]; + + if (collection->target_address == ~0ULL) + { + return -RT_EIO; + } + + if (map->cpu_id == cpu_id) + { + return RT_EOK; + } + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_MOVI); + its_encode_device_id(&cmd, map->device_id); + its_encode_event_id(&cmd, its_pirq_event_id(its, pirq)); + its_encode_collection(&cmd, collection->id); + + if (!(err = its_cmd_submit(its, &cmd, map, RT_TRUE))) + { + map->cpu_id = cpu_id; + } + + return err; +} + +static void gicv3_its_irq_compose_msi_msg(struct rt_pic_irq *pirq, struct rt_pci_msi_msg *msg) +{ + rt_ubase_t addr; + struct gicv3_its *its = raw_to_gicv3_its(pirq->pic); + + addr = (rt_ubase_t)its->base_phy + GITS_TRANSLATER; + + msg->address_hi = rt_upper_32_bits(addr); + msg->address_lo = rt_lower_32_bits(addr); + msg->data = its_pirq_event_id(its, pirq); +} + +static int gicv3_its_irq_alloc_msi(struct rt_pic *pic, struct rt_pci_msi_desc *msi_desc) +{ + rt_ubase_t level; + rt_uint32_t device_id = -1; + int irq = -1, hwirq, parent_irq, hwirq_index, lpi_base = 0; + struct its_map *map = RT_NULL, *map_tmp; + struct its_table *tbl; + struct its_command cmd; + struct rt_pic_irq *pirq; + struct rt_pci_device *pdev = msi_desc->pdev; + struct gicv3_its *its = raw_to_gicv3_its(pic); + struct rt_pic *ppic = &its->gic->parent; + + tbl = its_baser_type(its, GITS_BASER_TYPE_DEVICE); + RT_ASSERT(tbl != RT_NULL); + + if (!pdev->parent.ofw_node) + { + device_id = rt_pci_dev_id(pdev); + } + else + { + struct rt_ofw_cell_args args; + + for (int index = 0; ; ++index) + { + rt_err_t err = rt_ofw_parse_phandle_cells(pdev->parent.ofw_node, + "msi-parent", "#msi-cells", index, &args); + + if (err) + { + return (int)err; + } + + if (args.data == its->np) + { + device_id = args.args[0]; + } + + rt_ofw_node_put(args.data); + + if ((rt_int32_t)device_id >= 0) + { + break; + } + } + } + + if (device_id >= (1 << tbl->size_bits)) + { + LOG_E("Device ID = is %x not supported", device_id); + + return -RT_EINVAL; + } + + /* Find old map info */ + level = rt_spin_lock_irqsave(&map_lock); + rt_list_for_each_entry(map_tmp, &map_nodes, list) + { + if (map_tmp->device_id == device_id) + { + map = map_tmp; + lpi_base = map->lpi_base - 8192; + break; + } + } + rt_spin_unlock_irqrestore(&map_lock, level); + + if (!map) + { + rt_size_t itt_size; + + if (!(map = rt_calloc(1, sizeof(*map)))) + { + return -RT_ENOMEM; + } + + itt_size = tbl->itt_entries * (RT_FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, + HWREG64(its->base + GITS_TYPER)) + 1); + itt_size = rt_max_t(rt_size_t, itt_size, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; + + map->itt = rt_malloc_align(itt_size, ITS_ITT_ALIGN); + + if (!map->itt) + { + rt_free(map); + return -RT_ENOMEM; + } + + if (tbl->lvl2_bits) + { + void *lvl2_dte; + rt_uint64_t *entry; + + entry = tbl->base; + entry += device_id / (tbl->page_size / GITS_LVL1_ENTRY_SIZE); + + if (*entry) + { + lvl2_dte = (void *)(*entry - PV_OFFSET); + rt_page_ref_inc(lvl2_dte, tbl->lvl2_bits); + } + else + { + rt_size_t dte_size; + + lvl2_dte = rt_pages_alloc(tbl->lvl2_bits); + + if (!lvl2_dte) + { + rt_free_align(map->itt); + rt_free(map); + return -RT_ENOMEM; + } + + dte_size = rt_page_bits(tbl->lvl2_bits); + rt_memset(lvl2_dte, 0, dte_size); + + if (!(tbl->val & GITS_BASER_SHARE_MASK_ALL)) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, lvl2_dte, dte_size); + } + + *entry = rt_cpu_to_le64((rt_uint64_t)rt_kmem_v2p(lvl2_dte) | GITS_BASER_VALID); + + if (!(tbl->val & GITS_BASER_SHARE_MASK_ALL)) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, entry, sizeof(*entry)); + } + + rt_hw_dsb(); + } + + map->lvl2_dte = lvl2_dte; + } + + rt_memset(map->itt, 0, itt_size); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, map->itt, itt_size); + } + msi_desc->priv = map; + + /* Alloc the LPI base on the first LPI */ + level = rt_spin_lock_irqsave(&lpis_lock); + hwirq_index = rt_bitmap_next_clear_bit(lpis_vectors, lpi_base, lpi_nr); + + if (hwirq_index >= lpi_nr) + { + irq = -RT_EEMPTY; + goto _out_lock; + } + + hwirq = 8192 + hwirq_index; + parent_irq = ppic->ops->irq_map(ppic, hwirq, RT_IRQ_MODE_EDGE_RISING); + if (parent_irq < 0) + { + irq = parent_irq; + goto _out_lock; + } + + irq = rt_pic_config_irq(pic, hwirq_index, hwirq); + if (irq < 0) + { + goto _out_lock; + } + pirq = rt_pic_find_irq(pic, hwirq_index); + + pirq->mode = RT_IRQ_MODE_EDGE_RISING; + rt_pic_cascade(pirq, parent_irq); + + rt_bitmap_set_bit(lpis_vectors, hwirq_index); + +_out_lock: + rt_spin_unlock_irqrestore(&lpis_lock, level); + + if (irq < 0) + { + return irq; + } + + if (map->its) + { + rt_ref_get(&map->ref); + } + else + { + rt_list_init(&map->list); + rt_ref_init(&map->ref); + map->its = its; + map->device_id = device_id; + map->lpi_base = hwirq; + + level = rt_spin_lock_irqsave(&map_lock); + rt_list_insert_before(&map_nodes, &map->list); + rt_spin_unlock_irqrestore(&map_lock, level); + } + + /* Default to CPU#0 */ + map->cpu_id = 0; + RT_IRQ_AFFINITY_SET(pirq->affinity, map->cpu_id); + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_MAPD); + its_encode_device_id(&cmd, device_id); + its_encode_size(&cmd, rt_ilog2(tbl->itt_entries) - 1); + its_encode_itt(&cmd, (rt_uint64_t)rt_kmem_v2p(map->itt)); + its_encode_valid(&cmd, RT_TRUE); + its_cmd_submit(its, &cmd, map, RT_FALSE); + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_MAPTI); + its_encode_device_id(&cmd, device_id); + its_encode_event_id(&cmd, its_pirq_event_id(its, pirq)); + its_encode_phys_id(&cmd, hwirq); + its_encode_collection(&cmd, its->collections[map->cpu_id].id); + its_cmd_submit(its, &cmd, map, RT_TRUE); + + return irq; +} + +static void its_map_release(struct rt_ref *r) +{ + rt_ubase_t level; + struct gicv3_its *its; + struct its_table *tbl; + struct its_command cmd; + struct its_map *map = rt_container_of(r, struct its_map, ref); + + its = map->its; + tbl = its_baser_type(its, GITS_BASER_TYPE_DEVICE); + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_MAPD); + its_encode_device_id(&cmd, map->device_id); + its_encode_size(&cmd, rt_ilog2(tbl->itt_entries) - 1); + its_encode_itt(&cmd, (rt_uint64_t)rt_kmem_v2p(map->itt)); + its_encode_valid(&cmd, RT_FALSE); + its_cmd_submit(its, &cmd, map, RT_TRUE); + + level = rt_spin_lock_irqsave(&map_lock); + rt_list_insert_before(&map_nodes, &map->list); + rt_spin_unlock_irqrestore(&map_lock, level); + + if (map->itt) + { + rt_free_align(map->itt); + } + if (map->lvl2_dte) + { + if (rt_page_ref_get(map->lvl2_dte, tbl->lvl2_bits) == 1) + { + rt_uint64_t *entry; + + entry = tbl->base + (map->device_id / (tbl->page_size / GITS_LVL1_ENTRY_SIZE)); + *entry = rt_cpu_to_le64(0); + + if (!(tbl->val & GITS_BASER_SHARE_MASK_ALL)) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, entry, sizeof(*entry)); + } + } + rt_pages_free(map->lvl2_dte, tbl->lvl2_bits); + } + rt_free(map); +} + +static void gicv3_its_irq_free_msi(struct rt_pic *pic, int irq) +{ + rt_ubase_t level; + struct its_map *map; + struct its_command cmd; + struct rt_pic_irq *pirq; + struct gicv3_its *its = raw_to_gicv3_its(pic); + + pirq = rt_pic_find_pirq(pic, irq); + + if (!pirq) + { + return; + } + + map = pirq->msi_desc->priv; + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_DISCARD); + its_encode_device_id(&cmd, map->device_id); + its_encode_event_id(&cmd, its_pirq_event_id(its, pirq)); + its_cmd_submit(its, &cmd, map, RT_TRUE); + + rt_pic_uncascade(pirq); + + level = rt_spin_lock_irqsave(&lpis_lock); + rt_bitmap_clear_bit(lpis_vectors, pirq->hwirq - 8192); + rt_spin_unlock_irqrestore(&lpis_lock, level); + + rt_ref_put(&map->ref, its_map_release); +} + +static rt_err_t gicv3_its_irq_set_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t state) +{ + struct its_map *map; + struct its_command cmd; + struct rt_pic_irq *pirq; + struct gicv3_its *its = raw_to_gicv3_its(pic); + + if (type != RT_IRQ_STATE_PENDING || hwirq > 8192 + lpi_nr) + { + return -RT_ENOSYS; + } + + if (!(pirq = rt_pic_find_irq(pic, hwirq - 8192))) + { + return -RT_ENOSYS; + } + + map = pirq->msi_desc->priv; + rt_memset(&cmd, 0, sizeof(cmd)); + + if (state) + { + its_encode_cmd(&cmd, GITS_CMD_INT); + its_encode_device_id(&cmd, map->device_id); + its_encode_event_id(&cmd, its_pirq_event_id(its, pirq)); + } + else + { + its_encode_cmd(&cmd, GITS_CMD_CLEAR); + its_encode_device_id(&cmd, map->device_id); + its_encode_event_id(&cmd, its_pirq_event_id(its, pirq)); + } + + its_cmd_submit(its, &cmd, map, RT_TRUE); + + return RT_EOK; +} + +const static struct rt_pic_ops gicv3_its_ops = +{ + .name = "GICv3-ITS", + .irq_init = gicv3_its_irq_init, + .irq_ack = rt_pic_irq_parent_ack, + .irq_mask = gicv3_its_irq_mask, + .irq_unmask = gicv3_its_irq_unmask, + .irq_eoi = rt_pic_irq_parent_eoi, + .irq_set_priority = gicv3_its_irq_set_priority, + .irq_set_affinity = gicv3_its_irq_set_affinity, + .irq_compose_msi_msg = gicv3_its_irq_compose_msi_msg, + .irq_alloc_msi = gicv3_its_irq_alloc_msi, + .irq_free_msi = gicv3_its_irq_free_msi, + .irq_set_state = gicv3_its_irq_set_state, + .flags = RT_PIC_F_IRQ_ROUTING, +}; + +static rt_ssize_t its_baser_page_size(struct gicv3_its *its, struct its_table *tbl) +{ + rt_size_t page_size = 64 * SIZE_KB; + + while (page_size) + { + rt_uint64_t val, baser_page_size; + rt_off_t baser = GITS_BASERn((int)(tbl - its->tbls)); + + val = its_readq(its, baser); + val &= ~GITS_BASER_PAGE_SIZE_MASK; + + switch (page_size) + { + case 64 * SIZE_KB: + baser_page_size = GITS_BASER_PAGE_SIZE_64K; + break; + case 16 * SIZE_KB: + baser_page_size = GITS_BASER_PAGE_SIZE_16K; + break; + case 4 * SIZE_KB: + default: + baser_page_size = GITS_BASER_PAGE_SIZE_4K; + break; + } + + baser_page_size >>= GITS_BASER_PAGE_SIZE_SHIFT; + + val |= RT_FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, baser_page_size); + its_writeq(its, baser, val); + tbl->val = its_readq(its, baser); + + if (RT_FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, tbl->val) == baser_page_size) + { + break; + } + + switch (page_size) + { + case 64 * SIZE_KB: + page_size = 16 * SIZE_KB; + break; + case 16 * SIZE_KB: + page_size = 4 * SIZE_KB; + break; + case 4 * SIZE_KB: + default: + return -RT_EINVAL; + } + } + + return page_size; +} + +static rt_err_t its_table_init(struct gicv3_its *its) +{ + int inited = 0; + rt_off_t baser; + rt_bool_t indirect = RT_FALSE; + rt_size_t pages_nr, alloc_size; + rt_uint64_t val, type, entry_size, share, cache; + struct its_table *tbl; + + share = GITS_BASER_InnerShareable; + cache = GITS_BASER_RaWaWb; + + for (int i = 0; i < RT_ARRAY_SIZE(its->tbls); ++i) + { + tbl = &its->tbls[i]; + + val = its_readq(its, GITS_BASERn(i)); + type = GITS_BASER_TYPE(val); + + if (type != GITS_BASER_TYPE_DEVICE && + type != GITS_BASER_TYPE_COLLECTION) + { + continue; + } + + tbl->page_size = its_baser_page_size(its, tbl); + + if (tbl->page_size < 0) + { + continue; + } + + baser = GITS_BASERn((int)(tbl - its->tbls)); + entry_size = GITS_BASER_ENTRY_SIZE(val); + + if (type == GITS_BASER_TYPE_DEVICE) + { + tbl->size_bits = its_device_id_bits(its); + LOG_D("Device Max IDs = %lu", 1UL << tbl->size_bits); + + /* For MSI-X */ + tbl->itt_entries = 2048; + while (MAX_HANDLERS / tbl->itt_entries < (1 << tbl->size_bits) && + tbl->itt_entries > 32) + { + tbl->itt_entries >>= 1; + } + } + + its_writeq(its, baser, tbl->val | GITS_BASER_INDIRECT); + tbl->val = its_readq(its, baser); + + indirect = !!(tbl->val & GITS_BASER_INDIRECT); + if (indirect && type == GITS_BASER_TYPE_DEVICE) + { + /* The size of the level 2 table is equal to ITS page size */ + tbl->lvl2_bits = tbl->size_bits - rt_ilog2(tbl->page_size / (int)entry_size); + + /* Get level 1 entries count */ + alloc_size = (1 << tbl->size_bits) / (tbl->page_size / entry_size); + alloc_size *= GITS_LVL1_ENTRY_SIZE; + } + else + { + alloc_size = (1 << tbl->size_bits) * entry_size; + indirect = RT_FALSE; + } + + tbl->base = rt_malloc_align(alloc_size, tbl->page_size); + pages_nr = alloc_size / tbl->page_size; + + if (!tbl->base) + { + return -RT_ENOMEM; + } + + if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) + { + cache = GITS_BASER_nCnB; + } + + if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) + { + cache = GITS_BASER_nC; + share = 0; + } + + val = ((rt_ubase_t)rt_kmem_v2p(tbl->base) | + (type << GITS_BASER_TYPE_SHIFT) | + ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | + (pages_nr << GITS_BASER_PAGES_SHIFT) | + cache | share | GITS_BASER_VALID); + val |= indirect ? GITS_BASER_INDIRECT : 0; + + switch (tbl->page_size) + { + case 4 * SIZE_KB: + val |= GITS_BASER_PAGE_SIZE_4K; + break; + case 16 * SIZE_KB: + val |= GITS_BASER_PAGE_SIZE_16K; + break; + case 64 * SIZE_KB: + val |= GITS_BASER_PAGE_SIZE_64K; + break; + } + + its_writeq(its, baser, val); + tbl->val = its_readq(its, baser); + + rt_memset(tbl->base, 0, alloc_size); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, tbl->base, alloc_size); + + cache = tbl->val & GITS_BASER_INNER_MASK_ALL; + share = tbl->val & GITS_BASER_SHARE_MASK_ALL; + + ++inited; + } + + return inited == 2 ? RT_EOK : -RT_ENOSYS; +} + +static rt_err_t its_cmd_queue_init(struct gicv3_its *its) +{ + void *cmd_phy_base; + rt_uint64_t baser, tmp; + + its->cmd_base = rt_malloc_align(ITS_CMD_QUEUE_SIZE, ITS_CMD_QUEUE_ALIGN); + + if (!its->cmd_base) + { + return -RT_ENOMEM; + } + + its->cmd_idx = 0; + rt_memset(its->cmd_base, 0, ITS_CMD_QUEUE_SIZE); + + cmd_phy_base = rt_kmem_v2p(its->cmd_base); + + baser = GITS_CBASER_VALID | GITS_CBASER_RaWaWb | GITS_CBASER_InnerShareable | \ + ((rt_uint64_t)cmd_phy_base) | (ITS_CMD_QUEUE_SIZE / (4 * SIZE_KB) - 1); + + its_writeq(its, GITS_CBASER, baser); + tmp = its_readq(its, GITS_CBASER); + + if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) + { + tmp &= ~GITS_CBASER_SHARE_MASK_ALL; + } + + if ((tmp ^ baser) & GITS_CBASER_SHARE_MASK_ALL) + { + if (!(tmp & GITS_CBASER_SHARE_MASK_ALL)) + { + /* The HW reports non-shareable, we must remove the cacheability attributes as well */ + baser &= ~(GITS_CBASER_SHARE_MASK_ALL | GITS_CBASER_INNER_MASK_ALL); + baser |= GITS_CBASER_nC; + + its_writeq(its, GITS_CBASER, baser); + } + + LOG_I("Using cache flushing for CMD queue"); + its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; + + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, its->cmd_base, ITS_CMD_QUEUE_SIZE); + } + + /* Get the next command from the start of the buffer */ + its_writeq(its, GITS_CWRITER, 0); + + return RT_EOK; +} + +static rt_err_t its_lpi_table_init(struct gicv3 *gic) +{ + rt_size_t lpi_table_size, lpi_pending_table_size; + rt_uint32_t numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic->gicd_typer); + + if (HWREG32(gicr_rd_base_percpu(gic) + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) + { + gic->redist_flags |= RDIST_FLAGS_RD_TABLES_PREALLOCATED; + gic->redist_flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; + + LOG_I("Using preallocated redistributor tables"); + } + + lpi_id_bits = GICD_TYPER_ID_BITS(gic->gicd_typer); + + if (gic->redist_flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) + { + rt_uint64_t val = HWREG64(gicr_rd_base_percpu(gic) + GICR_PROPBASER); + lpi_id_bits = rt_min_t(rt_uint32_t, lpi_id_bits, (val & GICR_PROPBASER_IDBITS_MASK) + 1); + } + + lpi_nr = rt_min_t(rt_size_t, (1UL << lpi_id_bits) - 8192, gic->lpi_nr); + lpi_id_bits = __rt_clz(lpi_nr + 8192); + + if (numlpis > 2 && numlpis > lpi_nr) + { + lpi_nr = numlpis; + LOG_W("Using hypervisor restricted LPI range [%u]", lpi_nr); + } + + gic->lpi_nr = lpi_nr; + + /* LPI Configuration table entry is 1 byte, Pending table bytes is N / 8. */ + lpi_table_size = RT_GENMASK(lpi_id_bits, 0); + lpi_pending_table_size = lpi_table_size / 8; + + lpi_table = rt_malloc_align(lpi_table_size, ITS_LPI_CONFIG_TABLE_ALIGN); + lpi_pending_table = rt_malloc_align(lpi_pending_table_size, ITS_LPI_PENDING_TABLE_ALIGN); + lpis_vectors = rt_calloc(1, RT_BITMAP_LEN(lpi_nr) * sizeof(rt_bitmap_t)); + + if (!lpi_table || !lpi_pending_table || !lpis_vectors) + { + if (lpi_table) + { + rt_free_align(lpi_table); + } + if (lpi_pending_table) + { + rt_free_align(lpi_pending_table); + } + if (lpis_vectors) + { + rt_free_align(lpis_vectors); + } + + lpi_table = RT_NULL; + lpi_pending_table = RT_NULL; + lpis_vectors = RT_NULL; + + return -RT_ENOMEM; + } + + /* Set the default configuration */ + rt_memset(lpi_table, ITS_LPI_CONFIG_PROP_DEFAULT_PRIO | GITS_LPI_CFG_GROUP1, lpi_table_size); + /* + * We should make a full mask size with lpi_id_bits, + * otherwise 'undefined' LPI will occur. + */ + rt_memset(lpi_pending_table, 0, lpi_pending_table_size); + + /* Flush the table to memory */ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, lpi_table, lpi_table_size); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, lpi_pending_table, lpi_pending_table_size); + + LOG_D("ITS: Allocator initialized for %u LPIs", lpi_nr); + + return RT_EOK; +} + +static void its_init_fail(struct gicv3_its *its) +{ + if (its->base) + { + rt_iounmap(its->base); + } + + if (its->cmd_base) + { + rt_free_align(its->cmd_base); + } + + for (int i = 0; i < RT_ARRAY_SIZE(its->tbls); ++i) + { + struct its_table *tbl = &its->tbls[i]; + + if (tbl->base) + { + rt_free_align(tbl->base); + } + } + + rt_list_remove(&its->list); + rt_free(its); +} + +static rt_err_t its_quirk_cavium_22375(void *data) +{ + struct gicv3_its *its = data; + + its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; + + return RT_EOK; +} + +static rt_err_t its_enable_rockchip(void *data) +{ + struct gicv3_its *its = data; + struct gicv3 *gic = its->gic; + + if (!rt_ofw_machine_is_compatible("rockchip,rk3566") && + !rt_ofw_machine_is_compatible("rockchip,rk3567") && + !rt_ofw_machine_is_compatible("rockchip,rk3568") && + !rt_ofw_machine_is_compatible("rockchip,rk3588") && + !rt_ofw_machine_is_compatible("rockchip,rk3588s")) + { + return -RT_EINVAL; + } + + its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE; + gic->redist_flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE; + + return RT_EOK; +} + +static rt_err_t its_set_non_coherent(void *data) +{ + struct gicv3_its *its = data; + + if (!rt_ofw_prop_read_bool(its->np, "dma-noncoherent")) + { + return -RT_EINVAL; + } + + its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE; + + return RT_EOK; +} + +static const struct gic_quirk _its_quirks[] = +{ + { + .desc = "ITS: Cavium ThunderX errata: 22375, 24313", + .iidr = 0xa100034c, + .iidr_mask = 0xffff0fff, + .init = its_quirk_cavium_22375, + }, + { + .desc = "ITS: Rockchip erratum RK3566 ~ RK3588", + .iidr = 0x0201743b, + .iidr_mask = 0xffffffff, + .init = its_enable_rockchip, + }, + { + .desc = "ITS: non-coherent attribute", + .compatible = "arm,gic-v3-its", + .init = its_set_non_coherent, + }, + { /* sentinel */ } +}; + +static const struct rt_ofw_node_id gicv3_its_ofw_match[] = +{ + { .compatible = "arm,gic-v3-its" }, + { /* sentinel */ } +}; + +rt_err_t gicv3_its_ofw_probe(struct rt_ofw_node *np, const struct rt_ofw_node_id *id) +{ + rt_err_t err = -RT_EEMPTY; + struct rt_ofw_node *its_np; + struct gicv3_its *its, *its_next; + + rt_ofw_foreach_available_child_node(np, its_np) + { + if (!rt_ofw_node_match(its_np, gicv3_its_ofw_match)) + { + continue; + } + + if (!rt_ofw_prop_read_bool(its_np, "msi-controller")) + { + continue; + } + + if (!(its = rt_calloc(1, sizeof(struct gicv3_its)))) + { + rt_ofw_node_put(its_np); + + err = -RT_ENOMEM; + goto _free_all; + } + + its->base = rt_ofw_iomap(its_np, 0); + + if (!its->base) + { + LOG_E("%s: IO map failed", rt_ofw_node_full_name(its_np)); + its_init_fail(its); + continue; + } + + /* + * Make sure ALL the ITS are reset before we probe any, + * as they may be sharing memory + */ + for (int i = 0; i < GITS_BASER_NR_REGS; ++i) + { + its_writeq(its, GITS_BASER + (i << 3), 0); + } + + its->np = its_np; + rt_list_init(&its->list); + rt_list_insert_before(&its_nodes, &its->list); + } + + if (!rt_list_isempty(&its_nodes)) + { + if ((err = its_lpi_table_init(rt_ofw_data(np)))) + { + goto _free_all; + } + } + + rt_list_for_each_entry_safe(its, its_next, &its_nodes, list) + { + rt_uint32_t ctlr; + + its->base_phy = rt_kmem_v2p(its->base); + its->gic = rt_ofw_data(np); + + gic_common_init_quirk_hw(HWREG32(its->base + GITS_IIDR), _its_quirks, its); + gic_common_init_quirk_ofw(its->np, _its_quirks, its); + + if ((err = its_cmd_queue_init(its))) + { + goto _fail; + } + rt_spin_lock_init(&its->cmd_lock); + + if ((err = its_table_init(its))) + { + goto _fail; + } + + for (int i = 0; i < RT_CPUS_NR; ++i) + { + its->collections[i].target_address = ~0ULL; + } + + ctlr = its_readl(its, GITS_CTLR); + ctlr |= GITS_CTLR_ENABLE; + its_writel(its, GITS_CTLR, ctlr); + + its->parent.priv_data = its; + its->parent.ops = &gicv3_its_ops; + + rt_pic_linear_irq(&its->parent, its->gic->lpi_nr); + rt_pic_user_extends(&its->parent); + + its_np = its->np; + rt_ofw_data(its_np) = &its->parent; + rt_ofw_node_set_flag(its_np, RT_OFW_F_READLY); + + continue; + + _fail: + its_init_fail(its); + + if (err == -RT_ENOMEM) + { + break; + } + } + + if (rt_list_isempty(&its_nodes) && lpis_vectors) + { + rt_free(lpis_vectors); + rt_free_align(lpi_table); + rt_free_align(lpi_pending_table); + lpis_vectors = RT_NULL; + } + + return err; + +_free_all: + rt_list_for_each_entry_safe(its, its_next, &its_nodes, list) + { + rt_free(its); + rt_list_remove(&its->list); + } + + return err; +} diff --git a/rt-thread/components/drivers/pic/pic-gicv3.c b/rt-thread/components/drivers/pic/pic-gicv3.c index c5e4bc7..7a11f35 100644 --- a/rt-thread/components/drivers/pic/pic-gicv3.c +++ b/rt-thread/components/drivers/pic/pic-gicv3.c @@ -216,6 +216,11 @@ static void gicv3_dist_init(void) LOG_D("%d SPIs implemented", _gic.line_nr - 32); LOG_D("%d Extended SPIs implemented", _gic.espi_nr); + if (_gic.skip_init) + { + goto _get_max_irq; + } + /* Disable the distributor */ HWREG32(base + GICD_CTLR) = 0; gicv3_dist_wait_for_rwp(); @@ -266,20 +271,26 @@ static void gicv3_dist_init(void) HWREG64(base + GICD_IROUTERnE + i * 8) = affinity; } - if (GICD_TYPER_NUM_LPIS(_gic.gicd_typer)) +_get_max_irq: + if (GICD_TYPER_NUM_LPIS(_gic.gicd_typer) > 1) { /* Max LPI = 8192 + Math.pow(2, num_LPIs + 1) - 1 */ - rt_size_t num_lpis = (1 << (GICD_TYPER_NUM_LPIS(_gic.gicd_typer) + 1)) + 1; + rt_size_t num_lpis = 1UL << (GICD_TYPER_NUM_LPIS(_gic.gicd_typer) + 1); - _gic.lpi_nr = rt_min_t(int, num_lpis, 1 << GICD_TYPER_ID_BITS(_gic.gicd_typer)); + _gic.lpi_nr = rt_min_t(int, num_lpis, 1UL << GICD_TYPER_ID_BITS(_gic.gicd_typer)); } else { - _gic.lpi_nr = 1 << GICD_TYPER_ID_BITS(_gic.gicd_typer); + _gic.lpi_nr = 1UL << GICD_TYPER_ID_BITS(_gic.gicd_typer); } /* SPI + eSPI + LPIs */ - _gic.irq_nr = _gic.line_nr - 32 + _gic.espi_nr + _gic.lpi_nr; + _gic.irq_nr = _gic.line_nr - 32 + _gic.espi_nr; +#ifdef RT_PIC_ARM_GIC_V3_ITS + /* ITS will allocate the same number of lpi PIRQs */ + _gic.lpi_nr = rt_min_t(rt_size_t, RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX, _gic.lpi_nr); + _gic.irq_nr += _gic.lpi_nr; +#endif } static void gicv3_redist_enable(rt_bool_t enable) @@ -389,6 +400,8 @@ static void gicv3_cpu_init(void) int cpu_id = rt_hw_cpu_id(); #ifdef ARCH_SUPPORT_HYP _gicv3_eoi_mode_ns = RT_TRUE; +#else + _gicv3_eoi_mode_ns = !!rt_ofw_bootargs_select("pic.gicv3_eoimode", 0); #endif base = gicv3_percpu_redist_sgi_base(); @@ -700,6 +713,7 @@ static int gicv3_irq_map(struct rt_pic *pic, int hwirq, rt_uint32_t mode) if (pirq && hwirq >= GIC_SGI_NR) { pirq->mode = mode; + pirq->priority = GICD_INT_DEF_PRI; switch (gicv3_hwirq_type(hwirq)) { @@ -708,7 +722,6 @@ static int gicv3_irq_map(struct rt_pic *pic, int hwirq, rt_uint32_t mode) break; case SPI_TYPE: case ESPI_TYPE: - pirq->priority = GICD_INT_DEF_PRI; RT_IRQ_AFFINITY_SET(pirq->affinity, _init_cpu_id); default: break; @@ -823,7 +836,18 @@ static rt_bool_t gicv3_handler(void *data) } else { - pirq = rt_pic_find_irq(&gic->parent, hwirq - GIC_SGI_NR); + int irq_index; + + if (hwirq < 8192) + { + irq_index = hwirq - GIC_SGI_NR; + } + else + { + irq_index = gic->irq_nr - gic->lpi_nr + hwirq - 8192; + } + + pirq = rt_pic_find_irq(&gic->parent, irq_index); } gicv3_irq_ack(pirq); @@ -1045,6 +1069,7 @@ static rt_err_t gicv3_ofw_init(struct rt_ofw_node *np, const struct rt_ofw_node_ redist_stride = 0; } _gic.redist_stride = redist_stride; + _gic.skip_init = rt_ofw_prop_read_bool(np, "skip-init"); gic_common_init_quirk_ofw(np, _gicv3_quirks, &_gic.parent); gicv3_init(); diff --git a/rt-thread/components/drivers/pic/pic-gicv3.h b/rt-thread/components/drivers/pic/pic-gicv3.h index 6046d9b..61c5ae1 100644 --- a/rt-thread/components/drivers/pic/pic-gicv3.h +++ b/rt-thread/components/drivers/pic/pic-gicv3.h @@ -12,8 +12,8 @@ * 2023-02-01 GuEe-GUI move macros to header */ -#ifndef __IRQ_GICV3_H__ -#define __IRQ_GICV3_H__ +#ifndef __PIC_GICV3_H__ +#define __PIC_GICV3_H__ #include @@ -101,6 +101,8 @@ #define GICR_CTLR_IR (1UL << 2) #define GICR_CTLR_RWP (1UL << 3) +#define GICR_TYPER_CPU_NO(r) (((r) >> 8) & 0xffff) + #define GICR_RD_BASE_SIZE (64 * SIZE_KB) #define GICR_SGI_OFFSET (64 * SIZE_KB) #define GICR_SGI_BASE_SIZE GICR_SGI_OFFSET @@ -152,66 +154,142 @@ #define GITS_CTLR 0x0000 #define GITS_IIDR 0x0004 #define GITS_TYPER 0x0008 -#define GITS_MPAMIDR 0x0010 -#define GITS_PARTIDR 0x0014 #define GITS_MPIDR 0x0018 -#define GITS_STATUSR 0x0040 -#define GITS_UMSIR 0x0048 -#define GITS_CBASER 0x0048 +#define GITS_CBASER 0x0080 #define GITS_CWRITER 0x0088 #define GITS_CREADR 0x0090 -#define GITS_BASER 0x0100 /* 0x0100~0x0138 */ +#define GITS_BASER 0x0100 +#define GITS_IDREGS_BASE 0xffd0 +#define GITS_PIDR0 0xffe0 +#define GITS_PIDR1 0xffe4 +#define GITS_PIDR2 GICR_PIDR2 +#define GITS_PIDR4 0xffd0 +#define GITS_CIDR0 0xfff0 +#define GITS_CIDR1 0xfff4 +#define GITS_CIDR2 0xfff8 +#define GITS_CIDR3 0xfffc + +#define GITS_TRANSLATER 0x10040 + +#define GITS_SGIR 0x20020 + +#define GITS_SGIR_VPEID RT_GENMASK_ULL(47, 32) +#define GITS_SGIR_VINTID RT_GENMASK_ULL(3, 0) + +#define GITS_CTLR_ENABLE (1U << 0) +#define GITS_CTLR_ImDe (1U << 1) +#define GITS_CTLR_ITS_NUMBER_SHIFT 4 +#define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT) +#define GITS_CTLR_QUIESCENT (1U << 31) + +#define GITS_TYPER_PLPIS (1UL << 0) +#define GITS_TYPER_VLPIS (1UL << 1) +#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 +#define GITS_TYPER_ITT_ENTRY_SIZE RT_GENMASK_ULL(7, 4) +#define GITS_TYPER_IDBITS_SHIFT 8 +#define GITS_TYPER_DEVBITS_SHIFT 13 +#define GITS_TYPER_DEVBITS RT_GENMASK_ULL(17, 13) +#define GITS_TYPER_PTA (1UL << 19) +#define GITS_TYPER_HCC_SHIFT 24 +#define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff) +#define GITS_TYPER_VMOVP (1ULL << 37) +#define GITS_TYPER_VMAPP (1ULL << 40) +#define GITS_TYPER_SVPET RT_GENMASK_ULL(42, 41) /* * ITS commands */ -#define GITS_CMD_MAPD 0x08 -#define GITS_CMD_MAPC 0x09 -#define GITS_CMD_MAPTI 0x0a -#define GITS_CMD_MAPI 0x0b -#define GITS_CMD_MOVI 0x01 -#define GITS_CMD_DISCARD 0x0f -#define GITS_CMD_INV 0x0c -#define GITS_CMD_MOVALL 0x0e -#define GITS_CMD_INVALL 0x0d -#define GITS_CMD_INT 0x03 -#define GITS_CMD_CLEAR 0x04 -#define GITS_CMD_SYNC 0x05 +#define GITS_CMD_MAPD 0x08 +#define GITS_CMD_MAPC 0x09 +#define GITS_CMD_MAPTI 0x0a +#define GITS_CMD_MAPI 0x0b +#define GITS_CMD_MOVI 0x01 +#define GITS_CMD_DISCARD 0x0f +#define GITS_CMD_INV 0x0c +#define GITS_CMD_MOVALL 0x0e +#define GITS_CMD_INVALL 0x0d +#define GITS_CMD_INT 0x03 +#define GITS_CMD_CLEAR 0x04 +#define GITS_CMD_SYNC 0x05 /* ITS Config Area */ -#define GITS_LPI_CFG_GROUP1 (1 << 1) -#define GITS_LPI_CFG_ENABLED (1 << 0) +#define GITS_LPI_CFG_GROUP1 (1 << 1) +#define GITS_LPI_CFG_ENABLED (1 << 0) /* ITS Command Queue Descriptor */ +#define GITS_BASER_SHAREABILITY_SHIFT 10 +#define GITS_BASER_INNER_CACHEABILITY_SHIFT 59 +#define GITS_BASER_OUTER_CACHEABILITY_SHIFT 53 #define GITS_CBASER_VALID (1UL << 63) -#define GITS_CBASER_SHAREABILITY_SHIFT (10) -#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59) -#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53) +#define GITS_CBASER_SHAREABILITY_SHIFT 10 +#define GITS_CBASER_INNER_CACHEABILITY_SHIFT 59 +#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT 53 +#define GICR_PBASER_SHAREABILITY_SHIFT 10 +#define GICR_PBASER_INNER_CACHEABILITY_SHIFT 7 +#define GICR_PBASER_OUTER_CACHEABILITY_SHIFT 56 -#define GITS_TRANSLATION_TABLE_DESCRIPTORS_NR 8 +#define GITS_BASER_NR_REGS 8 +#define GITS_BASERn(idx) (GITS_BASER + sizeof(rt_uint64_t) * idx) + +#define GITS_BASER_VALID (1ULL << 63) +#define GITS_BASER_INDIRECT (1ULL << 62) +#define GITS_BASER_TYPE_SHIFT 56 +#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) +#define GITS_BASER_ENTRY_SIZE_SHIFT 48 +#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1) +#define GITS_BASER_PAGE_SIZE_SHIFT 8 +#define GITS_BASER_PAGE_SIZE_4K (0ULL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_16K (1ULL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_64K (2ULL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_MASK (3ULL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGES_SHIFT 0 + +#define GITS_LVL1_ENTRY_SIZE 8UL + +#define GITS_BASER_TYPE_NONE 0 +#define GITS_BASER_TYPE_DEVICE 1 +#define GITS_BASER_TYPE_VPE 2 +#define GITS_BASER_TYPE_RESERVED3 3 +#define GITS_BASER_TYPE_COLLECTION 4 +#define GITS_BASER_TYPE_RESERVED5 5 +#define GITS_BASER_TYPE_RESERVED6 6 +#define GITS_BASER_TYPE_RESERVED7 7 #define GITS_BASER_CACHEABILITY(reg, inner_outer, type) \ - (GITS_CBASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) + (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) #define GITS_BASER_SHAREABILITY(reg, type) \ - (GITS_CBASER_##type << reg##_SHAREABILITY_SHIFT) + (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) -#define GITS_CBASER_CACHE_DnGnRnE 0x0UL /* Device-nGnRnE. */ -#define GITS_CBASER_CACHE_NIN 0x1UL /* Normal Inner Non-cacheable. */ -#define GITS_CBASER_CACHE_NIRAWT 0x2UL /* Normal Inner Cacheable Read-allocate, Write-through. */ -#define GITS_CBASER_CACHE_NIRAWB 0x3UL /* Normal Inner Cacheable Read-allocate, Write-back. */ -#define GITS_CBASER_CACHE_NIWAWT 0x4UL /* Normal Inner Cacheable Write-allocate, Write-through. */ -#define GITS_CBASER_CACHE_NIWAWB 0x5UL /* Normal Inner Cacheable Write-allocate, Write-back. */ -#define GITS_CBASER_CACHE_NIRAWAWT 0x6UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. */ -#define GITS_CBASER_CACHE_NIRAWAWB 0x7UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. */ -#define GITS_CBASER_CACHE_MASK 0x7UL -#define GITS_CBASER_SHARE_NS 0x0UL /* Non-shareable. */ -#define GITS_CBASER_SHARE_IS 0x1UL /* Inner Shareable. */ -#define GITS_CBASER_SHARE_OS 0x2UL /* Outer Shareable. */ -#define GITS_CBASER_SHARE_RES 0x3UL /* Reserved. Treated as 0b00 */ -#define GITS_CBASER_SHARE_MASK 0x3UL +#define GIC_BASER_CACHE_DnGnRnE 0x0UL /* Device-nGnRnE. */ +#define GIC_BASER_CACHE_NIN 0x1UL /* Normal Inner Non-cacheable. */ +#define GIC_BASER_CACHE_NIRAWT 0x2UL /* Normal Inner Cacheable Read-allocate, Write-through. */ +#define GIC_BASER_CACHE_NIRAWB 0x3UL /* Normal Inner Cacheable Read-allocate, Write-back. */ +#define GIC_BASER_CACHE_NIWAWT 0x4UL /* Normal Inner Cacheable Write-allocate, Write-through. */ +#define GIC_BASER_CACHE_NIWAWB 0x5UL /* Normal Inner Cacheable Write-allocate, Write-back. */ +#define GIC_BASER_CACHE_NIRAWAWT 0x6UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. */ +#define GIC_BASER_CACHE_NIRAWAWB 0x7UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. */ +#define GIC_BASER_CACHE_MASK 0x7UL +#define GIC_BASER_SHARE_NS 0x0UL /* Non-shareable. */ +#define GIC_BASER_SHARE_IS 0x1UL /* Inner Shareable. */ +#define GIC_BASER_SHARE_OS 0x2UL /* Outer Shareable. */ +#define GIC_BASER_SHARE_RES 0x3UL /* Reserved. Treated as 0b00 */ +#define GIC_BASER_SHARE_MASK 0x3UL + +#define GITS_BASER_InnerShareable GITS_BASER_SHAREABILITY(GITS_BASER, SHARE_IS) +#define GITS_BASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GITS_BASER, SHARE_MASK) +#define GITS_BASER_INNER_MASK_ALL GITS_BASER_CACHEABILITY(GITS_BASER, INNER, MASK) +#define GITS_BASER_nCnB GITS_BASER_CACHEABILITY(GITS_BASER, INNER, DnGnRnE) +#define GITS_BASER_nC GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIN) +#define GITS_BASER_RaWt GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWT) +#define GITS_BASER_RaWb GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWB) +#define GITS_BASER_WaWt GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIWAWT) +#define GITS_BASER_WaWb GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIWAWB) +#define GITS_BASER_RaWaWt GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWAWT) +#define GITS_BASER_RaWaWb GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWAWB) #define GITS_CBASER_InnerShareable GITS_BASER_SHAREABILITY(GITS_CBASER, SHARE_IS) #define GITS_CBASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GITS_CBASER, SHARE_MASK) +#define GITS_CBASER_INNER_MASK_ALL GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK) #define GITS_CBASER_nCnB GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, DnGnRnE) #define GITS_CBASER_nC GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIN) #define GITS_CBASER_RaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWT) @@ -221,6 +299,18 @@ #define GITS_CBASER_RaWaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWAWT) #define GITS_CBASER_RaWaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWAWB) +#define GICR_PBASER_InnerShareable GITS_BASER_SHAREABILITY(GICR_PBASER, SHARE_IS) +#define GICR_PBASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GICR_PBASER, SHARE_MASK) +#define GICR_PBASER_INNER_MASK_ALL GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, MASK) +#define GICR_PBASER_nCnB GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, DnGnRnE) +#define GICR_PBASER_nC GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIN) +#define GICR_PBASER_RaWt GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWT) +#define GICR_PBASER_RaWb GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWB) +#define GICR_PBASER_WaWt GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIWAWT) +#define GICR_PBASER_WaWb GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIWAWB) +#define GICR_PBASER_RaWaWt GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWAWT) +#define GICR_PBASER_RaWaWb GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWAWB) + #define GIC_EPPI_BASE_INTID 1056 #define GIC_ESPI_BASE_INTID 4096 @@ -283,6 +373,7 @@ struct gicv3 rt_size_t dist_size; void *redist_percpu_base[RT_CPUS_NR]; + rt_uint64_t redist_percpu_flags[RT_CPUS_NR]; rt_size_t percpu_ppi_nr[RT_CPUS_NR]; struct @@ -294,6 +385,8 @@ struct gicv3 rt_uint64_t redist_flags; rt_size_t redist_stride; rt_size_t redist_regions_nr; + + rt_bool_t skip_init; }; -#endif /* __IRQ_GICV3_H__ */ +#endif /* __PIC_GICV3_H__ */ diff --git a/rt-thread/components/drivers/pic/pic.c b/rt-thread/components/drivers/pic/pic.c index 4525c7d..032c965 100644 --- a/rt-thread/components/drivers/pic/pic.c +++ b/rt-thread/components/drivers/pic/pic.c @@ -16,7 +16,9 @@ #include #include +#ifdef RT_USING_PIC_STATISTICS #include +#endif struct irq_traps { @@ -31,6 +33,7 @@ static int _ipi_hash[] = #ifdef RT_USING_SMP [RT_SCHEDULE_IPI] = RT_SCHEDULE_IPI, [RT_STOP_IPI] = RT_STOP_IPI, + [RT_SMP_CALL_IPI] = RT_SMP_CALL_IPI, #endif }; @@ -173,19 +176,52 @@ rt_err_t rt_pic_linear_irq(struct rt_pic *pic, rt_size_t irq_nr) return err; } +rt_err_t rt_pic_cancel_irq(struct rt_pic *pic) +{ + rt_err_t err = RT_EOK; + + if (pic && pic->pirqs) + { + rt_ubase_t level = rt_spin_lock_irqsave(&_pic_lock); + + /* + * This is only to make system runtime safely, + * we don't recommend PICs to unregister. + */ + rt_list_remove(&pic->list); + + rt_spin_unlock_irqrestore(&_pic_lock, level); + } + else + { + err = -RT_EINVAL; + } + + return err; +} + static void config_pirq(struct rt_pic *pic, struct rt_pic_irq *pirq, int irq, int hwirq) { rt_ubase_t level = rt_spin_lock_irqsave(&pirq->rw_lock); + if (pirq->irq < 0) + { + rt_list_init(&pirq->list); + rt_list_init(&pirq->children_nodes); + rt_list_init(&pirq->isr.list); + } + else if (pirq->pic != pic) + { + RT_ASSERT(rt_list_isempty(&pirq->list) == RT_TRUE); + RT_ASSERT(rt_list_isempty(&pirq->children_nodes) == RT_TRUE); + RT_ASSERT(rt_list_isempty(&pirq->isr.list) == RT_TRUE); + } + pirq->irq = irq; pirq->hwirq = hwirq; pirq->pic = pic; - rt_list_init(&pirq->list); - rt_list_init(&pirq->children_nodes); - rt_list_init(&pirq->isr.list); - rt_spin_unlock_irqrestore(&pirq->rw_lock, level); } @@ -494,6 +530,8 @@ rt_err_t rt_pic_do_traps(void) rt_err_t err = -RT_ERROR; struct irq_traps *traps; + rt_interrupt_enter(); + rt_list_for_each_entry(traps, &_traps_nodes, list) { if (traps->handler(traps->data)) @@ -504,6 +542,8 @@ rt_err_t rt_pic_do_traps(void) } } + rt_interrupt_leave(); + return err; } @@ -535,11 +575,17 @@ rt_err_t rt_pic_handle_isr(struct rt_pic_irq *pirq) rt_list_for_each_entry(child, &pirq->children_nodes, list) { - rt_pic_irq_ack(child->irq); + if (child->pic->ops->irq_ack) + { + child->pic->ops->irq_ack(child); + } err = rt_pic_handle_isr(child); - rt_pic_irq_eoi(child->irq); + if (child->pic->ops->irq_eoi) + { + child->pic->ops->irq_eoi(child); + } } } diff --git a/rt-thread/components/drivers/pin/Kconfig b/rt-thread/components/drivers/pin/Kconfig index 24a2c02..2520897 100644 --- a/rt-thread/components/drivers/pin/Kconfig +++ b/rt-thread/components/drivers/pin/Kconfig @@ -1,3 +1,7 @@ menuconfig RT_USING_PIN bool "Using Generic GPIO device drivers" default y + +if RT_USING_PIN + osource "$(SOC_DM_PIN_DIR)/Kconfig" +endif diff --git a/rt-thread/components/drivers/pin/SConscript b/rt-thread/components/drivers/pin/SConscript index bdad848..69e3b53 100644 --- a/rt-thread/components/drivers/pin/SConscript +++ b/rt-thread/components/drivers/pin/SConscript @@ -8,13 +8,13 @@ if not GetDepend(['RT_USING_PIN']): cwd = GetCurrentDir() CPPPATH = [cwd + '/../include'] -src = ['pin.c'] +src = ['dev_pin.c'] if GetDepend(['RT_USING_DM']): - src += ['pin_dm.c'] + src += ['dev_pin_dm.c'] if GetDepend(['RT_USING_OFW']): - src += ['pin_ofw.c'] + src += ['dev_pin_ofw.c'] group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) diff --git a/rt-thread/components/drivers/pin/pin.c b/rt-thread/components/drivers/pin/dev_pin.c similarity index 96% rename from rt-thread/components/drivers/pin/pin.c rename to rt-thread/components/drivers/pin/dev_pin.c index 303fb25..4403557 100644 --- a/rt-thread/components/drivers/pin/pin.c +++ b/rt-thread/components/drivers/pin/dev_pin.c @@ -10,7 +10,7 @@ * 2022-04-29 WangQiang add pin operate command in MSH */ -#include +#include static struct rt_device_pin _hw_pin; static rt_ssize_t _pin_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) @@ -132,6 +132,16 @@ rt_err_t rt_pin_irq_enable(rt_base_t pin, rt_uint8_t enabled) return -RT_ENOSYS; } +rt_err_t rt_pin_debounce(rt_base_t pin, rt_uint32_t debounce) +{ + RT_ASSERT(_hw_pin.ops != RT_NULL); + if (_hw_pin.ops->pin_debounce) + { + return _hw_pin.ops->pin_debounce(&_hw_pin.parent, pin, debounce); + } + return -RT_ENOSYS; +} + /* RT-Thread Hardware PIN APIs */ void rt_pin_mode(rt_base_t pin, rt_uint8_t mode) { diff --git a/rt-thread/components/drivers/pin/dev_pin_dm.c b/rt-thread/components/drivers/pin/dev_pin_dm.c new file mode 100644 index 0000000..90cca94 --- /dev/null +++ b/rt-thread/components/drivers/pin/dev_pin_dm.c @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-11-26 GuEe-GUI first version + */ + +#include "dev_pin_dm.h" + +static rt_size_t pin_total_nr = 0; +static struct rt_spinlock pin_lock = {}; +static rt_list_t pin_nodes = RT_LIST_OBJECT_INIT(pin_nodes); + +static struct rt_device_pin *pin_device_find(rt_ubase_t pin) +{ + struct rt_device_pin *gpio = RT_NULL, *gpio_tmp; + + rt_spin_lock(&pin_lock); + + rt_list_for_each_entry(gpio_tmp, &pin_nodes, list) + { + if (pin >= gpio_tmp->pin_start && + pin - gpio_tmp->pin_start < gpio_tmp->pin_nr) + { + gpio = gpio_tmp; + break; + } + } + + rt_spin_unlock(&pin_lock); + + return gpio; +} + +static void pin_api_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode) +{ + struct rt_device_pin *gpio = pin_device_find(pin); + + if (gpio && gpio->ops->pin_mode) + { + gpio->ops->pin_mode(&gpio->parent, pin - gpio->pin_start, mode); + } +} + +static void pin_api_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value) +{ + struct rt_device_pin *gpio = pin_device_find(pin); + + if (gpio && gpio->ops->pin_write) + { + gpio->ops->pin_write(&gpio->parent, pin - gpio->pin_start, value); + } +} + +static rt_ssize_t pin_api_read(struct rt_device *device, rt_base_t pin) +{ + struct rt_device_pin *gpio = pin_device_find(pin); + + if (gpio && gpio->ops->pin_read) + { + return gpio->ops->pin_read(&gpio->parent, pin - gpio->pin_start); + } + + return -RT_EINVAL; +} + +static rt_err_t pin_api_attach_irq(struct rt_device *device, rt_base_t pin, + rt_uint8_t mode, void (*hdr)(void *args), void *args) +{ + struct rt_device_pin *gpio = pin_device_find(pin); + + if (gpio) + { + rt_base_t pin_index = pin - gpio->pin_start; + + if (!gpio->ops->pin_attach_irq) + { + rt_err_t err; + struct rt_pin_irq_hdr *legacy_isr; + + if ((err = gpio->ops->pin_irq_mode(&gpio->parent, pin_index, mode))) + { + return err; + } + + legacy_isr = &gpio->legacy_isr[pin_index]; + legacy_isr->pin = pin_index; + legacy_isr->mode = mode; + legacy_isr->hdr = hdr; + legacy_isr->args = args; + + return RT_EOK; + } + else + { + return gpio->ops->pin_attach_irq(&gpio->parent, pin_index, mode, hdr, args); + } + } + + return -RT_EINVAL; +} + +static rt_err_t pin_api_detach_irq(struct rt_device *device, rt_base_t pin) +{ + struct rt_device_pin *gpio = pin_device_find(pin); + + if (gpio) + { + rt_base_t pin_index = pin - gpio->pin_start; + + if (!gpio->ops->pin_detach_irq) + { + struct rt_pin_irq_hdr *legacy_isr; + + legacy_isr = &gpio->legacy_isr[pin_index]; + rt_memset(legacy_isr, 0, sizeof(*legacy_isr)); + + return RT_EOK; + } + else + { + return gpio->ops->pin_detach_irq(&gpio->parent, pin); + } + } + + return -RT_EINVAL; +} + +static rt_err_t pin_api_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint8_t enabled) +{ + struct rt_device_pin *gpio = pin_device_find(pin); + + if (gpio && gpio->ops->pin_irq_enable) + { + return gpio->ops->pin_irq_enable(&gpio->parent, pin - gpio->pin_start, enabled); + } + + return -RT_EINVAL; +} + +static rt_base_t pin_api_get(const char *name) +{ + rt_base_t res = -RT_EINVAL; + struct rt_device_pin *gpio; + + rt_spin_lock(&pin_lock); + + rt_list_for_each_entry(gpio, &pin_nodes, list) + { + if (gpio->ops->pin_get && !(res = gpio->ops->pin_get(name))) + { + break; + } + } + + rt_spin_unlock(&pin_lock); + + return res; +} + +static rt_err_t pin_api_debounce(struct rt_device *device, rt_base_t pin, + rt_uint32_t debounce) +{ + struct rt_device_pin *gpio = pin_device_find(pin); + + if (gpio && gpio->ops->pin_debounce) + { + return gpio->ops->pin_debounce(&gpio->parent, pin - gpio->pin_start, debounce); + } + + return -RT_EINVAL; +} + +static rt_err_t pin_api_irq_mode(struct rt_device *device, rt_base_t pin, + rt_uint8_t mode) +{ + struct rt_device_pin *gpio = pin_device_find(pin); + + if (gpio && gpio->ops->pin_irq_mode) + { + return gpio->ops->pin_irq_mode(&gpio->parent, pin - gpio->pin_start, mode); + } + + return -RT_EINVAL; +} + +static const struct rt_pin_ops pin_api_dm_ops = +{ + .pin_mode = pin_api_mode, + .pin_write = pin_api_write, + .pin_read = pin_api_read, + .pin_attach_irq = pin_api_attach_irq, + .pin_detach_irq = pin_api_detach_irq, + .pin_irq_enable = pin_api_irq_enable, + .pin_get = pin_api_get, + .pin_debounce = pin_api_debounce, + .pin_irq_mode = pin_api_irq_mode, +}; + +rt_err_t pin_api_init(struct rt_device_pin *gpio, rt_size_t pin_nr) +{ + rt_err_t err = RT_EOK; + + if (!gpio || !gpio->ops) + { + return -RT_EINVAL; + } + + rt_spin_lock(&pin_lock); + + if (rt_list_isempty(&pin_nodes)) + { + rt_spin_unlock(&pin_lock); + rt_device_pin_register("gpio", &pin_api_dm_ops, RT_NULL); + rt_spin_lock(&pin_lock); + } + + gpio->pin_start = pin_total_nr; + gpio->pin_nr = pin_nr; + pin_total_nr += pin_nr; + + rt_list_init(&gpio->list); + rt_list_insert_before(&pin_nodes, &gpio->list); + + rt_spin_unlock(&pin_lock); + + return err; +} + +static void pin_dm_irq_mask(struct rt_pic_irq *pirq) +{ + struct rt_device_pin *gpio = pirq->pic->priv_data; + + gpio->ops->pin_irq_enable(&gpio->parent, pirq->hwirq, 0); +} + +static void pin_dm_irq_unmask(struct rt_pic_irq *pirq) +{ + struct rt_device_pin *gpio = pirq->pic->priv_data; + + gpio->ops->pin_irq_enable(&gpio->parent, pirq->hwirq, 1); +} + +static rt_err_t pin_dm_irq_set_triger_mode(struct rt_pic_irq *pirq, rt_uint32_t mode) +{ + rt_uint8_t pin_mode; + struct rt_device_pin *gpio = pirq->pic->priv_data; + + switch (mode) + { + case RT_IRQ_MODE_EDGE_RISING: + pin_mode = PIN_IRQ_MODE_RISING; + break; + + case RT_IRQ_MODE_EDGE_FALLING: + pin_mode = PIN_IRQ_MODE_FALLING; + break; + + case RT_IRQ_MODE_EDGE_BOTH: + pin_mode = PIN_IRQ_MODE_RISING_FALLING; + break; + + case RT_IRQ_MODE_LEVEL_HIGH: + pin_mode = PIN_IRQ_MODE_HIGH_LEVEL; + break; + + case RT_IRQ_MODE_LEVEL_LOW: + pin_mode = PIN_IRQ_MODE_LOW_LEVEL; + break; + + default: + return -RT_ENOSYS; + } + + return gpio->ops->pin_irq_mode(&gpio->parent, pirq->hwirq, pin_mode); +} + +static int pin_dm_irq_map(struct rt_pic *pic, int hwirq, rt_uint32_t mode) +{ + int irq = -1; + struct rt_device_pin *gpio = pic->priv_data; + struct rt_pic_irq *pirq = rt_pic_find_irq(pic, hwirq); + + if (pirq) + { + irq = rt_pic_config_irq(pic, hwirq, hwirq); + + if (irq >= 0) + { + rt_pic_cascade(pirq, gpio->irqchip.irq); + rt_pic_irq_set_triger_mode(irq, mode); + } + } + + return irq; +} + +static rt_err_t pin_dm_irq_parse(struct rt_pic *pic, + struct rt_ofw_cell_args *args, struct rt_pic_irq *out_pirq) +{ + rt_err_t err = RT_EOK; + + if (args->args_count == 2) + { + out_pirq->hwirq = args->args[0]; + out_pirq->mode = args->args[1] & RT_IRQ_MODE_MASK; + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +const static struct rt_pic_ops pin_dm_ops = +{ + .name = "GPIO", + .irq_enable = pin_dm_irq_mask, + .irq_disable = pin_dm_irq_unmask, + .irq_mask = pin_dm_irq_mask, + .irq_unmask = pin_dm_irq_unmask, + .irq_set_triger_mode = pin_dm_irq_set_triger_mode, + .irq_map = pin_dm_irq_map, + .irq_parse = pin_dm_irq_parse, +}; + +rt_err_t pin_pic_handle_isr(struct rt_device_pin *gpio, rt_base_t pin) +{ + rt_err_t err; + + if (gpio) + { + rt_ubase_t pin_index = pin; + struct rt_pin_irqchip *irqchip = &gpio->irqchip; + + if (pin_index < gpio->pin_nr) + { + struct rt_pic_irq *pirq; + struct rt_pin_irq_hdr *legacy_isr; + + pirq = rt_pic_find_irq(&irqchip->parent, pin_index); + + if (pirq->irq >= 0) + { + err = rt_pic_handle_isr(pirq); + } + else + { + err = -RT_EINVAL; + } + + legacy_isr = &gpio->legacy_isr[pin_index]; + + if (legacy_isr->hdr) + { + legacy_isr->hdr(legacy_isr->args); + } + } + else + { + err = -RT_EINVAL; + } + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_err_t pin_pic_init(struct rt_device_pin *gpio, int pin_irq) +{ + rt_err_t err; + + if (gpio) + { + struct rt_pin_irqchip *irqchip = &gpio->irqchip; + struct rt_pic *pic = &irqchip->parent; + + irqchip->irq = pin_irq; + + if (!gpio->pin_nr) + { + return -RT_EINVAL; + } + + gpio->legacy_isr = rt_calloc(gpio->pin_nr, sizeof(*gpio->legacy_isr)); + + if (!gpio->legacy_isr) + { + return -RT_ENOMEM; + } + + pic->priv_data = gpio; + pic->ops = &pin_dm_ops; + /* Make sure the type of gpio for pic */ + gpio->parent.parent.type = RT_Object_Class_Device; + rt_pic_default_name(&irqchip->parent); + + err = rt_pic_linear_irq(pic, gpio->pin_nr); + rt_pic_user_extends(pic); + + err = RT_EOK; + } + else + { + err = -RT_EINVAL; + } + + return err; +} + +rt_ssize_t rt_pin_get_named_pin(struct rt_device *dev, const char *propname, int index, + rt_uint8_t *out_mode, rt_uint8_t *out_value) +{ + rt_ssize_t res = -RT_ENOSYS; + + RT_ASSERT(dev != RT_NULL); + +#ifdef RT_USING_OFW + if (dev->ofw_node) + { + res = rt_ofw_get_named_pin(dev->ofw_node, propname, index, out_mode, out_value); + } + else + { + res = -RT_EINVAL; + } +#endif /* RT_USING_OFW */ + + return res; +} + +rt_ssize_t rt_pin_get_named_pin_count(struct rt_device *dev, const char *propname) +{ + rt_ssize_t count = -RT_ENOSYS; + + RT_ASSERT(dev != RT_NULL); + +#ifdef RT_USING_OFW + if (dev->ofw_node) + { + count = rt_ofw_get_named_pin_count(dev->ofw_node, propname); + } + else + { + count = -RT_EINVAL; + } +#endif /* RT_USING_OFW */ + + return count; +} diff --git a/rt-thread/components/drivers/pin/pin_dm.h b/rt-thread/components/drivers/pin/dev_pin_dm.h similarity index 70% rename from rt-thread/components/drivers/pin/pin_dm.h rename to rt-thread/components/drivers/pin/dev_pin_dm.h index b5146a2..09374ca 100644 --- a/rt-thread/components/drivers/pin/pin_dm.h +++ b/rt-thread/components/drivers/pin/dev_pin_dm.h @@ -15,7 +15,9 @@ #include #include -rt_err_t pin_pic_handle_isr(struct rt_device_pin *gpio, rt_base_t pin); -rt_err_t pin_pic_init(struct rt_device_pin *gpio); +rt_err_t pin_api_init(struct rt_device_pin *gpio, rt_size_t pin_nr); -#endif /* __PIN_DM_H__ */ +rt_err_t pin_pic_init(struct rt_device_pin *gpio, int pin_irq); +rt_err_t pin_pic_handle_isr(struct rt_device_pin *gpio, rt_base_t pin); + +#endif /* __DEV_PIN_DM_H__ */ diff --git a/rt-thread/components/drivers/pin/pin_ofw.c b/rt-thread/components/drivers/pin/dev_pin_ofw.c similarity index 87% rename from rt-thread/components/drivers/pin/pin_ofw.c rename to rt-thread/components/drivers/pin/dev_pin_ofw.c index 29d29d4..fbf0538 100644 --- a/rt-thread/components/drivers/pin/pin_ofw.c +++ b/rt-thread/components/drivers/pin/dev_pin_ofw.c @@ -10,7 +10,7 @@ #include -#include "pin_dm.h" +#include "dev_pin_dm.h" static const char * const gpio_suffixes[] = { @@ -59,6 +59,12 @@ rt_ssize_t rt_ofw_get_named_pin(struct rt_ofw_node *np, const char *propname, in } pin_dev_np = pin_args.data; + + if (!rt_ofw_data(pin_dev_np)) + { + rt_platform_ofw_request(pin_dev_np); + } + pin_dev = rt_ofw_data(pin_dev_np); if (!pin_dev) @@ -111,11 +117,11 @@ rt_ssize_t rt_ofw_get_named_pin(struct rt_ofw_node *np, const char *propname, in if (out_value) { - if (flags == (PIN_ACTIVE_HIGH | PIN_PUSH_PULL)) + if ((flags & 1) == PIN_ACTIVE_HIGH) { value = PIN_HIGH; } - else if (flags == (PIN_ACTIVE_LOW | PIN_PUSH_PULL)) + else if ((flags & 1) == PIN_ACTIVE_LOW) { value = PIN_LOW; } @@ -124,14 +130,20 @@ rt_ssize_t rt_ofw_get_named_pin(struct rt_ofw_node *np, const char *propname, in _out_converts: rt_ofw_node_put(pin_dev_np); - if (out_mode) + if (pin >= 0) { - *out_mode = mode; - } + /* Get virtual pin */ + pin += pin_dev->pin_start; - if (out_value) - { - *out_value = value; + if (out_mode) + { + *out_mode = mode; + } + + if (out_value) + { + *out_value = value; + } } return pin; @@ -142,7 +154,7 @@ rt_ssize_t rt_ofw_get_named_pin_count(struct rt_ofw_node *np, const char *propna char gpios_name[64]; rt_ssize_t count = 0; - if (!np || !propname) + if (!np) { return -RT_EINVAL; } diff --git a/rt-thread/components/drivers/pin/pin_dm.c b/rt-thread/components/drivers/pin/pin_dm.c deleted file mode 100644 index 52dd47f..0000000 --- a/rt-thread/components/drivers/pin/pin_dm.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-11-26 GuEe-GUI first version - */ - -#include "pin_dm.h" - -static void pin_dm_irq_mask(struct rt_pic_irq *pirq) -{ - struct rt_device_pin *gpio = pirq->pic->priv_data; - - gpio->ops->pin_irq_enable(&gpio->parent, pirq->hwirq, 0); -} - -static void pin_dm_irq_unmask(struct rt_pic_irq *pirq) -{ - struct rt_device_pin *gpio = pirq->pic->priv_data; - - gpio->ops->pin_irq_enable(&gpio->parent, pirq->hwirq, 1); -} - -static rt_err_t pin_dm_irq_set_triger_mode(struct rt_pic_irq *pirq, rt_uint32_t mode) -{ - rt_uint8_t pin_mode; - struct rt_device_pin *gpio = pirq->pic->priv_data; - - switch (mode) - { - case RT_IRQ_MODE_EDGE_RISING: - pin_mode = PIN_IRQ_MODE_RISING; - break; - - case RT_IRQ_MODE_EDGE_FALLING: - pin_mode = PIN_IRQ_MODE_FALLING; - break; - - case RT_IRQ_MODE_EDGE_BOTH: - pin_mode = PIN_IRQ_MODE_RISING_FALLING; - break; - - case RT_IRQ_MODE_LEVEL_HIGH: - pin_mode = PIN_IRQ_MODE_HIGH_LEVEL; - break; - - case RT_IRQ_MODE_LEVEL_LOW: - pin_mode = PIN_IRQ_MODE_LOW_LEVEL; - break; - - default: - return -RT_ENOSYS; - } - - return gpio->ops->pin_irq_mode(&gpio->parent, pirq->hwirq, pin_mode); -} - -static int pin_dm_irq_map(struct rt_pic *pic, int hwirq, rt_uint32_t mode) -{ - int irq = -1; - struct rt_device_pin *gpio = pic->priv_data; - struct rt_pic_irq *pirq = rt_pic_find_irq(pic, hwirq); - - if (pirq) - { - irq = rt_pic_config_irq(pic, hwirq, hwirq); - - if (irq >= 0) - { - rt_pic_cascade(pirq, gpio->irqchip.irq); - rt_pic_irq_set_triger_mode(irq, mode); - } - } - - return irq; -} - -static rt_err_t pin_dm_irq_parse(struct rt_pic *pic, struct rt_ofw_cell_args *args, struct rt_pic_irq *out_pirq) -{ - rt_err_t err = RT_EOK; - - if (args->args_count == 2) - { - out_pirq->hwirq = args->args[0]; - out_pirq->mode = args->args[1] & RT_IRQ_MODE_MASK; - } - else - { - err = -RT_EINVAL; - } - - return err; -} - -static struct rt_pic_ops pin_dm_ops = -{ - .name = "GPIO", - .irq_enable = pin_dm_irq_mask, - .irq_disable = pin_dm_irq_unmask, - .irq_mask = pin_dm_irq_mask, - .irq_unmask = pin_dm_irq_unmask, - .irq_set_triger_mode = pin_dm_irq_set_triger_mode, - .irq_map = pin_dm_irq_map, - .irq_parse = pin_dm_irq_parse, -}; - -rt_err_t pin_pic_handle_isr(struct rt_device_pin *gpio, rt_base_t pin) -{ - rt_err_t err; - - if (gpio) - { - struct rt_pin_irqchip *irqchip = &gpio->irqchip; - - if (pin >= irqchip->pin_range[0] && pin <= irqchip->pin_range[1]) - { - struct rt_pic_irq *pirq; - - pirq = rt_pic_find_irq(&irqchip->parent, pin - irqchip->pin_range[0]); - - if (pirq->irq >= 0) - { - err = rt_pic_handle_isr(pirq); - } - else - { - err = -RT_EINVAL; - } - } - else - { - err = -RT_EINVAL; - } - } - else - { - err = -RT_EINVAL; - } - - return err; -} - -rt_err_t pin_pic_init(struct rt_device_pin *gpio) -{ - rt_err_t err; - - if (gpio) - { - struct rt_pin_irqchip *irqchip = &gpio->irqchip; - - if (irqchip->pin_range[0] >= 0 && irqchip->pin_range[1] >= irqchip->pin_range[0]) - { - struct rt_pic *pic = &irqchip->parent; - rt_size_t pin_nr = irqchip->pin_range[1] - irqchip->pin_range[0] + 1; - - pic->priv_data = gpio; - pic->ops = &pin_dm_ops; - /* Make sure the type of gpio for pic */ - gpio->parent.parent.type = RT_Object_Class_Device; - rt_pic_default_name(&irqchip->parent); - - err = rt_pic_linear_irq(pic, pin_nr); - rt_pic_user_extends(pic); - } - else - { - err = -RT_EINVAL; - } - } - else - { - err = -RT_EINVAL; - } - - return err; -} - -rt_ssize_t rt_pin_get_named_pin(struct rt_device *dev, const char *propname, int index, - rt_uint8_t *out_mode, rt_uint8_t *out_value) -{ - rt_ssize_t res = -RT_ENOSYS; - - RT_ASSERT(dev != RT_NULL); - -#ifdef RT_USING_OFW - if (dev->ofw_node) - { - res = rt_ofw_get_named_pin(dev->ofw_node, propname, index, out_mode, out_value); - } - else - { - res = -RT_EINVAL; - } -#endif /* RT_USING_OFW */ - - return res; -} - -rt_ssize_t rt_pin_get_named_pin_count(struct rt_device *dev, const char *propname) -{ - rt_ssize_t count = -RT_ENOSYS; - - RT_ASSERT(dev != RT_NULL); - -#ifdef RT_USING_OFW - if (dev->ofw_node) - { - count = rt_ofw_get_named_pin_count(dev->ofw_node, propname); - } - else - { - count = -RT_EINVAL; - } -#endif /* RT_USING_OFW */ - - return count; -} diff --git a/rt-thread/components/drivers/pinctrl/Kconfig b/rt-thread/components/drivers/pinctrl/Kconfig index 227c8a9..536049b 100644 --- a/rt-thread/components/drivers/pinctrl/Kconfig +++ b/rt-thread/components/drivers/pinctrl/Kconfig @@ -4,3 +4,6 @@ menuconfig RT_USING_PINCTRL depends on RT_USING_PIN default n +if RT_USING_PINCTRL + osource "$(SOC_DM_PINCTRL_DIR)/Kconfig" +endif diff --git a/rt-thread/components/drivers/pinctrl/pinctrl.c b/rt-thread/components/drivers/pinctrl/pinctrl.c index f327492..2fbfa7a 100644 --- a/rt-thread/components/drivers/pinctrl/pinctrl.c +++ b/rt-thread/components/drivers/pinctrl/pinctrl.c @@ -92,6 +92,11 @@ static rt_err_t ofw_pin_ctrl_confs_apply(struct rt_ofw_node *np, int index) if (pinctrl_np) { + if (!rt_ofw_data(pinctrl_np)) + { + rt_platform_ofw_request(pinctrl_np); + } + pinctrl = rt_ofw_data(pinctrl_np); rt_ofw_node_put(pinctrl_np); @@ -217,6 +222,8 @@ rt_err_t rt_pin_ctrl_confs_apply_by_name(struct rt_device *device, const char *n err = ofw_pin_ctrl_confs_apply_by_name(device->ofw_node, name); } #endif /* RT_USING_OFW */ + + RT_UNUSED(name); } else { diff --git a/rt-thread/components/drivers/pm/pm.c b/rt-thread/components/drivers/pm/pm.c index 024e301..b4ad3b2 100644 --- a/rt-thread/components/drivers/pm/pm.c +++ b/rt-thread/components/drivers/pm/pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,6 +10,7 @@ * 2019-04-28 Zero-Free improve PM mode and device ops interface * 2020-11-23 zhangsz update pm mode select * 2020-11-27 zhangsz update pm 2.0 + * 2024-07-04 wdfk-prog The device is registered and uninstalled by linked list */ #include @@ -77,9 +78,6 @@ rt_weak void rt_pm_exit_critical(rt_uint32_t ctx, rt_uint8_t sleep_mode) /* lptimer start */ static void pm_lptimer_start(struct rt_pm *pm, uint32_t timeout) { - if (_pm.ops == RT_NULL) - return; - if (_pm.ops->timer_start != RT_NULL) _pm.ops->timer_start(pm, timeout); } @@ -87,9 +85,6 @@ static void pm_lptimer_start(struct rt_pm *pm, uint32_t timeout) /* lptimer stop */ static void pm_lptimer_stop(struct rt_pm *pm) { - if (_pm.ops == RT_NULL) - return; - if (_pm.ops->timer_stop != RT_NULL) _pm.ops->timer_stop(pm); } @@ -97,9 +92,6 @@ static void pm_lptimer_stop(struct rt_pm *pm) /* lptimer get timeout tick */ static rt_tick_t pm_lptimer_get_timeout(struct rt_pm *pm) { - if (_pm.ops == RT_NULL) - return RT_TICK_MAX; - if (_pm.ops->timer_get_tick != RT_NULL) return _pm.ops->timer_get_tick(pm); @@ -109,9 +101,6 @@ static rt_tick_t pm_lptimer_get_timeout(struct rt_pm *pm) /* enter sleep mode */ static void pm_sleep(struct rt_pm *pm, uint8_t sleep_mode) { - if (_pm.ops == RT_NULL) - return; - if (_pm.ops->sleep != RT_NULL) _pm.ops->sleep(pm, sleep_mode); } @@ -119,17 +108,22 @@ static void pm_sleep(struct rt_pm *pm, uint8_t sleep_mode) /** * This function will suspend all registered devices */ -static int _pm_device_suspend(rt_uint8_t mode) +static rt_err_t _pm_device_suspend(rt_uint8_t mode) { - int index, ret = RT_EOK; + rt_err_t ret = RT_EOK; + struct rt_device_pm *device_pm = RT_NULL; + rt_slist_t *node = RT_NULL; - for (index = 0; index < _pm.device_pm_number; index++) + for (node = rt_slist_first(&_pm.device_list); node; node = rt_slist_next(node)) { - if (_pm.device_pm[index].ops->suspend != RT_NULL) + device_pm = rt_slist_entry(node, struct rt_device_pm, list); + if (device_pm->ops != RT_NULL && device_pm->ops->suspend != RT_NULL) { - ret = _pm.device_pm[index].ops->suspend(_pm.device_pm[index].device, mode); + ret = device_pm->ops->suspend(device_pm->device, mode); if(ret != RT_EOK) + { break; + } } } @@ -141,13 +135,15 @@ static int _pm_device_suspend(rt_uint8_t mode) */ static void _pm_device_resume(rt_uint8_t mode) { - int index; + struct rt_device_pm *device_pm = RT_NULL; + rt_slist_t *node = RT_NULL; - for (index = 0; index < _pm.device_pm_number; index++) + for (node = rt_slist_first(&_pm.device_list); node; node = rt_slist_next(node)) { - if (_pm.device_pm[index].ops->resume != RT_NULL) + device_pm = rt_slist_entry(node, struct rt_device_pm, list); + if (device_pm->ops != RT_NULL && device_pm->ops->resume != RT_NULL) { - _pm.device_pm[index].ops->resume(_pm.device_pm[index].device, mode); + device_pm->ops->resume(device_pm->device, mode); } } } @@ -157,13 +153,16 @@ static void _pm_device_resume(rt_uint8_t mode) */ static void _pm_device_frequency_change(rt_uint8_t mode) { - rt_uint32_t index; + struct rt_device_pm *device_pm = RT_NULL; + rt_slist_t *node = RT_NULL; - /* make the frequency change */ - for (index = 0; index < _pm.device_pm_number; index ++) + for (node = rt_slist_first(&_pm.device_list); node; node = rt_slist_next(node)) { - if (_pm.device_pm[index].ops->frequency_change != RT_NULL) - _pm.device_pm[index].ops->frequency_change(_pm.device_pm[index].device, mode); + device_pm = rt_slist_entry(node, struct rt_device_pm, list); + if (device_pm->ops->frequency_change != RT_NULL) + { + device_pm->ops->frequency_change(device_pm->device, mode); + } } } @@ -172,13 +171,16 @@ static void _pm_device_frequency_change(rt_uint8_t mode) */ static void _pm_frequency_scaling(struct rt_pm *pm) { - rt_base_t level; + rt_base_t level = 0; if (pm->flags & RT_PM_FREQUENCY_PENDING) { level = rt_hw_interrupt_disable(); /* change system runing mode */ - pm->ops->run(pm, pm->run_mode); + if(pm->ops->run != RT_NULL) + { + pm->ops->run(pm, pm->run_mode); + } /* changer device frequency */ _pm_device_frequency_change(pm->run_mode); pm->flags &= ~RT_PM_FREQUENCY_PENDING; @@ -288,6 +290,12 @@ static rt_bool_t _pm_device_check_idle(void) return RT_TRUE; } +/** + * @brief Get the next system wake-up time + * @note When used by default, it goes into STANDBY mode and sleeps forever. tickless external rewriting is required + * @param mode: sleep mode + * @retval timeout_tick + */ rt_weak rt_tick_t pm_timer_next_timeout_tick(rt_uint8_t mode) { switch (mode) @@ -344,6 +352,7 @@ rt_weak rt_uint8_t pm_get_sleep_threshold_mode(rt_uint8_t cur_mode, rt_tick_t ti else if (timeout_tick < PM_STANDBY_THRESHOLD_TIME) sleep_mode = PM_SLEEP_MODE_DEEP; } + cur_mode = sleep_mode; #else if (timeout_tick < PM_TICKLESS_THRESHOLD_TIME) { @@ -359,8 +368,8 @@ rt_weak rt_uint8_t pm_get_sleep_threshold_mode(rt_uint8_t cur_mode, rt_tick_t ti */ static void _pm_change_sleep_mode(struct rt_pm *pm) { - rt_tick_t timeout_tick, delta_tick; - rt_base_t level; + rt_tick_t timeout_tick = 0, delta_tick = 0; + rt_base_t level = 0; uint8_t sleep_mode = PM_SLEEP_MODE_DEEP; level = rt_pm_enter_critical(pm->sleep_mode); @@ -380,23 +389,27 @@ static void _pm_change_sleep_mode(struct rt_pm *pm) if (_pm.sleep_mode == PM_SLEEP_MODE_NONE) { - pm->ops->sleep(pm, PM_SLEEP_MODE_NONE); + pm_sleep(pm, PM_SLEEP_MODE_NONE); rt_pm_exit_critical(level, pm->sleep_mode); } else { /* Notify app will enter sleep mode */ if (_pm_notify.notify) + { _pm_notify.notify(RT_PM_ENTER_SLEEP, pm->sleep_mode, _pm_notify.data); + } /* Suspend all peripheral device */ #ifdef PM_ENABLE_SUSPEND_SLEEP_MODE - int ret = _pm_device_suspend(pm->sleep_mode); + rt_err_t ret = _pm_device_suspend(pm->sleep_mode); if (ret != RT_EOK) { _pm_device_resume(pm->sleep_mode); if (_pm_notify.notify) + { _pm_notify.notify(RT_PM_EXIT_SLEEP, pm->sleep_mode, _pm_notify.data); + } if (pm->sleep_mode > PM_SUSPEND_SLEEP_MODE) { pm->sleep_mode = PM_SUSPEND_SLEEP_MODE; @@ -419,14 +432,7 @@ static void _pm_change_sleep_mode(struct rt_pm *pm) if (pm->timer_mask & (0x01 << pm->sleep_mode)) { - if (timeout_tick == RT_TICK_MAX) - { - pm_lptimer_start(pm, RT_TICK_MAX); - } - else - { - pm_lptimer_start(pm, timeout_tick); - } + pm_lptimer_start(pm, timeout_tick); } } @@ -440,7 +446,9 @@ static void _pm_change_sleep_mode(struct rt_pm *pm) pm_lptimer_stop(pm); if (delta_tick) { - rt_tick_set(rt_tick_get() + delta_tick); + rt_interrupt_enter(); + rt_tick_increase_tick(delta_tick); + rt_interrupt_leave(); } } @@ -451,14 +459,6 @@ static void _pm_change_sleep_mode(struct rt_pm *pm) _pm_notify.notify(RT_PM_EXIT_SLEEP, pm->sleep_mode, _pm_notify.data); rt_pm_exit_critical(level, pm->sleep_mode); - - if (pm->timer_mask & (0x01 << pm->sleep_mode)) - { - if (delta_tick) - { - rt_timer_check(); - } - } } } @@ -467,8 +467,10 @@ static void _pm_change_sleep_mode(struct rt_pm *pm) */ void rt_system_power_manager(void) { - if (_pm_init_flag == 0) + if (_pm_init_flag == 0 || _pm.ops == RT_NULL) + { return; + } /* CPU frequency scaling according to the runing mode settings */ _pm_frequency_scaling(&_pm); @@ -483,22 +485,28 @@ void rt_system_power_manager(void) * * @param parameter the parameter of run mode or sleep mode */ -void rt_pm_request(rt_uint8_t mode) +rt_err_t rt_pm_request(rt_uint8_t mode) { rt_base_t level; struct rt_pm *pm; if (_pm_init_flag == 0) - return; + { + return -RT_EPERM; + } if (mode > (PM_SLEEP_MODE_MAX - 1)) - return; + { + return -RT_EINVAL; + } level = rt_hw_interrupt_disable(); pm = &_pm; if (pm->modes[mode] < 255) pm->modes[mode] ++; rt_hw_interrupt_enable(level); + + return RT_EOK; } /** @@ -508,22 +516,28 @@ void rt_pm_request(rt_uint8_t mode) * @param parameter the parameter of run mode or sleep mode * */ -void rt_pm_release(rt_uint8_t mode) +rt_err_t rt_pm_release(rt_uint8_t mode) { rt_base_t level; struct rt_pm *pm; if (_pm_init_flag == 0) - return; + { + return -RT_EPERM; + } if (mode > (PM_SLEEP_MODE_MAX - 1)) - return; + { + return -RT_EINVAL; + } level = rt_hw_interrupt_disable(); pm = &_pm; if (pm->modes[mode] > 0) pm->modes[mode] --; rt_hw_interrupt_enable(level); + + return RT_EOK; } /** @@ -533,21 +547,27 @@ void rt_pm_release(rt_uint8_t mode) * @param parameter the parameter of run mode or sleep mode * */ -void rt_pm_release_all(rt_uint8_t mode) +rt_err_t rt_pm_release_all(rt_uint8_t mode) { rt_base_t level; struct rt_pm *pm; if (_pm_init_flag == 0) - return; + { + return -RT_EPERM; + } if (mode > (PM_SLEEP_MODE_MAX - 1)) - return; + { + return -RT_EINVAL; + } level = rt_hw_interrupt_disable(); pm = &_pm; pm->modes[mode] = 0; rt_hw_interrupt_enable(level); + + return RT_EOK; } /** @@ -557,19 +577,25 @@ void rt_pm_release_all(rt_uint8_t mode) * @param module_id the application or device module id * @param mode the system power sleep mode */ -void rt_pm_module_request(uint8_t module_id, rt_uint8_t mode) +rt_err_t rt_pm_module_request(uint8_t module_id, rt_uint8_t mode) { rt_base_t level; struct rt_pm *pm; if (_pm_init_flag == 0) - return; + { + return -RT_EPERM; + } if (mode > (PM_SLEEP_MODE_MAX - 1)) - return; + { + return -RT_EINVAL; + } if (module_id > (PM_MODULE_MAX_ID - 1)) - return; + { + return -RT_EINVAL; + } level = rt_hw_interrupt_disable(); pm = &_pm; @@ -577,6 +603,8 @@ void rt_pm_module_request(uint8_t module_id, rt_uint8_t mode) if (pm->modes[mode] < 255) pm->modes[mode] ++; rt_hw_interrupt_enable(level); + + return RT_EOK; } /** @@ -587,19 +615,25 @@ void rt_pm_module_request(uint8_t module_id, rt_uint8_t mode) * @param mode the system power sleep mode * */ -void rt_pm_module_release(uint8_t module_id, rt_uint8_t mode) +rt_err_t rt_pm_module_release(uint8_t module_id, rt_uint8_t mode) { rt_base_t level; struct rt_pm *pm; if (_pm_init_flag == 0) - return; + { + return -RT_EPERM; + } if (mode > (PM_SLEEP_MODE_MAX - 1)) - return; + { + return -RT_EINVAL; + } if (module_id > (PM_MODULE_MAX_ID - 1)) - return; + { + return -RT_EINVAL; + } level = rt_hw_interrupt_disable(); pm = &_pm; @@ -608,6 +642,8 @@ void rt_pm_module_release(uint8_t module_id, rt_uint8_t mode) if (pm->modes[mode] == 0) pm->module_status[module_id].req_status = 0x00; rt_hw_interrupt_enable(level); + + return RT_EOK; } /** @@ -618,22 +654,28 @@ void rt_pm_module_release(uint8_t module_id, rt_uint8_t mode) * @param mode the system power sleep mode * */ -void rt_pm_module_release_all(uint8_t module_id, rt_uint8_t mode) +rt_err_t rt_pm_module_release_all(uint8_t module_id, rt_uint8_t mode) { rt_base_t level; struct rt_pm *pm; if (_pm_init_flag == 0) - return; + { + return -RT_EPERM; + } if (mode > (PM_SLEEP_MODE_MAX - 1)) - return; + { + return -RT_EINVAL; + } level = rt_hw_interrupt_disable(); pm = &_pm; pm->modes[mode] = 0; pm->module_status[module_id].req_status = 0x00; rt_hw_interrupt_enable(level); + + return RT_EOK; } /** @@ -644,23 +686,24 @@ void rt_pm_module_release_all(uint8_t module_id, rt_uint8_t mode) * * @return none */ -void rt_pm_sleep_request(rt_uint16_t module_id, rt_uint8_t mode) +rt_err_t rt_pm_sleep_request(rt_uint16_t module_id, rt_uint8_t mode) { rt_base_t level; if (module_id >= PM_MODULE_MAX_ID) { - return; + return -RT_EINVAL; } if (mode >= (PM_SLEEP_MODE_MAX - 1)) { - return; + return -RT_EINVAL; } level = rt_hw_interrupt_disable(); _pm.sleep_status[mode][module_id / 32] |= 1 << (module_id % 32); rt_hw_interrupt_enable(level); + return RT_EOK; } /** @@ -670,9 +713,9 @@ void rt_pm_sleep_request(rt_uint16_t module_id, rt_uint8_t mode) * * @return NULL */ -void rt_pm_sleep_none_request(rt_uint16_t module_id) +rt_err_t rt_pm_sleep_none_request(rt_uint16_t module_id) { - rt_pm_sleep_request(module_id, PM_SLEEP_MODE_NONE); + return rt_pm_sleep_request(module_id, PM_SLEEP_MODE_NONE); } /** @@ -682,9 +725,9 @@ void rt_pm_sleep_none_request(rt_uint16_t module_id) * * @return NULL */ -void rt_pm_sleep_idle_request(rt_uint16_t module_id) +rt_err_t rt_pm_sleep_idle_request(rt_uint16_t module_id) { - rt_pm_sleep_request(module_id, PM_SLEEP_MODE_IDLE); + return rt_pm_sleep_request(module_id, PM_SLEEP_MODE_IDLE); } /** @@ -694,9 +737,9 @@ void rt_pm_sleep_idle_request(rt_uint16_t module_id) * * @return NULL */ -void rt_pm_sleep_light_request(rt_uint16_t module_id) +rt_err_t rt_pm_sleep_light_request(rt_uint16_t module_id) { - rt_pm_sleep_request(module_id, PM_SLEEP_MODE_LIGHT); + return rt_pm_sleep_request(module_id, PM_SLEEP_MODE_LIGHT); } /** @@ -707,23 +750,24 @@ void rt_pm_sleep_light_request(rt_uint16_t module_id) * * @return NULL */ -void rt_pm_sleep_release(rt_uint16_t module_id, rt_uint8_t mode) +rt_err_t rt_pm_sleep_release(rt_uint16_t module_id, rt_uint8_t mode) { rt_base_t level; if (module_id >= PM_MODULE_MAX_ID) { - return; + return -RT_EINVAL; } if (mode >= (PM_SLEEP_MODE_MAX - 1)) { - return; + return -RT_EINVAL; } level = rt_hw_interrupt_disable(); _pm.sleep_status[mode][module_id / 32] &= ~(1 << (module_id % 32)); rt_hw_interrupt_enable(level); + return RT_EOK; } /** @@ -733,9 +777,9 @@ void rt_pm_sleep_release(rt_uint16_t module_id, rt_uint8_t mode) * * @return none */ -void rt_pm_sleep_none_release(rt_uint16_t module_id) +rt_err_t rt_pm_sleep_none_release(rt_uint16_t module_id) { - rt_pm_sleep_release(module_id, PM_SLEEP_MODE_NONE); + return rt_pm_sleep_release(module_id, PM_SLEEP_MODE_NONE); } /** @@ -745,9 +789,9 @@ void rt_pm_sleep_none_release(rt_uint16_t module_id) * * @return none */ -void rt_pm_sleep_idle_release(rt_uint16_t module_id) +rt_err_t rt_pm_sleep_idle_release(rt_uint16_t module_id) { - rt_pm_sleep_release(module_id, PM_SLEEP_MODE_IDLE); + return rt_pm_sleep_release(module_id, PM_SLEEP_MODE_IDLE); } /** @@ -757,9 +801,9 @@ void rt_pm_sleep_idle_release(rt_uint16_t module_id) * * @return none */ -void rt_pm_sleep_light_release(rt_uint16_t module_id) +rt_err_t rt_pm_sleep_light_release(rt_uint16_t module_id) { - rt_pm_sleep_release(module_id, PM_SLEEP_MODE_LIGHT); + return rt_pm_sleep_release(module_id, PM_SLEEP_MODE_LIGHT); } /** @@ -770,24 +814,15 @@ void rt_pm_sleep_light_release(rt_uint16_t module_id) */ void rt_pm_device_register(struct rt_device *device, const struct rt_device_pm_ops *ops) { - rt_base_t level; struct rt_device_pm *device_pm; - RT_DEBUG_NOT_IN_INTERRUPT; - - level = rt_hw_interrupt_disable(); - - device_pm = (struct rt_device_pm *)RT_KERNEL_REALLOC(_pm.device_pm, - (_pm.device_pm_number + 1) * sizeof(struct rt_device_pm)); + device_pm = RT_KERNEL_MALLOC(sizeof(struct rt_device_pm)); if (device_pm != RT_NULL) { - _pm.device_pm = device_pm; - _pm.device_pm[_pm.device_pm_number].device = device; - _pm.device_pm[_pm.device_pm_number].ops = ops; - _pm.device_pm_number += 1; + rt_slist_append(&_pm.device_list, &device_pm->list); + device_pm->device = device; + device_pm->ops = ops; } - - rt_hw_interrupt_enable(level); } /** @@ -797,32 +832,18 @@ void rt_pm_device_register(struct rt_device *device, const struct rt_device_pm_o */ void rt_pm_device_unregister(struct rt_device *device) { - rt_base_t level; - rt_uint32_t index; - RT_DEBUG_NOT_IN_INTERRUPT; - - level = rt_hw_interrupt_disable(); - - for (index = 0; index < _pm.device_pm_number; index ++) + struct rt_device_pm *device_pm = RT_NULL; + rt_slist_t *node = RT_NULL; + for (node = rt_slist_first(&_pm.device_list); node; node = rt_slist_next(node)) { - if (_pm.device_pm[index].device == device) + device_pm = rt_slist_entry(node, struct rt_device_pm, list); + if (device_pm->device == device) { - /* remove current entry */ - for (; index < _pm.device_pm_number - 1; index ++) - { - _pm.device_pm[index] = _pm.device_pm[index + 1]; - } - - _pm.device_pm[_pm.device_pm_number - 1].device = RT_NULL; - _pm.device_pm[_pm.device_pm_number - 1].ops = RT_NULL; - - _pm.device_pm_number -= 1; - /* break out and not touch memory */ + rt_slist_remove(&_pm.device_list, &device_pm->list); + RT_KERNEL_FREE(device_pm); break; } } - - rt_hw_interrupt_enable(level); } /** @@ -914,10 +935,11 @@ static rt_err_t _rt_pm_device_control(rt_device_t dev, return RT_EOK; } -int rt_pm_run_enter(rt_uint8_t mode) +rt_err_t rt_pm_run_enter(rt_uint8_t mode) { - rt_base_t level; - struct rt_pm *pm; + rt_base_t level = 0; + struct rt_pm *pm = RT_NULL; + rt_err_t ret = RT_EOK; if (_pm_init_flag == 0) return -RT_EIO; @@ -925,12 +947,16 @@ int rt_pm_run_enter(rt_uint8_t mode) if (mode > PM_RUN_MODE_MAX) return -RT_EINVAL; - level = rt_hw_interrupt_disable(); pm = &_pm; + + level = rt_hw_interrupt_disable(); if (mode < pm->run_mode) { /* change system runing mode */ - pm->ops->run(pm, mode); + if(pm->ops != RT_NULL && pm->ops->run != RT_NULL) + { + pm->ops->run(pm, mode); + } /* changer device frequency */ _pm_device_frequency_change(mode); } @@ -941,7 +967,7 @@ int rt_pm_run_enter(rt_uint8_t mode) pm->run_mode = mode; rt_hw_interrupt_enable(level); - return RT_EOK; + return ret; } #ifdef RT_USING_DEVICE_OPS @@ -1004,7 +1030,8 @@ void rt_system_pm_init(const struct rt_pm_ops *ops, pm->ops = ops; pm->device_pm = RT_NULL; - pm->device_pm_number = 0; + + rt_slist_init(&pm->device_list); #if IDLE_THREAD_STACK_SIZE <= 256 #error "[pm.c ERR] IDLE Stack Size Too Small!" diff --git a/rt-thread/components/drivers/regulator/Kconfig b/rt-thread/components/drivers/regulator/Kconfig new file mode 100644 index 0000000..99bfdac --- /dev/null +++ b/rt-thread/components/drivers/regulator/Kconfig @@ -0,0 +1,23 @@ +menuconfig RT_USING_REGULATOR + bool "Using Voltage and Current Regulator" + select RT_USING_ADT + select RT_USING_ADT_REF + depends on RT_USING_DM + default n + +config RT_REGULATOR_FIXED + bool "Fixed regulator support" + depends on RT_USING_REGULATOR + depends on RT_USING_PIN + depends on RT_USING_PINCTRL + default y + +config RT_REGULATOR_GPIO + bool "GPIO regulator support" + depends on RT_USING_REGULATOR + depends on RT_USING_PIN + default y + +if RT_USING_REGULATOR + osource "$(SOC_DM_REGULATOR_DIR)/Kconfig" +endif diff --git a/rt-thread/components/drivers/regulator/SConscript b/rt-thread/components/drivers/regulator/SConscript new file mode 100644 index 0000000..29b567f --- /dev/null +++ b/rt-thread/components/drivers/regulator/SConscript @@ -0,0 +1,21 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_REGULATOR']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] + +src = ['regulator.c', 'regulator_dm.c'] + +if GetDepend(['RT_REGULATOR_FIXED']): + src += ['regulator-fixed.c'] + +if GetDepend(['RT_REGULATOR_GPIO']): + src += ['regulator-gpio.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/regulator/regulator-fixed.c b/rt-thread/components/drivers/regulator/regulator-fixed.c new file mode 100644 index 0000000..5f5773b --- /dev/null +++ b/rt-thread/components/drivers/regulator/regulator-fixed.c @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#include "regulator_dm.h" + +struct regulator_fixed +{ + struct rt_regulator_node parent; + struct rt_regulator_param param; + + rt_base_t enable_pin; + const char *input_supply; +}; + +#define raw_to_regulator_fixed(raw) rt_container_of(raw, struct regulator_fixed, parent) + +static rt_err_t regulator_fixed_enable(struct rt_regulator_node *reg_np) +{ + struct regulator_fixed *rf = raw_to_regulator_fixed(reg_np); + struct rt_regulator_param *param = &rf->param; + + if (rf->enable_pin < 0 || param->always_on) + { + return RT_EOK; + } + + rt_pin_mode(rf->enable_pin, PIN_MODE_OUTPUT); + rt_pin_write(rf->enable_pin, param->enable_active_high ? PIN_HIGH : PIN_LOW); + + return RT_EOK; +} + +static rt_err_t regulator_fixed_disable(struct rt_regulator_node *reg_np) +{ + struct regulator_fixed *rf = raw_to_regulator_fixed(reg_np); + struct rt_regulator_param *param = &rf->param; + + if (rf->enable_pin < 0 || param->always_on) + { + return RT_EOK; + } + + rt_pin_mode(rf->enable_pin, PIN_MODE_OUTPUT); + rt_pin_write(rf->enable_pin, param->enable_active_high ? PIN_LOW: PIN_HIGH); + + return RT_EOK; +} + +static rt_bool_t regulator_fixed_is_enabled(struct rt_regulator_node *reg_np) +{ + rt_uint8_t active; + struct regulator_fixed *rf = raw_to_regulator_fixed(reg_np); + struct rt_regulator_param *param = &rf->param; + + if (rf->enable_pin < 0 || param->always_on) + { + return RT_TRUE; + } + + rt_pin_mode(rf->enable_pin, PIN_MODE_INPUT); + active = rt_pin_read(rf->enable_pin); + + if (param->enable_active_high) + { + return active == PIN_HIGH; + } + + return active == PIN_LOW; +} + +static int regulator_fixed_get_voltage(struct rt_regulator_node *reg_np) +{ + struct regulator_fixed *rf = raw_to_regulator_fixed(reg_np); + + return rf->param.min_uvolt + (rf->param.max_uvolt - rf->param.min_uvolt) / 2; +} + +static const struct rt_regulator_ops regulator_fixed_ops = +{ + .enable = regulator_fixed_enable, + .disable = regulator_fixed_disable, + .is_enabled = regulator_fixed_is_enabled, + .get_voltage = regulator_fixed_get_voltage, +}; + +static rt_err_t regulator_fixed_probe(struct rt_platform_device *pdev) +{ + rt_err_t err; + rt_uint32_t val; + struct rt_device *dev = &pdev->parent; + struct regulator_fixed *rf = rt_calloc(1, sizeof(*rf)); + struct rt_regulator_node *rnp; + + if (!rf) + { + return -RT_ENOMEM; + } + + regulator_ofw_parse(dev->ofw_node, &rf->param); + + rnp = &rf->parent; + rnp->supply_name = rf->param.name; + rnp->ops = ®ulator_fixed_ops; + rnp->param = &rf->param; + rnp->dev = &pdev->parent; + + rf->enable_pin = rt_pin_get_named_pin(dev, "enable", 0, RT_NULL, RT_NULL); + + if (rf->enable_pin < 0) + { + rf->enable_pin = rt_pin_get_named_pin(dev, RT_NULL, 0, RT_NULL, RT_NULL); + } + + if (rf->enable_pin < 0) + { + rf->enable_pin = -1; + } + + rt_pin_ctrl_confs_apply(dev, 0); + + if (!rt_dm_dev_prop_read_u32(dev, "startup-delay-us", &val)) + { + rf->param.enable_delay = val; + } + + if (!rt_dm_dev_prop_read_u32(dev, "off-on-delay-us", &val)) + { + rf->param.off_on_delay = val; + } + + if ((err = rt_regulator_register(rnp))) + { + goto _fail; + } + + return RT_EOK; + +_fail: + rt_free(rf); + + return err; +} + +static const struct rt_ofw_node_id regulator_fixed_ofw_ids[] = +{ + { .compatible = "regulator-fixed" }, + { /* sentinel */ } +}; + +static struct rt_platform_driver regulator_fixed_driver = +{ + .name = "reg-fixed-voltage", + .ids = regulator_fixed_ofw_ids, + + .probe = regulator_fixed_probe, +}; + +static int regulator_fixed_register(void) +{ + rt_platform_driver_register(®ulator_fixed_driver); + + return 0; +} +INIT_SUBSYS_EXPORT(regulator_fixed_register); diff --git a/rt-thread/components/drivers/regulator/regulator-gpio.c b/rt-thread/components/drivers/regulator/regulator-gpio.c new file mode 100644 index 0000000..0698318 --- /dev/null +++ b/rt-thread/components/drivers/regulator/regulator-gpio.c @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#include + +#include "regulator_dm.h" + +struct regulator_gpio_state +{ + rt_uint32_t value; + rt_uint32_t gpios; +}; + +struct regulator_gpio_desc +{ + rt_base_t pin; + rt_uint32_t flags; +}; + +struct regulator_gpio +{ + struct rt_regulator_node parent; + + rt_base_t enable_pin; + + rt_size_t pins_nr; + struct regulator_gpio_desc *pins_desc; + + int state; + rt_size_t states_nr; + struct regulator_gpio_state *states; + + const char *input_supply; + rt_uint32_t startup_delay; + rt_uint32_t off_on_delay; + rt_bool_t enabled_at_boot; + struct rt_regulator_param param; +}; + +#define raw_to_regulator_gpio(raw) rt_container_of(raw, struct regulator_gpio, parent) + +static rt_err_t regulator_gpio_enable(struct rt_regulator_node *reg_np) +{ + struct regulator_gpio *rg = raw_to_regulator_gpio(reg_np); + struct rt_regulator_param *param = &rg->param; + + if (param->always_on) + { + return RT_EOK; + } + + if (rg->enable_pin >= 0) + { + rt_pin_mode(rg->enable_pin, PIN_MODE_OUTPUT); + rt_pin_write(rg->enable_pin, param->enable_active_high ? PIN_HIGH : PIN_LOW); + } + + return RT_EOK; +} + +static rt_err_t regulator_gpio_disable(struct rt_regulator_node *reg_np) +{ + struct regulator_gpio *rg = raw_to_regulator_gpio(reg_np); + struct rt_regulator_param *param = &rg->param; + + if (param->always_on) + { + return RT_EOK; + } + + if (rg->enable_pin >= 0) + { + rt_pin_mode(rg->enable_pin, PIN_MODE_OUTPUT); + rt_pin_write(rg->enable_pin, param->enable_active_high ? PIN_LOW : PIN_HIGH); + } + + return RT_EOK; +} + +static rt_bool_t regulator_gpio_is_enabled(struct rt_regulator_node *reg_np) +{ + struct regulator_gpio *rg = raw_to_regulator_gpio(reg_np); + struct rt_regulator_param *param = &rg->param; + + if (param->always_on) + { + return RT_TRUE; + } + + if (rg->enable_pin >= 0) + { + rt_uint8_t active_val = param->enable_active_high ? PIN_LOW : PIN_HIGH; + + rt_pin_mode(rg->enable_pin, PIN_MODE_INPUT); + return rt_pin_read(rg->enable_pin) == active_val; + } + + return RT_TRUE; +} + +static rt_err_t regulator_gpio_set_voltage(struct rt_regulator_node *reg_np, + int min_uvolt, int max_uvolt) +{ + int target = 0, best_val = RT_REGULATOR_UVOLT_INVALID; + struct regulator_gpio *rg = raw_to_regulator_gpio(reg_np); + + for (int i = 0; i < rg->states_nr; ++i) + { + struct regulator_gpio_state *state = &rg->states[i]; + + if (state->value < best_val && + state->value >= min_uvolt && + state->value <= max_uvolt) + { + target = state->gpios; + best_val = state->value; + } + } + + if (best_val == RT_REGULATOR_UVOLT_INVALID) + { + return -RT_EINVAL; + } + + for (int i = 0; i < rg->pins_nr; ++i) + { + int state = (target >> i) & 1; + struct regulator_gpio_desc *gpiod = &rg->pins_desc[i]; + + rt_pin_mode(gpiod->pin, PIN_MODE_OUTPUT); + rt_pin_write(gpiod->pin, gpiod->flags == PIND_OUT_HIGH ? state : !state); + } + + rg->state = target; + + return RT_EOK; +} + +static int regulator_gpio_get_voltage(struct rt_regulator_node *reg_np) +{ + struct regulator_gpio *rg = raw_to_regulator_gpio(reg_np); + + for (int i = 0; i < rg->states_nr; ++i) + { + if (rg->states[i].gpios == rg->state) + { + return rg->states[i].value; + } + } + + return -RT_EINVAL; +} + +static const struct rt_regulator_ops regulator_gpio_ops = +{ + .enable = regulator_gpio_enable, + .disable = regulator_gpio_disable, + .is_enabled = regulator_gpio_is_enabled, + .set_voltage = regulator_gpio_set_voltage, + .get_voltage = regulator_gpio_get_voltage, +}; + +static rt_err_t regulator_gpio_probe(struct rt_platform_device *pdev) +{ + rt_err_t err; + struct rt_device *dev = &pdev->parent; + struct regulator_gpio *rg = rt_calloc(1, sizeof(*rg)); + struct rt_regulator_node *rgp; + + if (!rg) + { + return -RT_ENOMEM; + } + + regulator_ofw_parse(dev->ofw_node, &rg->param); + + rgp = &rg->parent; + rgp->supply_name = rg->param.name; + rgp->ops = ®ulator_gpio_ops; + rgp->param = &rg->param; + rgp->dev = &pdev->parent; + + rt_dm_dev_prop_read_u32(dev, "startup-delay-us", &rg->startup_delay); + rt_dm_dev_prop_read_u32(dev, "off-on-delay-us", &rg->off_on_delay); + + /* GPIO flags are ignored, we check by enable-active-high */ + rg->enable_pin = rt_pin_get_named_pin(dev, "enable", 0, RT_NULL, RT_NULL); + + if (rg->enable_pin < 0 && rg->enable_pin != -RT_EEMPTY) + { + err = rg->enable_pin; + goto _fail; + } + + rg->pins_nr = rt_pin_get_named_pin_count(dev, "gpios"); + + if (rg->pins_nr > 0) + { + rg->pins_desc = rt_malloc(sizeof(*rg->pins_desc) * rg->pins_nr); + + if (!rg->pins_desc) + { + err = -RT_ENOMEM; + + goto _fail; + } + + for (int i = 0; i < rg->pins_nr; ++i) + { + rt_uint32_t val; + struct regulator_gpio_desc *gpiod = &rg->pins_desc[i]; + + gpiod->pin = rt_pin_get_named_pin(dev, RT_NULL, i, RT_NULL, RT_NULL); + + if (gpiod->pin < 0) + { + err = gpiod->pin; + goto _fail; + } + + if (rt_dm_dev_prop_read_u32_index(dev, "gpios-states", i, &val) < 0) + { + gpiod->flags = PIND_OUT_HIGH; + } + else + { + gpiod->flags = val ? PIND_OUT_HIGH : PIND_OUT_LOW; + } + + if (gpiod->flags == PIND_OUT_HIGH) + { + rg->state |= 1 << i; + } + } + } + + rg->states_nr = rt_dm_dev_prop_count_of_u32(dev, "states") / 2; + + if (rg->states_nr < 0) + { + err = -RT_EIO; + + goto _fail; + } + + rg->states = rt_malloc(sizeof(*rg->states) * rg->states_nr); + + if (!rg->states) + { + err = -RT_ENOMEM; + + goto _fail; + } + + for (int i = 0; i < rg->states_nr; ++i) + { + rt_dm_dev_prop_read_u32_index(dev, "states", i * 2, &rg->states[i].value); + rt_dm_dev_prop_read_u32_index(dev, "states", i * 2 + 1, &rg->states[i].gpios); + } + + if ((err = rt_regulator_register(rgp))) + { + goto _fail; + } + + return RT_EOK; + +_fail: + if (rg->pins_desc) + { + rt_free(rg->pins_desc); + } + if (rg->states) + { + rt_free(rg->states); + } + rt_free(rg); + + return err; +} + +static const struct rt_ofw_node_id regulator_gpio_ofw_ids[] = +{ + { .compatible = "regulator-gpio" }, + { /* sentinel */ } +}; + +static struct rt_platform_driver regulator_gpio_driver = +{ + .name = "regulator-gpio", + .ids = regulator_gpio_ofw_ids, + + .probe = regulator_gpio_probe, +}; + +static int regulator_gpio_register(void) +{ + rt_platform_driver_register(®ulator_gpio_driver); + + return 0; +} +INIT_SUBSYS_EXPORT(regulator_gpio_register); diff --git a/rt-thread/components/drivers/regulator/regulator.c b/rt-thread/components/drivers/regulator/regulator.c new file mode 100644 index 0000000..29071e9 --- /dev/null +++ b/rt-thread/components/drivers/regulator/regulator.c @@ -0,0 +1,629 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#include +#include + +#define DBG_TAG "rtdm.regulator" +#define DBG_LVL DBG_INFO +#include + +#include +#include +#include + +struct rt_regulator +{ + struct rt_regulator_node *reg_np; +}; + +static struct rt_spinlock _regulator_lock = { 0 }; + +static rt_err_t regulator_enable(struct rt_regulator_node *reg_np); +static rt_err_t regulator_disable(struct rt_regulator_node *reg_np); + +rt_err_t rt_regulator_register(struct rt_regulator_node *reg_np) +{ + const struct rt_regulator_param *param; + + if (!reg_np || !reg_np->dev || !reg_np->param || !reg_np->ops) + { + return -RT_EINVAL; + } + + rt_list_init(®_np->list); + rt_list_init(®_np->children_nodes); + rt_list_init(®_np->notifier_nodes); + rt_ref_init(®_np->ref); + rt_atomic_store(®_np->enabled_count, 0); + + param = reg_np->param; + + reg_np->parent = RT_NULL; + +#ifdef RT_USING_OFW + if (reg_np->dev->ofw_node) + { + rt_ofw_data(reg_np->dev->ofw_node) = reg_np; + } +#endif /* RT_USING_OFW */ + + if (param->boot_on || param->always_on) + { + regulator_enable(reg_np); + } + + return RT_EOK; +} + +rt_err_t rt_regulator_unregister(struct rt_regulator_node *reg_np) +{ + rt_err_t err = RT_EOK; + + if (!reg_np) + { + return -RT_EINVAL; + } + + rt_hw_spin_lock(&_regulator_lock.lock); + + if (rt_atomic_load(®_np->enabled_count) != 0) + { + err = -RT_EBUSY; + + LOG_E("%s was enabled by consumer", reg_np->supply_name); + + goto _unlock; + } + + if (!(reg_np->param->boot_on || reg_np->param->always_on)) + { + regulator_disable(reg_np); + } + + if (!rt_list_isempty(®_np->children_nodes) || rt_ref_read(®_np->ref) > 1) + { + err = -RT_EBUSY; + + goto _unlock; + } + + reg_np->parent = RT_NULL; + rt_list_remove(®_np->list); + +_unlock: + rt_hw_spin_unlock(&_regulator_lock.lock); + + return err; +} + +rt_err_t rt_regulator_notifier_register(struct rt_regulator *reg, + struct rt_regulator_notifier *notifier) +{ + struct rt_regulator_node *reg_np; + + if (!reg || !notifier) + { + return -RT_EINVAL; + } + + rt_hw_spin_lock(&_regulator_lock.lock); + + reg_np = reg->reg_np; + notifier->regulator = reg; + + rt_list_init(¬ifier->list); + rt_list_insert_after(®_np->notifier_nodes, ¬ifier->list); + + rt_hw_spin_unlock(&_regulator_lock.lock); + + return RT_EOK; +} + +rt_err_t rt_regulator_notifier_unregister(struct rt_regulator *reg, + struct rt_regulator_notifier *notifier) +{ + if (!reg || !notifier) + { + return -RT_EINVAL; + } + + rt_hw_spin_lock(&_regulator_lock.lock); + + rt_list_remove(¬ifier->list); + + rt_hw_spin_unlock(&_regulator_lock.lock); + + return RT_EOK; +} + +static rt_err_t regulator_notifier_call_chain(struct rt_regulator_node *reg_np, + rt_ubase_t msg, void *data) +{ + rt_err_t err = RT_EOK; + struct rt_regulator_notifier *notifier; + rt_list_t *head = ®_np->notifier_nodes; + + if (rt_list_isempty(head)) + { + return err; + } + + rt_list_for_each_entry(notifier, head, list) + { + err = notifier->callback(notifier, msg, data); + + if (err == -RT_EIO) + { + break; + } + } + + return err; +} + +static rt_uint32_t regulator_get_enable_time(struct rt_regulator_node *reg_np) +{ + if (reg_np->param->enable_delay) + { + return reg_np->param->enable_delay; + } + + if (reg_np->ops->enable_time) + { + return reg_np->ops->enable_time(reg_np); + } + + return 0; +} + +static void regulator_delay(rt_uint32_t delay) +{ + rt_uint32_t ms = delay / 1000; + rt_uint32_t us = delay % 1000; + + if (ms > 0) + { + /* + * For small enough values, handle super-millisecond + * delays in the usleep_range() call below. + */ + if (ms < 20) + { + us += ms * 1000; + } + else if (rt_thread_self()) + { + rt_thread_mdelay(ms); + } + else + { + rt_hw_us_delay(ms * 1000); + } + } + + /* + * Give the scheduler some room to coalesce with any other + * wakeup sources. For delays shorter than 10 us, don't even + * bother setting up high-resolution timers and just busy-loop. + */ + if (us >= 10) + { + rt_hw_us_delay((us + 100) >> 1); + } + else + { + rt_hw_us_delay(us); + } +} + +static rt_err_t regulator_enable(struct rt_regulator_node *reg_np) +{ + rt_err_t err = RT_EOK; + rt_uint32_t enable_delay = regulator_get_enable_time(reg_np); + + if (reg_np->ops->enable) + { + err = reg_np->ops->enable(reg_np); + + if (!err) + { + if (enable_delay) + { + regulator_delay(enable_delay); + } + + rt_atomic_add(®_np->enabled_count, 1); + err = regulator_notifier_call_chain(reg_np, RT_REGULATOR_MSG_ENABLE, RT_NULL); + } + } + + if (!err && reg_np->parent) + { + err = regulator_enable(reg_np->parent); + } + + return err; +} + +rt_err_t rt_regulator_enable(struct rt_regulator *reg) +{ + rt_err_t err; + + if (!reg) + { + return -RT_EINVAL; + } + + if (rt_regulator_is_enabled(reg)) + { + return RT_EOK; + } + + rt_hw_spin_lock(&_regulator_lock.lock); + + err = regulator_enable(reg->reg_np); + + rt_hw_spin_unlock(&_regulator_lock.lock); + + return err; +} + +static rt_err_t regulator_disable(struct rt_regulator_node *reg_np) +{ + rt_err_t err = RT_EOK; + + if (reg_np->ops->disable) + { + err = reg_np->ops->disable(reg_np); + + if (!err) + { + if (reg_np->param->off_on_delay) + { + regulator_delay(reg_np->param->off_on_delay); + } + + err = regulator_notifier_call_chain(reg_np, RT_REGULATOR_MSG_DISABLE, RT_NULL); + } + } + + if (!err && reg_np->parent) + { + err = regulator_disable(reg_np->parent); + } + + return err; +} + +rt_err_t rt_regulator_disable(struct rt_regulator *reg) +{ + rt_err_t err; + + if (!reg) + { + return -RT_EINVAL; + } + + if (!rt_regulator_is_enabled(reg)) + { + return RT_EOK; + } + + if (rt_atomic_load(®->reg_np->enabled_count) != 0) + { + rt_atomic_sub(®->reg_np->enabled_count, 1); + + return RT_EOK; + } + + rt_hw_spin_lock(&_regulator_lock.lock); + + err = regulator_disable(reg->reg_np); + + rt_hw_spin_unlock(&_regulator_lock.lock); + + return err; +} + +rt_bool_t rt_regulator_is_enabled(struct rt_regulator *reg) +{ + if (!reg) + { + return -RT_EINVAL; + } + + if (reg->reg_np->ops->is_enabled) + { + return reg->reg_np->ops->is_enabled(reg->reg_np); + } + + return rt_atomic_load(®->reg_np->enabled_count) > 0; +} + +static rt_err_t regulator_set_voltage(struct rt_regulator_node *reg_np, int min_uvolt, int max_uvolt) +{ + rt_err_t err = RT_EOK; + + if (reg_np->ops->set_voltage) + { + union rt_regulator_notifier_args args; + + RT_ASSERT(reg_np->ops->get_voltage != RT_NULL); + + args.old_uvolt = reg_np->ops->get_voltage(reg_np); + args.min_uvolt = min_uvolt; + args.max_uvolt = max_uvolt; + + err = regulator_notifier_call_chain(reg_np, RT_REGULATOR_MSG_VOLTAGE_CHANGE, &args); + + if (!err) + { + err = reg_np->ops->set_voltage(reg_np, min_uvolt, max_uvolt); + } + + if (err) + { + regulator_notifier_call_chain(reg_np, RT_REGULATOR_MSG_VOLTAGE_CHANGE_ERR, + (void *)(rt_base_t)args.old_uvolt); + } + } + + if (!err && reg_np->parent) + { + err = regulator_set_voltage(reg_np->parent, min_uvolt, max_uvolt); + } + + return err; +} + +rt_bool_t rt_regulator_is_supported_voltage(struct rt_regulator *reg, int min_uvolt, int max_uvolt) +{ + const struct rt_regulator_param *param; + + RT_ASSERT(reg != RT_NULL); + + param = reg->reg_np->param; + + if (!param) + { + return RT_FALSE; + } + + return param->min_uvolt <= min_uvolt && param->max_uvolt >= max_uvolt; +} + +rt_err_t rt_regulator_set_voltage(struct rt_regulator *reg, int min_uvolt, int max_uvolt) +{ + rt_err_t err; + + if (!reg) + { + return -RT_EINVAL; + } + + rt_hw_spin_lock(&_regulator_lock.lock); + + err = regulator_set_voltage(reg->reg_np, min_uvolt, max_uvolt); + + rt_hw_spin_unlock(&_regulator_lock.lock); + + return err; +} + +int rt_regulator_get_voltage(struct rt_regulator *reg) +{ + int uvolt = RT_REGULATOR_UVOLT_INVALID; + struct rt_regulator_node *reg_np; + + if (!reg) + { + return -RT_EINVAL; + } + + rt_hw_spin_lock(&_regulator_lock.lock); + + reg_np = reg->reg_np; + + if (reg_np->ops->get_voltage) + { + uvolt = reg_np->ops->get_voltage(reg->reg_np); + } + else + { + uvolt = -RT_ENOSYS; + } + + rt_hw_spin_unlock(&_regulator_lock.lock); + + return uvolt; +} + +rt_err_t rt_regulator_set_mode(struct rt_regulator *reg, rt_uint32_t mode) +{ + rt_err_t err; + struct rt_regulator_node *reg_np; + + if (!reg) + { + return -RT_EINVAL; + } + + rt_hw_spin_lock(&_regulator_lock.lock); + + reg_np = reg->reg_np; + + if (reg_np->ops->set_mode) + { + err = reg_np->ops->set_mode(reg_np, mode); + } + else + { + err = -RT_ENOSYS; + } + + rt_hw_spin_unlock(&_regulator_lock.lock); + + return err; +} + +rt_int32_t rt_regulator_get_mode(struct rt_regulator *reg) +{ + rt_int32_t mode; + struct rt_regulator_node *reg_np; + + if (!reg) + { + return -RT_EINVAL; + } + + rt_hw_spin_lock(&_regulator_lock.lock); + + reg_np = reg->reg_np; + + if (reg_np->ops->get_mode) + { + mode = reg_np->ops->get_mode(reg_np); + } + else + { + mode = -RT_ENOSYS; + } + + rt_hw_spin_unlock(&_regulator_lock.lock); + + return mode; +} + +static void regulator_check_parent(struct rt_regulator_node *reg_np) +{ + if (reg_np->parent) + { + return; + } + else + { + #ifdef RT_USING_OFW + rt_phandle parent_phandle = 0; + struct rt_ofw_node *np = reg_np->dev->ofw_node; + + while (np) + { + if (rt_ofw_prop_read_u32(np, "vin-supply", &parent_phandle)) + { + break; + } + + if (!(np = rt_ofw_find_node_by_phandle(parent_phandle))) + { + break; + } + + if (!(reg_np->parent = rt_ofw_data(np))) + { + LOG_W("%s parent ofw node = %s not init", + reg_np->supply_name, rt_ofw_node_full_name(np)); + + rt_ofw_node_put(np); + break; + } + + rt_list_insert_after(®_np->parent->children_nodes, ®_np->list); + rt_ofw_node_put(np); + } + #endif + } +} + +struct rt_regulator *rt_regulator_get(struct rt_device *dev, const char *id) +{ + struct rt_regulator *reg = RT_NULL; + struct rt_regulator_node *reg_np = RT_NULL; + + if (!dev || !id) + { + reg = rt_err_ptr(-RT_EINVAL); + goto _end; + } + +#ifdef RT_USING_OFW + if (dev->ofw_node) + { + rt_phandle supply_phandle; + struct rt_ofw_node *np = dev->ofw_node; + char supply_name[64]; + + rt_snprintf(supply_name, sizeof(supply_name), "%s-supply", id); + + if (rt_ofw_prop_read_u32(np, supply_name, &supply_phandle)) + { + goto _end; + } + + if (!(np = rt_ofw_find_node_by_phandle(supply_phandle))) + { + reg = rt_err_ptr(-RT_EIO); + goto _end; + } + + if (!rt_ofw_data(np)) + { + rt_platform_ofw_request(np); + } + + reg_np = rt_ofw_data(np); + rt_ofw_node_put(np); + } +#endif + + if (!reg_np) + { + reg = rt_err_ptr(-RT_ENOSYS); + goto _end; + } + + rt_hw_spin_lock(&_regulator_lock.lock); + + regulator_check_parent(reg_np); + + rt_hw_spin_unlock(&_regulator_lock.lock); + + reg = rt_calloc(1, sizeof(*reg)); + + if (!reg) + { + reg = rt_err_ptr(-RT_ENOMEM); + goto _end; + } + + reg->reg_np = reg_np; + rt_ref_get(®_np->ref); + +_end: + return reg; +} + +static void regulator_release(struct rt_ref *r) +{ + struct rt_regulator_node *reg_np = rt_container_of(r, struct rt_regulator_node, ref); + + rt_regulator_unregister(reg_np); +} + +void rt_regulator_put(struct rt_regulator *reg) +{ + if (!reg) + { + return; + } + + rt_ref_put(®->reg_np->ref, ®ulator_release); + rt_free(reg); +} diff --git a/rt-thread/components/drivers/regulator/regulator_dm.c b/rt-thread/components/drivers/regulator/regulator_dm.c new file mode 100644 index 0000000..d8096c4 --- /dev/null +++ b/rt-thread/components/drivers/regulator/regulator_dm.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#include "regulator_dm.h" + +#ifdef RT_USING_OFW +rt_err_t regulator_ofw_parse(struct rt_ofw_node *np, struct rt_regulator_param *param) +{ + rt_uint32_t pval; + + param->name = rt_ofw_prop_read_raw(np, "regulator-name", RT_NULL); + + if (!rt_ofw_prop_read_u32(np, "regulator-min-microvolt", &pval)) + { + param->min_uvolt = pval; + } + + if (!rt_ofw_prop_read_u32(np, "regulator-max-microvolt", &pval)) + { + param->max_uvolt = pval; + } + + if (!rt_ofw_prop_read_u32(np, "regulator-min-microamp", &pval)) + { + param->min_uamp = pval; + } + + if (!rt_ofw_prop_read_u32(np, "regulator-max-microamp", &pval)) + { + param->max_uamp = pval; + } + + if (!rt_ofw_prop_read_u32(np, "regulator-ramp-delay", &pval)) + { + param->ramp_delay = pval; + } + + if (!rt_ofw_prop_read_u32(np, "regulator-enable-ramp-delay", &pval)) + { + param->enable_delay = pval; + } + + param->enable_active_high = rt_ofw_prop_read_bool(np, "enable-active-high"); + param->boot_on = rt_ofw_prop_read_bool(np, "regulator-boot-on"); + param->always_on = rt_ofw_prop_read_bool(np, "regulator-always-on"); + param->soft_start = rt_ofw_prop_read_bool(np, "regulator-soft-start"); + param->pull_down = rt_ofw_prop_read_bool(np, "regulator-pull-down"); + param->over_current_protection = rt_ofw_prop_read_bool(np, "regulator-over-current-protection"); + + return RT_EOK; +} +#endif /* RT_USING_OFW */ diff --git a/rt-thread/components/drivers/regulator/regulator_dm.h b/rt-thread/components/drivers/regulator/regulator_dm.h new file mode 100644 index 0000000..207bb12 --- /dev/null +++ b/rt-thread/components/drivers/regulator/regulator_dm.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#ifndef __REGULATOR_DM_H__ +#define __REGULATOR_DM_H__ + +#include +#include + +#ifdef RT_USING_OFW +rt_err_t regulator_ofw_parse(struct rt_ofw_node *np, struct rt_regulator_param *param); +#else +rt_inline rt_err_t regulator_ofw_parse(struct rt_ofw_node *np, struct rt_regulator_param *param); +{ + return RT_EOK; +} +#endif /* RT_USING_OFW */ + +#endif /* __REGULATOR_DM_H__ */ diff --git a/rt-thread/components/drivers/reset/Kconfig b/rt-thread/components/drivers/reset/Kconfig new file mode 100644 index 0000000..ccba575 --- /dev/null +++ b/rt-thread/components/drivers/reset/Kconfig @@ -0,0 +1,14 @@ +menuconfig RT_USING_RESET + bool "Using Reset Controller support" + depends on RT_USING_DM + depends on RT_USING_OFW + default n + +config RT_RESET_SIMPLE + bool "Simple Reset Controller Driver" + depends on RT_USING_RESET + default n + +if RT_USING_RESET + osource "$(SOC_DM_RESET_DIR)/Kconfig" +endif diff --git a/rt-thread/components/drivers/reset/SConscript b/rt-thread/components/drivers/reset/SConscript new file mode 100644 index 0000000..8e64f78 --- /dev/null +++ b/rt-thread/components/drivers/reset/SConscript @@ -0,0 +1,18 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_RESET']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] + +src = ['reset.c'] + +if GetDepend(['RT_RESET_SIMPLE']): + src += ['reset-simple.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/reset/reset-simple.c b/rt-thread/components/drivers/reset/reset-simple.c new file mode 100644 index 0000000..e66cb8e --- /dev/null +++ b/rt-thread/components/drivers/reset/reset-simple.c @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-11-26 GuEe-GUI first version + */ + +#include "reset-simple.h" + +struct reset_simple_data +{ + rt_uint32_t reg_offset; + rt_bool_t active_low; + rt_bool_t status_active_low; +}; + +#define raw_to_reset_simple(raw) rt_container_of(raw, struct reset_simple, parent) + +static rt_err_t reset_simple_update(struct reset_simple *rsts, int id, rt_bool_t assert) +{ + rt_uint32_t reg; + rt_ubase_t level; + int reg_width = sizeof(rt_uint32_t); + int bank = id / (reg_width * 8); + int offset = id % (reg_width * 8); + + level = rt_spin_lock_irqsave(&rsts->lock); + + reg = HWREG32(rsts->mmio_base + (bank * reg_width)); + + if (assert ^ rsts->active_low) + { + reg |= RT_BIT(offset); + } + else + { + reg &= ~RT_BIT(offset); + } + + HWREG32(rsts->mmio_base + (bank * reg_width)) = reg; + + rt_spin_unlock_irqrestore(&rsts->lock, level); + + return RT_EOK; +} + +static rt_err_t reset_simple_assert(struct rt_reset_control *rstc) +{ + struct reset_simple *rsts = raw_to_reset_simple(rstc); + + return reset_simple_update(rsts, rstc->id, RT_TRUE); +} + +static rt_err_t reset_simple_deassert(struct rt_reset_control *rstc) +{ + struct reset_simple *rsts = raw_to_reset_simple(rstc); + + return reset_simple_update(rsts, rstc->id, RT_FALSE); +} + +static rt_err_t reset_simple_reset(struct rt_reset_control *rstc) +{ + rt_err_t err; + struct reset_simple *rsts = raw_to_reset_simple(rstc); + + if (!rsts->reset_us) + { + return -RT_ENOSYS; + } + + if ((err = reset_simple_assert(rstc))) + { + return err; + } + + rt_hw_us_delay(rsts->reset_us + (rsts->reset_us >> 1)); + + return reset_simple_deassert(rstc); +} + +static int reset_simple_status(struct rt_reset_control *rstc) +{ + rt_uint32_t value; + int reg_width = sizeof(rt_uint32_t); + int bank = rstc->id / (reg_width * 8); + int offset = rstc->id % (reg_width * 8); + struct reset_simple *rsts = raw_to_reset_simple(rstc); + + value = HWREG32(rsts->mmio_base + (bank * reg_width)); + + return !(value & RT_BIT(offset)) ^ !rsts->status_active_low; +} + +const struct rt_reset_control_ops reset_simple_ops = +{ + .reset = reset_simple_reset, + .assert = reset_simple_assert, + .deassert = reset_simple_deassert, + .status = reset_simple_status, +}; + +static rt_err_t reset_simple_probe(struct rt_platform_device *pdev) +{ + rt_err_t err; + struct rt_reset_controller *rstcer; + struct rt_device *dev = &pdev->parent; + const struct reset_simple_data *rsts_data = pdev->id->data; + struct reset_simple *rsts = rt_calloc(1, sizeof(*rsts)); + + if (!rsts) + { + return -RT_ENOMEM; + } + + rsts->mmio_base = rt_dm_dev_iomap(dev, 0); + + if (!rsts->mmio_base) + { + err = -RT_EIO; + goto _fail; + } + + rt_spin_lock_init(&rsts->lock); + + rstcer = &rsts->parent; + + rstcer->priv = rsts; + rstcer->ofw_node = dev->ofw_node; + rstcer->ops = &reset_simple_ops; + + if ((err = rt_reset_controller_register(rstcer))) + { + goto _fail; + } + + if (rsts_data) + { + rsts->mmio_base += rsts_data->reg_offset; + rsts->active_low = rsts_data->active_low; + rsts->status_active_low = rsts_data->status_active_low; + } + + return RT_EOK; + +_fail: + if (rsts->mmio_base) + { + rt_iounmap(rsts->mmio_base); + } + + rt_free(rsts); + + return err; +} + +static const struct reset_simple_data reset_simple_socfpga = +{ + .reg_offset = 0x20, + .status_active_low = RT_TRUE, +}; + +static const struct reset_simple_data reset_simple_active_low = +{ + .active_low = RT_TRUE, + .status_active_low = RT_TRUE, +}; + +static const struct rt_ofw_node_id reset_simple_ofw_ids[] = +{ + { .compatible = "altr,stratix10-rst-mgr", .data = &reset_simple_socfpga }, + { .compatible = "st,stm32-rcc", }, + { .compatible = "allwinner,sun6i-a31-clock-reset", .data = &reset_simple_active_low }, + { .compatible = "zte,zx296718-reset", .data = &reset_simple_active_low }, + { .compatible = "aspeed,ast2400-lpc-reset" }, + { .compatible = "aspeed,ast2500-lpc-reset" }, + { .compatible = "aspeed,ast2600-lpc-reset" }, + { .compatible = "bitmain,bm1880-reset", .data = &reset_simple_active_low }, + { .compatible = "brcm,bcm4908-misc-pcie-reset", .data = &reset_simple_active_low }, + { .compatible = "snps,dw-high-reset" }, + { .compatible = "snps,dw-low-reset", .data = &reset_simple_active_low }, + { .compatible = "sophgo,sg2042-reset", .data = &reset_simple_active_low }, + { /* sentinel */ } +}; + +static struct rt_platform_driver reset_simple_driver = +{ + .name = "reset-simple", + .ids = reset_simple_ofw_ids, + + .probe = reset_simple_probe, +}; + +static int reset_simple_register(void) +{ + rt_platform_driver_register(&reset_simple_driver); + + return 0; +} +INIT_SUBSYS_EXPORT(reset_simple_register); diff --git a/rt-thread/components/drivers/reset/reset-simple.h b/rt-thread/components/drivers/reset/reset-simple.h new file mode 100644 index 0000000..8223d69 --- /dev/null +++ b/rt-thread/components/drivers/reset/reset-simple.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-11-26 GuEe-GUI first version + */ + +#ifndef __RESET_SIMPLE_H__ +#define __RESET_SIMPLE_H__ + +#include +#include + +struct reset_simple +{ + struct rt_reset_controller parent; + + void *mmio_base; + + /* + * If true, bits are cleared to assert the reset. + * Otherwise, bits are set to assert the reset. + */ + rt_bool_t active_low; + /* + * If true, bits read back as cleared while the reset is asserted. + * Otherwise, bits read back as set while the reset is asserted. + */ + rt_bool_t status_active_low; + + /* + * Minimum delay in microseconds needed that needs to be + * waited for between an assert and a deassert to reset the device. + * If multiple consumers with different delay + * requirements are connected to this controller, it must + * be the largest minimum delay. 0 means that such a delay is + * unknown and the reset operation is unsupported. + */ + rt_uint32_t reset_us; + + /* protect registers during read-modify-write cycles */ + struct rt_spinlock lock; +}; + +extern const struct rt_reset_control_ops reset_simple_ops; + +#endif /* __RESET_SIMPLE_H__ */ diff --git a/rt-thread/components/drivers/reset/reset.c b/rt-thread/components/drivers/reset/reset.c new file mode 100644 index 0000000..290d2a7 --- /dev/null +++ b/rt-thread/components/drivers/reset/reset.c @@ -0,0 +1,432 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-11-26 GuEe-GUI first version + */ + +#include +#include + +#define DBG_TAG "rtdm.reset" +#define DBG_LVL DBG_INFO +#include + +#include +#include +#include +#include + +struct reset_control_array +{ + struct rt_reset_control captain; + + rt_size_t count; + struct rt_reset_control *rstcs[]; +}; + +#define reset_control_to_array(rstc) rt_container_of(rstc, struct reset_control_array, captain) + +rt_err_t rt_reset_controller_register(struct rt_reset_controller *rstcer) +{ + if (!rstcer) + { + return -RT_EINVAL; + } + +#if RT_NAME_MAX > 0 + rt_strncpy(rstcer->parent.name, RT_RESET_CONTROLLER_OBJ_NAME, RT_NAME_MAX); +#else + rstcer->parent.name = RT_RESET_CONTROLLER_OBJ_NAME; +#endif + + rt_list_init(&rstcer->rstc_nodes); + rt_spin_lock_init(&rstcer->spinlock); + + if (rstcer->ofw_node) + { + if (!rt_ofw_data(rstcer->ofw_node)) + { + rt_ofw_data(rstcer->ofw_node) = rstcer; + } + } + + return RT_EOK; +} + +rt_err_t rt_reset_controller_unregister(struct rt_reset_controller *rstcer) +{ + rt_err_t err = RT_EOK; + + if (!rstcer) + { + return -RT_EINVAL; + } + + rt_spin_lock(&rstcer->spinlock); + + if (!rt_list_isempty(&rstcer->rstc_nodes)) + { + err = -RT_EBUSY; + goto _out_lock; + } + +_out_lock: + rt_spin_unlock(&rstcer->spinlock); + + return err; +} + +rt_err_t rt_reset_control_reset(struct rt_reset_control *rstc) +{ + rt_err_t err; + + if (!rstc) + { + return RT_EOK; + } + + if (rstc->rstcer->ops->reset) + { + if ((err = rstc->rstcer->ops->reset(rstc))) + { + return err; + } + } + + if (rstc->is_array) + { + struct reset_control_array *rstc_arr = reset_control_to_array(rstc); + + for (int i = 0; i < rstc_arr->count; ++i) + { + if ((err = rt_reset_control_reset(rstc_arr->rstcs[i]))) + { + return err; + } + } + } + + return RT_EOK; +} + +rt_err_t rt_reset_control_assert(struct rt_reset_control *rstc) +{ + rt_err_t err; + + if (!rstc) + { + return RT_EOK; + } + + if (rstc->rstcer->ops->assert) + { + if ((err = rstc->rstcer->ops->assert(rstc))) + { + return err; + } + } + + if (rstc->is_array) + { + struct reset_control_array *rstc_arr = reset_control_to_array(rstc); + + for (int i = 0; i < rstc_arr->count; ++i) + { + if ((err = rt_reset_control_assert(rstc_arr->rstcs[i]))) + { + if (rstc->rstcer->ops->deassert) + { + rstc->rstcer->ops->deassert(rstc); + } + + while (i --> 0) + { + rt_reset_control_deassert(rstc_arr->rstcs[i]); + } + + return err; + } + } + } + + return RT_EOK; +} + +rt_err_t rt_reset_control_deassert(struct rt_reset_control *rstc) +{ + rt_err_t err; + + if (!rstc) + { + return RT_EOK; + } + + if (rstc->rstcer->ops->deassert) + { + if ((err = rstc->rstcer->ops->deassert(rstc))) + { + return err; + } + } + + if (rstc->is_array) + { + struct reset_control_array *rstc_arr = reset_control_to_array(rstc); + + for (int i = 0; i < rstc_arr->count; ++i) + { + if ((err = rt_reset_control_deassert(rstc_arr->rstcs[i]))) + { + if (rstc->rstcer->ops->assert) + { + rstc->rstcer->ops->assert(rstc); + } + + while (i --> 0) + { + rt_reset_control_assert(rstc_arr->rstcs[i]); + } + + return err; + } + } + } + + return RT_EOK; +} + +int rt_reset_control_status(struct rt_reset_control *rstc) +{ + if (!rstc) + { + return RT_EOK; + } + + if (rstc->rstcer->ops->status) + { + return rstc->rstcer->ops->status(rstc); + } + + return -RT_ENOSYS; +} + +static void reset_free(struct rt_reset_control *rstc) +{ + if (rstc->is_array) + { + struct reset_control_array *rstc_arr = reset_control_to_array(rstc); + + for (int i = 0; i < rstc_arr->count; ++i) + { + rt_reset_control_put(rstc_arr->rstcs[i]); + } + } + + rt_free(rstc); +} + +struct rt_reset_control *rt_reset_control_get_array(struct rt_device *dev) +{ + return rt_ofw_get_reset_control_array(dev->ofw_node); +} + +struct rt_reset_control *rt_reset_control_get_by_index(struct rt_device *dev, int index) +{ + return rt_ofw_get_reset_control_by_index(dev->ofw_node, index); +} + +struct rt_reset_control *rt_reset_control_get_by_name(struct rt_device *dev, const char *name) +{ + return rt_ofw_get_reset_control_by_name(dev->ofw_node, name); +} + +void rt_reset_control_put(struct rt_reset_control *rstc) +{ + struct rt_reset_controller *rstcer; + + if (!rstc) + { + return; + } + + rstcer = rstc->rstcer; + + rt_spin_lock(&rstcer->spinlock); + + rt_list_remove(&rstc->list); + + rt_spin_unlock(&rstcer->spinlock); + + reset_free(rstc); +} + +static struct rt_reset_control *ofw_get_reset_control(struct rt_ofw_node *np, int index, + const char *name, rt_bool_t is_array) +{ + rt_err_t err = RT_EOK; + struct rt_reset_control *rstc; + struct rt_ofw_cell_args reset_args = {}; + struct rt_reset_controller *rstcer = RT_NULL; + + if (is_array) + { + rt_size_t rstc_nr; + struct reset_control_array *rstc_arr; + + rstc_nr = rt_ofw_count_phandle_cells(np, "resets", "#reset-cells"); + + if (!rstc_nr) + { + return RT_NULL; + } + + rstc_arr = rt_calloc(1, sizeof(*rstc_arr) + sizeof(struct rt_reset_control *) * rstc_nr); + + if (!rstc_arr) + { + LOG_E("No memory to create %s[%d] reset control", + rt_ofw_node_full_name(np), index); + + return rt_err_ptr(-RT_ENOMEM); + } + + rstc_arr->count = rstc_nr - 1; + + for (int i = 0; i < rstc_arr->count; ++i) + { + rstc_arr->rstcs[i] = ofw_get_reset_control(np, i + 1, RT_NULL, RT_FALSE); + + if (rt_is_err(rstc_arr->rstcs[i])) + { + err = rt_ptr_err(rstc_arr->rstcs[i]); + + while (i --> 0) + { + rt_reset_control_put(rstc_arr->rstcs[i]); + } + + rt_free(rstc_arr); + + return rt_err_ptr(err); + } + } + + rstc = &rstc_arr->captain; + rstc->is_array = RT_TRUE; + } + else + { + rstc = rt_calloc(1, sizeof(*rstc)); + + if (!rstc) + { + LOG_E("No memory to create %s[%d] reset control", + rt_ofw_node_full_name(np), index); + + return rt_err_ptr(-RT_ENOMEM); + } + } + + if (!rt_ofw_parse_phandle_cells(np, "resets", "#reset-cells", index, &reset_args)) + { + void *rt_data; + struct rt_object *obj; + struct rt_ofw_node *reset_np = reset_args.data; + + if (!rt_ofw_data(reset_np)) + { + rt_platform_ofw_request(reset_np); + } + + rt_data = rt_ofw_data(reset_np); + + if (rt_data && (obj = rt_ofw_parse_object(reset_args.data, + RT_RESET_CONTROLLER_OBJ_NAME, "#reset-cells"))) + { + rstcer = rt_container_of(obj, struct rt_reset_controller, parent); + } + + rt_ofw_node_put(reset_np); + + if (!rstcer) + { + err = -RT_EINVAL; + goto _fail; + } + } + else + { + /* Not reset */ + goto _fail; + } + + if (!name && rt_ofw_prop_read_bool(np, "reset-names")) + { + rt_ofw_prop_read_string_index(np, "reset-names", index, &name); + } + + rstc->con_id = name; + rstc->rstcer = rstcer; + + if (rstcer->ops->ofw_parse) + { + err = rstcer->ops->ofw_parse(rstc, &reset_args); + + if (err) + { + LOG_E("Parse %s reset control error = %s", + rt_ofw_node_full_name(np), rt_strerror(err)); + + goto _fail; + } + } + + rstc->id = reset_args.args[0]; + + rt_list_init(&rstc->list); + + rt_spin_lock(&rstcer->spinlock); + + rt_list_insert_after(&rstcer->rstc_nodes, &rstc->list); + + rt_spin_unlock(&rstcer->spinlock); + + return rstc; + +_fail: + if (rstc && !rstc->is_array) + { + rt_free(rstc); + } + + return rt_err_ptr(err); +} + +struct rt_reset_control *rt_ofw_get_reset_control_array(struct rt_ofw_node *np) +{ + return ofw_get_reset_control(np, 0, RT_NULL, RT_TRUE); +} + +struct rt_reset_control *rt_ofw_get_reset_control_by_index(struct rt_ofw_node *np, int index) +{ + return ofw_get_reset_control(np, index, RT_NULL, RT_FALSE); +} + +struct rt_reset_control *rt_ofw_get_reset_control_by_name(struct rt_ofw_node *np, const char *name) +{ + if (np) + { + int index = rt_ofw_prop_index_of_string(np, "reset-names", name); + + if (index >= 0) + { + return ofw_get_reset_control(np, index, name, RT_FALSE); + } + } + + return RT_NULL; +} diff --git a/rt-thread/components/drivers/rtc/Kconfig b/rt-thread/components/drivers/rtc/Kconfig index e4310cb..a8b3366 100644 --- a/rt-thread/components/drivers/rtc/Kconfig +++ b/rt-thread/components/drivers/rtc/Kconfig @@ -7,6 +7,20 @@ config RT_USING_RTC bool "Using RTC alarm" default n + if RT_USING_ALARM + config RT_ALARM_STACK_SIZE + int "stack size for alarm thread" + default 2048 + + config RT_ALARM_TIMESLICE + int "timeslice for alarm thread" + default 5 + + config RT_ALARM_PRIORITY + int "priority for alarm thread" + default 10 + endif + config RT_USING_SOFT_RTC bool "Using software simulation RTC device" default n diff --git a/rt-thread/components/drivers/rtc/SConscript b/rt-thread/components/drivers/rtc/SConscript index fe0d5e9..f1e180f 100644 --- a/rt-thread/components/drivers/rtc/SConscript +++ b/rt-thread/components/drivers/rtc/SConscript @@ -7,11 +7,11 @@ CPPPATH = [cwd + '/../include'] group = [] if GetDepend(['RT_USING_RTC']): - src = src + ['rtc.c'] + src = src + ['dev_rtc.c'] if GetDepend(['RT_USING_ALARM']): - src = src + ['alarm.c'] + src = src + ['dev_alarm.c'] if GetDepend(['RT_USING_SOFT_RTC']): - src = src + ['soft_rtc.c'] + src = src + ['dev_soft_rtc.c'] group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_RTC'], CPPPATH = CPPPATH) diff --git a/rt-thread/components/drivers/rtc/alarm.c b/rt-thread/components/drivers/rtc/dev_alarm.c similarity index 97% rename from rt-thread/components/drivers/rtc/alarm.c rename to rt-thread/components/drivers/rtc/dev_alarm.c index b78528a..aabc415 100644 --- a/rt-thread/components/drivers/rtc/alarm.c +++ b/rt-thread/components/drivers/rtc/dev_alarm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,6 +9,7 @@ * 2013-05-17 aozima initial alarm event & mutex in system init. * 2020-10-15 zhangsz add alarm flags hour minute second. * 2020-11-09 zhangsz fix alarm set when modify rtc time. + * 2024-09-29 milo make internal thread's attributes configurable. */ #include @@ -23,6 +24,15 @@ #endif #if (defined(RT_USING_RTC) && defined(RT_USING_ALARM)) +#ifndef RT_ALARM_STACK_SIZE +#define RT_ALARM_STACK_SIZE 2048 +#endif +#ifndef RT_ALARM_TIMESLICE +#define RT_ALARM_TIMESLICE 5 +#endif +#ifndef RT_ALARM_PRIORITY +#define RT_ALARM_PRIORITY 10 +#endif static struct rt_alarm_container _container; rt_inline rt_uint32_t alarm_mkdaysec(struct tm *time) @@ -789,7 +799,9 @@ int rt_alarm_system_init(void) tid = rt_thread_create("alarmsvc", rt_alarmsvc_thread_init, RT_NULL, - 2048, 10, 5); + RT_ALARM_STACK_SIZE, + RT_ALARM_PRIORITY, + RT_ALARM_TIMESLICE); if (tid != RT_NULL) rt_thread_startup(tid); diff --git a/rt-thread/components/drivers/rtc/rtc.c b/rt-thread/components/drivers/rtc/dev_rtc.c similarity index 99% rename from rt-thread/components/drivers/rtc/rtc.c rename to rt-thread/components/drivers/rtc/dev_rtc.c index 4f4fbc6..f789036 100644 --- a/rt-thread/components/drivers/rtc/rtc.c +++ b/rt-thread/components/drivers/rtc/dev_rtc.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #ifdef RT_USING_RTC diff --git a/rt-thread/components/drivers/rtc/soft_rtc.c b/rt-thread/components/drivers/rtc/dev_soft_rtc.c similarity index 87% rename from rt-thread/components/drivers/rtc/soft_rtc.c rename to rt-thread/components/drivers/rtc/dev_soft_rtc.c index 0eab72e..cd5a37e 100644 --- a/rt-thread/components/drivers/rtc/soft_rtc.c +++ b/rt-thread/components/drivers/rtc/dev_soft_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,6 @@ #endif static struct rt_work rtc_sync_work; -static rt_device_t source_device = RT_NULL; static struct rt_device soft_rtc_dev; static rt_tick_t init_tick; @@ -82,18 +81,6 @@ static void set_rtc_time(time_t t) #endif } -static void _source_device_control(int cmd, void *args) -{ - if (source_device == RT_NULL) - return; - - if (rt_device_open(source_device, 0) == RT_EOK) - { - rt_device_control(source_device, cmd, args); - rt_device_close(source_device); - } -} - static rt_err_t soft_rtc_control(rt_device_t dev, int cmd, void *args) { time_t *t; @@ -114,7 +101,6 @@ static rt_err_t soft_rtc_control(rt_device_t dev, int cmd, void *args) { t = (time_t *) args; set_rtc_time(*t); - _source_device_control(RT_DEVICE_CTRL_RTC_SET_TIME, t); break; } #ifdef RT_USING_ALARM @@ -143,7 +129,6 @@ static rt_err_t soft_rtc_control(rt_device_t dev, int cmd, void *args) rt_ktime_boottime_get_us(&_tv); set_rtc_time(tv->tv_sec); init_tv.tv_usec = tv->tv_usec - _tv.tv_usec; - _source_device_control(RT_DEVICE_CTRL_RTC_SET_TIME, &(tv->tv_sec)); break; } case RT_DEVICE_CTRL_RTC_GET_TIMESPEC: @@ -162,7 +147,6 @@ static rt_err_t soft_rtc_control(rt_device_t dev, int cmd, void *args) rt_ktime_boottime_get_ns(&_ts); set_rtc_time(ts->tv_sec); init_ts.tv_nsec = ts->tv_nsec - _ts.tv_nsec; - _source_device_control(RT_DEVICE_CTRL_RTC_SET_TIME, &(ts->tv_sec)); break; } case RT_DEVICE_CTRL_RTC_GET_TIMERES: @@ -187,7 +171,6 @@ static rt_err_t soft_rtc_control(rt_device_t dev, int cmd, void *args) rt_tick_t tick = rt_tick_get() - init_tick; set_rtc_time(tv->tv_sec); init_tv.tv_usec = tv->tv_usec - ((tick % RT_TICK_PER_SECOND) * (1000000 / RT_TICK_PER_SECOND)); - _source_device_control(RT_DEVICE_CTRL_RTC_SET_TIME, &(tv->tv_sec)); break; } case RT_DEVICE_CTRL_RTC_GET_TIMERES: @@ -227,6 +210,9 @@ static int rt_soft_rtc_init(void) return 0; } /* make sure only one 'rtc' device */ +#if defined(RT_USING_SOFT_RTC) && defined(BSP_USING_ONCHIP_RTC) +#warning "Please note: Currently only one RTC device is allowed in the system, and the name is "rtc"." +#endif RT_ASSERT(!rt_device_find("rtc")); #ifdef RT_USING_ALARM @@ -272,13 +258,7 @@ rt_err_t rt_soft_rtc_sync(void) { time_t time = 0; - if (source_device == RT_NULL) - { - rt_kprintf("error: rtc source not found, please set it!!!\n"); - return RT_ENOSYS; - } - - _source_device_control(RT_DEVICE_CTRL_RTC_GET_TIME, &time); + rt_device_control(&soft_rtc_dev, RT_DEVICE_CTRL_RTC_GET_TIME, &time); set_rtc_time(time); return RT_EOK; } @@ -292,9 +272,8 @@ static void rtc_sync_work_func(struct rt_work *work, void *work_data) rt_err_t rt_soft_rtc_set_source(const char *name) { RT_ASSERT(name != RT_NULL); - RT_ASSERT(rt_device_find(name)); // make sure source is exist + RT_ASSERT(rt_device_find(name)); /* make sure source is exist*/ - source_device = rt_device_find(name); rt_work_init(&rtc_sync_work, rtc_sync_work_func, RT_NULL); rt_work_submit(&rtc_sync_work, rt_tick_from_millisecond(RTC_AUTO_SYNC_FIRST_DELAY * 1000)); @@ -317,7 +296,7 @@ static void cmd_rtc_sync(int argc, char **argv) rt_kprintf("local time: %.*s", 25, ctime(&now)); rt_kprintf("timestamps: %ld\n", (long)tv.tv_sec); } -MSH_CMD_EXPORT_ALIAS(cmd_rtc_sync, rtc_sync, Update time by real rtc); +MSH_CMD_EXPORT_ALIAS(cmd_rtc_sync, rtc_sync, Update time by soft rtc); #endif #endif /* RT_USING_SYSTEM_WORKQUEUE */ diff --git a/rt-thread/components/drivers/scsi/Kconfig b/rt-thread/components/drivers/scsi/Kconfig new file mode 100644 index 0000000..ba22188 --- /dev/null +++ b/rt-thread/components/drivers/scsi/Kconfig @@ -0,0 +1,20 @@ +menuconfig RT_USING_SCSI + bool "Using Small Computer System Interface (SCSI)" + depends on RT_USING_DM + default n + +config RT_SCSI_SD + bool "SD device on SCSI" + depends on RT_USING_SCSI + depends on RT_USING_BLK + default y + +config RT_SCSI_CDROM + bool "CD-ROM device on SCSI" + depends on RT_USING_SCSI + depends on RT_USING_BLK + default y + +if RT_USING_SCSI + osource "$(SOC_DM_SCSI_DIR)/Kconfig" +endif diff --git a/rt-thread/components/drivers/scsi/SConscript b/rt-thread/components/drivers/scsi/SConscript new file mode 100644 index 0000000..328d929 --- /dev/null +++ b/rt-thread/components/drivers/scsi/SConscript @@ -0,0 +1,21 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_SCSI']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] + +src = ['scsi.c'] + +if GetDepend(['RT_SCSI_SD']): + src += ['scsi_sd.c'] + +if GetDepend(['RT_SCSI_CDROM']): + src += ['scsi_cdrom.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/scsi/scsi.c b/rt-thread/components/drivers/scsi/scsi.c new file mode 100644 index 0000000..f5ac977 --- /dev/null +++ b/rt-thread/components/drivers/scsi/scsi.c @@ -0,0 +1,669 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "rtdm.scsi" +#define DBG_LVL DBG_INFO +#include + +/* + * Since SCSI is used for storage (almost), + * we do not want to implement SCSI as a system DM bus. + */ +struct scsi_driver +{ + rt_err_t (*probe)(struct rt_scsi_device *sdev); + rt_err_t (*remove)(struct rt_scsi_device *sdev); +}; + +extern rt_err_t scsi_sd_probe(struct rt_scsi_device *sdev); +extern rt_err_t scsi_sd_remove(struct rt_scsi_device *sdev); + +extern rt_err_t scsi_cdrom_probe(struct rt_scsi_device *sdev); +extern rt_err_t scsi_cdrom_remove(struct rt_scsi_device *sdev); + +static struct scsi_driver driver_table[SCSI_DEVICE_TYPE_MAX] = +{ +#ifdef RT_SCSI_SD + [SCSI_DEVICE_TYPE_DIRECT] = + { + .probe = scsi_sd_probe, + .remove = scsi_sd_remove, + }, +#endif /* RT_SCSI_SD */ +#ifdef RT_SCSI_CDROM + [SCSI_DEVICE_TYPE_CDROM] = + { + .probe = scsi_cdrom_probe, + .remove = scsi_cdrom_remove, + }, +#endif /* RT_SCSI_CDROM */ +}; + +static rt_err_t scsi_device_setup(struct rt_scsi_device *sdev) +{ + rt_err_t err; + rt_tick_t timeout; + + if (sdev->host->ops->reset) + { + if ((err = sdev->host->ops->reset(sdev))) + { + return err; + } + } + + if (!driver_table[sdev->devtype].probe) + { + LOG_E("Device type %x is not supported", sdev->devtype); + + return -RT_ENOSYS; + } + + timeout = rt_tick_from_millisecond(5000); + timeout += rt_tick_get(); + + while ((err = rt_scsi_test_unit_ready(sdev))) + { + if (rt_tick_get() >= timeout) + { + return -RT_ETIMEOUT; + } + } + + return driver_table[sdev->devtype].probe(sdev); +} + +rt_err_t rt_scsi_host_register(struct rt_scsi_host *scsi) +{ + struct rt_scsi_device tmp_sdev, *sdev; + + if (!scsi || !scsi->dev || !scsi->ops) + { + return -RT_EINVAL; + } + + if (!scsi->max_id || !scsi->max_lun) + { + return -RT_EINVAL; + } + + rt_list_init(&scsi->lun_nodes); + + rt_memset(&tmp_sdev, 0, sizeof(tmp_sdev)); + tmp_sdev.host = scsi; + + for (rt_size_t id = 0; id < scsi->max_id; ++id) + { + for (rt_size_t lun = 0; lun < scsi->max_lun; ++lun) + { + tmp_sdev.id = id; + tmp_sdev.lun = lun; + + if (rt_scsi_inquiry(&tmp_sdev, RT_NULL)) + { + continue; + } + + if (tmp_sdev.devtype >= SCSI_DEVICE_TYPE_MAX) + { + /* + * This might seem odd, but we're only aiming to + * support simple SCSI. + * If devices appear on the bus out of order, + * we won't perform additional scans. + */ + scsi->max_id = id; + scsi->max_lun = lun; + + LOG_D("Scan is end of ID: %u LUN: %u", id, lun); + break; + } + + if (!(sdev = rt_malloc(sizeof(*sdev)))) + { + if (!rt_list_isempty(&scsi->lun_nodes)) + { + LOG_E("No memory to create device ID: %u, LUN: %u", id, lun); + + return RT_EOK; + } + + return -RT_ENOMEM; + } + + rt_memcpy(sdev, &tmp_sdev, sizeof(*sdev)); + rt_list_init(&sdev->list); + + if (scsi_device_setup(sdev)) + { + rt_free(sdev); + continue; + } + + rt_list_insert_before(&scsi->lun_nodes, &sdev->list); + } + } + + return rt_list_isempty(&scsi->lun_nodes) ? -RT_EEMPTY : RT_EOK; +} + +rt_err_t rt_scsi_host_unregister(struct rt_scsi_host *scsi) +{ + struct rt_scsi_device *sdev, *next_sdev; + + if (!scsi) + { + return -RT_EINVAL; + } + + rt_list_for_each_entry_safe(sdev, next_sdev, &scsi->lun_nodes, list) + { + rt_list_remove(&sdev->list); + + if (sdev->host->ops->reset) + { + sdev->host->ops->reset(sdev); + } + + if (!driver_table[sdev->devtype].remove) + { + driver_table[sdev->devtype].remove(sdev); + } + + rt_free(sdev); + } + + return RT_EOK; +} + +rt_inline rt_err_t scsi_transfer(struct rt_scsi_device *sdev, struct rt_scsi_cmd *cmd) +{ + return sdev->host->ops->transfer(sdev, cmd); +} + +rt_err_t rt_scsi_request_sense(struct rt_scsi_device *sdev, + struct rt_scsi_request_sense_data *out_data) +{ + rt_err_t err; + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.request_sense.opcode = RT_SCSI_CMD_REQUEST_SENSE; + cmd.op.request_sense.config = 0; + cmd.op.request_sense.alloc_length = 0x12; + cmd.op.request_sense.control = 0; + cmd.op_size = sizeof(cmd.op.request_sense); + cmd.data.ptr = &cmd.data.request_sense; + cmd.data.size = sizeof(cmd.data.request_sense); + + err = scsi_transfer(sdev, &cmd); + + if (!err && out_data) + { + rt_memcpy(out_data, &cmd.data.request_sense, sizeof(*out_data)); + } + + return err; +} + +rt_err_t rt_scsi_test_unit_ready(struct rt_scsi_device *sdev) +{ + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.test_unit_ready.opcode = RT_SCSI_CMD_TEST_UNIT_READY; + cmd.op.test_unit_ready.control = 0; + cmd.op_size = sizeof(cmd.op.test_unit_ready); + + return scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); +} + +rt_err_t rt_scsi_inquiry(struct rt_scsi_device *sdev, + struct rt_scsi_inquiry_data *out_data) +{ + rt_err_t err; + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.inquiry.opcode = RT_SCSI_CMD_INQUIRY; + cmd.op.inquiry.config = 0; + cmd.op.inquiry.page = 0; + cmd.op.inquiry.alloc_length = 0x24; + cmd.op.inquiry.control = 0; + cmd.op_size = sizeof(cmd.op.inquiry); + cmd.data.ptr = &cmd.data.inquiry; + cmd.data.size = sizeof(cmd.data.inquiry); + + err = scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); + + if (!err) + { + sdev->devtype = cmd.data.inquiry.devtype & RT_SCSI_DEVTYPE_MASK; + sdev->removable = cmd.data.inquiry.rmb >> RT_SCSI_REMOVABLE_BIT; + + if (out_data) + { + rt_memcpy(out_data, &cmd.data.inquiry, sizeof(*out_data)); + } + } + + return err; +} + +rt_err_t rt_scsi_read_capacity10(struct rt_scsi_device *sdev, + struct rt_scsi_read_capacity10_data *out_data) +{ + rt_err_t err; + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.read_capacity10.opcode = RT_SCSI_CMD_READ_CAPACITY10; + cmd.op.read_capacity10.config = 0; + cmd.op.read_capacity10.logical_block_addr = 0; + cmd.op.read_capacity10.pmi = 0; + cmd.op.read_capacity10.control = 0; + cmd.op_size = sizeof(cmd.op.read_capacity10); + cmd.data.ptr = &cmd.data.read_capacity10; + cmd.data.size = sizeof(cmd.data.read_capacity10); + + err = scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); + + if (!err) + { + sdev->last_block = rt_be32_to_cpu(cmd.data.read_capacity10.last_block); + sdev->block_size = rt_be32_to_cpu(cmd.data.read_capacity10.block_size); + + if (out_data) + { + rt_memcpy(out_data, &cmd.data.read_capacity10, sizeof(*out_data)); + } + } + + return err; +} + +rt_err_t rt_scsi_read_capacity16(struct rt_scsi_device *sdev, + struct rt_scsi_read_capacity16_data *out_data) +{ + rt_err_t err; + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.read_capacity16.opcode = RT_SCSI_CMD_READ_CAPACITY16; + cmd.op.read_capacity16.config = 0x10; + cmd.op.read_capacity16.logical_block_addr = 0; + cmd.op.read_capacity16.alloc_len = rt_cpu_to_be32(sizeof(cmd.data.read_capacity16)); + cmd.op.read_capacity16.pmi = 0; + cmd.op.read_capacity16.control = 0; + cmd.op_size = sizeof(cmd.op.read_capacity16); + cmd.data.ptr = &cmd.data.read_capacity16; + cmd.data.size = sizeof(cmd.data.read_capacity16); + + err = scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); + + if (!err) + { + sdev->last_block = rt_be64_to_cpu(cmd.data.read_capacity16.last_block); + sdev->block_size = rt_be32_to_cpu(cmd.data.read_capacity16.block_size); + + if (out_data) + { + rt_memcpy(out_data, &cmd.data.read_capacity16, sizeof(*out_data)); + } + } + + return err; +} + +rt_err_t rt_scsi_read10(struct rt_scsi_device *sdev, + rt_off_t lba, void *buffer, rt_size_t size) +{ + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.read10.opcode = RT_SCSI_CMD_READ10; + cmd.op.read10.config = 0; + cmd.op.read10.lba = rt_cpu_to_be32(lba); + cmd.op.read10.size = rt_cpu_to_be16(size); + cmd.op_size = sizeof(cmd.op.read10); + cmd.data.ptr = buffer; + cmd.data.size = size * sdev->block_size; + + return scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); +} + +rt_err_t rt_scsi_read12(struct rt_scsi_device *sdev, + rt_off_t lba, void *buffer, rt_size_t size) +{ + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.read12.opcode = RT_SCSI_CMD_READ12; + cmd.op.read12.config = 0; + cmd.op.read12.lba = rt_cpu_to_be32(lba); + cmd.op.read12.size = rt_cpu_to_be32(size); + cmd.op.read12.control = 0; + cmd.op_size = sizeof(cmd.op.read12); + cmd.data.ptr = buffer; + cmd.data.size = size * sdev->block_size; + + return scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); +} + +rt_err_t rt_scsi_read16(struct rt_scsi_device *sdev, + rt_off_t lba, void *buffer, rt_size_t size) +{ + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.read16.opcode = RT_SCSI_CMD_READ16; + cmd.op.read16.config = 0; + cmd.op.read16.lba = rt_cpu_to_be64(lba); + cmd.op.read16.size = rt_cpu_to_be32(size); + cmd.op.read16.control = 0; + cmd.op_size = sizeof(cmd.op.read16); + cmd.data.ptr = buffer; + cmd.data.size = size * sdev->block_size; + + return scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); +} + +rt_err_t rt_scsi_write10(struct rt_scsi_device *sdev, + rt_off_t lba, const void *buffer, rt_size_t size) +{ + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.write10.opcode = RT_SCSI_CMD_WRITE10; + cmd.op.write10.config = 0; + cmd.op.write10.lba = rt_cpu_to_be32(lba); + cmd.op.write10.size = rt_cpu_to_be16(size); + cmd.op_size = sizeof(cmd.op.write10); + cmd.data.ptr = (void *)buffer; + cmd.data.size = size * sdev->block_size; + + return scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); +} + +rt_err_t rt_scsi_write12(struct rt_scsi_device *sdev, + rt_off_t lba, const void *buffer, rt_size_t size) +{ + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.write12.opcode = RT_SCSI_CMD_WRITE12; + cmd.op.write12.config = 0; + cmd.op.write12.lba = rt_cpu_to_be32(lba); + cmd.op.write12.size = rt_cpu_to_be32(size); + cmd.op.write12.control = 0; + cmd.op_size = sizeof(cmd.op.write12); + cmd.data.ptr = (void *)buffer; + cmd.data.size = size * sdev->block_size; + + return scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); +} + +rt_err_t rt_scsi_write16(struct rt_scsi_device *sdev, + rt_off_t lba, const void *buffer, rt_size_t size) +{ + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.write16.opcode = RT_SCSI_CMD_WRITE16; + cmd.op.write16.config = 0; + cmd.op.write16.lba = rt_cpu_to_be64(lba); + cmd.op.write16.size = rt_cpu_to_be32(size); + cmd.op.write16.control = 0; + cmd.op_size = sizeof(cmd.op.write16); + cmd.data.ptr = (void *)buffer; + cmd.data.size = size * sdev->block_size; + + return scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); +} + +rt_err_t rt_scsi_synchronize_cache10(struct rt_scsi_device *sdev, + rt_off_t lba, rt_size_t size) +{ + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.synchronize_cache10.opcode = RT_SCSI_CMD_SYNCHRONIZE_CACHE10; + cmd.op.synchronize_cache10.config = 0; + cmd.op.synchronize_cache10.lba = rt_cpu_to_be32(lba); + cmd.op.synchronize_cache10.size = rt_cpu_to_be16(size); + cmd.op.synchronize_cache10.control = 0; + cmd.op_size = sizeof(cmd.op.synchronize_cache10); + + return scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); +} + +rt_err_t rt_scsi_synchronize_cache16(struct rt_scsi_device *sdev, + rt_off_t lba, rt_size_t size) +{ + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.synchronize_cache16.opcode = RT_SCSI_CMD_SYNCHRONIZE_CACHE16; + cmd.op.synchronize_cache16.config = 0; + cmd.op.synchronize_cache16.lba = rt_cpu_to_be64(lba); + cmd.op.synchronize_cache16.size = rt_cpu_to_be32(size); + cmd.op.synchronize_cache16.control = 0; + cmd.op_size = sizeof(cmd.op.synchronize_cache16); + + return scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); +} + +rt_err_t rt_scsi_write_same10(struct rt_scsi_device *sdev, + rt_off_t lba, rt_size_t size) +{ + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.write_same10.opcode = RT_SCSI_CMD_WRITE_SAME10; + cmd.op.write_same10.config = RT_BIT(RT_SCSI_UNMAP_SHIFT); + cmd.op.write_same10.lba = rt_cpu_to_be32(lba); + cmd.op.write_same10.size = rt_cpu_to_be16(size); + cmd.op.write_same10.control = 0; + cmd.op_size = sizeof(cmd.op.write_same10); + + return scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); +} + +rt_err_t rt_scsi_write_same16(struct rt_scsi_device *sdev, + rt_off_t lba, rt_size_t size) +{ + struct rt_scsi_cmd cmd; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.write_same16.opcode = RT_SCSI_CMD_WRITE_SAME16; + cmd.op.write_same16.config = RT_BIT(RT_SCSI_UNMAP_SHIFT); + cmd.op.write_same16.lba = rt_cpu_to_be64(lba); + cmd.op.write_same16.size = rt_cpu_to_be32(size); + cmd.op.write_same16.control = 0; + cmd.op_size = sizeof(cmd.op.write_same16); + + return scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); +} + +rt_err_t rt_scsi_mode_select6(struct rt_scsi_device *sdev, + rt_uint8_t pf, rt_uint8_t sp, void *buffer, rt_size_t size, + struct rt_scsi_mode_select_data *data) +{ + rt_err_t err; + rt_uint8_t *real_buffer; + struct rt_scsi_cmd cmd; + + real_buffer = rt_malloc(4 + size); + + if (!real_buffer) + { + return -RT_ENOMEM; + } + + rt_memcpy(real_buffer + 4, buffer, size); + size += 4; + real_buffer[0] = 0; + real_buffer[1] = data->medium_type; + real_buffer[2] = data->device_specific; + real_buffer[3] = data->block_descriptor_length; + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.mode_select6.opcode = RT_SCSI_CMD_MODE_SELECT; + cmd.op.mode_select6.config = pf ? RT_BIT(RT_SCSI_PF_SHIFT) : 0; + cmd.op.mode_select6.config |= sp ? RT_BIT(RT_SCSI_SP_SHIFT) : 0; + cmd.op.mode_select6.param_list_len = (rt_uint8_t)size; + cmd.op.mode_select6.control = 0; + cmd.op_size = sizeof(cmd.op.mode_select6); + cmd.data.ptr = real_buffer; + cmd.data.size = size; + + err = scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); + + rt_free(real_buffer); + + return err; +} + +rt_err_t rt_scsi_mode_select10(struct rt_scsi_device *sdev, + rt_uint8_t pf, rt_uint8_t sp, void *buffer, rt_size_t size, + struct rt_scsi_mode_select_data *data) +{ + rt_err_t err; + rt_uint8_t *real_buffer; + struct rt_scsi_cmd cmd; + + real_buffer = rt_malloc(8 + size); + + if (!real_buffer) + { + return -RT_ENOMEM; + } + + rt_memcpy(real_buffer + 8, buffer, size); + size += 8; + real_buffer[0] = 0; + real_buffer[1] = 0; + real_buffer[2] = data->medium_type; + real_buffer[3] = data->device_specific; + real_buffer[4] = data->longlba ? 0x01 : 0; + real_buffer[5] = 0; + real_buffer[6] = rt_cpu_to_be16(data->block_descriptor_length); + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.mode_select10.opcode = RT_SCSI_CMD_MODE_SELECT10; + cmd.op.mode_select10.config = pf ? RT_BIT(RT_SCSI_PF_SHIFT) : 0; + cmd.op.mode_select10.config |= sp ? RT_BIT(RT_SCSI_SP_SHIFT) : 0; + cmd.op.mode_select10.param_list_len = rt_cpu_to_be16(size); + cmd.op.mode_select10.control = 0; + cmd.op_size = sizeof(cmd.op.mode_select10); + cmd.data.ptr = real_buffer; + cmd.data.size = size; + + err = scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); + + rt_free(real_buffer); + + return err; +} + +static void scsi_mode_sense_fill(struct rt_scsi_mode_select_data *data, + rt_uint8_t modepage, rt_uint8_t *buffer, rt_bool_t use10) +{ + if (buffer[0] == 0x86 && buffer[1] == 0x0b && (modepage == 6 || modepage == 8)) + { + data->header_length = 0; + data->length = 13; + data->medium_type = 0; + data->device_specific = 0; + data->longlba = 0; + data->block_descriptor_length = 0; + } + else if (use10) + { + data->length = rt_be16_to_cpu(buffer[0]) + 2; + data->medium_type = buffer[2]; + data->device_specific = buffer[3]; + data->longlba = buffer[4] & 0x01; + data->block_descriptor_length = rt_be16_to_cpu(buffer[6]); + } + else + { + data->length = buffer[0] + 1; + data->medium_type = buffer[1]; + data->device_specific = buffer[2]; + data->block_descriptor_length = buffer[3]; + } +} + +rt_err_t rt_scsi_mode_sense6(struct rt_scsi_device *sdev, + rt_uint8_t dbd, rt_uint8_t modepage, rt_uint8_t subpage, void *buffer, rt_size_t size, + struct rt_scsi_mode_select_data *data) +{ + rt_err_t err; + struct rt_scsi_cmd cmd; + + rt_memset(buffer, 0, size); + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.mode_sense6.opcode = RT_SCSI_CMD_MODE_SENSE; + cmd.op.mode_sense6.config = dbd & 0x18; + cmd.op.mode_sense6.page_control_code = modepage; + cmd.op.mode_sense6.subpage_code = subpage; + cmd.op.mode_sense6.allocation_len = (rt_uint8_t)size; + cmd.op.mode_sense6.control = 0; + cmd.op_size = sizeof(cmd.op.mode_sense6); + cmd.data.ptr = buffer; + cmd.data.size = size; + + err = scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); + + if (!err) + { + data->header_length = 4; + scsi_mode_sense_fill(data, modepage, buffer, RT_FALSE); + } + + return err; +} + +rt_err_t rt_scsi_mode_sense10(struct rt_scsi_device *sdev, + rt_uint8_t dbd, rt_uint8_t modepage, rt_uint8_t subpage, void *buffer, rt_size_t size, + struct rt_scsi_mode_select_data *data) +{ + rt_err_t err; + struct rt_scsi_cmd cmd; + + rt_memset(buffer, 0, size); + + rt_memset(&cmd, 0, sizeof(cmd)); + cmd.op.mode_sense6.opcode = RT_SCSI_CMD_MODE_SENSE10; + cmd.op.mode_sense6.config = dbd & 0x18; + cmd.op.mode_sense6.page_control_code = modepage; + cmd.op.mode_sense6.subpage_code = subpage; + cmd.op.mode_sense6.allocation_len = rt_cpu_to_be16(size); + cmd.op.mode_sense6.control = 0; + cmd.op_size = sizeof(cmd.op.mode_sense6); + cmd.data.ptr = buffer; + cmd.data.size = size; + + err = scsi_transfer(sdev, &cmd) ? : rt_scsi_request_sense(sdev, RT_NULL); + + if (!err) + { + data->header_length = 8; + scsi_mode_sense_fill(data, modepage, buffer, RT_FALSE); + } + + return err; +} diff --git a/rt-thread/components/drivers/scsi/scsi_cdrom.c b/rt-thread/components/drivers/scsi/scsi_cdrom.c new file mode 100644 index 0000000..93608d1 --- /dev/null +++ b/rt-thread/components/drivers/scsi/scsi_cdrom.c @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "scsi.blk" +#define DBG_LVL DBG_INFO +#include + +struct scsi_cdrom +{ + struct rt_blk_disk parent; + struct rt_scsi_device *sdev; + + int cdrom_id; + struct rt_device_blk_geometry geometry; +}; + +#define raw_to_scsi_cdrom(raw) rt_container_of(raw, struct scsi_cdrom, parent) + +static struct rt_dm_ida cdrom_ida = RT_DM_IDA_INIT(CUSTOM); +static struct rt_dm_ida scsi_cdrom_ida = RT_DM_IDA_INIT(SCSI_CDROM); + +static rt_ssize_t scsi_cdrom_read(struct rt_blk_disk *disk, rt_off_t sector, + void *buffer, rt_size_t sector_count) +{ + rt_err_t err; + struct scsi_cdrom *scdrom = raw_to_scsi_cdrom(disk); + struct rt_scsi_device *sdev = scdrom->sdev; + + sector_count &= RT_UINT32_MAX; + + if (sector >> 32) + { + err = rt_scsi_read16(sdev, sector, buffer, sector_count); + } + else + { + err = rt_scsi_read12(sdev, sector, buffer, sector_count); + } + + return !err ? sector_count : (rt_ssize_t)err; +} + +static rt_err_t scsi_cdrom_getgeome(struct rt_blk_disk *disk, + struct rt_device_blk_geometry *geometry) +{ + struct scsi_cdrom *scdrom = raw_to_scsi_cdrom(disk); + + rt_memcpy(geometry, &scdrom->geometry, sizeof(scdrom->geometry)); + + return RT_EOK; +} + +static const struct rt_blk_disk_ops scsi_cdrom_ops = +{ + .read = scsi_cdrom_read, + .getgeome = scsi_cdrom_getgeome, +}; + +rt_err_t scsi_cdrom_probe(struct rt_scsi_device *sdev) +{ + rt_err_t err; + union + { + struct rt_scsi_read_capacity10_data capacity10; + struct rt_scsi_read_capacity16_data capacity16; + } data; + struct scsi_cdrom *scdrom = rt_calloc(1, sizeof(*scdrom)); + + if (!scdrom) + { + return -RT_ENOMEM; + } + + if ((scdrom->cdrom_id = rt_dm_ida_alloc(&cdrom_ida)) < 0) + { + return -RT_EFULL; + } + + sdev->priv = scdrom; + scdrom->sdev = sdev; + scdrom->parent.ida = &scsi_cdrom_ida; + scdrom->parent.read_only = RT_TRUE; + scdrom->parent.parallel_io = RT_FALSE; + scdrom->parent.ops = &scsi_cdrom_ops; + scdrom->parent.max_partitions = RT_BLK_PARTITION_NONE; + + if ((err = rt_scsi_read_capacity10(sdev, &data.capacity10))) + { + goto _fail; + } + if (data.capacity10.last_block == 0xffffffff) + { + if ((err = rt_scsi_read_capacity16(sdev, &data.capacity16))) + { + goto _fail; + } + } + scdrom->geometry.bytes_per_sector = sdev->block_size; + scdrom->geometry.block_size = sdev->block_size; + scdrom->geometry.sector_count = sdev->last_block + 1; + + rt_dm_dev_set_name(&scdrom->parent.parent, "cdrom%u", scdrom->cdrom_id); + + if ((err = rt_hw_blk_disk_register(&scdrom->parent))) + { + goto _fail; + } + + return RT_EOK; + +_fail: + rt_dm_ida_free(&cdrom_ida, scdrom->cdrom_id); + rt_free(scdrom); + + return err; +} + +rt_err_t scsi_cdrom_remove(struct rt_scsi_device *sdev) +{ + struct scsi_cdrom *scdrom = sdev->priv; + + rt_dm_ida_free(&cdrom_ida, scdrom->cdrom_id); + + return rt_hw_blk_disk_unregister(&scdrom->parent); +} diff --git a/rt-thread/components/drivers/scsi/scsi_sd.c b/rt-thread/components/drivers/scsi/scsi_sd.c new file mode 100644 index 0000000..cc509a7 --- /dev/null +++ b/rt-thread/components/drivers/scsi/scsi_sd.c @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-25 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "scsi.blk" +#define DBG_LVL DBG_INFO +#include + +#include "../block/blk_dev.h" + +struct scsi_sd +{ + struct rt_blk_disk parent; + struct rt_scsi_device *sdev; + + int sd_id; + rt_bool_t use16; + struct rt_device_blk_geometry geometry; +}; + +#define raw_to_scsi_sd(raw) rt_container_of(raw, struct scsi_sd, parent) + +static struct rt_dm_ida sd_ida = RT_DM_IDA_INIT(CUSTOM); +static struct rt_dm_ida scsi_sd_ida = RT_DM_IDA_INIT(SCSI_SD); + +static rt_ssize_t scsi_sd_read(struct rt_blk_disk *disk, rt_off_t sector, + void *buffer, rt_size_t sector_count) +{ + rt_err_t err; + struct scsi_sd *ssd = raw_to_scsi_sd(disk); + struct rt_scsi_device *sdev = ssd->sdev; + + sector_count &= RT_UINT32_MAX; + + if (sector >> 32) + { + err = rt_scsi_read16(sdev, sector, buffer, sector_count); + } + else + { + err = rt_scsi_read10(sdev, sector, buffer, sector_count); + } + + return !err ? sector_count : (rt_ssize_t)err; +} + +static rt_ssize_t scsi_sd_write(struct rt_blk_disk *disk, rt_off_t sector, + const void *buffer, rt_size_t sector_count) +{ + rt_err_t err; + struct scsi_sd *ssd = raw_to_scsi_sd(disk); + struct rt_scsi_device *sdev = ssd->sdev; + + sector_count &= RT_UINT32_MAX; + + if (sector >> 32) + { + err = rt_scsi_write16(sdev, sector, buffer, sector_count); + } + else + { + err = rt_scsi_write10(sdev, sector, buffer, sector_count); + } + + return !err ? sector_count : (rt_ssize_t)err; +} + +static rt_err_t scsi_sd_getgeome(struct rt_blk_disk *disk, + struct rt_device_blk_geometry *geometry) +{ + struct scsi_sd *ssd = raw_to_scsi_sd(disk); + + rt_memcpy(geometry, &ssd->geometry, sizeof(ssd->geometry)); + + return RT_EOK; +} + +static rt_err_t scsi_sd_sync(struct rt_blk_disk *disk) +{ + rt_err_t err; + rt_size_t lba_count; + struct scsi_sd *ssd = raw_to_scsi_sd(disk); + struct rt_scsi_device *sdev = ssd->sdev; + + lba_count = ssd->geometry.sector_count; + + if (ssd->use16) + { + err = rt_scsi_synchronize_cache16(sdev, 0, lba_count); + } + else + { + err = rt_scsi_synchronize_cache10(sdev, 0, lba_count); + } + + return err; +} + +static rt_err_t scsi_sd_erase(struct rt_blk_disk *disk) +{ + rt_err_t err; + rt_size_t lba_count; + struct scsi_sd *ssd = raw_to_scsi_sd(disk); + struct rt_scsi_device *sdev = ssd->sdev; + + lba_count = ssd->geometry.sector_count; + + if (ssd->use16) + { + err = rt_scsi_write_same16(sdev, 0, lba_count); + } + else + { + err = rt_scsi_write_same10(sdev, 0, lba_count); + } + + return err; +} + +static rt_err_t scsi_sd_autorefresh(struct rt_blk_disk *disk, rt_bool_t is_auto) +{ + rt_err_t err; + int sp; + rt_size_t size; + rt_uint8_t buffer[64]; + rt_uint8_t *buffer_data; + rt_bool_t use6 = RT_TRUE; + struct scsi_sd *ssd = raw_to_scsi_sd(disk); + struct rt_scsi_device *sdev = ssd->sdev; + struct rt_scsi_mode_select_data data; + + err = rt_scsi_mode_sense6(sdev, 0x08, 8, 0, buffer, sizeof(buffer), &data); + + if (err && err != -RT_ENOMEM) + { + use6 = RT_FALSE; + err = rt_scsi_mode_sense10(sdev, 0x08, 8, 0, buffer, sizeof(buffer), &data); + } + if (err) + { + return err; + } + + size = rt_min_t(rt_size_t, sizeof(buffer), + data.length - data.header_length - data.block_descriptor_length); + buffer_data = buffer + data.header_length + data.block_descriptor_length; + buffer_data[2] &= ~0x05; + buffer_data[2] |= (!!is_auto) << 2 | (!!is_auto); + sp = buffer_data[0] & 0x80 ? 1 : 0; + buffer_data[0] &= ~0x80; + data.device_specific = 0; + + if (use6) + { + err = rt_scsi_mode_select6(sdev, 1, sp, buffer_data, size, &data); + } + else + { + err = rt_scsi_mode_select10(sdev, 1, sp, buffer_data, size, &data); + } + + return err; +} + +static const struct rt_blk_disk_ops scsi_sd_ops = +{ + .read = scsi_sd_read, + .write = scsi_sd_write, + .getgeome = scsi_sd_getgeome, + .sync = scsi_sd_sync, + .erase = scsi_sd_erase, + .autorefresh = scsi_sd_autorefresh, +}; + +rt_err_t scsi_sd_probe(struct rt_scsi_device *sdev) +{ + rt_err_t err; + union + { + struct rt_scsi_read_capacity10_data capacity10; + struct rt_scsi_read_capacity16_data capacity16; + } data; + struct scsi_sd *ssd = rt_calloc(1, sizeof(*ssd)); + + if (!ssd) + { + return -RT_ENOMEM; + } + + if ((ssd->sd_id = rt_dm_ida_alloc(&sd_ida)) < 0) + { + return -RT_EFULL; + } + + sdev->priv = ssd; + ssd->sdev = sdev; + ssd->parent.ida = &scsi_sd_ida; + ssd->parent.parallel_io = RT_FALSE; + ssd->parent.ops = &scsi_sd_ops; + ssd->parent.max_partitions = RT_BLK_PARTITION_MAX; + + if ((err = rt_scsi_read_capacity10(sdev, &data.capacity10))) + { + goto _fail; + } + if (data.capacity10.last_block == 0xffffffff) + { + if ((err = rt_scsi_read_capacity16(sdev, &data.capacity16))) + { + goto _fail; + } + ssd->use16 = RT_TRUE; + } + ssd->geometry.bytes_per_sector = sdev->block_size; + ssd->geometry.block_size = sdev->block_size; + ssd->geometry.sector_count = sdev->last_block + 1; + + rt_dm_dev_set_name(&ssd->parent.parent, "sd%c%c", letter_name(ssd->sd_id)); + + if ((err = rt_hw_blk_disk_register(&ssd->parent))) + { + goto _fail; + } + + return RT_EOK; + +_fail: + rt_dm_ida_free(&sd_ida, ssd->sd_id); + rt_free(ssd); + + return err; +} + +rt_err_t scsi_sd_remove(struct rt_scsi_device *sdev) +{ + struct scsi_sd *ssd = sdev->priv; + + rt_dm_ida_free(&sd_ida, ssd->sd_id); + + return rt_hw_blk_disk_unregister(&ssd->parent); +} diff --git a/rt-thread/components/drivers/sdio/Kconfig b/rt-thread/components/drivers/sdio/Kconfig index e5bff45..dd1fe0a 100644 --- a/rt-thread/components/drivers/sdio/Kconfig +++ b/rt-thread/components/drivers/sdio/Kconfig @@ -1,5 +1,6 @@ config RT_USING_SDIO bool "Using SD/MMC device drivers" + select RT_USING_BLK default n if RT_USING_SDIO @@ -24,5 +25,8 @@ config RT_USING_SDIO default 16 config RT_SDIO_DEBUG bool "Enable SDIO debug log output" - default n - endif + default n + config RT_USING_SDHCI + bool "Using sdhci for sd/mmc drivers" + default n + endif diff --git a/rt-thread/components/drivers/sdio/SConscript b/rt-thread/components/drivers/sdio/SConscript index d5b6eb1..98d71d1 100644 --- a/rt-thread/components/drivers/sdio/SConscript +++ b/rt-thread/components/drivers/sdio/SConscript @@ -3,16 +3,20 @@ from building import * cwd = GetCurrentDir() src = Split(""" -block_dev.c -mmcsd_core.c -sd.c -sdio.c -gpt.c -mmc.c +dev_block.c +dev_mmcsd_core.c +dev_sd.c +dev_sdio.c +dev_mmc.c """) # The set of source files associated with this SConscript file. -path = [cwd + '/../include'] +path = [cwd + '/../include' , cwd + '/sdhci/include'] + +if GetDepend('RT_USING_SDHCI'): + src += [os.path.join('sdhci', 'sdhci.c')] + src += [os.path.join('sdhci', 'fit-mmc.c')] + src += [os.path.join('sdhci', 'sdhci-platform.c')] group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_SDIO'], CPPPATH = path) diff --git a/rt-thread/components/drivers/sdio/block_dev.c b/rt-thread/components/drivers/sdio/block_dev.c deleted file mode 100644 index fcef99f..0000000 --- a/rt-thread/components/drivers/sdio/block_dev.c +++ /dev/null @@ -1,952 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-07-25 weety first version - */ - -#include -#include -#include - -#include -#include - -#define DBG_TAG "SDIO" -#ifdef RT_SDIO_DEBUG -#define DBG_LVL DBG_LOG -#else -#define DBG_LVL DBG_INFO -#endif /* RT_SDIO_DEBUG */ -#include - -static rt_list_t blk_devices = RT_LIST_OBJECT_INIT(blk_devices); - -#define BLK_MIN(a, b) ((a) < (b) ? (a) : (b)) -#define RT_DEVICE_CTRL_BLK_SSIZEGET 0x1268 /**< get number of bytes per sector */ -#define RT_DEVICE_CTRL_ALL_BLK_SSIZEGET 0x80081272 /**< get number of bytes per sector * sector counts*/ - -struct mmcsd_blk_device -{ - struct rt_mmcsd_card *card; - rt_list_t list; - struct rt_device dev; - struct dfs_partition part; - struct rt_device_blk_geometry geometry; - rt_size_t max_req_size; -}; - -#ifndef RT_MMCSD_MAX_PARTITION -#define RT_MMCSD_MAX_PARTITION 16 -#endif -#define RT_GPT_PARTITION_MAX 128 - -static int __send_status(struct rt_mmcsd_card *card, rt_uint32_t *status, unsigned retries) -{ - int err; - struct rt_mmcsd_cmd cmd; - - cmd.busy_timeout = 0; - cmd.cmd_code = SEND_STATUS; - cmd.arg = card->rca << 16; - cmd.flags = RESP_R1 | CMD_AC; - err = mmcsd_send_cmd(card->host, &cmd, retries); - if (err) - return err; - - if (status) - *status = cmd.resp[0]; - - return 0; -} - -static int card_busy_detect(struct rt_mmcsd_card *card, unsigned int timeout_ms, - rt_uint32_t *resp_errs) -{ - int timeout = rt_tick_from_millisecond(timeout_ms); - int err = 0; - rt_uint32_t status; - rt_tick_t start; - - start = rt_tick_get(); - do - { - rt_bool_t out = (int)(rt_tick_get() - start) > timeout; - - err = __send_status(card, &status, 5); - if (err) - { - LOG_E("error %d requesting status", err); - return err; - } - - /* Accumulate any response error bits seen */ - if (resp_errs) - *resp_errs |= status; - - if (out) - { - LOG_E("wait card busy timeout"); - return -RT_ETIMEOUT; - } - /* - * Some cards mishandle the status bits, - * so make sure to check both the busy - * indication and the card state. - */ - } - while (!(status & R1_READY_FOR_DATA) || - (R1_CURRENT_STATE(status) == 7)); - - return err; -} - -rt_int32_t mmcsd_num_wr_blocks(struct rt_mmcsd_card *card) -{ - rt_int32_t err; - rt_uint32_t blocks; - - struct rt_mmcsd_req req; - struct rt_mmcsd_cmd cmd; - struct rt_mmcsd_data data; - rt_uint32_t timeout_us; - - rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd)); - - cmd.cmd_code = APP_CMD; - cmd.arg = card->rca << 16; - cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_AC; - - err = mmcsd_send_cmd(card->host, &cmd, 0); - if (err) - return -RT_ERROR; - if (!controller_is_spi(card->host) && !(cmd.resp[0] & R1_APP_CMD)) - return -RT_ERROR; - - rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd)); - - cmd.cmd_code = SD_APP_SEND_NUM_WR_BLKS; - cmd.arg = 0; - cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC; - - rt_memset(&data, 0, sizeof(struct rt_mmcsd_data)); - - data.timeout_ns = card->tacc_ns * 100; - data.timeout_clks = card->tacc_clks * 100; - - timeout_us = data.timeout_ns / 1000; - timeout_us += data.timeout_clks * 1000 / - (card->host->io_cfg.clock / 1000); - - if (timeout_us > 100000) - { - data.timeout_ns = 100000000; - data.timeout_clks = 0; - } - - data.blksize = 4; - data.blks = 1; - data.flags = DATA_DIR_READ; - data.buf = &blocks; - - rt_memset(&req, 0, sizeof(struct rt_mmcsd_req)); - - req.cmd = &cmd; - req.data = &data; - - mmcsd_send_request(card->host, &req); - - if (cmd.err || data.err) - return -RT_ERROR; - - return blocks; -} - -static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, - rt_uint32_t sector, - void *buf, - rt_size_t blks, - rt_uint8_t dir) -{ - struct rt_mmcsd_cmd cmd, stop; - struct rt_mmcsd_data data; - struct rt_mmcsd_req req; - struct rt_mmcsd_host *host = card->host; - rt_uint32_t r_cmd, w_cmd; - - mmcsd_host_lock(host); - rt_memset(&req, 0, sizeof(struct rt_mmcsd_req)); - rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd)); - rt_memset(&stop, 0, sizeof(struct rt_mmcsd_cmd)); - rt_memset(&data, 0, sizeof(struct rt_mmcsd_data)); - req.cmd = &cmd; - req.data = &data; - - cmd.arg = sector; - if (!(card->flags & CARD_FLAG_SDHC)) - { - cmd.arg <<= 9; - } - cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC; - - data.blksize = SECTOR_SIZE; - data.blks = blks; - - if (blks > 1) - { - if (!controller_is_spi(card->host) || !dir) - { - req.stop = &stop; - stop.cmd_code = STOP_TRANSMISSION; - stop.arg = 0; - stop.flags = RESP_SPI_R1B | RESP_R1B | CMD_AC; - } - r_cmd = READ_MULTIPLE_BLOCK; - w_cmd = WRITE_MULTIPLE_BLOCK; - } - else - { - req.stop = RT_NULL; - r_cmd = READ_SINGLE_BLOCK; - w_cmd = WRITE_BLOCK; - } - - if (!controller_is_spi(card->host) && (card->flags & 0x8000)) - { - /* last request is WRITE,need check busy */ - card_busy_detect(card, 10000, RT_NULL); - } - - if (!dir) - { - cmd.cmd_code = r_cmd; - data.flags |= DATA_DIR_READ; - card->flags &= 0x7fff; - } - else - { - cmd.cmd_code = w_cmd; - data.flags |= DATA_DIR_WRITE; - card->flags |= 0x8000; - } - - mmcsd_set_data_timeout(&data, card); - data.buf = buf; - - mmcsd_send_request(host, &req); - - mmcsd_host_unlock(host); - - if (cmd.err || data.err || stop.err) - { - LOG_E("mmcsd request blocks error"); - LOG_E("%d,%d,%d, 0x%08x,0x%08x", - cmd.err, data.err, stop.err, data.flags, sector); - - return -RT_ERROR; - } - - return RT_EOK; -} - -static rt_err_t rt_mmcsd_init(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_err_t rt_mmcsd_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -static rt_err_t rt_mmcsd_close(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_err_t rt_mmcsd_control(rt_device_t dev, int cmd, void *args) -{ - struct mmcsd_blk_device *blk_dev = (struct mmcsd_blk_device *)dev->user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_BLK_GETGEOME: - rt_memcpy(args, &blk_dev->geometry, sizeof(struct rt_device_blk_geometry)); - break; - case RT_DEVICE_CTRL_BLK_PARTITION: - rt_memcpy(args, &blk_dev->part, sizeof(struct dfs_partition)); - break; - case RT_DEVICE_CTRL_BLK_SSIZEGET: - rt_memcpy(args, &blk_dev->geometry.bytes_per_sector, sizeof(rt_uint32_t)); - break; - case RT_DEVICE_CTRL_ALL_BLK_SSIZEGET: - { - rt_uint64_t count_mul_per = blk_dev->geometry.bytes_per_sector * blk_dev->geometry.sector_count; - rt_memcpy(args, &count_mul_per, sizeof(rt_uint64_t)); - } - break; - default: - break; - } - return RT_EOK; -} - -static rt_ssize_t rt_mmcsd_read(rt_device_t dev, - rt_off_t pos, - void *buffer, - rt_size_t size) -{ - rt_err_t err = 0; - rt_size_t offset = 0; - rt_size_t req_size = 0; - rt_size_t remain_size = size; - void *rd_ptr = (void *)buffer; - struct mmcsd_blk_device *blk_dev = (struct mmcsd_blk_device *)dev->user_data; - struct dfs_partition *part = &blk_dev->part; - - if (dev == RT_NULL) - { - rt_set_errno(-EINVAL); - return 0; - } - - rt_sem_take(part->lock, RT_WAITING_FOREVER); - while (remain_size) - { - req_size = (remain_size > blk_dev->max_req_size) ? blk_dev->max_req_size : remain_size; - err = rt_mmcsd_req_blk(blk_dev->card, part->offset + pos + offset, rd_ptr, req_size, 0); - if (err) - break; - offset += req_size; - rd_ptr = (void *)((rt_uint8_t *)rd_ptr + (req_size << 9)); - remain_size -= req_size; - } - rt_sem_release(part->lock); - - /* the length of reading must align to SECTOR SIZE */ - if (err) - { - rt_set_errno(-EIO); - return 0; - } - return size - remain_size; -} - -static rt_ssize_t rt_mmcsd_write(rt_device_t dev, - rt_off_t pos, - const void *buffer, - rt_size_t size) -{ - rt_err_t err = 0; - rt_size_t offset = 0; - rt_size_t req_size = 0; - rt_size_t remain_size = size; - void *wr_ptr = (void *)buffer; - struct mmcsd_blk_device *blk_dev = (struct mmcsd_blk_device *)dev->user_data; - struct dfs_partition *part = &blk_dev->part; - - if (dev == RT_NULL) - { - rt_set_errno(-EINVAL); - return 0; - } - - rt_sem_take(part->lock, RT_WAITING_FOREVER); - while (remain_size) - { - req_size = (remain_size > blk_dev->max_req_size) ? blk_dev->max_req_size : remain_size; - err = rt_mmcsd_req_blk(blk_dev->card, part->offset + pos + offset, wr_ptr, req_size, 1); - if (err) - break; - offset += req_size; - wr_ptr = (void *)((rt_uint8_t *)wr_ptr + (req_size << 9)); - remain_size -= req_size; - } - rt_sem_release(part->lock); - - /* the length of reading must align to SECTOR SIZE */ - if (err) - { - rt_set_errno(-EIO); - - return 0; - } - return size - remain_size; -} - -static rt_int32_t mmcsd_set_blksize(struct rt_mmcsd_card *card) -{ - struct rt_mmcsd_cmd cmd; - int err; - - /* Block-addressed cards ignore MMC_SET_BLOCKLEN. */ - if (card->flags & CARD_FLAG_SDHC) - return 0; - - mmcsd_host_lock(card->host); - cmd.cmd_code = SET_BLOCKLEN; - cmd.arg = 512; - cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_AC; - err = mmcsd_send_cmd(card->host, &cmd, 5); - mmcsd_host_unlock(card->host); - - if (err) - { - LOG_E("MMCSD: unable to set block size to %d: %d", cmd.arg, err); - - return -RT_ERROR; - } - - return 0; -} -rt_int32_t read_lba(struct rt_mmcsd_card *card, size_t lba, uint8_t *buffer, size_t count) -{ - rt_uint8_t status = 0; - - status = mmcsd_set_blksize(card); - if (status) - { - return status; - } - rt_thread_mdelay(1); - status = rt_mmcsd_req_blk(card, lba, buffer, count, 0); - return status; -} - -#ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops mmcsd_blk_ops = -{ - rt_mmcsd_init, - rt_mmcsd_open, - rt_mmcsd_close, - rt_mmcsd_read, - rt_mmcsd_write, - rt_mmcsd_control -}; -#endif - -#ifdef RT_USING_DFS_V2 - -static ssize_t rt_mmcsd_fops_read(struct dfs_file *file, void *buf, size_t count, off_t *pos) -{ - int result = 0; - rt_device_t dev = (rt_device_t)file->vnode->data; - struct mmcsd_blk_device *blk_dev = (struct mmcsd_blk_device *)dev->user_data; - int bytes_per_sector = blk_dev->geometry.bytes_per_sector; - int blk_pos = *pos / bytes_per_sector; - int first_offs = *pos % bytes_per_sector; - char *rbuf; - int rsize = 0; - - rbuf = rt_malloc(bytes_per_sector); - if (!rbuf) - { - return 0; - } - - /* - ** #1: read first unalign block size. - */ - result = rt_mmcsd_read(dev, blk_pos, rbuf, 1); - if (result != 1) - { - rt_free(rbuf); - return 0; - } - - if (count > bytes_per_sector - first_offs) - { - rsize = bytes_per_sector - first_offs; - } - else - { - rsize = count; - } - rt_memcpy(buf, rbuf + first_offs, rsize); - blk_pos++; - - /* - ** #2: read continuous block size. - */ - while (rsize < count) - { - result = rt_mmcsd_read(dev, blk_pos++, rbuf, 1); - if (result != 1) - { - break; - } - - if (count - rsize >= bytes_per_sector) - { - rt_memcpy(buf + rsize, rbuf, bytes_per_sector); - rsize += bytes_per_sector; - } - else - { - rt_memcpy(buf + rsize, rbuf, count - rsize); - rsize = count; - } - } - - rt_free(rbuf); - *pos += rsize; - - return rsize; -} - -static int rt_mmcsd_fops_ioctl(struct dfs_file *file, int cmd, void *arg) -{ - rt_device_t dev = (rt_device_t)file->vnode->data; - - return rt_mmcsd_control(dev,cmd,arg); -} - -static int rt_mmcsd_fops_open(struct dfs_file *file) -{ - rt_device_t dev = (rt_device_t)file->vnode->data; - rt_mmcsd_control(dev, RT_DEVICE_CTRL_ALL_BLK_SSIZEGET, &file->vnode->size); - return RT_EOK; -} - -static int rt_mmcsd_fops_close(struct dfs_file *file) -{ - return RT_EOK; -} - -static ssize_t rt_mmcsd_fops_write(struct dfs_file *file, const void *buf, size_t count, off_t *pos) -{ - int result = 0; - rt_device_t dev = (rt_device_t)file->vnode->data; - struct mmcsd_blk_device *blk_dev = (struct mmcsd_blk_device *)dev->user_data; - int bytes_per_sector = blk_dev->geometry.bytes_per_sector; - int blk_pos = *pos / bytes_per_sector; - int first_offs = *pos % bytes_per_sector; - char *rbuf = 0; - int wsize = 0; - - /* - ** #1: write first unalign block size. - */ - if (first_offs != 0) - { - if (count > bytes_per_sector - first_offs) - { - wsize = bytes_per_sector - first_offs; - } - else - { - wsize = count; - } - - rbuf = rt_malloc(bytes_per_sector); - if (!rbuf) - { - return 0; - } - - result = rt_mmcsd_read(dev, blk_pos, rbuf, 1); - if (result != 1) - { - rt_free(rbuf); - return 0; - } - - rt_memcpy(rbuf + first_offs, buf, wsize); - result = rt_mmcsd_write(dev, blk_pos, rbuf, 1); - if (result != 1) - { - rt_free(rbuf); - return 0; - } - rt_free(rbuf); - blk_pos += 1; - } - - /* - ** #2: write continuous block size. - */ - if ((count - wsize) / bytes_per_sector != 0) - { - result = rt_mmcsd_write(dev, blk_pos, buf + wsize, (count - wsize) / bytes_per_sector); - wsize += result * bytes_per_sector; - blk_pos += result; - if (result != (count - wsize) / bytes_per_sector) - { - *pos += wsize; - return wsize; - } - } - - /* - ** # 3: write last unalign block size. - */ - if ((count - wsize) != 0) - { - rbuf = rt_malloc(bytes_per_sector); - if (rbuf != RT_NULL) - { - result = rt_mmcsd_read(dev, blk_pos, rbuf, 1); - if (result == 1) - { - rt_memcpy(rbuf, buf + wsize, count - wsize); - result = rt_mmcsd_write(dev, blk_pos, rbuf, 1); - if (result == 1) - { - wsize += count - wsize; - } - } - - rt_free(rbuf); - } - } - - *pos += wsize; - return wsize; -} - -static int rt_mmcsd_fops_poll(struct dfs_file *file, struct rt_pollreq *req) -{ - int mask = 0; - - return mask; -} - -static int rt_mmcsd_fops_flush(struct dfs_file *file) -{ - return RT_EOK; -} - -const static struct dfs_file_ops mmcsd_blk_fops = -{ - rt_mmcsd_fops_open, - rt_mmcsd_fops_close, - rt_mmcsd_fops_ioctl, - rt_mmcsd_fops_read, - rt_mmcsd_fops_write, - rt_mmcsd_fops_flush, - generic_dfs_lseek, - RT_NULL, - RT_NULL, - rt_mmcsd_fops_poll -}; -#endif - -rt_int32_t gpt_device_probe(struct rt_mmcsd_card *card) -{ - rt_int32_t err = RT_EOK; - rt_uint8_t i, status; - char dname[10]; - char sname[16]; - struct mmcsd_blk_device *blk_dev = RT_NULL; - - blk_dev = rt_calloc(1, sizeof(struct mmcsd_blk_device)); - if (!blk_dev) - { - LOG_E("mmcsd:malloc memory failed!"); - return -1; - } - - blk_dev->max_req_size = BLK_MIN((card->host->max_dma_segs * - card->host->max_seg_size) >> 9, - (card->host->max_blk_count * - card->host->max_blk_size) >> 9); - blk_dev->part.offset = 0; - blk_dev->part.size = 0; - rt_snprintf(sname, sizeof(sname) - 1, "sem_%s%d", card->host->name, 0); - blk_dev->part.lock = rt_sem_create(sname, 1, RT_IPC_FLAG_FIFO); - /* register mmcsd device */ - blk_dev->dev.type = RT_Device_Class_Block; -#ifdef RT_USING_DEVICE_OPS - blk_dev->dev.ops = &mmcsd_blk_ops; -#else - blk_dev->dev.init = rt_mmcsd_init; - blk_dev->dev.open = rt_mmcsd_open; - blk_dev->dev.close = rt_mmcsd_close; - blk_dev->dev.read = rt_mmcsd_read; - blk_dev->dev.write = rt_mmcsd_write; - blk_dev->dev.control = rt_mmcsd_control; -#endif - blk_dev->card = card; - - blk_dev->geometry.bytes_per_sector = 1 << 9; - blk_dev->geometry.block_size = card->card_blksize; - blk_dev->geometry.sector_count = - card->card_capacity * (1024 / 512); - - blk_dev->dev.user_data = blk_dev; - - rt_device_register(&(blk_dev->dev), card->host->name, - RT_DEVICE_FLAG_RDWR); -#ifdef RT_USING_POSIX_DEVIO -#ifdef RT_USING_DFS_V2 - blk_dev->dev.fops = &mmcsd_blk_fops; -#endif -#endif - rt_list_insert_after(&blk_devices, &blk_dev->list); - - for (i = 0; i < RT_GPT_PARTITION_MAX; i++) - { - blk_dev = rt_calloc(1, sizeof(struct mmcsd_blk_device)); - if (!blk_dev) - { - LOG_E("mmcsd:malloc memory failed!"); - break; - } - blk_dev->max_req_size = BLK_MIN((card->host->max_dma_segs * - card->host->max_seg_size) >> 9, - (card->host->max_blk_count * - card->host->max_blk_size) >> 9); - - /* get the first partition */ - status = gpt_get_partition_param(card, &blk_dev->part, i); - if (status == RT_EOK) - { - rt_snprintf(dname, sizeof(dname) - 1, "%s%d", card->host->name, i); - rt_snprintf(sname, sizeof(sname) - 1, "sem_%s%d", card->host->name, i + 1); - blk_dev->part.lock = rt_sem_create(sname, 1, RT_IPC_FLAG_FIFO); - - /* register mmcsd device */ - blk_dev->dev.type = RT_Device_Class_Block; -#ifdef RT_USING_DEVICE_OPS - blk_dev->dev.ops = &mmcsd_blk_ops; -#else - blk_dev->dev.init = rt_mmcsd_init; - blk_dev->dev.open = rt_mmcsd_open; - blk_dev->dev.close = rt_mmcsd_close; - blk_dev->dev.read = rt_mmcsd_read; - blk_dev->dev.write = rt_mmcsd_write; - blk_dev->dev.control = rt_mmcsd_control; -#endif - blk_dev->card = card; - - blk_dev->geometry.bytes_per_sector = 1 << 9; - blk_dev->geometry.block_size = card->card_blksize; - blk_dev->geometry.sector_count = blk_dev->part.size; - - blk_dev->dev.user_data = blk_dev; - - rt_device_register(&(blk_dev->dev), dname, - RT_DEVICE_FLAG_RDWR); -#ifdef RT_USING_POSIX_DEVIO -#ifdef RT_USING_DFS_V2 - blk_dev->dev.fops = &mmcsd_blk_fops; -#endif -#endif - rt_list_insert_after(&blk_devices, &blk_dev->list); - } - else - { - rt_free(blk_dev); - blk_dev = RT_NULL; - break; - } - -#ifdef RT_USING_DFS_MNTTABLE - if (blk_dev) - { - LOG_I("try to mount file system!"); - /* try to mount file system on this block device */ - dfs_mount_device(&(blk_dev->dev)); - } -#endif - } - gpt_free(); - - return err; -} - -rt_int32_t mbr_device_probe(struct rt_mmcsd_card *card) -{ - rt_int32_t err = 0; - rt_uint8_t i, status; - rt_uint8_t *sector; - char dname[10]; - char sname[16]; - struct mmcsd_blk_device *blk_dev = RT_NULL; - - err = mmcsd_set_blksize(card); - if (err) - { - return err; - } - rt_thread_mdelay(1); - /* get the first sector to read partition table */ - sector = (rt_uint8_t *)rt_malloc(SECTOR_SIZE); - if (sector == RT_NULL) - { - LOG_E("allocate partition sector buffer failed!"); - - return -RT_ENOMEM; - } - - status = rt_mmcsd_req_blk(card, 0, sector, 1, 0); - if (status == RT_EOK) - { - blk_dev = rt_calloc(1, sizeof(struct mmcsd_blk_device)); - if (!blk_dev) - { - LOG_E("mmcsd:malloc memory failed!"); - return -1; - } - blk_dev->max_req_size = BLK_MIN((card->host->max_dma_segs * - card->host->max_seg_size) >> 9, - (card->host->max_blk_count * - card->host->max_blk_size) >> 9); - blk_dev->part.offset = 0; - blk_dev->part.size = 0; - rt_snprintf(sname, sizeof(sname) - 1, "sem_%s%d", card->host->name, 0); - blk_dev->part.lock = rt_sem_create(sname, 1, RT_IPC_FLAG_FIFO); - /* register mmcsd device */ - blk_dev->dev.type = RT_Device_Class_Block; -#ifdef RT_USING_DEVICE_OPS - blk_dev->dev.ops = &mmcsd_blk_ops; -#else - blk_dev->dev.init = rt_mmcsd_init; - blk_dev->dev.open = rt_mmcsd_open; - blk_dev->dev.close = rt_mmcsd_close; - blk_dev->dev.read = rt_mmcsd_read; - blk_dev->dev.write = rt_mmcsd_write; - blk_dev->dev.control = rt_mmcsd_control; -#endif - blk_dev->card = card; - - blk_dev->geometry.bytes_per_sector = 1 << 9; - blk_dev->geometry.block_size = card->card_blksize; - blk_dev->geometry.sector_count = - card->card_capacity * (1024 / 512); - - blk_dev->dev.user_data = blk_dev; - - rt_device_register(&(blk_dev->dev), card->host->name, - RT_DEVICE_FLAG_RDWR); - rt_list_insert_after(&blk_devices, &blk_dev->list); - for (i = 0; i < RT_MMCSD_MAX_PARTITION; i++) - { - blk_dev = rt_calloc(1, sizeof(struct mmcsd_blk_device)); - if (!blk_dev) - { - LOG_E("mmcsd:malloc memory failed!"); - break; - } - blk_dev->max_req_size = BLK_MIN((card->host->max_dma_segs * - card->host->max_seg_size) >> 9, - (card->host->max_blk_count * - card->host->max_blk_size) >> 9); - - /* get the first partition */ - status = dfs_filesystem_get_partition(&blk_dev->part, sector, i); - if (status == RT_EOK) - { - rt_snprintf(dname, sizeof(dname) - 1, "%s%d", card->host->name, i); - rt_snprintf(sname, sizeof(sname) - 1, "sem_%s%d", card->host->name, i + 1); - blk_dev->part.lock = rt_sem_create(sname, 1, RT_IPC_FLAG_FIFO); - - /* register mmcsd device */ - blk_dev->dev.type = RT_Device_Class_Block; -#ifdef RT_USING_DEVICE_OPS - blk_dev->dev.ops = &mmcsd_blk_ops; -#else - blk_dev->dev.init = rt_mmcsd_init; - blk_dev->dev.open = rt_mmcsd_open; - blk_dev->dev.close = rt_mmcsd_close; - blk_dev->dev.read = rt_mmcsd_read; - blk_dev->dev.write = rt_mmcsd_write; - blk_dev->dev.control = rt_mmcsd_control; -#endif - blk_dev->card = card; - - blk_dev->geometry.bytes_per_sector = 1 << 9; - blk_dev->geometry.block_size = card->card_blksize; - blk_dev->geometry.sector_count = blk_dev->part.size; - - blk_dev->dev.user_data = blk_dev; - - rt_device_register(&(blk_dev->dev), dname, - RT_DEVICE_FLAG_RDWR); - rt_list_insert_after(&blk_devices, &blk_dev->list); - } - else - { - rt_free(blk_dev); - blk_dev = RT_NULL; - break; - } - -#ifdef RT_USING_DFS_MNTTABLE - if (blk_dev) - { - LOG_I("try to mount file system!"); - /* try to mount file system on this block device */ - dfs_mount_device(&(blk_dev->dev)); - } -#endif - } - } - else - { - LOG_E("read mmcsd first sector failed"); - err = -RT_ERROR; - } - - /* release sector buffer */ - rt_free(sector); - - return err; - -} - -rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) -{ - uint32_t err = 0; - - LOG_D("probe mmcsd block device!"); - if (check_gpt(card) != 0) - { - err = gpt_device_probe(card); - } - else - { - err = mbr_device_probe(card); - } - return err; -} - -void rt_mmcsd_blk_remove(struct rt_mmcsd_card *card) -{ - rt_list_t *l, *n; - struct mmcsd_blk_device *blk_dev; - - for (l = (&blk_devices)->next, n = l->next; l != &blk_devices; l = n, n = n->next) - { - blk_dev = (struct mmcsd_blk_device *)rt_list_entry(l, struct mmcsd_blk_device, list); - if (blk_dev->card == card) - { - /* unmount file system */ - const char *mounted_path = dfs_filesystem_get_mounted_path(&(blk_dev->dev)); - if (mounted_path) - { - dfs_unmount(mounted_path); - LOG_D("unmount file system %s for device %s.\r\n", mounted_path, blk_dev->dev.parent.name); - } - rt_sem_delete(blk_dev->part.lock); - rt_device_unregister(&blk_dev->dev); - rt_list_remove(&blk_dev->list); - rt_free(blk_dev); - } - } -} - -/* - * This function will initialize block device on the mmc/sd. - * - * @deprecated since 2.1.0, this function does not need to be invoked - * in the system initialization. - */ -int rt_mmcsd_blk_init(void) -{ - /* nothing */ - return 0; -} diff --git a/rt-thread/components/drivers/sdio/dev_block.c b/rt-thread/components/drivers/sdio/dev_block.c new file mode 100644 index 0000000..d4f8f62 --- /dev/null +++ b/rt-thread/components/drivers/sdio/dev_block.c @@ -0,0 +1,422 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-07-25 weety first version + * 2023-08-08 GuEe-GUI port to the block + */ + +#include +#include +#include +#include + +#define DBG_TAG "SDIO" +#ifdef RT_SDIO_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* RT_SDIO_DEBUG */ +#include + +#ifndef RT_MMCSD_MAX_PARTITION +#define RT_MMCSD_MAX_PARTITION 16 +#endif + +struct mmcsd_blk_device +{ + struct rt_blk_disk parent; + struct rt_mmcsd_card *card; + + rt_size_t max_req_size; + struct rt_device_blk_geometry geometry; +}; + +#define raw_to_mmcsd_blk(raw) rt_container_of(raw, struct mmcsd_blk_device, parent) + +#ifdef RT_USING_DM +static struct rt_dm_ida sdio_ida = RT_DM_IDA_INIT(SDIO); +#endif + +static int __send_status(struct rt_mmcsd_card *card, rt_uint32_t *status, unsigned retries) +{ + int err; + struct rt_mmcsd_cmd cmd; + + cmd.busy_timeout = 0; + cmd.cmd_code = SEND_STATUS; + cmd.arg = card->rca << 16; + cmd.flags = RESP_R1 | CMD_AC; + err = mmcsd_send_cmd(card->host, &cmd, retries); + if (err) + return err; + + if (status) + *status = cmd.resp[0]; + + return 0; +} + +static int card_busy_detect(struct rt_mmcsd_card *card, unsigned int timeout_ms, + rt_uint32_t *resp_errs) +{ + int timeout = rt_tick_from_millisecond(timeout_ms); + int err = 0; + rt_uint32_t status; + rt_tick_t start; + + start = rt_tick_get(); + do + { + rt_bool_t out = (int)(rt_tick_get() - start) > timeout; + + err = __send_status(card, &status, 5); + if (err) + { + LOG_E("error %d requesting status", err); + return err; + } + + /* Accumulate any response error bits seen */ + if (resp_errs) + *resp_errs |= status; + + if (out) + { + LOG_E("wait card busy timeout"); + return -RT_ETIMEOUT; + } + /* + * Some cards mishandle the status bits, + * so make sure to check both the busy + * indication and the card state. + */ + } + while (!(status & R1_READY_FOR_DATA) || + (R1_CURRENT_STATE(status) == 7)); + + return err; +} + +rt_int32_t mmcsd_num_wr_blocks(struct rt_mmcsd_card *card) +{ + rt_int32_t err; + rt_uint32_t blocks; + + struct rt_mmcsd_req req; + struct rt_mmcsd_cmd cmd; + struct rt_mmcsd_data data; + rt_uint32_t timeout_us; + + rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd)); + + cmd.cmd_code = APP_CMD; + cmd.arg = card->rca << 16; + cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_AC; + + err = mmcsd_send_cmd(card->host, &cmd, 0); + if (err) + return -RT_ERROR; + if (!controller_is_spi(card->host) && !(cmd.resp[0] & R1_APP_CMD)) + return -RT_ERROR; + + rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd)); + + cmd.cmd_code = SD_APP_SEND_NUM_WR_BLKS; + cmd.arg = 0; + cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC; + + rt_memset(&data, 0, sizeof(struct rt_mmcsd_data)); + + data.timeout_ns = card->tacc_ns * 100; + data.timeout_clks = card->tacc_clks * 100; + + timeout_us = data.timeout_ns / 1000; + timeout_us += data.timeout_clks * 1000 / + (card->host->io_cfg.clock / 1000); + + if (timeout_us > 100000) + { + data.timeout_ns = 100000000; + data.timeout_clks = 0; + } + + data.blksize = 4; + data.blks = 1; + data.flags = DATA_DIR_READ; + data.buf = &blocks; + + rt_memset(&req, 0, sizeof(struct rt_mmcsd_req)); + + req.cmd = &cmd; + req.data = &data; + + mmcsd_send_request(card->host, &req); + + if (cmd.err || data.err) + return -RT_ERROR; + + return blocks; +} + +static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, + rt_uint32_t sector, + void *buf, + rt_size_t blks, + rt_uint8_t dir) +{ + struct rt_mmcsd_cmd cmd, stop; + struct rt_mmcsd_data data; + struct rt_mmcsd_req req; + struct rt_mmcsd_host *host = card->host; + rt_uint32_t r_cmd, w_cmd; + + mmcsd_host_lock(host); + rt_memset(&req, 0, sizeof(struct rt_mmcsd_req)); + rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd)); + rt_memset(&stop, 0, sizeof(struct rt_mmcsd_cmd)); + rt_memset(&data, 0, sizeof(struct rt_mmcsd_data)); + req.cmd = &cmd; + req.data = &data; + + cmd.arg = sector; + if (!(card->flags & CARD_FLAG_SDHC)) + { + cmd.arg <<= 9; + } + cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC; + + data.blksize = SECTOR_SIZE; + data.blks = blks; + + if (blks > 1) + { + if (!controller_is_spi(card->host) || !dir) + { + req.stop = &stop; + stop.cmd_code = STOP_TRANSMISSION; + stop.arg = 0; + stop.flags = RESP_SPI_R1B | RESP_R1B | CMD_AC; + } + r_cmd = READ_MULTIPLE_BLOCK; + w_cmd = WRITE_MULTIPLE_BLOCK; + } + else + { + req.stop = RT_NULL; + r_cmd = READ_SINGLE_BLOCK; + w_cmd = WRITE_BLOCK; + } + + if (!controller_is_spi(card->host) && (card->flags & 0x8000)) + { + /* last request is WRITE,need check busy */ + card_busy_detect(card, 10000, RT_NULL); + } + + if (!dir) + { + cmd.cmd_code = r_cmd; + data.flags |= DATA_DIR_READ; + card->flags &= 0x7fff; + } + else + { + cmd.cmd_code = w_cmd; + data.flags |= DATA_DIR_WRITE; + card->flags |= 0x8000; + } + + mmcsd_set_data_timeout(&data, card); + data.buf = buf; + + mmcsd_send_request(host, &req); + + mmcsd_host_unlock(host); + + if (cmd.err || data.err || stop.err) + { + LOG_E("mmcsd request blocks error"); + LOG_E("%d,%d,%d, 0x%08x,0x%08x", + cmd.err, data.err, stop.err, data.flags, sector); + + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_int32_t mmcsd_set_blksize(struct rt_mmcsd_card *card) +{ + struct rt_mmcsd_cmd cmd; + int err; + + /* Block-addressed cards ignore MMC_SET_BLOCKLEN. */ + if (card->flags & CARD_FLAG_SDHC) + return 0; + + mmcsd_host_lock(card->host); + cmd.cmd_code = SET_BLOCKLEN; + cmd.arg = 512; + cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_AC; + err = mmcsd_send_cmd(card->host, &cmd, 5); + mmcsd_host_unlock(card->host); + + if (err) + { + LOG_E("MMCSD: unable to set block size to %d: %d", cmd.arg, err); + + return -RT_ERROR; + } + + return 0; +} + +static rt_ssize_t mmcsd_blk_read(struct rt_blk_disk *disk, rt_off_t sector, + void *buffer, rt_size_t sector_count) +{ + rt_err_t err; + rt_size_t offset = 0; + rt_size_t req_size = 0; + rt_size_t remain_size = sector_count; + void *rd_ptr = (void *)buffer; + struct mmcsd_blk_device *blk_dev = raw_to_mmcsd_blk(disk); + + while (remain_size) + { + req_size = rt_min_t(rt_size_t, remain_size, blk_dev->max_req_size); + + err = rt_mmcsd_req_blk(blk_dev->card, sector + offset, rd_ptr, req_size, 0); + + if (err) + { + return err; + } + + offset += req_size; + rd_ptr = (void *)((rt_uint8_t *)rd_ptr + (req_size << 9)); + remain_size -= req_size; + } + + return sector_count - remain_size; +} + +static rt_ssize_t mmcsd_blk_write(struct rt_blk_disk *disk, rt_off_t sector, + const void *buffer, rt_size_t sector_count) +{ + rt_err_t err; + rt_size_t offset = 0; + rt_size_t req_size = 0; + rt_size_t remain_size = sector_count; + void *wr_ptr = (void *)buffer; + struct mmcsd_blk_device *blk_dev = raw_to_mmcsd_blk(disk); + + while (remain_size) + { + req_size = rt_min_t(rt_size_t, remain_size, blk_dev->max_req_size); + + err = rt_mmcsd_req_blk(blk_dev->card, sector + offset, wr_ptr, req_size, 1); + + if (err) + { + return err; + } + + offset += req_size; + wr_ptr = (void *)((rt_uint8_t *)wr_ptr + (req_size << 9)); + remain_size -= req_size; + } + + return sector_count - remain_size; +} + +static rt_err_t mmcsd_blk_getgeome(struct rt_blk_disk *disk, + struct rt_device_blk_geometry *geometry) +{ + struct mmcsd_blk_device *blk_dev = raw_to_mmcsd_blk(disk); + + rt_memcpy(geometry, &blk_dev->geometry, sizeof(*geometry)); + + return RT_EOK; +} + +static const struct rt_blk_disk_ops mmcsd_blk_ops = +{ + .read = mmcsd_blk_read, + .write = mmcsd_blk_write, + .getgeome = mmcsd_blk_getgeome, +}; + +rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) +{ + rt_err_t err; + struct rt_mmcsd_host *host = card->host; + struct mmcsd_blk_device *blk_dev = rt_calloc(1, sizeof(*blk_dev)); + + if (!blk_dev) + { + return -RT_ENOMEM; + } + card->blk_dev = blk_dev; + +#ifdef RT_USING_DM + blk_dev->parent.ida = &sdio_ida; +#endif + blk_dev->parent.parallel_io = RT_FALSE; + blk_dev->parent.removable = controller_is_removable(host); + blk_dev->parent.ops = &mmcsd_blk_ops; + blk_dev->parent.max_partitions = RT_MMCSD_MAX_PARTITION; + + blk_dev->card = card; + blk_dev->max_req_size = rt_min_t(rt_size_t, + host->max_dma_segs * host->max_seg_size, + host->max_blk_count * host->max_blk_size) >> 9; + blk_dev->geometry.bytes_per_sector = 1 << 9; + blk_dev->geometry.block_size = card->card_blksize; + blk_dev->geometry.sector_count = card->card_capacity * (1024 / 512); + + /* Set blk size before partitions probe, Why? */ + if ((err = mmcsd_set_blksize(card))) + { + goto _fail; + } + rt_thread_mdelay(1); + +#ifdef RT_USING_DM + rt_dm_dev_set_name(&blk_dev->parent.parent, host->name); +#else + rt_strncpy(blk_dev->parent.parent.parent.name, host->name, RT_NAME_MAX); +#endif + + if ((err = rt_hw_blk_disk_register(&blk_dev->parent))) + { + goto _fail; + } + + return RT_EOK; + +_fail: + card->blk_dev = RT_NULL; + free(blk_dev); + + return err; +} + +void rt_mmcsd_blk_remove(struct rt_mmcsd_card *card) +{ + struct mmcsd_blk_device *blk_dev = card->blk_dev; + + if (!blk_dev) + { + return; + } + + if (!rt_hw_blk_disk_unregister(&blk_dev->parent)) + { + card->blk_dev = RT_NULL; + rt_free(blk_dev); + } +} diff --git a/rt-thread/components/drivers/sdio/mmc.c b/rt-thread/components/drivers/sdio/dev_mmc.c similarity index 99% rename from rt-thread/components/drivers/sdio/mmc.c rename to rt-thread/components/drivers/sdio/dev_mmc.c index 3723d9d..6e1cdce 100644 --- a/rt-thread/components/drivers/sdio/mmc.c +++ b/rt-thread/components/drivers/sdio/dev_mmc.c @@ -9,8 +9,8 @@ * 2024-05-25 HPMicro add HS400 support */ -#include -#include +#include +#include #define DBG_TAG "SDIO" #ifdef RT_SDIO_DEBUG diff --git a/rt-thread/components/drivers/sdio/mmcsd_core.c b/rt-thread/components/drivers/sdio/dev_mmcsd_core.c similarity index 99% rename from rt-thread/components/drivers/sdio/mmcsd_core.c rename to rt-thread/components/drivers/sdio/dev_mmcsd_core.c index 7757026..33072c1 100644 --- a/rt-thread/components/drivers/sdio/mmcsd_core.c +++ b/rt-thread/components/drivers/sdio/dev_mmcsd_core.c @@ -9,10 +9,10 @@ */ #include -#include -#include -#include -#include +#include +#include +#include +#include #include #define DBG_TAG "SDIO" diff --git a/rt-thread/components/drivers/sdio/sd.c b/rt-thread/components/drivers/sdio/dev_sd.c similarity index 99% rename from rt-thread/components/drivers/sdio/sd.c rename to rt-thread/components/drivers/sdio/dev_sd.c index 6e826d5..22725db 100644 --- a/rt-thread/components/drivers/sdio/sd.c +++ b/rt-thread/components/drivers/sdio/dev_sd.c @@ -9,8 +9,8 @@ * 2024-05-26 HPMicro add UHS-I support */ -#include -#include +#include +#include #define DBG_TAG "SDIO" #ifdef RT_SDIO_DEBUG @@ -788,7 +788,7 @@ static rt_int32_t mmcsd_sd_init_card(struct rt_mmcsd_host *host, goto err1; /* set bus speed */ - max_data_rate = (unsigned int)-1; + max_data_rate = 0U; if (max_data_rate < card->hs_max_data_rate) { max_data_rate = card->hs_max_data_rate; diff --git a/rt-thread/components/drivers/sdio/sdio.c b/rt-thread/components/drivers/sdio/dev_sdio.c similarity index 99% rename from rt-thread/components/drivers/sdio/sdio.c rename to rt-thread/components/drivers/sdio/dev_sdio.c index 9fa3f53..013753a 100644 --- a/rt-thread/components/drivers/sdio/sdio.c +++ b/rt-thread/components/drivers/sdio/dev_sdio.c @@ -10,9 +10,9 @@ * 2024-07-05 Evlers fix a bug that read members in non-existent functions */ -#include -#include -#include +#include +#include +#include #define DBG_TAG "SDIO" #ifdef RT_SDIO_DEBUG diff --git a/rt-thread/components/drivers/sdio/gpt.c b/rt-thread/components/drivers/sdio/gpt.c deleted file mode 100644 index 53b686e..0000000 --- a/rt-thread/components/drivers/sdio/gpt.c +++ /dev/null @@ -1,563 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-05-05 linzhenxing first version - */ -#include -#include -#include -#include - -#define DBG_TAG "GPT" -#ifdef RT_SDIO_DEBUG -#define DBG_LVL DBG_LOG -#else -#define DBG_LVL DBG_INFO -#endif /* RT_SDIO_DEBUG */ -#include - -#define min(a, b) a < b ? a : b -static int force_gpt = 0; -static gpt_header *_gpt; -static gpt_entry *_ptes; -#define GPT_TYPE 1 -#define MBR_TYPE 0 - -static inline int efi_guidcmp (gpt_guid_t left, gpt_guid_t right) -{ - return rt_memcmp(&left, &right, sizeof (gpt_guid_t)); -} - -static uint32_t last_lba(struct rt_mmcsd_card *card) -{ - RT_ASSERT(card != RT_NULL); - return (card->card_sec_cnt) - 1; -} - -static inline int pmbr_part_valid(gpt_mbr_record *part) -{ - if (part->os_type != EFI_PMBR_OSTYPE_EFI_GPT) - { - goto invalid; - } - - /* set to 0x00000001 (i.e., the LBA of the GPT Partition Header) */ - if ((uint32_t)(part->starting_lba) != GPT_PRIMARY_PARTITION_TABLE_LBA) - { - goto invalid; - } - - return GPT_MBR_PROTECTIVE; -invalid: - return 0; -} - -/* -* -* return ret -* ret = 0, invalid mbr -* ret = 1, protect mbr -* ret = 2, hybrid mbr -*/ -int is_pmbr_valid(legacy_mbr *mbr, uint64_t total_sectors) -{ - uint32_t sz = 0; - int i, part = 0, ret = 0; /* invalid by default */ - - if (!mbr || (uint16_t)(mbr->signature) != MSDOS_MBR_SIGNATURE) - { - goto done; - } - - for (i = 0; i < 4; i++) - { - ret = pmbr_part_valid(&mbr->partition_record[i]); - if (ret == GPT_MBR_PROTECTIVE) - { - part = i; - /* - * Ok, we at least know that there's a protective MBR, - * now check if there are other partition types for - * hybrid MBR. - */ - goto check_hybrid; - } - } - - if (ret != GPT_MBR_PROTECTIVE) - { - goto done; - } - -check_hybrid: - for (i = 0; i < 4; i++) - { - if ((mbr->partition_record[i].os_type != - EFI_PMBR_OSTYPE_EFI_GPT) && - (mbr->partition_record[i].os_type != 0x00)) - { - ret = GPT_MBR_HYBRID; - } - - } - - /* - * Protective MBRs take up the lesser of the whole disk - * or 2 TiB (32bit LBA), ignoring the rest of the disk. - * Some partitioning programs, nonetheless, choose to set - * the size to the maximum 32-bit limitation, disregarding - * the disk size. - * - * Hybrid MBRs do not necessarily comply with this. - * - * Consider a bad value here to be a warning to support dd'ing - * an image from a smaller disk to a larger disk. - */ - if (ret == GPT_MBR_PROTECTIVE) - { - sz = (uint32_t)(mbr->partition_record[part].size_in_lba); - if (sz != (uint32_t) total_sectors - 1 && sz != 0xFFFFFFFF) - { - LOG_I("GPT: mbr size in lba (%u) different than whole disk (%u).", - sz, min(total_sectors - 1, 0xFFFFFFFF)); - } - } - -done: - return ret; - -} - -static gpt_entry *alloc_read_gpt_entries(struct rt_mmcsd_card *card, gpt_header *gpt) -{ - size_t count; - gpt_entry *pte; - - if (!gpt) - { - return RT_NULL; - } - - count = (size_t)(gpt->num_partition_entries) * (gpt->sizeof_partition_entry); - if (!count) - { - return RT_NULL; - } - - pte = rt_malloc(count); - if (!pte) - return RT_NULL; - - if (read_lba(card, (size_t)(gpt->partition_entry_lba),(uint8_t *)pte, count/512) != RT_EOK) - { - rt_free(pte); - return RT_NULL; - } - return pte; - -} - -static gpt_header *alloc_read_gpt_header(struct rt_mmcsd_card *card, size_t lba) -{ - gpt_header *gpt; - void *buf; - - buf = rt_malloc(512); - if (!buf) - { - return RT_NULL; - } - - if (read_lba(card, lba, (uint8_t *)buf, 1) != RT_EOK) - { - rt_free(buf); - return RT_NULL; - } - gpt = (gpt_header *)buf; - - return gpt; -} - -static int is_gpt_valid(struct rt_mmcsd_card *card, size_t lba, gpt_header **gpt, gpt_entry **ptes) -{ - size_t lastlba; - - if (!ptes || !gpt) - { - return 0; - } - - *gpt = alloc_read_gpt_header(card, lba); - if (!(*gpt)) - { - return 0; - } - - /* Check the GUID Partition Table signature */ - if ((uint64_t)((*gpt)->signature) != GPT_HEADER_SIGNATURE) - { - LOG_E("GUID Partition Table Header signature is wrong:" - "%ld != %ld",(uint64_t)((*gpt)->signature),(uint64_t)GPT_HEADER_SIGNATURE); - goto fail; - } - - /* Check the GUID Partition Table header size is too small */ - if ((uint32_t)((*gpt)->header_size) < sizeof(gpt_header)) - { - LOG_E("GUID Partition Table Header size is too small: %u < %zu", - (uint32_t)((*gpt)->header_size),sizeof(gpt_header)); - goto fail; - } - - /* Check that the start_lba entry points to the LBA that contains - * the GUID Partition Table */ - if ((uint64_t)((*gpt)->start_lba) != lba) - { - LOG_E("GPT start_lba incorrect: %ld != %ld", - (uint64_t)((*gpt)->start_lba), - (uint64_t)lba); - goto fail; - } - - /* Check the first_usable_lba and last_usable_lba are - * within the disk. - */ - lastlba = last_lba(card); - if ((uint64_t)((*gpt)->first_usable_lba) > lastlba) - { - LOG_E("GPT: first_usable_lba incorrect: %ld > %ld", - ((uint64_t)((*gpt)->first_usable_lba)), - (size_t)lastlba); - goto fail; - } - - if ((uint64_t)((*gpt)->last_usable_lba) > lastlba) - { - LOG_E("GPT: last_usable_lba incorrect: %ld > %ld", - (uint64_t)((*gpt)->last_usable_lba), - (size_t)lastlba); - goto fail; - } - - if ((uint64_t)((*gpt)->last_usable_lba) < (uint64_t)((*gpt)->first_usable_lba)) - { - LOG_E("GPT: last_usable_lba incorrect: %ld > %ld", - (uint64_t)((*gpt)->last_usable_lba), - (uint64_t)((*gpt)->first_usable_lba)); - goto fail; - } - /* Check that sizeof_partition_entry has the correct value */ - if ((uint32_t)((*gpt)->sizeof_partition_entry) != sizeof(gpt_entry)) { - LOG_E("GUID Partition Entry Size check failed."); - goto fail; - } - - *ptes = alloc_read_gpt_entries(card, *gpt); - if (!(*ptes)) - { - goto fail; - } - - /* We're done, all's well */ - return 1; - - fail: - rt_free(*gpt); - *gpt = RT_NULL; - return 0; -} - -/** - * is_pte_valid() - tests one PTE for validity - * pte:pte to check - * lastlba: last lba of the disk - * - * Description: returns 1 if valid, 0 on error. - */ -static inline int is_pte_valid(const gpt_entry *pte, const size_t lastlba) -{ - if ((!efi_guidcmp(pte->partition_type_guid, NULL_GUID)) || - (uint64_t)(pte->starting_lba) > lastlba || - (uint64_t)(pte->ending_lba) > lastlba) - { - return 0; - } - - return 1; -} - -/** - * compare_gpts() - Search disk for valid GPT headers and PTEs - * pgpt: primary GPT header - * agpt: alternate GPT header - * lastlba: last LBA number - * - * Description: Returns nothing. Sanity checks pgpt and agpt fields - * and prints warnings on discrepancies. - * - */ -static void compare_gpts(gpt_header *pgpt, gpt_header *agpt, size_t lastlba) -{ - int error_found = 0; - if (!pgpt || !agpt) - { - return; - } - - if ((uint64_t)(pgpt->start_lba) != (uint64_t)(agpt->alternate_lba)) - { - LOG_I("GPT:Primary header LBA != Alt. header alternate_lba"); - LOG_I("GPT:%lld != %lld", - (uint64_t)(pgpt->start_lba), - (uint64_t)(agpt->alternate_lba)); - error_found++; - } - - if ((uint64_t)(pgpt->alternate_lba) != (uint64_t)(agpt->start_lba)) - { - LOG_I("GPT:Primary header alternate_lba != Alt. header start_lba"); - LOG_I("GPT:%lld != %lld", - (uint64_t)(pgpt->alternate_lba), - (uint64_t)(agpt->start_lba)); - error_found++; - } - - if ((uint64_t)(pgpt->first_usable_lba) != (uint64_t)(agpt->first_usable_lba)) - { - LOG_I("GPT:first_usable_lbas don't match."); - LOG_I("GPT:%lld != %lld", - (uint64_t)(pgpt->first_usable_lba), - (uint64_t)(agpt->first_usable_lba)); - error_found++; - } - - if ((uint64_t)(pgpt->last_usable_lba) != (uint64_t)(agpt->last_usable_lba)) - { - LOG_I("GPT:last_usable_lbas don't match."); - LOG_I("GPT:%lld != %lld", - (uint64_t)(pgpt->last_usable_lba), - (uint64_t)(agpt->last_usable_lba)); - error_found++; - } - - if (efi_guidcmp(pgpt->disk_guid, agpt->disk_guid)) - { - LOG_I("GPT:disk_guids don't match."); - error_found++; - } - - if ((pgpt->num_partition_entries) != (agpt->num_partition_entries)) - { - LOG_I("GPT:num_partition_entries don't match: " - "0x%x != 0x%x", - (pgpt->num_partition_entries), - (agpt->num_partition_entries)); - error_found++; - } - - if ((pgpt->sizeof_partition_entry) != (agpt->sizeof_partition_entry)) - { - LOG_I("GPT:sizeof_partition_entry values don't match: " - "0x%x != 0x%x", - (pgpt->sizeof_partition_entry), - (agpt->sizeof_partition_entry)); - error_found++; - } - - if ((pgpt->partition_entry_array_crc32) != (agpt->partition_entry_array_crc32)) - { - LOG_I("GPT:partition_entry_array_crc32 values don't match: " - "0x%x != 0x%x", - (pgpt->partition_entry_array_crc32), - (agpt->partition_entry_array_crc32)); - error_found++; - } - - if ((pgpt->alternate_lba) != lastlba) - { - LOG_I("GPT:Primary header thinks Alt. header is not at the end of the disk."); - LOG_I("GPT:%lld != %lld", - (uint64_t)(pgpt->alternate_lba), - (size_t)lastlba); - error_found++; - } - - if ((agpt->start_lba) != lastlba) - { - LOG_I("GPT:Alternate GPT header not at the end of the disk."); - LOG_I("GPT:%lld != %lld", - (uint64_t)(agpt->start_lba), - (size_t)lastlba); - error_found++; - } - - if (error_found) - { - LOG_I("GPT: Use GNU Parted to correct GPT errors."); - } - return; -} - -/** - * find_valid_gpt() - Search disk for valid GPT headers and PTEs - * state: disk parsed partitions - * gpt: GPT header ptr, filled on return. - * ptes: PTEs ptr, filled on return. - * - * Description: Returns 1 if valid, 0 on error. - * If valid, returns pointers to newly allocated GPT header and PTEs. - * Validity depends on PMBR being valid (or being overridden by the - * 'gpt' kernel command line option) and finding either the Primary - * GPT header and PTEs valid, or the Alternate GPT header and PTEs - * valid. If the Primary GPT header is not valid, the Alternate GPT header - * is not checked unless the 'gpt' kernel command line option is passed. - * This protects against devices which misreport their size, and forces - * the user to decide to use the Alternate GPT. - */ -static int find_valid_gpt(struct rt_mmcsd_card *card, gpt_header **gpt, - gpt_entry **ptes) -{ - int good_pgpt = 0, good_agpt = 0, good_pmbr = 0; - gpt_header *pgpt = RT_NULL, *agpt = RT_NULL; - gpt_entry *pptes = RT_NULL, *aptes = RT_NULL; - legacy_mbr *legacymbr; - size_t total_sectors = last_lba(card) + 1; - size_t lastlba; - int status = 0; - - if (!ptes) - { - return 0; - } - - lastlba = last_lba(card); - if (!force_gpt) - { - /* This will be added to the EFI Spec. per Intel after v1.02. */ - legacymbr = rt_malloc(512); - if (!legacymbr) - { - goto fail; - } - - status = read_lba(card, 0, (uint8_t *)legacymbr, 1); - if (status) - { - LOG_I("status:%d", status); - goto fail; - } - - good_pmbr = is_pmbr_valid(legacymbr, total_sectors); - rt_free(legacymbr); - - if (!good_pmbr) - { - goto fail; - } - - rt_kprintf("Device has a %s MBR\n", - good_pmbr == GPT_MBR_PROTECTIVE ? - "protective" : "hybrid"); - } - - good_pgpt = is_gpt_valid(card, GPT_PRIMARY_PARTITION_TABLE_LBA, - &pgpt, &pptes); - if (good_pgpt) - { - good_agpt = is_gpt_valid(card, (pgpt->alternate_lba), &agpt, &aptes); - if (!good_agpt && force_gpt) - { - good_agpt = is_gpt_valid(card, lastlba, &agpt, &aptes); - } - - /* The obviously unsuccessful case */ - if (!good_pgpt && !good_agpt) - { - goto fail; - } - - compare_gpts(pgpt, agpt, lastlba); - - /* The good cases */ - if (good_pgpt) - { - *gpt = pgpt; - *ptes = pptes; - rt_free(agpt); - rt_free(aptes); - if (!good_agpt) - { - LOG_D("Alternate GPT is invalid, using primary GPT."); - } - return 1; - } - else if (good_agpt) - { - *gpt = agpt; - *ptes = aptes; - rt_free(pgpt); - rt_free(pptes); - LOG_D("Primary GPT is invalid, using alternate GPT."); - return 1; - } - } - - fail: - rt_free(pgpt); - rt_free(agpt); - rt_free(pptes); - rt_free(aptes); - *gpt = RT_NULL; - *ptes = RT_NULL; - return 0; -} - -int check_gpt(struct rt_mmcsd_card *card) -{ - if (!find_valid_gpt(card, &_gpt, &_ptes) || !_gpt || !_ptes) - { - rt_free(_gpt); - rt_free(_ptes); - return MBR_TYPE; - } - return GPT_TYPE; -} - -int gpt_get_partition_param(struct rt_mmcsd_card *card, struct dfs_partition *part, uint32_t pindex) -{ - if (!is_pte_valid(&_ptes[pindex], last_lba(card))) - { - return -1; - } - - part->offset = (off_t)(_ptes[pindex].starting_lba); - part->size = (_ptes[pindex].ending_lba) - (_ptes[pindex].starting_lba) + 1ULL; - - rt_kprintf("found part[%d], begin(sector): %d, end(sector):%d size: ", - pindex, _ptes[pindex].starting_lba, _ptes[pindex].ending_lba); - - if ((part->size >> 11) == 0) - { - rt_kprintf("%d%s", part->size >> 1, "KB\n"); /* KB */ - } - else - { - unsigned int part_size; - part_size = part->size >> 11; /* MB */ - if ((part_size >> 10) == 0) - rt_kprintf("%d.%d%s", part_size, (part->size >> 1) & 0x3FF, "MB\n"); - else - rt_kprintf("%d.%d%s", part_size >> 10, part_size & 0x3FF, "GB\n"); - } - return 0; -} - -void gpt_free(void) -{ - rt_free(_ptes); - rt_free(_gpt); -} diff --git a/rt-thread/components/drivers/sdio/sdhci/fit-mmc.c b/rt-thread/components/drivers/sdio/sdhci/fit-mmc.c new file mode 100644 index 0000000..a3fe063 --- /dev/null +++ b/rt-thread/components/drivers/sdio/sdhci/fit-mmc.c @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-08-16 zhujiale first version + */ +#include +#include "sdhci.h" +#include +#include +#include + + +static void rt_plat_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct rt_mmc_host *mmc = (struct rt_mmc_host *)host; + rt_uint32_t flags = req->cmd->flags; + + switch (flags & RESP_MASK) + { + case RESP_NONE: + flags |= MMC_RSP_NONE; + break; + case RESP_R1: + flags |= MMC_RSP_R1; + break; + case RESP_R1B: + flags |= MMC_RSP_R1B; + break; + case RESP_R2: + flags |= MMC_RSP_R2; + break; + case RESP_R3: + flags |= MMC_RSP_R3; + break; + case RESP_R4: + flags |= MMC_RSP_R4; + break; + case RESP_R5: + flags |= MMC_RSP_R5; + break; + case RESP_R6: + flags |= MMC_RSP_R6; + break; + case RESP_R7: + flags |= MMC_RSP_R7; + break; + } + if (req->data) + { + if ((rt_uint64_t)rt_kmem_v2p(req->data->buf) > 0xffffffff) + { + void *dma_buffer = rt_malloc(req->data->blks * req->data->blksize); + void *req_buf = NULL; + + if (req->data->flags & DATA_DIR_WRITE) + { + rt_memcpy(dma_buffer, req->data->buf, req->data->blks * req->data->blksize); + req_buf = req->data->buf; + req->data->buf = dma_buffer; + } + else if (req->data->flags & DATA_DIR_READ) + { + req_buf = req->data->buf; + req->data->buf = dma_buffer; + } + req->cmd->flags |= flags; + mmc->ops->request(mmc, req); + + rt_sem_take(&host->sem_ack, RT_WAITING_FOREVER); + + if (req->data->flags & DATA_DIR_READ) + { + rt_memcpy(req_buf, dma_buffer, req->data->blksize * req->data->blks); + req->data->buf = req_buf; + }else{ + req->data->buf = req_buf; + } + + rt_free(dma_buffer); + rt_sem_release(&host->sem_ack); + } + else + { + req->cmd->flags |= flags; + mmc->ops->request(mmc, req); + } + } + else + { + req->cmd->flags |= flags; + mmc->ops->request(mmc, req); + } +} + +static void rt_plat_set_ioconfig(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *iocfg) +{ + struct rt_mmc_host *mmc = (struct rt_mmc_host *)host; + + LOG_D("clock:%d,width:%d,power:%d,vdd:%d,timing:%d\n", + iocfg->clock, iocfg->bus_width, + iocfg->power_mode, iocfg->vdd, iocfg->timing); + + mmc->ops->set_ios(mmc, iocfg); +} + +static rt_int32_t rt_plat_get_card_status(struct rt_mmcsd_host *host) +{ + struct rt_mmc_host *mmc = (struct rt_mmc_host *)host; + + return mmc->ops->get_cd(mmc); +} + +static rt_int32_t rt_plat_execute_tuning(struct rt_mmcsd_host *host, rt_int32_t opcode) +{ + struct rt_mmc_host *mmc = (struct rt_mmc_host *)host; + + return mmc->ops->execute_tuning(mmc, opcode); +} + +static void rt_plat_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en) +{ + struct rt_mmc_host *mmc = (struct rt_mmc_host *)host; + + return mmc->ops->enable_sdio_irq(mmc, en); +} + + +static const struct rt_mmcsd_host_ops rt_mmcsd_ops = { + .request = rt_plat_request, + .set_iocfg = rt_plat_set_ioconfig, + .get_card_status = rt_plat_get_card_status, + .enable_sdio_irq = rt_plat_enable_sdio_irq, + .execute_tuning = rt_plat_execute_tuning, +}; + + +void rt_mmc_request_done(struct rt_mmc_host *host, struct rt_mmcsd_req *mrq) +{ + mmcsd_req_complete(&host->rthost); +} + +/*add host in rtt while sdhci complete*/ +int rt_mmc_add_host(struct rt_mmc_host *mmc) +{ + mmc->rthost.ops = &rt_mmcsd_ops; + mmc->rthost.flags = mmc->caps; + mmc->rthost.freq_max = mmc->f_max; + mmc->rthost.freq_min = 400000; + mmc->rthost.max_dma_segs = mmc->max_segs; + mmc->rthost.max_seg_size = mmc->max_seg_size; + mmc->rthost.max_blk_size = mmc->max_blk_size; + mmc->rthost.max_blk_count = mmc->max_blk_count; + mmc->rthost.valid_ocr = VDD_165_195|VDD_20_21|VDD_21_22|VDD_22_23|VDD_24_25|VDD_25_26|VDD_26_27|VDD_27_28|VDD_28_29|VDD_29_30|VDD_30_31|VDD_32_33|VDD_33_34|VDD_34_35|VDD_35_36; + + + mmcsd_change(&mmc->rthost); + return 0; +} + +struct rt_mmc_host *rt_mmc_alloc_host(int extra, struct rt_device *dev) +{ + struct rt_mmc_host *mmc; + + mmc = rt_malloc(sizeof(*mmc) + extra); + if (mmc) + { + rt_memset(mmc, 0, sizeof(*mmc) + extra); + mmc->parent = dev; + mmcsd_host_init(&mmc->rthost); + } + + return mmc; +} + +void rt_mmc_remove_host(struct rt_mmc_host *host) +{ + rt_free(host); +} + +int rt_mmc_abort_tuning(struct rt_mmc_host *host, rt_uint32_t opcode) +{ + return 0; +} + + +int rt_mmc_gpio_get_cd(struct rt_mmc_host *host) +{ + return -ENOSYS; +} + +void rt_mmc_detect_change(struct rt_mmc_host *host, unsigned long delay) +{ +} + + +int rt_mmc_regulator_set_vqmmc(struct rt_mmc_host *mmc, struct rt_mmcsd_io_cfg *ios) +{ + return 0; +} + +rt_bool_t rt_mmc_can_gpio_ro(struct rt_mmc_host *host) +{ + return RT_FALSE; +} + +int rt_mmc_gpio_get_ro(struct rt_mmc_host *host) +{ + return 0; +} + +int rt_mmc_send_abort_tuning(struct rt_mmc_host *host, rt_uint32_t opcode) +{ + return 0; +} +int rt_mmc_of_parse(struct rt_mmc_host *host) +{ + struct rt_device *dev = host->parent; + rt_uint32_t bus_width; + + if (!dev || !dev->ofw_node) + return 0; + + /* "bus-width" is translated to MMC_CAP_*_BIT_DATA flags */ + if (rt_dm_dev_prop_read_u32(dev, "bus-width", &bus_width) < 0) + { + bus_width = 1; + } + + switch (bus_width) + { + case 8: + host->caps |= MMC_CAP_8_BIT_DATA; + break; /* Hosts capable of 8-bit can also do 4 bits */ + case 4: + host->caps |= MMC_CAP_4_BIT_DATA; + break; + case 1: + break; + default: + return -EINVAL; + } + + /* f_max is obtained from the optional "max-frequency" property */ + rt_dm_dev_prop_read_u32(dev, "max-frequency", &host->f_max); + + if (rt_dm_dev_prop_read_bool(dev, "cap-mmc-highspeed")) + { + host->caps |= MMC_CAP_MMC_HIGHSPEED; + } + + if (rt_dm_dev_prop_read_bool(dev, "mmc-hs200-1_8v")) + { + host->caps |= MMC_CAP2_HS200_1_8V_SDR; + } + + if (rt_dm_dev_prop_read_bool(dev, "non-removable")) + { + host->caps |= MMC_CAP_NONREMOVABLE; + } + + if (rt_dm_dev_prop_read_bool(dev, "no-sdio")) + { + host->caps2 |= MMC_CAP2_NO_SDIO; + } + + if (rt_dm_dev_prop_read_bool(dev, "no-sd")) + { + host->caps2 |= MMC_CAP2_NO_SD; + } + + if (rt_dm_dev_prop_read_bool(dev, "mmc-ddr-3_3v")) + { + host->caps |= MMC_CAP_3_3V_DDR; + } + + if (rt_dm_dev_prop_read_bool(dev, "mmc-ddr-1_8v")) + { + host->caps |= MMC_CAP_1_8V_DDR; + } + + if (rt_dm_dev_prop_read_bool(dev, "mmc-ddr-1_2v")) + { + host->caps |= MMC_CAP_1_2V_DDR; + } + + return 0; +} + + +void rt_mmc_free_host(struct rt_mmc_host *host) +{ +} + +rt_bool_t rt_mmc_can_gpio_cd(struct rt_mmc_host *host) +{ + return RT_FALSE; +} + +int mmc_regulator_get_supply(struct rt_mmc_host *mmc) +{ + mmc->supply.vmmc = -RT_NULL; + mmc->supply.vqmmc = -RT_NULL; + + return 0; +} +int regulator_get_current_limit(struct regulator *regulator) +{ + return 0; +} + +int regulator_is_supported_voltage(struct regulator *regulator, + + int min_uV, int max_uV) +{ + return 0; +} diff --git a/rt-thread/components/drivers/sdio/sdhci/include/sdhci-platform.h b/rt-thread/components/drivers/sdio/sdhci/include/sdhci-platform.h new file mode 100644 index 0000000..f8d9644 --- /dev/null +++ b/rt-thread/components/drivers/sdio/sdhci/include/sdhci-platform.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-08-16 zhujiale first version + */ + +#ifndef _DRIVERS_MMC_RT_SDHCI_PLTFM_H +#define _DRIVERS_MMC_RT_SDHCI_PLTFM_H +#include +#include +#include +#include +#include +#include "sdhci.h" + +struct rt_sdhci_pltfm_data +{ + const struct rt_sdhci_ops *ops; + unsigned int quirks; + unsigned int quirks2; +}; + +struct rt_sdhci_pltfm_host +{ + struct rt_clk *clk; + unsigned int clock; + rt_uint64_t xfer_mode_shadow; + + unsigned long private[]; +}; +void rt_sdhci_get_property(struct rt_platform_device *pdev); + +static inline void sdhci_get_of_property(struct rt_platform_device *pdev) +{ + return rt_sdhci_get_property(pdev); +} +extern struct rt_sdhci_host *rt_sdhci_pltfm_init(struct rt_platform_device *pdev, + const struct rt_sdhci_pltfm_data *pdata, + size_t priv_size); +extern void rt_sdhci_pltfm_free(struct rt_platform_device *pdev); + +extern int rt_sdhci_pltfm_init_and_add_host(struct rt_platform_device *pdev, + const struct rt_sdhci_pltfm_data *pdata, + size_t priv_size); +extern void rt_sdhci_pltfm_remove(struct rt_platform_device *pdev); + +extern unsigned int rt_sdhci_pltfm_clk_get_max_clock(struct rt_sdhci_host *host); + +static inline void *sdhci_pltfm_priv(struct rt_sdhci_pltfm_host *host) +{ + return host->private; +} + +static inline int sdhci_pltfm_suspend(struct rt_device *dev) +{ + return 0; +} +static inline int sdhci_pltfm_resume(struct rt_device *dev) +{ + return 0; +} +#endif diff --git a/rt-thread/components/drivers/sdio/sdhci/include/sdhci.h b/rt-thread/components/drivers/sdio/sdhci/include/sdhci.h new file mode 100644 index 0000000..1ad3db1 --- /dev/null +++ b/rt-thread/components/drivers/sdio/sdhci/include/sdhci.h @@ -0,0 +1,677 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-08-16 zhujiale first version + */ +#ifndef __RT_SDHCI_HW_H +#define __RT_SDHCI_HW_H + +#include "sdhci_host.h" +#include "sdhci_misc.h" +#include "sdhci-platform.h" +#include +#include +#include +#include + +#define lower_32_bits(n) ((rt_uint32_t)((n) & 0xffffffff)) +#define upper_32_bits(n) ((rt_uint32_t)(((n) >> 16) >> 16)) + +#define MAX_TUNING_LOOP 40 +/* + * Controller registers + */ +#define RT_SDHCI_DMA_ADDRESS 0x00 +#define RT_SDHCI_ARGUMENT2 RT_SDHCI_DMA_ADDRESS +#define RT_SDHCI_32BIT_BLK_CNT RT_SDHCI_DMA_ADDRESS + +#define RT_SDHCI_BLOCK_SIZE 0x04 +#define RT_SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) + +#define RT_SDHCI_BLOCK_COUNT 0x06 + +#define RT_SDHCI_ARGUMENT 0x08 + +#define RT_SDHCI_TRANSFER_MODE 0x0C +#define RT_SDHCI_TRNS_DMA 0x01 +#define RT_SDHCI_TRNS_BLK_CNT_EN 0x02 +#define RT_SDHCI_TRNS_AUTO_CMD12 0x04 +#define RT_SDHCI_TRNS_AUTO_CMD23 0x08 +#define RT_SDHCI_TRNS_AUTO_SEL 0x0C +#define RT_SDHCI_TRNS_READ 0x10 +#define RT_SDHCI_TRNS_MULTI 0x20 + +#define RT_SDHCI_COMMAND 0x0E +#define RT_SDHCI_CMD_RESP_MASK 0x03 +#define RT_SDHCI_CMD_CRC 0x08 +#define RT_SDHCI_CMD_INDEX 0x10 +#define RT_SDHCI_CMD_DATA 0x20 +#define RT_SDHCI_CMD_ABORTCMD 0xC0 + +#define RT_SDHCI_CMD_RESP_NONE 0x00 +#define RT_SDHCI_CMD_RESP_LONG 0x01 +#define RT_SDHCI_CMD_RESP_SHORT 0x02 +#define RT_SDHCI_CMD_RESP_SHORT_BUSY 0x03 + +#define RT_SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) +#define RT_SDHCI_GET_CMD(c) ((c >> 8) & 0x3f) + +#define RT_SDHCI_RESPONSE 0x10 + +#define RT_SDHCI_BUFFER 0x20 + +#define RT_SDHCI_PRESENT_STATE 0x24 +#define RT_SDHCI_CMD_INHIBIT 0x00000001 +#define RT_SDHCI_DATA_INHIBIT 0x00000002 +#define RT_SDHCI_DOING_WRITE 0x00000100 +#define RT_SDHCI_DOING_READ 0x00000200 +#define RT_SDHCI_SPACE_AVAILABLE 0x00000400 +#define RT_SDHCI_DATA_AVAILABLE 0x00000800 +#define RT_SDHCI_CARD_PRESENT 0x00010000 +#define RT_SDHCI_CARD_PRES_SHIFT 16 +#define RT_SDHCI_CD_STABLE 0x00020000 +#define RT_SDHCI_CD_LVL 0x00040000 +#define RT_SDHCI_CD_LVL_SHIFT 18 +#define RT_SDHCI_WRITE_PROTECT 0x00080000 +#define RT_SDHCI_DATA_LVL_MASK 0x00F00000 +#define RT_SDHCI_DATA_LVL_SHIFT 20 +#define RT_SDHCI_DATA_0_LVL_MASK 0x00100000 +#define RT_SDHCI_CMD_LVL 0x01000000 + +#define RT_SDHCI_HOST_CONTROL 0x28 +#define RT_SDHCI_CTRL_LED 0x01 +#define RT_SDHCI_CTRL_4BITBUS 0x02 +#define RT_SDHCI_CTRL_HISPD 0x04 +#define RT_SDHCI_CTRL_DMA_MASK 0x18 +#define RT_SDHCI_CTRL_SDMA 0x00 +#define RT_SDHCI_CTRL_ADMA1 0x08 +#define RT_SDHCI_CTRL_ADMA32 0x10 +#define RT_SDHCI_CTRL_ADMA64 0x18 +#define RT_SDHCI_CTRL_ADMA3 0x18 +#define RT_SDHCI_CTRL_8BITBUS 0x20 +#define RT_SDHCI_CTRL_CDTEST_INS 0x40 +#define RT_SDHCI_CTRL_CDTEST_EN 0x80 + +#define RT_SDHCI_POWER_CONTROL 0x29 +#define RT_SDHCI_POWER_ON 0x01 +#define RT_SDHCI_POWER_180 0x0A +#define RT_SDHCI_POWER_300 0x0C +#define RT_SDHCI_POWER_330 0x0E +/* + * VDD2 - UHS2 or PCIe/NVMe + * VDD2 power on/off and voltage select + */ +#define RT_SDHCI_VDD2_POWER_ON 0x10 +#define RT_SDHCI_VDD2_POWER_120 0x80 +#define RT_SDHCI_VDD2_POWER_180 0xA0 + +#define RT_SDHCI_BLOCK_GAP_CONTROL 0x2A + +#define RT_SDHCI_WAKE_UP_CONTROL 0x2B +#define RT_SDHCI_WAKE_ON_INT 0x01 +#define RT_SDHCI_WAKE_ON_INSERT 0x02 +#define RT_SDHCI_WAKE_ON_REMOVE 0x04 + +#define RT_SDHCI_CLOCK_CONTROL 0x2C +#define RT_SDHCI_DIVIDER_SHIFT 8 +#define RT_SDHCI_DIVIDER_HI_SHIFT 6 +#define RT_SDHCI_DIV_MASK 0xFF +#define RT_SDHCI_DIV_MASK_LEN 8 +#define RT_SDHCI_DIV_HI_MASK 0x300 +#define RT_SDHCI_PROG_CLOCK_MODE 0x0020 +#define RT_SDHCI_CLOCK_CARD_EN 0x0004 +#define RT_SDHCI_CLOCK_PLL_EN 0x0008 +#define RT_SDHCI_CLOCK_INT_STABLE 0x0002 +#define RT_SDHCI_CLOCK_INT_EN 0x0001 + +#define RT_SDHCI_TIMEOUT_CONTROL 0x2E + +#define RT_SDHCI_SOFTWARE_RESET 0x2F +#define RT_SDHCI_RESET_ALL 0x01 +#define RT_SDHCI_RESET_CMD 0x02 +#define RT_SDHCI_RESET_DATA 0x04 + +#define RT_SDHCI_INT_STATUS 0x30 +#define RT_SDHCI_INT_ENABLE 0x34 +#define RT_SDHCI_SIGNAL_ENABLE 0x38 +#define RT_SDHCI_INT_RESPONSE 0x00000001 +#define RT_SDHCI_INT_DATA_END 0x00000002 +#define RT_SDHCI_INT_BLK_GAP 0x00000004 +#define RT_SDHCI_INT_DMA_END 0x00000008 +#define RT_SDHCI_INT_SPACE_AVAIL 0x00000010 +#define RT_SDHCI_INT_DATA_AVAIL 0x00000020 +#define RT_SDHCI_INT_CARD_INSERT 0x00000040 +#define RT_SDHCI_INT_CARD_REMOVE 0x00000080 +#define RT_SDHCI_INT_CARD_INT 0x00000100 +#define RT_SDHCI_INT_RETUNE 0x00001000 +#define RT_SDHCI_INT_CQE 0x00004000 +#define RT_SDHCI_INT_ERROR 0x00008000 +#define RT_SDHCI_INT_TIMEOUT 0x00010000 +#define RT_SDHCI_INT_CRC 0x00020000 +#define RT_SDHCI_INT_END_BIT 0x00040000 +#define RT_SDHCI_INT_INDEX 0x00080000 +#define RT_SDHCI_INT_DATA_TIMEOUT 0x00100000 +#define RT_SDHCI_INT_DATA_CRC 0x00200000 +#define RT_SDHCI_INT_DATA_END_BIT 0x00400000 +#define RT_SDHCI_INT_BUS_POWER 0x00800000 +#define RT_SDHCI_INT_AUTO_CMD_ERR 0x01000000 +#define RT_SDHCI_INT_ADMA_ERROR 0x02000000 + +#define RT_SDHCI_INT_NORMAL_MASK 0x00007FFF +#define RT_SDHCI_INT_ERROR_MASK 0xFFFF8000 + +#define RT_SDHCI_INT_CMD_MASK (RT_SDHCI_INT_RESPONSE | RT_SDHCI_INT_TIMEOUT | RT_SDHCI_INT_CRC | RT_SDHCI_INT_END_BIT | RT_SDHCI_INT_INDEX | RT_SDHCI_INT_AUTO_CMD_ERR) +#define RT_SDHCI_INT_DATA_MASK (RT_SDHCI_INT_DATA_END | RT_SDHCI_INT_DMA_END | RT_SDHCI_INT_DATA_AVAIL | RT_SDHCI_INT_SPACE_AVAIL | RT_SDHCI_INT_DATA_TIMEOUT | RT_SDHCI_INT_DATA_CRC | RT_SDHCI_INT_DATA_END_BIT | RT_SDHCI_INT_ADMA_ERROR | RT_SDHCI_INT_BLK_GAP) +#define RT_SDHCI_INT_ALL_MASK ((unsigned int)-1) + +#define RT_SDHCI_CQE_INT_ERR_MASK ( \ + RT_SDHCI_INT_ADMA_ERROR | RT_SDHCI_INT_BUS_POWER | RT_SDHCI_INT_DATA_END_BIT | RT_SDHCI_INT_DATA_CRC | RT_SDHCI_INT_DATA_TIMEOUT | RT_SDHCI_INT_INDEX | RT_SDHCI_INT_END_BIT | RT_SDHCI_INT_CRC | RT_SDHCI_INT_TIMEOUT) + +#define RT_SDHCI_CQE_INT_MASK (RT_SDHCI_CQE_INT_ERR_MASK | RT_SDHCI_INT_CQE) + +#define RT_SDHCI_AUTO_CMD_STATUS 0x3C +#define RT_SDHCI_AUTO_CMD_TIMEOUT 0x00000002 +#define RT_SDHCI_AUTO_CMD_CRC 0x00000004 +#define RT_SDHCI_AUTO_CMD_END_BIT 0x00000008 +#define RT_SDHCI_AUTO_CMD_INDEX 0x00000010 + +#define RT_SDHCI_HOST_CONTROL2 0x3E +#define RT_SDHCI_CTRL_UHS_MASK 0x0007 +#define RT_SDHCI_CTRL_UHS_SDR12 0x0000 +#define RT_SDHCI_CTRL_UHS_SDR25 0x0001 +#define RT_SDHCI_CTRL_UHS_SDR50 0x0002 +#define RT_SDHCI_CTRL_UHS_SDR104 0x0003 +#define RT_SDHCI_CTRL_UHS_DDR50 0x0004 +#define RT_SDHCI_CTRL_HS400 0x0005 /* Non-standard */ +#define RT_SDHCI_CTRL_VDD_180 0x0008 +#define RT_SDHCI_CTRL_DRV_TYPE_MASK 0x0030 +#define RT_SDHCI_CTRL_DRV_TYPE_B 0x0000 +#define RT_SDHCI_CTRL_DRV_TYPE_A 0x0010 +#define RT_SDHCI_CTRL_DRV_TYPE_C 0x0020 +#define RT_SDHCI_CTRL_DRV_TYPE_D 0x0030 +#define RT_SDHCI_CTRL_EXEC_TUNING 0x0040 +#define RT_SDHCI_CTRL_TUNED_CLK 0x0080 +#define RT_SDHCI_CMD23_ENABLE 0x0800 +#define RT_SDHCI_CTRL_V4_MODE 0x1000 +#define RT_SDHCI_CTRL_64BIT_ADDR 0x2000 +#define RT_SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 + +#define RT_SDHCI_CAPABILITIES 0x40 +#define RT_SDHCI_TIMEOUT_CLK_MASK RT_GENMASK(5, 0) +#define RT_SDHCI_TIMEOUT_CLK_SHIFT 0 +#define RT_SDHCI_TIMEOUT_CLK_UNIT 0x00000080 +#define RT_SDHCI_CLOCK_BASE_MASK RT_GENMASK(13, 8) +#define RT_SDHCI_CLOCK_BASE_SHIFT 8 +#define RT_SDHCI_CLOCK_V3_BASE_MASK RT_GENMASK(15, 8) +#define RT_SDHCI_MAX_BLOCK_MASK 0x00030000 +#define RT_SDHCI_MAX_BLOCK_SHIFT 16 +#define RT_SDHCI_CAN_DO_8BIT 0x00040000 +#define RT_SDHCI_CAN_DO_ADMA2 0x00080000 +#define RT_SDHCI_CAN_DO_ADMA1 0x00100000 +#define RT_SDHCI_CAN_DO_HISPD 0x00200000 +#define RT_SDHCI_CAN_DO_SDMA 0x00400000 +#define RT_SDHCI_CAN_DO_SUSPEND 0x00800000 +#define RT_SDHCI_CAN_VDD_330 0x01000000 +#define RT_SDHCI_CAN_VDD_300 0x02000000 +#define RT_SDHCI_CAN_VDD_180 0x04000000 +#define RT_SDHCI_CAN_64BIT_V4 0x08000000 +#define RT_SDHCI_CAN_64BIT 0x10000000 + +#define RT_SDHCI_CAPABILITIES_1 0x44 +#define RT_SDHCI_SUPPORT_SDR50 0x00000001 +#define RT_SDHCI_SUPPORT_SDR104 0x00000002 +#define RT_SDHCI_SUPPORT_DDR50 0x00000004 +#define RT_SDHCI_DRIVER_TYPE_A 0x00000010 +#define RT_SDHCI_DRIVER_TYPE_C 0x00000020 +#define RT_SDHCI_DRIVER_TYPE_D 0x00000040 +#define RT_SDHCI_RETUNING_TIMER_COUNT_MASK RT_GENMASK(11, 8) +#define RT_SDHCI_USE_SDR50_TUNING 0x00002000 +#define RT_SDHCI_RETUNING_MODE_MASK RT_GENMASK(15, 14) +#define RT_SDHCI_CLOCK_MUL_MASK RT_GENMASK(23, 16) +#define RT_SDHCI_CAN_DO_ADMA3 0x08000000 +#define RT_SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ + +#define RT_SDHCI_MAX_CURRENT 0x48 +#define RT_SDHCI_MAX_CURRENT_LIMIT RT_GENMASK(7, 0) +#define RT_SDHCI_MAX_CURRENT_330_MASK RT_GENMASK(7, 0) +#define RT_SDHCI_MAX_CURRENT_300_MASK RT_GENMASK(15, 8) +#define RT_SDHCI_MAX_CURRENT_180_MASK RT_GENMASK(23, 16) +#define RT_SDHCI_MAX_CURRENT_MULTIPLIER 4 + +/* 4C-4F reserved for more max current */ + +#define RT_SDHCI_SET_ACMD12_ERROR 0x50 +#define RT_SDHCI_SET_INT_ERROR 0x52 + +#define RT_SDHCI_ADMA_ERROR 0x54 + +/* 55-57 reserved */ + +#define RT_SDHCI_ADMA_ADDRESS 0x58 +#define RT_SDHCI_ADMA_ADDRESS_HI 0x5C + +/* 60-FB reserved */ + +#define RT_SDHCI_PRESET_FOR_HIGH_SPEED 0x64 +#define RT_SDHCI_PRESET_FOR_SDR12 0x66 +#define RT_SDHCI_PRESET_FOR_SDR25 0x68 +#define RT_SDHCI_PRESET_FOR_SDR50 0x6A +#define RT_SDHCI_PRESET_FOR_SDR104 0x6C +#define RT_SDHCI_PRESET_FOR_DDR50 0x6E +#define RT_SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ +#define RT_SDHCI_PRESET_DRV_MASK RT_GENMASK(15, 14) +#define BIT(nr) ((1) << (nr)) + +#define RT_SDHCI_PRESET_CLKGEN_SEL BIT(10) +#define RT_SDHCI_PRESET_SDCLK_FREQ_MASK RT_GENMASK(9, 0) + +#define RT_SDHCI_SLOT_INT_STATUS 0xFC + +#define RT_SDHCI_HOST_VERSION 0xFE +#define RT_SDHCI_VENDOR_VER_MASK 0xFF00 +#define RT_SDHCI_VENDOR_VER_SHIFT 8 +#define RT_SDHCI_SPEC_VER_MASK 0x00FF +#define RT_SDHCI_SPEC_VER_SHIFT 0 +#define RT_SDHCI_SPEC_100 0 +#define RT_SDHCI_SPEC_200 1 +#define RT_SDHCI_SPEC_300 2 +#define RT_SDHCI_SPEC_400 3 +#define RT_SDHCI_SPEC_410 4 +#define RT_SDHCI_SPEC_420 5 + +/* + * End of controller registers. + */ + +#define RT_SDHCI_MAX_DIV_SPEC_200 256 +#define RT_SDHCI_MAX_DIV_SPEC_300 2046 + +/* + * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. + */ +#define RT_SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) +#define ilog2(v) __rt_ffs(v) +#define RT_SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(RT_SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) +#define RT_SDHCI_MAX_SEGS 128 + +/* Allow for a command request and a data request at the same time */ +#define RT_SDHCI_MAX_MRQS 2 +#define MMC_CMD_TRANSFER_TIME (10 * 1000000L) /* max 10 ms */ + + +enum rt_sdhci_cookie +{ + COOKIE_UNMAPPED, + COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ + COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ +}; + +struct rt_sdhci_host +{ + const char *hw_name; /* Hardware bus name */ + + unsigned int quirks; /* Deviations from spec. */ + + void *data_buf; +/* Controller doesn't honor resets unless we touch the clock register */ +#define RT_SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0) +/* Controller has bad caps bits, but really supports DMA */ +#define RT_SDHCI_QUIRK_FORCE_DMA (1 << 1) +/* Controller doesn't like to be reset when there is no card inserted. */ +#define RT_SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 2) +/* Controller doesn't like clearing the power reg before a change */ +#define RT_SDHCI_QUIRK_SINGLE_POWER_WRITE (1 << 3) +/* Controller has an unusable DMA engine */ +#define RT_SDHCI_QUIRK_BROKEN_DMA (1 << 5) +/* Controller has an unusable ADMA engine */ +#define RT_SDHCI_QUIRK_BROKEN_ADMA (1 << 6) +/* Controller can only DMA from 32-bit aligned addresses */ +#define RT_SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 7) +/* Controller can only DMA chunk sizes that are a multiple of 32 bits */ +#define RT_SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 8) +/* Controller can only ADMA chunks that are a multiple of 32 bits */ +#define RT_SDHCI_QUIRK_32BIT_ADMA_SIZE (1 << 9) +/* Controller needs to be reset after each request to stay stable */ +#define RT_SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 10) +/* Controller needs voltage and power writes to happen separately */ +#define RT_SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 11) +/* Controller provides an incorrect timeout value for transfers */ +#define RT_SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 12) +/* Controller has an issue with buffer bits for small transfers */ +#define RT_SDHCI_QUIRK_BROKEN_SMALL_PIO (1 << 13) +/* Controller does not provide transfer-complete interrupt when not busy */ +#define RT_SDHCI_QUIRK_NO_BUSY_IRQ (1 << 14) +/* Controller has unreliable card detection */ +#define RT_SDHCI_QUIRK_BROKEN_CARD_DETECTION (1 << 15) +/* Controller reports inverted write-protect state */ +#define RT_SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1 << 16) +/* Controller has unusable command queue engine */ +#define RT_SDHCI_QUIRK_BROKEN_CQE (1 << 17) +/* Controller does not like fast PIO transfers */ +#define RT_SDHCI_QUIRK_PIO_NEEDS_DELAY (1 << 18) +/* Controller does not have a LED */ +#define RT_SDHCI_QUIRK_NO_LED (1 << 19) +/* Controller has to be forced to use block size of 2048 bytes */ +#define RT_SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1 << 20) +/* Controller cannot do multi-block transfers */ +#define RT_SDHCI_QUIRK_NO_MULTIBLOCK (1 << 21) +/* Controller can only handle 1-bit data transfers */ +#define RT_SDHCI_QUIRK_FORCE_1_BIT_DATA (1 << 22) +/* Controller needs 10ms delay between applying power and clock */ +#define RT_SDHCI_QUIRK_DELAY_AFTER_POWER (1 << 23) +/* Controller uses SDCLK instead of TMCLK for data timeouts */ +#define RT_SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 24) +/* Controller reports wrong base clock capability */ +#define RT_SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1 << 25) +/* Controller cannot support End Attribute in NOP ADMA descriptor */ +#define RT_SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1 << 26) +/* Controller uses Auto CMD12 command to stop the transfer */ +#define RT_SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1 << 28) +/* Controller doesn't have HISPD bit field in HI-SPEED SD card */ +#define RT_SDHCI_QUIRK_NO_HISPD_BIT (1 << 29) +/* Controller treats ADMA descriptors with length 0000h incorrectly */ +#define RT_SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1 << 30) +/* The read-only detection via RT_SDHCI_PRESENT_STATE register is unstable */ +#define RT_SDHCI_QUIRK_UNSTABLE_RO_DETECT (1 << 31) + + unsigned int quirks2; /* More deviations from spec. */ + +#define RT_SDHCI_QUIRK2_HOST_OFF_CARD_ON (1 << 0) +#define RT_SDHCI_QUIRK2_HOST_NO_CMD23 (1 << 1) +/* The system physically doesn't support 1.8v, even if the host does */ +#define RT_SDHCI_QUIRK2_NO_1_8_V (1 << 2) +#define RT_SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1 << 3) +#define RT_SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1 << 4) +/* Controller has a non-standard host control register */ +#define RT_SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1 << 5) +/* Controller does not support HS200 */ +#define RT_SDHCI_QUIRK2_BROKEN_HS200 (1 << 6) +/* Controller does not support DDR50 */ +#define RT_SDHCI_QUIRK2_BROKEN_DDR50 (1 << 7) +/* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ +#define RT_SDHCI_QUIRK2_STOP_WITH_TC (1 << 8) +/* Controller does not support 64-bit DMA */ +#define RT_SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1 << 9) +/* need clear transfer mode register before send cmd */ +#define RT_SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1 << 10) +/* Capability register bit-63 indicates HS400 support */ +#define RT_SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1 << 11) +/* forced tuned clock */ +#define RT_SDHCI_QUIRK2_TUNING_WORK_AROUND (1 << 12) +/* disable the block count for single block transactions */ +#define RT_SDHCI_QUIRK2_SUPPORT_SINGLE (1 << 13) +/* Controller broken with using ACMD23 */ +#define RT_SDHCI_QUIRK2_ACMD23_BROKEN (1 << 14) +/* Broken Clock divider zero in controller */ +#define RT_SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1 << 15) +/* Controller has CRC in 136 bit Command Response */ +#define RT_SDHCI_QUIRK2_RSP_136_HAS_CRC (1 << 16) + +#define RT_SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1 << 17) + +#define RT_SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1 << 18) +/* Issue CMD and DATA reset together */ +#define RT_SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1 << 19) + + int irq; /* Device IRQ */ + void *ioaddr; /* Mapped address */ + char *bounce_buffer; /* For packing SDMA reads/writes */ + rt_uint64_t bounce_addr; + unsigned int bounce_buffer_size; + + const struct rt_sdhci_ops *ops; /* Low level hw interface */ + + /* Internal data */ + struct rt_mmc_host *mmc; /* MMC structure */ + struct mmc_host_ops mmc_host_ops; /* MMC host ops */ + rt_uint64_t dma_mask; /* custom DMA mask */ + + rt_spinlock_t lock; + int flags; /* Host attributes */ +#define RT_SDHCI_USE_SDMA (1 << 0) /* Host is SDMA capable */ +#define RT_SDHCI_USE_ADMA (1 << 1) /* Host is ADMA capable */ +#define RT_SDHCI_REQ_USE_DMA (1 << 2) /* Use DMA for this req. */ +#define RT_SDHCI_DEVICE_DEAD (1 << 3) /* Device unresponsive */ +#define RT_SDHCI_SDR50_NEEDS_TUNING (1 << 4) /* SDR50 needs tuning */ +#define RT_SDHCI_AUTO_CMD12 (1 << 6) /* Auto CMD12 support */ +#define RT_SDHCI_AUTO_CMD23 (1 << 7) /* Auto CMD23 support */ +#define RT_SDHCI_PV_ENABLED (1 << 8) /* Preset value enabled */ +#define RT_SDHCI_USE_64_BIT_DMA (1 << 12) /* Use 64-bit DMA */ +#define RT_SDHCI_HS400_TUNING (1 << 13) /* Tuning for HS400 */ +#define RT_SDHCI_SIGNALING_330 (1 << 14) /* Host is capable of 3.3V signaling */ +#define RT_SDHCI_SIGNALING_180 (1 << 15) /* Host is capable of 1.8V signaling */ +#define RT_SDHCI_SIGNALING_120 (1 << 16) /* Host is capable of 1.2V signaling */ + + unsigned int version; /* RT_SDHCI spec. version */ + + unsigned int max_clk; /* Max possible freq (MHz) */ + unsigned int timeout_clk; /* Timeout freq (KHz) */ + rt_uint8_t max_timeout_count; /* Vendor specific max timeout count */ + unsigned int clk_mul; /* Clock Muliplier value */ + + unsigned int clock; /* Current clock (MHz) */ + rt_uint8_t pwr; /* Current voltage */ + rt_uint8_t drv_type; /* Current UHS-I driver type */ + rt_bool_t reinit_uhs; /* Force UHS-related re-initialization */ + + rt_bool_t runtime_suspended; /* Host is runtime suspended */ + rt_bool_t bus_on; /* Bus power prevents runtime suspend */ + rt_bool_t preset_enabled; /* Preset is enabled */ + rt_bool_t pending_reset; /* Cmd/data reset is pending */ + rt_bool_t irq_wake_enabled; /* IRQ wakeup is enabled */ + rt_bool_t v4_mode; /* Host Version 4 Enable */ + rt_bool_t always_defer_done; /* Always defer to complete requests */ + + struct rt_mmcsd_req *mrqs_done[RT_SDHCI_MAX_MRQS]; /* Requests done */ + struct rt_mmcsd_cmd *cmd; /* Current command */ + struct rt_mmcsd_cmd *data_cmd; /* Current data command */ + struct rt_mmcsd_cmd *deferred_cmd; /* Deferred command */ + struct rt_mmcsd_data *data; /* Current data request */ + unsigned int data_early : 1; /* Data finished before cmd */ + + unsigned int blocks; /* remaining PIO blocks */ + size_t align_buffer_sz; /* Bounce buffer size */ + rt_uint64_t align_addr; /* Mapped bounce buffer */ + + struct rt_workqueue *complete_wq; /* Request completion wq */ + struct rt_work complete_work; /* Request completion work */ + + struct rt_workqueue *irq_wq; + struct rt_work irq_work; + + struct rt_timer timer; /* Timer for timeouts */ + struct rt_timer data_timer; /* Timer for data timeouts */ + + rt_uint32_t caps; /* CAPABILITY_0 */ + rt_uint32_t caps1; /* CAPABILITY_1 */ + rt_bool_t read_caps; /* Capability flags have been read */ + + rt_bool_t sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */ + unsigned int ocr_avail_sdio; /* OCR bit masks */ + unsigned int ocr_avail_sd; + unsigned int ocr_avail_mmc; + rt_uint32_t ocr_mask; /* available voltages */ + + unsigned timing; /* Current timing */ + + rt_uint32_t thread_isr; + + /* cached registers */ + rt_uint32_t ier; + + rt_bool_t cqe_on; /* CQE is operating */ + rt_uint32_t cqe_ier; /* CQE interrupt mask */ + rt_uint32_t cqe_err_ier; /* CQE error interrupt mask */ + + rt_wqueue_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ + unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ + + unsigned int tuning_count; /* Timer count for re-tuning */ + unsigned int tuning_mode; /* Re-tuning mode supported by host */ + unsigned int tuning_err; /* Error code for re-tuning */ +#define RT_SDHCI_TUNING_MODE_1 0 +#define RT_SDHCI_TUNING_MODE_2 1 +#define RT_SDHCI_TUNING_MODE_3 2 + /* Delay (ms) between tuning commands */ + int tuning_delay; + int tuning_loop_count; + + /* Host SDMA buffer boundary. */ + rt_uint32_t sdma_boundary; + rt_uint64_t data_timeout; + + unsigned long private[]; +}; + +static inline rt_uint8_t u8_read(const volatile void *addr) +{ + return *(const volatile rt_uint8_t *)addr; +} + +static inline rt_uint16_t u16_read(const volatile void *addr) +{ + return *(const volatile rt_uint16_t *)addr; +} + +static inline rt_uint32_t u32_read(const volatile void *addr) +{ + return *(const volatile rt_uint32_t *)addr; +} + +static inline void u8_write(rt_uint8_t value, volatile void *addr) +{ + *(volatile rt_uint8_t *)addr = value; +} + +static inline void u16_write(rt_uint16_t value, volatile void *addr) +{ + *(volatile rt_uint16_t *)addr = value; +} + +static inline void u32_write(rt_uint32_t value, volatile void *addr) +{ + *(volatile rt_uint32_t *)addr = value; +} + +#define readb(c) u8_read(c) +#define readw(c) u16_read(c) +#define readl(c) u32_read(c) +#define readsb(p, d, l) ({ __raw_readsb(p,d,l); __iormb(); }) +#define readsw(p, d, l) ({ __raw_readsw(p,d,l); __iormb(); }) +#define readsl(p, d, l) ({ __raw_readsl(p,d,l); __iormb(); }) + +#define writeb(v, c) u8_write(v, c) +#define writew(v, c) u16_write(v, c) +#define writel(v, c) u32_write(v, c) +#define writesb(p, d, l) ({ __iowmb(); __raw_writesb(p,d,l); }) +#define writesw(p, d, l) ({ __iowmb(); __raw_writesw(p,d,l); }) +#define writesl(p, d, l) ({ __iowmb(); __raw_writesl(p,d,l); }) + +static inline void rt_sdhci_writel(struct rt_sdhci_host *host, rt_uint32_t val, int reg) +{ + writel(val, host->ioaddr + reg); +} + +static inline void rt_sdhci_writew(struct rt_sdhci_host *host, rt_uint16_t val, int reg) +{ + writew(val, host->ioaddr + reg); +} + +static inline void rt_sdhci_writeb(struct rt_sdhci_host *host, rt_uint8_t val, int reg) +{ + writeb(val, host->ioaddr + reg); +} + +static inline rt_uint32_t rt_sdhci_readl(struct rt_sdhci_host *host, int reg) +{ + return readl(host->ioaddr + reg); +} + +static inline rt_uint16_t rt_sdhci_readw(struct rt_sdhci_host *host, int reg) +{ + return readw(host->ioaddr + reg); +} + +static inline rt_uint8_t rt_sdhci_readb(struct rt_sdhci_host *host, int reg) +{ + return readb(host->ioaddr + reg); +} + + +struct rt_sdhci_ops +{ + void (*set_clock)(struct rt_sdhci_host *host, unsigned int clock); + void (*set_power)(struct rt_sdhci_host *host, unsigned char mode, + unsigned short vdd); + rt_uint32_t (*irq)(struct rt_sdhci_host *host, rt_uint32_t intmask); + int (*set_dma_mask)(struct rt_sdhci_host *host); + int (*enable_dma)(struct rt_sdhci_host *host); + unsigned int (*get_max_clock)(struct rt_sdhci_host *host); + unsigned int (*get_min_clock)(struct rt_sdhci_host *host); + unsigned int (*get_timeout_clock)(struct rt_sdhci_host *host); + unsigned int (*get_max_timeout_count)(struct rt_sdhci_host *host); + void (*set_timeout)(struct rt_sdhci_host *host, + struct rt_mmcsd_cmd *cmd); + void (*set_bus_width)(struct rt_sdhci_host *host, int width); + unsigned int (*get_ro)(struct rt_sdhci_host *host); + void (*reset)(struct rt_sdhci_host *host, rt_uint8_t mask); + int (*platform_execute_tuning)(struct rt_sdhci_host *host, rt_uint32_t opcode); + void (*set_uhs_signaling)(struct rt_sdhci_host *host, unsigned int uhs); + void (*hw_reset)(struct rt_sdhci_host *host); + void (*card_event)(struct rt_sdhci_host *host); + void (*voltage_switch)(struct rt_sdhci_host *host); + void (*request_done)(struct rt_sdhci_host *host, + struct rt_mmcsd_req *mrq); +}; + + +struct rt_sdhci_host *rt_sdhci_alloc_host(struct rt_device *dev, size_t priv_size); +void rt_sdhci_free_host(struct rt_sdhci_host *host); + +static inline void *sdhci_priv(struct rt_sdhci_host *host) +{ + return host->private; +} + +void rt_sdhci_read_caps(struct rt_sdhci_host *host, const rt_uint16_t *ver, + const rt_uint32_t *caps, const rt_uint32_t *caps1); +int rt_sdhci_setup_host(struct rt_sdhci_host *host); +void rt_sdhci_cleanup_host(struct rt_sdhci_host *host); +int rt_sdhci_set_and_add_host(struct rt_sdhci_host *host); +int rt_sdhci_init_host(struct rt_sdhci_host *host); +void rt_sdhci_uninit_host(struct rt_sdhci_host *host, int dead); + +rt_uint16_t rt_sdhci_clk_set(struct rt_sdhci_host *host, unsigned int clock, + unsigned int *actual_clock); +void rt_sdhci_set_clock(struct rt_sdhci_host *host, unsigned int clock); +void rt_sdhci_clk_enable(struct rt_sdhci_host *host, rt_uint16_t clk); +void rt_sdhci_set_power(struct rt_sdhci_host *host, unsigned char mode,unsigned short vdd); +void rt_read_reg(struct rt_sdhci_host* host); + +void rt_sdhci_set_power_with_noreg(struct rt_sdhci_host *host, unsigned char mode, + unsigned short vdd); +void rt_sdhci_start_request(struct rt_mmc_host *mmc, struct rt_mmcsd_req *mrq); +int rt_sdhci_start_request_atomic(struct rt_mmc_host *mmc, struct rt_mmcsd_req *mrq); +void rt_sdhci_set_bus_width(struct rt_sdhci_host *host, int width); +void rt_sdhci_reset(struct rt_sdhci_host *host, rt_uint8_t mask); +void rt_sdhci_set_uhs(struct rt_sdhci_host *host, unsigned timing); +int rt_sdhci_execute_tuning(struct rt_mmc_host *mmc, rt_uint32_t opcode); +int __sdhci_execute_tuning(struct rt_sdhci_host *host, rt_uint32_t opcode); +void rt_sdhci_ios_set(struct rt_mmc_host *mmc, struct rt_mmcsd_io_cfg *ios); +int rt_sdhci_start_signal_voltage_switch(struct rt_mmc_host *mmc, + struct rt_mmcsd_io_cfg *ios); +void rt_sdhci_enable_io_irq(struct rt_mmc_host *mmc, int enable); +void rt_sdhci_start_tuning(struct rt_sdhci_host *host); +void rt_sdhci_end_tuning(struct rt_sdhci_host *host); +void rt_sdhci_reset_tuning(struct rt_sdhci_host *host); +void rt_sdhci_send_tuning(struct rt_sdhci_host *host, rt_uint32_t opcode); +void rt_sdhci_abort_tuning(struct rt_sdhci_host *host, rt_uint32_t opcode); +void rt_sdhci_data_irq_timeout(struct rt_sdhci_host *host, rt_bool_t enable); +void rt_sdhci_timeout_set(struct rt_sdhci_host *host, struct rt_mmcsd_cmd *cmd); +void rt_read_reg_debug(struct rt_sdhci_host* host); + +#endif /* __RT_SDHCI_HW_H */ diff --git a/rt-thread/components/drivers/sdio/sdhci/include/sdhci_host.h b/rt-thread/components/drivers/sdio/sdhci/include/sdhci_host.h new file mode 100644 index 0000000..8584ab4 --- /dev/null +++ b/rt-thread/components/drivers/sdio/sdhci/include/sdhci_host.h @@ -0,0 +1,345 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-08-16 zhujiale first version + */ +#ifndef __RT_SDHCI_MMC_H__ +#define __RT_SDHCI_MMC_H__ + +#include +#include +#include +#include +#include +#define mmc_dev(x) ((x)->parent) + +#define MMC_SEND_TUNING_BLOCK_HS200 SEND_TUNING_BLOCK_HS200 +#define MMC_SEND_TUNING_BLOCK SEND_TUNING_BLOCK +#define MMC_STOP_TRANSMISSION STOP_TRANSMISSION +#define MMC_BUS_TEST_R 14 /* adtc R1 */ +#define MMC_WRITE_MULTIPLE_BLOCK WRITE_MULTIPLE_BLOCK +#define MMC_READ_MULTIPLE_BLOCK READ_MULTIPLE_BLOCK + +#define MMC_TIMING_UHS_DDR50 MMCSD_TIMING_UHS_DDR50 +#define MMC_TIMING_UHS_SDR50 MMCSD_TIMING_UHS_SDR50 +#define MMC_TIMING_MMC_HS200 MMCSD_TIMING_MMC_HS200 +#define MMC_TIMING_MMC_HS400 MMCSD_TIMING_MMC_HS400 +#define MMC_TIMING_UHS_SDR104 MMCSD_TIMING_UHS_SDR104 +#define MMC_TIMING_UHS_SDR25 MMCSD_TIMING_UHS_SDR25 +#define MMC_TIMING_MMC_DDR52 MMCSD_TIMING_MMC_DDR52 +#define MMC_TIMING_UHS_SDR12 MMCSD_TIMING_UHS_SDR12 +#define MMC_TIMING_SD_HS MMCSD_TIMING_SD_HS +#define MMC_TIMING_MMC_HS MMCSD_TIMING_MMC_HS + +#define MMC_POWER_OFF MMCSD_POWER_OFF +#define MMC_POWER_UP MMCSD_POWER_UP +#define MMC_POWER_ON MMCSD_POWER_ON +#define MMC_POWER_UNDEFINED 3 + +#define MMC_SET_DRIVER_TYPE_B 0 +#define MMC_SET_DRIVER_TYPE_A 1 +#define MMC_SET_DRIVER_TYPE_C 2 +#define MMC_SET_DRIVER_TYPE_D 3 + +#define MMC_SIGNAL_VOLTAGE_330 0 +#define MMC_SIGNAL_VOLTAGE_180 1 +#define MMC_SIGNAL_VOLTAGE_120 2 + +#define MMC_RSP_PRESENT (1 << 16) +#define MMC_RSP_136 (1 << 17) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 18) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 19) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 20) /* response contains opcode */ + +#define MMC_RSP_NONE (0) +#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) +#define MMC_RSP_R1B (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY) +#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC) +#define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R4 (MMC_RSP_PRESENT) +#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) +#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) +#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) + +#define MMC_CMD_ADTC CMD_ADTC + +#define MMC_BUS_WIDTH_8 MMCSD_BUS_WIDTH_8 +#define MMC_BUS_WIDTH_4 MMCSD_BUS_WIDTH_4 +#define MMC_BUS_WIDTH_1 MMCSD_BUS_WIDTH_1 + +#define MMC_PM_KEEP_POWER (1 << 0) /* preserve card power during suspend */ +#define MMC_PM_WAKE_SDIO_IRQ (1 << 1) /* wake up host system on SDIO IRQ assertion */ +enum mmc_blk_status +{ + MMC_BLK_SUCCESS = 0, + MMC_BLK_PARTIAL, + MMC_BLK_CMD_ERR, + MMC_BLK_RETRY, + MMC_BLK_ABORT, + MMC_BLK_DATA_ERR, + MMC_BLK_ECC_ERR, + MMC_BLK_NOMEDIUM, + MMC_BLK_NEW_REQUEST, +}; + +#define MMC_NUM_CLK_PHASES (MMC_TIMING_MMC_HS400 + 1) + +struct rt_mmc_host ; + +struct mmc_host_ops +{ + void (*request)(struct rt_mmc_host *host, struct rt_mmcsd_req *req); + void (*set_ios)(struct rt_mmc_host *host, struct rt_mmcsd_io_cfg *ios); + int (*get_ro)(struct rt_mmc_host *host); + int (*get_cd)(struct rt_mmc_host *host); + void (*enable_sdio_irq)(struct rt_mmc_host *host, int enable); + void (*ack_sdio_irq)(struct rt_mmc_host *host); + int (*start_signal_voltage_switch)(struct rt_mmc_host *host, struct rt_mmcsd_io_cfg *ios); + int (*card_busy)(struct rt_mmc_host *host); + int (*execute_tuning)(struct rt_mmc_host *host, unsigned opcode); + int (*prepare_hs400_tuning)(struct rt_mmc_host *host, struct rt_mmcsd_io_cfg *ios); + int (*hs400_prepare_ddr)(struct rt_mmc_host *host); + void (*hs400_downgrade)(struct rt_mmc_host *host); + void (*hs400_complete)(struct rt_mmc_host *host); + void (*hs400_enhanced_strobe)(struct rt_mmc_host *host, + struct rt_mmcsd_io_cfg* ios); + void (*hw_reset)(struct rt_mmc_host* host); + void (*card_event)(struct rt_mmc_host* host); +}; + +struct regulator; +struct mmc_pwrseq; + +struct mmc_supply +{ + struct regulator *vmmc; /* Card power supply */ + struct regulator *vqmmc; /* Optional Vccq supply */ +}; + +struct mmc_ctx +{ + struct task_struct *task; +}; + +/* VDD voltage 3.3 ~ 3.4 */ +#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ + +#define MMC_CAP2_HS200_1_8V_SDR MMCSD_SUP_HS200_1V8 +#define MMC_CAP_4_BIT_DATA MMCSD_BUSWIDTH_4 +#define MMC_CAP_8_BIT_DATA MMCSD_BUSWIDTH_8 +#define MMC_CAP2_HS200 MMCSD_SUP_HS200 +#define MMC_CAP_MMC_HIGHSPEED MMCSD_SUP_HIGHSPEED +#define MMC_CAP_SD_HIGHSPEED MMCSD_SUP_HIGHSPEED +#define MMC_CAP_1_8V_DDR MMCSD_SUP_DDR_1V8 +#define MMC_CAP_3_3V_DDR MMCSD_SUP_DDR_3V3 +#define MMC_CAP_1_2V_DDR MMCSD_SUP_DDR_1V2 +#define MMC_CAP_NONREMOVABLE MMCSD_SUP_NONREMOVABLE + + +#define MMC_CAP_UHS_DDR50 0 +#define MMC_CAP2_HS400 0 +#define MMC_CAP_UHS_SDR50 0 +#define MMC_CAP_UHS_SDR25 0 +#define MMC_CAP_UHS_SDR12 0 +#define MMC_CAP_UHS_SDR104 0 +#define MMC_CAP_UHS 0 +#define MMC_CAP2_HSX00_1_8V 0 +#define MMC_CAP2_HS400_ES 0 +#define MMC_CAP_NEEDS_POLL 0 +#define MMC_CAP2_HSX00_1_2V 0 +#define MMC_CAP2_HS400_1_8V 0 +#define MMC_CAP_DRIVER_TYPE_D 0 +#define MMC_CAP_DRIVER_TYPE_C 0 +#define MMC_SET_DRIVER_TYPE_B 0 +#define MMC_CAP_DRIVER_TYPE_A 0 +#define MMC_CAP2_SDIO_IRQ_NOTHREAD 0 +#define MMC_CAP_CMD23 0 +#define MMC_CAP_SDIO_IRQ 0 + +#define MMC_CAP2_NO_SDIO (1 << 19) +#define MMC_CAP2_NO_SD (1 << 21) +#define MMC_CAP2_NO_MMC (1 << 22) +#define MMC_CAP2_CQE (1 << 23) + +#define MMC_VDD_165_195 VDD_165_195 +#define MMC_VDD_20_21 VDD_20_21 +#define MMC_VDD_29_30 VDD_29_30 +#define MMC_VDD_30_31 VDD_30_31 +#define MMC_VDD_32_33 VDD_32_33 +#define MMC_VDD_33_34 VDD_33_34 + + +struct rt_mmc_host +{ + struct rt_mmcsd_host rthost; + struct rt_device *parent; + int index; + const struct mmc_host_ops *ops; + unsigned int f_min; + unsigned int f_max; + unsigned int f_init; + rt_uint32_t ocr_avail; + rt_uint32_t ocr_avail_sdio; /* SDIO-specific OCR */ + rt_uint32_t ocr_avail_sd; /* SD-specific OCR */ + rt_uint32_t ocr_avail_mmc; /* MMC-specific OCR */ + struct wakeup_source *ws; /* Enable consume of uevents */ + rt_uint32_t max_current_330; + rt_uint32_t max_current_300; + rt_uint32_t max_current_180; + rt_uint32_t caps; /* Host capabilities */ + + rt_uint32_t caps2; /* More host capabilities */ + + + /* host specific block data */ + unsigned int max_seg_size; /* see blk_queue_max_segment_size */ + unsigned short max_segs; /* see blk_queue_max_segments */ + unsigned short unused; + unsigned int max_req_size; /* maximum number of bytes in one req */ + unsigned int max_blk_size; /* maximum size of one mmc block */ + unsigned int max_blk_count; /* maximum number of blocks in one req */ + unsigned int max_busy_timeout; /* max busy timeout in ms */ + struct rt_mmcsd_io_cfg ios; /* current io bus settings */ + unsigned int retune_period; + /* group bitfields together to minimize padding */ + unsigned int use_spi_crc : 1; + unsigned int claimed : 1; /* host exclusively claimed */ + unsigned int doing_init_tune : 1; /* initial tuning in progress */ + unsigned int can_retune : 1; /* re-tuning can be used */ + unsigned int doing_retune : 1; /* re-tuning in progress */ + unsigned int retune_now : 1; /* do re-tuning at next req */ + unsigned int retune_paused : 1; /* re-tuning is temporarily disabled */ + unsigned int retune_crc_disable : 1; /* don't trigger retune upon crc */ + unsigned int can_dma_map_merge : 1; /* merging can be used */ + unsigned int vqmmc_enabled : 1; /* vqmmc regulator is enabled */ + + int need_retune; /* re-tuning is needed */ + int hold_retune; /* hold off re-tuning */ + rt_bool_t trigger_card_event; /* card_event necessary */ + unsigned int sdio_irqs; + rt_bool_t sdio_irq_pending; + + struct led_trigger *led; /* activity led */ + + struct mmc_supply supply; + + + /* Ongoing data transfer that allows commands during transfer */ + struct rt_mmcsd_req *ongoing_mrq; + + + unsigned int actual_clock; /* Actual HC clock rate */ + rt_uint32_t pm_caps; + unsigned long private[]; +}; + + +static inline int mmc_card_is_removable(struct rt_mmc_host *host) +{ + return !(host->caps & MMC_CAP_NONREMOVABLE); +} + +struct device_node; +struct rt_mmc_host *rt_mmc_alloc_host(int extra, struct rt_device *); +int rt_mmc_add_host(struct rt_mmc_host *); +void rt_mmc_remove_host(struct rt_mmc_host *); +void rt_mmc_free_host(struct rt_mmc_host *); +int rt_mmc_of_parse(struct rt_mmc_host *host); +int rt_mmc_of_parse_voltage(struct rt_mmc_host *host, rt_uint32_t *mask); + +static inline void *mmc_priv(struct rt_mmc_host *host) +{ + return (void *)host->private; +} + + +#define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI) + +#define mmc_dev(x) ((x)->parent) +#define mmc_classdev(x) (&(x)->class_dev) +#define mmc_hostname(x) (x->parent->parent.name) + +void rt_mmc_detect_change(struct rt_mmc_host *, unsigned long delay); +void rt_mmc_request_done(struct rt_mmc_host *, struct rt_mmcsd_req *); +void mmc_command_done(struct rt_mmc_host *host, struct rt_mmcsd_req *mrq); + +void mmc_cqe_request_done(struct rt_mmc_host *host, struct rt_mmcsd_req *mrq); + +static inline rt_bool_t sdio_irq_claimed(struct rt_mmc_host *host) +{ + return host->sdio_irqs > 0; +} + +static inline int mmc_regulator_set_ocr(struct rt_mmc_host *mmc, + struct regulator *supply, + unsigned short vdd_bit) +{ + return 0; +} + +int mmc_regulator_get_supply(struct rt_mmc_host *mmc); +int mmc_regulator_enable_vqmmc(struct rt_mmc_host *mmc); +void mmc_regulator_disable_vqmmc(struct rt_mmc_host *mmc); + +void mmc_retune_timer_stop(struct rt_mmc_host* host); + +enum dma_data_direction +{ + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, + DMA_NONE = 3, +}; +#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL << (n)) - 1)) +static inline void mmc_retune_needed(struct rt_mmc_host *host) +{ + if (host->can_retune) + host->need_retune = 1; +} + +static inline rt_bool_t mmc_can_retune(struct rt_mmc_host *host) +{ + return host->can_retune == 1; +} + +static inline rt_bool_t mmc_doing_retune(struct rt_mmc_host *host) +{ + return host->doing_retune == 1; +} + +static inline rt_bool_t mmc_doing_tune(struct rt_mmc_host *host) +{ + return host->doing_retune == 1 || host->doing_init_tune == 1; +} + +static inline int mmc_get_dma_dir(struct rt_mmcsd_data *data) +{ + return data->flags & DATA_DIR_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE; +} + +static inline rt_bool_t mmc_op_multi(rt_uint32_t opcode) +{ + return opcode == MMC_WRITE_MULTIPLE_BLOCK || opcode == MMC_READ_MULTIPLE_BLOCK; +} + +static inline rt_bool_t mmc_op_tuning(rt_uint32_t opcode) +{ + return opcode == MMC_SEND_TUNING_BLOCK || opcode == MMC_SEND_TUNING_BLOCK_HS200; +} + +int rt_mmc_gpio_get_cd(struct rt_mmc_host *host); +void rt_mmc_detect_change(struct rt_mmc_host *host, unsigned long delay); +int rt_mmc_regulator_set_vqmmc(struct rt_mmc_host *mmc, struct rt_mmcsd_io_cfg *ios); +rt_bool_t rt_mmc_can_gpio_ro(struct rt_mmc_host *host); +int rt_mmc_gpio_get_ro(struct rt_mmc_host *host); + +int rt_mmc_send_abort_tuning(struct rt_mmc_host *host, rt_uint32_t opcode); +int rt_mmc_of_parse(struct rt_mmc_host *host); + + +#endif diff --git a/rt-thread/components/drivers/sdio/sdhci/include/sdhci_misc.h b/rt-thread/components/drivers/sdio/sdhci/include/sdhci_misc.h new file mode 100644 index 0000000..4614458 --- /dev/null +++ b/rt-thread/components/drivers/sdio/sdhci/include/sdhci_misc.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-08-16 zhujiale first version + */ +#ifndef __RT_SDHCI_MISC_H__ +#define __RT_SDHCI_MISC_H__ + + +#define __BF_FIELD_CHECK(...) +#define __bf_shf(x) (__builtin_ffsll(x) - 1) +#define FIELD_GET(_mask, _reg) \ + ({ \ + __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + +#define FIELD_PREP(_mask, _val) \ + ({ \ + __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ + ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ + }) + +#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + +#define min_t(type, x, y) (((type)x < (type)y) ? x : y) +#define max_t(type, x, y) (((type)x > (type)y) ? x : y) +#define min(x, y) ((x) < (y) ? (x) : (y)) + +#define from_timer(var, callback_timer, timer_fieldname) \ + container_of(callback_timer, typeof(*var), timer_fieldname) + + +#define le32_to_cpu(x) (x) +#define le16_to_cpu(x) (x) +#define cpu_to_le16(x) (x) +#define cpu_to_le32(x) (x) +#define lower_32_bits(n) ((rt_uint32_t)((n) & 0xffffffff)) +#define upper_32_bits(n) ((rt_uint32_t)(((n) >> 16) >> 16)) + +#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + +#define do_div(n, base) ({ \ + uint32_t __base = (base); \ + uint32_t __rem; \ + __rem = ((uint64_t)(n)) % __base; \ + (n) = ((uint64_t)(n)) / __base; \ + __rem; \ +}) + +#define fallthrough \ + do { \ + } while (0) + +int regulator_is_supported_voltage(struct regulator *regulator, + int min_uV, int max_uV); +rt_bool_t rt_mmc_can_gpio_cd(struct rt_mmc_host *host); + +struct regulator +{ + const char *supply_name; +}; + +int regulator_get_current_limit(struct regulator *regulator); + +#endif diff --git a/rt-thread/components/drivers/sdio/sdhci/sdhci-platform.c b/rt-thread/components/drivers/sdio/sdhci/sdhci-platform.c new file mode 100644 index 0000000..d6cf4ed --- /dev/null +++ b/rt-thread/components/drivers/sdio/sdhci/sdhci-platform.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-08-16 zhujiale first version + */ +#include "sdhci-platform.h" + +static const struct rt_sdhci_ops sdhci_pltfm_ops = { + .set_clock = rt_sdhci_set_clock, + .set_bus_width = rt_sdhci_set_bus_width, + .reset = rt_sdhci_reset, + .set_uhs_signaling = rt_sdhci_set_uhs, +}; + +void rt_sdhci_get_property(struct rt_platform_device *pdev) +{ + struct rt_device *dev = &pdev->parent; + struct rt_sdhci_host *host = pdev->priv; + struct rt_sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + rt_uint32_t bus_width; + + if (rt_dm_dev_prop_read_bool(dev, "sdhci,auto-cmd12")) + host->quirks |= RT_SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; + + if (rt_dm_dev_prop_read_bool(dev, "sdhci,1-bit-only") || (rt_dm_dev_prop_read_u32(dev, "bus-width", &bus_width) == 0 && bus_width == 1)) + host->quirks |= RT_SDHCI_QUIRK_FORCE_1_BIT_DATA; + + if (rt_dm_dev_prop_read_bool(dev, "broken-cd")) + host->quirks |= RT_SDHCI_QUIRK_BROKEN_CARD_DETECTION; + + if (rt_dm_dev_prop_read_bool(dev, "no-1-8-v")) + host->quirks2 |= RT_SDHCI_QUIRK2_NO_1_8_V; + + rt_dm_dev_prop_read_u32(dev, "clock-frequency", &pltfm_host->clock); + + if (rt_dm_dev_prop_read_bool(dev, "keep-power-in-suspend")) + host->mmc->pm_caps |= MMC_PM_KEEP_POWER; + + if (rt_dm_dev_prop_read_bool(dev, "wakeup-source") || rt_dm_dev_prop_read_bool(dev, "enable-sdio-wakeup")) /* legacy */ + host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; +} + +struct rt_sdhci_host *rt_sdhci_pltfm_init(struct rt_platform_device *pdev, + const struct rt_sdhci_pltfm_data *pdata, + size_t priv_size) +{ + struct rt_sdhci_host *host; + struct rt_device *dev = &pdev->parent; + void *ioaddr; + int irq; + + ioaddr = rt_dm_dev_iomap(dev, 0); + if (!ioaddr) + { + return RT_NULL; + } + + irq = rt_dm_dev_get_irq(dev, 0); + if (irq < 0) + { + return RT_NULL; + } + host = rt_sdhci_alloc_host(dev,sizeof(struct rt_sdhci_pltfm_host) + priv_size); + if (!host) + { + return RT_NULL; + } + host->irq = irq; + host->ioaddr = ioaddr; + host->hw_name = rt_dm_dev_get_name(dev); + + if (pdata && pdata->ops) + host->ops = pdata->ops; + else + host->ops = &sdhci_pltfm_ops; + if (pdata) + { + host->quirks = pdata->quirks; + host->quirks2 = pdata->quirks2; + } + + pdev->priv = host; + + return host; +} + +int rt_sdhci_pltfm_init_and_add_host(struct rt_platform_device *pdev, + const struct rt_sdhci_pltfm_data *pdata, + size_t priv_size) +{ + struct rt_sdhci_host *host; + int ret = 0; + + host = rt_sdhci_pltfm_init(pdev, pdata, priv_size); + if (!host) + return -RT_ERROR; + + rt_sdhci_get_property(pdev); + + ret = rt_sdhci_init_host(host); + if (ret) + rt_sdhci_pltfm_free(pdev); + + return ret; +} + +void rt_sdhci_pltfm_free(struct rt_platform_device *pdev) +{ + struct rt_sdhci_host *host = pdev->priv; + + rt_sdhci_free_host(host); +} + +void rt_sdhci_pltfm_remove(struct rt_platform_device *pdev) +{ + struct rt_sdhci_host *host = pdev->priv; + int dead = (readl(host->ioaddr + RT_SDHCI_INT_STATUS) == 0xffffffff); + + rt_sdhci_uninit_host(host, dead); + rt_sdhci_pltfm_free(pdev); +} diff --git a/rt-thread/components/drivers/sdio/sdhci/sdhci.c b/rt-thread/components/drivers/sdio/sdhci/sdhci.c new file mode 100644 index 0000000..6f52b5e --- /dev/null +++ b/rt-thread/components/drivers/sdio/sdhci/sdhci.c @@ -0,0 +1,3152 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-08-16 zhujiale first version + */ + +#include +#include +#include "sdhci.h" +#include +#define DBG_TAG "RT_SDHCI" +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ +#include +static unsigned int debug_quirks = 0; +static unsigned int debug_quirks2; +/********************************************************* */ +/* cmd */ +/********************************************************* */ + + +void rt_read_reg_debug(struct rt_sdhci_host *host) +{ + rt_kprintf("0x00 addddddddddddd = %x \n", rt_sdhci_readl(host, 0x00)); + rt_kprintf("0x04 EMMC_BLOCKSIZE = %x \n", rt_sdhci_readw(host, 0x04)); + rt_kprintf("0x06 EMMC_BLOCKCOUNT = %x \n", rt_sdhci_readw(host, 0x06)); + rt_kprintf("0x08 RT_SDHCI_ARGUMENT = %x \n", rt_sdhci_readl(host, 0x08)); + rt_kprintf("0x0c EMMC_XFER_MODE = %x \n", rt_sdhci_readw(host, 0x0c)); + rt_kprintf("0x0e RT_SDHCI_COMMAND = %x \n", rt_sdhci_readw(host, 0x0e)); + rt_kprintf("0x24 RT_SDHCI_PRESENT_STATE = %x \n", rt_sdhci_readl(host, 0x24)); + rt_kprintf("0x28 RT_SDHCI_HOST_CONTROL = %x \n", rt_sdhci_readb(host, 0x28)); + rt_kprintf("0x29 RT_SDHCI_POWER_CONTROL = %x \n", rt_sdhci_readb(host, 0x29)); + rt_kprintf("0x2a EMMC_BGAP_CTRL = %x \n", rt_sdhci_readb(host, 0x2a)); + rt_kprintf("0x2c EMMC_CLK_CTRL = %x \n", rt_sdhci_readw(host, 0x2c)); + rt_kprintf("0x2e EMMC_TOUT_CTRL = %x \n", rt_sdhci_readb(host, 0x2e)); + rt_kprintf("0x2f EMMC_SW_RST = %x \n", rt_sdhci_readb(host, 0x2f)); + rt_kprintf("0x30 RT_SDHCI_INT_STATUS = %x \n", rt_sdhci_readw(host, 0x30)); + rt_kprintf("0x32 RT_SDHCI_ERR_INT_STATUS = %x \n", rt_sdhci_readw(host, 0x32)); + rt_kprintf("0x34 RT_SDHCI_INT_ENABLE = %x \n", rt_sdhci_readw(host, 0x34)); + rt_kprintf("0x36 EMMC ERROR INT STATEN = %x \n", rt_sdhci_readw(host, 0x36)); + rt_kprintf("0x38 EMMC NORMAL INT SIGNAL EN = %x \n", rt_sdhci_readw(host, 0x38)); + rt_kprintf("0x3a EMMC ERROR INT SIGNAL EN = %x \n", rt_sdhci_readw(host, 0x3a)); + rt_kprintf("0x3c EMMC_AUTO_CMD_STAT = %x \n", rt_sdhci_readw(host, 0x3c)); + rt_kprintf("0x3e EMMC_HOST_CTRL2 = %x \n", rt_sdhci_readw(host, 0x3e)); + rt_kprintf("0x40 EMMC_CAPABILITIES1 = %x \n", rt_sdhci_readl(host, 0x40)); + rt_kprintf("0x44 EMMC_CAPABILITIES2 = %x \n", rt_sdhci_readl(host, 0x44)); + rt_kprintf("0x52 EMMC_FORC_ERR_INT_STAT = %x \n", rt_sdhci_readw(host, 0x52)); + rt_kprintf("0x54 EMMC_ADMA_ERR_STAT = %x \n", rt_sdhci_readb(host, 0x54)); + rt_kprintf("0x58 EMMC_ADMA_SA = %x \n", rt_sdhci_readl(host, 0x58)); + rt_kprintf("0x66 EMMC_PRESET_SDR12 = %x \n", rt_sdhci_readw(host, 0x66)); + rt_kprintf("0x68 EMMC_PRESET_SDR25 = %x \n", rt_sdhci_readw(host, 0x68)); + rt_kprintf("0x6a EMMC_PRESET_SDR50 = %x \n", rt_sdhci_readw(host, 0x6a)); + rt_kprintf("0x6c EMMC_PRESET_SDR104 = %x \n", rt_sdhci_readw(host, 0x6c)); + rt_kprintf("0x6e EMMC_PRESET_DDR50 = %x \n", rt_sdhci_readw(host, 0x6e)); + rt_kprintf("0x78 EMMC_ADMA_ID = %x \n", rt_sdhci_readl(host, 0x78)); + rt_kprintf("0xfe EMMC_HOST_CNTRL_VERS = %x \n", rt_sdhci_readw(host, 0xfe)); + +} +static inline rt_bool_t sdhci_has_requests(struct rt_sdhci_host *host) +{ + return host->cmd || host->data_cmd; +} + +static inline rt_bool_t sdhci_auto_cmd23(struct rt_sdhci_host *host, + struct rt_mmcsd_req *mrq) +{ + return mrq->sbc && (host->flags & RT_SDHCI_AUTO_CMD23); +} + +static inline rt_bool_t sdhci_auto_cmd12(struct rt_sdhci_host *host, + struct rt_mmcsd_req *mrq) +{ + return !mrq->sbc && (host->flags & RT_SDHCI_AUTO_CMD12) && !mrq->cap_cmd_during_tfr; +} + +static inline rt_bool_t sdhci_manual_cmd23(struct rt_sdhci_host *host, + struct rt_mmcsd_req *mrq) +{ + return mrq->sbc && !(host->flags & RT_SDHCI_AUTO_CMD23); +} + +static inline rt_bool_t sdhci_data_line_cmd(struct rt_mmcsd_cmd *cmd) +{ + return cmd->data || cmd->flags & MMC_RSP_BUSY; +} + +void rt_sdhci_data_irq_timeout(struct rt_sdhci_host *host, rt_bool_t enable) +{ + if (enable) + host->ier |= RT_SDHCI_INT_DATA_TIMEOUT; + else + host->ier &= ~RT_SDHCI_INT_DATA_TIMEOUT; + rt_sdhci_writel(host, host->ier, RT_SDHCI_INT_ENABLE); + rt_sdhci_writel(host, host->ier, RT_SDHCI_SIGNAL_ENABLE); +} + +void rt_sdhci_set_uhs(struct rt_sdhci_host *host, unsigned timing) +{ + rt_uint16_t ctrl_2; + + ctrl_2 = rt_sdhci_readw(host, RT_SDHCI_HOST_CONTROL2); + + ctrl_2 &= ~RT_SDHCI_CTRL_UHS_MASK; + if ((timing == MMC_TIMING_MMC_HS200) || (timing == MMC_TIMING_UHS_SDR104)) + ctrl_2 |= RT_SDHCI_CTRL_UHS_SDR104; + else if (timing == MMC_TIMING_UHS_SDR12) + ctrl_2 |= RT_SDHCI_CTRL_UHS_SDR12; + else if (timing == MMC_TIMING_UHS_SDR25) + ctrl_2 |= RT_SDHCI_CTRL_UHS_SDR25; + else if (timing == MMC_TIMING_UHS_SDR50) + ctrl_2 |= RT_SDHCI_CTRL_UHS_SDR50; + else if ((timing == MMC_TIMING_UHS_DDR50) || (timing == MMC_TIMING_MMC_DDR52)) + ctrl_2 |= RT_SDHCI_CTRL_UHS_DDR50; + else if (timing == MMC_TIMING_MMC_HS400) + ctrl_2 |= RT_SDHCI_CTRL_HS400; /* Non-standard */ + rt_sdhci_writew(host, ctrl_2, RT_SDHCI_HOST_CONTROL2); +} + +void rt_sdhci_set_bus_width(struct rt_sdhci_host *host, int width) +{ + rt_uint8_t ctrl; + + ctrl = rt_sdhci_readb(host, RT_SDHCI_HOST_CONTROL); + if (width == MMC_BUS_WIDTH_8) + { + ctrl &= ~RT_SDHCI_CTRL_4BITBUS; + ctrl |= RT_SDHCI_CTRL_8BITBUS; + } + else + { + if (host->mmc->caps & MMC_CAP_8_BIT_DATA) + ctrl &= ~RT_SDHCI_CTRL_8BITBUS; + if (width == MMC_BUS_WIDTH_4) + ctrl |= RT_SDHCI_CTRL_4BITBUS; + else + ctrl &= ~RT_SDHCI_CTRL_4BITBUS; + } + rt_sdhci_writeb(host, ctrl, RT_SDHCI_HOST_CONTROL); +} + +static inline rt_bool_t sdhci_can_64bit_dma(struct rt_sdhci_host *host) +{ + if (host->version >= RT_SDHCI_SPEC_410 && host->v4_mode) + return host->caps & RT_SDHCI_CAN_64BIT_V4; + + return host->caps & RT_SDHCI_CAN_64BIT; +} + +static void sdhci_do_enable_v4_mode(struct rt_sdhci_host *host) +{ + rt_uint16_t ctrl2; + + ctrl2 = rt_sdhci_readw(host, RT_SDHCI_HOST_CONTROL2); + if (ctrl2 & RT_SDHCI_CTRL_V4_MODE) + return; + + ctrl2 |= RT_SDHCI_CTRL_V4_MODE; + rt_sdhci_writew(host, ctrl2, RT_SDHCI_HOST_CONTROL2); +} + +void rt_sdhci_cleanup_host(struct rt_sdhci_host *host) +{ + return; +} + +static void sdhci_set_default_irqs(struct rt_sdhci_host *host) +{ + host->ier = RT_SDHCI_INT_BUS_POWER | RT_SDHCI_INT_DATA_END_BIT | RT_SDHCI_INT_DATA_CRC | RT_SDHCI_INT_DATA_TIMEOUT | RT_SDHCI_INT_INDEX | RT_SDHCI_INT_END_BIT | RT_SDHCI_INT_CRC | RT_SDHCI_INT_TIMEOUT | RT_SDHCI_INT_DATA_END | RT_SDHCI_INT_RESPONSE; + + if (host->tuning_mode == RT_SDHCI_TUNING_MODE_2 || host->tuning_mode == RT_SDHCI_TUNING_MODE_3) + host->ier |= RT_SDHCI_INT_RETUNE; + + rt_sdhci_writel(host, host->ier, RT_SDHCI_INT_ENABLE); + rt_sdhci_writel(host, host->ier, RT_SDHCI_SIGNAL_ENABLE); +} + + +static inline void sdhci_auto_cmd_select(struct rt_sdhci_host *host, + struct rt_mmcsd_cmd *cmd, + rt_uint16_t *mode) +{ + rt_bool_t use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) && (cmd->cmd_code != SD_IO_RW_EXTENDED); + rt_bool_t use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq); + rt_uint16_t ctrl2; + + if (host->version >= RT_SDHCI_SPEC_410 && host->v4_mode && (use_cmd12 || use_cmd23)) + { + *mode |= RT_SDHCI_TRNS_AUTO_SEL; + + ctrl2 = rt_sdhci_readw(host, RT_SDHCI_HOST_CONTROL2); + if (use_cmd23) + ctrl2 |= RT_SDHCI_CMD23_ENABLE; + else + ctrl2 &= ~RT_SDHCI_CMD23_ENABLE; + rt_sdhci_writew(host, ctrl2, RT_SDHCI_HOST_CONTROL2); + + return; + } + + if (use_cmd12) + *mode |= RT_SDHCI_TRNS_AUTO_CMD12; + else if (use_cmd23) + *mode |= RT_SDHCI_TRNS_AUTO_CMD23; +} + + +static rt_bool_t sdhci_present_error(struct rt_sdhci_host *host, + struct rt_mmcsd_cmd *cmd, rt_bool_t present) +{ + if (!present || host->flags & RT_SDHCI_DEVICE_DEAD) + { + cmd->err = -ENOMEDIUM; + return RT_TRUE; + } + + return RT_FALSE; +} + +static rt_uint16_t sdhci_get_preset_value(struct rt_sdhci_host *host) +{ + rt_uint16_t preset = 0; + + switch (host->timing) + { + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + preset = rt_sdhci_readw(host, RT_SDHCI_PRESET_FOR_HIGH_SPEED); + break; + case MMC_TIMING_UHS_SDR12: + preset = rt_sdhci_readw(host, RT_SDHCI_PRESET_FOR_SDR12); + break; + case MMC_TIMING_UHS_SDR25: + preset = rt_sdhci_readw(host, RT_SDHCI_PRESET_FOR_SDR25); + break; + case MMC_TIMING_UHS_SDR50: + preset = rt_sdhci_readw(host, RT_SDHCI_PRESET_FOR_SDR50); + break; + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_MMC_HS200: + preset = rt_sdhci_readw(host, RT_SDHCI_PRESET_FOR_SDR104); + break; + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + preset = rt_sdhci_readw(host, RT_SDHCI_PRESET_FOR_DDR50); + break; + case MMC_TIMING_MMC_HS400: + preset = rt_sdhci_readw(host, RT_SDHCI_PRESET_FOR_HS400); + break; + default: + preset = rt_sdhci_readw(host, RT_SDHCI_PRESET_FOR_SDR12); + break; + } + return preset; +} + +static void sdhci_set_card_detection(struct rt_sdhci_host *host, rt_bool_t enable) +{ + rt_uint32_t present; + + if ((host->quirks & RT_SDHCI_QUIRK_BROKEN_CARD_DETECTION) || !mmc_card_is_removable(host->mmc)) + return; + + if (enable) + { + present = rt_sdhci_readl(host, RT_SDHCI_PRESENT_STATE) & RT_SDHCI_CARD_PRESENT; + + host->ier |= present ? RT_SDHCI_INT_CARD_REMOVE : RT_SDHCI_INT_CARD_INSERT; + } + else + { + host->ier &= ~(RT_SDHCI_INT_CARD_REMOVE | RT_SDHCI_INT_CARD_INSERT); + } + + rt_sdhci_writel(host, host->ier, RT_SDHCI_INT_ENABLE); + rt_sdhci_writel(host, host->ier, RT_SDHCI_SIGNAL_ENABLE); +} + +static void sdhci_enable_card_detection(struct rt_sdhci_host *host) +{ + sdhci_set_card_detection(host, RT_TRUE); +} + +/********************************************************* */ +/* reset */ +/********************************************************* */ +enum sdhci_reset_reason +{ + RT_SDHCI_RESET_FOR_INIT, + RT_SDHCI_RESET_FOR_REQUEST_ERROR, + RT_SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY, + RT_SDHCI_RESET_FOR_TUNING_ABORT, + RT_SDHCI_RESET_FOR_CARD_REMOVED, + RT_SDHCI_RESET_FOR_CQE_RECOVERY, +}; + +static rt_bool_t sdhci_needs_reset(struct rt_sdhci_host *host, struct rt_mmcsd_req *mrq) +{ + return (!(host->flags & RT_SDHCI_DEVICE_DEAD) && ((mrq->cmd && mrq->cmd->err) || (mrq->sbc && mrq->sbc->err) || (mrq->data && mrq->data->stop && mrq->data->stop->err) || (host->quirks & RT_SDHCI_QUIRK_RESET_AFTER_REQUEST))); +} + +static rt_bool_t sdhci_do_reset(struct rt_sdhci_host *host, rt_uint8_t mask) +{ + if (host->quirks & RT_SDHCI_QUIRK_NO_CARD_NO_RESET) + { + struct rt_mmc_host *mmc = host->mmc; + + if (!mmc->ops->get_cd(mmc)) + return RT_FALSE; + } + if (host->ops->reset) + { + host->ops->reset(host, mask); + } + return RT_TRUE; +} + +static void sdhci_reset_for_reason(struct rt_sdhci_host *host, enum sdhci_reset_reason reason) +{ + if (host->quirks2 & RT_SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) + { + sdhci_do_reset(host, RT_SDHCI_RESET_CMD | RT_SDHCI_RESET_DATA); + return; + } + + switch (reason) + { + case RT_SDHCI_RESET_FOR_INIT: + sdhci_do_reset(host, RT_SDHCI_RESET_CMD | RT_SDHCI_RESET_DATA); + break; + case RT_SDHCI_RESET_FOR_REQUEST_ERROR: + case RT_SDHCI_RESET_FOR_TUNING_ABORT: + case RT_SDHCI_RESET_FOR_CARD_REMOVED: + case RT_SDHCI_RESET_FOR_CQE_RECOVERY: + sdhci_do_reset(host, RT_SDHCI_RESET_CMD); + sdhci_do_reset(host, RT_SDHCI_RESET_DATA); + break; + case RT_SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY: + sdhci_do_reset(host, RT_SDHCI_RESET_DATA); + break; + } +} + +#define sdhci_reset_for(h, r) sdhci_reset_for_reason((h), RT_SDHCI_RESET_FOR_##r) + +static void sdhci_reset_for_all(struct rt_sdhci_host *host) +{ + if (sdhci_do_reset(host, RT_SDHCI_RESET_ALL)) + { + if (host->flags & (RT_SDHCI_USE_SDMA)) + { + if (host->ops->enable_dma) + host->ops->enable_dma(host); + } + host->preset_enabled = RT_FALSE; + } +} + + +static void sdhci_runtime_pm_bus_on(struct rt_sdhci_host *host) +{ + if (host->bus_on) + return; + host->bus_on = RT_TRUE; +} + +static void sdhci_runtime_pm_bus_off(struct rt_sdhci_host *host) +{ + if (!host->bus_on) + return; + host->bus_on = RT_FALSE; +} + +void rt_sdhci_reset(struct rt_sdhci_host *host, rt_uint8_t mask) +{ + ssize_t timeout; + + rt_sdhci_writeb(host, mask, RT_SDHCI_SOFTWARE_RESET); + + if (mask & RT_SDHCI_RESET_ALL) + { + host->clock = 0; + if (host->quirks2 & RT_SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) + sdhci_runtime_pm_bus_off(host); + } + + timeout = rt_tick_from_millisecond(150); + while (1) + { + timeout = timeout - rt_tick_get(); + + + if (!(rt_sdhci_readb(host, RT_SDHCI_SOFTWARE_RESET) & mask)) + break; + if (timeout < 0) + { + rt_kprintf("%s: Reset 0x%x never completed.\n", + mmc_hostname(host->mmc), (int)mask); + rt_read_reg_debug(host); + return; + } + rt_hw_us_delay(10); + } +} + +/********************************************************* */ +/* data */ +/********************************************************* */ +static rt_ubase_t sdhci_sdma_address(struct rt_sdhci_host *host) +{ + return (rt_ubase_t)rt_kmem_v2p(host->data->buf); +} + +static void sdhci_set_adma_addr(struct rt_sdhci_host *host, rt_uint32_t addr) +{ + rt_sdhci_writel(host, lower_32_bits(addr), RT_SDHCI_ADMA_ADDRESS); + if (host->flags & RT_SDHCI_USE_64_BIT_DMA) + rt_sdhci_writel(host, upper_32_bits(addr), RT_SDHCI_ADMA_ADDRESS_HI); +} + +static void sdhci_set_sdma_addr(struct rt_sdhci_host *host, rt_uint32_t addr) +{ + if (host->v4_mode) + sdhci_set_adma_addr(host, addr); + else + rt_sdhci_writel(host, addr, RT_SDHCI_DMA_ADDRESS); +} + +static void sdhci_config_dma(struct rt_sdhci_host *host) +{ + rt_uint8_t ctrl; + rt_uint16_t ctrl2; + + if (host->version < RT_SDHCI_SPEC_200) + return; + + ctrl = rt_sdhci_readb(host, RT_SDHCI_HOST_CONTROL); + + ctrl &= ~RT_SDHCI_CTRL_DMA_MASK; + if (!(host->flags & RT_SDHCI_REQ_USE_DMA)) + goto out; + + /* Note if DMA Select is zero then SDMA is selected */ + if (host->flags & RT_SDHCI_USE_64_BIT_DMA) + { + + if (host->v4_mode) + { + ctrl2 = rt_sdhci_readw(host, RT_SDHCI_HOST_CONTROL2); + ctrl2 |= RT_SDHCI_CTRL_64BIT_ADDR; + rt_sdhci_writew(host, ctrl2, RT_SDHCI_HOST_CONTROL2); + } + } + +out: + rt_sdhci_writeb(host, ctrl, RT_SDHCI_HOST_CONTROL); +} + +static inline void sdhci_set_block_info(struct rt_sdhci_host *host, + struct rt_mmcsd_data *data) +{ + int boundary; + size_t total_size = data->blks * data->blksize; + + if (total_size <= 512) + boundary = 0; /* 4k bytes*/ + else if (total_size <= 1024) + boundary = 1; /* 8 KB*/ + else if (total_size <= 2048) + boundary = 2; /* 16 KB*/ + else if (total_size <= 4096) + boundary = 3; /* 32 KB*/ + else if (total_size <= 8192) + boundary = 4; /* 64 KB*/ + else if (total_size <= 16384) + boundary = 5; /* 128 KB*/ + else if (total_size <= 32768) + boundary = 6; /* 256 KB*/ + else + boundary = 7; /* 512 KB*/ + rt_sdhci_writew(host, + RT_SDHCI_MAKE_BLKSZ(boundary, data->blksize), + RT_SDHCI_BLOCK_SIZE); + + if (host->version >= RT_SDHCI_SPEC_410 && host->v4_mode && (host->quirks2 & RT_SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) + { + if (rt_sdhci_readw(host, RT_SDHCI_BLOCK_COUNT)) + rt_sdhci_writew(host, 0, RT_SDHCI_BLOCK_COUNT); + rt_sdhci_writew(host, data->blks, RT_SDHCI_32BIT_BLK_CNT); + } + else + { + rt_sdhci_writew(host, data->blks, RT_SDHCI_BLOCK_COUNT); + } +} + +static void sdhci_set_transfer_irqs(struct rt_sdhci_host *host) +{ + rt_uint32_t pio_irqs = RT_SDHCI_INT_DATA_AVAIL | RT_SDHCI_INT_SPACE_AVAIL; + rt_uint32_t dma_irqs = RT_SDHCI_INT_DMA_END; + + if (host->flags & RT_SDHCI_REQ_USE_DMA) + host->ier = (host->ier & ~pio_irqs) | dma_irqs; + else + host->ier = (host->ier & ~dma_irqs) | pio_irqs; + + if (host->flags & (RT_SDHCI_AUTO_CMD23 | RT_SDHCI_AUTO_CMD12)) + host->ier |= RT_SDHCI_INT_AUTO_CMD_ERR; + else + host->ier &= ~RT_SDHCI_INT_AUTO_CMD_ERR; + rt_sdhci_writel(host, host->ier, RT_SDHCI_INT_ENABLE); + rt_sdhci_writel(host, host->ier, RT_SDHCI_SIGNAL_ENABLE); +} + +static void sdhci_prepare_data(struct rt_sdhci_host *host, struct rt_mmcsd_cmd *cmd) +{ + struct rt_mmcsd_data *data = cmd->data; + + LOG_D(data->blksize * data->blks > 524288); + LOG_D(data->blksize > host->mmc->max_blk_size); + LOG_D(data->blks > 65535); + + host->data = data; + host->data_early = 0; + host->data->bytes_xfered = 0; + + if (host->flags & RT_SDHCI_USE_SDMA) + { + unsigned int length_mask, offset_mask; + + host->flags |= RT_SDHCI_REQ_USE_DMA; + + length_mask = 0; + offset_mask = 0; + if (host->quirks & RT_SDHCI_QUIRK_32BIT_DMA_SIZE) + length_mask = 3; + if (host->quirks & RT_SDHCI_QUIRK_32BIT_DMA_ADDR) + offset_mask = 3; + + if ((data->blks * data->blksize) & length_mask) + { + host->flags &= ~RT_SDHCI_REQ_USE_DMA; + } + else if ((rt_ubase_t)rt_kmem_v2p(data->buf) & offset_mask) + { + host->flags &= ~RT_SDHCI_REQ_USE_DMA; + } + } + + sdhci_config_dma(host); + + if (host->flags & RT_SDHCI_REQ_USE_DMA) + { + if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, data->buf, data->blks * data->blksize); + else + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, data->buf, data->blks * data->blksize); + + sdhci_set_sdma_addr(host, sdhci_sdma_address(host)); + } + + if (!(host->flags & RT_SDHCI_REQ_USE_DMA)) + { + host->blocks = data->blks; + } + + sdhci_set_transfer_irqs(host); + + sdhci_set_block_info(host, data); +} + +static void sdhci_set_mrq_done(struct rt_sdhci_host *host, struct rt_mmcsd_req *mrq) +{ + int i; + + for (i = 0; i < RT_SDHCI_MAX_MRQS; i++) + { + if (host->mrqs_done[i] == mrq) + { + LOG_D(1); + return; + } + } + + for (i = 0; i < RT_SDHCI_MAX_MRQS; i++) + { + if (!host->mrqs_done[i]) + { + host->mrqs_done[i] = mrq; + break; + } + } + + LOG_D(i >= RT_SDHCI_MAX_MRQS); +} + +static inline rt_bool_t sdhci_defer_done(struct rt_sdhci_host *host, + struct rt_mmcsd_req *mrq) +{ + struct rt_mmcsd_data *data = mrq->data; + + return host->pending_reset || host->always_defer_done || ((host->flags & RT_SDHCI_REQ_USE_DMA) && data && data->host_cookie == COOKIE_MAPPED); +} + + +/********************************************************* */ +/* pio */ +/********************************************************* */ + +static void rt_sdhci_read_block_pio(struct rt_sdhci_host *host,void **buf) +{ + rt_uint32_t scratch; + size_t len; + + rt_uint32_t blksize = host->data->blksize; + while (blksize) + { + len = min(4U, blksize); + + scratch = rt_sdhci_readl(host, RT_SDHCI_BUFFER); + rt_memcpy(*buf, &scratch, len); + + *buf += len; + blksize -= len; + } +} + +static void rt_sdhci_write_block_pio(struct rt_sdhci_host *host,void **buf) +{ + size_t blksize, len; + rt_uint32_t scratch; + LOG_D("PIO writing\n"); + + blksize = host->data->blksize; + scratch = 0; + + while (blksize) + { + len = min(4U, blksize); + rt_memcpy(&scratch, *buf, len); + *buf += len; + blksize -= len; + rt_sdhci_writel(host, scratch, RT_SDHCI_BUFFER); + } +} + +static void sdhci_transfer_pio(struct rt_sdhci_host *host) +{ + rt_uint32_t mask; + + if (host->blocks == 0) + return; + + if (host->data->flags & DATA_DIR_READ) + mask = RT_SDHCI_DATA_AVAILABLE; + else + mask = RT_SDHCI_SPACE_AVAILABLE; + + if ((host->quirks & RT_SDHCI_QUIRK_BROKEN_SMALL_PIO) && (host->data->blks == 1)) + { + mask = ~0; + } + void *buf = (void *)host->data->buf; + while (rt_sdhci_readl(host, RT_SDHCI_PRESENT_STATE) & mask) + { + if (host->quirks & RT_SDHCI_QUIRK_PIO_NEEDS_DELAY) + rt_hw_us_delay(100); + + if (host->data->flags & DATA_DIR_READ) + rt_sdhci_read_block_pio(host,&buf); + else + rt_sdhci_write_block_pio(host,&buf); + + host->data->blks--; + if (host->data->blks == 0) + break; + } +} + +/********************************************************* */ +/* config */ +/********************************************************* */ + + +static rt_bool_t sdhci_timing_has_preset(unsigned char timing) +{ + switch (timing) + { + case MMC_TIMING_UHS_SDR12: + case MMC_TIMING_UHS_SDR25: + case MMC_TIMING_UHS_SDR50: + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + return RT_TRUE; + } + return RT_FALSE; +} + +static rt_bool_t sdhci_preset_needed(struct rt_sdhci_host *host, unsigned char timing) +{ + return !(host->quirks2 & RT_SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && sdhci_timing_has_preset(timing); +} + +static rt_bool_t sdhci_presetable_values_change(struct rt_sdhci_host *host, struct rt_mmcsd_io_cfg *ios) +{ + return !host->preset_enabled && (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type); +} + + +static void sdhci_preset_value_enable(struct rt_sdhci_host *host, rt_bool_t enable) +{ + if (host->version < RT_SDHCI_SPEC_300) + return; + + if (host->preset_enabled != enable) + { + rt_uint16_t ctrl = rt_sdhci_readw(host, RT_SDHCI_HOST_CONTROL2); + + if (enable) + ctrl |= RT_SDHCI_CTRL_PRESET_VAL_ENABLE; + else + ctrl &= ~RT_SDHCI_CTRL_PRESET_VAL_ENABLE; + + rt_sdhci_writew(host, ctrl, RT_SDHCI_HOST_CONTROL2); + + if (enable) + host->flags |= RT_SDHCI_PV_ENABLED; + else + host->flags &= ~RT_SDHCI_PV_ENABLED; + + host->preset_enabled = enable; + } +} + +static void sdhci_set_power_reg(struct rt_sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + struct rt_mmc_host *mmc = host->mmc; + + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); + + if (mode != MMC_POWER_OFF) + rt_sdhci_writeb(host, RT_SDHCI_POWER_ON, RT_SDHCI_POWER_CONTROL); + else + rt_sdhci_writeb(host, 0, RT_SDHCI_POWER_CONTROL); +} + +void rt_sdhci_set_power_with_noreg(struct rt_sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + rt_uint8_t pwr = 0; + + if (mode != MMC_POWER_OFF) + { + switch (1 << vdd) + { + case MMC_VDD_165_195: + case MMC_VDD_20_21: + pwr = RT_SDHCI_POWER_180; + break; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + pwr = RT_SDHCI_POWER_300; + break; + case MMC_VDD_32_33: + case MMC_VDD_33_34: + case MMC_VDD_34_35: + case MMC_VDD_35_36: + pwr = RT_SDHCI_POWER_330; + break; + default: + break; + } + } + + if (host->pwr == pwr) + return; + + host->pwr = pwr; + + if (pwr == 0) + { + rt_sdhci_writeb(host, 0, RT_SDHCI_POWER_CONTROL); + if (host->quirks2 & RT_SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) + sdhci_runtime_pm_bus_off(host); + } + else + { + if (!(host->quirks & RT_SDHCI_QUIRK_SINGLE_POWER_WRITE)) + rt_sdhci_writeb(host, 0, RT_SDHCI_POWER_CONTROL); + + if (host->quirks & RT_SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) + rt_sdhci_writeb(host, pwr, RT_SDHCI_POWER_CONTROL); + + pwr |= RT_SDHCI_POWER_ON; + + rt_sdhci_writeb(host, pwr, RT_SDHCI_POWER_CONTROL); + + if (host->quirks2 & RT_SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) + sdhci_runtime_pm_bus_on(host); + + if (host->quirks & RT_SDHCI_QUIRK_DELAY_AFTER_POWER) + rt_thread_mdelay(10); + } +} + +void rt_sdhci_set_power(struct rt_sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + if (!host->mmc->supply.vmmc) + rt_sdhci_set_power_with_noreg(host, mode, vdd); + else + sdhci_set_power_reg(host, mode, vdd); +} + + +int rt_sdhci_start_signal_voltage_switch(struct rt_mmc_host *mmc, + struct rt_mmcsd_io_cfg *ios) +{ + struct rt_sdhci_host *host = mmc_priv(mmc); + rt_uint16_t ctrl; + int ret; + + if (host->version < RT_SDHCI_SPEC_300) + return 0; + + ctrl = rt_sdhci_readw(host, RT_SDHCI_HOST_CONTROL2); + + switch (ios->signal_voltage) + { + case MMC_SIGNAL_VOLTAGE_330: + if (!(host->flags & RT_SDHCI_SIGNALING_330)) + return -EINVAL; + ctrl &= ~RT_SDHCI_CTRL_VDD_180; + rt_sdhci_writew(host, ctrl, RT_SDHCI_HOST_CONTROL2); + + if (!mmc->supply.vqmmc) + { + ret = rt_mmc_regulator_set_vqmmc(mmc, ios); + if (ret < 0) + { + return -EIO; + } + } + rt_thread_mdelay(5); + + ctrl = rt_sdhci_readw(host, RT_SDHCI_HOST_CONTROL2); + if (!(ctrl & RT_SDHCI_CTRL_VDD_180)) + return 0; + return -EAGAIN; + case MMC_SIGNAL_VOLTAGE_180: + if (!(host->flags & RT_SDHCI_SIGNALING_180)) + return -EINVAL; + if (!mmc->supply.vqmmc) + { + ret = rt_mmc_regulator_set_vqmmc(mmc, ios); + if (ret < 0) + { + LOG_D("%s: Switching to 1.8V signalling voltage failed\n", + mmc_hostname(mmc)); + return -EIO; + } + } + + ctrl |= RT_SDHCI_CTRL_VDD_180; + rt_sdhci_writew(host, ctrl, RT_SDHCI_HOST_CONTROL2); + + if (host->ops->voltage_switch) + host->ops->voltage_switch(host); + + ctrl = rt_sdhci_readw(host, RT_SDHCI_HOST_CONTROL2); + if (ctrl & RT_SDHCI_CTRL_VDD_180) + return 0; + + LOG_D("%s: 1.8V regulator output did not become stable\n", + mmc_hostname(mmc)); + + return -EAGAIN; + case MMC_SIGNAL_VOLTAGE_120: + if (!(host->flags & RT_SDHCI_SIGNALING_120)) + return -EINVAL; + if (!mmc->supply.vqmmc) + { + ret = rt_mmc_regulator_set_vqmmc(mmc, ios); + if (ret < 0) + { + LOG_D("%s: Switching to 1.2V signalling voltage failed\n", + mmc_hostname(mmc)); + return -EIO; + } + } + return 0; + default: + return 0; + } +} + + +static int sdhci_get_cd(struct rt_mmc_host *mmc) +{ + struct rt_sdhci_host *host = mmc_priv(mmc); + int gpio_cd = rt_mmc_gpio_get_cd(mmc); + + if (host->flags & RT_SDHCI_DEVICE_DEAD) + return 0; + + if (!mmc_card_is_removable(mmc)) + return 1; + + if (gpio_cd >= 0) + return !!gpio_cd; + + if (host->quirks & RT_SDHCI_QUIRK_BROKEN_CARD_DETECTION) + return 1; + + return !!(rt_sdhci_readl(host, RT_SDHCI_PRESENT_STATE) & RT_SDHCI_CARD_PRESENT); +} + +static int sdhci_check_ro(struct rt_sdhci_host *host) +{ + int is_readonly; + rt_base_t flags; + flags = rt_spin_lock_irqsave(&host->lock); + + if (host->flags & RT_SDHCI_DEVICE_DEAD) + is_readonly = 0; + else if (host->ops->get_ro) + is_readonly = host->ops->get_ro(host); + else if (rt_mmc_can_gpio_ro(host->mmc)) + is_readonly = rt_mmc_gpio_get_ro(host->mmc); + else + is_readonly = !(rt_sdhci_readl(host, RT_SDHCI_PRESENT_STATE) + & RT_SDHCI_WRITE_PROTECT); + + rt_spin_unlock_irqrestore(&host->lock, flags); + + return host->quirks & RT_SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? !is_readonly : is_readonly; +} + +#define SAMPLE_COUNT 5 +static int rt_sdhci_ro_get(struct rt_mmc_host *mmc) +{ + struct rt_sdhci_host *host = mmc_priv(mmc); + int i, ro_count; + + if (!(host->quirks & RT_SDHCI_QUIRK_UNSTABLE_RO_DETECT)) + return sdhci_check_ro(host); + + ro_count = 0; + for (i = 0; i < SAMPLE_COUNT; i++) + { + if (sdhci_check_ro(host)) + { + if (++ro_count > SAMPLE_COUNT / 2) + return 1; + } + rt_thread_mdelay(30); + } + return 0; +} + +static void rt_sdhci_enable_io_irq_nolock(struct rt_sdhci_host *host, int enable) +{ + if (!(host->flags & RT_SDHCI_DEVICE_DEAD)) + { + if (enable) + host->ier |= RT_SDHCI_INT_CARD_INT; + else + host->ier &= ~RT_SDHCI_INT_CARD_INT; + + rt_sdhci_writel(host, host->ier, RT_SDHCI_INT_ENABLE); + rt_sdhci_writel(host, host->ier, RT_SDHCI_SIGNAL_ENABLE); + } +} + +static void sdhci_ack_sdio_irq(struct rt_mmc_host *mmc) +{ + rt_base_t flags; + struct rt_sdhci_host *host = mmc_priv(mmc); + flags = rt_spin_lock_irqsave(&host->lock); + rt_sdhci_enable_io_irq_nolock(host, RT_TRUE); + rt_spin_unlock_irqrestore(&host->lock, flags); +} + +static void sdhci_del_timer(struct rt_sdhci_host *host, struct rt_mmcsd_req *mrq) +{ + if (sdhci_data_line_cmd(mrq->cmd)) + rt_timer_stop(&host->data_timer); + else + rt_timer_stop(&host->timer); +} + +static unsigned int sdhci_target_timeout(struct rt_sdhci_host *host, + struct rt_mmcsd_cmd *cmd, + struct rt_mmcsd_data *data) +{ + unsigned int target_timeout; + + if (!data) + { + target_timeout = cmd->busy_timeout * 1000; + } + else + { + target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); + if (host->clock && data->timeout_clks) + { + rt_uint32_t val; + + val = 1000000ULL * data->timeout_clks; + if (do_div(val, host->clock)) + target_timeout++; + target_timeout += val; + } + } + + return target_timeout; +} + +static rt_uint8_t sdhci_calc_timeout(struct rt_sdhci_host *host, struct rt_mmcsd_cmd *cmd, + rt_bool_t *too_big) +{ + rt_uint8_t count; + struct rt_mmcsd_data *data; + unsigned target_timeout, current_timeout; + + *too_big = RT_FALSE; + + if (host->quirks & RT_SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) + return host->max_timeout_count; + + if (cmd == NULL) + return host->max_timeout_count; + + data = cmd->data; + if (!data && !cmd->busy_timeout) + return host->max_timeout_count; + + target_timeout = sdhci_target_timeout(host, cmd, data); + + count = 0; + current_timeout = (1 << 13) * 1000 / host->timeout_clk; + while (current_timeout < target_timeout) + { + count++; + current_timeout <<= 1; + if (count > host->max_timeout_count) + { + if (!(host->quirks2 & RT_SDHCI_QUIRK2_DISABLE_HW_TIMEOUT)) + LOG_D("Too large timeout 0x%x requested for CMD%d!\n", + count, cmd->cmd_code); + count = host->max_timeout_count; + *too_big = RT_TRUE; + break; + } + } + + return count; +} + +static void sdhci_calc_sw_timeout(struct rt_sdhci_host *host, + struct rt_mmcsd_cmd *cmd) +{ + struct rt_mmcsd_data *data = cmd->data; + struct rt_mmc_host *mmc = host->mmc; + struct rt_mmcsd_io_cfg *ios = &mmc->ios; + unsigned char bus_width = 1 << ios->bus_width; + unsigned int blksz; + unsigned int freq; + rt_uint64_t target_timeout; + rt_uint64_t transfer_time; + + target_timeout = sdhci_target_timeout(host, cmd, data); + target_timeout *= 1000L; + + if (data) + { + blksz = data->blksize; + freq = mmc->actual_clock ?: host->clock; + transfer_time = (rt_uint64_t)blksz * 1000000000L * (8 / bus_width); + do_div(transfer_time, freq); + transfer_time = transfer_time * 2; + host->data_timeout = data->blks * target_timeout + transfer_time; + } + else + { + host->data_timeout = target_timeout; + } + + if (host->data_timeout) + host->data_timeout += MMC_CMD_TRANSFER_TIME; +} + + +void rt_sdhci_timeout_set(struct rt_sdhci_host *host, struct rt_mmcsd_cmd *cmd) +{ + rt_bool_t too_big = RT_FALSE; + rt_uint8_t count = sdhci_calc_timeout(host, cmd, &too_big); + + if (too_big && host->quirks2 & RT_SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) + { + sdhci_calc_sw_timeout(host, cmd); + rt_sdhci_data_irq_timeout(host, RT_FALSE); + } + else if (!(host->ier & RT_SDHCI_INT_DATA_TIMEOUT)) + { + rt_sdhci_data_irq_timeout(host, RT_FALSE); + } + + rt_sdhci_writeb(host, count, RT_SDHCI_TIMEOUT_CONTROL); +} + +static void sdhci_set_timeout(struct rt_sdhci_host *host, struct rt_mmcsd_cmd *cmd) +{ + if (host->ops->set_timeout) + host->ops->set_timeout(host, cmd); + else + rt_sdhci_timeout_set(host, cmd); +} + +static void sdhci_start_timer(struct rt_sdhci_host *host, struct rt_mmcsd_req *mrq, + unsigned long timeout) +{ + if (sdhci_data_line_cmd(mrq->cmd)) + { + rt_tick_t tick = rt_tick_get(); + + if (timeout < tick) + { + timeout = tick; + } + tick = timeout - tick; + + rt_timer_stop(&host->data_timer); + rt_timer_control(&host->data_timer, RT_TIMER_CTRL_SET_TIME, &tick); + rt_timer_start(&host->data_timer); + } + else + { + rt_tick_t tick = rt_tick_get(); + + if (timeout < tick) + { + timeout = tick; + } + tick = timeout - tick; + + rt_timer_stop(&host->timer); + rt_timer_control(&host->timer, RT_TIMER_CTRL_SET_TIME, &tick); + rt_timer_start(&host->timer); + } +} + +static void __sdhci_finish_mrq(struct rt_sdhci_host *host, struct rt_mmcsd_req *mrq) +{ + if (host->cmd && host->cmd->mrq == mrq) + host->cmd = NULL; + + if (host->data_cmd && host->data_cmd->mrq == mrq) + host->data_cmd = NULL; + + if (host->deferred_cmd && host->deferred_cmd->mrq == mrq) + host->deferred_cmd = NULL; + + if (host->data && host->data->mrq == mrq) + host->data = NULL; + + if (sdhci_needs_reset(host, mrq)) + host->pending_reset = RT_TRUE; + + sdhci_set_mrq_done(host, mrq); + + sdhci_del_timer(host, mrq); +} + +static void sdhci_finish_mrq(struct rt_sdhci_host *host, struct rt_mmcsd_req *mrq) +{ + __sdhci_finish_mrq(host, mrq); + + rt_workqueue_submit_work(host->complete_wq, &host->complete_work, 0); +} + +static void sdhci_error_out_mrqs(struct rt_sdhci_host *host, int err) +{ + if (host->data_cmd) + { + host->data_cmd->err = err; + sdhci_finish_mrq(host, host->data_cmd->mrq); + } + + if (host->cmd) + { + host->cmd->err = err; + sdhci_finish_mrq(host, host->cmd->mrq); + } +} + +static void sdhci_card_event(struct rt_mmc_host *mmc) +{ + struct rt_sdhci_host *host = mmc_priv(mmc); + rt_uint32_t flags; + int present; + + if (host->ops->card_event) + host->ops->card_event(host); + + present = mmc->ops->get_cd(mmc); + + flags = rt_spin_lock_irqsave(&host->lock); + + if (sdhci_has_requests(host) && !present) + { + rt_kprintf("%s: Card removed during transfer!\n", + mmc_hostname(mmc)); + rt_kprintf("%s: Resetting controller.\n", + mmc_hostname(mmc)); + + sdhci_do_reset(host, RT_SDHCI_RESET_CMD); + sdhci_do_reset(host, RT_SDHCI_RESET_DATA); + sdhci_error_out_mrqs(host, -ENOMEDIUM); + } + + rt_spin_unlock_irqrestore(&host->lock, flags); +} + +static int sdhci_card_busy(struct rt_mmc_host *mmc) +{ + struct rt_sdhci_host *host = mmc_priv(mmc); + rt_uint32_t present_state; + + present_state = rt_sdhci_readl(host, RT_SDHCI_PRESENT_STATE); + + return !(present_state & RT_SDHCI_DATA_0_LVL_MASK); +} + + +static int sdhci_prepare_hs400_tuning(struct rt_mmc_host *mmc, struct rt_mmcsd_io_cfg *ios) +{ + struct rt_sdhci_host *host = mmc_priv(mmc); + rt_uint32_t flags; + + flags = rt_spin_lock_irqsave(&host->lock); + host->flags |= RT_SDHCI_HS400_TUNING; + rt_spin_unlock_irqrestore(&host->lock, flags); + + return 0; +} + + +static void sdhci_set_transfer_mode(struct rt_sdhci_host *host, + struct rt_mmcsd_cmd *cmd) +{ + rt_uint16_t mode = 0; + struct rt_mmcsd_data *data = cmd->data; + + if (data == NULL) + { + if (host->quirks2 & RT_SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) + { + if (!mmc_op_tuning(cmd->cmd_code)) + rt_sdhci_writew(host, 0x0, RT_SDHCI_TRANSFER_MODE); + } + else + { + mode = rt_sdhci_readw(host, RT_SDHCI_TRANSFER_MODE); + rt_sdhci_writew(host, mode & ~(RT_SDHCI_TRNS_AUTO_CMD12 | RT_SDHCI_TRNS_AUTO_CMD23), RT_SDHCI_TRANSFER_MODE); + } + return; + } + + if (!(host->quirks2 & RT_SDHCI_QUIRK2_SUPPORT_SINGLE)) + mode = RT_SDHCI_TRNS_BLK_CNT_EN; + + if (mmc_op_multi(cmd->cmd_code) || data->blks > 1) + { + mode = RT_SDHCI_TRNS_BLK_CNT_EN | RT_SDHCI_TRNS_MULTI; + sdhci_auto_cmd_select(host, cmd, &mode); + if (sdhci_auto_cmd23(host, cmd->mrq)) + rt_sdhci_writel(host, cmd->mrq->sbc->arg, RT_SDHCI_ARGUMENT2); + } + + if (data->flags & DATA_DIR_READ) + mode |= RT_SDHCI_TRNS_READ; + if (host->flags & RT_SDHCI_REQ_USE_DMA) + mode |= RT_SDHCI_TRNS_DMA; + + rt_sdhci_writew(host, mode, RT_SDHCI_TRANSFER_MODE); +} + +static rt_bool_t sdhci_send_command(struct rt_sdhci_host *host, struct rt_mmcsd_cmd *cmd) +{ + int flags; + rt_uint32_t mask; + unsigned long timeout; + cmd->err = 0; + + if ((host->quirks2 & RT_SDHCI_QUIRK2_STOP_WITH_TC) && cmd->cmd_code == MMC_STOP_TRANSMISSION) + cmd->flags |= MMC_RSP_BUSY; + + mask = RT_SDHCI_CMD_INHIBIT; + if (sdhci_data_line_cmd(cmd)) + mask |= RT_SDHCI_DATA_INHIBIT; + + if (cmd->mrq->data && (cmd == cmd->mrq->data->stop)) + mask &= ~RT_SDHCI_DATA_INHIBIT; + + if (rt_sdhci_readl(host, RT_SDHCI_PRESENT_STATE) & mask) + return RT_FALSE; + + host->cmd = cmd; + host->data_timeout = 0; + if (sdhci_data_line_cmd(cmd)) + { + host->data_cmd = cmd; + sdhci_set_timeout(host, cmd); + } + + if (cmd->data) + { + sdhci_prepare_data(host, cmd); + } + rt_sdhci_writel(host, cmd->arg, RT_SDHCI_ARGUMENT); + + sdhci_set_transfer_mode(host, cmd); + + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) + { + cmd->flags &= ~MMC_RSP_BUSY; + } + + if (!(cmd->flags & MMC_RSP_PRESENT)) + flags = RT_SDHCI_CMD_RESP_NONE; + else if (cmd->flags & MMC_RSP_136) + flags = RT_SDHCI_CMD_RESP_LONG; + else if (cmd->flags & MMC_RSP_BUSY) + flags = RT_SDHCI_CMD_RESP_SHORT_BUSY; + else + flags = RT_SDHCI_CMD_RESP_SHORT; + + if (cmd->flags & MMC_RSP_CRC) + flags |= RT_SDHCI_CMD_CRC; + if (cmd->flags & MMC_RSP_OPCODE) + flags |= RT_SDHCI_CMD_INDEX; + + if (cmd->data || mmc_op_tuning(cmd->cmd_code)) + flags |= RT_SDHCI_CMD_DATA; + + timeout = rt_tick_get(); + if (host->data_timeout) + timeout += rt_tick_from_millisecond(host->data_timeout * 1000); + else if (!cmd->data && cmd->busy_timeout > 9000) + timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * RT_TICK_PER_SECOND + RT_TICK_PER_SECOND; + else + timeout += 10 * RT_TICK_PER_SECOND; + sdhci_start_timer(host, cmd->mrq, timeout); + + rt_sdhci_writew(host, RT_SDHCI_MAKE_CMD(cmd->cmd_code, flags), RT_SDHCI_COMMAND); + return RT_TRUE; +} + +/********************************************************* */ +/* dma */ +/********************************************************* */ +static void __sdhci_finish_data(struct rt_sdhci_host *host, rt_bool_t sw_data_timeout) +{ + struct rt_mmcsd_cmd *data_cmd = host->data_cmd; + struct rt_mmcsd_data *data = host->data; + + host->data = NULL; + host->data_cmd = NULL; + + if (data->err) + { + if (!host->cmd || host->cmd == data_cmd) + sdhci_reset_for(host, REQUEST_ERROR); + else + sdhci_reset_for(host, REQUEST_ERROR_DATA_ONLY); + } + + if (data->err) + { + data->bytes_xfered = 0; + } + else + { + data->bytes_xfered = data->blksize * data->blks; + } + + if (data->stop && ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) || data->err)) + { + if (data->mrq->cap_cmd_during_tfr) + { + __sdhci_finish_mrq(host, data->mrq); + } + else + { + host->cmd = NULL; + if (!sdhci_send_command(host, data->stop)) + { + if (sw_data_timeout) + { + data->stop->err = -EIO; + __sdhci_finish_mrq(host, data->mrq); + } + else + { + host->deferred_cmd = data->stop; + } + } + } + } + else + { + __sdhci_finish_mrq(host, data->mrq); + } +} + +static void sdhci_finish_data(struct rt_sdhci_host *host) +{ + __sdhci_finish_data(host, RT_FALSE); +} + + +/********************************************************* */ +/* irq */ +/********************************************************* */ +static void sdhci_data_irq(struct rt_sdhci_host *host, rt_uint32_t intmask) +{ + rt_uint32_t command; + + if (intmask & RT_SDHCI_INT_DATA_AVAIL && !host->data) + { + command = RT_SDHCI_GET_CMD(rt_sdhci_readw(host, RT_SDHCI_COMMAND)); + if (command == MMC_SEND_TUNING_BLOCK || command == MMC_SEND_TUNING_BLOCK_HS200) + { + host->tuning_done = 1; + rt_wqueue_wakeup(&host->buf_ready_int, 0); + return; + } + } + + if (!host->data) + { + struct rt_mmcsd_cmd *data_cmd = host->data_cmd; + + if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) + { + if (intmask & RT_SDHCI_INT_DATA_TIMEOUT) + { + host->data_cmd = NULL; + data_cmd->err = -ETIMEDOUT; + __sdhci_finish_mrq(host, data_cmd->mrq); + return; + } + if (intmask & RT_SDHCI_INT_DATA_END) + { + host->data_cmd = NULL; + + if (host->cmd == data_cmd) + return; + + __sdhci_finish_mrq(host, data_cmd->mrq); + return; + } + } + + + if (host->pending_reset) + return; + rt_kprintf("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", + mmc_hostname(host->mmc), (unsigned)intmask); + rt_read_reg_debug(host); + + return; + } + + if (intmask & RT_SDHCI_INT_DATA_TIMEOUT) + host->data->err = -ETIMEDOUT; + else if (intmask & RT_SDHCI_INT_DATA_END_BIT) + host->data->err = -EILSEQ; + else if ((intmask & RT_SDHCI_INT_DATA_CRC) && RT_SDHCI_GET_CMD(rt_sdhci_readw(host, RT_SDHCI_COMMAND)) != MMC_BUS_TEST_R) + { + host->data->err = -EILSEQ; + } + + + if (host->data->err) + { + sdhci_finish_data(host); + } + else + { + if (intmask & (RT_SDHCI_INT_DATA_AVAIL | RT_SDHCI_INT_SPACE_AVAIL)) + sdhci_transfer_pio(host); + + if (intmask & RT_SDHCI_INT_DMA_END) + { + rt_uint32_t dmastart, dmanow; + + dmastart = sdhci_sdma_address(host); + dmanow = dmastart + host->data->bytes_xfered; + dmanow = (dmanow & ~((rt_uint32_t)RT_SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + RT_SDHCI_DEFAULT_BOUNDARY_SIZE; + host->data->bytes_xfered = dmanow - dmastart; + LOG_D("DMA base %pad, transferred 0x%06x bytes, next %pad\n", + &dmastart, host->data->bytes_xfered, &dmanow); + sdhci_set_sdma_addr(host, dmanow); + } + + if (intmask & RT_SDHCI_INT_DATA_END) + { + struct rt_mmcsd_data *data = host->data; + if (data->buf) + { + if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, data->buf, data->blks * data->blksize); + } else { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, data->buf, data->blks * data->blksize); + } + } + if (host->cmd == host->data_cmd) + { + host->data_early = 1; + } + else + { + sdhci_finish_data(host); + } + } + } +} + +static void rt_sdhci_read_rsp_136(struct rt_sdhci_host *host, struct rt_mmcsd_cmd *cmd) +{ + int i, reg; + + for (i = 0; i < 4; i++) + { + reg = RT_SDHCI_RESPONSE + (3 - i) * 4; + cmd->resp[i] = rt_sdhci_readl(host, reg); + } + + if (host->quirks2 & RT_SDHCI_QUIRK2_RSP_136_HAS_CRC) + return; + + for (i = 0; i < 4; i++) + { + cmd->resp[i] <<= 8; + if (i != 3) + cmd->resp[i] |= cmd->resp[i + 1] >> 24; + } +} + +static void sdhci_command_end(struct rt_sdhci_host *host) +{ + struct rt_mmcsd_cmd *cmd = host->cmd; + + host->cmd = NULL; + + if (cmd->flags & MMC_RSP_PRESENT) + { + if (cmd->flags & MMC_RSP_136) + { + rt_sdhci_read_rsp_136(host, cmd); + } + else + { + cmd->resp[0] = rt_sdhci_readl(host, RT_SDHCI_RESPONSE); + } + } + + if (cmd->flags & MMC_RSP_BUSY) + { + if (cmd->data) + { + LOG_D("Cannot wait for busy signal when also doing a data transfer"); + } + else if (!(host->quirks & RT_SDHCI_QUIRK_NO_BUSY_IRQ) && cmd == host->data_cmd) + { + return; + } + } + + if (cmd == cmd->mrq->sbc) + { + if (!sdhci_send_command(host, cmd->mrq->cmd)) + { + host->deferred_cmd = cmd->mrq->cmd; + } + } + else + { + if (host->data && host->data_early) + sdhci_finish_data(host); + + if (!cmd->data) + __sdhci_finish_mrq(host, cmd->mrq); + } +} + + +static void sdhci_cmd_irq(struct rt_sdhci_host *host, rt_uint32_t intmask, rt_uint32_t *intmask_p) +{ + if (intmask & RT_SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) + { + struct rt_mmcsd_req *mrq = host->data_cmd->mrq; + rt_uint16_t auto_cmd_status = rt_sdhci_readw(host, RT_SDHCI_AUTO_CMD_STATUS); + int data_err_bit = (auto_cmd_status & RT_SDHCI_AUTO_CMD_TIMEOUT) ? RT_SDHCI_INT_DATA_TIMEOUT : RT_SDHCI_INT_DATA_CRC; + + if (!mrq->sbc && (host->flags & RT_SDHCI_AUTO_CMD12)) + { + *intmask_p |= data_err_bit; + return; + } + } + + if (!host->cmd) + { + if (host->pending_reset) + return; + rt_kprintf("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", + mmc_hostname(host->mmc), (unsigned)intmask); + rt_read_reg_debug(host); + return; + } + if (intmask & (RT_SDHCI_INT_TIMEOUT | RT_SDHCI_INT_CRC | RT_SDHCI_INT_END_BIT | RT_SDHCI_INT_INDEX)) + { + if (intmask & RT_SDHCI_INT_TIMEOUT) + host->cmd->err = -ETIMEDOUT; + else + host->cmd->err = -EILSEQ; + + /* Treat data command CRC error the same as data CRC error */ + if (host->cmd->data && (intmask & (RT_SDHCI_INT_CRC | RT_SDHCI_INT_TIMEOUT)) == RT_SDHCI_INT_CRC) + { + host->cmd = NULL; + *intmask_p |= RT_SDHCI_INT_DATA_CRC; + return; + } + + __sdhci_finish_mrq(host, host->cmd->mrq); + return; + } + + if (intmask & RT_SDHCI_INT_AUTO_CMD_ERR) + { + struct rt_mmcsd_req *mrq = host->cmd->mrq; + rt_uint16_t auto_cmd_status = rt_sdhci_readw(host, RT_SDHCI_AUTO_CMD_STATUS); + int err = (auto_cmd_status & RT_SDHCI_AUTO_CMD_TIMEOUT) ? -ETIMEDOUT : -EILSEQ; + + if (mrq->sbc && (host->flags & RT_SDHCI_AUTO_CMD23)) + { + mrq->sbc->err = err; + __sdhci_finish_mrq(host, mrq); + return; + } + } + + if (intmask & RT_SDHCI_INT_RESPONSE) + sdhci_command_end(host); +} + +static void sdhci_irq(int irq, void *dev_id) +{ +#define IRQ_NONE 0 +#define IRQ_WAIT 1 +#define IRQ_DONE 2 + + struct rt_mmcsd_req* mrqs_done[RT_SDHCI_MAX_MRQS] = { 0 }; + struct rt_sdhci_host *host = dev_id; + rt_uint32_t intmask, mask, unexpected = 0; + int max_loops = 16; + int i, result= IRQ_NONE ; + rt_spin_lock(&host->lock); + + if (host->runtime_suspended) + { + rt_spin_unlock(&host->lock); + return; + } + + intmask = rt_sdhci_readl(host, RT_SDHCI_INT_STATUS); + if (!intmask || intmask == 0xffffffff) + { + result = IRQ_NONE; + goto out; + } + + do { + LOG_D("IRQ status 0x%08x\n", intmask); + + if (host->ops->irq) + { + intmask = host->ops->irq(host, intmask); + if (!intmask) + goto cont; + } + + /* Clear selected interrupts. */ + mask = intmask & (RT_SDHCI_INT_CMD_MASK | RT_SDHCI_INT_DATA_MASK | RT_SDHCI_INT_BUS_POWER); + rt_sdhci_writel(host, mask, RT_SDHCI_INT_STATUS); + + if (intmask & (RT_SDHCI_INT_CARD_INSERT | RT_SDHCI_INT_CARD_REMOVE)) + { + rt_uint32_t present = rt_sdhci_readl(host, RT_SDHCI_PRESENT_STATE) & RT_SDHCI_CARD_PRESENT; + + host->ier &= ~(RT_SDHCI_INT_CARD_INSERT | RT_SDHCI_INT_CARD_REMOVE); + host->ier |= present ? RT_SDHCI_INT_CARD_REMOVE : RT_SDHCI_INT_CARD_INSERT; + rt_sdhci_writel(host, host->ier, RT_SDHCI_INT_ENABLE); + rt_sdhci_writel(host, host->ier, RT_SDHCI_SIGNAL_ENABLE); + + rt_sdhci_writel(host, intmask & (RT_SDHCI_INT_CARD_INSERT | RT_SDHCI_INT_CARD_REMOVE), RT_SDHCI_INT_STATUS); + + host->thread_isr |= intmask & (RT_SDHCI_INT_CARD_INSERT | RT_SDHCI_INT_CARD_REMOVE); + result = IRQ_WAIT; + } + + if (intmask & RT_SDHCI_INT_CMD_MASK) + sdhci_cmd_irq(host, intmask & RT_SDHCI_INT_CMD_MASK, &intmask); + + if (intmask & RT_SDHCI_INT_DATA_MASK) + sdhci_data_irq(host, intmask & RT_SDHCI_INT_DATA_MASK); + + if (intmask & RT_SDHCI_INT_BUS_POWER) + rt_kprintf("%s: Card is consuming too much power!\n", + mmc_hostname(host->mmc)); + + intmask &= ~(RT_SDHCI_INT_CARD_INSERT | RT_SDHCI_INT_CARD_REMOVE | RT_SDHCI_INT_CMD_MASK | RT_SDHCI_INT_DATA_MASK | RT_SDHCI_INT_ERROR | RT_SDHCI_INT_BUS_POWER | RT_SDHCI_INT_RETUNE | RT_SDHCI_INT_CARD_INT); + + if (intmask) + { + unexpected |= intmask; + rt_sdhci_writel(host, intmask, RT_SDHCI_INT_STATUS); + } + cont: + if (result == IRQ_NONE) + result = IRQ_WAIT; + intmask = rt_sdhci_readl(host, RT_SDHCI_INT_STATUS); + } while (intmask && --max_loops); + + for (i = 0; i < RT_SDHCI_MAX_MRQS; i++) + { + struct rt_mmcsd_req *mrq = host->mrqs_done[i]; + + if (!mrq) + continue; + + if (sdhci_defer_done(host, mrq)) + { + result = IRQ_WAIT; + } + else + { + mrqs_done[i] = mrq; + host->mrqs_done[i] = NULL; + } + } +out: + if (host->deferred_cmd) + result = IRQ_WAIT; + + rt_spin_unlock(&host->lock); + + for (i = 0; i < RT_SDHCI_MAX_MRQS; i++) + { + if (!mrqs_done[i]) + continue; + + if (host->ops->request_done) + host->ops->request_done(host, mrqs_done[i]); + else + rt_mmc_request_done(host->mmc, mrqs_done[i]); + } + + if (unexpected) + { + rt_kprintf("%s: Unexpected interrupt 0x%08x.\n", + mmc_hostname(host->mmc), unexpected); + rt_read_reg_debug(host); + } + + if (result == IRQ_WAIT) + { + rt_workqueue_submit_work(host->irq_wq, &host->irq_work, 0); + } +} + +static rt_bool_t sdhci_send_command_retry(struct rt_sdhci_host *host, + struct rt_mmcsd_cmd *cmd, + unsigned long flags) +{ + struct rt_mmcsd_cmd *deferred_cmd = host->deferred_cmd; + int timeout = 10; /* Approx. 10 ms */ + rt_bool_t present; + while (!sdhci_send_command(host, cmd)) + { + if (!timeout--) + { + rt_kprintf("%s: Controller never released inhibit bit(s).\n", + mmc_hostname(host->mmc)); + rt_read_reg_debug(host); + cmd->err = -EIO; + return RT_FALSE; + } + + rt_spin_unlock_irqrestore(&host->lock, flags); + + rt_thread_mdelay(1); + + present = host->mmc->ops->get_cd(host->mmc); + + flags = rt_spin_lock_irqsave(&host->lock); + + if (cmd == deferred_cmd && cmd != host->deferred_cmd) + return RT_TRUE; + + if (sdhci_present_error(host, cmd, present)) + return RT_FALSE; + } + + if (cmd == host->deferred_cmd) + host->deferred_cmd = NULL; + + return RT_TRUE; +} + +static rt_bool_t rt_sdhci_start_request_done(struct rt_sdhci_host *host) +{ + rt_base_t flags; + struct rt_mmcsd_req *mrq; + int i; + + flags = rt_spin_lock_irqsave(&host->lock); + + for (i = 0; i < RT_SDHCI_MAX_MRQS; i++) + { + mrq = host->mrqs_done[i]; + if (mrq) + break; + } + + if (!mrq) + { + rt_spin_unlock_irqrestore(&host->lock, flags); + return RT_TRUE; + } + + if (sdhci_needs_reset(host, mrq)) + { + if (host->cmd || host->data_cmd) + { + rt_spin_unlock_irqrestore(&host->lock, flags); + return RT_TRUE; + } + + /* Some controllers need this kick or reset won't work here */ + if (host->quirks & RT_SDHCI_QUIRK_CLOCK_BEFORE_RESET) + /* This is to force an update */ + host->ops->set_clock(host, host->clock); + + sdhci_reset_for(host, REQUEST_ERROR); + + host->pending_reset = RT_FALSE; + } + + if (host->flags & RT_SDHCI_REQ_USE_DMA) + { + struct rt_mmcsd_data *data = mrq->data; + + if (data && data->host_cookie == COOKIE_MAPPED) + { + if (host->bounce_buffer) + { + /* + * On reads, copy the bounced data into the + * sglist + */ + if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) + { + unsigned int length = data->bytes_xfered; + + if (length > host->bounce_buffer_size) + { + LOG_E("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n", + mmc_hostname(host->mmc), + host->bounce_buffer_size, + data->bytes_xfered); + /* Cap it down and continue */ + length = host->bounce_buffer_size; + } + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, data->buf, data->blks * data->blksize); + } else { + /* No copying, just switch ownership */ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, data->buf, data->blks * data->blksize); + } + } + data->host_cookie = COOKIE_UNMAPPED; + } + else { + if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, data->buf, data->blks * data->blksize); + } else { + /* No copying, just switch ownership */ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, data->buf, data->blks * data->blksize); + } + } + } + + host->mrqs_done[i] = NULL; + + rt_spin_unlock_irqrestore(&host->lock, flags); + + if (host->ops->request_done) + host->ops->request_done(host, mrq); + else + rt_mmc_request_done(host->mmc, mrq); + + return RT_FALSE; +} + + +static void sdhci_thread_irq(struct rt_work *work, void *work_data) +{ + struct rt_sdhci_host* host = work_data; + struct rt_mmcsd_cmd *cmd; + rt_base_t flags; + rt_uint32_t isr; + + while (!rt_sdhci_start_request_done(host)); + + flags = rt_spin_lock_irqsave(&host->lock); + + isr = host->thread_isr; + host->thread_isr = 0; + + cmd = host->deferred_cmd; + if (cmd && !sdhci_send_command_retry(host, cmd, flags)) + sdhci_finish_mrq(host, cmd->mrq); + + rt_spin_unlock_irqrestore(&host->lock, flags); + + if (isr & (RT_SDHCI_INT_CARD_INSERT | RT_SDHCI_INT_CARD_REMOVE)) + { + struct rt_mmc_host *mmc = host->mmc; + + mmc->ops->card_event(mmc); + } +} + + +void rt_sdhci_enable_io_irq(struct rt_mmc_host *mmc, int enable) +{ + struct rt_sdhci_host *host = mmc_priv(mmc); + rt_uint32_t flags; + + flags = rt_spin_lock_irqsave(&host->lock); + rt_sdhci_enable_io_irq_nolock(host, enable); + rt_spin_unlock_irqrestore(&host->lock, flags); +} + + +/********************************************************* */ +/* request */ +/********************************************************* */ + +void rt_sdhci_start_request(struct rt_mmc_host *mmc, struct rt_mmcsd_req *mrq) +{ + struct rt_sdhci_host *host = mmc_priv(mmc); + struct rt_mmcsd_cmd *cmd; + rt_base_t flags; + rt_bool_t present; + + /* Firstly check card presence */ + present = mmc->ops->get_cd(mmc); + + flags = rt_spin_lock_irqsave(&host->lock); + + if (sdhci_present_error(host, mrq->cmd, present)) + goto out_finish; + + cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd; + + if (!sdhci_send_command_retry(host, cmd, flags)) + goto out_finish; + + rt_spin_unlock_irqrestore(&host->lock, flags); + + return; + +out_finish: + sdhci_finish_mrq(host, mrq); + rt_spin_unlock_irqrestore(&host->lock, flags); +} + + +static void sdhci_complete_work(struct rt_work *work, void *work_data) +{ + struct rt_sdhci_host *host = work_data; + + while (!rt_sdhci_start_request_done(host)); +} + + +/********************************************************* */ +/* timer */ +/********************************************************* */ +static void sdhci_timeout_timer(void *parameter) +{ + struct rt_sdhci_host *host = parameter; + rt_base_t flags; + + flags = rt_spin_lock_irqsave(&host->lock); + + if (host->cmd && !sdhci_data_line_cmd(host->cmd)) + { + rt_kprintf("%s: Timeout waiting for hardware cmd interrupt.\n", + mmc_hostname(host->mmc)); + rt_read_reg_debug(host); + + host->cmd->err = -ETIMEDOUT; + sdhci_finish_mrq(host, host->cmd->mrq); + } + + rt_spin_unlock_irqrestore(&host->lock, flags); +} + +static void sdhci_timeout_data_timer(void *parameter) +{ + struct rt_sdhci_host *host = parameter; + rt_base_t flags; + + flags = rt_spin_lock_irqsave(&host->lock); + + if (host->data || host->data_cmd || (host->cmd && sdhci_data_line_cmd(host->cmd))) + { + rt_kprintf("%s: Timeout waiting for hardware interrupt.\n", + mmc_hostname(host->mmc)); + rt_read_reg_debug(host); + + if (host->data) + { + host->data->err = -ETIMEDOUT; + __sdhci_finish_data(host, RT_TRUE); + rt_workqueue_submit_work(host->complete_wq, &host->complete_work, 0); + } + else if (host->data_cmd) + { + host->data_cmd->err = -ETIMEDOUT; + sdhci_finish_mrq(host, host->data_cmd->mrq); + } + else + { + host->cmd->err = -ETIMEDOUT; + sdhci_finish_mrq(host, host->cmd->mrq); + } + } + + rt_spin_unlock_irqrestore(&host->lock, flags); +} + + +/********************************************************* */ +/* tuning */ +/********************************************************* */ +int rt_sdhci_execute_tuning(struct rt_mmc_host *mmc, rt_uint32_t opcode) +{ + struct rt_sdhci_host *host = mmc_priv(mmc); + int err = 0; + unsigned int tuning_count = 0; + rt_bool_t hs400_tuning; + + hs400_tuning = host->flags & RT_SDHCI_HS400_TUNING; + + if (host->tuning_mode == RT_SDHCI_TUNING_MODE_1) + tuning_count = host->tuning_count; + + switch (host->timing) + { + /* HS400 tuning is done in HS200 mode */ + case MMC_TIMING_MMC_HS400: + err = -EINVAL; + goto out; + + case MMC_TIMING_MMC_HS200: + if (hs400_tuning) + tuning_count = 0; + break; + + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_UHS_DDR50: + break; + + case MMC_TIMING_UHS_SDR50: + if (host->flags & RT_SDHCI_SDR50_NEEDS_TUNING) + break; + fallthrough; + + default: + goto out; + } + + if (host->ops->platform_execute_tuning) + { + err = host->ops->platform_execute_tuning(host, opcode); + goto out; + } + + mmc->retune_period = tuning_count; + + if (host->tuning_delay < 0) + host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK; + + rt_sdhci_start_tuning(host); + + host->tuning_err = __sdhci_execute_tuning(host, opcode); + + rt_sdhci_end_tuning(host); +out: + host->flags &= ~RT_SDHCI_HS400_TUNING; + + return err; +} + +int __sdhci_execute_tuning(struct rt_sdhci_host *host, rt_uint32_t opcode) +{ + int i; + + for (i = 0; i < host->tuning_loop_count; i++) + { + rt_uint16_t ctrl; + + rt_sdhci_send_tuning(host, opcode); + + if (!host->tuning_done) + { + rt_sdhci_abort_tuning(host, opcode); + return -ETIMEDOUT; + } + + if (host->tuning_delay > 0) + rt_thread_mdelay(host->tuning_delay); + + ctrl = rt_sdhci_readw(host, RT_SDHCI_HOST_CONTROL2); + if (!(ctrl & RT_SDHCI_CTRL_EXEC_TUNING)) + { + if (ctrl & RT_SDHCI_CTRL_TUNED_CLK) + return 0; /* Success! */ + break; + } + } + + LOG_D("%s: Tuning failed, falling back to fixed sampling clock\n", + mmc_hostname(host->mmc)); + rt_sdhci_reset_tuning(host); + return -EAGAIN; +} + +void rt_sdhci_start_tuning(struct rt_sdhci_host *host) +{ + rt_uint16_t ctrl; + + ctrl = rt_sdhci_readw(host, RT_SDHCI_HOST_CONTROL2); + ctrl |= RT_SDHCI_CTRL_EXEC_TUNING; + if (host->quirks2 & RT_SDHCI_QUIRK2_TUNING_WORK_AROUND) + ctrl |= RT_SDHCI_CTRL_TUNED_CLK; + rt_sdhci_writew(host, ctrl, RT_SDHCI_HOST_CONTROL2); + + rt_sdhci_writel(host, RT_SDHCI_INT_DATA_AVAIL, RT_SDHCI_INT_ENABLE); + rt_sdhci_writel(host, RT_SDHCI_INT_DATA_AVAIL, RT_SDHCI_SIGNAL_ENABLE); +} + +void rt_sdhci_end_tuning(struct rt_sdhci_host *host) +{ + rt_sdhci_writel(host, host->ier, RT_SDHCI_INT_ENABLE); + rt_sdhci_writel(host, host->ier, RT_SDHCI_SIGNAL_ENABLE); +} + +void rt_sdhci_abort_tuning(struct rt_sdhci_host *host, rt_uint32_t opcode) +{ + rt_sdhci_reset_tuning(host); + + sdhci_reset_for(host, TUNING_ABORT); + + rt_sdhci_end_tuning(host); +} + +void rt_sdhci_send_tuning(struct rt_sdhci_host *host, rt_uint32_t opcode) +{ + struct rt_mmc_host *mmc = host->mmc; + struct rt_mmcsd_cmd cmd = {}; + struct rt_mmcsd_req mrq = {}; + unsigned long flags; + rt_uint32_t b = host->sdma_boundary; + + flags = rt_spin_lock_irqsave(&host->lock); + + cmd.cmd_code = opcode; + cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; + cmd.mrq = &mrq; + + mrq.cmd = &cmd; + + if (cmd.cmd_code == MMC_SEND_TUNING_BLOCK_HS200 && mmc->ios.bus_width == MMC_BUS_WIDTH_8) + rt_sdhci_writew(host, RT_SDHCI_MAKE_BLKSZ(b, 128), RT_SDHCI_BLOCK_SIZE); + else + rt_sdhci_writew(host, RT_SDHCI_MAKE_BLKSZ(b, 64), RT_SDHCI_BLOCK_SIZE); + + rt_sdhci_writew(host, RT_SDHCI_TRNS_READ, RT_SDHCI_TRANSFER_MODE); + + if (!sdhci_send_command_retry(host, &cmd, flags)) + { + rt_spin_unlock_irqrestore(&host->lock, flags); + host->tuning_done = 0; + return; + } + + host->cmd = NULL; + + sdhci_del_timer(host, &mrq); + + host->tuning_done = 0; + + rt_spin_unlock_irqrestore(&host->lock, flags); +} + +void rt_sdhci_reset_tuning(struct rt_sdhci_host *host) +{ + rt_uint16_t ctrl; + + ctrl = rt_sdhci_readw(host, RT_SDHCI_HOST_CONTROL2); + ctrl &= ~RT_SDHCI_CTRL_TUNED_CLK; + ctrl &= ~RT_SDHCI_CTRL_EXEC_TUNING; + rt_sdhci_writew(host, ctrl, RT_SDHCI_HOST_CONTROL2); +} + + +/********************************************************* */ +/* error */ +/********************************************************* */ +static const struct mmc_host_ops rt_sdhci_ops = { + .request = rt_sdhci_start_request, + .set_ios = rt_sdhci_ios_set, + .get_cd = sdhci_get_cd, + .get_ro = rt_sdhci_ro_get, + .enable_sdio_irq = rt_sdhci_enable_io_irq, + .ack_sdio_irq = sdhci_ack_sdio_irq, + .start_signal_voltage_switch = rt_sdhci_start_signal_voltage_switch, + .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, + .execute_tuning = rt_sdhci_execute_tuning, + .card_event = sdhci_card_event, + .card_busy = sdhci_card_busy, +}; + + +void rt_sdhci_uninit_host(struct rt_sdhci_host *host, int dead) +{ + struct rt_mmc_host *mmc = host->mmc; + unsigned long flags; + + if (dead) + { + flags = rt_spin_lock_irqsave(&host->lock); + + host->flags |= RT_SDHCI_DEVICE_DEAD; + + if (sdhci_has_requests(host)) + { + rt_kprintf("%s: Controller removed during " + " transfer!\n", + mmc_hostname(mmc)); + sdhci_error_out_mrqs(host, -ENOMEDIUM); + } + + rt_spin_unlock_irqrestore(&host->lock, flags); + } + + sdhci_set_card_detection(host, RT_FALSE); + + rt_mmc_remove_host(mmc); + + + if (!dead) + sdhci_reset_for_all(host); + + rt_sdhci_writel(host, 0, RT_SDHCI_INT_ENABLE); + rt_sdhci_writel(host, 0, RT_SDHCI_SIGNAL_ENABLE); + + rt_timer_delete(&host->timer); + rt_timer_delete(&host->data_timer); + + rt_workqueue_destroy(host->complete_wq); + +} + +rt_uint16_t rt_sdhci_clk_set(struct rt_sdhci_host *host, unsigned int clock, + unsigned int *actual_clock) +{ + int div = 0; /* Initialized for compiler warning */ + int real_div = div, clk_mul = 1; + rt_uint16_t clk = 0; + rt_bool_t switch_base_clk = RT_FALSE; + + if (host->version >= RT_SDHCI_SPEC_300) + { + if (host->preset_enabled) + { + rt_uint16_t pre_val; + + clk = rt_sdhci_readw(host, RT_SDHCI_CLOCK_CONTROL); + pre_val = sdhci_get_preset_value(host); + div = FIELD_GET(RT_SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val); + if (host->clk_mul && (pre_val & RT_SDHCI_PRESET_CLKGEN_SEL)) + { + clk = RT_SDHCI_PROG_CLOCK_MODE; + real_div = div + 1; + clk_mul = host->clk_mul; + } + else + { + real_div = max_t(int, 1, div << 1); + } + goto clock_set; + } + + if (host->clk_mul) + { + for (div = 1; div <= 1024; div++) + { + if ((host->max_clk * host->clk_mul / div) + <= clock) + break; + } + if ((host->max_clk * host->clk_mul / div) <= clock) + { + + clk = RT_SDHCI_PROG_CLOCK_MODE; + real_div = div; + clk_mul = host->clk_mul; + div--; + } + else + { + + switch_base_clk = RT_TRUE; + } + } + + if (!host->clk_mul || switch_base_clk) + { + if (host->max_clk <= clock) + div = 1; + else + { + for (div = 2; div < RT_SDHCI_MAX_DIV_SPEC_300; + div += 2) + { + if ((host->max_clk / div) <= clock) + break; + } + } + real_div = div; + div >>= 1; + if ((host->quirks2 & RT_SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) + && !div && host->max_clk <= 25000000) + div = 1; + } + } + else + { + for (div = 1; div < RT_SDHCI_MAX_DIV_SPEC_200; div *= 2) + { + if ((host->max_clk / div) <= clock) + break; + } + real_div = div; + div >>= 1; + } + +clock_set: + if (real_div) + *actual_clock = (host->max_clk * clk_mul) / real_div; + clk |= (div & RT_SDHCI_DIV_MASK) << RT_SDHCI_DIVIDER_SHIFT; + clk |= ((div & RT_SDHCI_DIV_HI_MASK) >> RT_SDHCI_DIV_MASK_LEN) + << RT_SDHCI_DIVIDER_HI_SHIFT; + + return clk; +} + +void rt_sdhci_clk_enable(struct rt_sdhci_host *host, rt_uint16_t clk) +{ + long timeout; + + clk |= RT_SDHCI_CLOCK_INT_EN; + rt_sdhci_writew(host, clk, RT_SDHCI_CLOCK_CONTROL); + + timeout = rt_tick_from_millisecond(150); + while (1) + { + timeout = timeout - rt_tick_get(); + + clk = rt_sdhci_readw(host, RT_SDHCI_CLOCK_CONTROL); + if (clk & RT_SDHCI_CLOCK_INT_STABLE) + break; + if (timeout < 0) + { + rt_kprintf("%s: Internal clock never stabilised.\n", + mmc_hostname(host->mmc)); + rt_read_reg_debug(host); + return; + } + rt_hw_us_delay(10); + } + + if (host->version >= RT_SDHCI_SPEC_410 && host->v4_mode) + { + clk |= RT_SDHCI_CLOCK_PLL_EN; + clk &= ~RT_SDHCI_CLOCK_INT_STABLE; + rt_sdhci_writew(host, clk, RT_SDHCI_CLOCK_CONTROL); + + timeout = rt_tick_from_millisecond(150); + while (1) + { + timeout = timeout - rt_tick_get(); + + clk = rt_sdhci_readw(host, RT_SDHCI_CLOCK_CONTROL); + if (clk & RT_SDHCI_CLOCK_INT_STABLE) + break; + if (timeout < 0) + { + rt_kprintf("%s: PLL clock never stabilised.\n", + mmc_hostname(host->mmc)); + rt_read_reg_debug(host); + return; + } + rt_hw_us_delay(10); + } + } + + clk |= RT_SDHCI_CLOCK_CARD_EN; + rt_sdhci_writew(host, clk, RT_SDHCI_CLOCK_CONTROL); +} + +void rt_sdhci_set_clock(struct rt_sdhci_host *host, unsigned int clock) +{ + rt_uint16_t clk; + + host->mmc->actual_clock = 0; + + rt_sdhci_writew(host, 0, RT_SDHCI_CLOCK_CONTROL); + + if (clock == 0) + return; + + clk = rt_sdhci_clk_set(host, clock, &host->mmc->actual_clock); + rt_sdhci_clk_enable(host, clk); +} + +void rt_sdhci_read_caps(struct rt_sdhci_host *host, const rt_uint16_t *ver, + const rt_uint32_t *caps, const rt_uint32_t *caps1) +{ + rt_uint16_t v; + rt_uint64_t dt_caps_mask = 0; + rt_uint64_t dt_caps = 0; + + if (host->read_caps) + return; + + host->read_caps = RT_TRUE; + + if (debug_quirks) + host->quirks = debug_quirks; + + if (debug_quirks2) + host->quirks2 = debug_quirks2; + + sdhci_reset_for_all(host); + + if (host->v4_mode) + sdhci_do_enable_v4_mode(host); +#ifdef RT_USING_OFW + rt_ofw_prop_read_u64(mmc_dev(host->mmc)->ofw_node, + "sdhci-caps-mask", &dt_caps_mask); + rt_ofw_prop_read_u64(mmc_dev(host->mmc)->ofw_node, + "sdhci-caps", &dt_caps); +#endif + v = ver ? *ver : rt_sdhci_readw(host, RT_SDHCI_HOST_VERSION); + host->version = (v & RT_SDHCI_SPEC_VER_MASK) >> RT_SDHCI_SPEC_VER_SHIFT; + + if (caps) + { + host->caps = *caps; + } + else + { + host->caps = rt_sdhci_readl(host, RT_SDHCI_CAPABILITIES); + host->caps &= ~lower_32_bits(dt_caps_mask); + host->caps |= lower_32_bits(dt_caps); + } + + if (host->version < RT_SDHCI_SPEC_300) + return; + + if (caps1) + { + host->caps1 = *caps1; + } + else + { + host->caps1 = rt_sdhci_readl(host, RT_SDHCI_CAPABILITIES_1); + host->caps1 &= ~upper_32_bits(dt_caps_mask); + host->caps1 |= upper_32_bits(dt_caps); + } +} + +struct rt_sdhci_host *rt_sdhci_alloc_host(struct rt_device *dev, + size_t priv_size) +{ + struct rt_mmc_host *mmc; + struct rt_sdhci_host *host; + + mmc = rt_mmc_alloc_host(sizeof(struct rt_sdhci_host) + priv_size, dev); + if (!mmc) + return NULL; + + host = mmc_priv(mmc); + host->mmc = mmc; + host->mmc_host_ops = rt_sdhci_ops; + mmc->ops = &host->mmc_host_ops; + + host->flags = RT_SDHCI_SIGNALING_330; + + host->cqe_ier = RT_SDHCI_CQE_INT_MASK; + host->cqe_err_ier = RT_SDHCI_CQE_INT_ERR_MASK; + + host->tuning_delay = -1; + host->tuning_loop_count = MAX_TUNING_LOOP; + + host->sdma_boundary = RT_SDHCI_DEFAULT_BOUNDARY_ARG; + + host->max_timeout_count = 0xE; + + return host; +} + +int rt_sdhci_setup_host(struct rt_sdhci_host *host) +{ + struct rt_mmc_host *mmc; + size_t max_current_caps; + unsigned int ocr_avail; + unsigned int override_timeout_clk; + size_t max_clk; + int ret = 0; + bool enable_vqmmc = RT_FALSE; + + RT_ASSERT(host != NULL); + + + mmc = host->mmc; + + if (!mmc->supply.vqmmc) + { + if (ret) + return ret; + enable_vqmmc = RT_TRUE; + } + + LOG_D("Version: 0x%08x | Present: 0x%08x\n", + rt_sdhci_readw(host, RT_SDHCI_HOST_VERSION), + rt_sdhci_readl(host, RT_SDHCI_PRESENT_STATE)); + LOG_D("Caps: 0x%08x | Caps_1: 0x%08x\n", + rt_sdhci_readl(host, RT_SDHCI_CAPABILITIES), + rt_sdhci_readl(host, RT_SDHCI_CAPABILITIES_1)); + + rt_sdhci_read_caps(host,RT_NULL,RT_NULL,RT_NULL); + + override_timeout_clk = host->timeout_clk; + + if (host->version > RT_SDHCI_SPEC_420) + { + rt_kprintf("%s: Unknown controller version (%d). You may experience problems.\n", + mmc_hostname(mmc), host->version); + } + + if (host->quirks & RT_SDHCI_QUIRK_FORCE_DMA) + host->flags |= RT_SDHCI_USE_SDMA; + else if (!(host->caps & RT_SDHCI_CAN_DO_SDMA)) + LOG_D("Controller doesn't have SDMA capability\n"); + else + host->flags |= RT_SDHCI_USE_SDMA; + + if ((host->quirks & RT_SDHCI_QUIRK_BROKEN_DMA) && (host->flags & RT_SDHCI_USE_SDMA)) + { + LOG_D("Disabling DMA as it is marked broken\n"); + host->flags &= ~RT_SDHCI_USE_SDMA; + } + + if (sdhci_can_64bit_dma(host)) + host->flags |= RT_SDHCI_USE_64_BIT_DMA; + + if (host->flags & RT_SDHCI_USE_SDMA) + { + if (host->ops->set_dma_mask) + ret = host->ops->set_dma_mask(host); + + if (!ret && host->ops->enable_dma) + ret = host->ops->enable_dma(host); + + if (ret) + { + rt_kprintf("%s: No suitable DMA available - falling back to PIO\n", + mmc_hostname(mmc)); + host->flags &= ~RT_SDHCI_USE_SDMA; + + ret = 0; + } + } + + if ((host->flags & RT_SDHCI_USE_64_BIT_DMA) && !host->v4_mode) + host->flags &= ~RT_SDHCI_USE_SDMA; + + if (!(host->flags & RT_SDHCI_USE_SDMA)) + { + host->dma_mask = DMA_BIT_MASK(64); + } + if (host->version >= RT_SDHCI_SPEC_300) + host->max_clk = FIELD_GET(RT_SDHCI_CLOCK_V3_BASE_MASK, host->caps); + else + host->max_clk = FIELD_GET(RT_SDHCI_CLOCK_BASE_MASK, host->caps); + + host->max_clk *= 1000000; + if (host->max_clk == 0 || host->quirks & RT_SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) + { + if (!host->ops->get_max_clock) + { + rt_kprintf("%s: Hardware doesn't specify base clock frequency. %p \n", + mmc_hostname(mmc), host->ops->get_max_clock); + ret = -ENODEV; + goto undma; + } + host->max_clk = host->ops->get_max_clock(host); + } + + host->clk_mul = FIELD_GET(RT_SDHCI_CLOCK_MUL_MASK, host->caps1); + + if (host->clk_mul) + host->clk_mul += 1; + + max_clk = host->max_clk; + + if (host->ops->get_min_clock) + mmc->f_min = host->ops->get_min_clock(host); + else if (host->version >= RT_SDHCI_SPEC_300) + { + if (host->clk_mul) + max_clk = host->max_clk * host->clk_mul; + + mmc->f_min = host->max_clk / RT_SDHCI_MAX_DIV_SPEC_300; + } + else + mmc->f_min = host->max_clk / RT_SDHCI_MAX_DIV_SPEC_200; + + if (!mmc->f_max || mmc->f_max > max_clk) + mmc->f_max = max_clk; + + if (!(host->quirks & RT_SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) + { + host->timeout_clk = FIELD_GET(RT_SDHCI_TIMEOUT_CLK_MASK, host->caps); + + if (host->caps & RT_SDHCI_TIMEOUT_CLK_UNIT) + host->timeout_clk *= 1000; + + if (host->timeout_clk == 0) + { + if (!host->ops->get_timeout_clock) + { + rt_kprintf("%s: Hardware doesn't specify timeout clock frequency.\n", + mmc_hostname(mmc)); + ret = -ENODEV; + goto undma; + } + + host->timeout_clk = + DIV_ROUND_UP(host->ops->get_timeout_clock(host), + 1000); + } + + if (override_timeout_clk) + host->timeout_clk = override_timeout_clk; + + mmc->max_busy_timeout = host->ops->get_max_timeout_count ? host->ops->get_max_timeout_count(host) : 1 << 27; + mmc->max_busy_timeout /= host->timeout_clk; + } + + if (host->quirks2 & RT_SDHCI_QUIRK2_DISABLE_HW_TIMEOUT && !host->ops->get_max_timeout_count) + mmc->max_busy_timeout = 0; + + mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23; + mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; + + if (host->quirks & RT_SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) + host->flags |= RT_SDHCI_AUTO_CMD12; + + if ((host->version >= RT_SDHCI_SPEC_300) && (!(host->flags & RT_SDHCI_USE_SDMA) || host->v4_mode) && !(host->quirks2 & RT_SDHCI_QUIRK2_ACMD23_BROKEN)) + { + host->flags |= RT_SDHCI_AUTO_CMD23; + LOG_D("Auto-CMD23 available\n"); + } + else + { + LOG_D("Auto-CMD23 unavailable\n"); + } + + if (!(host->quirks & RT_SDHCI_QUIRK_FORCE_1_BIT_DATA)) + mmc->caps |= MMC_CAP_4_BIT_DATA; + + if (host->quirks2 & RT_SDHCI_QUIRK2_HOST_NO_CMD23) + mmc->caps &= ~MMC_CAP_CMD23; + + if (host->caps & RT_SDHCI_CAN_DO_HISPD) + mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; + if ((host->quirks & RT_SDHCI_QUIRK_BROKEN_CARD_DETECTION) && mmc_card_is_removable(mmc) && rt_mmc_gpio_get_cd(mmc) < 0) + mmc->caps |= MMC_CAP_NEEDS_POLL; + + if (mmc->supply.vqmmc) + { + if (enable_vqmmc) + { + host->sdhci_core_to_disable_vqmmc = !ret; + } + + if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, + 1950000)) + host->caps1 &= ~(RT_SDHCI_SUPPORT_SDR104 | RT_SDHCI_SUPPORT_SDR50 | RT_SDHCI_SUPPORT_DDR50); + + if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000, + 3600000)) + host->flags &= ~RT_SDHCI_SIGNALING_330; + + if (ret) + { + rt_kprintf("%s: Failed to enable vqmmc regulator: %d\n", + mmc_hostname(mmc), ret); + mmc->supply.vqmmc = (void *)-EINVAL; + } + } + if (host->quirks2 & RT_SDHCI_QUIRK2_NO_1_8_V) + { + host->caps1 &= ~(RT_SDHCI_SUPPORT_SDR104 | RT_SDHCI_SUPPORT_SDR50 | RT_SDHCI_SUPPORT_DDR50); + mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES); + mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS); + } + + if (host->caps1 & (RT_SDHCI_SUPPORT_SDR104 | RT_SDHCI_SUPPORT_SDR50 | RT_SDHCI_SUPPORT_DDR50)) + mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; + + if (host->caps1 & RT_SDHCI_SUPPORT_SDR104) + { + mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; + + if (!(host->quirks2 & RT_SDHCI_QUIRK2_BROKEN_HS200)) + mmc->caps2 |= MMC_CAP2_HS200; + } + else if (host->caps1 & RT_SDHCI_SUPPORT_SDR50) + { + mmc->caps |= MMC_CAP_UHS_SDR50; + } + + if (host->quirks2 & RT_SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && (host->caps1 & RT_SDHCI_SUPPORT_HS400)) + mmc->caps2 |= MMC_CAP2_HS400; + if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && (!mmc->supply.vqmmc || !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, 1300000))) + mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; + if ((host->caps1 & RT_SDHCI_SUPPORT_DDR50) && !(host->quirks2 & RT_SDHCI_QUIRK2_BROKEN_DDR50)) + mmc->caps |= MMC_CAP_UHS_DDR50; + + if (host->caps1 & RT_SDHCI_USE_SDR50_TUNING) + host->flags |= RT_SDHCI_SDR50_NEEDS_TUNING; + + if (host->caps1 & RT_SDHCI_DRIVER_TYPE_A) + mmc->caps |= MMC_CAP_DRIVER_TYPE_A; + if (host->caps1 & RT_SDHCI_DRIVER_TYPE_C) + mmc->caps |= MMC_CAP_DRIVER_TYPE_C; + if (host->caps1 & RT_SDHCI_DRIVER_TYPE_D) + mmc->caps |= MMC_CAP_DRIVER_TYPE_D; + + host->tuning_count = FIELD_GET(RT_SDHCI_RETUNING_TIMER_COUNT_MASK, + host->caps1); + + if (host->tuning_count) + host->tuning_count = 1 << (host->tuning_count - 1); + + /* Re-tuning mode supported by the Host Controller */ + host->tuning_mode = FIELD_GET(RT_SDHCI_RETUNING_MODE_MASK, host->caps1); + + ocr_avail = 0; + + max_current_caps = rt_sdhci_readl(host, RT_SDHCI_MAX_CURRENT); + + if (!max_current_caps && mmc->supply.vmmc) + { + int curr = regulator_get_current_limit(mmc->supply.vmmc); + if (curr > 0) + { + curr = curr / 1000; /* convert to mA */ + curr = curr / RT_SDHCI_MAX_CURRENT_MULTIPLIER; + + curr = min_t(rt_uint32_t, curr, RT_SDHCI_MAX_CURRENT_LIMIT); + max_current_caps = + FIELD_PREP(RT_SDHCI_MAX_CURRENT_330_MASK, curr) | FIELD_PREP(RT_SDHCI_MAX_CURRENT_300_MASK, curr) | FIELD_PREP(RT_SDHCI_MAX_CURRENT_180_MASK, curr); + } + } + + if (host->caps & RT_SDHCI_CAN_VDD_330) + { + ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; + + mmc->max_current_330 = FIELD_GET(RT_SDHCI_MAX_CURRENT_330_MASK, + max_current_caps) + * RT_SDHCI_MAX_CURRENT_MULTIPLIER; + } + if (host->caps & RT_SDHCI_CAN_VDD_300) + { + ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; + + mmc->max_current_300 = FIELD_GET(RT_SDHCI_MAX_CURRENT_300_MASK, + max_current_caps) + * RT_SDHCI_MAX_CURRENT_MULTIPLIER; + } + if (host->caps & RT_SDHCI_CAN_VDD_180) + { + ocr_avail |= MMC_VDD_165_195; + + mmc->max_current_180 = FIELD_GET(RT_SDHCI_MAX_CURRENT_180_MASK, + max_current_caps) + * RT_SDHCI_MAX_CURRENT_MULTIPLIER; + } + + if (host->ocr_mask) + ocr_avail = host->ocr_mask; + + if (mmc->ocr_avail) + ocr_avail = mmc->ocr_avail; + + mmc->ocr_avail = ocr_avail; + mmc->ocr_avail_sdio = ocr_avail; + if (host->ocr_avail_sdio) + mmc->ocr_avail_sdio &= host->ocr_avail_sdio; + mmc->ocr_avail_sd = ocr_avail; + if (host->ocr_avail_sd) + mmc->ocr_avail_sd &= host->ocr_avail_sd; + else + mmc->ocr_avail_sd &= ~MMC_VDD_165_195; + mmc->ocr_avail_mmc = ocr_avail; + if (host->ocr_avail_mmc) + mmc->ocr_avail_mmc &= host->ocr_avail_mmc; + + if (mmc->ocr_avail == 0) + { + rt_kprintf("%s: Hardware doesn't report any support voltages.\n", + mmc_hostname(mmc)); + ret = -ENODEV; + goto unreg; + } + + if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) || (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V))) + host->flags |= RT_SDHCI_SIGNALING_180; + + if (mmc->caps2 & MMC_CAP2_HSX00_1_2V) + host->flags |= RT_SDHCI_SIGNALING_120; + + rt_spin_lock_init(&host->lock); + + mmc->max_req_size = 524288; + if (host->flags & RT_SDHCI_USE_SDMA) + { + mmc->max_segs = 1; + } + else + { /* PIO */ + mmc->max_segs = RT_SDHCI_MAX_SEGS; + } + + mmc->max_seg_size = mmc->max_req_size; + + if (host->quirks & RT_SDHCI_QUIRK_FORCE_BLK_SZ_2048) + { + mmc->max_blk_size = 2; + } + else + { + mmc->max_blk_size = (host->caps & RT_SDHCI_MAX_BLOCK_MASK) >> RT_SDHCI_MAX_BLOCK_SHIFT; + if (mmc->max_blk_size >= 3) + { + rt_kprintf("%s: Invalid maximum block size, assuming 512 bytes\n", + mmc_hostname(mmc)); + mmc->max_blk_size = 0; + } + } + + mmc->max_blk_size = 512 << mmc->max_blk_size; + + /* + * Maximum block count. + */ + mmc->max_blk_count = (host->quirks & RT_SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; + return 0; + +unreg: +undma: + return ret; +} + +static void sdhci_init(struct rt_sdhci_host *host, int soft) +{ + struct rt_mmc_host *mmc = host->mmc; + rt_base_t flags; + + if (soft) + { + sdhci_do_reset(host, RT_SDHCI_RESET_CMD | RT_SDHCI_RESET_DATA); + } + else + { + sdhci_do_reset(host, RT_SDHCI_RESET_ALL); + } + if (host->v4_mode) + { + sdhci_do_enable_v4_mode(host); + } + flags = rt_spin_lock_irqsave(&host->lock); + sdhci_set_default_irqs(host); + rt_spin_unlock_irqrestore(&host->lock, flags); + + host->cqe_on = RT_FALSE; + + if (soft) + { + /* force clock reconfiguration */ + host->clock = 0; + host->reinit_uhs = RT_TRUE; + mmc->ops->set_ios(mmc, &mmc->ios); + } +} + +static void sdhci_reinit(struct rt_sdhci_host *host) +{ + rt_uint32_t cd = host->ier & (RT_SDHCI_INT_CARD_REMOVE | RT_SDHCI_INT_CARD_INSERT); + + sdhci_init(host, 0); + sdhci_enable_card_detection(host); + + if (cd != (host->ier & (RT_SDHCI_INT_CARD_REMOVE | RT_SDHCI_INT_CARD_INSERT))) + rt_mmc_detect_change(host->mmc, rt_tick_from_millisecond(200)); +} + +int rt_sdhci_init_host(struct rt_sdhci_host *host) +{ + struct rt_mmc_host *mmc = host->mmc; + int ret; + + if ((mmc->caps2 & MMC_CAP2_CQE) && (host->quirks & RT_SDHCI_QUIRK_BROKEN_CQE)) + { + mmc->caps2 &= ~MMC_CAP2_CQE; + } + + host->complete_wq = rt_workqueue_create("sdhci", 4096, 20); + if (!host->complete_wq) + return -ENOMEM; + + rt_work_init(&host->complete_work, sdhci_complete_work, host); + + rt_timer_init(&host->timer, "sdhci_timer", sdhci_timeout_timer, host, 0, RT_TIMER_FLAG_SOFT_TIMER); + rt_timer_init(&host->data_timer, "sdhci_data_timer", sdhci_timeout_data_timer, host, 0, RT_TIMER_FLAG_SOFT_TIMER); + + rt_wqueue_init(&host->buf_ready_int); + + sdhci_init(host, 0); + + host->irq_wq = rt_workqueue_create("sdhci_irq", 8192, 1); + rt_work_init(&host->irq_work, sdhci_thread_irq, host); + rt_hw_interrupt_install(host->irq, sdhci_irq, host, mmc_hostname(mmc)); + rt_pic_irq_unmask(host->irq); + ret = rt_mmc_add_host(mmc); + if (ret) + goto unirq; + + LOG_D("%s: RT_SDHCI controller on %s [%s] using %s\n", + mmc_hostname(mmc), host->hw_name, mmc_dev(mmc)->parent.name, + (host->flags & RT_SDHCI_USE_SDMA) ? "DMA" : "PIO"); + + sdhci_enable_card_detection(host); + + return 0; + +unirq: + sdhci_reset_for_all(host); + rt_sdhci_writel(host, 0, RT_SDHCI_INT_ENABLE); + rt_sdhci_writel(host, 0, RT_SDHCI_SIGNAL_ENABLE); + + return ret; +} + +int rt_sdhci_set_and_add_host(struct rt_sdhci_host *host) +{ + int ret; + ret = rt_sdhci_setup_host(host); + if (ret) + return ret; + + ret = rt_sdhci_init_host(host); + if (ret) + goto cleanup; + + return 0; + +cleanup: + rt_sdhci_cleanup_host(host); + + return ret; +} + +void rt_sdhci_ios_set(struct rt_mmc_host *mmc, struct rt_mmcsd_io_cfg *ios) +{ + struct rt_sdhci_host *host = mmc_priv(mmc); + rt_bool_t reinit_uhs = host->reinit_uhs; + rt_bool_t turning_on_clk = RT_FALSE; + rt_uint8_t ctrl; + + host->reinit_uhs = RT_FALSE; + + if (ios->power_mode == MMC_POWER_UNDEFINED) + return; + + if (host->flags & RT_SDHCI_DEVICE_DEAD) + { + if (mmc->supply.vmmc && ios->power_mode == MMC_POWER_OFF) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); + return; + } + + if (ios->power_mode == MMC_POWER_OFF) + { + rt_sdhci_writel(host, 0, RT_SDHCI_SIGNAL_ENABLE); + sdhci_reinit(host); + } + + if (host->version >= RT_SDHCI_SPEC_300 && (ios->power_mode == MMC_POWER_UP) && !(host->quirks2 & RT_SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) + sdhci_preset_value_enable(host, RT_FALSE); + + if (!ios->clock || ios->clock != host->clock) + { + turning_on_clk = ios->clock && !host->clock; + + host->ops->set_clock(host, ios->clock); + host->clock = ios->clock; + + if (host->quirks & RT_SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && host->clock) + { + host->timeout_clk = mmc->actual_clock ? mmc->actual_clock / 1000 : host->clock / 1000; + mmc->max_busy_timeout = + host->ops->get_max_timeout_count ? host->ops->get_max_timeout_count(host) : 1 << 27; + mmc->max_busy_timeout /= host->timeout_clk; + } + } + + if (host->ops->set_power) + host->ops->set_power(host, ios->power_mode, ios->vdd); + else + rt_sdhci_set_power(host, ios->power_mode, ios->vdd); + + host->ops->set_bus_width(host, ios->bus_width); + + if (!reinit_uhs && turning_on_clk && host->timing == ios->timing && host->version >= RT_SDHCI_SPEC_300 && !sdhci_presetable_values_change(host, ios)) + return; + + ctrl = rt_sdhci_readb(host, RT_SDHCI_HOST_CONTROL); + + if (!(host->quirks & RT_SDHCI_QUIRK_NO_HISPD_BIT)) + { + if (ios->timing == MMC_TIMING_SD_HS || ios->timing == MMC_TIMING_MMC_HS || ios->timing == MMC_TIMING_MMC_HS400 || ios->timing == MMC_TIMING_MMC_HS200 || ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_SDR50 || ios->timing == MMC_TIMING_UHS_SDR104 || ios->timing == MMC_TIMING_UHS_DDR50 || ios->timing == MMC_TIMING_UHS_SDR25) + ctrl |= RT_SDHCI_CTRL_HISPD; + else + ctrl &= ~RT_SDHCI_CTRL_HISPD; + } + + if (host->version >= RT_SDHCI_SPEC_300) + { + rt_uint16_t clk, ctrl_2; + + clk = rt_sdhci_readw(host, RT_SDHCI_CLOCK_CONTROL); + if (clk & RT_SDHCI_CLOCK_CARD_EN) + { + clk &= ~RT_SDHCI_CLOCK_CARD_EN; + rt_sdhci_writew(host, clk, RT_SDHCI_CLOCK_CONTROL); + } + + rt_sdhci_writeb(host, ctrl, RT_SDHCI_HOST_CONTROL); + + if (!host->preset_enabled) + { + ctrl_2 = rt_sdhci_readw(host, RT_SDHCI_HOST_CONTROL2); + ctrl_2 &= ~RT_SDHCI_CTRL_DRV_TYPE_MASK; + if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) + ctrl_2 |= RT_SDHCI_CTRL_DRV_TYPE_A; + else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) + ctrl_2 |= RT_SDHCI_CTRL_DRV_TYPE_B; + else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) + ctrl_2 |= RT_SDHCI_CTRL_DRV_TYPE_C; + else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) + ctrl_2 |= RT_SDHCI_CTRL_DRV_TYPE_D; + else + { + LOG_D("%s: invalid driver type, default to driver type B\n", + mmc_hostname(mmc)); + ctrl_2 |= RT_SDHCI_CTRL_DRV_TYPE_B; + } + + rt_sdhci_writew(host, ctrl_2, RT_SDHCI_HOST_CONTROL2); + host->drv_type = ios->drv_type; + } + + host->ops->set_uhs_signaling(host, ios->timing); + host->timing = ios->timing; + + if (sdhci_preset_needed(host, ios->timing)) + { + rt_uint16_t preset; + + sdhci_preset_value_enable(host, RT_TRUE); + preset = sdhci_get_preset_value(host); + ios->drv_type = FIELD_GET(RT_SDHCI_PRESET_DRV_MASK, + preset); + host->drv_type = ios->drv_type; + } + + host->ops->set_clock(host, host->clock); + } + else + rt_sdhci_writeb(host, ctrl, RT_SDHCI_HOST_CONTROL); +} +void rt_sdhci_free_host(struct rt_sdhci_host *host) +{ + rt_sdhci_cleanup_host(host); + rt_free(host); +} diff --git a/rt-thread/components/drivers/sensor/Kconfig b/rt-thread/components/drivers/sensor/Kconfig index 86f8711..976e6a7 100644 --- a/rt-thread/components/drivers/sensor/Kconfig +++ b/rt-thread/components/drivers/sensor/Kconfig @@ -10,6 +10,6 @@ if RT_USING_SENSOR config RT_USING_SENSOR_CMD bool "Using Sensor cmd" - select PKG_USING_RT_VSNPRINTF_FULL if RT_USING_SENSOR_V2 + select RT_KLIBC_USING_VSNPRINTF_STANDARD if RT_USING_SENSOR_V2 default y endif diff --git a/rt-thread/components/drivers/sensor/v1/sensor.c b/rt-thread/components/drivers/sensor/v1/sensor.c index 6da12f9..479cf83 100644 --- a/rt-thread/components/drivers/sensor/v1/sensor.c +++ b/rt-thread/components/drivers/sensor/v1/sensor.c @@ -40,7 +40,10 @@ static char *const sensor_name_str[] = "spo2_", /* SpO2 sensor */ "iaq_", /* IAQ sensor */ "etoh_", /* EtOH sensor */ - "bp_" /* Blood Pressure */ + "bp_", /* Blood Pressure */ + "volt_", /* Voltage sensor */ + "curr_", /* Current sensor */ + "pow_" /* Power sensor */ }; /* Sensor interrupt correlation function */ diff --git a/rt-thread/components/drivers/sensor/v1/sensor_cmd.c b/rt-thread/components/drivers/sensor/v1/sensor_cmd.c index 0410af4..486bd0b 100644 --- a/rt-thread/components/drivers/sensor/v1/sensor_cmd.c +++ b/rt-thread/components/drivers/sensor/v1/sensor_cmd.c @@ -83,6 +83,15 @@ static void sensor_show_data(rt_size_t num, rt_sensor_t sensor, struct rt_sensor case RT_SENSOR_CLASS_BP: LOG_I("num:%3d, bp.sbp:%5d mmHg, bp.dbp:%5d mmHg, timestamp:%5d", num, sensor_data->data.bp.sbp, sensor_data->data.bp.dbp, sensor_data->timestamp); break; + case RT_SENSOR_CLASS_VOLTAGE: + LOG_I("num:%3d, voltage:%5d mV, timestamp:%5d", num, sensor_data->data.mv, sensor_data->timestamp); + break; + case RT_SENSOR_CLASS_CURRENT: + LOG_I("num:%3d, current:%5d mA, timestamp:%5d", num, sensor_data->data.ma, sensor_data->timestamp); + break; + case RT_SENSOR_CLASS_POWER: + LOG_I("num:%3d, power:%5d mW, timestamp:%5d", num, sensor_data->data.mv, sensor_data->timestamp); + break; default: break; } @@ -281,7 +290,7 @@ static void sensor_polling(int argc, char **argv) MSH_CMD_EXPORT(sensor_polling, Sensor polling mode test function); #endif -static void sensor(int argc, char **argv) +static int sensor(int argc, char **argv) { static rt_device_t dev = RT_NULL; struct rt_sensor_data data; @@ -302,7 +311,7 @@ static void sensor(int argc, char **argv) rt_kprintf(" sodr Set output date rate to var\n"); rt_kprintf(" read [num] Read [num] times sensor\n"); rt_kprintf(" num default 5\n"); - return ; + return -RT_EINVAL; } else if (!strcmp(argv[1], "info")) { @@ -310,7 +319,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { LOG_W("Please probe sensor device first!"); - return ; + return -RT_ERROR; } rt_device_control(dev, RT_SENSOR_CTRL_GET_INFO, &info); switch (info.vendor) @@ -418,6 +427,15 @@ static void sensor(int argc, char **argv) case RT_SENSOR_UNIT_MMHG: rt_kprintf("unit :mmHg\n"); break; + case RT_SENSOR_UNIT_MV: + rt_kprintf("unit :mV\n"); + break; + case RT_SENSOR_UNIT_MA: + rt_kprintf("unit :mA\n"); + break; + case RT_SENSOR_UNIT_MW: + rt_kprintf("unit :mW\n"); + break; } rt_kprintf("range_max :%d\n", info.range_max); rt_kprintf("range_min :%d\n", info.range_min); @@ -431,7 +449,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { LOG_W("Please probe sensor device first!"); - return ; + return -RT_ERROR; } if (argc == 3) { @@ -469,12 +487,12 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { LOG_E("Can't find device:%s", argv[2]); - return; + return -RT_ERROR; } if (rt_device_open(dev, RT_DEVICE_FLAG_RDWR) != RT_EOK) { LOG_E("open device failed!"); - return; + return -RT_ERROR; } rt_device_control(dev, RT_SENSOR_CTRL_GET_ID, ®); LOG_I("device id: 0x%x!", reg); @@ -483,7 +501,7 @@ static void sensor(int argc, char **argv) else if (dev == RT_NULL) { LOG_W("Please probe sensor first!"); - return ; + return -RT_ERROR; } else if (!strcmp(argv[1], "sr")) { @@ -510,6 +528,8 @@ static void sensor(int argc, char **argv) { LOG_W("Unknown command, please enter 'sensor' get help information!"); } + + return RT_EOK; } #ifdef RT_USING_FINSH MSH_CMD_EXPORT(sensor, sensor test function); diff --git a/rt-thread/components/drivers/sensor/v2/sensor_cmd.c b/rt-thread/components/drivers/sensor/v2/sensor_cmd.c index e278f34..1b65c00 100644 --- a/rt-thread/components/drivers/sensor/v2/sensor_cmd.c +++ b/rt-thread/components/drivers/sensor/v2/sensor_cmd.c @@ -550,7 +550,7 @@ static void sensor_cmd_warning_probe(void) LOG_W("Please probe sensor device first!"); } -static void sensor(int argc, char **argv) +static int sensor(int argc, char **argv) { static rt_device_t dev = RT_NULL; struct rt_sensor_data data; @@ -562,14 +562,14 @@ static void sensor(int argc, char **argv) if (argc < 2) { sensor_cmd_warning_unknown(); - return; + return -RT_ERROR; } else if (!rt_strcmp(argv[1], "info")) { if (dev == RT_NULL) { sensor_cmd_warning_probe(); - return ; + return -RT_ERROR; } sensor = (rt_sensor_t)dev; rt_kprintf("name :%s\n", sensor->info.name); @@ -595,7 +595,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { sensor_cmd_warning_probe(); - return; + return -RT_ERROR; } if (argc == 3) { @@ -628,7 +628,7 @@ static void sensor(int argc, char **argv) information = rt_object_get_information(RT_Object_Class_Device); if(information == RT_NULL) - return; + return -RT_ERROR; rt_kprintf("device name sensor name sensor type mode resolution range\n"); rt_kprintf("----------- ------------- ------------------ ---- ---------- ----------\n"); @@ -655,7 +655,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { sensor_cmd_warning_probe(); - return; + return -RT_ERROR; } if (rt_device_control(dev, RT_SENSOR_CTRL_SOFT_RESET, RT_NULL) != RT_EOK) @@ -671,19 +671,19 @@ static void sensor(int argc, char **argv) if (argc < 3) { sensor_cmd_warning_unknown(); - return; + return -RT_ERROR; } new_dev = rt_device_find(argv[2]); if (new_dev == RT_NULL) { LOG_E("Can't find device:%s", argv[2]); - return; + return -RT_ERROR; } if (rt_device_open(new_dev, RT_DEVICE_FLAG_RDWR) != RT_EOK) { LOG_E("open device failed!"); - return; + return -RT_ERROR; } if (rt_device_control(new_dev, RT_SENSOR_CTRL_GET_ID, ®) == RT_EOK) { @@ -702,7 +702,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { sensor_cmd_warning_probe(); - return; + return -RT_ERROR; } sensor = (rt_sensor_t)dev; @@ -734,7 +734,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { sensor_cmd_warning_probe(); - return; + return -RT_ERROR; } sensor = (rt_sensor_t)dev; @@ -766,7 +766,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { sensor_cmd_warning_probe(); - return; + return -RT_ERROR; } sensor = (rt_sensor_t)dev; @@ -795,5 +795,7 @@ static void sensor(int argc, char **argv) { sensor_cmd_warning_unknown(); } + + return RT_EOK; } MSH_CMD_EXPORT(sensor, sensor test function); diff --git a/rt-thread/components/drivers/serial/Kconfig b/rt-thread/components/drivers/serial/Kconfig index 00fcfb6..349aaea 100644 --- a/rt-thread/components/drivers/serial/Kconfig +++ b/rt-thread/components/drivers/serial/Kconfig @@ -21,4 +21,7 @@ menuconfig RT_USING_SERIAL int "Set RX buffer size" depends on !RT_USING_SERIAL_V2 default 64 - endif + config RT_USING_SERIAL_BYPASS + bool "Using serial bypass" + default n + endif diff --git a/rt-thread/components/drivers/serial/SConscript b/rt-thread/components/drivers/serial/SConscript index 7ee41a4..04fa37e 100644 --- a/rt-thread/components/drivers/serial/SConscript +++ b/rt-thread/components/drivers/serial/SConscript @@ -12,9 +12,12 @@ if GetDepend(['RT_USING_SMART']): src += Glob('serial_tty.c') if GetDepend(['RT_USING_SERIAL_V2']): - src += ['serial_v2.c'] + src += ['dev_serial_v2.c'] else: - src += ['serial.c'] + src += ['dev_serial.c'] + +if GetDepend(['RT_USING_SERIAL_BYPASS']): + src += ['bypass.c'] if GetDepend(['RT_USING_DM']): src += ['serial_dm.c'] diff --git a/rt-thread/components/drivers/serial/bypass.c b/rt-thread/components/drivers/serial/bypass.c new file mode 100644 index 0000000..04ed71a --- /dev/null +++ b/rt-thread/components/drivers/serial/bypass.c @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-11-20 zhujiale the first version + */ + +#include +#define DBG_TAG "UART" +#define DBG_LVL DBG_INFO +#include + +static struct rt_serial_bypass_func* rt_bypass_alloc_func(const char* name, rt_uint8_t level, bypass_function_t func, void* data) +{ + struct rt_serial_bypass_func* bypass; + + if (!func) + return RT_NULL; + + bypass = rt_malloc(sizeof(struct rt_serial_bypass_func)); + rt_memset(bypass, 0, sizeof(struct rt_serial_bypass_func)); + + if (rt_strlen(name) > RT_NAME_MAX - 1) + rt_memcpy(bypass->name, name, RT_NAME_MAX); + else + rt_memcpy(bypass->name, name, rt_strlen(name) + 1); + + bypass->level = level; + + rt_list_init(&bypass->node); + bypass->bypass = func; + bypass->data = data; + + return bypass; +} + +rt_err_t rt_serial_bypass_init(struct rt_serial_device* serial) +{ + serial->bypass = rt_malloc(sizeof(struct rt_serial_bypass)); + rt_memset(serial->bypass, 0, sizeof(struct rt_serial_bypass)); + serial->bypass->pipe = rt_ringbuffer_create(serial->config.bufsz); + serial->bypass->mutex = rt_mutex_create("serial_bypass", RT_IPC_FLAG_FIFO); + + return RT_EOK; +} + +static rt_err_t rt_bypass_register(struct rt_serial_bypass_head* bypass, const char* name, rt_uint8_t level, bypass_function_t func, void* data) +{ + struct rt_serial_bypass_func* pass = RT_NULL; + struct rt_list_node* node; + int flags; + + RT_DEBUG_NOT_IN_INTERRUPT; + + pass = rt_bypass_alloc_func(name, level, func, data); + + RT_ASSERT(bypass != RT_NULL); + + node = bypass->head.next; + + if (node == &bypass->head) + { + rt_list_insert_before(&pass->node, node); + return RT_EOK; + } + flags = rt_spin_lock_irqsave(&(bypass->spinlock)); + do { + struct rt_serial_bypass_func* temp_curr; + temp_curr = rt_container_of(node, struct rt_serial_bypass_func, node); + + if (level < temp_curr->level) + { + rt_list_insert_before(node, &pass->node); + + rt_spin_unlock_irqrestore(&(bypass->spinlock), flags); + return RT_EOK; + } + else if (level == temp_curr->level) + { + rt_spin_unlock_irqrestore(&(bypass->spinlock), flags); + LOG_E("Conflict: bypass [%s] level conflicts with [%s] at level [%d]\n", name, temp_curr->name, level); + rt_free(pass); + return -RT_ERROR; + } + + node = node->next; + + } while (node != &bypass->head); + + rt_list_insert_before(&bypass->head, &pass->node); + + rt_spin_unlock_irqrestore(&(bypass->spinlock), flags); + return RT_EOK; + +} + +rt_err_t rt_bypass_upper_register(struct rt_serial_device* serial, const char* name, rt_uint8_t level, bypass_function_t func, void* data) +{ + if (!serial->bypass) + rt_serial_bypass_init(serial); + + if (!serial->bypass->upper_h) + { + serial->bypass->upper_h = rt_malloc(sizeof(struct rt_serial_bypass_head)); + rt_spin_lock_init(&serial->bypass->upper_h->spinlock); + rt_list_init(&serial->bypass->upper_h->head); + + } + + return rt_bypass_register(serial->bypass->upper_h, name, level, func, data); +} + + + +void rt_bypass_putchar(struct rt_serial_device* serial, rt_uint8_t ch) +{ + rt_mutex_take(serial->bypass->mutex, RT_WAITING_FOREVER); + rt_ringbuffer_putchar(serial->bypass->pipe, ch); + rt_mutex_release(serial->bypass->mutex); +} + +rt_size_t rt_bypass_getchar(struct rt_serial_device* serial, rt_uint8_t* ch) +{ + int flags; + rt_mutex_take(serial->bypass->mutex, RT_WAITING_FOREVER); + flags = rt_ringbuffer_getchar(serial->bypass->pipe, ch); + rt_mutex_release(serial->bypass->mutex); + return flags; +} + +static inline rt_err_t _bypass_getchar_form_serial_fifo(struct rt_serial_device* serial, char* ch) +{ + rt_base_t level; + struct rt_serial_rx_fifo* rx_fifo; + rx_fifo = (struct rt_serial_rx_fifo*)serial->serial_rx; + /* disable interrupt */ + level = rt_spin_lock_irqsave(&(serial->spinlock)); + + /* there's no data: */ + if ((rx_fifo->get_index == rx_fifo->put_index) && (rx_fifo->is_full == RT_FALSE)) + { + /* no data, enable interrupt and break out */ + rt_spin_unlock_irqrestore(&(serial->spinlock), level); + return -RT_EEMPTY; + } + + /* otherwise there's the data: */ + *ch = rx_fifo->buffer[rx_fifo->get_index]; + rx_fifo->get_index += 1; + if (rx_fifo->get_index >= serial->config.bufsz) rx_fifo->get_index = 0; + + if (rx_fifo->is_full == RT_TRUE) + { + rx_fifo->is_full = RT_FALSE; + } + + /* enable interrupt */ + rt_spin_unlock_irqrestore(&(serial->spinlock), level); + + return RT_EOK; +} + +static void _lower_work(struct rt_serial_device* serial) +{ + struct rt_list_node* node; + struct rt_serial_bypass_func* temp_curr = RT_NULL; + if (serial->bypass && serial->bypass->lower_h) + { + while (1) + { + char ch; + if (_bypass_getchar_form_serial_fifo(serial, &ch)) + return; + + node = serial->bypass->lower_h->head.next; + + while (node != &serial->bypass->lower_h->head) + { + temp_curr = rt_container_of(node, struct rt_serial_bypass_func, node); + + if (!temp_curr->bypass(serial, ch, temp_curr->data)) + { + break; + } + + node = node->next; + } + if (node == &serial->bypass->lower_h->head) + { + rt_bypass_putchar(serial, ch); + } + } + } +} + + +static void rt_lower_work(struct rt_work* work, void* work_data) +{ + struct rt_serial_device* serial = (struct rt_serial_device*)work_data; + + RT_ASSERT(serial != RT_NULL); + + _lower_work(serial); +} + +rt_err_t rt_bypass_lower_register(struct rt_serial_device* serial, const char* name, rt_uint8_t level, bypass_function_t func, void* data) +{ + if (!serial->bypass) + rt_serial_bypass_init(serial); + + if (!serial->bypass->lower_h) + { + serial->bypass->lower_workq = rt_workqueue_create("serial bypass", RT_SYSTEM_WORKQUEUE_STACKSIZE, + RT_SYSTEM_WORKQUEUE_PRIORITY); + rt_work_init(&serial->bypass->work, rt_lower_work, (void*)serial); + + serial->bypass->lower_h = rt_malloc(sizeof(struct rt_serial_bypass_head)); + rt_spin_lock_init(&serial->bypass->lower_h->spinlock); + rt_list_init(&serial->bypass->lower_h->head); + + } + + return rt_bypass_register(serial->bypass->lower_h, name, level, func, data); +} + +void rt_bypass_work_straight(struct rt_serial_device* serial) +{ + if (serial->bypass && serial->bypass->lower_h) + { + _lower_work(serial); + return; + } + + while (1) + { + char ch; + if (_bypass_getchar_form_serial_fifo(serial, &ch)) + return; + + rt_bypass_putchar(serial, ch); + } + +} + +rt_err_t rt_bypass_unregister(struct rt_serial_bypass_head* bypass, rt_uint8_t level) +{ + struct rt_list_node* node; + struct rt_serial_bypass_func* temp_curr = RT_NULL; + int flags; + + /*Can not unregister protect level in bypass it general be msh or tty*/ + if (level > RT_BYPASS_PROTECT_LEVEL_1) + return -RT_ERROR; + + if (!bypass) + return -RT_ERROR; + + node = bypass->head.next; + flags = rt_spin_lock_irqsave(&(bypass->spinlock)); + + do { + temp_curr = rt_container_of(node, struct rt_serial_bypass_func, node); + + if (level == temp_curr->level) + { + rt_list_remove(node); + rt_spin_unlock_irqrestore(&(bypass->spinlock), flags); + rt_free(temp_curr); + return RT_EOK; + } + + node = node->next; + } while (node != &bypass->head); + + LOG_E("Can't find bypass with level [%d]", level); + rt_spin_unlock_irqrestore(&(bypass->spinlock), flags); + return -RT_ERROR; +} + +rt_err_t rt_bypass_upper_unregister(struct rt_serial_device* serial, rt_uint8_t level) +{ + if (!serial->bypass || !serial->bypass->upper_h) + return -RT_ERROR; + return rt_bypass_unregister(serial->bypass->upper_h, level); +} + +rt_err_t rt_bypass_lower_unregister(struct rt_serial_device* serial, rt_uint8_t level) +{ + if (!serial->bypass || !serial->bypass->lower_h) + return -RT_ERROR; + return rt_bypass_unregister(serial->bypass->lower_h, level); +} + +int serial_bypass_list(int argc, char** argv) +{ + struct rt_serial_device* serial = RT_NULL; + struct rt_serial_bypass_func* current; + struct rt_list_node* node; + int flags; + + serial = (struct rt_serial_device*)rt_console_get_device(); + if (!serial || !serial->bypass) + { + rt_kprintf("Serial bypass not initialized.\n"); + return -1; + } + + /* 遍历 Upper Bypass 链表 */ + if (serial->bypass->upper_h) + { + rt_kprintf("Upper bypass chain:\n"); + node = serial->bypass->upper_h->head.next; + + flags = rt_spin_lock_irqsave(&(serial->bypass->upper_h->spinlock)); /* 加锁*/ + while (node != &serial->bypass->upper_h->head) + { + current = rt_container_of(node, struct rt_serial_bypass_func, node); + rt_kprintf(" - Name: [%s], Level: [%d]\n", current->name, current->level); + node = node->next; + } + rt_spin_unlock_irqrestore(&(serial->bypass->upper_h->spinlock), flags); /* 解锁*/ + } + else + { + rt_kprintf("Upper bypass chain is empty.\n"); + } + + /* 遍历 Lower Bypass 链表 */ + if (serial->bypass->lower_h) + { + rt_kprintf("Lower bypass chain:\n"); + node = serial->bypass->lower_h->head.next; + + flags = rt_spin_lock_irqsave(&(serial->bypass->lower_h->spinlock)); /* 加锁*/ + while (node != &serial->bypass->lower_h->head) + { + current = rt_container_of(node, struct rt_serial_bypass_func, node); + rt_kprintf(" - Name: [%s], Level: [%d]\n", current->name, current->level); + node = node->next; + } + rt_spin_unlock_irqrestore(&(serial->bypass->lower_h->spinlock), flags); /* 解锁*/ + } + else + { + rt_kprintf("Lower bypass chain is empty.\n"); + } + + return 0; +} + + +MSH_CMD_EXPORT(serial_bypass_list, serial bypass list) diff --git a/rt-thread/components/drivers/serial/serial.c b/rt-thread/components/drivers/serial/dev_serial.c similarity index 96% rename from rt-thread/components/drivers/serial/serial.c rename to rt-thread/components/drivers/serial/dev_serial.c index 19043e2..458a5b7 100644 --- a/rt-thread/components/drivers/serial/serial.c +++ b/rt-thread/components/drivers/serial/dev_serial.c @@ -27,6 +27,7 @@ * 2020-12-14 Meco Man implement function of setting window's size(TIOCSWINSZ) * 2021-08-22 Meco Man implement function of getting window's size(TIOCGWINSZ) * 2023-09-15 xqyjlj perf rt_hw_interrupt_disable/enable + * 2024-11-25 zhujiale add bypass mode */ #include @@ -303,6 +304,23 @@ rt_inline int _serial_int_rx(struct rt_serial_device *serial, rt_uint8_t *data, rx_fifo = (struct rt_serial_rx_fifo*) serial->serial_rx; RT_ASSERT(rx_fifo != RT_NULL); +#ifdef RT_USING_SERIAL_BYPASS + if (serial->bypass) + { + rt_bypass_work_straight(serial); + while (length) + { + rt_uint8_t ch; + if (!rt_bypass_getchar(serial, &ch)) + break; + + *data = ch & 0xff; + data++; length--; + } + + return size - length; + } +#endif /* read from software FIFO */ while (length) { @@ -1413,10 +1431,31 @@ void rt_hw_serial_isr(struct rt_serial_device *serial, int event) ch = serial->ops->getc(serial); if (ch == -1) break; - /* disable interrupt */ - level = rt_spin_lock_irqsave(&(serial->spinlock)); +#ifdef RT_USING_SERIAL_BYPASS + if (serial->bypass && serial->bypass->upper_h && (serial->bypass->upper_h->head.next != &serial->bypass->upper_h->head)) + { + rt_bool_t skip = RT_FALSE; + char buf = (char)ch; + int ret; + rt_list_t* node = serial->bypass->upper_h->head.next; + do { + struct rt_serial_bypass_func* bypass_run = rt_container_of(node, struct rt_serial_bypass_func, node); + ret = bypass_run->bypass(serial, buf, bypass_run->data); + if (!ret) + { + skip = RT_TRUE; + break; + } + node = node->next; + } while (node != &serial->bypass->upper_h->head); + if (skip) + continue; + } + +#endif + level = rt_spin_lock_irqsave(&(serial->spinlock)); rx_fifo->buffer[rx_fifo->put_index] = ch; rx_fifo->put_index += 1; if (rx_fifo->put_index >= serial->config.bufsz) rx_fifo->put_index = 0; @@ -1435,17 +1474,12 @@ void rt_hw_serial_isr(struct rt_serial_device *serial, int event) rt_spin_unlock_irqrestore(&(serial->spinlock), level); } - /** - * Invoke callback. - * First try notify if any, and if notify is existed, rx_indicate() - * is not callback. This separate the priority and makes the reuse - * of same serial device reasonable for RT console. - */ - if (serial->rx_notify.notify) - { - serial->rx_notify.notify(serial->rx_notify.dev); - } - else if (serial->parent.rx_indicate != RT_NULL) +#ifdef RT_USING_SERIAL_BYPASS + if (serial->bypass && serial->bypass->lower_h) + rt_workqueue_dowork(serial->bypass->lower_workq, &serial->bypass->work); +#endif + + if (serial->parent.rx_indicate != RT_NULL) { rt_size_t rx_length; diff --git a/rt-thread/components/drivers/serial/serial_v2.c b/rt-thread/components/drivers/serial/dev_serial_v2.c similarity index 99% rename from rt-thread/components/drivers/serial/serial_v2.c rename to rt-thread/components/drivers/serial/dev_serial_v2.c index 111bfbc..18f9c89 100644 --- a/rt-thread/components/drivers/serial/serial_v2.c +++ b/rt-thread/components/drivers/serial/dev_serial_v2.c @@ -599,7 +599,7 @@ static rt_ssize_t _serial_fifo_tx_nonblocking(struct rt_device *dev, rt_hw_interrupt_enable(level); rt_uint8_t *put_ptr = RT_NULL; - /* Get the linear length buffer from rinbuffer */ + /* Get the linear length buffer from ringbuffer */ tx_fifo->put_size = rt_serial_get_linear_buffer(&(tx_fifo->rb), &put_ptr); /* Call the transmit interface for transmission */ serial->ops->transmit(serial, @@ -1624,7 +1624,7 @@ void rt_hw_serial_isr(struct rt_serial_device *serial, int event) tx_fifo->activated = RT_TRUE; rt_uint8_t *put_ptr = RT_NULL; - /* Get the linear length buffer from rinbuffer */ + /* Get the linear length buffer from ringbuffer */ tx_fifo->put_size = rt_serial_get_linear_buffer(&(tx_fifo->rb), &put_ptr); /* Call the transmit interface for transmission again */ serial->ops->transmit(serial, diff --git a/rt-thread/components/drivers/serial/serial_tty.c b/rt-thread/components/drivers/serial/serial_tty.c index bbf61f8..b5c4549 100644 --- a/rt-thread/components/drivers/serial/serial_tty.c +++ b/rt-thread/components/drivers/serial/serial_tty.c @@ -114,59 +114,24 @@ static void _setup_debug_rxind_hook(void) #endif /* LWP_DEBUG_INIT */ -static void _tty_rx_notify(struct rt_device *device) +static rt_err_t _serial_ty_bypass(struct rt_serial_device* serial, char ch,void *data) { lwp_tty_t tp; - struct serial_tty_context *softc; - - tp = rt_container_of(device, struct lwp_tty, parent); - RT_ASSERT(tp); - - softc = tty_softc(tp); - - if (_ttyworkq) - rt_workqueue_submit_work(_ttyworkq, &softc->work, 0); -} - -static void _tty_rx_worker(struct rt_work *work, void *data) -{ - char input; - rt_ssize_t readbytes; - lwp_tty_t tp = data; - struct serial_tty_context *softc; - struct rt_serial_device *serial; + tp = (lwp_tty_t)data; tty_lock(tp); - - while (1) - { - softc = tty_softc(tp); - serial = softc->parent; - readbytes = rt_device_read(&serial->parent, -1, &input, 1); - if (readbytes != 1) - { - break; - } - - ttydisc_rint(tp, input, 0); - } - + ttydisc_rint(tp, ch, 0); ttydisc_rint_done(tp); tty_unlock(tp); + + return RT_EOK; + } -rt_inline void _setup_serial(struct rt_serial_device *serial, lwp_tty_t tp, +rt_inline void _setup_serial(struct rt_serial_device* serial, lwp_tty_t tp, struct serial_tty_context *softc) { - struct rt_device_notify notify; - - softc->backup_notify = serial->rx_notify; - notify.dev = &tp->parent; - notify.notify = _tty_rx_notify; - - rt_device_init(&serial->parent); - - rt_device_control(&serial->parent, RT_DEVICE_CTRL_NOTIFY_SET, ¬ify); + rt_bypass_lower_register(serial, "tty", RT_BYPASS_PROTECT_LEVEL_1, _serial_ty_bypass, (void *)tp); } rt_inline void _restore_serial(struct rt_serial_device *serial, lwp_tty_t tp, @@ -267,7 +232,7 @@ static void serial_tty_close(struct lwp_tty *tp) LOG_D("%s", __func__); - _restore_serial(serial, tp, softc); + rt_bypass_lower_unregister(serial, RT_BYPASS_PROTECT_LEVEL_1); rt_device_close(&serial->parent); } @@ -345,7 +310,6 @@ rt_err_t rt_hw_serial_register_tty(struct rt_serial_device *serial) { _serial_tty_set_speed(tty); rc = lwp_tty_register(tty, dev_name); - rt_work_init(&softc->work, _tty_rx_worker, tty); if (rc != RT_EOK) { diff --git a/rt-thread/components/drivers/smp_call/SConscript b/rt-thread/components/drivers/smp_call/SConscript new file mode 100644 index 0000000..2f4fe0b --- /dev/null +++ b/rt-thread/components/drivers/smp_call/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = [] +if GetDepend("RT_USING_SMP"): + src += Glob('*.c') +CPPPATH = [cwd] +group = DefineGroup('smp', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/smp_call/smp_call.c b/rt-thread/components/drivers/smp_call/smp_call.c new file mode 100644 index 0000000..6c65e82 --- /dev/null +++ b/rt-thread/components/drivers/smp_call/smp_call.c @@ -0,0 +1,374 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/9/12 zhujiale the first version + * 2024/10/24 Shell added non-blocking IPI calling method; + * fixup data racing + */ + +#include "smp_call.h" + +#define DBG_TAG "SMP" +#define DBG_LVL DBG_INFO +#include + +static struct smp_data +{ + /* call request data to each cores */ + struct rt_smp_call_req call_req_cores[RT_CPUS_NR]; + + /* call queue of this core */ + rt_ll_slist_t call_queue; +} _smp_data_cores[RT_CPUS_NR]; + +#define _CALL_REQ_USAGE_FREED 0 +#define _CALL_REQ_USAGE_BUSY 1 +static void _call_req_take(struct rt_smp_call_req *req) +{ + rt_base_t exp; + do + { + exp = _CALL_REQ_USAGE_FREED; + } + while (!rt_atomic_compare_exchange_strong(&req->event.typed.usage_tracer, &exp, _CALL_REQ_USAGE_BUSY)); +} + +static void _call_req_release(struct rt_smp_call_req *req) +{ + rt_atomic_store(&req->event.typed.usage_tracer, _CALL_REQ_USAGE_FREED); +} + +void rt_smp_request_wait_freed(struct rt_smp_call_req *req) +{ + rt_base_t usage_tracer; + + RT_DEBUG_IN_THREAD_CONTEXT; + + usage_tracer = rt_atomic_load(&req->event.typed.usage_tracer); + while (usage_tracer != _CALL_REQ_USAGE_FREED) + { + rt_thread_yield(); + usage_tracer = rt_atomic_load(&req->event.typed.usage_tracer); + } +} + +static void _mask_out_cpu(struct rt_smp_event *event, int oncpu) +{ + rt_base_t new_mask, old_mask; + rt_atomic_t *maskp = event->typed.calling_cpu_mask; + do + { + old_mask = rt_atomic_load(maskp); + new_mask = old_mask & ~(1ul << oncpu); + } while (!rt_atomic_compare_exchange_strong(maskp, &old_mask, new_mask)); +} + +static void _do_glob_request(struct rt_smp_call_req *req_global, + struct rt_smp_call_req *req_local) +{ + struct rt_smp_event *event; + + /* release the global request data */ + rt_memcpy(req_local, req_global, sizeof(struct rt_smp_call_req)); + rt_hw_spin_unlock(&req_global->freed_lock); + + event = &req_local->event; + RT_ASSERT(!!event->func); + event->func(event->data); + + return ; +} + +static void _do_request(struct rt_smp_call_req *req) +{ + struct rt_smp_event *event; + + event = &req->event; + RT_ASSERT(!!event->func); + event->func(event->data); + + _call_req_release(req); + return ; +} + +static rt_err_t _smp_call_handler(struct rt_smp_call_req *req, int oncpu) +{ + switch (req->event.event_id) + { + case SMP_CALL_EVENT_GLOB_SYNC: + { + struct rt_smp_call_req req_local; + _do_glob_request(req, &req_local); + _mask_out_cpu(&req_local.event, oncpu); + break; + } + case SMP_CALL_EVENT_GLOB_ASYNC: + { + struct rt_smp_call_req req_local; + _do_glob_request(req, &req_local); + break; + } + case SMP_CALL_EVENT_REQUEST: + { + _do_request(req); + break; + } + default: + LOG_E("error event id\n"); + return -RT_ERROR; + } + return RT_EOK; +} + +void rt_smp_call_ipi_handler(int vector, void *param) +{ + int oncpu = rt_hw_cpu_id(); + struct rt_smp_call_req *request; + + RT_ASSERT(rt_interrupt_get_nest()); + + while (1) + { + rt_ll_slist_t *node = rt_ll_slist_dequeue(&_smp_data_cores[oncpu].call_queue); + if (node) + { + request = rt_list_entry(node, struct rt_smp_call_req, slist_node); + + _smp_call_handler(request, oncpu); + } + else + { + break; + } + } +} + +static void _smp_call_remote_request(int callcpu, rt_smp_call_cb_t func, + void *data, rt_uint8_t flags, + struct rt_smp_call_req *call_req) +{ + rt_base_t cpu_mask = 1ul << callcpu; + + _call_req_take(call_req); + + rt_ll_slist_enqueue(&_smp_data_cores[callcpu].call_queue, &call_req->slist_node); + + rt_hw_ipi_send(RT_SMP_CALL_IPI, cpu_mask); +} + +/** + * @brief SMP call request with user provided @call_req. Compare to + * rt_smp_call_func* family, you can call it in ISR or IRQ-masked + * environment. + * + * @param callcpu the logical core id of the target + * @param flags control flags of your request + * @param call_req the pre-initialized request data + * @return rt_err_t RT_EOK on succeed, otherwise the errno to failure + */ +rt_err_t rt_smp_call_request(int callcpu, rt_uint8_t flags, struct rt_smp_call_req *call_req) +{ + rt_ubase_t clvl; + int oncpu; + + if (rt_atomic_load(&call_req->event.typed.usage_tracer) == + _CALL_REQ_USAGE_BUSY) + { + return -RT_EBUSY; + } + + if (flags & SMP_CALL_WAIT_ALL) + { + return -RT_EINVAL; + } + + clvl = rt_enter_critical(); + oncpu = rt_hw_cpu_id(); + + if (oncpu == callcpu && !(flags & SMP_CALL_NO_LOCAL)) + { + rt_ubase_t level; + + /* handle IPI on irq-masked environment */ + level = rt_hw_local_irq_disable(); + call_req->event.func(call_req->event.data); + rt_hw_local_irq_enable(level); + } + else if (callcpu < RT_CPUS_NR) + { + _smp_call_remote_request(callcpu, call_req->event.func, call_req->event.data, flags, call_req); + } + + rt_exit_critical_safe(clvl); + + return RT_EOK; +} + +void rt_smp_call_req_init(struct rt_smp_call_req *call_req, + rt_smp_call_cb_t func, void *data) +{ + call_req->event.typed.usage_tracer = 0; + call_req->event.data = data; + call_req->event.func = func; + call_req->event.event_id = SMP_CALL_EVENT_REQUEST; +} + +static void _smp_call_func_cond(int oncpu, rt_ubase_t cpu_mask, + rt_smp_call_cb_t func, void *data, + rt_uint8_t flags, rt_smp_cond_t cond) +{ + rt_ubase_t tmp_mask; + rt_bool_t sync_call = RT_FALSE; + rt_ubase_t oncpu_mask = 1 << oncpu; + rt_atomic_t calling_cpu_mask, *maskp; + int tmp_id = 0, rcpu_cnt = 0, event_id, call_local; + + if (!(flags & SMP_CALL_NO_LOCAL) && (oncpu_mask & cpu_mask)) + { + call_local = RT_TRUE; + cpu_mask = cpu_mask & (~oncpu_mask); + } + else + { + call_local = RT_FALSE; + } + + if (cpu_mask) + { + tmp_mask = cpu_mask; + + if (flags & SMP_CALL_WAIT_ALL) + { + sync_call = RT_TRUE; + maskp = &calling_cpu_mask; + event_id = SMP_CALL_EVENT_GLOB_SYNC; + rt_atomic_store(maskp, cpu_mask); + } + else + { + event_id = SMP_CALL_EVENT_GLOB_ASYNC; + maskp = RT_NULL; + } + + while (tmp_mask) + { + struct rt_smp_call_req *call_req; + struct rt_smp_event *event; + int lz_bit = __rt_ffsl(tmp_mask); + + tmp_id = lz_bit - 1; + tmp_mask &= ~(1ul << tmp_id); + + if (cond && !cond(tmp_id, data)) + { + cpu_mask &= ~(1ul << tmp_id); + continue; + } + + /* need to wait one more */ + rcpu_cnt++; + + call_req = &_smp_data_cores[oncpu].call_req_cores[tmp_id]; + + /* very careful here, spinning wait on previous occupation */ + rt_hw_spin_lock(&call_req->freed_lock); + + event = &call_req->event; + event->event_id = event_id; + event->func = func; + event->data = data; + event->typed.calling_cpu_mask = maskp; + + rt_ll_slist_enqueue(&_smp_data_cores[tmp_id].call_queue, &call_req->slist_node); + } + + if (cpu_mask) + { + RT_ASSERT(rcpu_cnt); + + rt_hw_ipi_send(RT_SMP_CALL_IPI, cpu_mask); + } + } + + if (call_local && (!cond || cond(tmp_id, data))) + { + rt_ubase_t level; + + /* callback on local with sims ISR */ + level = rt_hw_local_irq_disable(); + func(data); + rt_hw_local_irq_enable(level); + } + + if (sync_call && rcpu_cnt) + { + while (rt_atomic_load(maskp) & cpu_mask) + ; + } +} + +/** + * @brief call function on specified CPU , + * + * @param cpu_mask cpu mask for call + * @param func the function pointer + * @param data the data pointer + * @param flag call flag if you set SMP_CALL_WAIT_ALL + * then it will wait all cpu call finish and return + * else it will call function on specified CPU and return immediately + * @param cond the condition function pointer,if you set it then it will call function only when cond return true + */ +void rt_smp_call_func_cond(rt_ubase_t cpu_mask, rt_smp_call_cb_t func, void *data, rt_uint8_t flag, rt_smp_cond_t cond) +{ + int oncpu; + rt_ubase_t clvl; + + RT_ASSERT(!rt_hw_interrupt_is_disabled()); + + clvl = rt_enter_critical(); + oncpu = rt_hw_cpu_id(); + + if (cpu_mask <= RT_ALL_CPU) + { + _smp_call_func_cond(oncpu, cpu_mask, func, data, flag, cond); + } + + rt_exit_critical_safe(clvl); +} + +void rt_smp_call_each_cpu(rt_smp_call_cb_t func, void *data, rt_uint8_t flag) +{ + rt_smp_call_func_cond(RT_ALL_CPU, func, data, flag, RT_NULL); +} + +void rt_smp_call_each_cpu_cond(rt_smp_call_cb_t func, void *data, rt_uint8_t flag, rt_smp_cond_t cond_func) +{ + rt_smp_call_func_cond(RT_ALL_CPU, func, data, flag, cond_func); +} + +void rt_smp_call_cpu_mask(rt_ubase_t cpu_mask, rt_smp_call_cb_t func, void *data, rt_uint8_t flag) +{ + rt_smp_call_func_cond(cpu_mask, func, data, flag, RT_NULL); +} + +void rt_smp_call_cpu_mask_cond(rt_ubase_t cpu_mask, rt_smp_call_cb_t func, void *data, rt_uint8_t flag, rt_smp_cond_t cond_func) +{ + rt_smp_call_func_cond(cpu_mask, func, data, flag, cond_func); +} + +void rt_smp_call_init(void) +{ + rt_memset(&_smp_data_cores, 0, sizeof(_smp_data_cores)); + + for (int i = 0; i < RT_CPUS_NR; i++) + { + for (int j = 0; j < RT_CPUS_NR; j++) + { + rt_hw_spin_lock_init(&_smp_data_cores[i].call_req_cores[j].freed_lock); + } + } +} diff --git a/rt-thread/components/drivers/smp_call/smp_call.h b/rt-thread/components/drivers/smp_call/smp_call.h new file mode 100644 index 0000000..0ff9dd3 --- /dev/null +++ b/rt-thread/components/drivers/smp_call/smp_call.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/9/12 zhujiale the first version + * 2024/10/24 Shell added non-blocking IPI calling method + */ + +#ifndef __SMP_IPI_H__ +#define __SMP_IPI_H__ +#include + +#ifdef RT_USING_SMP + +/* callback of smp call */ +typedef void (*rt_smp_call_cb_t)(void *data); +typedef rt_bool_t (*rt_smp_cond_t)(int cpu, void *info); + +#define SMP_CALL_EVENT_GLOB_ASYNC 0x1 +#define SMP_CALL_EVENT_GLOB_SYNC 0x2 +#define SMP_CALL_EVENT_REQUEST 0x4 + +#define SMP_CALL_WAIT_ALL (1ul << 0) +#define SMP_CALL_NO_LOCAL (1ul << 1) +#define SMP_CALL_SIGNAL (1ul << 2) + +#define RT_ALL_CPU ((1 << RT_CPUS_NR) - 1) +struct rt_smp_event +{ + int event_id; + void *data; + rt_smp_call_cb_t func; + + union + { + rt_atomic_t *calling_cpu_mask; + rt_atomic_t usage_tracer; + } typed; +}; + +struct rt_smp_call_req +{ + /* handle the busy status synchronization */ + rt_hw_spinlock_t freed_lock; + struct rt_smp_event event; + rt_ll_slist_t slist_node; +}; + +void rt_smp_call_ipi_handler(int vector, void *param); +void rt_smp_call_each_cpu(rt_smp_call_cb_t func, void *data, rt_uint8_t flags); +void rt_smp_call_each_cpu_cond(rt_smp_call_cb_t func, void *data, rt_uint8_t flag, rt_smp_cond_t cond_func); +void rt_smp_call_cpu_mask(rt_ubase_t cpu_mask, rt_smp_call_cb_t func, void *data, rt_uint8_t flags); +void rt_smp_call_cpu_mask_cond(rt_ubase_t cpu_mask, rt_smp_call_cb_t func, void *data, rt_uint8_t flag, rt_smp_cond_t cond_func); +void rt_smp_call_init(void); + +rt_err_t rt_smp_call_request(int callcpu, rt_uint8_t flags, struct rt_smp_call_req *call_req); +void rt_smp_call_req_init(struct rt_smp_call_req *call_req, + rt_smp_call_cb_t func, void *data); +void rt_smp_request_wait_freed(struct rt_smp_call_req *req); + +#define rt_smp_for_each_cpu(_iter) for (_iter = 0; (_iter) < RT_CPUS_NR; (_iter)++) +rt_inline size_t rt_smp_get_next_remote(size_t iter, size_t cpuid) +{ + iter++; + return iter == cpuid ? iter + 1 : iter; +} +#define rt_smp_for_each_remote_cpu(_iter, _cpuid) for (_iter = rt_smp_get_next_remote(-1, _cpuid); (_iter) < RT_CPUS_NR; _iter=rt_smp_get_next_remote(_iter, _cpuid)) + +#endif // RT_USING_SMP + +#endif // __SMP_IPI_H__ diff --git a/rt-thread/components/drivers/spi/SConscript b/rt-thread/components/drivers/spi/SConscript index cea447f..6897dab 100644 --- a/rt-thread/components/drivers/spi/SConscript +++ b/rt-thread/components/drivers/spi/SConscript @@ -3,29 +3,29 @@ from gcc import * import rtconfig cwd = GetCurrentDir() -src = ['spi_core.c', 'spi_dev.c'] +src = ['dev_spi_core.c', 'dev_spi.c'] CPPPATH = [cwd, cwd + '/../include'] LOCAL_CFLAGS = '' if GetDepend('RT_USING_SPI_BITOPS'): - src += ['spi-bit-ops.c'] + src += ['dev_spi_bit_ops.c'] if GetDepend('RT_USING_QSPI'): - src += ['qspi_core.c'] + src += ['dev_qspi_core.c'] src_device = [] if GetDepend('RT_USING_SPI_WIFI'): - src_device += ['spi_wifi_rw009.c'] + src_device += ['dev_spi_wifi_rw009.c'] if GetDepend('RT_USING_ENC28J60'): src_device += ['enc28j60.c'] if GetDepend('RT_USING_SPI_MSD'): - src_device += ['spi_msd.c'] + src_device += ['dev_spi_msd.c'] if GetDepend('RT_USING_SFUD'): - src_device += ['spi_flash_sfud.c', 'sfud/src/sfud.c'] + src_device += ['dev_spi_flash_sfud.c', 'sfud/src/sfud.c'] CPPPATH += [cwd + '/sfud/inc'] if GetDepend('RT_SFUD_USING_SFDP'): src_device += ['sfud/src/sfud_sfdp.c'] @@ -35,6 +35,9 @@ if GetDepend('RT_USING_SFUD'): elif rtconfig.PLATFORM in ['armcc']: LOCAL_CFLAGS += ' --c99' +if GetDepend('RT_USING_DM'): + src += ['dev_spi_dm.c', 'dev_spi_bus.c'] + src += src_device group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_SPI'], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS) diff --git a/rt-thread/components/drivers/spi/qspi_core.c b/rt-thread/components/drivers/spi/dev_qspi_core.c similarity index 93% rename from rt-thread/components/drivers/spi/qspi_core.c rename to rt-thread/components/drivers/spi/dev_qspi_core.c index cd40c51..9dd2c5f 100644 --- a/rt-thread/components/drivers/spi/qspi_core.c +++ b/rt-thread/components/drivers/spi/dev_qspi_core.c @@ -8,7 +8,7 @@ * 2018-11-16 zylx first version. */ -#include +#include "drivers/dev_spi.h" rt_err_t rt_qspi_configure(struct rt_qspi_device *device, struct rt_qspi_configuration *cfg) { @@ -18,10 +18,23 @@ rt_err_t rt_qspi_configure(struct rt_qspi_device *device, struct rt_qspi_configu /* reset the CS pin */ if (device->parent.cs_pin != PIN_NONE) { - if (cfg->parent.mode & RT_SPI_CS_HIGH) - rt_pin_write(device->parent.cs_pin, PIN_LOW); + rt_err_t result = rt_mutex_take(&(device->parent.bus->lock), RT_WAITING_FOREVER); + if (result == RT_EOK) + { + if (cfg->parent.mode & RT_SPI_CS_HIGH) + { + rt_pin_write(device->parent.cs_pin, PIN_LOW); + } + else + { + rt_pin_write(device->parent.cs_pin, PIN_HIGH); + } + rt_mutex_release(&(device->parent.bus->lock)); + } else - rt_pin_write(device->parent.cs_pin, PIN_HIGH); + { + return result; + } } /* If the configurations are the same, we don't need to set again. */ diff --git a/rt-thread/components/drivers/spi/spi_dev.c b/rt-thread/components/drivers/spi/dev_spi.c similarity index 69% rename from rt-thread/components/drivers/spi/spi_dev.c rename to rt-thread/components/drivers/spi/dev_spi.c index 963b70c..3f55fd0 100644 --- a/rt-thread/components/drivers/spi/spi_dev.c +++ b/rt-thread/components/drivers/spi/dev_spi.c @@ -8,7 +8,15 @@ */ #include -#include +#include "drivers/dev_spi.h" + +#define DBG_TAG "spi.dev" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_DM +#include "dev_spi_dm.h" +#endif /* SPI bus device interface, compatible with RT-Thread 0.3.x/1.0.x */ static rt_ssize_t _spi_bus_device_read(rt_device_t dev, @@ -155,3 +163,66 @@ rt_err_t rt_spidev_device_init(struct rt_spi_device *dev, const char *name) /* register to device manager */ return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR); } + +#ifdef RT_USING_DM +static rt_err_t spidev_probe(struct rt_spi_device *spi_dev) +{ + const char *bus_name; + struct rt_device *dev = &spi_dev->parent; + + if (spi_dev->parent.ofw_node) + { + if (rt_dm_dev_prop_index_of_string(dev, "compatible", "spidev") >= 0) + { + LOG_E("spidev is not supported in OFW"); + + return -RT_EINVAL; + } + } + + bus_name = rt_dm_dev_get_name(&spi_dev->bus->parent); + rt_dm_dev_set_name(dev, "%s_%d", bus_name, spi_dev->chip_select); + + return RT_EOK; +} + +static const struct rt_spi_device_id spidev_ids[] = +{ + { .name = "dh2228fv" }, + { .name = "ltc2488" }, + { .name = "sx1301" }, + { .name = "bk4" }, + { .name = "dhcom-board" }, + { .name = "m53cpld" }, + { .name = "spi-petra" }, + { .name = "spi-authenta" }, + { .name = "em3581" }, + { .name = "si3210" }, + { /* sentinel */ }, +}; + +static const struct rt_ofw_node_id spidev_ofw_ids[] = +{ + { .compatible = "cisco,spi-petra" }, + { .compatible = "dh,dhcom-board" }, + { .compatible = "lineartechnology,ltc2488" }, + { .compatible = "lwn,bk4" }, + { .compatible = "menlo,m53cpld" }, + { .compatible = "micron,spi-authenta" }, + { .compatible = "rohm,dh2228fv" }, + { .compatible = "semtech,sx1301" }, + { .compatible = "silabs,em3581" }, + { .compatible = "silabs,si3210" }, + { .compatible = "rockchip,spidev" }, + { /* sentinel */ }, +}; + +static struct rt_spi_driver spidev_driver = +{ + .ids = spidev_ids, + .ofw_ids = spidev_ofw_ids, + + .probe = spidev_probe, +}; +RT_SPI_DRIVER_EXPORT(spidev_driver); +#endif /* RT_USING_DM */ diff --git a/rt-thread/components/drivers/spi/spi-bit-ops.c b/rt-thread/components/drivers/spi/dev_spi_bit_ops.c similarity index 90% rename from rt-thread/components/drivers/spi/spi-bit-ops.c rename to rt-thread/components/drivers/spi/dev_spi_bit_ops.c index f551741..d2a26a7 100644 --- a/rt-thread/components/drivers/spi/spi-bit-ops.c +++ b/rt-thread/components/drivers/spi/dev_spi_bit_ops.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2021-10-11 kyle first version */ -#include +#include #include #define DBG_TAG "SPI" @@ -423,6 +423,7 @@ rt_ssize_t spi_bit_xfer(struct rt_spi_device *device, struct rt_spi_message *mes struct rt_spi_bit_ops *ops = obj->ops; struct rt_spi_configuration *config = &obj->config; rt_base_t cs_pin = device->cs_pin; + rt_ssize_t length = 0; RT_ASSERT(device != NULL); RT_ASSERT(message != NULL); @@ -443,10 +444,17 @@ rt_ssize_t spi_bit_xfer(struct rt_spi_device *device, struct rt_spi_message *mes #endif /* take CS */ - if (message->cs_take && (cs_pin != PIN_NONE)) + if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (cs_pin != PIN_NONE)) { LOG_I("spi take cs\n"); - rt_pin_write(cs_pin, PIN_LOW); + if (device->config.mode & RT_SPI_CS_HIGH) + { + rt_pin_write(cs_pin, PIN_HIGH); + } + else + { + rt_pin_write(cs_pin, PIN_LOW); + } spi_delay(ops); /* spi phase */ @@ -461,50 +469,41 @@ rt_ssize_t spi_bit_xfer(struct rt_spi_device *device, struct rt_spi_message *mes { if (config->data_width <= 8) { - spi_xfer_3line_data8(ops, - config, - message->send_buf, - message->recv_buf, - message->length); + length = spi_xfer_3line_data8(ops, config, message->send_buf, message->recv_buf, message->length); } else if (config->data_width <= 16) { - spi_xfer_3line_data16(ops, - config, - message->send_buf, - message->recv_buf, - message->length); + length = spi_xfer_3line_data16(ops, config, message->send_buf, message->recv_buf, message->length); } } else { if (config->data_width <= 8) { - spi_xfer_4line_data8(ops, - config, - message->send_buf, - message->recv_buf, - message->length); + length = spi_xfer_4line_data8(ops, config, message->send_buf, message->recv_buf, message->length); } else if (config->data_width <= 16) { - spi_xfer_4line_data16(ops, - config, - message->send_buf, - message->recv_buf, - message->length); + length = spi_xfer_4line_data16(ops, config, message->send_buf, message->recv_buf, message->length); } } /* release CS */ - if (message->cs_release && (cs_pin != PIN_NONE)) + if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (cs_pin != PIN_NONE)) { spi_delay(ops); - rt_pin_write(cs_pin, PIN_HIGH); + if (device->config.mode & RT_SPI_CS_HIGH) + { + rt_pin_write(cs_pin, PIN_LOW); + } + else + { + rt_pin_write(cs_pin, PIN_HIGH); + } LOG_I("spi release cs\n"); } - return message->length; + return length; } static const struct rt_spi_ops spi_bit_bus_ops = @@ -522,9 +521,5 @@ rt_err_t rt_spi_bit_add_bus(struct rt_spi_bit_obj *obj, obj->config.max_hz = 1 * 1000 * 1000; obj->config.mode = RT_SPI_MASTER | RT_SPI_MSB | RT_SPI_MODE_0; - /* idle status */ - if (obj->config.mode & RT_SPI_CPOL) SCLK_H(ops); - else SCLK_L(ops); - return rt_spi_bus_register(&obj->bus, bus_name, &spi_bit_bus_ops); } diff --git a/rt-thread/components/drivers/spi/spi-bit-ops.h b/rt-thread/components/drivers/spi/dev_spi_bit_ops.h similarity index 95% rename from rt-thread/components/drivers/spi/spi-bit-ops.h rename to rt-thread/components/drivers/spi/dev_spi_bit_ops.h index d1e83cd..cf2335e 100644 --- a/rt-thread/components/drivers/spi/spi-bit-ops.h +++ b/rt-thread/components/drivers/spi/dev_spi_bit_ops.h @@ -9,8 +9,8 @@ * 2022-6-14 solar Remove the const attribute of private data in ops */ -#ifndef __SPI_BIT_OPS_H__ -#define __SPI_BIT_OPS_H__ +#ifndef __DEV_SPI_BIT_OPS_H__ +#define __DEV_SPI_BIT_OPS_H__ #include diff --git a/rt-thread/components/drivers/spi/dev_spi_bus.c b/rt-thread/components/drivers/spi/dev_spi_bus.c new file mode 100644 index 0000000..34aa298 --- /dev/null +++ b/rt-thread/components/drivers/spi/dev_spi_bus.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-12-06 GuEe-GUI first version + */ + +#include "dev_spi_dm.h" + +#define DBG_TAG "spi.bus" +#define DBG_LVL DBG_INFO +#include + +extern rt_err_t rt_spidev_device_init(struct rt_spi_device *dev, const char *name); + +static struct rt_bus spi_bus; + +void spi_bus_scan_devices(struct rt_spi_bus *bus) +{ +#ifdef RT_USING_OFW + if (bus->parent.ofw_node) + { + struct rt_ofw_node *np = bus->parent.ofw_node, *spi_dev_np; + + rt_ofw_foreach_available_child_node(np, spi_dev_np) + { + rt_uint64_t reg_offset; + struct rt_spi_device *spi_dev; + + if (!rt_ofw_prop_read_bool(spi_dev_np, "compatible")) + { + continue; + } + + spi_dev = rt_calloc(1, sizeof(*spi_dev)); + + if (!spi_dev) + { + rt_ofw_node_put(spi_dev_np); + LOG_E("Not memory to create spi device: %s", + rt_ofw_node_full_name(spi_dev_np)); + + return; + } + + rt_ofw_get_address(spi_dev_np, 0, ®_offset, RT_NULL); + + spi_dev->parent.ofw_node = spi_dev_np; + spi_dev->parent.type = RT_Device_Class_Unknown; + spi_dev->name = rt_ofw_node_name(spi_dev_np); + spi_dev->bus = bus; + + rt_dm_dev_set_name(&spi_dev->parent, rt_ofw_node_full_name(spi_dev_np)); + + if (spi_device_ofw_parse(spi_dev)) + { + continue; + } + + rt_spi_device_register(spi_dev); + } + } +#endif /* RT_USING_OFW */ +} + +rt_err_t rt_spi_driver_register(struct rt_spi_driver *driver) +{ + RT_ASSERT(driver != RT_NULL); + + driver->parent.bus = &spi_bus; + + return rt_driver_register(&driver->parent); +} + +rt_err_t rt_spi_device_register(struct rt_spi_device *device) +{ + RT_ASSERT(device != RT_NULL); + + return rt_bus_add_device(&spi_bus, &device->parent); +} + +static rt_bool_t spi_match(rt_driver_t drv, rt_device_t dev) +{ + const struct rt_spi_device_id *id; + struct rt_spi_driver *driver = rt_container_of(drv, struct rt_spi_driver, parent); + struct rt_spi_device *device = rt_container_of(dev, struct rt_spi_device, parent); + + if ((id = driver->ids)) + { + for (; id->name[0]; ++id) + { + if (!rt_strcmp(id->name, device->name)) + { + device->id = id; + device->ofw_id = RT_NULL; + + return RT_TRUE; + } + } + } + +#ifdef RT_USING_OFW + device->ofw_id = rt_ofw_node_match(device->parent.ofw_node, driver->ofw_ids); + + if (device->ofw_id) + { + device->id = RT_NULL; + + return RT_TRUE; + } +#endif + + return RT_FALSE; +} + +static rt_err_t spi_probe(rt_device_t dev) +{ + rt_err_t err; + struct rt_spi_bus *bus; + struct rt_spi_driver *driver = rt_container_of(dev->drv, struct rt_spi_driver, parent); + struct rt_spi_device *device = rt_container_of(dev, struct rt_spi_device, parent); + + if (!device->bus) + { + return -RT_EINVAL; + } + + err = driver->probe(device); + + if (err) + { + return err; + } + + bus = device->bus; + + if (bus->pins) + { + device->cs_pin = bus->pins[device->chip_select]; + + rt_pin_mode(device->cs_pin, PIN_MODE_OUTPUT); + } + else + { + device->cs_pin = PIN_NONE; + } + + /* Driver not register SPI device to system */ + if (device->parent.type == RT_Device_Class_Unknown) + { + rt_spidev_device_init(device, rt_dm_dev_get_name(&device->parent)); + } + + return err; +} + +static rt_err_t spi_remove(rt_device_t dev) +{ + struct rt_spi_driver *driver = rt_container_of(dev->drv, struct rt_spi_driver, parent); + struct rt_spi_device *device = rt_container_of(dev, struct rt_spi_device, parent); + + if (driver && driver->remove) + { + driver->remove(device); + } + rt_free(device); + + return RT_EOK; +} + +static rt_err_t spi_shutdown(rt_device_t dev) +{ + struct rt_spi_driver *driver = rt_container_of(dev->drv, struct rt_spi_driver, parent); + struct rt_spi_device *device = rt_container_of(dev, struct rt_spi_device, parent); + + if (driver && driver->shutdown) + { + driver->shutdown(device); + } + rt_free(device); + + return RT_EOK; +} + +static struct rt_bus spi_bus = +{ + .name = "spi", + .match = spi_match, + .probe = spi_probe, + .remove = spi_remove, + .shutdown = spi_shutdown, +}; + +static int spi_bus_init(void) +{ + rt_bus_register(&spi_bus); + + return 0; +} +INIT_CORE_EXPORT(spi_bus_init); diff --git a/rt-thread/components/drivers/spi/spi_core.c b/rt-thread/components/drivers/spi/dev_spi_core.c similarity index 89% rename from rt-thread/components/drivers/spi/spi_core.c rename to rt-thread/components/drivers/spi/dev_spi_core.c index d9d4221..d84aaac 100644 --- a/rt-thread/components/drivers/spi/spi_core.c +++ b/rt-thread/components/drivers/spi/dev_spi_core.c @@ -13,12 +13,16 @@ * 2012-09-28 aozima fixed rt_spi_release_bus assert error. */ -#include +#include "drivers/dev_spi.h" #define DBG_TAG "spi.core" #define DBG_LVL DBG_INFO #include +#ifdef RT_USING_DM +#include "dev_spi_dm.h" +#endif + extern rt_err_t rt_spi_bus_device_init(struct rt_spi_bus *bus, const char *name); extern rt_err_t rt_spidev_device_init(struct rt_spi_device *dev, const char *name); @@ -41,6 +45,46 @@ rt_err_t rt_spi_bus_register(struct rt_spi_bus *bus, /* set bus mode */ bus->mode = RT_SPI_BUS_MODE_SPI; +#ifdef RT_USING_DM + if (!bus->slave) + { + int pin_count = rt_pin_get_named_pin_count(&bus->parent, "cs"); + + if (pin_count > 0) + { + pin_count = rt_max_t(int, pin_count, bus->num_chipselect); + bus->pins = rt_malloc(sizeof(bus->pins[0]) * pin_count); + + if (!bus->pins) + { + rt_device_unregister(&bus->parent); + return -RT_ENOMEM; + } + + for (int i = 0; i < pin_count; ++i) + { + bus->pins[i] = rt_pin_get_named_pin(&bus->parent, "cs", i, + RT_NULL, RT_NULL); + } + } + else if (pin_count == 0) + { + bus->pins = RT_NULL; + } + else + { + result = pin_count; + + LOG_E("CS PIN find error = %s", rt_strerror(result)); + + rt_device_unregister(&bus->parent); + return result; + } + } + + spi_bus_scan_devices(bus); +#endif + return RT_EOK; } @@ -106,6 +150,13 @@ rt_err_t rt_spi_bus_configure(struct rt_spi_device *device) LOG_E("SPI device %s configuration failed", device->parent.parent.name); } } + else + { + /* RT_EBUSY is not an error condition and + * the configuration will take effect once the device has the bus + */ + result = -RT_EBUSY; + } /* release lock */ rt_mutex_release(&(device->bus->lock)); @@ -128,10 +179,23 @@ rt_err_t rt_spi_configure(struct rt_spi_device *device, /* reset the CS pin */ if (device->cs_pin != PIN_NONE) { - if (cfg->mode & RT_SPI_CS_HIGH) - rt_pin_write(device->cs_pin, PIN_LOW); + rt_err_t result = rt_mutex_take(&(device->bus->lock), RT_WAITING_FOREVER); + if (result == RT_EOK) + { + if (cfg->mode & RT_SPI_CS_HIGH) + { + rt_pin_write(device->cs_pin, PIN_LOW); + } + else + { + rt_pin_write(device->cs_pin, PIN_HIGH); + } + rt_mutex_release(&(device->bus->lock)); + } else - rt_pin_write(device->cs_pin, PIN_HIGH); + { + return result; + } } /* If the configurations are the same, we don't need to set again. */ diff --git a/rt-thread/components/drivers/spi/dev_spi_dm.c b/rt-thread/components/drivers/spi/dev_spi_dm.c new file mode 100644 index 0000000..063615c --- /dev/null +++ b/rt-thread/components/drivers/spi/dev_spi_dm.c @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-12-06 GuEe-GUI first version + */ + +#include "dev_spi_dm.h" + +#define DBG_TAG "spi.dm" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_OFW +static void ofw_parse_delay(struct rt_ofw_node *np, struct rt_spi_delay *delay, + const char *prop) +{ + rt_uint32_t value; + + if (!rt_ofw_prop_read_u32(np, prop, &value)) + { + if (value > RT_UINT16_MAX) + { + delay->value = RT_DIV_ROUND_UP(value, 1000); + delay->unit = RT_SPI_DELAY_UNIT_USECS; + } + else + { + delay->value = value; + delay->unit = RT_SPI_DELAY_UNIT_NSECS; + } + } +} + +rt_err_t spi_device_ofw_parse(struct rt_spi_device *spi_dev) +{ + rt_err_t err; + rt_uint32_t value; + struct rt_spi_bus *spi_bus = spi_dev->bus; + struct rt_ofw_node *np = spi_dev->parent.ofw_node; + struct rt_spi_configuration *conf = &spi_dev->config; + + if (rt_ofw_prop_read_bool(np, "spi-cpha")) + { + conf->mode |= RT_SPI_CPHA; + } + if (rt_ofw_prop_read_bool(np, "spi-cpol")) + { + conf->mode |= RT_SPI_CPOL; + } + if (rt_ofw_prop_read_bool(np, "spi-3wire")) + { + conf->mode |= RT_SPI_3WIRE; + } + if (rt_ofw_prop_read_bool(np, "spi-lsb-first")) + { + conf->mode |= RT_SPI_LSB; + } + if (rt_ofw_prop_read_bool(np, "spi-cs-high")) + { + conf->mode |= RT_SPI_CS_HIGH; + } + + value = 1; + rt_ofw_prop_read_u32(np, "spi-tx-bus-width", &value); + conf->data_width_tx = value; + + value = 1; + rt_ofw_prop_read_u32(np, "spi-rx-bus-width", &value); + conf->data_width_rx = value; + + if (spi_bus->slave) + { + if (!rt_ofw_node_tag_equ(np, "slave")) + { + LOG_E("Invalid SPI device = %s", rt_ofw_node_full_name(np)); + + return -RT_EINVAL; + } + + return RT_EOK; + } + + if ((err = rt_ofw_prop_read_u32(np, "reg", &value))) + { + LOG_E("Find 'reg' failed"); + + return err; + } + spi_dev->chip_select = value; + + if (!rt_ofw_prop_read_u32(np, "spi-max-frequency", &value)) + { + conf->max_hz = value; + } + + ofw_parse_delay(np, &spi_dev->cs_setup, "spi-cs-setup-delay-ns"); + ofw_parse_delay(np, &spi_dev->cs_hold, "spi-cs-hold-delay-ns"); + ofw_parse_delay(np, &spi_dev->cs_inactive, "spi-cs-inactive-delay-ns"); + + return RT_EOK; +} +#endif /* RT_USING_OFW */ diff --git a/rt-thread/components/drivers/spi/dev_spi_dm.h b/rt-thread/components/drivers/spi/dev_spi_dm.h new file mode 100644 index 0000000..c124295 --- /dev/null +++ b/rt-thread/components/drivers/spi/dev_spi_dm.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-11-26 GuEe-GUI first version + */ + +#ifndef __DEV_SPI_DM_H__ +#define __DEV_SPI_DM_H__ + +#include +#include +#include + +#ifdef RT_USING_OFW +rt_err_t spi_device_ofw_parse(struct rt_spi_device *spi_dev); +#else +rt_inline rt_err_t spi_device_ofw_parse(struct rt_spi_device *spi_dev) +{ + return RT_EOK; +} +#endif /* RT_USING_OFW */ + +void spi_bus_scan_devices(struct rt_spi_bus *bus); + +#endif /* __DEV_SPI_DM_H__ */ diff --git a/rt-thread/components/drivers/spi/spi_flash.h b/rt-thread/components/drivers/spi/dev_spi_flash.h similarity index 93% rename from rt-thread/components/drivers/spi/spi_flash.h rename to rt-thread/components/drivers/spi/dev_spi_flash.h index 2651c76..5ae54c4 100644 --- a/rt-thread/components/drivers/spi/spi_flash.h +++ b/rt-thread/components/drivers/spi/dev_spi_flash.h @@ -9,8 +9,8 @@ * 2020/1/7 redoc add include */ -#ifndef SPI_FLASH_H__ -#define SPI_FLASH_H__ +#ifndef __DEV_SPI_FLASH_H__ +#define __DEV_SPI_FLASH_H__ #include diff --git a/rt-thread/components/drivers/spi/spi_flash_sfud.c b/rt-thread/components/drivers/spi/dev_spi_flash_sfud.c similarity index 99% rename from rt-thread/components/drivers/spi/spi_flash_sfud.c rename to rt-thread/components/drivers/spi/dev_spi_flash_sfud.c index 761c9cc..e1c90db 100644 --- a/rt-thread/components/drivers/spi/spi_flash_sfud.c +++ b/rt-thread/components/drivers/spi/dev_spi_flash_sfud.c @@ -11,8 +11,8 @@ #include #include #include -#include "spi_flash.h" -#include "spi_flash_sfud.h" +#include "dev_spi_flash.h" +#include "dev_spi_flash_sfud.h" #ifdef RT_USING_SFUD diff --git a/rt-thread/components/drivers/spi/spi_flash_sfud.h b/rt-thread/components/drivers/spi/dev_spi_flash_sfud.h similarity index 88% rename from rt-thread/components/drivers/spi/spi_flash_sfud.h rename to rt-thread/components/drivers/spi/dev_spi_flash_sfud.h index 6099c98..5c3236f 100644 --- a/rt-thread/components/drivers/spi/spi_flash_sfud.h +++ b/rt-thread/components/drivers/spi/dev_spi_flash_sfud.h @@ -6,15 +6,20 @@ * Change Logs: * Date Author Notes * 2016-09-28 armink first version. + * 2024-10-24 yekai Add C++ support */ -#ifndef _SPI_FLASH_SFUD_H_ -#define _SPI_FLASH_SFUD_H_ +#ifndef __DEV_SPI_FLASH_SFUD_H__ +#define __DEV_SPI_FLASH_SFUD_H__ #include #include #include "./sfud/inc/sfud.h" -#include "spi_flash.h" +#include "dev_spi_flash.h" + +#ifdef __cplusplus +extern "C" { +#endif /** * Probe SPI flash by SFUD(Serial Flash Universal Driver) driver library and though SPI device. @@ -66,4 +71,8 @@ sfud_flash_t rt_sfud_flash_find(const char *spi_dev_name); */ sfud_flash_t rt_sfud_flash_find_by_dev_name(const char *flash_dev_name); -#endif /* _SPI_FLASH_SFUD_H_ */ +#ifdef __cplusplus +} +#endif + +#endif /* __DEV_SPI_FLASH_SFUD_H__ */ diff --git a/rt-thread/components/drivers/spi/spi_msd.c b/rt-thread/components/drivers/spi/dev_spi_msd.c similarity index 99% rename from rt-thread/components/drivers/spi/spi_msd.c rename to rt-thread/components/drivers/spi/dev_spi_msd.c index 0ca1bdf..8d81e34 100644 --- a/rt-thread/components/drivers/spi/spi_msd.c +++ b/rt-thread/components/drivers/spi/dev_spi_msd.c @@ -14,7 +14,7 @@ */ #include -#include "spi_msd.h" +#include "dev_spi_msd.h" //#define MSD_TRACE diff --git a/rt-thread/components/drivers/spi/spi_msd.h b/rt-thread/components/drivers/spi/dev_spi_msd.h similarity index 97% rename from rt-thread/components/drivers/spi/spi_msd.h rename to rt-thread/components/drivers/spi/dev_spi_msd.h index 2b66be7..7304b13 100644 --- a/rt-thread/components/drivers/spi/spi_msd.h +++ b/rt-thread/components/drivers/spi/dev_spi_msd.h @@ -8,12 +8,12 @@ * 2009-04-17 Bernard first version. */ -#ifndef SPI_MSD_H_INCLUDED -#define SPI_MSD_H_INCLUDED +#ifndef __DEV_SPI_MSD_H_INCLUDED__ +#define __DEV_SPI_MSD_H_INCLUDED__ #include #include -#include +#include "drivers/dev_spi.h" /* SD command (SPI mode) */ #define GO_IDLE_STATE 0 /* CMD0 R1 */ @@ -125,4 +125,4 @@ struct msd_device extern rt_err_t msd_init(const char * sd_device_name, const char * spi_device_name); -#endif // SPI_MSD_H_INCLUDED +#endif // __DEV_SPI_MSD_H_INCLUDED diff --git a/rt-thread/components/drivers/spi/spi_wifi_rw009.c b/rt-thread/components/drivers/spi/dev_spi_wifi_rw009.c similarity index 99% rename from rt-thread/components/drivers/spi/spi_wifi_rw009.c rename to rt-thread/components/drivers/spi/dev_spi_wifi_rw009.c index 44f70e2..b3bd807 100644 --- a/rt-thread/components/drivers/spi/spi_wifi_rw009.c +++ b/rt-thread/components/drivers/spi/dev_spi_wifi_rw009.c @@ -11,7 +11,7 @@ */ #include -#include +#include "drivers/dev_spi.h" #include #include @@ -32,7 +32,7 @@ #endif /* #ifdef WIFI_DEBUG_ON */ /********************************* RW009 **************************************/ -#include "spi_wifi_rw009.h" +#include "dev_spi_wifi_rw009.h" /* tools */ #define node_entry(node, type, member) \ diff --git a/rt-thread/components/drivers/spi/spi_wifi_rw009.h b/rt-thread/components/drivers/spi/dev_spi_wifi_rw009.h similarity index 98% rename from rt-thread/components/drivers/spi/spi_wifi_rw009.h rename to rt-thread/components/drivers/spi/dev_spi_wifi_rw009.h index 9bba269..5aecbce 100644 --- a/rt-thread/components/drivers/spi/spi_wifi_rw009.h +++ b/rt-thread/components/drivers/spi/dev_spi_wifi_rw009.h @@ -9,8 +9,8 @@ * 2014-09-18 aozima update command & response. */ -#ifndef SPI_WIFI_H_INCLUDED -#define SPI_WIFI_H_INCLUDED +#ifndef __DEV_SPI_WIFI_H_INCLUDED__ +#define __DEV_SPI_WIFI_H_INCLUDED__ #include @@ -209,4 +209,4 @@ extern int32_t rw009_rssi(void); extern rt_err_t rw009_join(const char * SSID, const char * passwd); extern rt_err_t rw009_softap(const char * SSID, const char * passwd,uint32_t security,uint32_t channel); -#endif // SPI_WIFI_H_INCLUDED +#endif // __DEV_SPI_WIFI_H_INCLUDED__ diff --git a/rt-thread/components/drivers/spi/enc28j60.h b/rt-thread/components/drivers/spi/enc28j60.h index 017877a..013222c 100644 --- a/rt-thread/components/drivers/spi/enc28j60.h +++ b/rt-thread/components/drivers/spi/enc28j60.h @@ -6,13 +6,13 @@ * Change Logs: * Date Author Notes */ -#ifndef EN28J60_H_INCLUDED -#define EN28J60_H_INCLUDED +#ifndef __EN28J60_H_INCLUDED__ +#define __EN28J60_H_INCLUDED__ #include #include -#include +#include "drivers/dev_spi.h" #include // ENC28J60 Control Registers @@ -340,4 +340,4 @@ struct net_device extern rt_err_t enc28j60_attach(const char *spi_device_name); extern void enc28j60_isr(void); -#endif // EN28J60_H_INCLUDED +#endif // __EN28J60_H_INCLUDED__ diff --git a/rt-thread/components/drivers/thermal/Kconfig b/rt-thread/components/drivers/thermal/Kconfig new file mode 100644 index 0000000..b993aaf --- /dev/null +++ b/rt-thread/components/drivers/thermal/Kconfig @@ -0,0 +1,28 @@ +menuconfig RT_USING_THERMAL + bool "Using Thermal Management device drivers" + depends on RT_USING_DM + default n + +if RT_USING_THERMAL + comment "Thermal Sensors Drivers" +endif + +if RT_USING_THERMAL + osource "$(SOC_DM_THERMAL_DIR)/Kconfig" +endif + +if RT_USING_THERMAL + comment "Thermal Cool Drivers" +endif + +config RT_THERMAL_COOL_PWM_FAN + bool "PWM Fan" + depends on RT_USING_THERMAL + depends on RT_USING_PWM + depends on RT_USING_REGULATOR + depends on RT_USING_OFW + default n + +if RT_USING_THERMAL + osource "$(SOC_DM_THERMAL_COOL_DIR)/Kconfig" +endif diff --git a/rt-thread/components/drivers/thermal/SConscript b/rt-thread/components/drivers/thermal/SConscript new file mode 100644 index 0000000..d33d2d2 --- /dev/null +++ b/rt-thread/components/drivers/thermal/SConscript @@ -0,0 +1,18 @@ +from building import * + +group = [] + +if not GetDepend(['RT_USING_THERMAL']): + Return('group') + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/../include'] + +src = ['thermal.c', 'thermal_dm.c'] + +if GetDepend(['RT_THERMAL_COOL_PWM_FAN']): + src += ['thermal-cool-pwm-fan.c'] + +group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/rt-thread/components/drivers/thermal/thermal-cool-pwm-fan.c b/rt-thread/components/drivers/thermal/thermal-cool-pwm-fan.c new file mode 100644 index 0000000..d6c2539 --- /dev/null +++ b/rt-thread/components/drivers/thermal/thermal-cool-pwm-fan.c @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-3-08 GuEe-GUI the first version + */ + +#include +#include +#include + +#define DBG_TAG "thermal.cool.pwm-fan" +#define DBG_LVL DBG_INFO +#include + +#define MAX_PWM 255 + +struct pwm_fan_cool +{ + struct rt_thermal_cooling_device parent; + + rt_uint32_t pwm_fan_level; + rt_uint32_t pwm_fan_max_level; + rt_uint32_t *pwm_fan_cooling_levels; + + struct rt_device_pwm *pwm_dev; + struct rt_pwm_configuration pwm_conf; + + struct rt_regulator *supply; + struct rt_spinlock lock; +}; + +#define raw_to_pwm_fan_cool(raw) rt_container_of(raw, struct pwm_fan_cool, parent) + +static rt_err_t pwm_fan_power_on(struct pwm_fan_cool *pf_cool) +{ + rt_err_t err = RT_EOK; + + if ((err = rt_pwm_enable(pf_cool->pwm_dev, pf_cool->pwm_conf.channel))) + { + return err; + } + + if (pf_cool->supply && (err = rt_regulator_enable(pf_cool->supply))) + { + rt_pwm_disable(pf_cool->pwm_dev, pf_cool->pwm_conf.channel); + + return err; + } + + return err; +} + +static rt_err_t pwm_fan_power_off(struct pwm_fan_cool *pf_cool) +{ + rt_err_t err = RT_EOK; + + if (pf_cool->supply && (err = rt_regulator_disable(pf_cool->supply))) + { + return err; + } + + if ((err = rt_pwm_disable(pf_cool->pwm_dev, pf_cool->pwm_conf.channel))) + { + rt_regulator_enable(pf_cool->supply); + + return err; + } + + return err; +} + +static rt_err_t pwm_fan_cool_get_max_level(struct rt_thermal_cooling_device *cdev, + rt_ubase_t *out_level) +{ + struct pwm_fan_cool *pf_cool = raw_to_pwm_fan_cool(cdev); + + *out_level = pf_cool->pwm_fan_max_level; + + return RT_EOK; +} + +static rt_err_t pwm_fan_cool_get_cur_level(struct rt_thermal_cooling_device *cdev, + rt_ubase_t *out_level) +{ + struct pwm_fan_cool *pf_cool = raw_to_pwm_fan_cool(cdev); + + *out_level = pf_cool->pwm_fan_level; + + return RT_EOK; +} + +static rt_err_t pwm_fan_cool_set_cur_level(struct rt_thermal_cooling_device *cdev, + rt_ubase_t level) +{ + rt_ubase_t pwm; + rt_err_t err = RT_EOK; + struct pwm_fan_cool *pf_cool = raw_to_pwm_fan_cool(cdev); + + if (pf_cool->pwm_fan_level == level) + { + return RT_EOK; + } + + rt_spin_lock(&pf_cool->lock); + + if ((pwm = pf_cool->pwm_fan_cooling_levels[level])) + { + rt_ubase_t period; + struct rt_pwm_configuration *pwm_conf = &pf_cool->pwm_conf; + + period = pwm_conf->period; + pwm_conf->pulse = RT_DIV_ROUND_UP(pwm * (period - 1), MAX_PWM); + + err = rt_pwm_set(pf_cool->pwm_dev, + pwm_conf->channel, pwm_conf->period, pwm_conf->pulse); + + if (!err && pf_cool->pwm_fan_level == 0) + { + err = pwm_fan_power_on(pf_cool); + } + } + else if (pf_cool->pwm_fan_level > 0) + { + err = pwm_fan_power_off(pf_cool); + } + + rt_spin_unlock(&pf_cool->lock); + + if (!err) + { + pf_cool->pwm_fan_level = level; + } + + return RT_EOK; +} + +const static struct rt_thermal_cooling_device_ops pwm_fan_cool_ops = +{ + .get_max_level = pwm_fan_cool_get_max_level, + .get_cur_level = pwm_fan_cool_get_cur_level, + .set_cur_level = pwm_fan_cool_set_cur_level, +}; + +static void pwm_fan_cool_free(struct pwm_fan_cool *pf_cool) +{ + if (!rt_is_err_or_null(pf_cool->supply)) + { + rt_regulator_put(pf_cool->supply); + } + + if (pf_cool->pwm_fan_cooling_levels) + { + rt_free(pf_cool->pwm_fan_cooling_levels); + } + + rt_free(pf_cool); +} + +static rt_err_t pwm_fan_cool_probe(struct rt_platform_device *pdev) +{ + rt_err_t err; + int levels_nr; + struct rt_ofw_cell_args pwm_args; + struct rt_device *dev = &pdev->parent; + struct rt_ofw_node *np = dev->ofw_node, *pwm_np; + struct pwm_fan_cool *pf_cool = rt_calloc(1, sizeof(*pf_cool)); + + if (!pf_cool) + { + return -RT_ENOMEM; + } + + if (rt_ofw_parse_phandle_cells(np, "pwms", "#pwm-cells", 0, &pwm_args)) + { + err = -RT_EINVAL; + goto _fail; + } + + pwm_np = pwm_args.data; + + if (!rt_ofw_data(pwm_np)) + { + rt_platform_ofw_request(pwm_np); + } + + pf_cool->pwm_dev = rt_ofw_data(pwm_np); + rt_ofw_node_put(pwm_np); + + if (!pf_cool->pwm_dev) + { + err = -RT_EINVAL; + goto _fail; + } + + pf_cool->pwm_conf.channel = pwm_args.args[0]; + pf_cool->pwm_conf.period = pwm_args.args[1]; + + pf_cool->supply = rt_regulator_get(dev, "fan"); + + if (rt_is_err(pf_cool->supply)) + { + err = rt_ptr_err(pf_cool->supply); + goto _fail; + } + + if ((levels_nr = rt_dm_dev_prop_count_of_u32(dev, "cooling-levels")) <= 0) + { + err = -RT_EINVAL; + goto _fail; + } + + pf_cool->pwm_fan_cooling_levels = rt_calloc(levels_nr, sizeof(rt_uint32_t)); + + if (!pf_cool->pwm_fan_cooling_levels) + { + err = -RT_ENOMEM; + goto _fail; + } + + if (rt_dm_dev_prop_read_u32_array_index(dev, "cooling-levels", + 0, levels_nr, pf_cool->pwm_fan_cooling_levels) <= 0) + { + err = -RT_EINVAL; + goto _fail; + } + + pf_cool->pwm_fan_level = MAX_PWM; + pf_cool->pwm_fan_max_level = levels_nr - 1; + + rt_spin_lock_init(&pf_cool->lock); + pwm_fan_cool_set_cur_level(&pf_cool->parent, 0); + + rt_dm_dev_set_name(&pf_cool->parent.parent, "%s", rt_dm_dev_get_name(&pdev->parent)); + pf_cool->parent.parent.ofw_node = dev->ofw_node; + pf_cool->parent.ops = &pwm_fan_cool_ops; + + if ((err = rt_thermal_cooling_device_register(&pf_cool->parent))) + { + goto _fail; + } + + dev->user_data = pf_cool; + + return RT_EOK; + +_fail: + pwm_fan_cool_free(pf_cool); + + return err; +} + +static rt_err_t pwm_fan_cool_remove(struct rt_platform_device *pdev) +{ + struct pwm_fan_cool *pf_cool = pdev->parent.ofw_node; + + rt_thermal_cooling_device_unregister(&pf_cool->parent); + + pwm_fan_power_off(pf_cool); + pwm_fan_cool_free(pf_cool); + + return RT_EOK; +} + +static rt_err_t pwm_fan_cool_shutdown(struct rt_platform_device *pdev) +{ + return pwm_fan_cool_remove(pdev); +} + +static const struct rt_ofw_node_id pwm_fan_cool_ofw_ids[] = +{ + { .compatible = "pwm-fan" }, + { /* sentinel */ } +}; + +static struct rt_platform_driver pwm_fan_cool_driver = +{ + .name = "pwm-fan-cool", + .ids = pwm_fan_cool_ofw_ids, + + .probe = pwm_fan_cool_probe, + .remove = pwm_fan_cool_remove, + .shutdown = pwm_fan_cool_shutdown, +}; +RT_PLATFORM_DRIVER_EXPORT(pwm_fan_cool_driver); diff --git a/rt-thread/components/drivers/thermal/thermal.c b/rt-thread/components/drivers/thermal/thermal.c new file mode 100644 index 0000000..e9765c8 --- /dev/null +++ b/rt-thread/components/drivers/thermal/thermal.c @@ -0,0 +1,917 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-3-08 GuEe-GUI the first version + */ + +#include + +#define DBG_TAG "rtdm.thermal" +#define DBG_LVL DBG_INFO +#include + +#include "thermal_dm.h" + +#ifndef INT_MAX +#define INT_MAX (RT_UINT32_MAX >> 1) +#endif + +#define device_list(dev) (dev)->parent.parent.list +#define device_foreach(dev, nodes) rt_list_for_each_entry(dev, nodes, parent.parent.list) + +static struct rt_spinlock nodes_lock = {}; +static rt_list_t thermal_zone_device_nodes = RT_LIST_OBJECT_INIT(thermal_zone_device_nodes); +static rt_list_t thermal_cooling_device_nodes = RT_LIST_OBJECT_INIT(thermal_cooling_device_nodes); +static rt_list_t thermal_cooling_governor_nodes = RT_LIST_OBJECT_INIT(thermal_cooling_governor_nodes); + +#ifdef RT_USING_OFW +static void thermal_ofw_params_parse(struct rt_ofw_node *np, + struct rt_thermal_zone_params *tz_params) +{ + rt_uint32_t coef[2], prop; + + if (!np) + { + return; + } + + if (!rt_ofw_prop_read_u32(np, "sustainable-power", &prop)) + { + tz_params->sustainable_power = prop; + } + + /* + * For now, the thermal framework supports only one sensor per thermal zone. + * Thus, we are considering only the first two values as slope and offset. + */ + if (rt_ofw_prop_read_u32_array_index(np, "coefficients", 0, 1, coef) < 0) + { + coef[0] = 1; + coef[1] = 0; + } + + tz_params->slope = coef[0]; + tz_params->offset = coef[1]; +} + +static void thermal_ofw_setup(struct rt_ofw_node *np, struct rt_thermal_zone_device *zdev) +{ + int i = 0; + rt_uint32_t delay, pdelay; + struct rt_ofw_cell_args args; + struct rt_ofw_node *tmp_np, *tz_np, *trip_np, *cm_np, *cdev_np; + + if (!np || !zdev) + { + return; + } + + tmp_np = rt_ofw_find_node_by_path("/thermal-zones"); + + if (!tmp_np) + { + return; + } + + rt_ofw_foreach_child_node(tmp_np, tz_np) + { + if (!rt_ofw_parse_phandle_cells(tz_np, "thermal-sensors", "#thermal-sensor-cells", 0, &args)) + { + if (args.data == np && (!args.args_count || args.args[0] == zdev->zone_id)) + { + rt_ofw_node_put(args.data); + + goto _found; + } + rt_ofw_node_put(args.data); + } + } + + return; + +_found: + rt_ofw_prop_read_u32(tz_np, "polling-delay-passive", &pdelay); + rt_ofw_prop_read_u32(tz_np, "polling-delay", &delay); + + zdev->passive_delay = rt_tick_from_millisecond(pdelay); + zdev->polling_delay = rt_tick_from_millisecond(delay); + + thermal_ofw_params_parse(tz_np, &zdev->params); + + if (zdev->trips_nr) + { + goto _scan_cooling; + } + + tmp_np = rt_ofw_get_child_by_tag(tz_np, "trips"); + if (!tmp_np) + { + goto _scan_cooling; + } + + zdev->trips_nr = rt_ofw_get_child_count(tmp_np); + if (!zdev->trips_nr) + { + goto _scan_cooling; + } + zdev->trips = rt_calloc(zdev->trips_nr, sizeof(*zdev->trips)); + zdev->trips_free = RT_TRUE; + + if (!zdev->trips) + { + LOG_E("%s: No memory to create %s", rt_ofw_node_full_name(np), "trips"); + RT_ASSERT(0); + } + + rt_ofw_foreach_child_node(tmp_np, trip_np) + { + const char *type; + + rt_ofw_prop_read_u32(trip_np, "temperature", (rt_uint32_t *)&zdev->trips[i].temperature); + rt_ofw_prop_read_u32(trip_np, "hysteresis", (rt_uint32_t *)&zdev->trips[i].hysteresis); + rt_ofw_prop_read_string(trip_np, "type", &type); + zdev->trips[i].type = thermal_type(type); + + rt_ofw_data(trip_np) = &zdev->trips[i]; + + ++i; + } + +_scan_cooling: + i = 0; + tmp_np = rt_ofw_get_child_by_tag(tz_np, "cooling-maps"); + if (!tmp_np) + { + goto _end; + } + + zdev->cooling_maps_nr = rt_ofw_get_child_count(tmp_np); + if (!zdev->cooling_maps_nr) + { + goto _end; + } + zdev->cooling_maps = rt_calloc(zdev->cooling_maps_nr, sizeof(*zdev->cooling_maps)); + + if (!zdev->cooling_maps) + { + LOG_E("%s: No memory to create %s", rt_ofw_node_full_name(np), "cooling_maps"); + RT_ASSERT(0); + } + + rt_ofw_foreach_child_node(tmp_np, cm_np) + { + struct rt_thermal_cooling_device *cdev; + struct rt_thermal_cooling_map *map = &zdev->cooling_maps[i++]; + + map->cells_nr = rt_ofw_count_phandle_cells(cm_np, "cooling-device", "#cooling-cells"); + map->cells = rt_calloc(sizeof(*map->cells), map->cells_nr); + + if (!map->cells) + { + LOG_E("%s: No memory to create %s", rt_ofw_node_full_name(np), "cells"); + RT_ASSERT(0); + } + + trip_np = rt_ofw_parse_phandle(cm_np, "trip", 0); + map->trips = rt_ofw_data(trip_np); + rt_ofw_node_put(trip_np); + + if (!map->trips) + { + LOG_E("%s: trips(%s) not found", rt_ofw_node_full_name(np), + rt_ofw_node_full_name(trip_np)); + RT_ASSERT(0); + } + + rt_ofw_prop_read_u32(cm_np, "contribution", &map->contribution); + + for (int c = 0; c < map->cells_nr; ++c) + { + struct rt_thermal_cooling_cell *cell = &map->cells[c]; + + if (rt_ofw_parse_phandle_cells(cm_np, "cooling-device", "#cooling-cells", c, &args)) + { + continue; + } + + cdev_np = args.data; + + rt_spin_lock(&nodes_lock); + device_foreach(cdev, &thermal_cooling_device_nodes) + { + if (cdev->parent.ofw_node == cdev_np) + { + cell->cooling_devices = cdev; + break; + } + } + rt_spin_unlock(&nodes_lock); + + cell->level_range[0] = args.args[0]; + cell->level_range[1] = args.args[1]; + + if (cell->cooling_devices) + { + thermal_bind(cell->cooling_devices, zdev); + } + + rt_ofw_node_put(cdev_np); + } + } +_end: +} +#else +rt_inline void thermal_ofw_setup(struct rt_ofw_node *np, struct rt_thermal_zone_device *zdev) +{ +} +#endif /* RT_USING_OFW */ + +static void thermal_zone_poll(struct rt_work *work, void *work_data) +{ + struct rt_thermal_zone_device *zdev = work_data; + + rt_thermal_zone_device_update(zdev, RT_THERMAL_MSG_EVENT_UNSPECIFIED); +} + +rt_err_t rt_thermal_zone_device_register(struct rt_thermal_zone_device *zdev) +{ + if (!zdev || !zdev->ops || !zdev->ops->get_temp) + { + return -RT_EINVAL; + } + + zdev->ops->get_temp(zdev, &zdev->temperature); + zdev->last_temperature = zdev->temperature; + + if (!zdev->trips) + { + zdev->trips_nr = 0; + } + + rt_spin_lock_init(&zdev->nodes_lock); + rt_list_init(&zdev->notifier_nodes); + rt_list_init(&device_list(zdev)); + rt_mutex_init(&zdev->mutex, rt_dm_dev_get_name(&zdev->parent), RT_IPC_FLAG_PRIO); + + zdev->temperature = RT_THERMAL_TEMP_INVALID; + zdev->prev_low_trip = -INT_MAX; + zdev->prev_high_trip = INT_MAX; + + rt_spin_lock(&nodes_lock); + rt_list_insert_before(&thermal_zone_device_nodes, &device_list(zdev)); + rt_spin_unlock(&nodes_lock); + + thermal_ofw_setup(zdev->parent.ofw_node, zdev); + + rt_work_init(&zdev->poller, thermal_zone_poll, zdev); + zdev->enabled = RT_TRUE; + + /* Start to poll */ + rt_work_submit(&zdev->poller, zdev->polling_delay); + + return RT_EOK; +} + +rt_err_t rt_thermal_zone_device_unregister(struct rt_thermal_zone_device *zdev) +{ + if (!zdev) + { + return -RT_EINVAL; + } + + rt_spin_lock(&zdev->nodes_lock); + if (rt_list_isempty(&zdev->notifier_nodes)) + { + LOG_E("%s: there is %u user", rt_dm_dev_get_name(&zdev->parent), + rt_list_len(&zdev->notifier_nodes)); + + rt_spin_unlock(&zdev->nodes_lock); + + return -RT_EBUSY; + } + rt_spin_unlock(&zdev->nodes_lock); + + rt_work_cancel(&zdev->poller); + + rt_spin_lock(&nodes_lock); + rt_list_remove(&device_list(zdev)); + rt_spin_unlock(&nodes_lock); + + if (zdev->trips_free && zdev->trips) + { + rt_free(zdev->trips); + } + + if (zdev->cooling_maps_nr && zdev->cooling_maps_nr) + { + for (int i = 0; i < zdev->cooling_maps_nr; ++i) + { + struct rt_thermal_cooling_device *cdev; + struct rt_thermal_cooling_map *map = &zdev->cooling_maps[i]; + + for (int c = 0; c < map->cells_nr; ++c) + { + cdev = map->cells[i].cooling_devices; + + if (cdev) + { + thermal_unbind(cdev, zdev); + } + } + + rt_free(map->cells); + } + + rt_free(zdev->cooling_maps); + } + + rt_mutex_detach(&zdev->mutex); + + return RT_EOK; +} + +rt_err_t rt_thermal_cooling_device_register(struct rt_thermal_cooling_device *cdev) +{ + rt_err_t err; + + if (!cdev || !cdev->ops || + !cdev->ops->get_max_level || !cdev->ops->get_cur_level || !cdev->ops->set_cur_level) + { + return -RT_EINVAL; + } + + if ((err = cdev->ops->get_max_level(cdev, &cdev->max_level))) + { + return err; + } + + rt_list_init(&device_list(cdev)); + rt_list_init(&cdev->governor_node); + + rt_spin_lock(&nodes_lock); + rt_list_insert_before(&thermal_cooling_device_nodes, &device_list(cdev)); + rt_spin_unlock(&nodes_lock); + + err = rt_thermal_cooling_device_change_governor(cdev, RT_NULL); + + return err; +} + +rt_err_t rt_thermal_cooling_device_unregister(struct rt_thermal_cooling_device *cdev) +{ + if (!cdev) + { + return -RT_EINVAL; + } + + if (cdev->parent.ref_count) + { + LOG_E("%s: there is %u user", + rt_dm_dev_get_name(&cdev->parent), cdev->parent.ref_count); + return -RT_EINVAL; + } + + rt_spin_lock(&nodes_lock); + rt_list_remove(&device_list(cdev)); + rt_spin_unlock(&nodes_lock); + + return RT_EOK; +} + +static void dumb_governor_tuning(struct rt_thermal_zone_device *zdev, + int map_idx, int cell_idx, rt_ubase_t *level) +{ + struct rt_thermal_cooling_map *map = &zdev->cooling_maps[map_idx]; + + if (zdev->cooling && zdev->temperature > map->trips->temperature) + { + if (zdev->temperature - zdev->last_temperature > map->trips->hysteresis) + { + ++*level; + } + else if (zdev->last_temperature - zdev->temperature > map->trips->hysteresis) + { + --*level; + } + } + else + { + *level = 0; + } +} + +static struct rt_thermal_cooling_governor dumb_governor = +{ + .name = "dumb", + .tuning = dumb_governor_tuning, +}; + +static int system_thermal_cooling_governor_init(void) +{ + rt_thermal_cooling_governor_register(&dumb_governor); + + return 0; +} +INIT_CORE_EXPORT(system_thermal_cooling_governor_init); + +rt_err_t rt_thermal_cooling_governor_register(struct rt_thermal_cooling_governor *gov) +{ + rt_err_t err = RT_EOK; + struct rt_thermal_cooling_governor *gov_tmp; + + if (!gov || !gov->name || !gov->tuning) + { + return -RT_EINVAL; + } + + rt_list_init(&gov->list); + rt_list_init(&gov->cdev_nodes); + + rt_spin_lock(&nodes_lock); + + rt_list_for_each_entry(gov_tmp, &thermal_cooling_governor_nodes, list) + { + if (!rt_strcmp(gov_tmp->name, gov->name)) + { + err = -RT_ERROR; + goto _out_unlock; + } + } + + rt_list_insert_before(&thermal_cooling_governor_nodes, &gov->list); + +_out_unlock: + rt_spin_unlock(&nodes_lock); + + return err; +} + +rt_err_t rt_thermal_cooling_governor_unregister(struct rt_thermal_cooling_governor *gov) +{ + if (!gov) + { + return -RT_EINVAL; + } + + if (gov == &dumb_governor) + { + return -RT_EINVAL; + } + + rt_spin_lock(&nodes_lock); + + if (!rt_list_isempty(&gov->cdev_nodes)) + { + goto _out_unlock; + } + + rt_list_remove(&gov->list); + +_out_unlock: + rt_spin_unlock(&nodes_lock); + + return RT_EOK; +} + +rt_err_t rt_thermal_cooling_device_change_governor(struct rt_thermal_cooling_device *cdev, + const char *name) +{ + rt_err_t err; + struct rt_thermal_cooling_governor *gov; + + if (!cdev) + { + return -RT_EINVAL; + } + + name = name ? : dumb_governor.name; + err = -RT_ENOSYS; + + rt_spin_lock(&nodes_lock); + + rt_list_for_each_entry(gov, &thermal_cooling_governor_nodes, list) + { + if (!rt_strcmp(gov->name, name)) + { + if (cdev->gov) + { + rt_list_remove(&cdev->governor_node); + } + + cdev->gov = gov; + rt_list_insert_before(&cdev->governor_node, &gov->cdev_nodes); + + err = RT_EOK; + break; + } + } + + rt_spin_unlock(&nodes_lock); + + return err; +} + +rt_err_t rt_thermal_zone_notifier_register(struct rt_thermal_zone_device *zdev, + struct rt_thermal_notifier *notifier) +{ + if (!zdev || !notifier) + { + return -RT_EINVAL; + } + + notifier->zdev = zdev; + rt_list_init(¬ifier->list); + + rt_spin_lock(&zdev->nodes_lock); + rt_list_insert_after(&zdev->notifier_nodes, ¬ifier->list); + rt_spin_unlock(&zdev->nodes_lock); + + return RT_EOK; +} + +rt_err_t rt_thermal_zone_notifier_unregister(struct rt_thermal_zone_device *zdev, + struct rt_thermal_notifier *notifier) +{ + if (!zdev || !notifier) + { + return -RT_EINVAL; + } + + rt_spin_lock(&zdev->nodes_lock); + rt_list_remove(¬ifier->list); + rt_spin_unlock(&zdev->nodes_lock); + + return RT_EOK; +} + +void rt_thermal_zone_device_update(struct rt_thermal_zone_device *zdev, rt_ubase_t msg) +{ + rt_err_t err; + rt_bool_t passive = RT_FALSE, need_cool = RT_FALSE; + struct rt_thermal_notifier *notifier, *next_notifier; + + RT_ASSERT(zdev != RT_NULL); + + if (!rt_interrupt_get_nest()) + { + rt_mutex_take(&zdev->mutex, RT_WAITING_FOREVER); + } + + /* Check thermal zone status */ + if (msg == RT_THERMAL_MSG_DEVICE_DOWN) + { + zdev->enabled = RT_FALSE; + } + else if (msg == RT_THERMAL_MSG_DEVICE_UP) + { + zdev->enabled = RT_TRUE; + } + + /* Read temperature */ + zdev->last_temperature = zdev->temperature; + zdev->ops->get_temp(zdev, &zdev->temperature); + + for (int i = 0; i < zdev->trips_nr; ++i) + { + struct rt_thermal_trip *tmp_trip = &zdev->trips[i]; + + if (zdev->temperature <= tmp_trip->temperature) + { + continue; + } + + switch (tmp_trip->type) + { + case RT_THERMAL_TRIP_PASSIVE: + passive = RT_TRUE; + goto cooling; + + case RT_THERMAL_TRIP_CRITICAL: + if (zdev->ops->critical) + { + zdev->ops->critical(zdev); + } + else if (zdev->last_temperature > tmp_trip->temperature) + { + /* Tried to cool already, but failed */ + rt_hw_cpu_reset(); + } + else + { + goto cooling; + } + break; + + case RT_THERMAL_TRIP_HOT: + if (zdev->ops->hot) + { + zdev->ops->hot(zdev); + break; + } + + default: + cooling: + zdev->cooling = need_cool = RT_TRUE; + rt_thermal_cooling_device_kick(zdev); + break; + } + } + + if (!need_cool && zdev->cooling) + { + rt_thermal_cooling_device_kick(zdev); + } + + /* Set the new trips */ + if (zdev->ops->set_trips) + { + rt_bool_t same_trip = RT_FALSE; + int low = -INT_MAX, high = INT_MAX; + struct rt_thermal_trip trip; + + for (int i = 0; i < zdev->trips_nr; ++i) + { + int trip_low; + rt_bool_t low_set = RT_FALSE; + + if (i >= zdev->trips_nr) + { + goto _call_notifier; + } + rt_memcpy(&trip, &zdev->trips[i], sizeof(trip)); + + trip_low = trip.temperature - trip.hysteresis; + + if (trip_low < zdev->temperature && trip_low > low) + { + low = trip_low; + low_set = RT_TRUE; + same_trip = RT_FALSE; + } + + if (trip.temperature > zdev->temperature && trip.temperature < high) + { + high = trip.temperature; + same_trip = low_set; + } + } + + /* No need to change trip points */ + if (zdev->prev_low_trip == low && zdev->prev_high_trip == high) + { + goto _call_notifier; + } + + if (same_trip && + (zdev->prev_low_trip != -INT_MAX || zdev->prev_high_trip != INT_MAX)) + { + goto _call_notifier; + } + + zdev->prev_low_trip = low; + zdev->prev_high_trip = high; + + if ((err = zdev->ops->set_trips(zdev, low, high))) + { + LOG_E("%s: Set trips error = %s", rt_dm_dev_get_name(&zdev->parent), + rt_strerror(err)); + } + } + + /* Call all notifier, maybe have governor */ +_call_notifier: + rt_spin_lock(&zdev->nodes_lock); + + rt_list_for_each_entry_safe(notifier, next_notifier, &zdev->notifier_nodes, list) + { + rt_spin_unlock(&zdev->nodes_lock); + + notifier->callback(notifier, msg); + + rt_spin_lock(&zdev->nodes_lock); + } + + rt_spin_unlock(&zdev->nodes_lock); + + /* Prepare for the next report */ + if (!zdev->enabled) + { + rt_work_cancel(&zdev->poller); + } + else if (passive && zdev->passive_delay) + { + rt_work_submit(&zdev->poller, zdev->passive_delay); + } + else if (zdev->polling_delay) + { + rt_work_submit(&zdev->poller, zdev->polling_delay); + } + + if (!rt_interrupt_get_nest()) + { + rt_mutex_release(&zdev->mutex); + } +} + +void rt_thermal_cooling_device_kick(struct rt_thermal_zone_device *zdev) +{ + RT_ASSERT(zdev != RT_NULL); + + for (int i = 0; i < zdev->cooling_maps_nr; ++i) + { + rt_ubase_t level; + struct rt_thermal_cooling_device *cdev; + struct rt_thermal_cooling_cell *cell; + struct rt_thermal_cooling_map *map = &zdev->cooling_maps[i]; + + for (int c = 0; c < map->cells_nr; ++c) + { + cell = &map->cells[c]; + cdev = cell->cooling_devices; + + if (!cdev) + { + continue; + } + + /* Update status */ + if (cdev->ops->get_max_level(cdev, &cdev->max_level)) + { + continue; + } + + if (cdev->ops->get_cur_level(cdev, &level) || level > cdev->max_level) + { + continue; + } + + /* Check if cooling is required */ + if (level >= cell->level_range[0] && level <= cell->level_range[1]) + { + /* Is cooling, not call */ + continue; + } + + cdev->gov->tuning(zdev, i, c, &level); + level = rt_min_t(rt_ubase_t, level, cdev->max_level); + + cdev->ops->set_cur_level(cdev, level); + } + } +} + +rt_err_t rt_thermal_zone_set_trip(struct rt_thermal_zone_device *zdev, int trip_id, + const struct rt_thermal_trip *trip) +{ + rt_err_t err; + struct rt_thermal_trip tmp_trip; + + if (!zdev || !trip) + { + return -RT_EINVAL; + } + + rt_mutex_take(&zdev->mutex, RT_WAITING_FOREVER); + + if (!zdev->ops->set_trip_temp && !zdev->ops->set_trip_hyst && !zdev->trips) + { + err = -RT_EINVAL; + goto _out_unlock; + } + + if (trip_id >= zdev->trips_nr) + { + err = -RT_EINVAL; + goto _out_unlock; + } + + rt_memcpy(&tmp_trip, &zdev->trips[trip_id], sizeof(tmp_trip)); + + if (tmp_trip.type != trip->type) + { + err = -RT_EINVAL; + goto _out_unlock; + } + + if (tmp_trip.temperature != trip->temperature && zdev->ops->set_trip_temp) + { + if ((err = zdev->ops->set_trip_temp(zdev, trip_id, trip->temperature))) + { + goto _out_unlock; + } + } + + if (tmp_trip.hysteresis != trip->hysteresis && zdev->ops->set_trip_hyst) + { + if ((err = zdev->ops->set_trip_hyst(zdev, trip_id, trip->hysteresis))) + { + goto _out_unlock; + } + } + + if (zdev->trips && + (tmp_trip.temperature != trip->temperature || tmp_trip.hysteresis != trip->hysteresis)) + { + zdev->trips[trip_id] = *trip; + } + +_out_unlock: + rt_mutex_release(&zdev->mutex); + + if (!err) + { + rt_thermal_zone_device_update(zdev, RT_THERMAL_MSG_TRIP_CHANGED); + } + + return err; +} + +rt_err_t rt_thermal_zone_get_trip(struct rt_thermal_zone_device *zdev, int trip_id, + struct rt_thermal_trip *out_trip) +{ + rt_err_t err = RT_EOK; + + if (!zdev || !out_trip) + { + return -RT_EINVAL; + } + + rt_mutex_take(&zdev->mutex, RT_WAITING_FOREVER); + + if (!zdev->trips_nr) + { + err = -RT_ENOSYS; + goto _out_unlock; + } + + if (trip_id >= zdev->trips_nr) + { + err = -RT_EINVAL; + goto _out_unlock; + } + + *out_trip = zdev->trips[trip_id]; + +_out_unlock: + rt_mutex_release(&zdev->mutex); + + return err; +} + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_MSH) +static int list_thermal(int argc, char**argv) +{ + struct rt_thermal_zone_device *zdev; + + /* Thermal is an important subsystem, please do not output too much. */ + rt_spin_lock(&nodes_lock); + device_foreach(zdev, &thermal_zone_device_nodes) + { + int temperature = zdev->temperature; + + rt_kprintf("%s-%d\n", rt_dm_dev_get_name(&zdev->parent), zdev->zone_id); + rt_kprintf("temperature:\t%+d.%u C\n", temperature / 1000, rt_abs(temperature) % 1000); + + for (int i = 0, id = 0; i < zdev->cooling_maps_nr; ++i) + { + rt_ubase_t level; + struct rt_thermal_trip *trips; + struct rt_thermal_cooling_device *cdev; + struct rt_thermal_cooling_cell *cell; + struct rt_thermal_cooling_map *map = &zdev->cooling_maps[i]; + + for (int c = 0; c < map->cells_nr; ++c, ++id) + { + trips = map->trips; + cell = &map->cells[c]; + cdev = cell->cooling_devices; + + if (cdev) + { + cdev->ops->get_cur_level(cdev, &level); + + rt_kprintf("cooling%u:\t%s[%+d.%u C] %d\n", id, + rt_dm_dev_get_name(&cdev->parent), + trips->temperature / 1000, rt_abs(trips->temperature) % 1000, + level); + } + else + { + rt_kprintf("cooling%u:\t%s[%+d.%u C] %d\n", id, + "(not supported)", + trips->temperature / 1000, rt_abs(trips->temperature) % 1000, + 0); + } + } + } + } + rt_spin_unlock(&nodes_lock); + + return 0; +} +MSH_CMD_EXPORT(list_thermal, dump all of thermal information); +#endif /* RT_USING_CONSOLE && RT_USING_MSH */ diff --git a/rt-thread/components/drivers/thermal/thermal_dm.c b/rt-thread/components/drivers/thermal/thermal_dm.c new file mode 100644 index 0000000..9c1d81f --- /dev/null +++ b/rt-thread/components/drivers/thermal/thermal_dm.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-3-08 GuEe-GUI the first version + */ + +#define DBG_TAG "rtdm.thermal" +#define DBG_LVL DBG_INFO +#include + +#include "thermal_dm.h" + +enum rt_thermal_trip_type thermal_type(const char *type) +{ + if (!type) + { + return RT_THERMAL_TRIP_TYPE_MAX; + } + + if (!rt_strcmp(type, "active")) + { + return RT_THERMAL_TRIP_ACTIVE; + } + else if (!rt_strcmp(type, "passive")) + { + return RT_THERMAL_TRIP_PASSIVE; + } + else if (!rt_strcmp(type, "hot")) + { + return RT_THERMAL_TRIP_HOT; + } + else if (!rt_strcmp(type, "critical")) + { + return RT_THERMAL_TRIP_CRITICAL; + } + + return RT_THERMAL_TRIP_TYPE_MAX; +} + +rt_err_t thermal_bind(struct rt_thermal_cooling_device *cdev, + struct rt_thermal_zone_device *zdev) +{ + if (cdev->ops->bind) + { + return cdev->ops->bind(cdev, zdev); + } + + return RT_EOK; +} + +rt_err_t thermal_unbind(struct rt_thermal_cooling_device *cdev, + struct rt_thermal_zone_device *zdev) +{ + if (cdev->ops->unbind) + { + return cdev->ops->unbind(cdev, zdev); + } + + return RT_EOK; +} diff --git a/rt-thread/components/drivers/thermal/thermal_dm.h b/rt-thread/components/drivers/thermal/thermal_dm.h new file mode 100644 index 0000000..15d3314 --- /dev/null +++ b/rt-thread/components/drivers/thermal/thermal_dm.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-3-08 GuEe-GUI the first version + */ + +#ifndef __THERMAL_DM_H__ +#define __THERMAL_DM_H__ + +#include +#include +#include + +#include + +enum rt_thermal_trip_type thermal_type(const char *type); + +rt_err_t thermal_bind(struct rt_thermal_cooling_device *cdev, + struct rt_thermal_zone_device *zdev); +rt_err_t thermal_unbind(struct rt_thermal_cooling_device *cdev, + struct rt_thermal_zone_device *zdev); + +#endif /* __THERMAL_DM_H__ */ diff --git a/rt-thread/components/drivers/touch/SConscript b/rt-thread/components/drivers/touch/SConscript index df698c7..ba646b0 100644 --- a/rt-thread/components/drivers/touch/SConscript +++ b/rt-thread/components/drivers/touch/SConscript @@ -3,7 +3,7 @@ from building import * cwd = GetCurrentDir() -src = ['touch.c'] +src = ['dev_touch.c'] CPPPATH = [cwd, cwd + '/../include'] group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_TOUCH', 'RT_USING_DEVICE'], CPPPATH = CPPPATH) diff --git a/rt-thread/components/drivers/touch/touch.c b/rt-thread/components/drivers/touch/dev_touch.c similarity index 100% rename from rt-thread/components/drivers/touch/touch.c rename to rt-thread/components/drivers/touch/dev_touch.c diff --git a/rt-thread/components/drivers/usb/cherryusb/CherryUSB.svg b/rt-thread/components/drivers/usb/cherryusb/CherryUSB.svg index c1ed478..91de329 100644 --- a/rt-thread/components/drivers/usb/cherryusb/CherryUSB.svg +++ b/rt-thread/components/drivers/usb/cherryusb/CherryUSB.svg @@ -1,3 +1,3 @@ -
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optional
required
required \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/Kconfig b/rt-thread/components/drivers/usb/cherryusb/Kconfig index 3e9ce5f..67c6ad5 100644 --- a/rt-thread/components/drivers/usb/cherryusb/Kconfig +++ b/rt-thread/components/drivers/usb/cherryusb/Kconfig @@ -38,6 +38,8 @@ if RT_USING_CHERRYUSB bool "dwc2_gd" config RT_CHERRYUSB_DEVICE_DWC2_HC bool "dwc2_hc" + config RT_CHERRYUSB_DEVICE_DWC2_KENDRYTE + bool "dwc2_kendryte" config RT_CHERRYUSB_DEVICE_DWC2_CUSTOM bool "dwc2_custom" config RT_CHERRYUSB_DEVICE_MUSB_ES @@ -48,6 +50,14 @@ if RT_USING_CHERRYUSB bool "musb_bk" config RT_CHERRYUSB_DEVICE_MUSB_CUSTOM bool "musb_custom" + config RT_CHERRYUSB_DEVICE_KINETIS_MCX + bool "kinetis_mcx" + config RT_CHERRYUSB_DEVICE_KINETIS_CUSTOM + bool "kinetis_custom" + config RT_CHERRYUSB_DEVICE_CHIPIDEA_MCX + bool "chipidea_mcx" + config RT_CHERRYUSB_DEVICE_CHIPIDEA_CUSTOM + bool "chipidea_custom" config RT_CHERRYUSB_DEVICE_BL bool "bouffalo" config RT_CHERRYUSB_DEVICE_CH32 @@ -107,7 +117,7 @@ if RT_USING_CHERRYUSB choice prompt "Select usb device template" - default RT_CHERRYUSB_DEVICE_TEMPLATE + default RT_CHERRYUSB_DEVICE_TEMPLATE_NONE config RT_CHERRYUSB_DEVICE_TEMPLATE_NONE bool "none (Implement it yourself)" config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM @@ -162,16 +172,20 @@ if RT_USING_CHERRYUSB bool "ehci_hpm" config RT_CHERRYUSB_HOST_EHCI_AIC bool "ehci_aic" - config RT_CHERRYUSB_HOST_EHCI_NUVOTON_NUC980 - bool "ehci_nuvoton_nuc980" - config RT_CHERRYUSB_HOST_EHCI_NUVOTON_MA35D0 - bool "ehci_nuvoton_ma35d0" + config RT_CHERRYUSB_HOST_EHCI_MCX + bool "ehci_mcx" + config RT_CHERRYUSB_HOST_EHCI_NUC980 + bool "ehci_nuc980" + config RT_CHERRYUSB_HOST_EHCI_MA35D0 + bool "ehci_ma35d0" config RT_CHERRYUSB_HOST_EHCI_CUSTOM bool "ehci_custom" config RT_CHERRYUSB_HOST_DWC2_ST bool "dwc2_st" config RT_CHERRYUSB_HOST_DWC2_ESP bool "dwc2_esp" + config RT_CHERRYUSB_HOST_DWC2_KENDRYTE + bool "dwc2_kendryte" config RT_CHERRYUSB_HOST_DWC2_CUSTOM bool "dwc2_custom" config RT_CHERRYUSB_HOST_MUSB_ES @@ -186,6 +200,10 @@ if RT_USING_CHERRYUSB bool "pusb2" config RT_CHERRYUSB_HOST_XHCI bool "xhci" + config RT_CHERRYUSB_HOST_KINETIS_MCX + bool "kinetis_mcx" + config RT_CHERRYUSB_HOST_KINETIS_CUSTOM + bool "kinetis_custom" endchoice config RT_CHERRYUSB_HOST_CDC_ACM @@ -203,6 +221,7 @@ if RT_USING_CHERRYUSB prompt "Enable usb msc driver" default n select RT_USING_DFS + select RT_USING_DFS_ELMFAT config RT_CHERRYUSB_HOST_CDC_ECM bool @@ -294,7 +313,12 @@ if RT_USING_CHERRYUSB config CONFIG_USBHOST_PLATFORM_RTL8152 bool - config CHERRYUSB_HOST_TEMPLATE + config RT_LWIP_PBUF_POOL_BUFSIZE + int "The size of each pbuf in the pbuf pool" + range 1500 2000 + default 1600 + + config RT_CHERRYUSB_HOST_TEMPLATE bool prompt "Use usb host template" default n diff --git a/rt-thread/components/drivers/usb/cherryusb/Kconfig.cherryusb b/rt-thread/components/drivers/usb/cherryusb/Kconfig.cherryusb deleted file mode 100644 index 4d44a75..0000000 --- a/rt-thread/components/drivers/usb/cherryusb/Kconfig.cherryusb +++ /dev/null @@ -1,312 +0,0 @@ -# Kconfig file for CherryUSB -menuconfig CHERRYUSB - bool "Using CherryUSB" - default n - -if CHERRYUSB - - menuconfig CHERRYUSB_DEVICE - bool "Enable usb device mode" - default n - - if CHERRYUSB_DEVICE - choice - prompt "Select usb device speed" - default CHERRYUSB_DEVICE_SPEED_FS - config CHERRYUSB_DEVICE_SPEED_FS - bool "FS" - config CHERRYUSB_DEVICE_SPEED_HS - bool "HS" - config CHERRYUSB_DEVICE_SPEED_AUTO - bool "AUTO" - endchoice - - choice - prompt "Select usb device ip, and some ip need config in usb_config.h, please check" - default CHERRYUSB_DEVICE_CUSTOM - config CHERRYUSB_DEVICE_CUSTOM - bool "CUSTOM (Implement it yourself)" - config CHERRYUSB_DEVICE_FSDEV - bool "fsdev" - config CHERRYUSB_DEVICE_DWC2_ST - bool "dwc2_st" - config CHERRYUSB_DEVICE_DWC2_ESP - bool "dwc2_esp" - config CHERRYUSB_DEVICE_DWC2_AT - bool "dwc2_at" - config CHERRYUSB_DEVICE_DWC2_GD - bool "dwc2_gd" - config CHERRYUSB_DEVICE_DWC2_HC - bool "dwc2_hc" - config CHERRYUSB_DEVICE_DWC2_CUSTOM - bool "dwc2_custom" - config CHERRYUSB_DEVICE_MUSB_ES - bool "musb_es" - config CHERRYUSB_DEVICE_MUSB_SUNXI - bool "musb_sunxi" - config CHERRYUSB_DEVICE_MUSB_BK - bool "musb_bk" - config CHERRYUSB_DEVICE_MUSB_CUSTOM - bool "musb_custom" - config CHERRYUSB_DEVICE_BL - bool "bouffalo" - config CHERRYUSB_DEVICE_HPM - bool "hpm" - config CHERRYUSB_DEVICE_AIC - bool "aic" - config CHERRYUSB_DEVICE_CH32 - bool "ch32" - config CHERRYUSB_DEVICE_PUSB2 - bool "pusb2" - endchoice - - config CHERRYUSB_DEVICE_CDC_ACM - bool - prompt "Enable usb cdc acm device" - default n - - config CHERRYUSB_DEVICE_HID - bool - prompt "Enable usb hid device" - default n - - config CHERRYUSB_DEVICE_MSC - bool - prompt "Enable usb msc device" - default n - - config CHERRYUSB_DEVICE_AUDIO - bool - prompt "Enable usb audio device" - default n - - config CHERRYUSB_DEVICE_VIDEO - bool - prompt "Enable usb video device" - default n - - config CHERRYUSB_DEVICE_CDC_RNDIS - bool - prompt "Enable usb cdc rndis device" - default n - - config CHERRYUSB_DEVICE_CDC_ECM - bool - prompt "Enable usb cdc ecm device" - default n - - config CHERRYUSB_DEVICE_CDC_NCM - bool - prompt "Enable usb cdc ncm device" - default n - - config CHERRYUSB_DEVICE_DFU - bool - prompt "Enable usb dfu device" - default n - - choice - prompt "Select usb device template" - default CHERRYUSB_DEVICE_TEMPLATE - config CHERRYUSB_DEVICE_TEMPLATE_NONE - bool "none (Implement it yourself)" - config CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM - bool "cdc_acm" - config CHERRYUSB_DEVICE_TEMPLATE_MSC - bool "msc" - config CHERRYUSB_DEVICE_TEMPLATE_HID_KEYBOARD - bool "hid_keyboard" - config CHERRYUSB_DEVICE_TEMPLATE_HID_MOUSE - bool "hid_mouse" - config CHERRYUSB_DEVICE_TEMPLATE_HID_CUSTOM - bool "hid_custom" - config CHERRYUSB_DEVICE_TEMPLATE_VIDEO - bool "video" - config CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V1_MIC_SPEAKER - bool "audio_v1_mic_speaker_multichan" - config CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V2_MIC_SPEAKER - bool "audio_v2_mic_speaker_multichan" - config CHERRYUSB_DEVICE_TEMPLATE_CDC_RNDIS - bool "cdc_rndis" - config CHERRYUSB_DEVICE_TEMPLATE_CDC_ECM - bool "cdc_ecm" - config CHERRYUSB_DEVICE_TEMPLATE_CDC_NCM - bool "cdc_ncm" - config CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC - bool "cdc_acm_msc" - config CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC_HID - bool "cdc_acm_msc_hid" - config CHERRYUSB_DEVICE_TEMPLATE_WINUSBV1 - bool "winusbv1" - config CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_CDC - bool "winusbv2_cdc" - config CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_HID - bool "winusbv2_hid" - endchoice - - endif - - menuconfig CHERRYUSB_HOST - bool "Enable usb host mode" - default n - - if CHERRYUSB_HOST - choice - prompt "Select usb host ip, and some ip need config in usb_config.h, please check" - default CHERRYUSB_HOST_CUSTOM - config CHERRYUSB_HOST_CUSTOM - bool "CUSTOM (Implement it yourself)" - config CHERRYUSB_HOST_EHCI_BL - bool "ehci_bouffalo" - config CHERRYUSB_HOST_EHCI_HPM - bool "ehci_hpm" - config CHERRYUSB_HOST_EHCI_AIC - bool "ehci_aic" - config CHERRYUSB_HOST_EHCI_NUVOTON_NUC980 - bool "ehci_nuvoton_nuc980" - config CHERRYUSB_HOST_EHCI_NUVOTON_MA35D0 - bool "ehci_nuvoton_ma35d0" - config CHERRYUSB_HOST_EHCI_CUSTOM - bool "ehci_custom" - config CHERRYUSB_HOST_DWC2_ST - bool "dwc2_st" - config CHERRYUSB_HOST_DWC2_ESP - bool "dwc2_esp" - config CHERRYUSB_HOST_DWC2_HC - bool "dwc2_hc" - config CHERRYUSB_HOST_DWC2_CUSTOM - bool "dwc2_custom" - config CHERRYUSB_HOST_MUSB_ES - bool "musb_es" - config CHERRYUSB_HOST_MUSB_SUNXI - bool "musb_sunxi" - config CHERRYUSB_HOST_MUSB_BK - bool "musb_bk" - config CHERRYUSB_HOST_MUSB_CUSTOM - bool "musb_custom" - config CHERRYUSB_HOST_PUSB2 - bool "pusb2" - config CHERRYUSB_HOST_XHCI - bool "xhci" - endchoice - - config CHERRYUSB_HOST_CDC_ACM - bool - prompt "Enable usb cdc acm driver" - default n - - config CHERRYUSB_HOST_HID - bool - prompt "Enable usb hid driver" - default n - - config CHERRYUSB_HOST_MSC - bool - prompt "Enable usb msc driver" - default n - - config CHERRYUSB_HOST_CDC_ECM - bool - prompt "Enable usb cdc ecm driver" - select USBHOST_PLATFORM_CDC_ECM - default n - - config CHERRYUSB_HOST_CDC_RNDIS - bool - prompt "Enable usb rndis driver" - select USBHOST_PLATFORM_CDC_RNDIS - default n - - config CHERRYUSB_HOST_CDC_NCM - bool - prompt "Enable usb cdc ncm driver" - select USBHOST_PLATFORM_CDC_NCM - default n - - config CHERRYUSB_HOST_VIDEO - bool - prompt "Enable usb video driver, it is commercial charge" - default n - - config CHERRYUSB_HOST_AUDIO - bool - prompt "Enable usb audio driver, it is commercial charge" - default n - - config CHERRYUSB_HOST_BLUETOOTH - bool - prompt "Enable usb bluetooth driver" - default n - - config CHERRYUSB_HOST_ASIX - bool - prompt "Enable usb asix driver" - select USBHOST_PLATFORM_ASIX - default n - - config CHERRYUSB_HOST_RTL8152 - bool - prompt "Enable usb rtl8152 driver" - select USBHOST_PLATFORM_RTL8152 - default n - - config CHERRYUSB_HOST_FTDI - bool - prompt "Enable usb ftdi driver" - default n - - config CHERRYUSB_HOST_CH34X - bool - prompt "Enable usb ch34x driver" - default n - - config CHERRYUSB_HOST_CP210X - bool - prompt "Enable usb cp210x driver" - default n - - config CHERRYUSB_HOST_PL2303 - bool - prompt "Enable usb pl2303 driver" - default n - - config USBHOST_PLATFORM_CDC_ECM - bool - - config USBHOST_PLATFORM_CDC_RNDIS - bool - - config USBHOST_PLATFORM_CDC_NCM - bool - - config USBHOST_PLATFORM_ASIX - bool - - config USBHOST_PLATFORM_RTL8152 - bool - - config CHERRYUSB_HOST_TEMPLATE - bool - prompt "Use usb host template" - default n - - if CHERRYUSB_HOST_TEMPLATE - config TEST_USBH_CDC_ACM - int - prompt "demo for test cdc acm" - default 0 - depends on CHERRYUSB_HOST_CDC_ACM - config TEST_USBH_HID - int - prompt "demo for test hid" - default 0 - depends on CHERRYUSB_HOST_HID - config TEST_USBH_MSC - int - prompt "demo for test msc" - default 0 - depends on CHERRYUSB_HOST_MSC - endif - endif - -endif diff --git a/rt-thread/components/drivers/usb/cherryusb/README.md b/rt-thread/components/drivers/usb/cherryusb/README.md index d79df88..e56946a 100644 --- a/rt-thread/components/drivers/usb/cherryusb/README.md +++ b/rt-thread/components/drivers/usb/cherryusb/README.md @@ -1,6 +1,16 @@ -# CherryUSB +

CherryUSB

+

+ + + + +

-[中文版](./README_zh.md) +

+ 中文 + | + English +

CherryUSB is a tiny, beautiful and portable USB host and device stack for embedded system with USB IP. @@ -17,12 +27,12 @@ In order to make it easier for users to learn USB basics, enumeration, driver lo - Class-drivers and porting-drivers are templating and simplification - Clear API classification (slave: initialisation, registration api, command callback api, data sending and receiving api; host: initialisation, lookup api, data sending and receiving api) -### Easy to use USB +### Easy to use USB In order to facilitate the use of the USB interface and to take into account the fact that users have learned about uart and dma, the following advantages have been designed for the data sending and receiving class of interface: - Equivalent to using uart tx dma/uart rx dma -- There is no limit to the length of send and receive, the user does not need to care about the USB packetization process (the porting driver does the packetization process) +- There is no limit to the length of send and receive, the user does not need to care about the USB packetization process (the porting driver does it) ### Easy to bring out USB performance @@ -32,9 +42,9 @@ Taking into account USB performance issues and trying to achieve the theoretical - Memory zero copy - If IP has DMA then uses DMA mode (DMA with hardware packetization) - Unlimited length make it easier to interface with hardware DMA and take advantage of DMA -- Subcontracting function is handled in interrupt +- Packetization is handled in interrupt -## Directoy Structure +## Directory Structure | Directory | Description | |:-------------:|:---------------------------:| @@ -65,21 +75,23 @@ CherryUSB Device Stack has the following functions： - Support Device Firmware Upgrade CLASS (DFU) - Support USB MIDI CLASS (MIDI) - Support Remote NDIS (RNDIS) -- Support WINUSB1.0、WINUSB2.0(with BOS) +- Support WINUSB1.0、WINUSB2.0、WEBUSB、BOS - Support Vendor class +- Support UF2 +- Support Android Debug Bridge (Only support shell) - Support multi device with the same USB IP CherryUSB Device Stack resource usage (GCC 10.2 with -O2): | file | FLASH (Byte) | No Cache RAM (Byte) | RAM (Byte) | Heap (Byte) | |:-------------:|:--------------:|:-------------------------:|:-------------:|:----------------:| -|usbd_core.c | 3516 | 256(default) + 320 | 0 | 0 | -|usbd_cdc.c | 392 | 0 | 0 | 0 | -|usbd_msc.c | 2839 | 128 + 512(default) | 16 | 0 | -|usbd_hid.c | 364 | 0 | 0 | 0 | -|usbd_audio.c | 1455 | 0 | 0 | 0 | -|usbd_video.c | 2494 | 0 | 84 | 0 | -|usbd_rndis.c | 2109 | 3340 | 76 | 0 | +|usbd_core.c | ~4400 | 512(default) + 320 | 0 | 0 | +|usbd_cdc_acm.c | ~400 | 0 | 0 | 0 | +|usbd_msc.c | ~3800 | 128 + 512(default) | 16 | 0 | +|usbd_hid.c | ~360 | 0 | 0 | 0 | +|usbd_audio.c | ~1500 | 0 | 0 | 0 | +|usbd_video.c | ~2600 | 0 | 84 | 0 | +|usbd_rndis.c | ~2100 | 2 * 1580(default)+156+8 | 76 | 0 | ## Host Stack Overview @@ -87,6 +99,7 @@ The CherryUSB Host Stack has a standard enumeration implementation for devices m CherryUSB Host Stack has the following functions： +- Support low speed, full speed, high speed and super speed devices - Automatic loading of supported Class drivers - Support blocking transfers and asynchronous transfers - Support Composite Device @@ -98,8 +111,9 @@ CherryUSB Host Stack has the following functions： - Support USB Audio CLASS (UAC1.0) - Support Remote NDIS (RNDIS) - Support USB Bluetooth class (support nimble and zephyr bluetooth stack, support **CLASS:0xE0** or vendor class like cdc acm) -- Support Vendor class +- Support Vendor class (serial, net, wifi) - Support USB modeswitch +- Support Android Open Accessory - Support multi host with the same USB IP The CherryUSB Host stack also provides the lsusb function, which allows you to view information about all mounted devices, including those on external hubs, with the help of a shell plugin. @@ -108,16 +122,17 @@ CherryUSB Host Stack resource usage (GCC 10.2 with -O2): | file | FLASH (Byte) | No Cache RAM (Byte) | RAM (Byte) | Heap (Byte) | |:-------------:|:--------------:|:-------------------------------:|:---------------------------:|:------------:| -|usbh_core.c | ~7700 | 512 + 8 * (1+x) *n | 28 | 0 | -|usbh_hub.c | ~5600 | 32 + 4* (1+x) | 12 + sizeof(struct usbh_hub) * (1+x) | 0 | -|usbh_cdc_acm.c | ~1200 | 7 | 4 + sizeof(struct usbh_cdc_acm) * x | 0 | -|usbh_msc.c | ~2500 | 32 | 4 + sizeof(struct usbh_msc) * x | 0 | -|usbh_hid.c | ~1000 | 128 | 4 + sizeof(struct usbh_hid) * x | 0 | -|usbh_video.c | ~3700 | 128 | 4 + sizeof(struct usbh_video) * x | 0 | -|usbh_audio.c | ~3100 | 128 | 4 + sizeof(struct usbh_audio) * x | 0 | -|usbh_rndis.c | ~3900 | 4096 + 2 * 2048(default)| sizeof(struct usbh_rndis) * 1 | 0 | -|usbh_cdc_ecm.c | ~2500 | 2 * 1514 | sizeof(struct usbh_cdc_ecm) * 1 | 0 | -|usbh_bluetooth.c | ~2300 | 2 * 2048(default) | sizeof(struct usbh_bluetooth) * 1 | 0 | +|usbh_core.c | ~9000 | 512 + 8 * (1+x) *n | 28 | raw_config_desc | +|usbh_hub.c | ~6000 | 32 + 4 * (1+x) | 12 + sizeof(struct usbh_hub) * (1+x) | 0 | +|usbh_cdc_acm.c | ~900 | 7 | 4 + sizeof(struct usbh_cdc_acm) * x | 0 | +|usbh_msc.c | ~2700 | 64 | 4 + sizeof(struct usbh_msc) * x | 0 | +|usbh_hid.c | ~1400 | 256 | 4 + sizeof(struct usbh_hid) * x | 0 | +|usbh_video.c | ~3800 | 128 | 4 + sizeof(struct usbh_video) * x | 0 | +|usbh_audio.c | ~4100 | 128 | 4 + sizeof(struct usbh_audio) * x | 0 | +|usbh_rndis.c | ~4200 | 512 + 2 * 2048(default)| sizeof(struct usbh_rndis) * 1 | 0 | +|usbh_cdc_ecm.c | ~2200 | 2 * 1514 + 16 | sizeof(struct usbh_cdc_ecm) * 1 | 0 | +|usbh_cdc_ncm.c | ~3300 | 2 * 2048(default) + 16 + 32 | sizeof(struct usbh_cdc_ncm) * 1 | 0 | +|usbh_bluetooth.c | ~1000 | 2 * 2048(default) | sizeof(struct usbh_bluetooth) * 1 | 0 | Among them, `sizeof(struct usbh_hub)` and `sizeof(struct usbh_hubport)` are affected by the following macros： @@ -145,13 +160,14 @@ Only standard and commercial USB IP are listed. | IP | device | host | Support status | |:----------------:|:----------:|:--------:|:--------------:| -| OHCI(intel) | none | OHCI | × | +| OHCI(intel) | none | OHCI | √ | | EHCI(intel) | none | EHCI | √ | | XHCI(intel) | none | XHCI | √ | | UHCI(intel) | none | UHCI | × | | DWC2(synopsys) | DWC2 | DWC2 | √ | | MUSB(mentor) | MUSB | MUSB | √ | | FOTG210(faraday)| FOTG210 | EHCI | √ | +| CHIPIDEA(synopsys)| CHIPIDEA | EHCI | √ | | CDNS2(cadence) | CDNS2 | CDNS2 | √ | | CDNS3(cadence) | CDNS3 | XHCI | × | | DWC3(synopsys) | DWC3 | XHCI | × | @@ -175,17 +191,27 @@ USB basic concepts and how the CherryUSB Device stack is implemented, see [Cherr |Bouffalolab | BL702/BL616/BL808 | bouffalolab/ehci|[bouffalo_sdk](https://github.com/CherryUSB/bouffalo_sdk)|<= latest | Long-term | |ST | STM32F1x | fsdev |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|<= latest | Long-term | |ST | STM32F4/STM32H7 | dwc2 |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|<= latest | Long-term | -|HPMicro | HPM6750 | hpm/ehci |[hpm_sdk](https://github.com/CherryUSB/hpm_sdk)|<= latest | Long-term | +|HPMicro | HPM6000/HPM5000 | hpm/ehci |[hpm_sdk](https://github.com/CherryUSB/hpm_sdk)|<= latest | Long-term | |Essemi | ES32F36xx | musb |[es32f369_repo](https://github.com/CherryUSB/cherryusb_es32)|<= latest | Long-term | -|Phytium | e2000 | pusb2/xhci |[phytium_repo](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)|v0.10.2 | Long-term | +|Phytium | e2000 | pusb2/xhci |[phytium_repo](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)|>=1.4.0 | Long-term | |Artinchip | d12x/d13x/d21x | aic/ehci/ohci |[luban-lite](https://gitee.com/artinchip/luban-lite)|<= latest | Long-term | -|Espressif | esp32s2/esp32s3 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|<= latest | the same with ST | -|AllwinnerTech | F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|<= latest | the same with Essemi | -|Bekencorp | bk7256/bk7258 | musb |[bk_idk](https://github.com/CherryUSB/bk_idk)| v0.7.0 | the same with Essemi | -|Sophgo | cv18xx | dwc2 |[cvi_alios_open](https://github.com/CherryUSB/cvi_alios_open)| v0.7.0 | the same with ST | +|Espressif | esp32s2/esp32s3/esp32p4 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|<= latest | Long-term | +|NXP | mcx | kinetis/chipidea/ehci |[nxp_mcx_repo](https://github.com/CherryUSB/cherryusb_mcx)|<= latest | Long-term | +|Kendryte | k230 | dwc2 |[k230_repo](https://github.com/CherryUSB/canmv_k230)|v1.2.0 | Long-term | +|AllwinnerTech | F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|<= latest | the same with musb | +|Bekencorp | bk7256/bk7258 | musb |[bk_idk](https://github.com/CherryUSB/bk_idk)| v0.7.0 | the same with musb | +|Sophgo | cv18xx | dwc2 |[cvi_alios_open](https://github.com/CherryUSB/cvi_alios_open)| v0.7.0 | TBD | |WCH | CH32V307/ch58x | ch32_usbfs/ch32_usbhs/ch58x |[wch_repo](https://github.com/CherryUSB/cherryusb_wch)|<= v0.10.2 | TBD | |Raspberry pi | rp2040 | rp2040 |[pico-examples](https://github.com/CherryUSB/pico-examples)|<= v0.10.2 | No more updated | +## Package Support + +CherryUSB package is available as follows: + +- [RT-Thread](https://packages.rt-thread.org/detail.html?package=CherryUSB) +- [YOC](https://www.xrvm.cn/document?temp=usb-host-protocol-stack-device-driver-adaptation-instructions&slug=yocbook) +- [ESP-Registry](https://components.espressif.com/components/cherry-embedded/cherryusb) + ## Commercial Support Refer to https://cherryusb.readthedocs.io/zh-cn/latest/support/index.html. @@ -198,4 +224,4 @@ CherryUSB discord: https://discord.com/invite/wFfvrSAey8. Thanks to the following companies for their support (in no particular order). - \ No newline at end of file + diff --git a/rt-thread/components/drivers/usb/cherryusb/README_zh.md b/rt-thread/components/drivers/usb/cherryusb/README_zh.md index 0aee5a7..50d2b6f 100644 --- a/rt-thread/components/drivers/usb/cherryusb/README_zh.md +++ b/rt-thread/components/drivers/usb/cherryusb/README_zh.md @@ -1,6 +1,16 @@ -# CherryUSB +

CherryUSB

+

+ + + + +

-[English](./README.md) +

+ 中文 + | + English +

CherryUSB 是一个小而美的、可移植性高的、用于嵌入式系统(带 USB IP)的 USB 主从协议栈。 @@ -22,7 +32,7 @@ CherryUSB 是一个小而美的、可移植性高的、用于嵌入式系统(带 为了方便用户使用 USB 接口，考虑到用户学习过 uart 和 dma，因此，设计的数据收发类接口具备以下优点： - 等价于使用 uart tx dma/uart rx dma -- 收发长度没有限制，用户不需要关心 USB 分包过程（porting 驱动做分包过程） +- 收发长度没有限制，用户不需要关心 USB 分包过程（分包过程在 porting 中处理） ### 易于发挥 USB 性能 @@ -32,7 +42,7 @@ CherryUSB 是一个小而美的、可移植性高的、用于嵌入式系统(带 - Memory zero copy - IP 如果带 DMA 则使用 DMA 模式（DMA 带硬件分包功能） - 长度无限制，方便对接硬件 DMA 并且发挥 DMA 的优势 -- 分包功能在中断中处理 +- 分包过程在中断中执行 ## 目录结构 @@ -65,21 +75,23 @@ CherryUSB Device 协议栈当前实现以下功能： - 支持 Device Firmware Upgrade CLASS (DFU) - 支持 USB MIDI CLASS (MIDI) - 支持 Remote NDIS (RNDIS) -- 支持 WINUSB1.0、WINUSB2.0(带 BOS ) +- 支持 WINUSB1.0、WINUSB2.0、WEBUSB、BOS - 支持 Vendor 类 class +- 支持 UF2 +- 支持 Android Debug Bridge (Only support shell) - 支持相同 USB IP 的多从机 CherryUSB Device 协议栈资源占用说明（GCC 10.2 with -O2）： | file | FLASH (Byte) | No Cache RAM (Byte) | RAM (Byte) | Heap (Byte) | |:-------------:|:--------------:|:-------------------------:|:-------------:|:----------------:| -|usbd_core.c | 3516 | 256(default) + 320 | 0 | 0 | -|usbd_cdc.c | 392 | 0 | 0 | 0 | -|usbd_msc.c | 2839 | 128 + 512(default) | 16 | 0 | -|usbd_hid.c | 364 | 0 | 0 | 0 | -|usbd_audio.c | 1455 | 0 | 0 | 0 | -|usbd_video.c | 2494 | 0 | 84 | 0 | -|usbd_rndis.c | 2109 | 3340 | 76 | 0 | +|usbd_core.c | ~4400 | 512(default) + 320 | 0 | 0 | +|usbd_cdc_acm.c | ~400 | 0 | 0 | 0 | +|usbd_msc.c | ~3800 | 128 + 512(default) | 16 | 0 | +|usbd_hid.c | ~360 | 0 | 0 | 0 | +|usbd_audio.c | ~1500 | 0 | 0 | 0 | +|usbd_video.c | ~2600 | 0 | 84 | 0 | +|usbd_rndis.c | ~2100 | 2 * 1580(default)+156+8 | 76 | 0 | ## Host 协议栈简介 @@ -87,6 +99,7 @@ CherryUSB Host 协议栈对挂载在 roothub、外部 hub 上的设备规范了 CherryUSB Host 协议栈当前实现以下功能： +- 支持 low speed, full speed, high speed 和 super speed 设备 - 自动加载支持的Class 驱动 - 支持阻塞式传输和异步传输 - 支持复合设备 @@ -98,8 +111,9 @@ CherryUSB Host 协议栈当前实现以下功能： - Support USB Audio CLASS (UAC1.0) - 支持 Remote NDIS (RNDIS) - 支持 USB Bluetooth (支持 nimble and zephyr bluetooth 协议栈，支持 **CLASS: 0xE0** 或者厂家自定义类，类似于 cdc acm 功能) -- 支持 Vendor 类 class +- 支持 Vendor 类 class (serial, net, wifi) - 支持 USB modeswitch +- 支持 Android Open Accessory - 支持相同 USB IP 的多主机 同时，CherryUSB Host 协议栈还提供了 lsusb 的功能，借助 shell 插件可以查看所有挂载设备的信息，包括外部 hub 上的设备的信息。 @@ -108,16 +122,17 @@ CherryUSB Host 协议栈资源占用说明（GCC 10.2 with -O2）： | file | FLASH (Byte) | No Cache RAM (Byte) | RAM (Byte) | Heap (Byte) | |:-------------:|:--------------:|:-------------------------------:|:---------------------------:|:------------:| -|usbh_core.c | ~7700 | 512 + 8 * (1+x) *n | 28 | 0 | -|usbh_hub.c | ~5600 | 32 + 4* (1+x) | 12 + sizeof(struct usbh_hub) * (1+x) | 0 | -|usbh_cdc_acm.c | ~1200 | 7 | 4 + sizeof(struct usbh_cdc_acm) * x | 0 | -|usbh_msc.c | ~2500 | 32 | 4 + sizeof(struct usbh_msc) * x | 0 | -|usbh_hid.c | ~1000 | 128 | 4 + sizeof(struct usbh_hid) * x | 0 | -|usbh_video.c | ~3700 | 128 | 4 + sizeof(struct usbh_video) * x | 0 | -|usbh_audio.c | ~3100 | 128 | 4 + sizeof(struct usbh_audio) * x | 0 | -|usbh_rndis.c | ~3900 | 4096 + 2 * 2048(default)| sizeof(struct usbh_rndis) * 1 | 0 | -|usbh_cdc_ecm.c | ~2500 | 2 * 1514 | sizeof(struct usbh_cdc_ecm) * 1 | 0 | -|usbh_bluetooth.c | ~2300 | 2 * 2048(default) | sizeof(struct usbh_bluetooth) * 1 | 0 | +|usbh_core.c | ~9000 | 512 + 8 * (1+x) *n | 28 | raw_config_desc | +|usbh_hub.c | ~6000 | 32 + 4 * (1+x) | 12 + sizeof(struct usbh_hub) * (1+x) | 0 | +|usbh_cdc_acm.c | ~900 | 7 | 4 + sizeof(struct usbh_cdc_acm) * x | 0 | +|usbh_msc.c | ~2700 | 64 | 4 + sizeof(struct usbh_msc) * x | 0 | +|usbh_hid.c | ~1400 | 256 | 4 + sizeof(struct usbh_hid) * x | 0 | +|usbh_video.c | ~3800 | 128 | 4 + sizeof(struct usbh_video) * x | 0 | +|usbh_audio.c | ~4100 | 128 | 4 + sizeof(struct usbh_audio) * x | 0 | +|usbh_rndis.c | ~4200 | 512 + 2 * 2048(default)| sizeof(struct usbh_rndis) * 1 | 0 | +|usbh_cdc_ecm.c | ~2200 | 2 * 1514 + 16 | sizeof(struct usbh_cdc_ecm) * 1 | 0 | +|usbh_cdc_ncm.c | ~3300 | 2 * 2048(default) + 16 + 32 | sizeof(struct usbh_cdc_ncm) * 1 | 0 | +|usbh_bluetooth.c | ~1000 | 2 * 2048(default) | sizeof(struct usbh_bluetooth) * 1 | 0 | 其中，`sizeof(struct usbh_hub)` 和 `sizeof(struct usbh_hubport)` 受以下宏影响： @@ -145,13 +160,14 @@ x 受以下宏影响： | IP | device | host | Support status | |:----------------:|:----------:|:--------:|:--------------:| -| OHCI(intel) | none | OHCI | × | +| OHCI(intel) | none | OHCI | √ | | EHCI(intel) | none | EHCI | √ | | XHCI(intel) | none | XHCI | √ | | UHCI(intel) | none | UHCI | × | | DWC2(synopsys) | DWC2 | DWC2 | √ | | MUSB(mentor) | MUSB | MUSB | √ | | FOTG210(faraday)| FOTG210 | EHCI | √ | +| CHIPIDEA(synopsys)| CHIPIDEA | EHCI | √ | | CDNS2(cadence) | CDNS2 | CDNS2 | √ | | CDNS3(cadence) | CDNS3 | XHCI | × | | DWC3(synopsys) | DWC3 | XHCI | × | @@ -176,20 +192,30 @@ CherryUSB 快速入门、USB 基本概念，API 手册，Class 基本概念和 |Bouffalolab | BL702/BL616/BL808 | bouffalolab/ehci|[bouffalo_sdk](https://github.com/CherryUSB/bouffalo_sdk)|<= latest | Long-term | |ST | STM32F1x | fsdev |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|<= latest | Long-term | |ST | STM32F4/STM32H7 | dwc2 |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|<= latest | Long-term | -|HPMicro | HPM6750 | hpm/ehci |[hpm_sdk](https://github.com/CherryUSB/hpm_sdk)|<= latest | Long-term | +|HPMicro | HPM6000/HPM5000 | hpm/ehci |[hpm_sdk](https://github.com/CherryUSB/hpm_sdk)|<= latest | Long-term | |Essemi | ES32F36xx | musb |[es32f369_repo](https://github.com/CherryUSB/cherryusb_es32)|<= latest | Long-term | -|Phytium | e2000 | pusb2/xhci |[phytium_repo](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)|v0.10.2 | Long-term | +|Phytium | e2000 | pusb2/xhci |[phytium_repo](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)|>=1.4.0 | Long-term | |Artinchip | d12x/d13x/d21x | aic/ehci/ohci |[luban-lite](https://gitee.com/artinchip/luban-lite)|<= latest | Long-term | -|Espressif | esp32s2/esp32s3 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|<= latest | the same with ST | -|AllwinnerTech | F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|<= latest | the same with Essemi | -|Bekencorp | bk7256/bk7258 | musb |[bk_idk](https://github.com/CherryUSB/bk_idk)| v0.7.0 | the same with Essemi | -|Sophgo | cv18xx | dwc2 |[cvi_alios_open](https://github.com/CherryUSB/cvi_alios_open)| v0.7.0 | the same with ST | +|Espressif | esp32s2/esp32s3/esp32p4 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|<= latest | Long-term | +|NXP | mcx | kinetis/chipidea/ehci |[nxp_mcx_repo](https://github.com/CherryUSB/cherryusb_mcx)|<= latest | Long-term | +|Kendryte | k230 | dwc2 |[k230_repo](https://github.com/CherryUSB/canmv_k230)|v1.2.0 | Long-term | +|AllwinnerTech | F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|<= latest | the same with musb | +|Bekencorp | bk7256/bk7258 | musb |[bk_idk](https://github.com/CherryUSB/bk_idk)| v0.7.0 | the same with musb | +|Sophgo | cv18xx | dwc2 |[cvi_alios_open](https://github.com/CherryUSB/cvi_alios_open)| v0.7.0 | TBD | |WCH | CH32V307/ch58x | ch32_usbfs/ch32_usbhs/ch58x |[wch_repo](https://github.com/CherryUSB/cherryusb_wch)|<= v0.10.2 | TBD | |Raspberry pi | rp2040 | rp2040 |[pico-examples](https://github.com/CherryUSB/pico-examples)|<= v0.10.2 | No more updated | +## 软件包支持 + +CherryUSB 软件包可以通过以下方式获取: + +- [RT-Thread](https://packages.rt-thread.org/detail.html?package=CherryUSB) +- [YOC](https://www.xrvm.cn/document?temp=usb-host-protocol-stack-device-driver-adaptation-instructions&slug=yocbook) +- [ESP-Registry](https://components.espressif.com/components/cherry-embedded/cherryusb) + ## 商业支持 -参考 https://cherryusb.readthedocs.io/zh-cn/latest/support/index.html。 +参考 https://cherryusb.readthedocs.io/zh-cn/latest/support/index.html 。 ## 联系 @@ -200,4 +226,4 @@ CherryUSB 微信群：与我联系后邀请加入 感谢以下企业支持（顺序不分先后）。 - + diff --git a/rt-thread/components/drivers/usb/cherryusb/SConscript b/rt-thread/components/drivers/usb/cherryusb/SConscript index ee4dc91..58d0aa0 100644 --- a/rt-thread/components/drivers/usb/cherryusb/SConscript +++ b/rt-thread/components/drivers/usb/cherryusb/SConscript @@ -15,6 +15,8 @@ path += [cwd + '/class/vendor/net'] path += [cwd + '/class/vendor/serial'] src = [] +LIBS = [] +LIBPATH = [] CPPDEFINES = [] # USB DEVICE @@ -43,6 +45,9 @@ if GetDepend(['RT_CHERRYUSB_DEVICE']): if GetDepend(['RT_CHERRYUSB_DEVICE_DWC2_HC']): src += Glob('port/dwc2/usb_dc_dwc2.c') src += Glob('port/dwc2/usb_glue_hc.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_DWC2_KENDRYTE']): + src += Glob('port/dwc2/usb_dc_dwc2.c') + src += Glob('port/dwc2/usb_glue_kendryte.c') if GetDepend(['RT_CHERRYUSB_DEVICE_DWC2_CUSTOM']): src += Glob('port/dwc2/usb_dc_dwc2.c') if GetDepend(['RT_CHERRYUSB_DEVICE_MUSB_ES']): @@ -56,6 +61,14 @@ if GetDepend(['RT_CHERRYUSB_DEVICE']): src += Glob('port/musb/usb_glue_bk.c') if GetDepend(['RT_CHERRYUSB_DEVICE_MUSB_CUSTOM']): src += Glob('port/musb/usb_dc_musb.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_KINETIS_MCX']): + src += Glob('port/kinetis/usb_dc_kinetis.c') + src += Glob('port/kinetis/usb_glue_mcx.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_KINETIS_CUSTOM']): + src += Glob('port/kinetis/usb_dc_kinetis.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_CHIPIDEA_MCX']): + src += Glob('port/chipidea/usb_dc_chipidea.c') + src += Glob('port/chipidea/usb_glue_mcx.c') if GetDepend(['RT_CHERRYUSB_DEVICE_BL']): src += Glob('port/bouffalolab/usb_dc_bl.c') if GetDepend(['RT_CHERRYUSB_DEVICE_HPM']): @@ -68,9 +81,18 @@ if GetDepend(['RT_CHERRYUSB_DEVICE']): src += Glob('port/ch32/usb_dc_usbhs.c') else: src += Glob('port/ch32/usb_dc_usbfs.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_PUSB2']): + path += [cwd + '/port/xhci/rt-thread'] + src += Glob('port/pusb2/rt-thread/usb_dc_glue_phytium.c') + if GetDepend(['ARCH_ARMV8']): + LIBPATH = [cwd + '/port/pusb2'] + LIBS = ['libpusb2_dc_a64.a'] + if GetDepend(['ARCH_ARM_CORTEX_A']): + LIBPATH = [cwd + '/port/pusb2'] + LIBS = ['libpusb2_dc_a32_softfp_neon.a'] if GetDepend(['RT_CHERRYUSB_DEVICE_CDC_ACM']): - src += Glob('class/cdc/usbd_cdc.c') + src += Glob('class/cdc/usbd_cdc_acm.c') if GetDepend(['RT_CHERRYUSB_DEVICE_HID']): src += Glob('class/hid/usbd_hid.c') if GetDepend(['RT_CHERRYUSB_DEVICE_MSC']): @@ -140,10 +162,14 @@ if GetDepend(['RT_CHERRYUSB_HOST']): src += Glob('port/ehci/usb_hc_ehci.c') src += Glob('port/ehci/usb_glue_aic.c') src += Glob('port/ohci/usb_hc_ohci.c') - if GetDepend(['RT_CHERRYUSB_HOST_EHCI_NUVOTON_NUC980']): + if GetDepend(['RT_CHERRYUSB_HOST_EHCI_MCX']): + path += [cwd + '/port/chipidea'] + src += Glob('port/ehci/usb_hc_ehci.c') + src += Glob('port/ehci/usb_glue_mcx.c') + if GetDepend(['RT_CHERRYUSB_HOST_EHCI_NUC980']): src += Glob('port/ehci/usb_hc_ehci.c') src += Glob('port/ehci/usb_glue_nuc980.c') - if GetDepend(['RT_CHERRYUSB_HOST_EHCI_NUVOTON_MA35D0']): + if GetDepend(['RT_CHERRYUSB_HOST_EHCI_MA35D0']): src += Glob('port/ehci/usb_hc_ehci.c') src += Glob('port/ehci/usb_glue_ma35d0.c') if GetDepend(['RT_CHERRYUSB_HOST_EHCI_CUSTOM']): @@ -154,6 +180,9 @@ if GetDepend(['RT_CHERRYUSB_HOST']): if GetDepend(['RT_CHERRYUSB_HOST_DWC2_ESP']): src += Glob('port/dwc2/usb_hc_dwc2.c') src += Glob('port/dwc2/usb_glue_esp.c') + if GetDepend(['RT_CHERRYUSB_HOST_DWC2_KENDRYTE']): + src += Glob('port/dwc2/usb_hc_dwc2.c') + src += Glob('port/dwc2/usb_glue_kendryte.c') if GetDepend(['RT_CHERRYUSB_HOST_DWC2_CUSTOM']): src += Glob('port/dwc2/usb_hc_dwc2.c') if GetDepend(['RT_CHERRYUSB_HOST_MUSB_STANDARD']): @@ -169,6 +198,31 @@ if GetDepend(['RT_CHERRYUSB_HOST']): src += Glob('port/musb/usb_glue_bk.c') if GetDepend(['RT_CHERRYUSB_HOST_MUSB_CUSTOM']): src += Glob('port/musb/usb_hc_musb.c') + if GetDepend(['RT_CHERRYUSB_HOST_KINETIS_MCX']): + src += Glob('port/kinetis/usb_hc_kinetis.c') + src += Glob('port/kinetis/usb_glue_mcx.c') + if GetDepend(['RT_CHERRYUSB_HOST_KINETIS_CUSTOM']): + src += Glob('port/kinetis/usb_hc_kinetis.c') + if GetDepend(['RT_CHERRYUSB_HOST_PUSB2']): + path += [cwd + '/port/pusb2/rt-thread'] + src += Glob('port/pusb2/rt-thread/usb_hc_glue_phytium.c') + if GetDepend(['ARCH_ARMV8']): + LIBPATH = [cwd + '/port/pusb2'] + LIBS = ['libpusb2_hc_a64.a'] + if GetDepend(['ARCH_ARM_CORTEX_A']): + LIBPATH = [cwd + '/port/pusb2'] + LIBS = ['libpusb2_hc_a32_softfp_neon.a'] + + if GetDepend(['RT_CHERRYUSB_HOST_XHCI']): + path += [cwd + '/port/xhci/phytium/rt-thread'] + src += Glob('port/xhci/phytium/rt-thread/usb_glue_phytium_plat.c') + src += Glob('port/xhci/phytium/rt-thread/usb_glue_phytium.c') + if GetDepend(['ARCH_ARMV8']): + LIBPATH = [cwd + '/port/xhci/phytium'] + LIBS = ['libxhci_a64.a'] + if GetDepend(['ARCH_ARM_CORTEX_A']): + LIBPATH = [cwd + '/port/xhci/phytium'] + LIBS = ['libxhci_a32_softfp_neon.a'] if GetDepend(['RT_CHERRYUSB_HOST_CDC_ACM']): src += Glob('class/cdc/usbh_cdc_acm.c') @@ -217,7 +271,7 @@ if GetDepend(['RT_CHERRYUSB_HOST']): src += Glob('platform/rtthread/usb_msh.c') src += Glob('platform/rtthread/usb_check.c') -group = DefineGroup('CherryUSB', src, depend = ['RT_USING_CHERRYUSB'], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('CherryUSB', src, depend = ['RT_USING_CHERRYUSB'], LIBS = LIBS, LIBPATH=LIBPATH, CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/rt-thread/components/drivers/usb/cherryusb/VERSION b/rt-thread/components/drivers/usb/cherryusb/VERSION index 8a0bfa8..340d4ae 100644 --- a/rt-thread/components/drivers/usb/cherryusb/VERSION +++ b/rt-thread/components/drivers/usb/cherryusb/VERSION @@ -1,5 +1,5 @@ VERSION_MAJOR = 1 -VERSION_MINOR = 3 -PATCHLEVEL = 1 +VERSION_MINOR = 4 +PATCHLEVEL = 2 VERSION_TWEAK = 0 EXTRAVERSION = 0 diff --git a/rt-thread/components/drivers/usb/cherryusb/cherryusb.cmake b/rt-thread/components/drivers/usb/cherryusb/cherryusb.cmake index d8451d2..2717170 100644 --- a/rt-thread/components/drivers/usb/cherryusb/cherryusb.cmake +++ b/rt-thread/components/drivers/usb/cherryusb/cherryusb.cmake @@ -36,14 +36,17 @@ ${CMAKE_CURRENT_LIST_DIR}/class/audio ${CMAKE_CURRENT_LIST_DIR}/class/video ${CMAKE_CURRENT_LIST_DIR}/class/wireless ${CMAKE_CURRENT_LIST_DIR}/class/midi +${CMAKE_CURRENT_LIST_DIR}/class/adb ${CMAKE_CURRENT_LIST_DIR}/class/vendor/net ${CMAKE_CURRENT_LIST_DIR}/class/vendor/serial +${CMAKE_CURRENT_LIST_DIR}/class/vendor/wifi +${CMAKE_CURRENT_LIST_DIR}/class/aoa ) if(CONFIG_CHERRYUSB_DEVICE) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/core/usbd_core.c) - if(CONFIG_CHERRYUSB_DEVICE_CDC) - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/cdc/usbd_cdc.c) + if(CONFIG_CHERRYUSB_DEVICE_CDC_ACM) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/cdc/usbd_cdc_acm.c) endif() if(CONFIG_CHERRYUSB_DEVICE_HID) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/hid/usbd_hid.c) @@ -69,6 +72,9 @@ if(CONFIG_CHERRYUSB_DEVICE) if(CONFIG_CHERRYUSB_DEVICE_DFU) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/dfu/usbd_dfu.c) endif() + if(CONFIG_CHERRYUSB_DEVICE_ADB) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/adb/usbd_adb.c) + endif() if(DEFINED CONFIG_CHERRYUSB_DEVICE_DCD) if("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "fsdev") @@ -97,6 +103,12 @@ if(CONFIG_CHERRYUSB_DEVICE) elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "musb_bk") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_dc_musb.c) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_glue_bk.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "chipidea_mcx") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/chipidea/usb_dc_chipidea.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/chipidea/usb_glue_mcx.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "kinetis_mcx") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/kinetis/usb_dc_kinetis.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/kinetis/usb_glue_mcx.c) elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "hpm") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/hpm/usb_dc_hpm.c) elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "bl") @@ -121,6 +133,9 @@ if(CONFIG_CHERRYUSB_HOST) if(CONFIG_CHERRYUSB_HOST_CDC_ECM) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/cdc/usbh_cdc_ecm.c) endif() + if(CONFIG_CHERRYUSB_HOST_CDC_RNDIS) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/wireless/usbh_rndis.c) + endif() if(CONFIG_CHERRYUSB_HOST_CDC_NCM) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/cdc/usbh_cdc_ncm.c) endif() @@ -142,18 +157,10 @@ if(CONFIG_CHERRYUSB_HOST) endif() if(CONFIG_CHERRYUSB_HOST_VIDEO) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/video/usbh_video.c) - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherryrb/chry_ringbuffer.c) - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherrypool/chry_pool.c) - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherrypool/usbh_uvc_queue.c) - list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherryrb) - list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherrypool) endif() if(CONFIG_CHERRYUSB_HOST_AUDIO) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/audio/usbh_audio.c) endif() - if(CONFIG_CHERRYUSB_HOST_CDC_RNDIS) - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/wireless/usbh_rndis.c) - endif() if(CONFIG_CHERRYUSB_HOST_BLUETOOTH) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/wireless/usbh_bluetooth.c) @@ -209,6 +216,12 @@ if(CONFIG_CHERRYUSB_HOST) if(CONFIG_CHERRYUSB_HOST_PL2303) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/serial/usbh_pl2303.c) endif() + if(CONFIG_CHERRYUSB_HOST_BL616) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/wifi/usbh_bl616.c) + endif() + if(CONFIG_CHERRYUSB_HOST_AOA) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/aoa/usbh_aoa.c) + endif() if(DEFINED CONFIG_CHERRYUSB_HOST_HCD) if("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "ehci_bouffalo") @@ -226,6 +239,12 @@ if(CONFIG_CHERRYUSB_HOST) #list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_hc_ehci_iso.c) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_glue_aic.c) list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/port/ehci) + elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "ehci_mcx") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_hc_ehci.c) + #list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_hc_ehci_iso.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_glue_mcx.c) + list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/port/ehci) + list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/port/chipidea) elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "ehci_nuvoton") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_hc_ehci.c) #list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_hc_ehci_iso.c) @@ -248,6 +267,9 @@ if(CONFIG_CHERRYUSB_HOST) elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "musb_bk") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_hc_musb.c) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_glue_bk.c) + elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "kinetis_mcx") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/kinetis/usb_hc_kinetis.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/kinetis/usb_glue_mcx.c) endif() endif() @@ -260,5 +282,25 @@ if(DEFINED CONFIG_CHERRYUSB_OSAL) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/usb_osal_rtthread.c) elseif("${CONFIG_CHERRYUSB_OSAL}" STREQUAL "yoc") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/usb_osal_yoc.c) + elseif("${CONFIG_CHERRYUSB_OSAL}" STREQUAL "idf") + list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/osal/idf) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/idf/usb_osal_idf.c) + elseif("${CONFIG_CHERRYUSB_OSAL}" STREQUAL "threadx") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/usb_osal_threadx.c) + endif() +endif() + +if(CONFIG_CHERRYRB) +list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherryrb/chry_ringbuffer.c) +list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherryrb) +endif() + +if(CONFIG_CHERRYMP) +list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherrymp/chry_mempool.c) +list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherrymp) + if("${CONFIG_CHERRYUSB_OSAL}" STREQUAL "freertos") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherrymp/chry_mempool_osal_freertos.c) + elseif("${CONFIG_CHERRYUSB_OSAL}" STREQUAL "rtthread") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherrymp/chry_mempool_osal_rtthread.c) endif() endif() \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/cherryusb_config_template.h b/rt-thread/components/drivers/usb/cherryusb/cherryusb_config_template.h index 493f8a4..e7d5230 100644 --- a/rt-thread/components/drivers/usb/cherryusb/cherryusb_config_template.h +++ b/rt-thread/components/drivers/usb/cherryusb/cherryusb_config_template.h @@ -6,16 +6,10 @@ #ifndef CHERRYUSB_CONFIG_H #define CHERRYUSB_CONFIG_H -#define CHERRYUSB_VERSION 0x010301 -#define CHERRYUSB_VERSION_STR "v1.3.1" - /* ================ USB common Configuration ================ */ #define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) -#define usb_malloc(size) malloc(size) -#define usb_free(ptr) free(ptr) - #ifndef CONFIG_USB_DBG_LEVEL #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO #endif @@ -72,6 +66,10 @@ #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" #endif +/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ +// #define CONFIG_USBDEV_MSC_POLLING + +/* move msc read & write from isr to thread */ // #define CONFIG_USBDEV_MSC_THREAD #ifndef CONFIG_USBDEV_MSC_PRIO @@ -210,6 +208,9 @@ #define CONFIG_USBDEV_EP_NUM 8 #endif +/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. */ +// #define CONFIG_USB_HS + /* ---------------- FSDEV Configuration ---------------- */ //#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference @@ -220,7 +221,7 @@ // #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4) /* IN Endpoints Max packet Size / 4 */ // #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4) -// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4) +// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (1024 / 4) // #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4) // #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4) // #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4) @@ -229,6 +230,8 @@ // #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4) // #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_DMA_ENABLE + /* ---------------- MUSB Configuration ---------------- */ // #define CONFIG_USB_MUSB_SUNXI @@ -268,7 +271,7 @@ * (largest USB packet used / 4) + 1 for status information + 1 transfer complete + * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario */ -// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4) +// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE)) /* ---------------- MUSB Configuration ---------------- */ // #define CONFIG_USB_MUSB_SUNXI diff --git a/rt-thread/components/drivers/usb/cherryusb/class/adb/usbd_adb.c b/rt-thread/components/drivers/usb/cherryusb/class/adb/usbd_adb.c new file mode 100644 index 0000000..7629ea3 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/class/adb/usbd_adb.c @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_adb.h" + +#define ADB_OUT_EP_IDX 0 +#define ADB_IN_EP_IDX 1 + +#define ADB_STATE_READ_MSG 0 +#define ADB_STATE_READ_DATA 1 +#define ADB_STATE_WRITE_MSG 2 +#define ADB_STATE_WRITE_DATA 3 +#define ADB_STATE_AWRITE_MSG 4 +#define ADB_STATE_AWRITE_DATA 5 + +#define MAX_PAYLOAD_V1 (4 * 1024) +#define MAX_PAYLOAD_V2 (256 * 1024) +#define MAX_PAYLOAD MAX_PAYLOAD_V1 +#define A_VERSION 0x01000000 + +#define A_SYNC 0x434e5953 +#define A_CNXN 0x4e584e43 +#define A_OPEN 0x4e45504f +#define A_OKAY 0x59414b4f +#define A_CLSE 0x45534c43 +#define A_WRTE 0x45545257 +#define A_AUTH 0x48545541 + +struct adb_msg { + uint32_t command; /* command identifier constant (A_CNXN, ...) */ + uint32_t arg0; /* first argument */ + uint32_t arg1; /* second argument */ + uint32_t data_length; /* length of payload (0 is allowed) */ + uint32_t data_crc32; /* crc32 of data payload */ + uint32_t magic; /* command ^ 0xffffffff */ +}; + +struct adb_packet { + struct adb_msg msg; + uint8_t payload[MAX_PAYLOAD]; +}; + +struct usbd_adb { + uint8_t state; + uint8_t common_state; + uint8_t write_state; + bool writable; + uint32_t localid; + uint32_t shell_remoteid; + uint32_t file_remoteid; +} adb_client; + +static struct usbd_endpoint adb_ep_data[2]; + +USB_NOCACHE_RAM_SECTION struct adb_packet tx_packet; +USB_NOCACHE_RAM_SECTION struct adb_packet rx_packet; + +static inline uint32_t adb_packet_checksum(struct adb_packet *packet) +{ + uint32_t sum = 0; + uint32_t i; + + for (i = 0; i < packet->msg.data_length; ++i) { + sum += (uint32_t)(packet->payload[i]); + } + + return sum; +} + +static uint32_t usbd_adb_get_remoteid(uint32_t localid) +{ + if (localid == ADB_SHELL_LOALID) { + return adb_client.shell_remoteid; + } else { + return adb_client.file_remoteid; + } +} + +static void adb_send_msg(struct adb_packet *packet) +{ + adb_client.common_state = ADB_STATE_WRITE_MSG; + + packet->msg.data_crc32 = adb_packet_checksum(packet); + packet->msg.magic = packet->msg.command ^ 0xffffffff; + + usbd_ep_start_write(0, adb_ep_data[ADB_IN_EP_IDX].ep_addr, (uint8_t *)&packet->msg, sizeof(struct adb_msg)); +} + +static void adb_send_okay(struct adb_packet *packet, uint32_t localid) +{ + packet->msg.command = A_OKAY; + packet->msg.arg0 = localid; + packet->msg.arg1 = usbd_adb_get_remoteid(localid); + packet->msg.data_length = 0; + + adb_send_msg(&tx_packet); +} + +static void adb_send_close(struct adb_packet *packet, uint32_t localid, uint32_t remoteid) +{ + packet->msg.command = A_CLSE; + packet->msg.arg0 = localid; + packet->msg.arg1 = remoteid; + packet->msg.data_length = 0; + + adb_send_msg(&tx_packet); +} + +void usbd_adb_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)ep; + + if (adb_client.common_state == ADB_STATE_READ_MSG) { + if (nbytes != sizeof(struct adb_msg)) { + USB_LOG_ERR("invalid adb msg size:%d\r\n", nbytes); + return; + } + + USB_LOG_DBG("command:%x arg0:%x arg1:%x len:%d\r\n", + rx_packet.msg.command, + rx_packet.msg.arg0, + rx_packet.msg.arg1, + rx_packet.msg.data_length); + + if (rx_packet.msg.data_length) { + /* setup next out ep read transfer */ + adb_client.common_state = ADB_STATE_READ_DATA; + usbd_ep_start_read(busid, adb_ep_data[ADB_OUT_EP_IDX].ep_addr, rx_packet.payload, rx_packet.msg.data_length); + } else { + if (rx_packet.msg.command == A_CLSE) { + adb_client.writable = false; + usbd_adb_notify_write_done(); + USB_LOG_INFO("Close remoteid:%x\r\n", rx_packet.msg.arg0); + } + adb_client.common_state = ADB_STATE_READ_MSG; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, adb_ep_data[ADB_OUT_EP_IDX].ep_addr, (uint8_t *)&rx_packet.msg, sizeof(struct adb_msg)); + } + } else if (adb_client.common_state == ADB_STATE_READ_DATA) { + switch (rx_packet.msg.command) { + case A_SYNC: + + break; + case A_CNXN: /* CONNECT(version, maxdata, "system-id-string") */ + char *support_feature = "device::" + "ro.product.name=cherryadb;" + "ro.product.model=cherrysh;" + "ro.product.device=cherryadb;" + "features=cmd,shell_v1"; + + tx_packet.msg.command = A_CNXN; + tx_packet.msg.arg0 = A_VERSION; + tx_packet.msg.arg1 = MAX_PAYLOAD; + tx_packet.msg.data_length = strlen(support_feature); + memcpy(tx_packet.payload, support_feature, strlen(support_feature)); + + adb_send_msg(&tx_packet); + + adb_client.writable = false; + break; + case A_OPEN: /* OPEN(local-id, 0, "destination") */ + rx_packet.payload[rx_packet.msg.data_length] = '\0'; + + if (strncmp((const char *)rx_packet.payload, "shell:", 6) == 0) { + adb_client.localid = ADB_SHELL_LOALID; + adb_client.shell_remoteid = rx_packet.msg.arg0; + adb_send_okay(&tx_packet, ADB_SHELL_LOALID); + + USB_LOG_INFO("Open shell service, remoteid:%x\r\n", rx_packet.msg.arg0); + } else if (strncmp((const char *)rx_packet.payload, "sync:", 5) == 0) { + adb_client.localid = ADB_FILE_LOALID; + adb_client.file_remoteid = rx_packet.msg.arg0; + adb_send_okay(&tx_packet, ADB_FILE_LOALID); + USB_LOG_INFO("Open file service, remoteid:%x\r\n", rx_packet.msg.arg0); + } + break; + case A_OKAY: + + break; + case A_CLSE: + + break; + case A_WRTE: /* WRITE(local-id, remote-id, "data") */ + if ((rx_packet.msg.arg0 == adb_client.shell_remoteid) && (rx_packet.msg.arg1 == ADB_SHELL_LOALID)) { + adb_send_okay(&tx_packet, rx_packet.msg.arg1); + } else if ((rx_packet.msg.arg0 == adb_client.file_remoteid) && (rx_packet.msg.arg1 == ADB_FILE_LOALID)) { + adb_send_okay(&tx_packet, rx_packet.msg.arg1); + } else { + adb_send_close(&tx_packet, 0, rx_packet.msg.arg0); + } + break; + case A_AUTH: + + break; + + default: + break; + } + } +} + +void usbd_adb_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)ep; + (void)nbytes; + + if (adb_client.common_state == ADB_STATE_WRITE_MSG) { + if (tx_packet.msg.data_length) { + adb_client.common_state = ADB_STATE_WRITE_DATA; + usbd_ep_start_write(busid, adb_ep_data[ADB_IN_EP_IDX].ep_addr, tx_packet.payload, tx_packet.msg.data_length); + } else { + if (rx_packet.msg.command == A_WRTE) { + adb_client.writable = true; + if (adb_client.localid == ADB_SHELL_LOALID) { + usbd_adb_notify_shell_read(rx_packet.payload, rx_packet.msg.data_length); + } else { + } + } + adb_client.common_state = ADB_STATE_READ_MSG; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, adb_ep_data[ADB_OUT_EP_IDX].ep_addr, (uint8_t *)&rx_packet.msg, sizeof(struct adb_msg)); + } + } else if (adb_client.common_state == ADB_STATE_WRITE_DATA) { + adb_client.common_state = ADB_STATE_READ_MSG; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, adb_ep_data[ADB_OUT_EP_IDX].ep_addr, (uint8_t *)&rx_packet.msg, sizeof(struct adb_msg)); + } else if (adb_client.write_state == ADB_STATE_AWRITE_MSG) { + if (tx_packet.msg.data_length) { + adb_client.write_state = ADB_STATE_AWRITE_DATA; + usbd_ep_start_write(busid, adb_ep_data[ADB_IN_EP_IDX].ep_addr, tx_packet.payload, tx_packet.msg.data_length); + } else { + } + } else if (adb_client.write_state == ADB_STATE_AWRITE_DATA) { + usbd_adb_notify_write_done(); + } +} + +void adb_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + (void)arg; + + switch (event) { + case USBD_EVENT_INIT: + break; + case USBD_EVENT_DEINIT: + break; + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONFIGURED: + adb_client.common_state = ADB_STATE_READ_MSG; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, adb_ep_data[ADB_OUT_EP_IDX].ep_addr, (uint8_t *)&rx_packet.msg, sizeof(struct adb_msg)); + break; + + default: + break; + } +} + +struct usbd_interface *usbd_adb_init_intf(uint8_t busid, struct usbd_interface *intf, uint8_t in_ep, uint8_t out_ep) +{ + (void)busid; + + intf->class_interface_handler = NULL; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = adb_notify_handler; + + adb_ep_data[ADB_OUT_EP_IDX].ep_addr = out_ep; + adb_ep_data[ADB_OUT_EP_IDX].ep_cb = usbd_adb_bulk_out; + adb_ep_data[ADB_IN_EP_IDX].ep_addr = in_ep; + adb_ep_data[ADB_IN_EP_IDX].ep_cb = usbd_adb_bulk_in; + + usbd_add_endpoint(busid, &adb_ep_data[ADB_OUT_EP_IDX]); + usbd_add_endpoint(busid, &adb_ep_data[ADB_IN_EP_IDX]); + + return intf; +} + +bool usbd_adb_can_write(void) +{ + return adb_client.writable; +} + +int usbd_abd_write(uint32_t localid, const uint8_t *data, uint32_t len) +{ + struct adb_packet *packet; + + packet = &tx_packet; + packet->msg.command = A_WRTE; + packet->msg.arg0 = localid; + packet->msg.arg1 = usbd_adb_get_remoteid(localid); + packet->msg.data_length = len; + memcpy(packet->payload, data, len); + + packet->msg.data_crc32 = adb_packet_checksum(packet); + packet->msg.magic = packet->msg.command ^ 0xffffffff; + + adb_client.write_state = ADB_STATE_AWRITE_MSG; + usbd_ep_start_write(0, adb_ep_data[ADB_IN_EP_IDX].ep_addr, (uint8_t *)&packet->msg, sizeof(struct adb_msg)); + return 0; +} + +void usbd_adb_close(uint32_t localid) +{ + adb_send_close(&tx_packet, 0, usbd_adb_get_remoteid(localid)); +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/adb/usbd_adb.h b/rt-thread/components/drivers/usb/cherryusb/class/adb/usbd_adb.h new file mode 100644 index 0000000..4dbc730 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/class/adb/usbd_adb.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_ADB_H +#define USBD_ADB_H + +#include + +#define ADB_SHELL_LOALID 0x01 +#define ADB_FILE_LOALID 0x02 + +// clang-format off +#define ADB_DESCRIPTOR_INIT(bFirstInterface, in_ep, out_ep, wMaxPacketSize) \ + USB_INTERFACE_DESCRIPTOR_INIT(bFirstInterface, 0x00, 0x02, 0xff, 0x42, 0x01, 0x02), \ + USB_ENDPOINT_DESCRIPTOR_INIT(in_ep, 0x02, wMaxPacketSize, 0x00), \ + USB_ENDPOINT_DESCRIPTOR_INIT(out_ep, 0x02, wMaxPacketSize, 0x00) +// clang-format on + +#ifdef __cplusplus +extern "C" { +#endif + +struct usbd_interface *usbd_adb_init_intf(uint8_t busid, struct usbd_interface *intf, uint8_t in_ep, uint8_t out_ep); + +void usbd_adb_notify_shell_read(uint8_t *data, uint32_t len); +void usbd_adb_notify_file_read(uint8_t *data, uint32_t len); +void usbd_adb_notify_write_done(void); +bool usbd_adb_can_write(void); +int usbd_abd_write(uint32_t localid, const uint8_t *data, uint32_t len); +void usbd_adb_close(uint32_t localid); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_ADB_H */ \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/aoa/usb_aoa.h b/rt-thread/components/drivers/usb/cherryusb/class/aoa/usb_aoa.h new file mode 100644 index 0000000..6b6c715 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/class/aoa/usb_aoa.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_AOA_H +#define USB_AOA_H + +//AOA 1.0 +#define AOA_ACCESSORY_VENDOR_ID 0x18D1 +#define AOA_ACCESSORY_PRODUCT_ID 0x2D00 +#define AOA_ACCESSORY_ADB_PRODUCT_ID 0x2D01 + +//AOA 2.0 +#define AOA_AUDIO_PRODUCT_ID 0x2D02 +#define AOA_AUDIO_ADB_PRODUCT_ID 0x2D03 +#define AOA_ACCESSORY_AUDIO_PRODUCT_ID 0x2D04 +#define AOA_ACCESSORY_AUDIO_ADB_PRODUCT_ID 0x2D05 + +//AOA 1.0 +#define AOA_ACCESSORY_GET_PROTOCOL 51 +#define AOA_ACCESSORY_SEND_STRING 52 +#define AOA_ACCESSORY_START 53 + +//AOA 2.0 +#define AOA_ACCESSORY_REGISTER_HID 54 +#define AOA_ACCESSORY_UNREGISTER_HID 55 +#define AOA_ACCESSORY_SET_HID_REPORT_DESC 56 +#define AOA_ACCESSORY_SEND_HID_EVENT 57 +#define AOA_ACCESSORY_SET_AUDIO_MODE 58 + +#define AOA_ACCESSORY_STRING_MANUFACTURER 0 +#define AOA_ACCESSORY_STRING_MODEL 1 +#define AOA_ACCESSORY_STRING_DESCRIPTION 2 +#define AOA_ACCESSORY_STRING_VERSION 3 +#define AOA_ACCESSORY_STRING_URI 4 +#define AOA_ACCESSORY_STRING_SERIAL 5 + +struct aoa_string_info { + char acc_manufacturer[64]; + char acc_model[64]; + char acc_description[64]; + char acc_version[64]; + char acc_uri[64]; + char acc_serial[64]; +}; + +#endif /* USB_AOA_H */ \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/aoa/usbh_aoa.c b/rt-thread/components/drivers/usb/cherryusb/class/aoa/usbh_aoa.c new file mode 100644 index 0000000..20cef52 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/class/aoa/usbh_aoa.c @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_aoa.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_aoa" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/aoa" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_aoa_buffer[128]; + +static struct usbh_aoa g_aoa_class; + +int usbh_aoa_switch(struct usbh_hubport *hport, struct aoa_string_info *info) +{ + struct usb_setup_packet *setup; + int ret; + + setup = hport->setup; + + if (setup == NULL) { + return -USB_ERR_INVAL; + } + + USB_LOG_INFO("Try switch into aoa mode\r\n"); + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_GET_PROTOCOL; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 2; + + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + USB_LOG_INFO("AOA version: v%d.%d\r\n", g_aoa_buffer[0], g_aoa_buffer[1]); + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_STRING; + setup->wValue = 0; + setup->wIndex = AOA_ACCESSORY_STRING_MANUFACTURER; + setup->wLength = strlen(info->acc_manufacturer) + 1; + + memcpy(g_aoa_buffer, info->acc_manufacturer, strlen(info->acc_manufacturer)); + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_STRING; + setup->wValue = 0; + setup->wIndex = AOA_ACCESSORY_STRING_MODEL; + setup->wLength = strlen(info->acc_model) + 1; + + memcpy(g_aoa_buffer, info->acc_model, strlen(info->acc_model)); + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_STRING; + setup->wValue = 0; + setup->wIndex = AOA_ACCESSORY_STRING_DESCRIPTION; + setup->wLength = strlen(info->acc_description) + 1; + + memcpy(g_aoa_buffer, info->acc_description, strlen(info->acc_description)); + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_STRING; + setup->wValue = 0; + setup->wIndex = AOA_ACCESSORY_STRING_VERSION; + setup->wLength = strlen(info->acc_version) + 1; + + memcpy(g_aoa_buffer, info->acc_version, strlen(info->acc_version)); + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_STRING; + setup->wValue = 0; + setup->wIndex = AOA_ACCESSORY_STRING_URI; + setup->wLength = strlen(info->acc_uri) + 1; + + memcpy(g_aoa_buffer, info->acc_uri, strlen(info->acc_uri)); + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_STRING; + setup->wValue = 0; + setup->wIndex = AOA_ACCESSORY_STRING_SERIAL; + setup->wLength = strlen(info->acc_serial) + 1; + + memcpy(g_aoa_buffer, info->acc_serial, strlen(info->acc_serial)); + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_START; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 0; + + ret = usbh_control_transfer(hport, setup, NULL); + if (ret < 0) { + return ret; + } + + USB_LOG_INFO("Switch into aoa mode success, wait usb device restart...\r\n"); + return 0; +} + +int usbh_aoa_register_hid(struct usbh_aoa *aoa_class, uint16_t id, uint8_t *report, uint32_t report_len) +{ + struct usb_setup_packet *setup; + int ret; + uint8_t len; + uint32_t offset; + + if (!aoa_class || !aoa_class->hport) { + return -USB_ERR_INVAL; + } + setup = aoa_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_REGISTER_HID; + setup->wValue = id; + setup->wIndex = report_len; + setup->wLength = 0; + + ret = usbh_control_transfer(aoa_class->hport, setup, NULL); + if (ret < 0) { + return ret; + } + + offset = 0; + while (report_len > 0) { + len = report_len > 64 ? 64 : report_len; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SET_HID_REPORT_DESC; + setup->wValue = id; + setup->wIndex = offset; + setup->wLength = len; + + memcpy(g_aoa_buffer, report + offset, len); + ret = usbh_control_transfer(aoa_class->hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + offset += len; + report_len -= len; + } + return ret; +} + +int usbh_aoa_send_hid_event(struct usbh_aoa *aoa_class, uint16_t id, uint8_t *event, uint32_t event_len) +{ + struct usb_setup_packet *setup; + int ret; + uint8_t len; + uint32_t offset; + + if (!aoa_class || !aoa_class->hport) { + return -USB_ERR_INVAL; + } + setup = aoa_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_HID_EVENT; + setup->wValue = id; + setup->wIndex = 0; + setup->wLength = event_len; + + memcpy(g_aoa_buffer, event, event_len); + return usbh_control_transfer(aoa_class->hport, setup, event); +} + +static int usbh_aoa_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret = 0; + + struct usbh_aoa *aoa_class = &g_aoa_class; + + memset(aoa_class, 0, sizeof(struct usbh_aoa)); + + aoa_class->hport = hport; + aoa_class->intf = intf; + + hport->config.intf[intf].priv = aoa_class; + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(aoa_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(aoa_class->bulkout, ep_desc); + } + } + + strncpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register AOA Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_aoa_run(aoa_class); + return 0; +} + +static int usbh_aoa_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_aoa *aoa_class = (struct usbh_aoa *)hport->config.intf[intf].priv; + + if (aoa_class) { + if (aoa_class->bulkin) { + usbh_kill_urb(&aoa_class->bulkin_urb); + } + + if (aoa_class->bulkout) { + usbh_kill_urb(&aoa_class->bulkout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister AOA Class:%s\r\n", hport->config.intf[intf].devname); + usbh_aoa_stop(aoa_class); + } + + memset(aoa_class, 0, sizeof(struct usbh_aoa)); + } + + return ret; +} + +__WEAK void usbh_aoa_run(struct usbh_aoa *aoa_class) +{ + (void)aoa_class; +} + +__WEAK void usbh_aoa_stop(struct usbh_aoa *aoa_class) +{ + (void)aoa_class; +} + +static const uint16_t aoa_id_table[][2] = { + { AOA_ACCESSORY_VENDOR_ID, AOA_ACCESSORY_PRODUCT_ID }, + { AOA_ACCESSORY_VENDOR_ID, AOA_ACCESSORY_ADB_PRODUCT_ID }, + { AOA_ACCESSORY_VENDOR_ID, AOA_AUDIO_PRODUCT_ID }, + { AOA_ACCESSORY_VENDOR_ID, AOA_AUDIO_ADB_PRODUCT_ID }, + { AOA_ACCESSORY_VENDOR_ID, AOA_ACCESSORY_AUDIO_PRODUCT_ID }, + { AOA_ACCESSORY_VENDOR_ID, AOA_ACCESSORY_AUDIO_ADB_PRODUCT_ID }, + { 0, 0 }, +}; + +const struct usbh_class_driver aoa_class_driver = { + .driver_name = "aoa", + .connect = usbh_aoa_connect, + .disconnect = usbh_aoa_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info aoa_intf_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0xff, + .bInterfaceProtocol = 0x00, + .id_table = aoa_id_table, + .class_driver = &aoa_class_driver +}; \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/aoa/usbh_aoa.h b/rt-thread/components/drivers/usb/cherryusb/class/aoa/usbh_aoa.h new file mode 100644 index 0000000..3b184e8 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/class/aoa/usbh_aoa.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_AOA_H +#define USBH_AOA_H + +#include "usb_aoa.h" + +struct usbh_aoa { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; + + uint8_t intf; + uint8_t minor; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_aoa_switch(struct usbh_hubport *hport, struct aoa_string_info *info); +int usbh_aoa_register_hid(struct usbh_aoa *aoa_class, uint16_t id, uint8_t *report, uint32_t report_len); +int usbh_aoa_send_hid_event(struct usbh_aoa *aoa_class, uint16_t id, uint8_t *event, uint32_t event_len); + +void usbh_aoa_run(struct usbh_aoa *aoa_class); +void usbh_aoa_stop(struct usbh_aoa *aoa_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_AOA_H */ \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/audio/usb_audio.h b/rt-thread/components/drivers/usb/cherryusb/class/audio/usb_audio.h index 2b3cdaf..ff7a9fe 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/audio/usb_audio.h +++ b/rt-thread/components/drivers/usb/cherryusb/class/audio/usb_audio.h @@ -132,11 +132,11 @@ #define AUDIO_FORMAT_ALAW 0x0004 #define AUDIO_FORMAT_MULAW 0x0005 -#define AUDIO_V2_FORMAT_PCM 0x00000001 -#define AUDIO_V2_FORMAT_PCM8 0x00000002 -#define AUDIO_V2_FORMAT_IEEE_FLOAT 0x00000004 -#define AUDIO_V2_FORMAT_ALAW 0x00000008 -#define AUDIO_V2_FORMAT_MULAW 0x00000010 +#define AUDIO_V2_FORMAT_PCM 0x00000001 +#define AUDIO_V2_FORMAT_PCM8 0x00000002 +#define AUDIO_V2_FORMAT_IEEE_FLOAT 0x00000004 +#define AUDIO_V2_FORMAT_ALAW 0x00000008 +#define AUDIO_V2_FORMAT_MULAW 0x00000010 /* bmChannelConfig: a bitmap field that indicates which spatial locations * are occupied by the channels present in the cluster. The bit allocations @@ -648,6 +648,18 @@ struct audio_cs_if_ac_feature_unit_descriptor { #define AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(ch, n) (7 + (ch + 1) * n) +struct audio_cs_if_ac_selector_unit_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bUnitID; + uint8_t bNrInPins; + uint8_t baSourceID[1]; + uint8_t iSelector; +} __PACKED; + +#define AUDIO_SIZEOF_AC_SELECTOR_UNIT_DESC(n) (6 + n) + struct audio_cs_if_as_general_descriptor { uint8_t bLength; uint8_t bDescriptorType; @@ -812,6 +824,60 @@ struct audio_cs_ep_ep_general_descriptor { #define AUDIO_AS_DESCRIPTOR_INIT_LEN(n) (0x09 + 0x09 + 0x07 + 0x08 + 3 * n + 0x09 + 0x07) +#define AUDIO_AS_ALTSETTING_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bTerminalLink, bNrChannels, bSubFrameSize, bBitResolution, bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval, ...) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + bAlternateSetting, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ \ + bTerminalLink, /* bTerminalLink : Unit ID of the Output Terminal*/ \ + 0x01, /* bDelay */ \ + WBVAL(AUDIO_FORMAT_PCM), /* wFormatTag : AUDIO_FORMAT_PCM */ \ + 0x08 + PP_NARG(__VA_ARGS__), /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType */ \ + bNrChannels, /* bNrChannels */ \ + bSubFrameSize, /* bSubFrameSize : Bytes per audio subframe */ \ + bBitResolution, /* bBitResolution : bits per sample */ \ + (PP_NARG(__VA_ARGS__)/3), /* bSamFreqType : only one frequency supported */ \ + __VA_ARGS__, /* tSamFreq : Audio sampling frequency coded on 3 bytes */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress : IN endpoint 1 */ \ + bmAttributes, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + bInterval, /* bInterval : one packet per frame */ \ + 0x00, /* bRefresh */ \ + 0x00, /* bSynchAddress */ \ + 0x07, /* bLength */ \ + AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ \ + AUDIO_EP_CONTROL_SAMPLING_FEQ, /* bmAttributes AUDIO_SAMPLING_FREQ_CONTROL */ \ + 0x00, /* bLockDelayUnits */ \ + 0x00, /* wLockDelay */ \ + 0x00 + +#define AUDIO_AS_ALTSETTING_DESCRIPTOR_INIT_LEN(n) (0x09 + 0x07 + 0x08 + 3 * n + 0x09 + 0x07) + +#define AUDIO_AS_ALTSETTING0_DESCRIPTOR_INIT(bInterfaceNumber) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + 0x00 /* iInterface */ + #define AUDIO_MS_STANDARD_DESCRIPTOR_INIT(bInterfaceNumber, bNumEndpoints) \ 0x09, /* bLength */ \ USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ @@ -1096,6 +1162,58 @@ struct audio_v2_control_range3_param_block { 0x00, /* wLockDelay */ \ 0x00 +#define AUDIO_V2_AS_ALTSETTING_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bTerminalLink, bNrChannels, bmChannelConfig, bSubslotSize, bBitResolution, bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + bAlternateSetting, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x10, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ \ + bTerminalLink, /* bTerminalLink : Unit ID of the Output or Input Terminal*/ \ + 0x00, /* bmControls */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType : AUDIO_FORMAT_TYPE_I */ \ + DBVAL(AUDIO_V2_FORMAT_PCM), /* bmFormats PCM */ \ + bNrChannels, /* bNrChannels */ \ + DBVAL(bmChannelConfig), /* bmChannelConfig */ \ + 0x00, /* iChannelNames */ \ + 0x06, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType */ \ + bSubslotSize, /* bSubslotSize */ \ + bBitResolution, /* bBitResolution */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress 3 out endpoint for Audio */ \ + bmAttributes, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* XXXX wMaxPacketSize in Bytes (SampleRate * SlotByteSize * NumChannels) */ \ + bInterval, /* bInterval */ \ + 0x08, /* bLength */ \ + AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ \ + 0x00, /* bmAttributes */ \ + 0x00, /* bmControls */ \ + 0x00, /* bLockDelayUnits */ \ + 0x00, /* wLockDelay */ \ + 0x00 + +#define AUDIO_V2_AS_ALTSETTING0_DESCRIPTOR_INIT(bInterfaceNumber) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + 0x00 /* iInterface */ + #define AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT(bInterfaceNumber, bTerminalLink, bNrChannels, bmChannelConfig, bSubslotSize, bBitResolution, bEndpointAddress, wMaxPacketSize, bInterval, bFeedbackEndpointAddress) \ 0x09, /* bLength */ \ USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ @@ -1150,12 +1268,13 @@ struct audio_v2_control_range3_param_block { bFeedbackEndpointAddress, /* bFeedbackEndpointAddress Revise Dir to bEndpointAddress */ \ 0x11, /* bmAttributes: TransferType=Isochronous SyncType=None EndpointType=Feedback */ \ WBVAL(4), /* XXXX wMaxPacketSize in Bytes */ \ - bInterval /* bInterval */ \ + bInterval /* bInterval */ // clang-format on -#define AUDIO_V2_AS_DESCRIPTOR_INIT_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08) -#define AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08 + 0x07) +#define AUDIO_V2_AS_DESCRIPTOR_INIT_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08) +#define AUDIO_V2_AS_ALTSETTING_DESCRIPTOR_INIT_LEN (0x09 + 0x10 + 0x06 + 0x07 + 0x08) +#define AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08 + 0x07) #define AUDIO_SAMPLE_FREQ_NUM(num) (uint8_t)(num), (uint8_t)((num >> 8)) #define AUDIO_SAMPLE_FREQ_3B(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16)) diff --git a/rt-thread/components/drivers/usb/cherryusb/class/audio/usbd_audio.c b/rt-thread/components/drivers/usb/cherryusb/class/audio/usbd_audio.c index c78c8ed..458f1c1 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/audio/usbd_audio.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/audio/usbd_audio.c @@ -62,7 +62,7 @@ static int audio_class_interface_request_handler(uint8_t busid, struct usb_setup setup->bRequest); uint8_t entity_id; - uint8_t ep; + uint8_t ep = 0; uint8_t subtype = 0x01; uint8_t control_selector; uint8_t ch; @@ -136,27 +136,26 @@ static int audio_class_interface_request_handler(uint8_t busid, struct usb_setup memcpy(&volume, *data, *len); if (volume < 0x8000) { volume_db = volume / 256; - } else if (volume > 0x8000) { - volume_db = (0xffff - volume + 1) / -256; + } else { + volume_db = (volume - 0x10000) / 256; } - volume_db += 128; /* 0 ~ 255 */ - USB_LOG_DBG("Set ep:0x%02x ch:%d volume:0x%04x\r\n", ep, ch, volume); + USB_LOG_DBG("Set ep:0x%02x ch:%d vol_hex:0x%04x, vol_db:%d dB\r\n", ep, ch, volume, volume_db); usbd_audio_set_volume(busid, ep, ch, volume_db); break; case AUDIO_REQUEST_GET_CUR: volume_db = usbd_audio_get_volume(busid, ep, ch); - volume_db -= 128; if (volume_db >= 0) { volume = volume_db * 256; } else { - volume = volume_db * 256 + 0xffff + 1; + volume = volume_db * 256 + 0x10000; } + USB_LOG_DBG("Get ep:0x%02x ch:%d vol_hex:0x%04x, vol_db:%d dB\r\n", ep, ch, volume, volume_db); memcpy(*data, &volume, 2); *len = 2; break; case AUDIO_REQUEST_GET_MIN: - (*data)[0] = 0x00; /* -2560/256 dB */ - (*data)[1] = 0xdb; + (*data)[0] = 0x00; /* -100 dB */ + (*data)[1] = 0x9c; *len = 2; break; case AUDIO_REQUEST_GET_MAX: @@ -165,7 +164,7 @@ static int audio_class_interface_request_handler(uint8_t busid, struct usb_setup *len = 2; break; case AUDIO_REQUEST_GET_RES: - (*data)[0] = 0x00; /* -256/256 dB */ + (*data)[0] = 0x00; /* 1 dB */ (*data)[1] = 0x01; *len = 2; break; @@ -178,22 +177,31 @@ static int audio_class_interface_request_handler(uint8_t busid, struct usb_setup case AUDIO_REQUEST_CUR: if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { volume_db = usbd_audio_get_volume(busid, ep, ch); - volume = volume_db; + if (volume_db >= 0) { + volume = volume_db * 256; + } else { + volume = volume_db * 256 + 0x10000; + } + USB_LOG_DBG("Get ep:0x%02x ch:%d vol_hex:0x%04x, vol_db:%d dB\r\n", ep, ch, volume, volume_db); memcpy(*data, &volume, 2); *len = 2; } else { memcpy(&volume, *data, *len); - volume_db = volume; - USB_LOG_DBG("Set ep:0x%02x ch:%d volume:0x%02x\r\n", ep, ch, volume); + if (volume < 0x8000) { + volume_db = volume / 256; + } else { + volume_db = (volume - 0x10000) / 256; + } + USB_LOG_DBG("Set ep:0x%02x ch:%d vol_hex:0x%04x, vol_db:%d dB\r\n", ep, ch, volume, volume_db); usbd_audio_set_volume(busid, ep, ch, volume_db); } break; case AUDIO_REQUEST_RANGE: if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { *((uint16_t *)(*data + 0)) = 1; - *((uint16_t *)(*data + 2)) = 0; - *((uint16_t *)(*data + 4)) = 100; - *((uint16_t *)(*data + 6)) = 1; + *((uint16_t *)(*data + 2)) = 0x9c00; /* MIN -100 dB */ + *((uint16_t *)(*data + 4)) = 0x0000; /* MAX 0 dB */ + *((uint16_t *)(*data + 6)) = 0x100; /* RES 1 dB */ *len = 8; } else { } @@ -287,7 +295,7 @@ static void audio_notify_handler(uint8_t busid, uint8_t event, void *arg) } } -struct usbd_interface *usbd_audio_init_intf(uint8_t busid, +struct usbd_interface *usbd_audio_init_intf(uint8_t busid, struct usbd_interface *intf, uint16_t uac_version, struct audio_entity_info *table, @@ -312,33 +320,58 @@ struct usbd_interface *usbd_audio_init_intf(uint8_t busid, return intf; } -__WEAK void usbd_audio_set_volume(uint8_t busid, uint8_t ep, uint8_t ch, int volume) +__WEAK void usbd_audio_set_volume(uint8_t busid, uint8_t ep, uint8_t ch, int volume_db) { + (void)busid; + (void)ep; + (void)ch; + (void)volume_db; } __WEAK int usbd_audio_get_volume(uint8_t busid, uint8_t ep, uint8_t ch) { + (void)busid; + (void)ep; + (void)ch; + return 0; } __WEAK void usbd_audio_set_mute(uint8_t busid, uint8_t ep, uint8_t ch, bool mute) { + (void)busid; + (void)ep; + (void)ch; + (void)mute; } __WEAK bool usbd_audio_get_mute(uint8_t busid, uint8_t ep, uint8_t ch) { + (void)busid; + (void)ep; + (void)ch; + return 0; } __WEAK void usbd_audio_set_sampling_freq(uint8_t busid, uint8_t ep, uint32_t sampling_freq) { + (void)busid; + (void)ep; + (void)sampling_freq; } __WEAK uint32_t usbd_audio_get_sampling_freq(uint8_t busid, uint8_t ep) { + (void)busid; + (void)ep; + return 0; } __WEAK void usbd_audio_get_sampling_freq_table(uint8_t busid, uint8_t ep, uint8_t **sampling_freq_table) { + (void)busid; + (void)ep; + (void)sampling_freq_table; } diff --git a/rt-thread/components/drivers/usb/cherryusb/class/audio/usbd_audio.h b/rt-thread/components/drivers/usb/cherryusb/class/audio/usbd_audio.h index 442405a..75a0b17 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/audio/usbd_audio.h +++ b/rt-thread/components/drivers/usb/cherryusb/class/audio/usbd_audio.h @@ -27,7 +27,7 @@ struct usbd_interface *usbd_audio_init_intf(uint8_t busid, struct usbd_interface void usbd_audio_open(uint8_t busid, uint8_t intf); void usbd_audio_close(uint8_t busid, uint8_t intf); -void usbd_audio_set_volume(uint8_t busid, uint8_t ep, uint8_t ch, int volume); +void usbd_audio_set_volume(uint8_t busid, uint8_t ep, uint8_t ch, int volume_db); int usbd_audio_get_volume(uint8_t busid, uint8_t ep, uint8_t ch); void usbd_audio_set_mute(uint8_t busid, uint8_t ep, uint8_t ch, bool mute); bool usbd_audio_get_mute(uint8_t busid, uint8_t ep, uint8_t ch); diff --git a/rt-thread/components/drivers/usb/cherryusb/class/audio/usbh_audio.c b/rt-thread/components/drivers/usb/cherryusb/class/audio/usbh_audio.c index 223c340..6d8b455 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/audio/usbh_audio.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/audio/usbh_audio.c @@ -21,10 +21,6 @@ #define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ #define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ -#ifndef CONFIG_USBHOST_MAX_AUDIO_CLASS -#define CONFIG_USBHOST_MAX_AUDIO_CLASS 4 -#endif - USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_audio_buf[128]; static struct usbh_audio g_audio_class[CONFIG_USBHOST_MAX_AUDIO_CLASS]; @@ -32,11 +28,11 @@ static uint32_t g_devinuse = 0; static struct usbh_audio *usbh_audio_class_alloc(void) { - int devno; + uint8_t devno; for (devno = 0; devno < CONFIG_USBHOST_MAX_AUDIO_CLASS; devno++) { - if ((g_devinuse & (1 << devno)) == 0) { - g_devinuse |= (1 << devno); + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); memset(&g_audio_class[devno], 0, sizeof(struct usbh_audio)); g_audio_class[devno].minor = devno; return &g_audio_class[devno]; @@ -47,15 +43,15 @@ static struct usbh_audio *usbh_audio_class_alloc(void) static void usbh_audio_class_free(struct usbh_audio *audio_class) { - int devno = audio_class->minor; + uint8_t devno = audio_class->minor; - if (devno >= 0 && devno < 32) { - g_devinuse &= ~(1 << devno); + if (devno < 32) { + g_devinuse &= ~(1U << devno); } memset(audio_class, 0, sizeof(struct usbh_audio)); } -int usbh_audio_open(struct usbh_audio *audio_class, const char *name, uint32_t samp_freq) +int usbh_audio_open(struct usbh_audio *audio_class, const char *name, uint32_t samp_freq, uint8_t bitresolution) { struct usb_setup_packet *setup; struct usb_endpoint_descriptor *ep_desc; @@ -74,20 +70,24 @@ int usbh_audio_open(struct usbh_audio *audio_class, const char *name, uint32_t s return 0; } - for (uint8_t i = 0; i < audio_class->module_num; i++) { - if (strcmp(name, audio_class->module[i].name) == 0) { - for (uint8_t j = 0; j < audio_class->num_of_intf_altsettings; j++) { - for (uint8_t k = 0; k < audio_class->module[i].altsetting[j].sampfreq_num; k++) { - if (audio_class->module[i].altsetting[j].sampfreq[k] == samp_freq) { - intf = audio_class->module[i].data_intf; - altsetting = j; - goto freq_found; + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + if (strcmp(name, audio_class->as_msg_table[i].stream_name) == 0) { + intf = audio_class->as_msg_table[i].stream_intf; + for (uint8_t j = 1; j < audio_class->as_msg_table[i].num_of_altsetting; j++) { + if (audio_class->as_msg_table[i].as_format[j].bBitResolution == bitresolution) { + for (uint8_t k = 0; k < audio_class->as_msg_table[i].as_format[j].bSamFreqType; k++) { + uint32_t freq = 0; + + memcpy(&freq, &audio_class->as_msg_table[i].as_format[j].tSamFreq[3 * k], 3); + if (freq == samp_freq) { + altsetting = j; + goto freq_found; + } } } } } } - return -USB_ERR_NODEV; freq_found: @@ -105,16 +105,18 @@ freq_found: ep_desc = &audio_class->hport->config.intf[intf].altsetting[altsetting].ep[0].ep_desc; - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_ENDPOINT; - setup->bRequest = AUDIO_REQUEST_SET_CUR; - setup->wValue = (AUDIO_EP_CONTROL_SAMPLING_FEQ << 8) | 0x00; - setup->wIndex = ep_desc->bEndpointAddress; - setup->wLength = 3; + if (audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].ep_attr & AUDIO_EP_CONTROL_SAMPLING_FEQ) { + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_ENDPOINT; + setup->bRequest = AUDIO_REQUEST_SET_CUR; + setup->wValue = (AUDIO_EP_CONTROL_SAMPLING_FEQ << 8) | 0x00; + setup->wIndex = ep_desc->bEndpointAddress; + setup->wLength = 3; - memcpy(g_audio_buf, &samp_freq, 3); - ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); - if (ret < 0) { - return ret; + memcpy(g_audio_buf, &samp_freq, 3); + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } } mult = (ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT; @@ -127,7 +129,7 @@ freq_found: USBH_EP_INIT(audio_class->isoout, ep_desc); } - USB_LOG_INFO("Open audio module :%s, altsetting: %u\r\n", name, altsetting); + USB_LOG_INFO("Open audio stream :%s, altsetting: %u\r\n", name, altsetting); audio_class->is_opened = true; return ret; } @@ -145,9 +147,9 @@ int usbh_audio_close(struct usbh_audio *audio_class, const char *name) } setup = audio_class->hport->setup; - for (size_t i = 0; i < audio_class->module_num; i++) { - if (strcmp(name, audio_class->module[i].name) == 0) { - intf = audio_class->module[i].data_intf; + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + if (strcmp(name, audio_class->as_msg_table[i].stream_name) == 0) { + intf = audio_class->as_msg_table[i].stream_intf; } } @@ -155,7 +157,17 @@ int usbh_audio_close(struct usbh_audio *audio_class, const char *name) return -USB_ERR_NODEV; } - USB_LOG_INFO("Close audio module :%s\r\n", name); + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_SET_INTERFACE; + setup->wValue = 0; + setup->wIndex = intf; + setup->wLength = 0; + + ret = usbh_control_transfer(audio_class->hport, setup, NULL); + if (ret < 0) { + return ret; + } + USB_LOG_INFO("Close audio stream :%s\r\n", name); audio_class->is_opened = false; ep_desc = &audio_class->hport->config.intf[intf].altsetting[altsetting].ep[0].ep_desc; @@ -169,52 +181,128 @@ int usbh_audio_close(struct usbh_audio *audio_class, const char *name) } } - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = USB_REQUEST_SET_INTERFACE; - setup->wValue = 0; - setup->wIndex = intf; - setup->wLength = 0; - - ret = usbh_control_transfer(audio_class->hport, setup, NULL); - return ret; } -int usbh_audio_set_volume(struct usbh_audio *audio_class, const char *name, uint8_t ch, uint8_t volume) +int usbh_audio_set_volume(struct usbh_audio *audio_class, const char *name, uint8_t ch, int volume_db) { struct usb_setup_packet *setup; int ret; - uint8_t intf = 0xff; uint8_t feature_id = 0xff; + uint8_t intf; uint16_t volume_hex; + int volume_min_db; + int volume_max_db; if (!audio_class || !audio_class->hport) { return -USB_ERR_INVAL; } + + if ((volume_db > 127) || (volume_db < -127)) { + return -USB_ERR_INVAL; + } + setup = audio_class->hport->setup; - for (size_t i = 0; i < audio_class->module_num; i++) { - if (strcmp(name, audio_class->module[i].name) == 0) { - intf = audio_class->ctrl_intf; - feature_id = audio_class->module[i].feature_unit_id; + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + if (strcmp(name, audio_class->as_msg_table[i].stream_name) == 0) { + feature_id = audio_class->as_msg_table[i].feature_terminal_id; + intf = audio_class->as_msg_table[i].stream_intf; } } - if (intf == 0xff) { + if (feature_id == 0xff) { return -USB_ERR_NODEV; } + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = AUDIO_REQUEST_GET_CUR; + setup->wValue = (AUDIO_FU_CONTROL_VOLUME << 8) | ch; + setup->wIndex = (feature_id << 8) | audio_class->ctrl_intf; + setup->wLength = 2; + + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } + + memcpy(&audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_cur, g_audio_buf, 2); + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = AUDIO_REQUEST_GET_MIN; + setup->wValue = (AUDIO_FU_CONTROL_VOLUME << 8) | ch; + setup->wIndex = (feature_id << 8) | audio_class->ctrl_intf; + setup->wLength = 2; + + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } + + memcpy(&audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_min, g_audio_buf, 2); + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = AUDIO_REQUEST_GET_MAX; + setup->wValue = (AUDIO_FU_CONTROL_VOLUME << 8) | ch; + setup->wIndex = (feature_id << 8) | audio_class->ctrl_intf; + setup->wLength = 2; + + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } + memcpy(&audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_max, g_audio_buf, 2); + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = AUDIO_REQUEST_GET_RES; + setup->wValue = (AUDIO_FU_CONTROL_VOLUME << 8) | ch; + setup->wIndex = (feature_id << 8) | audio_class->ctrl_intf; + setup->wLength = 2; + + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } + memcpy(&audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_res, g_audio_buf, 2); + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; setup->bRequest = AUDIO_REQUEST_SET_CUR; setup->wValue = (AUDIO_FU_CONTROL_VOLUME << 8) | ch; - setup->wIndex = (feature_id << 8) | intf; + setup->wIndex = (feature_id << 8) | audio_class->ctrl_intf; setup->wLength = 2; - volume_hex = -0xDB00 / 100 * volume + 0xdb00; + if (audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_min < 0x8000) { + volume_min_db = audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_min / 256; + } else { + volume_min_db = (audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_min - 0x10000) / 256; + } + + if (audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_max < 0x8000) { + volume_max_db = audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_max / 256; + } else { + volume_max_db = (audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_max - 0x10000) / 256; + } + + USB_LOG_INFO("Get ch:%d dB range: %d dB ~ %d dB\r\n", volume_min_db, volume_max_db); + + if (volume_db >= 0) { + volume_hex = volume_db * 256; + if (volume_hex > audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_max) { + return -USB_ERR_RANGE; + } + } else { + volume_hex = volume_db * 256 + 0x10000; + if (volume_hex < audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_min) { + return -USB_ERR_RANGE; + } + } memcpy(g_audio_buf, &volume_hex, 2); - ret = usbh_control_transfer(audio_class->hport, setup, NULL); - + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } + audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_cur = volume_hex; return ret; } @@ -222,34 +310,37 @@ int usbh_audio_set_mute(struct usbh_audio *audio_class, const char *name, uint8_ { struct usb_setup_packet *setup; int ret; - uint8_t intf = 0xff; uint8_t feature_id = 0xff; + uint8_t intf = 0xff; if (!audio_class || !audio_class->hport) { return -USB_ERR_INVAL; } setup = audio_class->hport->setup; - for (size_t i = 0; i < audio_class->module_num; i++) { - if (strcmp(name, audio_class->module[i].name) == 0) { - intf = audio_class->ctrl_intf; - feature_id = audio_class->module[i].feature_unit_id; + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + if (strcmp(name, audio_class->as_msg_table[i].stream_name) == 0) { + feature_id = audio_class->as_msg_table[i].feature_terminal_id; + intf = audio_class->as_msg_table[i].stream_intf; } } - if (intf == 0xff) { + if (feature_id == 0xff) { return -USB_ERR_NODEV; } setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; setup->bRequest = AUDIO_REQUEST_SET_CUR; setup->wValue = (AUDIO_FU_CONTROL_MUTE << 8) | ch; - setup->wIndex = (feature_id << 8) | intf; + setup->wIndex = (feature_id << 8) | audio_class->ctrl_intf; setup->wLength = 1; memcpy(g_audio_buf, &mute, 1); ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); - + if (ret < 0) { + return ret; + } + audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].mute = mute; return ret; } @@ -257,26 +348,28 @@ void usbh_audio_list_module(struct usbh_audio *audio_class) { USB_LOG_INFO("============= Audio module information ===================\r\n"); USB_LOG_RAW("bcdADC :%04x\r\n", audio_class->bcdADC); - USB_LOG_RAW("Num of modules :%u\r\n", audio_class->module_num); - USB_LOG_RAW("Num of altsettings:%u\r\n", audio_class->num_of_intf_altsettings); + USB_LOG_RAW("Num of audio stream :%u\r\n", audio_class->stream_intf_num); - for (uint8_t i = 0; i < audio_class->module_num; i++) { - USB_LOG_RAW(" module name :%s\r\n", audio_class->module[i].name); - USB_LOG_RAW(" module feature unit id :%d\r\n", audio_class->module[i].feature_unit_id); + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + USB_LOG_RAW("\tstream name :%s\r\n", audio_class->as_msg_table[i].stream_name); + USB_LOG_RAW("\tstream intf :%u\r\n", audio_class->as_msg_table[i].stream_intf); + USB_LOG_RAW("\tNum of altsetting :%u\r\n", audio_class->as_msg_table[i].num_of_altsetting); - for (uint8_t j = 0; j < audio_class->num_of_intf_altsettings; j++) { + for (uint8_t j = 0; j < audio_class->as_msg_table[i].num_of_altsetting; j++) { if (j == 0) { - USB_LOG_RAW(" Ingore altsetting 0\r\n"); + USB_LOG_RAW("\t\tIngore altsetting 0\r\n"); continue; } - USB_LOG_RAW(" Altsetting %u\r\n", j); - USB_LOG_RAW(" module channels :%u\r\n", audio_class->module[i].altsetting[j].channels); - //USB_LOG_RAW(" module format_type :%u\r\n",audio_class->module[i].altsetting[j].format_type); - USB_LOG_RAW(" module bitresolution :%u\r\n", audio_class->module[i].altsetting[j].bitresolution); - USB_LOG_RAW(" module sampfreq num :%u\r\n", audio_class->module[i].altsetting[j].sampfreq_num); + USB_LOG_RAW("\t\tAltsetting :%u\r\n", j); + USB_LOG_RAW("\t\t\tbNrChannels :%u\r\n", audio_class->as_msg_table[i].as_format[j].bNrChannels); + USB_LOG_RAW("\t\t\tbBitResolution :%u\r\n", audio_class->as_msg_table[i].as_format[j].bBitResolution); + USB_LOG_RAW("\t\t\tbSamFreqType :%u\r\n", audio_class->as_msg_table[i].as_format[j].bSamFreqType); - for (uint8_t k = 0; k < audio_class->module[i].altsetting[j].sampfreq_num; k++) { - USB_LOG_RAW(" module sampfreq :%d hz\r\n", audio_class->module[i].altsetting[j].sampfreq[k]); + for (uint8_t k = 0; k < audio_class->as_msg_table[i].as_format[j].bSamFreqType; k++) { + uint32_t freq = 0; + + memcpy(&freq, &audio_class->as_msg_table[i].as_format[j].tSamFreq[3 * k], 3); + USB_LOG_RAW("\t\t\t\tSampleFreq :%u\r\n", freq); } } } @@ -287,14 +380,14 @@ void usbh_audio_list_module(struct usbh_audio *audio_class) static int usbh_audio_ctrl_connect(struct usbh_hubport *hport, uint8_t intf) { int ret; - uint8_t cur_iface = 0xff; - uint8_t cur_iface_count = 0xff; - uint8_t cur_alt_setting = 0xff; + uint8_t cur_iface = 0; + uint8_t cur_iface_count = 0; + uint8_t cur_alt_setting = 0; uint8_t input_offset = 0; uint8_t output_offset = 0; uint8_t feature_unit_offset = 0; - uint8_t format_offset = 0; uint8_t *p; + struct usbh_audio_ac_msg ac_msg_table[CONFIG_USBHOST_AUDIO_MAX_STREAMS]; struct usbh_audio *audio_class = usbh_audio_class_alloc(); if (audio_class == NULL) { @@ -304,8 +397,6 @@ static int usbh_audio_ctrl_connect(struct usbh_hubport *hport, uint8_t intf) audio_class->hport = hport; audio_class->ctrl_intf = intf; - audio_class->num_of_intf_altsettings = hport->config.intf[intf + 1].altsetting_num; - hport->config.intf[intf].priv = audio_class; p = hport->raw_config_desc; @@ -331,72 +422,49 @@ static int usbh_audio_ctrl_connect(struct usbh_hubport *hport, uint8_t intf) case AUDIO_CONTROL_INPUT_TERMINAL: { struct audio_cs_if_ac_input_terminal_descriptor *desc = (struct audio_cs_if_ac_input_terminal_descriptor *)p; - audio_class->module[input_offset].input_terminal_id = desc->bTerminalID; - audio_class->module[input_offset].input_terminal_type = desc->wTerminalType; - audio_class->module[input_offset].input_channel_config = desc->wChannelConfig; - - if (desc->wTerminalType == AUDIO_TERMINAL_STREAMING) { - audio_class->module[input_offset].terminal_link_id = desc->bTerminalID; - } - if (desc->wTerminalType == AUDIO_INTERM_MIC) { - audio_class->module[input_offset].name = "mic"; - } + memcpy(&ac_msg_table[input_offset].ac_input, desc, sizeof(struct audio_cs_if_ac_input_terminal_descriptor)); input_offset++; } break; - break; case AUDIO_CONTROL_OUTPUT_TERMINAL: { struct audio_cs_if_ac_output_terminal_descriptor *desc = (struct audio_cs_if_ac_output_terminal_descriptor *)p; - audio_class->module[output_offset].output_terminal_id = desc->bTerminalID; - audio_class->module[output_offset].output_terminal_type = desc->wTerminalType; - if (desc->wTerminalType == AUDIO_TERMINAL_STREAMING) { - audio_class->module[output_offset].terminal_link_id = desc->bTerminalID; - } - if (desc->wTerminalType == AUDIO_OUTTERM_SPEAKER) { - audio_class->module[output_offset].name = "speaker"; - } + + memcpy(&ac_msg_table[output_offset].ac_output, desc, sizeof(struct audio_cs_if_ac_output_terminal_descriptor)); output_offset++; } break; case AUDIO_CONTROL_FEATURE_UNIT: { struct audio_cs_if_ac_feature_unit_descriptor *desc = (struct audio_cs_if_ac_feature_unit_descriptor *)p; - audio_class->module[feature_unit_offset].feature_unit_id = desc->bUnitID; - audio_class->module[feature_unit_offset].feature_unit_controlsize = desc->bControlSize; - for (uint8_t j = 0; j < desc->bControlSize; j++) { - audio_class->module[feature_unit_offset].feature_unit_controls[j] = p[6 + j]; - } + memcpy(&ac_msg_table[feature_unit_offset].ac_feature_unit, desc, desc->bLength); feature_unit_offset++; } break; - case AUDIO_CONTROL_PROCESSING_UNIT: + default: + USB_LOG_ERR("Do not support %02x subtype\r\n", p[DESC_bDescriptorSubType]); + return -USB_ERR_NOTSUPP; + } + } else if ((cur_iface > audio_class->ctrl_intf) && (cur_iface < (audio_class->ctrl_intf + cur_iface_count))) { + switch (p[DESC_bDescriptorSubType]) { + case AUDIO_STREAMING_GENERAL: { + struct audio_cs_if_as_general_descriptor *desc = (struct audio_cs_if_as_general_descriptor *)p; - break; + /* all altsetting have the same general */ + audio_class->as_msg_table[cur_iface - audio_class->ctrl_intf - 1].stream_intf = cur_iface; + memcpy(&audio_class->as_msg_table[cur_iface - audio_class->ctrl_intf - 1].as_general, desc, sizeof(struct audio_cs_if_as_general_descriptor)); + } break; + case AUDIO_STREAMING_FORMAT_TYPE: { + struct audio_cs_if_as_format_type_descriptor *desc = (struct audio_cs_if_as_format_type_descriptor *)p; + audio_class->as_msg_table[cur_iface - audio_class->ctrl_intf - 1].num_of_altsetting = (cur_alt_setting + 1); + memcpy(&audio_class->as_msg_table[cur_iface - audio_class->ctrl_intf - 1].as_format[cur_alt_setting], desc, desc->bLength); + } break; default: break; } - } else if ((cur_iface < (audio_class->ctrl_intf + cur_iface_count)) && (cur_iface > audio_class->ctrl_intf)) { - switch (p[DESC_bDescriptorSubType]) { - case AUDIO_STREAMING_GENERAL: - - break; - case AUDIO_STREAMING_FORMAT_TYPE: { - struct audio_cs_if_as_format_type_descriptor *desc = (struct audio_cs_if_as_format_type_descriptor *)p; - - audio_class->module[format_offset].data_intf = cur_iface; - audio_class->module[format_offset].altsetting[cur_alt_setting].channels = desc->bNrChannels; - audio_class->module[format_offset].altsetting[cur_alt_setting].format_type = desc->bFormatType; - audio_class->module[format_offset].altsetting[cur_alt_setting].bitresolution = desc->bBitResolution; - audio_class->module[format_offset].altsetting[cur_alt_setting].sampfreq_num = desc->bSamFreqType; - - for (uint8_t j = 0; j < desc->bSamFreqType; j++) { - audio_class->module[format_offset].altsetting[cur_alt_setting].sampfreq[j] = (uint32_t)(p[10 + j * 3] << 16) | - (uint32_t)(p[9 + j * 3] << 8) | - (uint32_t)(p[8 + j * 3] << 0); - } - if (cur_alt_setting == (hport->config.intf[intf + 1].altsetting_num - 1)) { - format_offset++; - } - } break; - default: - break; + } + break; + case AUDIO_ENDPOINT_DESCRIPTOR_TYPE: + if ((cur_iface > audio_class->ctrl_intf) && (cur_iface < (audio_class->ctrl_intf + cur_iface_count))) { + if (p[DESC_bDescriptorSubType] == AUDIO_ENDPOINT_GENERAL) { + struct audio_cs_ep_ep_general_descriptor *desc = (struct audio_cs_ep_ep_general_descriptor *)p; + audio_class->as_msg_table[cur_iface - audio_class->ctrl_intf - 1].ep_attr = desc->bmAttributes; } } break; @@ -407,16 +475,98 @@ static int usbh_audio_ctrl_connect(struct usbh_hubport *hport, uint8_t intf) p += p[DESC_bLength]; } - if ((input_offset != output_offset) && (input_offset != feature_unit_offset) && (input_offset != format_offset)) { + if ((input_offset != output_offset) && (input_offset != feature_unit_offset)) { + USB_LOG_ERR("Audio control descriptor is invalid\r\n"); return -USB_ERR_INVAL; } - audio_class->module_num = input_offset; + if (cur_iface_count == 0xff) { + USB_LOG_ERR("Audio descriptor must have iad descriptor\r\n"); + return -USB_ERR_INVAL; + } - for (size_t i = 0; i < audio_class->module_num; i++) { - ret = usbh_audio_close(audio_class, audio_class->module[i].name); + audio_class->stream_intf_num = input_offset; + + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + /* Search 0x0101 in input or output desc */ + for (uint8_t streamidx = 0; streamidx < audio_class->stream_intf_num; streamidx++) { + if (audio_class->as_msg_table[i].as_general.bTerminalLink == ac_msg_table[streamidx].ac_input.bTerminalID) { + /* INPUT --> FEATURE UNIT --> OUTPUT */ + audio_class->as_msg_table[i].input_terminal_id = ac_msg_table[streamidx].ac_input.bTerminalID; + + /* Search input terminal id in feature desc */ + for (uint8_t featureidx = 0; featureidx < audio_class->stream_intf_num; featureidx++) { + if (ac_msg_table[streamidx].ac_input.bTerminalID == ac_msg_table[featureidx].ac_feature_unit.bSourceID) { + audio_class->as_msg_table[i].feature_terminal_id = ac_msg_table[featureidx].ac_feature_unit.bUnitID; + + /* Search feature unit id in output desc */ + for (uint8_t outputid = 0; outputid < audio_class->stream_intf_num; outputid++) { + if (ac_msg_table[featureidx].ac_feature_unit.bUnitID == ac_msg_table[outputid].ac_output.bSourceID) { + audio_class->as_msg_table[i].output_terminal_id = ac_msg_table[outputid].ac_output.bTerminalID; + + switch (ac_msg_table[outputid].ac_output.wTerminalType) { + case AUDIO_OUTTERM_SPEAKER: + audio_class->as_msg_table[i].stream_name = "speaker"; + break; + case AUDIO_OUTTERM_HEADPHONES: + audio_class->as_msg_table[i].stream_name = "headphoens"; + break; + case AUDIO_OUTTERM_HEADDISPLAY: + audio_class->as_msg_table[i].stream_name = "headdisplay"; + break; + default: + audio_class->as_msg_table[i].stream_name = "unknown"; + break; + } + break; + } + } + break; + } + } + } else if (audio_class->as_msg_table[i].as_general.bTerminalLink == ac_msg_table[streamidx].ac_output.bTerminalID) { + /* OUTPUT --> FEATURE UNIT --> INPUT */ + audio_class->as_msg_table[i].output_terminal_id = ac_msg_table[streamidx].ac_output.bTerminalID; + + /* Search output terminal id in feature desc */ + for (uint8_t featureidx = 0; featureidx < audio_class->stream_intf_num; featureidx++) { + if (ac_msg_table[streamidx].ac_output.bSourceID == ac_msg_table[featureidx].ac_feature_unit.bUnitID) { + audio_class->as_msg_table[i].feature_terminal_id = ac_msg_table[featureidx].ac_feature_unit.bUnitID; + + /* Search feature unit id in input desc */ + for (uint8_t inputid = 0; inputid < audio_class->stream_intf_num; inputid++) { + if (ac_msg_table[featureidx].ac_feature_unit.bSourceID == ac_msg_table[inputid].ac_input.bTerminalID) { + audio_class->as_msg_table[i].input_terminal_id = ac_msg_table[inputid].ac_input.bTerminalID; + + switch (ac_msg_table[inputid].ac_input.wTerminalType) { + case AUDIO_INTERM_MIC: + audio_class->as_msg_table[i].stream_name = "mic"; + break; + default: + audio_class->as_msg_table[i].stream_name = "unknown"; + break; + } + break; + } + } + break; + } + } + } + } + } + + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + if (audio_class->as_msg_table[i].stream_name == NULL) { + USB_LOG_ERR("Audio stream search fail\r\n"); + return -USB_ERR_NODEV; + } + } + + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + ret = usbh_audio_close(audio_class, audio_class->as_msg_table[i].stream_name); if (ret < 0) { - USB_LOG_ERR("Fail to close audio module :%s\r\n", audio_class->module[i].name); + USB_LOG_ERR("Fail to close audio stream :%s\r\n", audio_class->as_msg_table[i].stream_name); return ret; } } @@ -456,20 +606,26 @@ static int usbh_audio_ctrl_disconnect(struct usbh_hubport *hport, uint8_t intf) static int usbh_audio_data_connect(struct usbh_hubport *hport, uint8_t intf) { + (void)hport; + (void)intf; return 0; } static int usbh_audio_data_disconnect(struct usbh_hubport *hport, uint8_t intf) { + (void)hport; + (void)intf; return 0; } __WEAK void usbh_audio_run(struct usbh_audio *audio_class) { + (void)audio_class; } __WEAK void usbh_audio_stop(struct usbh_audio *audio_class) { + (void)audio_class; } const struct usbh_class_driver audio_ctrl_class_driver = { @@ -486,18 +642,18 @@ const struct usbh_class_driver audio_streaming_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info audio_ctrl_intf_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS, - .class = USB_DEVICE_CLASS_AUDIO, - .subclass = AUDIO_SUBCLASS_AUDIOCONTROL, - .protocol = 0x00, + .bInterfaceClass = USB_DEVICE_CLASS_AUDIO, + .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOCONTROL, + .bInterfaceProtocol = 0x00, .id_table = NULL, .class_driver = &audio_ctrl_class_driver }; CLASS_INFO_DEFINE const struct usbh_class_info audio_streaming_intf_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS, - .class = USB_DEVICE_CLASS_AUDIO, - .subclass = AUDIO_SUBCLASS_AUDIOSTREAMING, - .protocol = 0x00, + .bInterfaceClass = USB_DEVICE_CLASS_AUDIO, + .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = 0x00, .id_table = NULL, .class_driver = &audio_streaming_class_driver }; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/audio/usbh_audio.h b/rt-thread/components/drivers/usb/cherryusb/class/audio/usbh_audio.h index 038a8f7..2e583ac 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/audio/usbh_audio.h +++ b/rt-thread/components/drivers/usb/cherryusb/class/audio/usbh_audio.h @@ -8,34 +8,31 @@ #include "usb_audio.h" -struct usbh_audio_format_type { - uint8_t channels; - uint8_t format_type; - uint8_t bitresolution; - uint8_t sampfreq_num; - uint32_t sampfreq[3]; +#ifndef CONFIG_USBHOST_AUDIO_MAX_STREAMS +#define CONFIG_USBHOST_AUDIO_MAX_STREAMS 3 +#endif + +struct usbh_audio_ac_msg { + struct audio_cs_if_ac_input_terminal_descriptor ac_input; + struct audio_cs_if_ac_feature_unit_descriptor ac_feature_unit; + struct audio_cs_if_ac_output_terminal_descriptor ac_output; }; -/** - * bSourceID in feature_unit = input_terminal_id - * bSourceID in output_terminal = feature_unit_id - * terminal_link_id = input_terminal_id or output_terminal_id (if input_terminal_type or output_terminal_type is 0x0101) - * - * -*/ -struct usbh_audio_module { - const char *name; - uint8_t data_intf; +struct usbh_audio_as_msg { + const char *stream_name; + uint8_t stream_intf; uint8_t input_terminal_id; - uint16_t input_terminal_type; - uint16_t input_channel_config; + uint8_t feature_terminal_id; uint8_t output_terminal_id; - uint16_t output_terminal_type; - uint8_t feature_unit_id; - uint8_t feature_unit_controlsize; - uint8_t feature_unit_controls[8]; - uint8_t terminal_link_id; - struct usbh_audio_format_type altsetting[CONFIG_USBHOST_MAX_INTF_ALTSETTINGS]; + uint8_t ep_attr; + uint8_t num_of_altsetting; + uint16_t volume_min; + uint16_t volume_max; + uint16_t volume_res; + uint16_t volume_cur; + bool mute; + struct audio_cs_if_as_general_descriptor as_general; + struct audio_cs_if_as_format_type_descriptor as_format[CONFIG_USBHOST_MAX_INTF_ALTSETTINGS]; }; struct usbh_audio { @@ -50,9 +47,8 @@ struct usbh_audio { bool is_opened; uint16_t bcdADC; uint8_t bInCollection; - uint8_t num_of_intf_altsettings; - struct usbh_audio_module module[2]; - uint8_t module_num; + uint8_t stream_intf_num; + struct usbh_audio_as_msg as_msg_table[CONFIG_USBHOST_AUDIO_MAX_STREAMS]; void *user_data; }; @@ -61,9 +57,9 @@ struct usbh_audio { extern "C" { #endif -int usbh_audio_open(struct usbh_audio *audio_class, const char *name, uint32_t samp_freq); +int usbh_audio_open(struct usbh_audio *audio_class, const char *name, uint32_t samp_freq, uint8_t bitresolution); int usbh_audio_close(struct usbh_audio *audio_class, const char *name); -int usbh_audio_set_volume(struct usbh_audio *audio_class, const char *name, uint8_t ch, uint8_t volume); +int usbh_audio_set_volume(struct usbh_audio *audio_class, const char *name, uint8_t ch, int volume_db); int usbh_audio_set_mute(struct usbh_audio *audio_class, const char *name, uint8_t ch, bool mute); void usbh_audio_run(struct usbh_audio *audio_class); diff --git a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usb_cdc.h b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usb_cdc.h index 2bf0a17..d1546ee 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usb_cdc.h +++ b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usb_cdc.h @@ -421,7 +421,7 @@ struct cdc_ncm_ndp16 { 0x02, /* bInterfaceCount */ \ USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ CDC_ABSTRACT_CONTROL_MODEL, /* bFunctionSubClass */ \ - CDC_COMMON_PROTOCOL_AT_COMMANDS, /* bFunctionProtocol */ \ + CDC_COMMON_PROTOCOL_NONE, /* bFunctionProtocol */ \ 0x00, /* iFunction */ \ 0x09, /* bLength */ \ USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ @@ -430,7 +430,7 @@ struct cdc_ncm_ndp16 { 0x01, /* bNumEndpoints */ \ USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass */ \ - CDC_COMMON_PROTOCOL_AT_COMMANDS, /* bInterfaceProtocol */ \ + CDC_COMMON_PROTOCOL_NONE, /* bInterfaceProtocol */ \ str_idx, /* iInterface */ \ 0x05, /* bLength */ \ CDC_CS_INTERFACE, /* bDescriptorType */ \ @@ -489,8 +489,8 @@ struct cdc_ncm_ndp16 { bFirstInterface, /* bFirstInterface */ \ 0x02, /* bInterfaceCount */ \ USB_DEVICE_CLASS_WIRELESS, /* bFunctionClass */ \ - CDC_DIRECT_LINE_CONTROL_MODEL, /* bFunctionSubClass */ \ - CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO, /* bFunctionProtocol */ \ + 0x01, /* bFunctionSubClass */ \ + 0x03, /* bFunctionProtocol */ \ 0x00, /* iFunction */ \ 0x09, /* bLength */ \ USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ @@ -498,8 +498,8 @@ struct cdc_ncm_ndp16 { 0x00, /* bAlternateSetting */ \ 0x01, /* bNumEndpoints */ \ USB_DEVICE_CLASS_WIRELESS, /* bInterfaceClass */ \ - CDC_DIRECT_LINE_CONTROL_MODEL, /* bInterfaceSubClass */ \ - CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO, /* bInterfaceProtocol */ \ + 0x01, /* bInterfaceSubClass */ \ + 0x03, /* bInterfaceProtocol */ \ str_idx, /* iInterface */ \ 0x05, /* bLength */ \ CDC_CS_INTERFACE, /* bDescriptorType */ \ @@ -524,7 +524,7 @@ struct cdc_ncm_ndp16 { int_ep, /* bEndpointAddress */ \ 0x03, /* bmAttributes */ \ 0x08, 0x00, /* wMaxPacketSize */ \ - 0x10, /* bInterval */ \ + 0x05, /* bInterval */ \ 0x09, /* bLength */ \ USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ @@ -596,7 +596,7 @@ eth_statistics, wMaxSegmentSize, wNumberMCFilters, bNumberPowerFilters, str_idx) int_ep, /* bEndpointAddress */ \ 0x03, /* bmAttributes */ \ 0x10, 0x00, /* wMaxPacketSize */ \ - 0x10, /* bInterval */ \ + 0x05, /* bInterval */ \ 0x09, /* bLength */ \ USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ diff --git a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc.h b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc.h index ebf3d02..2cf3df1 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc.h +++ b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc.h @@ -1,29 +1,13 @@ /* - * Copyright (c) 2022, sakumisu + * Copyright (c) 2024, sakumisu * * SPDX-License-Identifier: Apache-2.0 */ #ifndef USBD_CDC_H #define USBD_CDC_H -#include "usb_cdc.h" +// legacy for old version -#ifdef __cplusplus -extern "C" { -#endif +#include "usbd_cdc_acm.h" -/* Init cdc acm interface driver */ -struct usbd_interface *usbd_cdc_acm_init_intf(uint8_t busid, struct usbd_interface *intf); - -/* Setup request command callback api */ -void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding); -void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding); -void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr); -void usbd_cdc_acm_set_rts(uint8_t busid, uint8_t intf, bool rts); -void usbd_cdc_acm_send_break(uint8_t busid, uint8_t intf); - -#ifdef __cplusplus -} -#endif - -#endif /* USBD_CDC_H */ +#endif \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc.c b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_acm.c similarity index 94% rename from rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc.c rename to rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_acm.c index 50d13d7..cf7c3c0 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_acm.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "usbd_core.h" -#include "usbd_cdc.h" +#include "usbd_cdc_acm.h" const char *stop_name[] = { "1", "1.5", "2" }; const char *parity_name[] = { "N", "O", "E", "M", "S" }; @@ -85,6 +85,8 @@ static int cdc_acm_class_interface_request_handler(uint8_t busid, struct usb_set struct usbd_interface *usbd_cdc_acm_init_intf(uint8_t busid, struct usbd_interface *intf) { + (void)busid; + intf->class_interface_handler = cdc_acm_class_interface_request_handler; intf->class_endpoint_handler = NULL; intf->vendor_handler = NULL; @@ -95,10 +97,16 @@ struct usbd_interface *usbd_cdc_acm_init_intf(uint8_t busid, struct usbd_interfa __WEAK void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) { + (void)busid; + (void)intf; + (void)line_coding; } __WEAK void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) { + (void)busid; + (void)intf; + line_coding->dwDTERate = 2000000; line_coding->bDataBits = 8; line_coding->bParityType = 0; @@ -107,12 +115,20 @@ __WEAK void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc __WEAK void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr) { + (void)busid; + (void)intf; + (void)dtr; } __WEAK void usbd_cdc_acm_set_rts(uint8_t busid, uint8_t intf, bool rts) { + (void)busid; + (void)intf; + (void)rts; } __WEAK void usbd_cdc_acm_send_break(uint8_t busid, uint8_t intf) { + (void)busid; + (void)intf; } diff --git a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_acm.h b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_acm.h new file mode 100644 index 0000000..662c238 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_acm.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CDC_ACM_H +#define USBD_CDC_ACM_H + +#include "usb_cdc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init cdc acm interface driver */ +struct usbd_interface *usbd_cdc_acm_init_intf(uint8_t busid, struct usbd_interface *intf); + +/* Setup request command callback api */ +void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding); +void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding); +void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr); +void usbd_cdc_acm_set_rts(uint8_t busid, uint8_t intf, bool rts); +void usbd_cdc_acm_send_break(uint8_t busid, uint8_t intf); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_CDC_ACM_H */ diff --git a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.c b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.c index b0c1217..5ae10a2 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.c @@ -7,17 +7,21 @@ #include "usbd_cdc_ecm.h" #define CDC_ECM_OUT_EP_IDX 0 -#define CDC_ECM_IN_EP_IDX 1 -#define CDC_ECM_INT_EP_IDX 2 +#define CDC_ECM_IN_EP_IDX 1 +#define CDC_ECM_INT_EP_IDX 2 + +/* Ethernet Maximum Segment size, typically 1514 bytes */ +#define CONFIG_CDC_ECM_ETH_MAX_SEGSZE 1536U /* Describe EndPoints configuration */ static struct usbd_endpoint cdc_ecm_ep_data[3]; +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_rx_buffer[CONFIG_CDC_ECM_ETH_MAX_SEGSZE]; static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_tx_buffer[CONFIG_CDC_ECM_ETH_MAX_SEGSZE]; +#endif static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_notify_buf[16]; -volatile uint8_t *g_cdc_ecm_rx_data_buffer = NULL; volatile uint32_t g_cdc_ecm_rx_data_length = 0; volatile uint32_t g_cdc_ecm_tx_data_length = 0; @@ -68,8 +72,10 @@ void usbd_cdc_ecm_send_notify(uint8_t notifycode, uint8_t value, uint32_t *speed break; } - if (bytes2send) { - usbd_ep_start_write(0, cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX].ep_addr, g_cdc_ecm_notify_buf, bytes2send); + if (usb_device_is_configured(0)) { + if (bytes2send) { + usbd_ep_start_write(0, cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX].ep_addr, g_cdc_ecm_notify_buf, bytes2send); + } } } @@ -79,6 +85,10 @@ static int cdc_ecm_class_interface_request_handler(uint8_t busid, struct usb_set "bRequest 0x%02x\r\n", setup->bRequest); + (void)busid; + (void)data; + (void)len; + g_cmd_intf = LO_BYTE(setup->wIndex); switch (setup->bRequest) { @@ -89,11 +99,11 @@ static int cdc_ecm_class_interface_request_handler(uint8_t busid, struct usb_set * bit3 Broadcast * bit4 Multicast */ - if (g_current_net_status == 0) { - g_current_net_status = 1; - usbd_cdc_ecm_send_notify(CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION, CDC_ECM_NET_CONNECTED, NULL); - } - +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP + g_connect_speed_table[0] = 100000000; /* 100 Mbps */ + g_connect_speed_table[1] = 100000000; /* 100 Mbps */ + usbd_cdc_ecm_set_connect(true, g_connect_speed_table); +#endif break; default: USB_LOG_WRN("Unhandled CDC ECM Class bRequest 0x%02x\r\n", setup->bRequest); @@ -105,15 +115,19 @@ static int cdc_ecm_class_interface_request_handler(uint8_t busid, struct usb_set void cdc_ecm_notify_handler(uint8_t busid, uint8_t event, void *arg) { + (void)busid; + (void)arg; + switch (event) { case USBD_EVENT_RESET: g_current_net_status = 0; g_cdc_ecm_rx_data_length = 0; g_cdc_ecm_tx_data_length = 0; - g_cdc_ecm_rx_data_buffer = NULL; break; case USBD_EVENT_CONFIGURED: - usbd_ep_start_read(0, cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr, &g_cdc_ecm_rx_buffer[g_cdc_ecm_rx_data_length], usbd_get_ep_mps(busid, cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr)); +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP + usbd_cdc_ecm_start_read(g_cdc_ecm_rx_buffer, CONFIG_CDC_ECM_ETH_MAX_SEGSZE); +#endif break; default: @@ -123,36 +137,45 @@ void cdc_ecm_notify_handler(uint8_t busid, uint8_t event, void *arg) void cdc_ecm_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) { - g_cdc_ecm_rx_data_length += nbytes; + (void)busid; - if (nbytes < usbd_get_ep_mps(busid, ep)) { - g_cdc_ecm_rx_data_buffer = g_cdc_ecm_rx_buffer; - usbd_cdc_ecm_data_recv_done(g_cdc_ecm_rx_buffer, g_cdc_ecm_rx_data_length); - } else { - usbd_ep_start_read(0, ep, &g_cdc_ecm_rx_buffer[g_cdc_ecm_rx_data_length], usbd_get_ep_mps(busid, ep)); - } + g_cdc_ecm_rx_data_length = nbytes; + usbd_cdc_ecm_data_recv_done(g_cdc_ecm_rx_data_length); } void cdc_ecm_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) { - if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) { + (void)busid; + + if ((nbytes % usbd_get_ep_mps(0, ep)) == 0 && nbytes) { /* send zlp */ usbd_ep_start_write(0, ep, NULL, 0); } else { + usbd_cdc_ecm_data_send_done(g_cdc_ecm_tx_data_length); g_cdc_ecm_tx_data_length = 0; } } void cdc_ecm_int_in(uint8_t busid, uint8_t ep, uint32_t nbytes) { - if (g_current_net_status == 1) { - g_current_net_status = 2; - usbd_cdc_ecm_send_notify(CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION, CDC_ECM_NET_CONNECTED, g_connect_speed_table); + (void)busid; + (void)ep; + (void)nbytes; + + if (g_current_net_status == 2) { + g_current_net_status = 3; + usbd_cdc_ecm_send_notify(CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE, 0, g_connect_speed_table); + } else { + g_current_net_status = 0; } } int usbd_cdc_ecm_start_write(uint8_t *buf, uint32_t len) { + if (!usb_device_is_configured(0)) { + return -USB_ERR_NODEV; + } + if (g_cdc_ecm_tx_data_length > 0) { return -USB_ERR_BUSY; } @@ -160,14 +183,17 @@ int usbd_cdc_ecm_start_write(uint8_t *buf, uint32_t len) g_cdc_ecm_tx_data_length = len; USB_LOG_DBG("txlen:%d\r\n", g_cdc_ecm_tx_data_length); - return usbd_ep_start_write(0, cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX].ep_addr, buf, g_cdc_ecm_tx_data_length); + return usbd_ep_start_write(0, cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX].ep_addr, buf, len); } -void usbd_cdc_ecm_start_read_next(void) +int usbd_cdc_ecm_start_read(uint8_t *buf, uint32_t len) { + if (!usb_device_is_configured(0)) { + return -USB_ERR_NODEV; + } + g_cdc_ecm_rx_data_length = 0; - g_cdc_ecm_rx_data_buffer = NULL; - usbd_ep_start_read(0, cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr, g_cdc_ecm_rx_buffer, usbd_get_ep_mps(0, cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr)); + return usbd_ep_start_read(0, cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr, buf, len); } #ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP @@ -175,19 +201,19 @@ struct pbuf *usbd_cdc_ecm_eth_rx(void) { struct pbuf *p; - if (g_cdc_ecm_rx_data_buffer == NULL) { + if (g_cdc_ecm_rx_data_length == 0) { return NULL; } p = pbuf_alloc(PBUF_RAW, g_cdc_ecm_rx_data_length, PBUF_POOL); if (p == NULL) { - usbd_cdc_ecm_start_read_next(); + usbd_cdc_ecm_start_read(g_cdc_ecm_rx_buffer, CONFIG_CDC_ECM_ETH_MAX_SEGSZE); return NULL; } usb_memcpy(p->payload, (uint8_t *)g_cdc_ecm_rx_buffer, g_cdc_ecm_rx_data_length); p->len = g_cdc_ecm_rx_data_length; USB_LOG_DBG("rxlen:%d\r\n", g_cdc_ecm_rx_data_length); - usbd_cdc_ecm_start_read_next(); + usbd_cdc_ecm_start_read(g_cdc_ecm_rx_buffer, CONFIG_CDC_ECM_ETH_MAX_SEGSZE); return p; } @@ -235,11 +261,24 @@ struct usbd_interface *usbd_cdc_ecm_init_intf(struct usbd_interface *intf, const return intf; } -void usbd_cdc_ecm_set_connect_speed(uint32_t speed[2]) +void usbd_cdc_ecm_set_connect(bool connect, uint32_t speed[2]) { - memcpy(g_connect_speed_table, speed, 8); + if (connect) { + g_current_net_status = 2; + memcpy(g_connect_speed_table, speed, 8); + usbd_cdc_ecm_send_notify(CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION, CDC_ECM_NET_CONNECTED, NULL); + } else { + g_current_net_status = 1; + usbd_cdc_ecm_send_notify(CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION, CDC_ECM_NET_DISCONNECTED, NULL); + } } -__WEAK void usbd_cdc_ecm_data_recv_done(uint8_t *buf, uint32_t len) +__WEAK void usbd_cdc_ecm_data_recv_done(uint32_t len) { + (void)len; +} + +__WEAK void usbd_cdc_ecm_data_send_done(uint32_t len) +{ + (void)len; } diff --git a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.h b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.h index 8d9e5c9..3e0284e 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.h +++ b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.h @@ -12,21 +12,15 @@ extern "C" { #endif -/* Ethernet Maximum Segment size, typically 1514 bytes */ -#define CONFIG_CDC_ECM_ETH_MAX_SEGSZE 1514U - /* Init cdc ecm interface driver */ struct usbd_interface *usbd_cdc_ecm_init_intf(struct usbd_interface *intf, const uint8_t int_ep, const uint8_t out_ep, const uint8_t in_ep); -/* Setup request command callback api */ -void usbd_cdc_ecm_set_connect_speed(uint32_t speed[2]); +void usbd_cdc_ecm_set_connect(bool connect, uint32_t speed[2]); -/* Api for eth only without any net stack */ -uint8_t *usbd_cdc_ecm_get_tx_buffer(void); -void usbd_cdc_ecm_send_done(void); +void usbd_cdc_ecm_data_recv_done(uint32_t len); +void usbd_cdc_ecm_data_send_done(uint32_t len); int usbd_cdc_ecm_start_write(uint8_t *buf, uint32_t len); -void usbd_cdc_ecm_data_recv_done(uint8_t *buf, uint32_t len); -void usbd_cdc_ecm_start_read_next(void); +int usbd_cdc_ecm_start_read(uint8_t *buf, uint32_t len); #ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP #include "lwip/netif.h" diff --git a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.c b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.c index c2c953a..53666b3 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.c @@ -12,18 +12,18 @@ #define DEV_FORMAT "/dev/ttyACM%d" -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_acm_buf[64]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_acm_buf[CONFIG_USBHOST_MAX_CDC_ACM_CLASS][USB_ALIGN_UP(64, CONFIG_USB_ALIGN_SIZE)]; static struct usbh_cdc_acm g_cdc_acm_class[CONFIG_USBHOST_MAX_CDC_ACM_CLASS]; static uint32_t g_devinuse = 0; static struct usbh_cdc_acm *usbh_cdc_acm_class_alloc(void) { - int devno; + uint8_t devno; for (devno = 0; devno < CONFIG_USBHOST_MAX_CDC_ACM_CLASS; devno++) { - if ((g_devinuse & (1 << devno)) == 0) { - g_devinuse |= (1 << devno); + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); memset(&g_cdc_acm_class[devno], 0, sizeof(struct usbh_cdc_acm)); g_cdc_acm_class[devno].minor = devno; return &g_cdc_acm_class[devno]; @@ -34,10 +34,10 @@ static struct usbh_cdc_acm *usbh_cdc_acm_class_alloc(void) static void usbh_cdc_acm_class_free(struct usbh_cdc_acm *cdc_acm_class) { - int devno = cdc_acm_class->minor; + uint8_t devno = cdc_acm_class->minor; - if (devno >= 0 && devno < 32) { - g_devinuse &= ~(1 << devno); + if (devno < 32) { + g_devinuse &= ~(1U << devno); } memset(cdc_acm_class, 0, sizeof(struct usbh_cdc_acm)); } @@ -57,9 +57,9 @@ int usbh_cdc_acm_set_line_coding(struct usbh_cdc_acm *cdc_acm_class, struct cdc_ setup->wIndex = cdc_acm_class->intf; setup->wLength = 7; - memcpy(g_cdc_acm_buf, line_coding, sizeof(struct cdc_line_coding)); + memcpy(g_cdc_acm_buf[cdc_acm_class->minor], line_coding, sizeof(struct cdc_line_coding)); - return usbh_control_transfer(cdc_acm_class->hport, setup, g_cdc_acm_buf); + return usbh_control_transfer(cdc_acm_class->hport, setup, g_cdc_acm_buf[cdc_acm_class->minor]); } int usbh_cdc_acm_get_line_coding(struct usbh_cdc_acm *cdc_acm_class, struct cdc_line_coding *line_coding) @@ -78,11 +78,11 @@ int usbh_cdc_acm_get_line_coding(struct usbh_cdc_acm *cdc_acm_class, struct cdc_ setup->wIndex = cdc_acm_class->intf; setup->wLength = 7; - ret = usbh_control_transfer(cdc_acm_class->hport, setup, g_cdc_acm_buf); + ret = usbh_control_transfer(cdc_acm_class->hport, setup, g_cdc_acm_buf[cdc_acm_class->minor]); if (ret < 0) { return ret; } - memcpy(line_coding, g_cdc_acm_buf, sizeof(struct cdc_line_coding)); + memcpy(line_coding, g_cdc_acm_buf[cdc_acm_class->minor], sizeof(struct cdc_line_coding)); return ret; } @@ -231,20 +231,26 @@ int usbh_cdc_acm_bulk_out_transfer(struct usbh_cdc_acm *cdc_acm_class, uint8_t * static int usbh_cdc_data_connect(struct usbh_hubport *hport, uint8_t intf) { + (void)hport; + (void)intf; return 0; } static int usbh_cdc_data_disconnect(struct usbh_hubport *hport, uint8_t intf) { + (void)hport; + (void)intf; return 0; } __WEAK void usbh_cdc_acm_run(struct usbh_cdc_acm *cdc_acm_class) { + (void)cdc_acm_class; } __WEAK void usbh_cdc_acm_stop(struct usbh_cdc_acm *cdc_acm_class) { + (void)cdc_acm_class; } const struct usbh_class_driver cdc_acm_class_driver = { @@ -260,19 +266,19 @@ const struct usbh_class_driver cdc_data_class_driver = { }; CLASS_INFO_DEFINE const struct usbh_class_info cdc_acm_class_info = { - .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, - .class = USB_DEVICE_CLASS_CDC, - .subclass = CDC_ABSTRACT_CONTROL_MODEL, - .protocol = CDC_COMMON_PROTOCOL_AT_COMMANDS, + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS, + .bInterfaceClass = USB_DEVICE_CLASS_CDC, + .bInterfaceSubClass = CDC_ABSTRACT_CONTROL_MODEL, + .bInterfaceProtocol = 0x00, .id_table = NULL, .class_driver = &cdc_acm_class_driver }; CLASS_INFO_DEFINE const struct usbh_class_info cdc_data_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS, - .class = USB_DEVICE_CLASS_CDC_DATA, - .subclass = 0x00, - .protocol = 0x00, + .bInterfaceClass = USB_DEVICE_CLASS_CDC_DATA, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, .id_table = NULL, .class_driver = &cdc_data_class_driver }; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.c b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.c index ad05d51..c4743e5 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.c @@ -236,6 +236,7 @@ void usbh_cdc_ecm_rx_thread(void *argument) uint32_t g_cdc_ecm_rx_length; int ret; + (void)argument; USB_LOG_INFO("Create cdc ecm rx thread\r\n"); // clang-format off find_class: @@ -306,10 +307,12 @@ int usbh_cdc_ecm_eth_output(uint32_t buflen) __WEAK void usbh_cdc_ecm_run(struct usbh_cdc_ecm *cdc_ecm_class) { + (void)cdc_ecm_class; } __WEAK void usbh_cdc_ecm_stop(struct usbh_cdc_ecm *cdc_ecm_class) { + (void)cdc_ecm_class; } const struct usbh_class_driver cdc_ecm_class_driver = { @@ -320,9 +323,9 @@ const struct usbh_class_driver cdc_ecm_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info cdc_ecm_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, - .class = USB_DEVICE_CLASS_CDC, - .subclass = CDC_ETHERNET_NETWORKING_CONTROL_MODEL, - .protocol = CDC_COMMON_PROTOCOL_NONE, + .bInterfaceClass = USB_DEVICE_CLASS_CDC, + .bInterfaceSubClass = CDC_ETHERNET_NETWORKING_CONTROL_MODEL, + .bInterfaceProtocol = CDC_COMMON_PROTOCOL_NONE, .id_table = NULL, .class_driver = &cdc_ecm_class_driver }; \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.c b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.c index 99e8871..f9f3c53 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.c @@ -48,7 +48,7 @@ static int usbh_cdc_ncm_get_ntb_parameters(struct usbh_cdc_ncm *cdc_ncm_class, s setup->wLength = 28; ret = usbh_control_transfer(cdc_ncm_class->hport, setup, g_cdc_ncm_buf); - if (ret < 0) { + if (ret < 8) { return ret; } @@ -259,6 +259,7 @@ void usbh_cdc_ncm_rx_thread(void *argument) uint32_t transfer_size = (16 * 1024); #endif + (void)argument; USB_LOG_INFO("Create cdc ncm rx thread\r\n"); // clang-format off find_class: @@ -330,7 +331,7 @@ find_class: #else if ((g_cdc_ncm_rx_length + (16 * 1024)) > CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE) { #endif - USB_LOG_ERR("Rx packet is overflow, please ruduce tcp window size or increase CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE\r\n"); + USB_LOG_ERR("Rx packet is overflow, please reduce tcp window size or increase CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE\r\n"); while (1) { } } @@ -386,10 +387,12 @@ int usbh_cdc_ncm_eth_output(uint32_t buflen) __WEAK void usbh_cdc_ncm_run(struct usbh_cdc_ncm *cdc_ncm_class) { + (void)cdc_ncm_class; } __WEAK void usbh_cdc_ncm_stop(struct usbh_cdc_ncm *cdc_ncm_class) { + (void)cdc_ncm_class; } const struct usbh_class_driver cdc_ncm_class_driver = { @@ -400,9 +403,9 @@ const struct usbh_class_driver cdc_ncm_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info cdc_ncm_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, - .class = USB_DEVICE_CLASS_CDC, - .subclass = CDC_NETWORK_CONTROL_MODEL, - .protocol = CDC_COMMON_PROTOCOL_NONE, + .bInterfaceClass = USB_DEVICE_CLASS_CDC, + .bInterfaceSubClass = CDC_NETWORK_CONTROL_MODEL, + .bInterfaceProtocol = CDC_COMMON_PROTOCOL_NONE, .id_table = NULL, .class_driver = &cdc_ncm_class_driver }; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/hid/usb_hid.h b/rt-thread/components/drivers/usb/cherryusb/class/hid/usb_hid.h index 5a88a34..b244d11 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/hid/usb_hid.h +++ b/rt-thread/components/drivers/usb/cherryusb/class/hid/usb_hid.h @@ -558,26 +558,24 @@ struct usb_hid_kbd_report }; /* Keyboard output report (1 byte) (HID B.1), - * see USBHID_KBDOUT_* definitions + * see HID_KBD_OUTPUT_* definitions */ /* Mouse input report (HID B.2) */ struct usb_hid_mouse_report { uint8_t buttons; /* See HID_MOUSE_INPUT_BUTTON_* definitions */ - uint8_t xdisp; /* X displacement */ - uint8_t ydisp; /* y displacement */ + int8_t xdisp; /* X displacement */ + int8_t ydisp; /* y displacement */ /* Device specific additional bytes may follow */ -#ifdef CONFIG_INPUT_MOUSE_WHEEL uint8_t wdisp; /* Wheel displacement */ -#endif }; /* Joystick input report (1 bytes) (HID D.1) */ struct usb_hid_js_report { - uint8_t xpos; /* X position */ - uint8_t ypos; /* X position */ + int8_t xpos; /* X position */ + int8_t ypos; /* X position */ uint8_t buttons; /* See USBHID_JSIN_* definitions */ uint8_t throttle; /* Throttle */ }; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/hid/usbd_hid.c b/rt-thread/components/drivers/usb/cherryusb/class/hid/usbd_hid.c index d98b82e..fed749f 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/hid/usbd_hid.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/hid/usbd_hid.c @@ -50,6 +50,8 @@ static int hid_class_interface_request_handler(uint8_t busid, struct usb_setup_p struct usbd_interface *usbd_hid_init_intf(uint8_t busid, struct usbd_interface *intf, const uint8_t *desc, uint32_t desc_len) { + (void)busid; + intf->class_interface_handler = hid_class_interface_request_handler; intf->class_endpoint_handler = NULL; intf->vendor_handler = NULL; @@ -60,30 +62,65 @@ struct usbd_interface *usbd_hid_init_intf(uint8_t busid, struct usbd_interface * return intf; } +/* + * Appendix G: HID Request Support Requirements + * + * The following table enumerates the requests that need to be supported by various types of HID class devices. + * Device type GetReport SetReport GetIdle SetIdle GetProtocol SetProtocol + * ------------------------------------------------------------------------------------------ + * Boot Mouse Required Optional Optional Optional Required Required + * Non-Boot Mouse Required Optional Optional Optional Optional Optional + * Boot Keyboard Required Optional Required Required Required Required + * Non-Boot Keybrd Required Optional Required Required Optional Optional + * Other Device Required Optional Optional Optional Optional Optional + */ + __WEAK void usbd_hid_get_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t **data, uint32_t *len) { + (void)busid; + (void)intf; + (void)report_id; + (void)report_type; (*data[0]) = 0; *len = 1; } __WEAK uint8_t usbd_hid_get_idle(uint8_t busid, uint8_t intf, uint8_t report_id) { + (void)busid; + (void)intf; + (void)report_id; return 0; } __WEAK uint8_t usbd_hid_get_protocol(uint8_t busid, uint8_t intf) { + (void)busid; + (void)intf; return 0; } __WEAK void usbd_hid_set_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint32_t report_len) { + (void)busid; + (void)intf; + (void)report_id; + (void)report_type; + (void)report; + (void)report_len; } __WEAK void usbd_hid_set_idle(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t duration) { + (void)busid; + (void)intf; + (void)report_id; + (void)duration; } __WEAK void usbd_hid_set_protocol(uint8_t busid, uint8_t intf, uint8_t protocol) { + (void)busid; + (void)intf; + (void)protocol; } \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/hid/usbh_hid.c b/rt-thread/components/drivers/usb/cherryusb/class/hid/usbh_hid.c index 1761ba6..0fd58ab 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/hid/usbh_hid.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/hid/usbh_hid.c @@ -12,18 +12,26 @@ #define DEV_FORMAT "/dev/input%d" -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hid_buf[128]; +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hid_buf[CONFIG_USBHOST_MAX_HID_CLASS][USB_ALIGN_UP(64, CONFIG_USB_ALIGN_SIZE)]; static struct usbh_hid g_hid_class[CONFIG_USBHOST_MAX_HID_CLASS]; static uint32_t g_devinuse = 0; static struct usbh_hid *usbh_hid_class_alloc(void) { - int devno; + uint8_t devno; for (devno = 0; devno < CONFIG_USBHOST_MAX_HID_CLASS; devno++) { - if ((g_devinuse & (1 << devno)) == 0) { - g_devinuse |= (1 << devno); + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); memset(&g_hid_class[devno], 0, sizeof(struct usbh_hid)); g_hid_class[devno].minor = devno; return &g_hid_class[devno]; @@ -34,18 +42,17 @@ static struct usbh_hid *usbh_hid_class_alloc(void) static void usbh_hid_class_free(struct usbh_hid *hid_class) { - int devno = hid_class->minor; + uint8_t devno = hid_class->minor; - if (devno >= 0 && devno < 32) { - g_devinuse &= ~(1 << devno); + if (devno < 32) { + g_devinuse &= ~(1U << devno); } memset(hid_class, 0, sizeof(struct usbh_hid)); } -static int usbh_hid_get_report_descriptor(struct usbh_hid *hid_class, uint8_t *buffer) +int usbh_hid_get_report_descriptor(struct usbh_hid *hid_class, uint8_t *buffer, uint32_t buflen) { struct usb_setup_packet *setup; - int ret; if (!hid_class || !hid_class->hport) { return -USB_ERR_INVAL; @@ -56,14 +63,9 @@ static int usbh_hid_get_report_descriptor(struct usbh_hid *hid_class, uint8_t *b setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; setup->wValue = HID_DESCRIPTOR_TYPE_HID_REPORT << 8; setup->wIndex = hid_class->intf; - setup->wLength = 128; + setup->wLength = buflen; - ret = usbh_control_transfer(hid_class->hport, setup, g_hid_buf); - if (ret < 0) { - return ret; - } - memcpy(buffer, g_hid_buf, ret - 8); - return ret; + return usbh_control_transfer(hid_class->hport, setup, buffer); } int usbh_hid_set_idle(struct usbh_hid *hid_class, uint8_t report_id, uint8_t duration) @@ -100,11 +102,11 @@ int usbh_hid_get_idle(struct usbh_hid *hid_class, uint8_t *buffer) setup->wIndex = hid_class->intf; setup->wLength = 1; - ret = usbh_control_transfer(hid_class->hport, setup, g_hid_buf); - if (ret < 0) { + ret = usbh_control_transfer(hid_class->hport, setup, g_hid_buf[hid_class->minor]); + if (ret < 8) { return ret; } - memcpy(buffer, g_hid_buf, 1); + memcpy(buffer, g_hid_buf[hid_class->minor], ret - 8); return ret; } @@ -147,6 +149,7 @@ int usbh_hid_set_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t int usbh_hid_get_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t report_id, uint8_t *buffer, uint32_t buflen) { struct usb_setup_packet *setup; + int ret; if (!hid_class || !hid_class->hport) { return -USB_ERR_INVAL; @@ -159,13 +162,21 @@ int usbh_hid_get_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t setup->wIndex = 0; setup->wLength = buflen; - return usbh_control_transfer(hid_class->hport, setup, buffer); + ret = usbh_control_transfer(hid_class->hport, setup, g_hid_buf[hid_class->minor]); + if (ret < 8) { + return ret; + } + memcpy(buffer, g_hid_buf[hid_class->minor], ret - 8); + return ret; } int usbh_hid_connect(struct usbh_hubport *hport, uint8_t intf) { struct usb_endpoint_descriptor *ep_desc; int ret; + uint8_t cur_iface = 0xff; + uint8_t *p; + bool found = false; struct usbh_hid *hid_class = usbh_hid_class_alloc(); if (hid_class == NULL) { @@ -178,6 +189,42 @@ int usbh_hid_connect(struct usbh_hubport *hport, uint8_t intf) hport->config.intf[intf].priv = hid_class; + p = hport->raw_config_desc; + while (p[DESC_bLength]) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_INTERFACE: + cur_iface = p[INTF_DESC_bInterfaceNumber]; + if (cur_iface == intf) { + hid_class->protocol = p[7]; + struct usb_hid_descriptor *desc = (struct usb_hid_descriptor *)(p + 9); + + if (desc->bDescriptorType != HID_DESCRIPTOR_TYPE_HID) { + USB_LOG_ERR("HID descriptor not found\r\n"); + return -USB_ERR_INVAL; + } + + if (desc->subdesc[0].bDescriptorType != HID_DESCRIPTOR_TYPE_HID_REPORT) { + USB_LOG_ERR("HID report descriptor not found\r\n"); + return -USB_ERR_INVAL; + } + + hid_class->report_size = desc->subdesc[0].wDescriptorLength; + found = true; + goto found; + } + break; + default: + break; + } + /* skip to next descriptor */ + p += p[DESC_bLength]; + } + + if (found == false) { + USB_LOG_ERR("HID interface not found\r\n"); + return -USB_ERR_INVAL; + } +found: // /* 0x0 = boot protocol, 0x1 = report protocol */ // ret = usbh_hid_set_protocol(hid_class, 0x1); // if (ret < 0) { @@ -189,7 +236,8 @@ int usbh_hid_connect(struct usbh_hubport *hport, uint8_t intf) USB_LOG_WRN("Do not support set idle\r\n"); } - ret = usbh_hid_get_report_descriptor(hid_class, hid_class->report_desc); + /* We read report desc but do nothing (because of too much memory usage for parsing report desc, parsed by users) */ + ret = usbh_hid_get_report_descriptor(hid_class, g_hid_buf[hid_class->minor], MIN(sizeof(g_hid_buf[hid_class->minor]), hid_class->report_size)); if (ret < 0) { return ret; } @@ -239,10 +287,12 @@ int usbh_hid_disconnect(struct usbh_hubport *hport, uint8_t intf) __WEAK void usbh_hid_run(struct usbh_hid *hid_class) { + (void)hid_class; } __WEAK void usbh_hid_stop(struct usbh_hid *hid_class) { + (void)hid_class; } const struct usbh_class_driver hid_class_driver = { @@ -253,9 +303,9 @@ const struct usbh_class_driver hid_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info hid_custom_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS, - .class = USB_DEVICE_CLASS_HID, - .subclass = 0x00, - .protocol = 0x00, + .bInterfaceClass = USB_DEVICE_CLASS_HID, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, .id_table = NULL, .class_driver = &hid_class_driver }; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/hid/usbh_hid.h b/rt-thread/components/drivers/usb/cherryusb/class/hid/usbh_hid.h index 17caaba..5e8fce6 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/hid/usbh_hid.h +++ b/rt-thread/components/drivers/usb/cherryusb/class/hid/usbh_hid.h @@ -15,7 +15,9 @@ struct usbh_hid { struct usbh_urb intin_urb; /* INTR IN urb */ struct usbh_urb intout_urb; /* INTR OUT urb */ - uint8_t report_desc[256]; + uint16_t report_size; + + uint8_t protocol; uint8_t intf; /* interface number */ uint8_t minor; @@ -26,6 +28,7 @@ struct usbh_hid { extern "C" { #endif +int usbh_hid_get_report_descriptor(struct usbh_hid *hid_class, uint8_t *buffer, uint32_t buflen); int usbh_hid_set_idle(struct usbh_hid *hid_class, uint8_t report_id, uint8_t duration); int usbh_hid_get_idle(struct usbh_hid *hid_class, uint8_t *buffer); int usbh_hid_set_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t report_id, uint8_t *buffer, uint32_t buflen); diff --git a/rt-thread/components/drivers/usb/cherryusb/class/hub/usb_hub.h b/rt-thread/components/drivers/usb/cherryusb/class/hub/usb_hub.h index 7956b16..68e0ecf 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/hub/usb_hub.h +++ b/rt-thread/components/drivers/usb/cherryusb/class/hub/usb_hub.h @@ -10,6 +10,12 @@ #define HUB_DESCRIPTOR_TYPE_HUB 0x29 #define HUB_DESCRIPTOR_TYPE_HUB3 0x2A +#define HUB_MAX_DEPTH 5 + +#define HUB_SUBCLASS 0x00 +#define HUB_PROTOCOL_STT 0x01 +#define HUB_PROTOCOL_MTT 0x02 + /* Hub class requests */ #define HUB_REQUEST_GET_STATUS USB_REQUEST_GET_STATUS #define HUB_REQUEST_CLEAR_FEATURE USB_REQUEST_CLEAR_FEATURE @@ -27,23 +33,31 @@ #define HUB_FEATURE_HUB_C_OVERCURRENT (0x1) /* Port features */ -#define HUB_PORT_FEATURE_CONNECTION (0x00) -#define HUB_PORT_FEATURE_ENABLE (0x01) -#define HUB_PORT_FEATURE_SUSPEND (0x02) -#define HUB_PORT_FEATURE_OVERCURRENT (0x03) -#define HUB_PORT_FEATURE_RESET (0x04) -#define HUB_PORT_FEATURE_L1 (0x05) -#define HUB_PORT_FEATURE_POWER (0x08) -#define HUB_PORT_FEATURE_LOWSPEED (0x09) -#define HUB_PORT_FEATURE_HIGHSPEED (0x0a) +#define HUB_PORT_FEATURE_CONNECTION (0x00) +#define HUB_PORT_FEATURE_ENABLE (0x01) +#define HUB_PORT_FEATURE_SUSPEND (0x02) +#define HUB_PORT_FEATURE_OVERCURRENT (0x03) +#define HUB_PORT_FEATURE_RESET (0x04) +#define HUB_PORT_FEATURE_L1 (0x05) /* USB 2.0 only */ + +#define HUB_PORT_FEATURE_POWER (0x08) /* USB 2.0 only */ +#define HUB_PORT_FEATURE_POWER_SS (0x09) /* USB 3.0 only */ +/* This is a bit tricky because HUB_PORT_FEATURE_POWER_SS and + HUB_PORT_FEATURE_LOWSPEED share the same bit. */ +#define HUB_PORT_FEATURE_LOWSPEED (0x09) /* USB 2.0 only */ +#define HUB_PORT_FEATURE_HIGHSPEED (0x0a) /* USB 2.0 only */ +#define HUB_PORT_FEATURE_TEST (0x0b) /* USB 2.0 only */ +#define HUB_PORT_FEATURE_INDICATOR (0x0c) /* USB 2.0 only */ + +/* Port status change (wPortChange) */ #define HUB_PORT_FEATURE_C_CONNECTION (0x10) -#define HUB_PORT_FEATURE_C_ENABLE (0x11) -#define HUB_PORT_FEATURE_C_SUSPEND (0x12) +#define HUB_PORT_FEATURE_C_ENABLE (0x11) /* USB 2.0 only */ +#define HUB_PORT_FEATURE_C_SUSPEND (0x12) /* USB 2.0 only */ #define HUB_PORT_FEATURE_C_OVER_CURREN (0x13) #define HUB_PORT_FEATURE_C_RESET (0x14) -#define HUB_PORT_FEATURE_TEST (0x15) -#define HUB_PORT_FEATURE_INDICATOR (0x16) -#define HUB_PORT_FEATURE_C_PORTL1 (0x17) +#define HUB_PORT_FEATURE_C_BH_RESET (0x15) /* USB 3.0 only */ +#define HUB_PORT_FEATURE_C_LINK_STATE (0x16) /* USB 3.0 only */ +#define HUB_PORT_FEATURE_C_CONFIG_ERR (0x17) /* USB 3.0 only */ /* Hub status */ #define HUB_STATUS_LOCALPOWER (1 << 0) @@ -56,23 +70,42 @@ /* Hub port status */ #define HUB_PORT_STATUS_CONNECTION (1 << 0) #define HUB_PORT_STATUS_ENABLE (1 << 1) -#define HUB_PORT_STATUS_SUSPEND (1 << 2) +#define HUB_PORT_STATUS_SUSPEND (1 << 2) /* USB 2.0 only */ #define HUB_PORT_STATUS_OVERCURRENT (1 << 3) #define HUB_PORT_STATUS_RESET (1 << 4) -#define HUB_PORT_STATUS_L1 (1 << 5) -#define HUB_PORT_STATUS_POWER (1 << 8) -#define HUB_PORT_STATUS_LOW_SPEED (1 << 9) -#define HUB_PORT_STATUS_HIGH_SPEED (1 << 10) -#define HUB_PORT_STATUS_TEST (1 << 11) -#define HUB_PORT_STATUS_INDICATOR (1 << 12) +#define HUB_PORT_STATUS_L1 (1 << 5) /* USB 2.0 only */ + +/* Port Link State (PORT_LINK_STATE), USB 3.0 only */ +#define HUB_PORT_STATUS_LS_U0 (0x00 << 5) +#define HUB_PORT_STATUS_LS_U1 (0x01 << 5) +#define HUB_PORT_STATUS_LS_U2 (0x02 << 5) +#define HUB_PORT_STATUS_LS_U3 (0x03 << 5) +#define HUB_PORT_STATUS_LS_SS_DISABLED (0x04 << 5) +#define HUB_PORT_STATUS_LS_RX_DETECT (0x05 << 5) +#define HUB_PORT_STATUS_LS_SS_INACTIVE (0x06 << 5) +#define HUB_PORT_STATUS_LS_POLLING (0x07 << 5) +#define HUB_PORT_STATUS_LS_RECOVERY (0x08 << 5) +#define HUB_PORT_STATUS_LS_HOT_RESET (0x09 << 5) +#define HUB_PORT_STATUS_LS_COMP_MOD (0x0a << 5) +#define HUB_PORT_STATUS_LS_LOOPBACK (0x0b << 5) + +#define HUB_PORT_STATUS_POWER (1 << 8) +#define HUB_PORT_STATUS_POWER_SS (1 << 9) /* USB 3.0 only */ +#define HUB_PORT_STATUS_LOW_SPEED (1 << 9) /* USB 2.0 only */ +#define HUB_PORT_STATUS_HIGH_SPEED (1 << 10) /* USB 2.0 only */ +#define HUB_PORT_STATUS_TEST (1 << 11) /* USB 2.0 only */ +#define HUB_PORT_STATUS_INDICATOR (1 << 12) /* USB 2.0 only */ /* Hub port status change */ #define HUB_PORT_STATUS_C_CONNECTION (1 << 0) -#define HUB_PORT_STATUS_C_ENABLE (1 << 1) -#define HUB_PORT_STATUS_C_SUSPEND (1 << 2) +#define HUB_PORT_STATUS_C_ENABLE (1 << 1) /* USB 2.0 only */ +#define HUB_PORT_STATUS_C_SUSPEND (1 << 2) /* USB 2.0 only */ #define HUB_PORT_STATUS_C_OVERCURRENT (1 << 3) #define HUB_PORT_STATUS_C_RESET (1 << 4) -#define HUB_PORT_STATUS_C_L1 (1 << 5) +#define HUB_PORT_STATUS_C_L1 (1 << 5) /* USB 2.0 only */ +#define HUB_PORT_STATUS_C_BH_RESET (1 << 5) /* USB 3.0 only */ +#define HUB_PORT_STATUS_C_PORTLINK (1 << 6) /* USB 3.0 only */ +#define HUB_PORT_STATUS_C_CONFIGERR (1 << 7) /* USB 3.0 only */ /* Hub characteristics */ #define HUB_CHAR_LPSM_SHIFT (0) /* Bits 0-1: Logical Power Switching Mode */ @@ -106,6 +139,21 @@ struct usb_hub_descriptor { #define USB_SIZEOF_HUB_DESC 9 +/* Super speed Hub descriptor */ +struct usb_hub_ss_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t bHubHdrDecLat; + uint16_t wHubDelay; + uint8_t DeviceRemovable; +} __PACKED; + +#define USB_SIZEOF_HUB_SS_DESC 11 + /* Hub status */ struct hub_status { uint16_t wPortStatus; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/hub/usbh_hub.c b/rt-thread/components/drivers/usb/cherryusb/class/hub/usbh_hub.c index 1745d8c..9dae396 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/hub/usbh_hub.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/hub/usbh_hub.c @@ -33,11 +33,11 @@ static uint32_t g_devinuse = 0; static struct usbh_hub *usbh_hub_class_alloc(void) { - int devno; + uint8_t devno; for (devno = 0; devno < CONFIG_USBHOST_MAX_EXTHUBS; devno++) { - if ((g_devinuse & (1 << devno)) == 0) { - g_devinuse |= (1 << devno); + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); memset(&g_hub_class[devno], 0, sizeof(struct usbh_hub)); g_hub_class[devno].index = EXTHUB_FIRST_INDEX + devno; return &g_hub_class[devno]; @@ -48,16 +48,14 @@ static struct usbh_hub *usbh_hub_class_alloc(void) static void usbh_hub_class_free(struct usbh_hub *hub_class) { - int devno = hub_class->index - EXTHUB_FIRST_INDEX; + uint8_t devno = hub_class->index - EXTHUB_FIRST_INDEX; - if (devno >= 0 && devno < 32) { - g_devinuse &= ~(1 << devno); + if (devno < 32) { + g_devinuse &= ~(1U << devno); } memset(hub_class, 0, sizeof(struct usbh_hub)); } -#endif -#if CONFIG_USBHOST_MAX_EXTHUBS > 0 static int _usbh_hub_get_hub_descriptor(struct usbh_hub *hub, uint8_t *buffer) { struct usb_setup_packet *setup; @@ -67,15 +65,7 @@ static int _usbh_hub_get_hub_descriptor(struct usbh_hub *hub, uint8_t *buffer) setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; - - /* TODO: hub descriptor has some difference between USB 2.0 and USB 3.x, - and we havn't handle the difference here */ - if ((hub->parent->speed == USB_SPEED_SUPER) || - (hub->parent->speed == USB_SPEED_SUPER_PLUS)) { - setup->wValue = HUB_DESCRIPTOR_TYPE_HUB3 << 8; - } else { - setup->wValue = HUB_DESCRIPTOR_TYPE_HUB << 8; - } + setup->wValue = HUB_DESCRIPTOR_TYPE_HUB << 8; setup->wIndex = 0; setup->wLength = USB_SIZEOF_HUB_DESC; @@ -87,8 +77,8 @@ static int _usbh_hub_get_hub_descriptor(struct usbh_hub *hub, uint8_t *buffer) memcpy(buffer, g_hub_buf[hub->bus->busid], USB_SIZEOF_HUB_DESC); return ret; } -#if 0 -static int _usbh_hub_get_status(struct usbh_hub *hub, uint8_t *buffer) + +static int _usbh_hub_get_hub_ss_descriptor(struct usbh_hub *hub, uint8_t *buffer) { struct usb_setup_packet *setup; int ret; @@ -96,20 +86,20 @@ static int _usbh_hub_get_status(struct usbh_hub *hub, uint8_t *buffer) setup = hub->parent->setup; setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; - setup->bRequest = HUB_REQUEST_GET_STATUS; - setup->wValue = 0; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = HUB_DESCRIPTOR_TYPE_HUB3 << 8; + setup->wIndex = 0; - setup->wLength = 2; + setup->wLength = USB_SIZEOF_HUB_SS_DESC; ret = usbh_control_transfer(hub->parent, setup, g_hub_buf[hub->bus->busid]); if (ret < 0) { return ret; } - memcpy(buffer, g_hub_buf[hub->bus->busid], 2); + memcpy(buffer, g_hub_buf[hub->bus->busid], USB_SIZEOF_HUB_SS_DESC); return ret; } #endif -#endif static int _usbh_hub_get_portstatus(struct usbh_hub *hub, uint8_t port, struct hub_port_status *port_status) { @@ -180,6 +170,8 @@ static int _usbh_hub_set_depth(struct usbh_hub *hub, uint16_t depth) #if CONFIG_USBHOST_MAX_EXTHUBS > 0 static int parse_hub_descriptor(struct usb_hub_descriptor *desc, uint16_t length) { + (void)length; + if (desc->bLength != USB_SIZEOF_HUB_DESC) { USB_LOG_ERR("invalid device bLength 0x%02x\r\n", desc->bLength); return -1; @@ -199,6 +191,29 @@ static int parse_hub_descriptor(struct usb_hub_descriptor *desc, uint16_t length } return 0; } + +static int parse_hub_ss_descriptor(struct usb_hub_ss_descriptor *desc, uint16_t length) +{ + (void)length; + + if (desc->bLength < USB_SIZEOF_HUB_SS_DESC) { + USB_LOG_ERR("invalid device bLength 0x%02x\r\n", desc->bLength); + return -1; + } else if (desc->bDescriptorType != HUB_DESCRIPTOR_TYPE_HUB3) { + USB_LOG_ERR("unexpected descriptor 0x%02x\r\n", desc->bDescriptorType); + return -2; + } else { + USB_LOG_RAW("SuperSpeed Hub Descriptor:\r\n"); + USB_LOG_RAW("bLength: 0x%02x \r\n", desc->bLength); + USB_LOG_RAW("bDescriptorType: 0x%02x \r\n", desc->bDescriptorType); + USB_LOG_RAW("bNbrPorts: 0x%02x \r\n", desc->bNbrPorts); + USB_LOG_RAW("wHubCharacteristics: 0x%04x \r\n", desc->wHubCharacteristics); + USB_LOG_RAW("bPwrOn2PwrGood: 0x%02x \r\n", desc->bPwrOn2PwrGood); + USB_LOG_RAW("bHubContrCurrent: 0x%02x \r\n", desc->bHubContrCurrent); + USB_LOG_RAW("DeviceRemovable: 0x%02x \r\n", desc->DeviceRemovable); + } + return 0; +} #endif static int usbh_hub_get_portstatus(struct usbh_hub *hub, uint8_t port, struct hub_port_status *port_status) @@ -311,22 +326,65 @@ static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf) hub->hub_addr = hport->dev_addr; hub->parent = hport; hub->bus = hport->bus; + hub->speed = hport->speed; + hport->self = hub; hport->config.intf[intf].priv = hub; - ret = _usbh_hub_get_hub_descriptor(hub, (uint8_t *)&hub->hub_desc); - if (ret < 0) { - return ret; + if (hport->depth > HUB_MAX_DEPTH) { + USB_LOG_ERR("Hub depth(%d) is overflow\r\n", hport->depth); + return -USB_ERR_INVAL; } - parse_hub_descriptor(&hub->hub_desc, USB_SIZEOF_HUB_DESC); + /* + * Super-Speed hubs need to know their depth to be able to + * parse the bits of the route-string that correspond to + * their downstream port number. + * + */ + if ((hport->depth != 0) && (hport->speed == USB_SPEED_SUPER)) { + ret = usbh_hub_set_depth(hub, hport->depth - 1); + if (ret < 0) { + USB_LOG_ERR("Unable to set hub depth \r\n"); + return ret; + } + } - for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + /* Get hub descriptor. */ + if (hport->speed == USB_SPEED_SUPER) { + ret = _usbh_hub_get_hub_ss_descriptor(hub, (uint8_t *)&hub->hub_ss_desc); + if (ret < 0) { + return ret; + } + + parse_hub_ss_descriptor(&hub->hub_ss_desc, USB_SIZEOF_HUB_SS_DESC); + hub->nports = hub->hub_ss_desc.bNbrPorts; + hub->powerdelay = hub->hub_ss_desc.bPwrOn2PwrGood * 2; + hub->tt_think = 0U; + } else { + ret = _usbh_hub_get_hub_descriptor(hub, (uint8_t *)&hub->hub_desc); + if (ret < 0) { + return ret; + } + + parse_hub_descriptor(&hub->hub_desc, USB_SIZEOF_HUB_DESC); + hub->nports = hub->hub_desc.bNbrPorts; + hub->powerdelay = hub->hub_desc.bPwrOn2PwrGood * 2; + hub->tt_think = ((hub->hub_desc.wHubCharacteristics & HUB_CHAR_TTTT_MASK) >> 5); + } + + for (uint8_t port = 0; port < hub->nports; port++) { hub->child[port].port = port + 1; hub->child[port].parent = hub; hub->child[port].bus = hport->bus; } + if (hport->device_desc.bDeviceProtocol == HUB_PROTOCOL_MTT) { + hub->ismtt = 1; + } else { + hub->ismtt = 0; + } + ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc; if (ep_desc->bEndpointAddress & 0x80) { USBH_EP_INIT(hub->intin, ep_desc); @@ -334,28 +392,16 @@ static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf) return -1; } - if (hport->speed == USB_SPEED_SUPER) { - uint16_t depth = 0; - struct usbh_hubport *parent = hport->parent->parent; - while (parent) { - depth++; - parent = parent->parent->parent; - } - - ret = usbh_hub_set_depth(hub, depth); - if (ret < 0) { - return ret; - } - } - - for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + for (uint8_t port = 0; port < hub->nports; port++) { ret = usbh_hub_set_feature(hub, port + 1, HUB_PORT_FEATURE_POWER); if (ret < 0) { return ret; } } - for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + usb_osal_msleep(hub->powerdelay); + + for (uint8_t port = 0; port < hub->nports; port++) { ret = usbh_hub_get_portstatus(hub, port + 1, &port_status); USB_LOG_INFO("port %u, status:0x%02x, change:0x%02x\r\n", port + 1, port_status.wPortStatus, port_status.wPortChange); if (ret < 0) { @@ -395,7 +441,7 @@ static int usbh_hub_disconnect(struct usbh_hubport *hport, uint8_t intf) usb_osal_timer_delete(hub->int_timer); } - for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + for (uint8_t port = 0; port < hub->nports; port++) { child = &hub->child[port]; usbh_hubport_release(child); child->parent = NULL; @@ -415,7 +461,7 @@ static void usbh_hub_events(struct usbh_hub *hub) { struct usbh_hubport *child; struct hub_port_status port_status; - uint8_t portchange_index; + uint16_t portchange_index; uint16_t portstatus; uint16_t portchange; uint16_t mask; @@ -429,11 +475,10 @@ static void usbh_hub_events(struct usbh_hub *hub) } flags = usb_osal_enter_critical_section(); - portchange_index = hub->int_buffer[0]; - hub->int_buffer[0] &= ~portchange_index; + memcpy(&portchange_index, hub->int_buffer, 2); usb_osal_leave_critical_section(flags); - for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + for (uint8_t port = 0; port < hub->nports; port++) { USB_LOG_DBG("Port change:0x%02x\r\n", portchange_index); if (!(portchange_index & (1 << (port + 1)))) { @@ -539,12 +584,23 @@ static void usbh_hub_events(struct usbh_hub *hub) } } - if (portstatus & HUB_PORT_STATUS_HIGH_SPEED) { - speed = USB_SPEED_HIGH; - } else if (portstatus & HUB_PORT_STATUS_LOW_SPEED) { - speed = USB_SPEED_LOW; + /* + * Figure out device speed. This is a bit tricky because + * HUB_PORT_STATUS_POWER_SS and HUB_PORT_STATUS_LOW_SPEED share the same bit. + */ + if (portstatus & HUB_PORT_STATUS_POWER) { + if (portstatus & HUB_PORT_STATUS_HIGH_SPEED) { + speed = USB_SPEED_HIGH; + } else if (portstatus & HUB_PORT_STATUS_LOW_SPEED) { + speed = USB_SPEED_LOW; + } else { + speed = USB_SPEED_FULL; + } + } else if (portstatus & HUB_PORT_STATUS_POWER_SS) { + speed = USB_SPEED_SUPER; } else { - speed = USB_SPEED_FULL; + USB_LOG_WRN("Port %u does not enable power\r\n", port + 1); + continue; } child = &hub->child[port]; @@ -553,6 +609,7 @@ static void usbh_hub_events(struct usbh_hub *hub) memset(child, 0, sizeof(struct usbh_hubport)); child->parent = hub; + child->depth = (hub->parent ? hub->parent->depth : 0) + 1; child->connected = true; child->port = port + 1; child->speed = speed; @@ -624,7 +681,7 @@ int usbh_hub_initialize(struct usbh_bus *bus) hub->is_roothub = true; hub->parent = NULL; hub->hub_addr = 1; - hub->hub_desc.bNbrPorts = CONFIG_USBHOST_MAX_RHPORTS; + hub->nports = CONFIG_USBHOST_MAX_RHPORTS; hub->int_buffer = bus->hcd.roothub_intbuf; hub->bus = bus; @@ -652,7 +709,7 @@ int usbh_hub_deinitialize(struct usbh_bus *bus) flags = usb_osal_enter_critical_section(); hub = &bus->hcd.roothub; - for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + for (uint8_t port = 0; port < hub->nports; port++) { hport = &hub->child[port]; usbh_hubport_release(hport); @@ -677,9 +734,9 @@ const struct usbh_class_driver hub_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info hub_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS, - .class = USB_DEVICE_CLASS_HUB, - .subclass = 0, - .protocol = 0, + .bInterfaceClass = USB_DEVICE_CLASS_HUB, + .bInterfaceSubClass = 0, + .bInterfaceProtocol = 0, .id_table = NULL, .class_driver = &hub_class_driver }; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/hub/usbh_hub.h b/rt-thread/components/drivers/usb/cherryusb/class/hub/usbh_hub.h index 1f34c53..dcce660 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/hub/usbh_hub.h +++ b/rt-thread/components/drivers/usb/cherryusb/class/hub/usbh_hub.h @@ -10,10 +10,6 @@ struct usbh_hub; -#define USBH_HUB_MAX_PORTS 4 -/* Maximum size of an interrupt IN transfer */ -#define USBH_HUB_INTIN_BUFSIZE ((USBH_HUB_MAX_PORTS + 8) >> 3) - #ifdef __cplusplus extern "C" { #endif diff --git a/rt-thread/components/drivers/usb/cherryusb/class/msc/usbd_msc.c b/rt-thread/components/drivers/usb/cherryusb/class/msc/usbd_msc.c index 055cdc4..1f84d02 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/msc/usbd_msc.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/msc/usbd_msc.c @@ -9,6 +9,8 @@ #include "usb_scsi.h" #if defined(CONFIG_USBDEV_MSC_THREAD) #include "usb_osal.h" +#elif defined(CONFIG_USBDEV_MSC_POLLING) +#include "chry_ringbuffer.h" #endif #define MSD_OUT_EP_IDX 0 @@ -50,6 +52,10 @@ USB_NOCACHE_RAM_SECTION struct usbd_msc_priv { usb_osal_mq_t usbd_msc_mq; usb_osal_thread_t usbd_msc_thread; uint32_t nbytes; +#elif defined(CONFIG_USBDEV_MSC_POLLING) + chry_ringbuffer_t msc_rb; + uint8_t msc_rb_pool[2]; + uint32_t nbytes; #endif } g_usbd_msc[CONFIG_USBDEV_MAX_BUS]; @@ -94,21 +100,25 @@ static int msc_storage_class_interface_request_handler(uint8_t busid, struct usb void msc_storage_notify_handler(uint8_t busid, uint8_t event, void *arg) { + (void)arg; + switch (event) { case USBD_EVENT_INIT: -#ifdef CONFIG_USBDEV_MSC_THREAD +#if defined(CONFIG_USBDEV_MSC_THREAD) g_usbd_msc[busid].usbd_msc_mq = usb_osal_mq_create(1); if (g_usbd_msc[busid].usbd_msc_mq == NULL) { USB_LOG_ERR("No memory to alloc for g_usbd_msc[busid].usbd_msc_mq\r\n"); } - g_usbd_msc[busid].usbd_msc_thread = usb_osal_thread_create("usbd_msc", CONFIG_USBDEV_MSC_STACKSIZE, CONFIG_USBDEV_MSC_PRIO, usbdev_msc_thread, (void *)busid); + g_usbd_msc[busid].usbd_msc_thread = usb_osal_thread_create("usbd_msc", CONFIG_USBDEV_MSC_STACKSIZE, CONFIG_USBDEV_MSC_PRIO, usbdev_msc_thread, (void *)(uint32_t)busid); if (g_usbd_msc[busid].usbd_msc_thread == NULL) { USB_LOG_ERR("No memory to alloc for g_usbd_msc[busid].usbd_msc_thread\r\n"); } +#elif defined(CONFIG_USBDEV_MSC_POLLING) + chry_ringbuffer_init(&g_usbd_msc[busid].msc_rb, g_usbd_msc[busid].msc_rb_pool, sizeof(g_usbd_msc[busid].msc_rb_pool)); #endif break; case USBD_EVENT_DEINIT: -#ifdef CONFIG_USBDEV_MSC_THREAD +#if defined(CONFIG_USBDEV_MSC_THREAD) if (g_usbd_msc[busid].usbd_msc_mq) { usb_osal_mq_delete(g_usbd_msc[busid].usbd_msc_mq); } @@ -500,6 +510,9 @@ static bool SCSI_readCapacity10(uint8_t busid, uint8_t **data, uint32_t *len) static bool SCSI_read10(uint8_t busid, uint8_t **data, uint32_t *len) { + (void)data; + (void)len; + if (((g_usbd_msc[busid].cbw.bmFlags & 0x80U) != 0x80U) || (g_usbd_msc[busid].cbw.dDataLength == 0U)) { SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); return false; @@ -522,9 +535,12 @@ static bool SCSI_read10(uint8_t busid, uint8_t **data, uint32_t *len) return false; } g_usbd_msc[busid].stage = MSC_DATA_IN; -#ifdef CONFIG_USBDEV_MSC_THREAD +#if defined(CONFIG_USBDEV_MSC_THREAD) usb_osal_mq_send(g_usbd_msc[busid].usbd_msc_mq, MSC_DATA_IN); return true; +#elif defined(CONFIG_USBDEV_MSC_POLLING) + chry_ringbuffer_write_byte(&g_usbd_msc[busid].msc_rb, MSC_DATA_IN); + return true; #else return SCSI_processRead(busid); #endif @@ -532,6 +548,9 @@ static bool SCSI_read10(uint8_t busid, uint8_t **data, uint32_t *len) static bool SCSI_read12(uint8_t busid, uint8_t **data, uint32_t *len) { + (void)data; + (void)len; + if (((g_usbd_msc[busid].cbw.bmFlags & 0x80U) != 0x80U) || (g_usbd_msc[busid].cbw.dDataLength == 0U)) { SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); return false; @@ -554,9 +573,12 @@ static bool SCSI_read12(uint8_t busid, uint8_t **data, uint32_t *len) return false; } g_usbd_msc[busid].stage = MSC_DATA_IN; -#ifdef CONFIG_USBDEV_MSC_THREAD +#if defined(CONFIG_USBDEV_MSC_THREAD) usb_osal_mq_send(g_usbd_msc[busid].usbd_msc_mq, MSC_DATA_IN); return true; +#elif defined(CONFIG_USBDEV_MSC_POLLING) + chry_ringbuffer_write_byte(&g_usbd_msc[busid].msc_rb, MSC_DATA_IN); + return true; #else return SCSI_processRead(busid); #endif @@ -565,6 +587,10 @@ static bool SCSI_read12(uint8_t busid, uint8_t **data, uint32_t *len) static bool SCSI_write10(uint8_t busid, uint8_t **data, uint32_t *len) { uint32_t data_len = 0; + + (void)data; + (void)len; + if (((g_usbd_msc[busid].cbw.bmFlags & 0x80U) != 0x00U) || (g_usbd_msc[busid].cbw.dDataLength == 0U)) { SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); return false; @@ -594,6 +620,10 @@ static bool SCSI_write10(uint8_t busid, uint8_t **data, uint32_t *len) static bool SCSI_write12(uint8_t busid, uint8_t **data, uint32_t *len) { uint32_t data_len = 0; + + (void)data; + (void)len; + if (((g_usbd_msc[busid].cbw.bmFlags & 0x80U) != 0x00U) || (g_usbd_msc[busid].cbw.dDataLength == 0U)) { SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); return false; @@ -803,6 +833,8 @@ static bool SCSI_CBWDecode(uint8_t busid, uint32_t nbytes) void mass_storage_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) { + (void)ep; + switch (g_usbd_msc[busid].stage) { case MSC_READ_CBW: if (SCSI_CBWDecode(busid, nbytes) == false) { @@ -815,9 +847,12 @@ void mass_storage_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) switch (g_usbd_msc[busid].cbw.CB[0]) { case SCSI_CMD_WRITE10: case SCSI_CMD_WRITE12: -#ifdef CONFIG_USBDEV_MSC_THREAD +#if defined(CONFIG_USBDEV_MSC_THREAD) g_usbd_msc[busid].nbytes = nbytes; usb_osal_mq_send(g_usbd_msc[busid].usbd_msc_mq, MSC_DATA_OUT); +#elif defined(CONFIG_USBDEV_MSC_POLLING) + g_usbd_msc[busid].nbytes = nbytes; + chry_ringbuffer_write_byte(&g_usbd_msc[busid].msc_rb, MSC_DATA_OUT); #else if (SCSI_processWrite(busid, nbytes) == false) { usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ @@ -835,13 +870,18 @@ void mass_storage_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) void mass_storage_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) { + (void)ep; + (void)nbytes; + switch (g_usbd_msc[busid].stage) { case MSC_DATA_IN: switch (g_usbd_msc[busid].cbw.CB[0]) { case SCSI_CMD_READ10: case SCSI_CMD_READ12: -#ifdef CONFIG_USBDEV_MSC_THREAD +#if defined(CONFIG_USBDEV_MSC_THREAD) usb_osal_mq_send(g_usbd_msc[busid].usbd_msc_mq, MSC_DATA_IN); +#elif defined(CONFIG_USBDEV_MSC_POLLING) + chry_ringbuffer_write_byte(&g_usbd_msc[busid].msc_rb, MSC_DATA_IN); #else if (SCSI_processRead(busid) == false) { usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ @@ -870,19 +910,38 @@ void mass_storage_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) } } -#ifdef CONFIG_USBDEV_MSC_THREAD +#if defined(CONFIG_USBDEV_MSC_THREAD) static void usbdev_msc_thread(void *argument) { uintptr_t event; int ret; - uint8_t busid = (uint8_t)argument; + uint8_t busid = (uint8_t)(uint32_t)argument; while (1) { ret = usb_osal_mq_recv(g_usbd_msc[busid].usbd_msc_mq, (uintptr_t *)&event, USB_OSAL_WAITING_FOREVER); if (ret < 0) { continue; } - USB_LOG_DBG("%d\r\n", event); + USB_LOG_DBG("event:%d\r\n", event); + if (event == MSC_DATA_OUT) { + if (SCSI_processWrite(busid, g_usbd_msc[busid].nbytes) == false) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ + } + } else if (event == MSC_DATA_IN) { + if (SCSI_processRead(busid) == false) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ + } + } else { + } + } +} +#elif defined(CONFIG_USBDEV_MSC_POLLING) +void usbd_msc_polling(uint8_t busid) +{ + uint8_t event; + + if (chry_ringbuffer_read_byte(&g_usbd_msc[busid].msc_rb, &event)) { + USB_LOG_DBG("event:%d\r\n", event); if (event == MSC_DATA_OUT) { if (SCSI_processWrite(busid, g_usbd_msc[busid].nbytes) == false) { usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ @@ -918,9 +977,9 @@ struct usbd_interface *usbd_msc_init_intf(uint8_t busid, struct usbd_interface * for (uint8_t i = 0u; i <= g_usbd_msc[busid].max_lun; i++) { usbd_msc_get_cap(busid, i, &g_usbd_msc[busid].scsi_blk_nbr[i], &g_usbd_msc[busid].scsi_blk_size[i]); - if (g_usbd_msc[busid].scsi_blk_size[i] > CONFIG_USBDEV_MSC_MAX_BUFSIZE) { - USB_LOG_ERR("msc block buffer overflow\r\n"); - return NULL; + if (CONFIG_USBDEV_MSC_MAX_BUFSIZE % g_usbd_msc[busid].scsi_blk_size[i]) { + USB_LOG_ERR("CONFIG_USBDEV_MSC_MAX_BUFSIZE must be a multiple of block size\r\n"); + while(1){} } } @@ -932,7 +991,7 @@ void usbd_msc_set_readonly(uint8_t busid, bool readonly) g_usbd_msc[busid].readonly = readonly; } -bool usbd_msc_set_popup(uint8_t busid) +bool usbd_msc_get_popup(uint8_t busid) { return g_usbd_msc[busid].popup; } diff --git a/rt-thread/components/drivers/usb/cherryusb/class/msc/usbd_msc.h b/rt-thread/components/drivers/usb/cherryusb/class/msc/usbd_msc.h index c71f64a..63a8752 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/msc/usbd_msc.h +++ b/rt-thread/components/drivers/usb/cherryusb/class/msc/usbd_msc.h @@ -23,7 +23,9 @@ int usbd_msc_sector_read(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *b int usbd_msc_sector_write(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length); void usbd_msc_set_readonly(uint8_t busid, bool readonly); -bool usbd_msc_set_popup(uint8_t busid); +bool usbd_msc_get_popup(uint8_t busid); + +void usbd_msc_polling(uint8_t busid); #ifdef __cplusplus } diff --git a/rt-thread/components/drivers/usb/cherryusb/class/msc/usbh_msc.c b/rt-thread/components/drivers/usb/cherryusb/class/msc/usbh_msc.c index 42e12d9..96cb53d 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/msc/usbh_msc.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/msc/usbh_msc.c @@ -15,7 +15,7 @@ #define MSC_INQUIRY_TIMEOUT 500 -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_msc_buf[64]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_msc_buf[CONFIG_USBHOST_MAX_MSC_CLASS][USB_ALIGN_UP(64, CONFIG_USB_ALIGN_SIZE)]; static struct usbh_msc g_msc_class[CONFIG_USBHOST_MAX_MSC_CLASS]; static uint32_t g_devinuse = 0; @@ -23,11 +23,11 @@ static struct usbh_msc_modeswitch_config *g_msc_modeswitch_config = NULL; static struct usbh_msc *usbh_msc_class_alloc(void) { - int devno; + uint8_t devno; for (devno = 0; devno < CONFIG_USBHOST_MAX_MSC_CLASS; devno++) { - if ((g_devinuse & (1 << devno)) == 0) { - g_devinuse |= (1 << devno); + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); memset(&g_msc_class[devno], 0, sizeof(struct usbh_msc)); g_msc_class[devno].sdchar = 'a' + devno; return &g_msc_class[devno]; @@ -38,10 +38,10 @@ static struct usbh_msc *usbh_msc_class_alloc(void) static void usbh_msc_class_free(struct usbh_msc *msc_class) { - int devno = msc_class->sdchar - 'a'; + uint8_t devno = msc_class->sdchar - 'a'; - if (devno >= 0 && devno < 32) { - g_devinuse &= ~(1 << devno); + if (devno < 32) { + g_devinuse &= ~(1U << devno); } memset(msc_class, 0, sizeof(struct usbh_msc)); } @@ -87,6 +87,8 @@ static void usbh_msc_cbw_dump(struct CBW *cbw) static void usbh_msc_csw_dump(struct CSW *csw) { + (void)csw; + USB_LOG_DBG("CSW:\r\n"); USB_LOG_DBG(" signature: 0x%08x\r\n", (unsigned int)csw->dSignature); USB_LOG_DBG(" tag: 0x%08x\r\n", (unsigned int)csw->dTag); @@ -182,14 +184,14 @@ static inline int usbh_msc_scsi_testunitready(struct usbh_msc *msc_class) struct CBW *cbw; /* Construct the CBW */ - cbw = (struct CBW *)g_msc_buf; + cbw = (struct CBW *)g_msc_buf[msc_class->sdchar - 'a']; memset(cbw, 0, USB_SIZEOF_MSC_CBW); cbw->dSignature = MSC_CBW_Signature; cbw->bCBLength = SCSICMD_TESTUNITREADY_SIZEOF; cbw->CB[0] = SCSI_CMD_TESTUNITREADY; - return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, NULL, MSC_INQUIRY_TIMEOUT); + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf[msc_class->sdchar - 'a'], NULL, MSC_INQUIRY_TIMEOUT); } static inline int usbh_msc_scsi_requestsense(struct usbh_msc *msc_class) @@ -197,7 +199,7 @@ static inline int usbh_msc_scsi_requestsense(struct usbh_msc *msc_class) struct CBW *cbw; /* Construct the CBW */ - cbw = (struct CBW *)g_msc_buf; + cbw = (struct CBW *)g_msc_buf[msc_class->sdchar - 'a']; memset(cbw, 0, USB_SIZEOF_MSC_CBW); cbw->dSignature = MSC_CBW_Signature; @@ -207,7 +209,7 @@ static inline int usbh_msc_scsi_requestsense(struct usbh_msc *msc_class) cbw->CB[0] = SCSI_CMD_REQUESTSENSE; cbw->CB[4] = SCSIRESP_FIXEDSENSEDATA_SIZEOF; - return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, g_msc_buf, MSC_INQUIRY_TIMEOUT); + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf[msc_class->sdchar - 'a'], g_msc_buf[msc_class->sdchar - 'a'], MSC_INQUIRY_TIMEOUT); } static inline int usbh_msc_scsi_inquiry(struct usbh_msc *msc_class) @@ -215,7 +217,7 @@ static inline int usbh_msc_scsi_inquiry(struct usbh_msc *msc_class) struct CBW *cbw; /* Construct the CBW */ - cbw = (struct CBW *)g_msc_buf; + cbw = (struct CBW *)g_msc_buf[msc_class->sdchar - 'a']; memset(cbw, 0, USB_SIZEOF_MSC_CBW); cbw->dSignature = MSC_CBW_Signature; @@ -225,7 +227,7 @@ static inline int usbh_msc_scsi_inquiry(struct usbh_msc *msc_class) cbw->CB[0] = SCSI_CMD_INQUIRY; cbw->CB[4] = SCSIRESP_INQUIRY_SIZEOF; - return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, g_msc_buf, MSC_INQUIRY_TIMEOUT); + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf[msc_class->sdchar - 'a'], g_msc_buf[msc_class->sdchar - 'a'], MSC_INQUIRY_TIMEOUT); } static inline int usbh_msc_scsi_readcapacity10(struct usbh_msc *msc_class) @@ -233,7 +235,7 @@ static inline int usbh_msc_scsi_readcapacity10(struct usbh_msc *msc_class) struct CBW *cbw; /* Construct the CBW */ - cbw = (struct CBW *)g_msc_buf; + cbw = (struct CBW *)g_msc_buf[msc_class->sdchar - 'a']; memset(cbw, 0, USB_SIZEOF_MSC_CBW); cbw->dSignature = MSC_CBW_Signature; @@ -242,7 +244,7 @@ static inline int usbh_msc_scsi_readcapacity10(struct usbh_msc *msc_class) cbw->bCBLength = SCSICMD_READCAPACITY10_SIZEOF; cbw->CB[0] = SCSI_CMD_READCAPACITY10; - return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, g_msc_buf, MSC_INQUIRY_TIMEOUT); + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf[msc_class->sdchar - 'a'], g_msc_buf[msc_class->sdchar - 'a'], MSC_INQUIRY_TIMEOUT); } static inline void usbh_msc_modeswitch(struct usbh_msc *msc_class, const uint8_t *message) @@ -250,11 +252,11 @@ static inline void usbh_msc_modeswitch(struct usbh_msc *msc_class, const uint8_t struct CBW *cbw; /* Construct the CBW */ - cbw = (struct CBW *)g_msc_buf; + cbw = (struct CBW *)g_msc_buf[msc_class->sdchar - 'a']; - memcpy(g_msc_buf, message, 31); + memcpy(g_msc_buf[msc_class->sdchar - 'a'], message, 31); - usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, NULL, MSC_INQUIRY_TIMEOUT); + usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf[msc_class->sdchar - 'a'], NULL, MSC_INQUIRY_TIMEOUT); } static int usbh_msc_connect(struct usbh_hubport *hport, uint8_t intf) @@ -274,12 +276,17 @@ static int usbh_msc_connect(struct usbh_hubport *hport, uint8_t intf) hport->config.intf[intf].priv = msc_class; - ret = usbh_msc_get_maxlun(msc_class, g_msc_buf); + ret = usbh_msc_get_maxlun(msc_class, g_msc_buf[msc_class->sdchar - 'a']); if (ret < 0) { - return ret; + if (ret == -USB_ERR_STALL) { + USB_LOG_WRN("Device does not support multiple LUNs\r\n"); + g_msc_buf[msc_class->sdchar - 'a'][0] = 0; + } else { + return ret; + } } - USB_LOG_INFO("Get max LUN:%u\r\n", g_msc_buf[0] + 1); + USB_LOG_INFO("Get max LUN:%u\r\n", g_msc_buf[msc_class->sdchar - 'a'][0] + 1); for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; @@ -370,13 +377,12 @@ static int usbh_msc_disconnect(struct usbh_hubport *hport, uint8_t intf) return ret; } - int usbh_msc_scsi_write10(struct usbh_msc *msc_class, uint32_t start_sector, const uint8_t *buffer, uint32_t nsectors) { struct CBW *cbw; /* Construct the CBW */ - cbw = (struct CBW *)g_msc_buf; + cbw = (struct CBW *)g_msc_buf[msc_class->sdchar - 'a']; memset(cbw, 0, USB_SIZEOF_MSC_CBW); cbw->dSignature = MSC_CBW_Signature; @@ -387,7 +393,7 @@ int usbh_msc_scsi_write10(struct usbh_msc *msc_class, uint32_t start_sector, con SET_BE32(&cbw->CB[2], start_sector); SET_BE16(&cbw->CB[7], nsectors); - return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, (uint8_t *)buffer, CONFIG_USBHOST_MSC_TIMEOUT); + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf[msc_class->sdchar - 'a'], (uint8_t *)buffer, CONFIG_USBHOST_MSC_TIMEOUT); } int usbh_msc_scsi_read10(struct usbh_msc *msc_class, uint32_t start_sector, const uint8_t *buffer, uint32_t nsectors) @@ -395,7 +401,7 @@ int usbh_msc_scsi_read10(struct usbh_msc *msc_class, uint32_t start_sector, cons struct CBW *cbw; /* Construct the CBW */ - cbw = (struct CBW *)g_msc_buf; + cbw = (struct CBW *)g_msc_buf[msc_class->sdchar - 'a']; memset(cbw, 0, USB_SIZEOF_MSC_CBW); cbw->dSignature = MSC_CBW_Signature; @@ -407,7 +413,7 @@ int usbh_msc_scsi_read10(struct usbh_msc *msc_class, uint32_t start_sector, cons SET_BE32(&cbw->CB[2], start_sector); SET_BE16(&cbw->CB[7], nsectors); - return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, (uint8_t *)buffer, CONFIG_USBHOST_MSC_TIMEOUT); + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf[msc_class->sdchar - 'a'], (uint8_t *)buffer, CONFIG_USBHOST_MSC_TIMEOUT); } void usbh_msc_modeswitch_enable(struct usbh_msc_modeswitch_config *config) @@ -421,10 +427,12 @@ void usbh_msc_modeswitch_enable(struct usbh_msc_modeswitch_config *config) __WEAK void usbh_msc_run(struct usbh_msc *msc_class) { + (void)msc_class; } __WEAK void usbh_msc_stop(struct usbh_msc *msc_class) { + (void)msc_class; } const struct usbh_class_driver msc_class_driver = { @@ -435,9 +443,9 @@ const struct usbh_class_driver msc_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info msc_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, - .class = USB_DEVICE_CLASS_MASS_STORAGE, - .subclass = MSC_SUBCLASS_SCSI, - .protocol = MSC_PROTOCOL_BULK_ONLY, + .bInterfaceClass = USB_DEVICE_CLASS_MASS_STORAGE, + .bInterfaceSubClass = MSC_SUBCLASS_SCSI, + .bInterfaceProtocol = MSC_PROTOCOL_BULK_ONLY, .id_table = NULL, .class_driver = &msc_class_driver }; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/template/usbh_xxx.c b/rt-thread/components/drivers/usb/cherryusb/class/template/usbh_xxx.c index 22b3636..4456b3c 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/template/usbh_xxx.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/template/usbh_xxx.c @@ -9,11 +9,11 @@ static uint32_t g_devinuse = 0; static struct usbh_xxx *usbh_xxx_class_alloc(void) { - int devno; + uint8_t devno; for (devno = 0; devno < CONFIG_USBHOST_MAX_CUSTOM_CLASS; devno++) { - if ((g_devinuse & (1 << devno)) == 0) { - g_devinuse |= (1 << devno); + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); memset(&g_xxx_class[devno], 0, sizeof(struct usbh_xxx)); g_xxx_class[devno].minor = devno; return &g_xxx_class[devno]; @@ -24,10 +24,10 @@ static struct usbh_xxx *usbh_xxx_class_alloc(void) static void usbh_xxx_class_free(struct usbh_xxx *xxx_class) { - int devno = xxx_class->minor; + uint8_t devno = xxx_class->minor; - if (devno >= 0 && devno < 32) { - g_devinuse &= ~(1 << devno); + if (devno < 32) { + g_devinuse &= ~(1U << devno); } memset(xxx_class, 0, sizeof(struct usbh_xxx)); } @@ -89,9 +89,9 @@ static const struct usbh_class_driver xxx_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info xxx_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, - .class = 0, - .subclass = 0, - .protocol = 0, + .bInterfaceClass = 0, + .bInterfaceSubClass = 0, + .bInterfaceProtocol = 0, .id_table = NULL, .class_driver = &xxx_class_driver }; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.c b/rt-thread/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.c index 9d3e973..66c1f07 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.c @@ -70,7 +70,7 @@ static int usbh_asix_read_cmd(struct usbh_asix *asix_class, setup->wLength = size; ret = usbh_control_transfer(asix_class->hport, setup, g_asix_buf); - if (ret < 0) { + if (ret < 8) { return ret; } memcpy(data, g_asix_buf, ret - 8); @@ -98,9 +98,12 @@ static int usbh_asix_write_cmd(struct usbh_asix *asix_class, setup->wIndex = index; setup->wLength = size; - memcpy(g_asix_buf, data, size); - - return usbh_control_transfer(asix_class->hport, setup, g_asix_buf); + if (data && size) { + memcpy(g_asix_buf, data, size); + return usbh_control_transfer(asix_class->hport, setup, g_asix_buf); + } else { + return usbh_control_transfer(asix_class->hport, setup, NULL); + } } static int usbh_asix_mdio_write(struct usbh_asix *asix_class, int phy_id, int loc, int val) @@ -680,6 +683,7 @@ void usbh_asix_rx_thread(void *argument) uint32_t transfer_size = (16 * 1024); #endif + (void)argument; USB_LOG_INFO("Create asix rx thread\r\n"); // clang-format off find_class: @@ -742,7 +746,7 @@ find_class: #else if ((g_asix_rx_length + (16 * 1024)) > CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE) { #endif - USB_LOG_ERR("Rx packet is overflow, please ruduce tcp window size or increase CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE\r\n"); + USB_LOG_ERR("Rx packet is overflow, please reduce tcp window size or increase CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE\r\n"); while (1) { } } @@ -791,10 +795,12 @@ int usbh_asix_eth_output(uint32_t buflen) __WEAK void usbh_asix_run(struct usbh_asix *asix_class) { + (void)asix_class; } __WEAK void usbh_asix_stop(struct usbh_asix *asix_class) { + (void)asix_class; } static const uint16_t asix_id_table[][2] = { @@ -811,9 +817,9 @@ static const struct usbh_class_driver asix_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info asix_class_info = { .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, - .class = 0xff, - .subclass = 0x00, - .protocol = 0x00, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, .id_table = asix_id_table, .class_driver = &asix_class_driver }; \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.c b/rt-thread/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.c index dde665d..10fc048 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.c @@ -961,7 +961,7 @@ static int usbh_rtl8152_read_regs(struct usbh_rtl8152 *rtl8152_class, setup->wLength = size; ret = usbh_control_transfer(rtl8152_class->hport, setup, g_rtl8152_buf); - if (ret < 0) { + if (ret < 8) { return ret; } memcpy(data, g_rtl8152_buf, ret - 8); @@ -997,9 +997,10 @@ static int generic_ocp_read(struct usbh_rtl8152 *tp, uint16_t index, uint16_t si { uint16_t limit = 64; int ret = 0; + uint8_t *buf = data; /* both size and indix must be 4 bytes align */ - if ((size & 3) || !size || (index & 3) || !data) + if ((size & 3) || !size || (index & 3) || !buf) return -USB_ERR_INVAL; if ((uint32_t)index + (uint32_t)size > 0xffff) @@ -1007,20 +1008,20 @@ static int generic_ocp_read(struct usbh_rtl8152 *tp, uint16_t index, uint16_t si while (size) { if (size > limit) { - ret = usbh_rtl8152_read_regs(tp, index, type, limit, data); + ret = usbh_rtl8152_read_regs(tp, index, type, limit, buf); if (ret < 0) break; index += limit; - data += limit; + buf += limit; size -= limit; } else { - ret = usbh_rtl8152_read_regs(tp, index, type, size, data); + ret = usbh_rtl8152_read_regs(tp, index, type, size, buf); if (ret < 0) break; index += size; - data += size; + buf += size; size = 0; break; } @@ -1035,9 +1036,10 @@ static int generic_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t b int ret; uint16_t byteen_start, byteen_end, byen; uint16_t limit = 512; + uint8_t *buf = data; /* both size and indix must be 4 bytes align */ - if ((size & 3) || !size || (index & 3) || !data) + if ((size & 3) || !size || (index & 3) || !buf) return -USB_ERR_INVAL; if ((uint32_t)index + (uint32_t)size > 0xffff) @@ -1050,12 +1052,12 @@ static int generic_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t b /* Split the first DWORD if the byte_en is not 0xff */ if (byen != BYTE_EN_DWORD) { - ret = usbh_rtl8152_write_regs(tp, index, type | byen, 4, data); + ret = usbh_rtl8152_write_regs(tp, index, type | byen, 4, buf); if (ret < 0) goto error1; index += 4; - data += 4; + buf += 4; size -= 4; } @@ -1070,22 +1072,22 @@ static int generic_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t b if (size > limit) { ret = usbh_rtl8152_write_regs(tp, index, type | BYTE_EN_DWORD, - limit, data); + limit, buf); if (ret < 0) goto error1; index += limit; - data += limit; + buf += limit; size -= limit; } else { ret = usbh_rtl8152_write_regs(tp, index, type | BYTE_EN_DWORD, - size, data); + size, buf); if (ret < 0) goto error1; index += size; - data += size; + buf += size; size = 0; break; } @@ -1093,7 +1095,7 @@ static int generic_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t b /* Set the last DWORD */ if (byen != BYTE_EN_DWORD) - ret = usbh_rtl8152_write_regs(tp, index, type | byen, 4, data); + ret = usbh_rtl8152_write_regs(tp, index, type | byen, 4, buf); } error1: @@ -2140,6 +2142,7 @@ void usbh_rtl8152_rx_thread(void *argument) uint32_t transfer_size = (16 * 1024); #endif + (void)argument; USB_LOG_INFO("Create rtl8152 rx thread\r\n"); // clang-format off find_class: @@ -2210,7 +2213,7 @@ find_class: #else if ((g_rtl8152_rx_length + (16 * 1024)) > CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE) { #endif - USB_LOG_ERR("Rx packet is overflow, please ruduce tcp window size or increase CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE\r\n"); + USB_LOG_ERR("Rx packet is overflow, please reduce tcp window size or increase CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE\r\n"); while (1) { } } @@ -2248,10 +2251,12 @@ int usbh_rtl8152_eth_output(uint32_t buflen) __WEAK void usbh_rtl8152_run(struct usbh_rtl8152 *rtl8152_class) { + (void)rtl8152_class; } __WEAK void usbh_rtl8152_stop(struct usbh_rtl8152 *rtl8152_class) { + (void)rtl8152_class; } static const uint16_t rtl_id_table[][2] = { @@ -2267,9 +2272,9 @@ static const struct usbh_class_driver rtl8152_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info rtl8152_class_info = { .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, - .class = 0xff, - .subclass = 0x00, - .protocol = 0x00, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, .id_table = rtl_id_table, .class_driver = &rtl8152_class_driver }; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.c b/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.c index 7c275e1..3bee462 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.c @@ -17,11 +17,11 @@ static uint32_t g_devinuse = 0; static struct usbh_ch34x *usbh_ch34x_class_alloc(void) { - int devno; + uint8_t devno; for (devno = 0; devno < CONFIG_USBHOST_MAX_CP210X_CLASS; devno++) { - if ((g_devinuse & (1 << devno)) == 0) { - g_devinuse |= (1 << devno); + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); memset(&g_ch34x_class[devno], 0, sizeof(struct usbh_ch34x)); g_ch34x_class[devno].minor = devno; return &g_ch34x_class[devno]; @@ -32,10 +32,10 @@ static struct usbh_ch34x *usbh_ch34x_class_alloc(void) static void usbh_ch34x_class_free(struct usbh_ch34x *ch34x_class) { - int devno = ch34x_class->minor; + uint8_t devno = ch34x_class->minor; - if (devno >= 0 && devno < 32) { - g_devinuse &= ~(1 << devno); + if (devno < 32) { + g_devinuse &= ~(1U << devno); } memset(ch34x_class, 0, sizeof(struct usbh_ch34x)); } @@ -349,10 +349,12 @@ int usbh_ch34x_bulk_out_transfer(struct usbh_ch34x *ch34x_class, uint8_t *buffer __WEAK void usbh_ch34x_run(struct usbh_ch34x *ch34x_class) { + (void)ch34x_class; } __WEAK void usbh_ch34x_stop(struct usbh_ch34x *ch34x_class) { + (void)ch34x_class; } static const uint16_t ch34x_id_table[][2] = { @@ -368,9 +370,9 @@ const struct usbh_class_driver ch34x_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info ch34x_class_info = { .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, - .class = 0xff, - .subclass = 0x00, - .protocol = 0x00, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, .id_table = ch34x_id_table, .class_driver = &ch34x_class_driver }; \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.c b/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.c index ae882fb..6f41b41 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.c @@ -10,18 +10,18 @@ USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cp210x_buf[64]; -#define CONFIG_USBHOST_MAX_CP210X_CLASS 4 +#define CONFIG_USBHOST_MAX_CP210X_CLASS 1 static struct usbh_cp210x g_cp210x_class[CONFIG_USBHOST_MAX_CP210X_CLASS]; static uint32_t g_devinuse = 0; static struct usbh_cp210x *usbh_cp210x_class_alloc(void) { - int devno; + uint8_t devno; for (devno = 0; devno < CONFIG_USBHOST_MAX_CP210X_CLASS; devno++) { - if ((g_devinuse & (1 << devno)) == 0) { - g_devinuse |= (1 << devno); + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); memset(&g_cp210x_class[devno], 0, sizeof(struct usbh_cp210x)); g_cp210x_class[devno].minor = devno; return &g_cp210x_class[devno]; @@ -32,10 +32,10 @@ static struct usbh_cp210x *usbh_cp210x_class_alloc(void) static void usbh_cp210x_class_free(struct usbh_cp210x *cp210x_class) { - int devno = cp210x_class->minor; + uint8_t devno = cp210x_class->minor; - if (devno >= 0 && devno < 32) { - g_devinuse &= ~(1 << devno); + if (devno < 32) { + g_devinuse &= ~(1U << devno); } memset(cp210x_class, 0, sizeof(struct usbh_cp210x)); } @@ -298,10 +298,12 @@ int usbh_cp210x_bulk_out_transfer(struct usbh_cp210x *cp210x_class, uint8_t *buf __WEAK void usbh_cp210x_run(struct usbh_cp210x *cp210x_class) { + (void)cp210x_class; } __WEAK void usbh_cp210x_stop(struct usbh_cp210x *cp210x_class) { + (void)cp210x_class; } static const uint16_t cp210x_id_table[][2] = { @@ -317,9 +319,9 @@ const struct usbh_class_driver cp210x_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info cp210x_class_info = { .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, - .class = 0xff, - .subclass = 0x00, - .protocol = 0x00, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, .id_table = cp210x_id_table, .class_driver = &cp210x_class_driver }; \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.c b/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.c index ba5aae5..82defaa 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.c @@ -10,18 +10,18 @@ USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_ftdi_buf[64]; -#define CONFIG_USBHOST_MAX_FTDI_CLASS 4 +#define CONFIG_USBHOST_MAX_FTDI_CLASS 1 static struct usbh_ftdi g_ftdi_class[CONFIG_USBHOST_MAX_FTDI_CLASS]; static uint32_t g_devinuse = 0; static struct usbh_ftdi *usbh_ftdi_class_alloc(void) { - int devno; + uint8_t devno; for (devno = 0; devno < CONFIG_USBHOST_MAX_FTDI_CLASS; devno++) { - if ((g_devinuse & (1 << devno)) == 0) { - g_devinuse |= (1 << devno); + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); memset(&g_ftdi_class[devno], 0, sizeof(struct usbh_ftdi)); g_ftdi_class[devno].minor = devno; return &g_ftdi_class[devno]; @@ -32,10 +32,10 @@ static struct usbh_ftdi *usbh_ftdi_class_alloc(void) static void usbh_ftdi_class_free(struct usbh_ftdi *ftdi_class) { - int devno = ftdi_class->minor; + uint8_t devno = ftdi_class->minor; - if (devno >= 0 && devno < 32) { - g_devinuse &= ~(1 << devno); + if (devno < 32) { + g_devinuse &= ~(1U << devno); } memset(ftdi_class, 0, sizeof(struct usbh_ftdi)); } @@ -57,7 +57,7 @@ static void usbh_ftdi_caculate_baudrate(uint32_t *itdf_divisor, uint32_t actual_ } int divisor = FTDI_USB_CLK / baudrate; int frac_bits = 0; - for (int i = 0; i < sizeof(frac) / sizeof(frac[0]); i++) { + for (uint8_t i = 0; i < sizeof(frac) / sizeof(frac[0]); i++) { if ((divisor & 0xF) == frac[i]) { frac_bits = i; break; @@ -370,10 +370,12 @@ int usbh_ftdi_bulk_out_transfer(struct usbh_ftdi *ftdi_class, uint8_t *buffer, u __WEAK void usbh_ftdi_run(struct usbh_ftdi *ftdi_class) { + (void)ftdi_class; } __WEAK void usbh_ftdi_stop(struct usbh_ftdi *ftdi_class) { + (void)ftdi_class; } static const uint16_t ftdi_id_table[][2] = { @@ -390,9 +392,9 @@ const struct usbh_class_driver ftdi_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info ftdi_class_info = { .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, - .class = 0xff, - .subclass = 0x00, - .protocol = 0x00, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, .id_table = ftdi_id_table, .class_driver = &ftdi_class_driver }; \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.c b/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.c index c64a1c3..01ee700 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.c @@ -15,7 +15,7 @@ USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_pl2303_buf[64]; -#define CONFIG_USBHOST_MAX_PL2303_CLASS 4 +#define CONFIG_USBHOST_MAX_PL2303_CLASS 1 #define UT_WRITE_VENDOR_DEVICE (USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE) #define UT_READ_VENDOR_DEVICE (USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE) @@ -25,11 +25,11 @@ static uint32_t g_devinuse = 0; static struct usbh_pl2303 *usbh_pl2303_class_alloc(void) { - int devno; + uint8_t devno; for (devno = 0; devno < CONFIG_USBHOST_MAX_PL2303_CLASS; devno++) { - if ((g_devinuse & (1 << devno)) == 0) { - g_devinuse |= (1 << devno); + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); memset(&g_pl2303_class[devno], 0, sizeof(struct usbh_pl2303)); g_pl2303_class[devno].minor = devno; return &g_pl2303_class[devno]; @@ -40,10 +40,10 @@ static struct usbh_pl2303 *usbh_pl2303_class_alloc(void) static void usbh_pl2303_class_free(struct usbh_pl2303 *pl2303_class) { - int devno = pl2303_class->minor; + uint8_t devno = pl2303_class->minor; - if (devno >= 0 && devno < 32) { - g_devinuse &= ~(1 << devno); + if (devno < 32) { + g_devinuse &= ~(1U << devno); } memset(pl2303_class, 0, sizeof(struct usbh_pl2303)); } @@ -413,10 +413,12 @@ int usbh_pl2303_bulk_out_transfer(struct usbh_pl2303 *pl2303_class, uint8_t *buf __WEAK void usbh_pl2303_run(struct usbh_pl2303 *pl2303_class) { + (void)pl2303_class; } __WEAK void usbh_pl2303_stop(struct usbh_pl2303 *pl2303_class) { + (void)pl2303_class; } static const uint16_t pl2303_id_table[][2] = { @@ -438,9 +440,9 @@ const struct usbh_class_driver pl2303_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info pl2303_class_info = { .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, - .class = 0xff, - .subclass = 0x00, - .protocol = 0x00, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, .id_table = pl2303_id_table, .class_driver = &pl2303_class_driver }; \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/vendor/wifi/README.md b/rt-thread/components/drivers/usb/cherryusb/class/vendor/wifi/README.md new file mode 100644 index 0000000..18384f6 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/class/vendor/wifi/README.md @@ -0,0 +1,6 @@ +# BL616 USB WIFI + +Usbwifi firmware please contact bouffalolab. You can purchase a module in the following ways: + +- https://iot.mi.com/moduleBrowser.html +- https://docs.ai-thinker.com/ai_m61 \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.c b/rt-thread/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.c new file mode 100644 index 0000000..9275faa --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.c @@ -0,0 +1,512 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_bl616.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_bl616" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/wifi/bl616" + +#define MAC_FMT "%02X:%02X:%02X:%02X:%02X:%02X" +#define ARR_ELE_6(e) (e)[0], (e)[1], (e)[2], (e)[3], (e)[4], (e)[5] + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bl616_tx_buffer[2048 + 512]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bl616_rx_buffer[2048 + 512]; + +static struct usbh_bl616 g_bl616_class; + +static const char *auth_to_str(uint8_t auth) +{ + const char *table[RNM_WIFI_AUTH_MAX] = { + [RNM_WIFI_AUTH_UNKNOWN] = "UNKNOWN", + [RNM_WIFI_AUTH_OPEN] = "OPEN", + [RNM_WIFI_AUTH_WEP] = "WEP", + [RNM_WIFI_AUTH_WPA_PSK] = "WPA-PSK", + [RNM_WIFI_AUTH_WPA2_PSK] = "WPA2-PSK", + [RNM_WIFI_AUTH_WPA_WPA2_PSK] = "WPA2-PSK/WPA-PSK", + [RNM_WIFI_AUTH_WPA_ENTERPRISE] = "WPA-ENT", + [RNM_WIFI_AUTH_WPA3_SAE] = "WPA3-SAE", + [RNM_WIFI_AUTH_WPA2_PSK_WPA3_SAE] = "WPA2-PSK/WPA3-SAE", + }; + if (auth < RNM_WIFI_AUTH_MAX) + return table[auth]; + else + return table[RNM_WIFI_AUTH_UNKNOWN]; +} + +static const char *cipher_to_str(uint8_t cipher) +{ + const char *table[RNM_WIFI_CIPHER_MAX] = { + [RNM_WIFI_CIPHER_UNKNOWN] = "UNKNOWN", + [RNM_WIFI_CIPHER_NONE] = "NONE", + [RNM_WIFI_CIPHER_WEP] = "WEP", + [RNM_WIFI_CIPHER_AES] = "AES", + [RNM_WIFI_CIPHER_TKIP] = "TKIP", + [RNM_WIFI_CIPHER_TKIP_AES] = "TKIP/AES", + }; + if (cipher < RNM_WIFI_CIPHER_MAX) + return table[cipher]; + else + return table[RNM_WIFI_CIPHER_UNKNOWN]; +} + +static int parse_get_mac_rsp_msg(struct usbh_bl616 *bl616_class, void *buf, int buf_len) +{ + usb_data_t *usb_hdr = buf; + rnm_mac_addr_ind_msg_t *rsp = buf + sizeof(usb_data_t); + + if (buf_len != sizeof(usb_data_t) + sizeof(rnm_mac_addr_ind_msg_t)) { + return -1; + } + if (usb_hdr->type != USBWIFI_DATA_TYPE_CMD || usb_hdr->length != sizeof(rnm_mac_addr_ind_msg_t)) { + return -1; + } + if (rsp->hdr.cmd != BFLB_CMD_GET_MAC_ADDR || !(rsp->hdr.flags & RNM_MSG_FLAG_ACK)) { + return -1; + } + memcpy(bl616_class->sta_mac, rsp->sta_mac, 6); + memcpy(bl616_class->ap_mac, rsp->ap_mac, 6); + + return 0; +} + +static int usbh_bl616_bulk_in_transfer(struct usbh_bl616 *bl616_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &bl616_class->bulkin_urb; + + usbh_bulk_urb_fill(urb, bl616_class->hport, bl616_class->bulkin, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +static int usbh_bl616_bulk_out_transfer(struct usbh_bl616 *bl616_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &bl616_class->bulkout_urb; + + usbh_bulk_urb_fill(urb, bl616_class->hport, bl616_class->bulkout, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +static int usbh_bl616_get_wifi_mac(struct usbh_bl616 *bl616_class) +{ + int ret; + uint32_t msg_len; + usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; + rnm_base_msg_t *rnm_msg = (rnm_base_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); + + memset(usb_hdr, 0, sizeof(usb_data_t)); + memset(rnm_msg, 0, sizeof(rnm_base_msg_t)); + + usb_hdr->type = USBWIFI_DATA_TYPE_CMD; + usb_hdr->length = sizeof(rnm_base_msg_t); + usb_hdr->payload_offset = sizeof(usb_data_t); + + rnm_msg->cmd = BFLB_CMD_GET_MAC_ADDR; + + msg_len = sizeof(usb_data_t) + sizeof(rnm_base_msg_t); + + ret = usbh_bl616_bulk_out_transfer(bl616_class, g_bl616_tx_buffer, msg_len, 500); + if (ret < 0) { + return ret; + } + ret = usbh_bl616_bulk_in_transfer(bl616_class, g_bl616_rx_buffer, sizeof(g_bl616_rx_buffer), 500); + if (ret < 0) { + return ret; + } + + ret = parse_get_mac_rsp_msg(bl616_class, g_bl616_rx_buffer, ret); + return ret; +} + +static int usbh_bl616_wifi_open(struct usbh_bl616 *bl616_class) +{ + uint32_t msg_len; + usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; + rnm_base_msg_t *msg = (rnm_base_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); + + memset(usb_hdr, 0, sizeof(usb_data_t)); + memset(msg, 0, sizeof(rnm_base_msg_t)); + + usb_hdr->type = USBWIFI_DATA_TYPE_CMD; + usb_hdr->length = sizeof(rnm_base_msg_t); + usb_hdr->payload_offset = sizeof(usb_data_t); + + msg->cmd = BFLB_CMD_HELLO; + + msg_len = sizeof(usb_data_t) + sizeof(rnm_base_msg_t); + + return usbh_bl616_bulk_out_transfer(bl616_class, g_bl616_tx_buffer, msg_len, 500); +} + +static int usbh_bl616_wifi_close(struct usbh_bl616 *bl616_class) +{ + uint32_t msg_len; + usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; + rnm_base_msg_t *msg = (rnm_base_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); + + memset(usb_hdr, 0, sizeof(usb_data_t)); + memset(msg, 0, sizeof(rnm_base_msg_t)); + + usb_hdr->type = USBWIFI_DATA_TYPE_CMD; + usb_hdr->length = sizeof(rnm_base_msg_t); + usb_hdr->payload_offset = sizeof(usb_data_t); + + msg->cmd = BFLB_CMD_UNLOAD_DRV; + + msg_len = sizeof(usb_data_t) + sizeof(rnm_base_msg_t); + + return usbh_bl616_bulk_out_transfer(bl616_class, g_bl616_tx_buffer, msg_len, 500); +} + +int usbh_bl616_wifi_sta_connect(const char *ssid, + const int ssid_len, + const char *password, + const int pwd_len) +{ + uint32_t msg_len; + usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; + rnm_sta_connect_msg_t *msg = (rnm_sta_connect_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); + + memset(usb_hdr, 0, sizeof(usb_data_t)); + memset(msg, 0, sizeof(rnm_sta_connect_msg_t)); + + usb_hdr->type = USBWIFI_DATA_TYPE_CMD; + usb_hdr->length = sizeof(rnm_sta_connect_msg_t); + usb_hdr->payload_offset = sizeof(usb_data_t); + + msg->hdr.cmd = BFLB_CMD_STA_CONNECT; + msg->hdr.msg_id = 0x0001; + msg->hdr.session_id = 0x0002; + msg->ssid_len = ssid_len; + memcpy(msg->ssid, ssid, ssid_len); + if (password) { + memcpy(msg->password, password, pwd_len); + } + + msg_len = sizeof(usb_data_t) + sizeof(rnm_sta_connect_msg_t); + + return usbh_bl616_bulk_out_transfer(&g_bl616_class, g_bl616_tx_buffer, msg_len, 500); +} + +int usbh_bl616_wifi_sta_disconnect(void) +{ + uint32_t msg_len; + usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; + rnm_base_msg_t *msg = (rnm_base_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); + + memset(usb_hdr, 0, sizeof(usb_data_t)); + memset(msg, 0, sizeof(rnm_base_msg_t)); + + usb_hdr->type = USBWIFI_DATA_TYPE_CMD; + usb_hdr->length = sizeof(rnm_base_msg_t); + usb_hdr->payload_offset = sizeof(usb_data_t); + + msg->cmd = BFLB_CMD_STA_DISCONNECT; + + msg_len = sizeof(usb_data_t) + sizeof(rnm_base_msg_t); + + return usbh_bl616_bulk_out_transfer(&g_bl616_class, g_bl616_tx_buffer, msg_len, 500); +} + +int usbh_bl616_get_wifi_scan_result(void) +{ + uint32_t msg_len; + usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; + rnm_base_msg_t *msg = (rnm_base_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); + + memset(usb_hdr, 0, sizeof(usb_data_t)); + memset(msg, 0, sizeof(rnm_base_msg_t)); + + usb_hdr->type = USBWIFI_DATA_TYPE_CMD; + usb_hdr->length = sizeof(rnm_base_msg_t); + usb_hdr->payload_offset = sizeof(usb_data_t); + + msg->cmd = BFLB_CMD_SCAN_RESULTS; + + msg_len = sizeof(usb_data_t) + sizeof(rnm_base_msg_t); + + return usbh_bl616_bulk_out_transfer(&g_bl616_class, g_bl616_tx_buffer, msg_len, 500); +} + +int usbh_bl616_wifi_scan(void) +{ + int ret; + uint32_t msg_len; + usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; + rnm_base_msg_t *msg = (rnm_base_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); + + memset(usb_hdr, 0, sizeof(usb_data_t)); + memset(msg, 0, sizeof(rnm_base_msg_t)); + + usb_hdr->type = USBWIFI_DATA_TYPE_CMD; + usb_hdr->length = sizeof(rnm_base_msg_t); + usb_hdr->payload_offset = sizeof(usb_data_t); + + msg->cmd = BFLB_CMD_SCAN; + + msg_len = sizeof(usb_data_t) + sizeof(rnm_base_msg_t); + + ret = usbh_bl616_bulk_out_transfer(&g_bl616_class, g_bl616_tx_buffer, msg_len, 500); + if (ret < 0) { + return ret; + } + + usb_osal_msleep(500); + return usbh_bl616_get_wifi_scan_result(); +} + +static int usbh_bl616_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret = 0; + + struct usbh_bl616 *bl616_class = &g_bl616_class; + + memset(bl616_class, 0, sizeof(struct usbh_bl616)); + + bl616_class->hport = hport; + bl616_class->intf = intf; + + hport->config.intf[intf].priv = bl616_class; + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(bl616_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(bl616_class->bulkout, ep_desc); + } + } + + usbh_bl616_get_wifi_mac(bl616_class); + usbh_bl616_wifi_close(bl616_class); + usbh_bl616_wifi_open(bl616_class); + + USB_LOG_INFO("BL616 WIFI STA MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", + bl616_class->sta_mac[0], + bl616_class->sta_mac[1], + bl616_class->sta_mac[2], + bl616_class->sta_mac[3], + bl616_class->sta_mac[4], + bl616_class->sta_mac[5]); + + USB_LOG_INFO("BL616 WIFI AP MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", + bl616_class->ap_mac[0], + bl616_class->ap_mac[1], + bl616_class->ap_mac[2], + bl616_class->ap_mac[3], + bl616_class->ap_mac[4], + bl616_class->ap_mac[5]); + + strncpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register BL616 WIFI Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_bl616_run(bl616_class); + return ret; +} + +static int usbh_bl616_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_bl616 *bl616_class = (struct usbh_bl616 *)hport->config.intf[intf].priv; + + if (bl616_class) { + if (bl616_class->bulkin) { + usbh_kill_urb(&bl616_class->bulkin_urb); + } + + if (bl616_class->bulkout) { + usbh_kill_urb(&bl616_class->bulkout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister BL616 WIFI Class:%s\r\n", hport->config.intf[intf].devname); + usbh_bl616_stop(bl616_class); + } + + memset(bl616_class, 0, sizeof(struct usbh_bl616)); + } + + return ret; +} + +void usbh_bl616_rx_thread(void *argument) +{ + int ret; + usb_data_t *usb_hdr; + rnm_base_msg_t *msg; + rnm_sta_ip_update_ind_msg_t *ipmsg; + rnm_scan_ind_msg_t *scanmsg; + uint8_t *data; + + (void)argument; + USB_LOG_INFO("Create bl616 wifi rx thread\r\n"); + + while (1) { + ret = usbh_bl616_bulk_in_transfer(&g_bl616_class, g_bl616_rx_buffer, sizeof(g_bl616_rx_buffer), USB_OSAL_WAITING_FOREVER); + if (ret < 0) { + break; + } + + usb_hdr = (usb_data_t *)g_bl616_rx_buffer; + + if (usb_hdr->type == USBWIFI_DATA_TYPE_CMD) { + msg = (rnm_base_msg_t *)(g_bl616_rx_buffer + usb_hdr->payload_offset); + + switch (msg->cmd) { + case BFLB_CMD_STA_CONNECTED_IND: + USB_LOG_INFO("AP connected\n"); + g_bl616_class.connect_status = true; + usbh_bl616_sta_connect_callback(); + + break; + case BFLB_CMD_STA_DISCONNECTED_IND: + if (g_bl616_class.connect_status == true) { + g_bl616_class.connect_status = false; + USB_LOG_INFO("AP disconnected\n"); + usbh_bl616_sta_disconnect_callback(); + } + break; + case BFLB_CMD_STA_IP_UPDATE_IND: + ipmsg = (rnm_sta_ip_update_ind_msg_t *)(g_bl616_rx_buffer + usb_hdr->payload_offset); + + USB_LOG_INFO("WIFI IP update\r\n"); + USB_LOG_INFO("WIFI IPv4 Address : %d:%d:%d:%d\r\n", + ipmsg->ip4_addr[0], + ipmsg->ip4_addr[1], + ipmsg->ip4_addr[2], + ipmsg->ip4_addr[3]); + USB_LOG_INFO("WIFI IPv4 Mask : %d:%d:%d:%d\r\n", + ipmsg->ip4_mask[0], + ipmsg->ip4_mask[1], + ipmsg->ip4_mask[2], + ipmsg->ip4_mask[3]); + USB_LOG_INFO("WIFI IPv4 Gateway : %d:%d:%d:%d\r\n\r\n", + ipmsg->ip4_gw[0], + ipmsg->ip4_gw[1], + ipmsg->ip4_gw[2], + ipmsg->ip4_gw[3]); + + g_bl616_class.mode = BL_MODE_STA; + usbh_bl616_sta_update_ip(ipmsg->ip4_addr, ipmsg->ip4_mask, ipmsg->ip4_gw); + break; + case BFLB_CMD_SCAN_RESULTS: + scanmsg = (rnm_scan_ind_msg_t *)(g_bl616_rx_buffer + usb_hdr->payload_offset); + USB_LOG_INFO("WIFI scan result:\r\n"); + for (uint32_t i = 0; i < scanmsg->num; ++i) { + struct bf1b_wifi_scan_record *r = &scanmsg->records[i]; + USB_LOG_INFO("BSSID " MAC_FMT ", channel %u, rssi %d, auth %s, cipher %s, SSID %s\r\n", + ARR_ELE_6(r->bssid), r->channel, r->rssi, + auth_to_str(r->auth_mode), cipher_to_str(r->cipher), r->ssid); + } + break; + default: + break; + } + } else if (usb_hdr->type == USBWIFI_DATA_TYPE_PKT) { + data = (uint8_t *)(g_bl616_rx_buffer + usb_hdr->payload_offset); + usbh_bl616_eth_input(data, usb_hdr->length); + } else { + } + } + + USB_LOG_INFO("Delete bl616 wifi rx thread\r\n"); + usb_osal_thread_delete(NULL); +} + +uint8_t *usbh_bl616_get_eth_txbuf(void) +{ + return (g_bl616_tx_buffer + sizeof(usb_data_t)); +} + +int usbh_bl616_eth_output(uint32_t buflen) +{ + usb_data_t *usb_hdr; + uint32_t txlen; + + if (g_bl616_class.connect_status == false) { + return -USB_ERR_NOTCONN; + } + + usb_hdr = (usb_data_t *)g_bl616_tx_buffer; + memset(usb_hdr, 0, sizeof(usb_data_t)); + + usb_hdr->type = USBWIFI_DATA_TYPE_PKT; + usb_hdr->length = buflen; + usb_hdr->payload_offset = sizeof(usb_data_t); + + txlen = buflen + sizeof(usb_data_t); + if (!(txlen % USB_GET_MAXPACKETSIZE(g_bl616_class.bulkout->wMaxPacketSize))) { + txlen += 1; + } + USB_LOG_DBG("txlen:%d\r\n", txlen); + + usbh_bulk_urb_fill(&g_bl616_class.bulkout_urb, g_bl616_class.hport, g_bl616_class.bulkout, g_bl616_tx_buffer, txlen, USB_OSAL_WAITING_FOREVER, NULL, NULL); + return usbh_submit_urb(&g_bl616_class.bulkout_urb); +} + +int wifi_sta_connect(int argc, char **argv) +{ + if (argc < 3) { + USB_LOG_ERR("Usage: %s \r\n", argv[0]); + return -1; + } + usbh_bl616_wifi_sta_connect(argv[1], strlen(argv[1]), argv[2], strlen(argv[2])); + return 0; +} + +int wifi_scan(int argc, char **argv) +{ + (void)argc; + (void)argv; + + usbh_bl616_wifi_scan(); + return 0; +} + +__WEAK void usbh_bl616_run(struct usbh_bl616 *bl616_class) +{ + (void)bl616_class; +} + +__WEAK void usbh_bl616_stop(struct usbh_bl616 *bl616_class) +{ + (void)bl616_class; +} + +static const uint16_t bl616_id_table[][2] = { + { 0x349b, 0x616f }, + { 0, 0 }, +}; + +static const struct usbh_class_driver bl616_class_driver = { + .driver_name = "bl616_wifi", + .connect = usbh_bl616_connect, + .disconnect = usbh_bl616_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info bl616_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = bl616_id_table, + .class_driver = &bl616_class_driver +}; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.h b/rt-thread/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.h new file mode 100644 index 0000000..6ec5a7a --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_BL616_H +#define USBH_BL616_H + +#define USBWIFI_DATA_TYPE_CMD 0xA55A +#define USBWIFI_DATA_TYPE_PKT 0x6996 + +#define USB_DATA_FLAG_AP_PKT (1u << 0) + +typedef enum { + BFLB_CMD_REBOOT = 0, + BFLB_CMD_RESET, + BFLB_CMD_HELLO, + BFLB_CMD_PING, + + BFLB_CMD_GET_MAC_ADDR, + + // Scan + BFLB_CMD_SCAN, + BFLB_CMD_SCAN_RESULTS, + + // STA + BFLB_CMD_STA_CONNECT, + BFLB_CMD_STA_DISCONNECT, + BFLB_CMD_STA_CONNECTED_IND, + BFLB_CMD_STA_DISCONNECTED_IND, + BFLB_CMD_STA_IP_UPDATE_IND, + BFLB_CMD_STA_SET_AUTO_RECONNECT, + BFLB_CMD_STA_GET_LINK_STATUS, + + // AP + BFLB_CMD_AP_START, + BFLB_CMD_AP_STOP, + BFLB_CMD_AP_STARTED_IND, + BFLB_CMD_AP_STOPPED_IND, + BFLB_CMD_AP_GET_STA_LIST, + + // Monitor + BFLB_CMD_MONITOR_START, + BFLB_CMD_MONITOR_STOP, + BFLB_CMD_MONITOR_SET_CHANNEL, + BFLB_CMD_MONITOR_GET_CHANNEL, + + BFLB_CMD_SET_LPM_MODE, + + // OTA + BFLB_CMD_GET_DEV_VERSION, + BFLB_CMD_OTA, + + BFLB_CMD_EXT, + + BFLB_CMD_USER_EXT, + BFLB_CMD_UNLOAD_DRV, + + BFLB_CMD_MAX, +} bflb_cmd_t; + +typedef enum { + STATUS_OK, + STATUS_NOMEM = 128, + STATUS_INVALID_INPUT, + STATUS_INVALID_MODE, + STATUS_ERR_UNSPECIFIED, + STATUS_NOT_IMPLEMENTED, +} cmd_status_t; + +typedef enum { + RNM_WIFI_AUTH_UNKNOWN = 0, + RNM_WIFI_AUTH_OPEN, + RNM_WIFI_AUTH_WEP, + RNM_WIFI_AUTH_WPA_PSK, + RNM_WIFI_AUTH_WPA2_PSK, + RNM_WIFI_AUTH_WPA_WPA2_PSK, + RNM_WIFI_AUTH_WPA_ENTERPRISE, + RNM_WIFI_AUTH_WPA3_SAE, + RNM_WIFI_AUTH_WPA2_PSK_WPA3_SAE, + RNM_WIFI_AUTH_MAX, +} rnm_wifi_auth_mode_t; + +typedef enum { + RNM_WIFI_CIPHER_UNKNOWN = 0, + RNM_WIFI_CIPHER_NONE, + RNM_WIFI_CIPHER_WEP, + RNM_WIFI_CIPHER_AES, + RNM_WIFI_CIPHER_TKIP, + RNM_WIFI_CIPHER_TKIP_AES, + RNM_WIFI_CIPHER_MAX, +} rnm_wifi_cipher_t; + +/* common header */ +typedef struct { + uint16_t cmd; + // flag ACK is used by server to indicate a response to client +#define RNM_MSG_FLAG_ACK (1 << 0) + // flag TRANSPARENT is never transfered to peer but used locally +#define RNM_MSG_FLAG_TRANSPARENT (1 << 1) + // flag ASYNC is used by server to notify client events such as STA_CONNECTED +#define RNM_MSG_FLAG_ASYNC (1 << 2) + uint16_t flags; + uint16_t status; + uint16_t msg_id; + uint16_t session_id; + uint16_t msg_id_replying; +} rnm_base_msg_t; + +typedef struct { + rnm_base_msg_t hdr; +} rnm_ack_msg_t; + +typedef struct { + rnm_base_msg_t hdr; + uint8_t sta_mac[6]; + uint8_t ap_mac[6]; +} rnm_mac_addr_ind_msg_t; + +typedef struct { + rnm_base_msg_t hdr; + uint16_t ssid_len; + uint8_t ssid[32]; + uint8_t password[64]; +} rnm_sta_connect_msg_t; + +typedef struct { + rnm_base_msg_t hdr; + uint8_t ip4_addr[4]; + uint8_t ip4_mask[4]; + uint8_t ip4_gw[4]; + uint8_t ip4_dns1[4]; + uint8_t ip4_dns2[4]; + uint8_t gw_mac[6]; +} rnm_sta_ip_update_ind_msg_t; + +struct bf1b_wifi_scan_record { + uint8_t bssid[6]; + // TODO use compressed SSID encoding to save room + uint8_t ssid[32 + 1]; + uint16_t channel; + int8_t rssi; + uint8_t auth_mode; + uint8_t cipher; +} __PACKED; + +typedef struct { + rnm_base_msg_t hdr; + uint16_t num; + struct bf1b_wifi_scan_record records[]; +} rnm_scan_ind_msg_t; + +typedef enum { + BL_MODE_NONE, + BL_MODE_STA, // card is STA + BL_MODE_AP, // card is AP + BL_MODE_STA_AP, // card is STA&AP + BL_MODE_SNIFFER, // card is sniffer + BL_MODE_MAX, +} bl_wifi_mode_t; + +typedef struct { + uint16_t type; + uint16_t length; + uint16_t flags; + uint16_t payload_offset; + uint32_t rsvd[8]; + uint8_t payload[]; +} __attribute__((aligned(4))) usb_data_t; + +struct usbh_bl616 { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; + + uint8_t intf; + + uint8_t sta_mac[6]; + uint8_t ap_mac[6]; + uint8_t mode; + bool connect_status; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_bl616_wifi_sta_connect(const char *ssid, + const int ssid_len, + const char *password, + const int pwd_len); + +int usbh_bl616_wifi_sta_disconnect(void); +int usbh_bl616_wifi_scan(void); + +void usbh_bl616_sta_connect_callback(void); +void usbh_bl616_sta_disconnect_callback(void); +void usbh_bl616_sta_update_ip(uint8_t ip4_addr[4], uint8_t ip4_mask[4], uint8_t ip4_gw[4]); + +uint8_t *usbh_bl616_get_eth_txbuf(void); +int usbh_bl616_eth_output(uint32_t buflen); +void usbh_bl616_eth_input(uint8_t *buf, uint32_t buflen); +void usbh_bl616_rx_thread(void *argument); + +void usbh_bl616_run(struct usbh_bl616 *bl616_class); +void usbh_bl616_stop(struct usbh_bl616 *bl616_class); + +int wifi_sta_connect(int argc, char **argv); +int wifi_scan(int argc, char **argv); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_BL616_H */ diff --git a/rt-thread/components/drivers/usb/cherryusb/class/vendor/xbox/usbh_xbox.c b/rt-thread/components/drivers/usb/cherryusb/class/vendor/xbox/usbh_xbox.c new file mode 100644 index 0000000..0c3339c --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/class/vendor/xbox/usbh_xbox.c @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2024 Till Harbaum + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_xbox.h" + +#define DEV_FORMAT "/dev/xbox%d" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_xbox_buf[128]; + +static struct usbh_xbox g_xbox_class[CONFIG_USBHOST_MAX_XBOX_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_xbox *usbh_xbox_class_alloc(void) +{ + uint8_t devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_XBOX_CLASS; devno++) { + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); + memset(&g_xbox_class[devno], 0, sizeof(struct usbh_xbox)); + g_xbox_class[devno].minor = devno; + return &g_xbox_class[devno]; + } + } + return NULL; +} + +static void usbh_xbox_class_free(struct usbh_xbox *xbox_class) +{ + uint8_t devno = xbox_class->minor; + + if (devno < 32) { + g_devinuse &= ~(1U << devno); + } + memset(xbox_class, 0, sizeof(struct usbh_xbox)); +} + +int usbh_xbox_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + + struct usbh_xbox *xbox_class = usbh_xbox_class_alloc(); + if (xbox_class == NULL) { + USB_LOG_ERR("Fail to alloc xbox_class\r\n"); + return -USB_ERR_NOMEM; + } + + xbox_class->hport = hport; + xbox_class->intf = intf; + + hport->config.intf[intf].priv = xbox_class; + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(xbox_class->intin, ep_desc); + } else { + USBH_EP_INIT(xbox_class->intout, ep_desc); + } + } + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, xbox_class->minor); + + USB_LOG_INFO("Register XBOX Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_xbox_run(xbox_class); + return 0; +} + +int usbh_xbox_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_xbox *xbox_class = (struct usbh_xbox *)hport->config.intf[intf].priv; + + if (xbox_class) { + if (xbox_class->intin) { + usbh_kill_urb(&xbox_class->intin_urb); + } + + if (xbox_class->intout) { + usbh_kill_urb(&xbox_class->intout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister XBOX Class:%s\r\n", hport->config.intf[intf].devname); + usbh_xbox_stop(xbox_class); + } + + usbh_xbox_class_free(xbox_class); + } + + return ret; +} + +__WEAK void usbh_xbox_run(struct usbh_xbox *xbox_class) +{ +} + +__WEAK void usbh_xbox_stop(struct usbh_xbox *xbox_class) +{ +} + +const struct usbh_class_driver xbox_class_driver = { + .driver_name = "xbox", + .connect = usbh_xbox_connect, + .disconnect = usbh_xbox_disconnect +}; + +static const uint16_t xbox_id_table[][2] = { + { 0x0079, 0x18d4 }, // GPD Win 2 X-Box Controller + { 0x03eb, 0xff01 }, // Wooting One (Legacy) + { 0x03eb, 0xff02 }, // Wooting Two (Legacy) + { 0x044f, 0xb326 }, // Thrustmaster Gamepad GP XID + { 0x045e, 0x028e }, // Microsoft X-Box 360 pad + { 0x045e, 0x028f }, // Microsoft X-Box 360 pad v2 + { 0x046d, 0xc21d }, // Logitech Gamepad F310 + { 0x046d, 0xc21e }, // Logitech Gamepad F510 + { 0x046d, 0xc21f }, // Logitech Gamepad F710 + { 0x046d, 0xc242 }, // Logitech Chillstream Controller + { 0x046d, 0xcaa3 }, // Logitech DriveFx Racing Wheel + { 0x056e, 0x2004 }, // Elecom JC-U3613M + { 0x06a3, 0xf51a }, // Saitek P3600 + { 0x0738, 0x4716 }, // Mad Catz Wired Xbox 360 Controller + { 0x0738, 0x4718 }, // Mad Catz Street Fighter IV FightStick SE + { 0x0738, 0x4726 }, // Mad Catz Xbox 360 Controller + { 0x0738, 0x4736 }, // Mad Catz MicroCon Gamepad + { 0x0738, 0x4740 }, // Mad Catz Beat Pad + { 0x0738, 0x9871 }, // Mad Catz Portable Drum + { 0x0738, 0xb726 }, // Mad Catz Xbox controller - MW2 + { 0x0738, 0xbeef }, // Mad Catz JOYTECH NEO SE Advanced GamePad + { 0x0738, 0xcb02 }, // Saitek Cyborg Rumble Pad - PC/Xbox 360 + { 0x0738, 0xcb03 }, // Saitek P3200 Rumble Pad - PC/Xbox 360 + { 0x0738, 0xcb29 }, // Saitek Aviator Stick AV8R02 + { 0x0738, 0xf738 }, // Super SFIV FightStick TE S + { 0x07ff, 0xffff }, // Mad Catz GamePad + { 0x0e6f, 0x0113 }, // Afterglow AX.1 Gamepad for Xbox 360 + { 0x0e6f, 0x011f }, // Rock Candy Gamepad Wired Controller + { 0x0e6f, 0x0131 }, // PDP EA Sports Controller + { 0x0e6f, 0x0133 }, // Xbox 360 Wired Controller + { 0x0e6f, 0x0201 }, // Pelican PL-3601 'TSZ' Wired Xbox 360 Controller + { 0x0e6f, 0x0213 }, // Afterglow Gamepad for Xbox 360 + { 0x0e6f, 0x021f }, // Rock Candy Gamepad for Xbox 360 + { 0x0e6f, 0x0301 }, // Logic3 Controller + { 0x0e6f, 0x0401 }, // Logic3 Controller + { 0x0e6f, 0x0413 }, // Afterglow AX.1 Gamepad for Xbox 360 + { 0x0e6f, 0x0501 }, // PDP Xbox 360 Controller + { 0x0e6f, 0xf900 }, // PDP Afterglow AX.1 + { 0x0f0d, 0x000a }, // Hori Co. DOA4 FightStick + { 0x0f0d, 0x000c }, // Hori PadEX Turbo + { 0x1038, 0x1430 }, // SteelSeries Stratus Duo + { 0x1038, 0x1431 }, // SteelSeries Stratus Duo + { 0x11c9, 0x55f0 }, // Nacon GC-100XF + { 0x1209, 0x2882 }, // Ardwiino Controller + { 0x12ab, 0x0301 }, // PDP AFTERGLOW AX.1 + { 0x1430, 0x4748 }, // RedOctane Guitar Hero X-plorer + { 0x1430, 0xf801 }, // RedOctane Controller + { 0x146b, 0x0601 }, // BigBen Interactive XBOX 360 Controller + { 0x1532, 0x0037 }, // Razer Sabertooth + { 0x15e4, 0x3f00 }, // Power A Mini Pro Elite + { 0x15e4, 0x3f0a }, // Xbox Airflo wired controller + { 0x15e4, 0x3f10 }, // Batarang Xbox 360 controller + { 0x162e, 0xbeef }, // Joytech Neo-Se Take2 + { 0x1689, 0xfd00 }, // Razer Onza Tournament Edition + { 0x1689, 0xfd01 }, // Razer Onza Classic Edition + { 0x1689, 0xfe00 }, // Razer Sabertooth + { 0x1949, 0x041a }, // Amazon Game Controller + { 0x1bad, 0x0002 }, // Harmonix Rock Band Guitar + { 0x1bad, 0xf016 }, // Mad Catz Xbox 360 Controller + { 0x1bad, 0xf021 }, // Mad Cats Ghost Recon FS GamePad + { 0x1bad, 0xf023 }, // MLG Pro Circuit Controller (Xbox) + { 0x1bad, 0xf025 }, // Mad Catz Call Of Duty + { 0x1bad, 0xf027 }, // Mad Catz FPS Pro + { 0x1bad, 0xf028 }, // Street Fighter IV FightPad + { 0x1bad, 0xf030 }, // Mad Catz Xbox 360 MC2 MicroCon Racing Wheel + { 0x1bad, 0xf036 }, // Mad Catz MicroCon GamePad Pro + { 0x1bad, 0xf038 }, // Street Fighter IV FightStick TE + { 0x1bad, 0xf501 }, // HoriPad EX2 Turbo + { 0x1bad, 0xf506 }, // Hori Real Arcade Pro.EX Premium VLX + { 0x1bad, 0xf900 }, // Harmonix Xbox 360 Controller + { 0x1bad, 0xf901 }, // Gamestop Xbox 360 Controller + { 0x1bad, 0xf903 }, // Tron Xbox 360 controller + { 0x1bad, 0xf904 }, // PDP Versus Fighting Pad + { 0x1bad, 0xfa01 }, // MadCatz GamePad + { 0x1bad, 0xfd00 }, // Razer Onza TE + { 0x1bad, 0xfd01 }, // Razer Onza + { 0x20d6, 0x2001 }, // BDA Xbox Series X Wired Controller + { 0x20d6, 0x281f }, // PowerA Wired Controller For Xbox 360 + { 0x24c6, 0x5300 }, // PowerA MINI PROEX Controller + { 0x24c6, 0x5303 }, // Xbox Airflo wired controller + { 0x24c6, 0x530a }, // Xbox 360 Pro EX Controller + { 0x24c6, 0x531a }, // PowerA Pro Ex + { 0x24c6, 0x5397 }, // FUS1ON Tournament Controller + { 0x24c6, 0x5500 }, // Hori XBOX 360 EX 2 with Turbo + { 0x24c6, 0x5501 }, // Hori Real Arcade Pro VX-SA + { 0x24c6, 0x5506 }, // Hori SOULCALIBUR V Stick + { 0x24c6, 0x550d }, // Hori GEM Xbox controller + { 0x24c6, 0x5b00 }, // ThrustMaster Ferrari 458 Racing Wheel + { 0x24c6, 0x5b02 }, // Thrustmaster, Inc. GPX Controller + { 0x24c6, 0x5b03 }, // Thrustmaster Ferrari 458 Racing Wheel + { 0x24c6, 0x5d04 }, // Razer Sabertooth + { 0x24c6, 0xfafe }, // Rock Candy Gamepad for Xbox 360 + { 0x2563, 0x058d }, // OneXPlayer Gamepad + { 0x2dc8, 0x3106 }, // 8BitDo Ultimate Wireless / Pro 2 Wired Controller + { 0x2dc8, 0x3109 }, // 8BitDo Ultimate Wireless Bluetooth + { 0x31e3, 0x1100 }, // Wooting One + { 0x31e3, 0x1200 }, // Wooting Two + { 0x31e3, 0x1210 }, // Wooting Lekker + { 0x31e3, 0x1220 }, // Wooting Two HE + { 0x31e3, 0x1230 }, // Wooting Two HE (ARM) + { 0x31e3, 0x1300 }, // Wooting 60HE (AVR) + { 0x31e3, 0x1310 }, // Wooting 60HE (ARM) + { 0x3285, 0x0607 }, // Nacon GC-100 + { 0x413d, 0x2104 }, // Black Shark Green Ghost Gamepad + { 0x0000, 0x0000 } // end of list +}; + +CLASS_INFO_DEFINE const struct usbh_class_info xbox_custom_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_VEND_SPECIFIC, + .bInterfaceSubClass = 0x5d, + .bInterfaceProtocol = 0x01, + .id_table = xbox_id_table, + .class_driver = &xbox_class_driver +}; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/vendor/xbox/usbh_xbox.h b/rt-thread/components/drivers/usb/cherryusb/class/vendor/xbox/usbh_xbox.h new file mode 100644 index 0000000..85d4672 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/class/vendor/xbox/usbh_xbox.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2024, Till Harbaum + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_XBOX_H +#define USBH_XBOX_H + +struct usbh_xbox { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *intin; /* INTR IN endpoint */ + struct usb_endpoint_descriptor *intout; /* INTR OUT endpoint */ + struct usbh_urb intin_urb; /* INTR IN urb */ + struct usbh_urb intout_urb; /* INTR OUT urb */ + + uint8_t intf; /* interface number */ + uint8_t minor; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +void usbh_xbox_run(struct usbh_xbox *xbox_class); +void usbh_xbox_stop(struct usbh_xbox *xbox_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_XBOX_H */ diff --git a/rt-thread/components/drivers/usb/cherryusb/class/video/usbd_video.c b/rt-thread/components/drivers/usb/cherryusb/class/video/usbd_video.c index b11fa6a..dae28eb 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/video/usbd_video.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/video/usbd_video.c @@ -18,12 +18,28 @@ struct usbd_video_priv { uint8_t power_mode; uint8_t error_code; struct video_entity_info info[3]; + uint8_t *ep_buf0; + uint8_t *ep_buf1; + bool ep_buf0_ready; + bool ep_buf1_ready; + uint32_t ep_buf0_len; + uint32_t ep_buf1_len; + uint8_t ep_buf_idx; + bool stream_finish; + uint32_t max_packets; + uint8_t *stream_buf; + uint32_t stream_len; + uint32_t stream_offset; + uint8_t stream_frameid; + uint32_t stream_headerlen; } g_usbd_video[CONFIG_USBDEV_MAX_BUS]; static int usbd_video_control_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) { uint8_t control_selector = (uint8_t)(setup->wValue >> 8); + (void)busid; + switch (control_selector) { case VIDEO_VC_VIDEO_POWER_MODE_CONTROL: switch (setup->bRequest) { @@ -669,7 +685,7 @@ static int video_class_interface_request_handler(uint8_t busid, struct usb_setup } else { return usbd_video_control_unit_terminal_request_handler(busid, setup, data, len); /* Unit and Terminal Requests */ } - } else if (intf_num == 1) { /* Video Stream Inteface */ + } else if (intf_num == 1) { /* Video Stream Inteface */ return usbd_video_stream_request_handler(busid, setup, data, len); /* Interface Stream Requests */ } return -1; @@ -698,7 +714,7 @@ static void video_notify_handler(uint8_t busid, uint8_t event, void *arg) } } -void usbd_video_probe_and_commit_controls_init(uint8_t busid, uint32_t dwFrameInterval, uint32_t dwMaxVideoFrameSize, uint32_t dwMaxPayloadTransferSize) +static void usbd_video_probe_and_commit_controls_init(uint8_t busid, uint32_t dwFrameInterval, uint32_t dwMaxVideoFrameSize, uint32_t dwMaxPayloadTransferSize) { g_usbd_video[busid].probe.hintUnion.bmHint = 0x01; g_usbd_video[busid].probe.hintUnion1.bmHint = 0; @@ -735,9 +751,47 @@ void usbd_video_probe_and_commit_controls_init(uint8_t busid, uint32_t dwFrameIn g_usbd_video[busid].commit.bPreferedVersion = 0; g_usbd_video[busid].commit.bMinVersion = 0; g_usbd_video[busid].commit.bMaxVersion = 0; + + g_usbd_video[busid].stream_frameid = 0; + g_usbd_video[busid].stream_headerlen = 2; } -struct usbd_interface *usbd_video_init_intf(uint8_t busid, struct usbd_interface *intf, +static uint32_t usbd_video_prepare_ep_buf_data(uint8_t busid, uint32_t remain, uint8_t *ep_buf) +{ + struct video_payload_header *header; + uint32_t len; + uint32_t offset; + + len = MIN(remain, (g_usbd_video[busid].probe.dwMaxPayloadTransferSize - g_usbd_video[busid].stream_headerlen) * g_usbd_video[busid].max_packets); + offset = 0; + while (len > 0) { + header = (struct video_payload_header *)&ep_buf[offset]; + header->bHeaderLength = g_usbd_video[busid].stream_headerlen; + header->headerInfoUnion.bmheaderInfo = 0; + header->headerInfoUnion.headerInfoBits.endOfHeader = 1; + header->headerInfoUnion.headerInfoBits.endOfFrame = 0; + header->headerInfoUnion.headerInfoBits.frameIdentifier = g_usbd_video[busid].stream_frameid; + + uint32_t len2 = MIN(len, g_usbd_video[busid].probe.dwMaxPayloadTransferSize - g_usbd_video[busid].stream_headerlen); + + usb_memcpy(&ep_buf[offset + g_usbd_video[busid].stream_headerlen], + &g_usbd_video[busid].stream_buf[g_usbd_video[busid].stream_offset], + len2); + + g_usbd_video[busid].stream_offset += len2; + len -= len2; + offset += (len2 + g_usbd_video[busid].stream_headerlen); + + if (g_usbd_video[busid].stream_offset == g_usbd_video[busid].stream_len) { + header->headerInfoUnion.headerInfoBits.endOfFrame = 1; + } + } + + return offset; +} + +struct usbd_interface *usbd_video_init_intf(uint8_t busid, + struct usbd_interface *intf, uint32_t dwFrameInterval, uint32_t dwMaxVideoFrameSize, uint32_t dwMaxPayloadTransferSize) @@ -761,28 +815,70 @@ struct usbd_interface *usbd_video_init_intf(uint8_t busid, struct usbd_interface return intf; } -uint32_t usbd_video_payload_fill(uint8_t busid, uint8_t *input, uint32_t input_len, uint8_t *output, uint32_t *out_len) +bool usbd_video_stream_split_transfer(uint8_t busid, uint8_t ep) { - uint32_t packets; - uint32_t last_packet_size; - uint32_t picture_pos = 0; - static uint8_t uvc_header[2] = { 0x02, 0x80 }; + uint32_t remain; - packets = (input_len + (g_usbd_video[busid].probe.dwMaxPayloadTransferSize - 2) ) / (g_usbd_video[busid].probe.dwMaxPayloadTransferSize - 2); - last_packet_size = input_len - ((packets - 1) * (g_usbd_video[busid].probe.dwMaxPayloadTransferSize - 2)); - - for (size_t i = 0; i < packets; i++) { - output[g_usbd_video[busid].probe.dwMaxPayloadTransferSize * i] = uvc_header[0]; - output[g_usbd_video[busid].probe.dwMaxPayloadTransferSize * i + 1] = uvc_header[1]; - if (i == (packets - 1)) { - memcpy(&output[2 + g_usbd_video[busid].probe.dwMaxPayloadTransferSize * i], &input[picture_pos], last_packet_size); - output[g_usbd_video[busid].probe.dwMaxPayloadTransferSize * i + 1] |= (1 << 1); - } else { - memcpy(&output[2 + g_usbd_video[busid].probe.dwMaxPayloadTransferSize * i], &input[picture_pos], g_usbd_video[busid].probe.dwMaxPayloadTransferSize - 2); - picture_pos += g_usbd_video[busid].probe.dwMaxPayloadTransferSize - 2; + if (g_usbd_video[busid].ep_buf1_ready && (g_usbd_video[busid].ep_buf_idx == 0)) { /* callback: buf1 ready and buf0 was sent */ + g_usbd_video[busid].ep_buf0_ready = false; + g_usbd_video[busid].ep_buf_idx = 1; + usbd_ep_start_write(busid, ep, g_usbd_video[busid].ep_buf1, g_usbd_video[busid].ep_buf1_len); + } else if (g_usbd_video[busid].ep_buf0_ready && (g_usbd_video[busid].ep_buf_idx == 1)) { /* callback: buf0 ready and buf1 was sent */ + g_usbd_video[busid].ep_buf1_ready = false; + g_usbd_video[busid].ep_buf_idx = 0; + usbd_ep_start_write(busid, ep, g_usbd_video[busid].ep_buf0, g_usbd_video[busid].ep_buf0_len); + } else { + if (g_usbd_video[busid].stream_finish) { + return true; } } - uvc_header[1] ^= 1; - *out_len = (input_len + 2 * packets); - return packets; -} \ No newline at end of file + + if (!g_usbd_video[busid].ep_buf0_ready) { + remain = g_usbd_video[busid].stream_len - g_usbd_video[busid].stream_offset; + if (remain == 0) { + g_usbd_video[busid].stream_frameid ^= 1; + g_usbd_video[busid].stream_finish = true; + } else { + g_usbd_video[busid].ep_buf0_len = usbd_video_prepare_ep_buf_data(busid, remain, g_usbd_video[busid].ep_buf0); + g_usbd_video[busid].ep_buf0_ready = true; + if (!g_usbd_video[busid].ep_buf1_ready) { + g_usbd_video[busid].ep_buf_idx = 0; + usbd_ep_start_write(busid, ep, g_usbd_video[busid].ep_buf0, g_usbd_video[busid].ep_buf0_len); + } + } + } + + if (!g_usbd_video[busid].ep_buf1_ready) { + remain = g_usbd_video[busid].stream_len - g_usbd_video[busid].stream_offset; + if (remain == 0) { + g_usbd_video[busid].stream_frameid ^= 1; + g_usbd_video[busid].stream_finish = true; + } else { + g_usbd_video[busid].ep_buf1_len = usbd_video_prepare_ep_buf_data(busid, remain, g_usbd_video[busid].ep_buf1); + g_usbd_video[busid].ep_buf1_ready = true; + } + } + + return false; +} + +int usbd_video_stream_start_write(uint8_t busid, uint8_t ep, uint8_t *ep_buf0, uint8_t *ep_buf1, uint32_t ep_bufsize, uint8_t *stream_buf, uint32_t stream_len) +{ + if ((usb_device_is_configured(busid) == 0) || (stream_len == 0)) { + return -1; + } + + g_usbd_video[busid].ep_buf0 = ep_buf0; + g_usbd_video[busid].ep_buf1 = ep_buf1; + g_usbd_video[busid].ep_buf0_ready = false; + g_usbd_video[busid].ep_buf1_ready = false; + g_usbd_video[busid].ep_buf_idx = 0; + g_usbd_video[busid].stream_finish = false; + g_usbd_video[busid].max_packets = ep_bufsize / g_usbd_video[busid].probe.dwMaxPayloadTransferSize; + g_usbd_video[busid].stream_buf = stream_buf; + g_usbd_video[busid].stream_len = stream_len; + g_usbd_video[busid].stream_offset = 0; + + usbd_video_stream_split_transfer(busid, ep); + return 0; +} diff --git a/rt-thread/components/drivers/usb/cherryusb/class/video/usbd_video.h b/rt-thread/components/drivers/usb/cherryusb/class/video/usbd_video.h index 14636fb..a2a98bb 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/video/usbd_video.h +++ b/rt-thread/components/drivers/usb/cherryusb/class/video/usbd_video.h @@ -20,7 +20,9 @@ struct usbd_interface *usbd_video_init_intf(uint8_t busid, struct usbd_interface void usbd_video_open(uint8_t busid, uint8_t intf); void usbd_video_close(uint8_t busid, uint8_t intf); -uint32_t usbd_video_payload_fill(uint8_t busid, uint8_t *input, uint32_t input_len, uint8_t *output, uint32_t *out_len); + +bool usbd_video_stream_split_transfer(uint8_t busid, uint8_t ep); +int usbd_video_stream_start_write(uint8_t busid, uint8_t ep, uint8_t *ep_buf0, uint8_t *ep_buf1, uint32_t ep_bufsize, uint8_t *stream_buf, uint32_t stream_len); #ifdef __cplusplus } diff --git a/rt-thread/components/drivers/usb/cherryusb/class/video/usbh_video.c b/rt-thread/components/drivers/usb/cherryusb/class/video/usbh_video.c index 0d3f79f..7379151 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/video/usbh_video.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/video/usbh_video.c @@ -34,11 +34,11 @@ static uint32_t g_devinuse = 0; static struct usbh_video *usbh_video_class_alloc(void) { - int devno; + uint8_t devno; for (devno = 0; devno < CONFIG_USBHOST_MAX_VIDEO_CLASS; devno++) { - if ((g_devinuse & (1 << devno)) == 0) { - g_devinuse |= (1 << devno); + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); memset(&g_video_class[devno], 0, sizeof(struct usbh_video)); g_video_class[devno].minor = devno; return &g_video_class[devno]; @@ -49,10 +49,10 @@ static struct usbh_video *usbh_video_class_alloc(void) static void usbh_video_class_free(struct usbh_video *video_class) { - int devno = video_class->minor; + uint8_t devno = video_class->minor; - if (devno >= 0 && devno < 32) { - g_devinuse &= ~(1 << devno); + if (devno < 32) { + g_devinuse &= ~(1U << devno); } memset(video_class, 0, sizeof(struct usbh_video)); } @@ -495,20 +495,26 @@ static int usbh_video_ctrl_disconnect(struct usbh_hubport *hport, uint8_t intf) static int usbh_video_streaming_connect(struct usbh_hubport *hport, uint8_t intf) { + (void)hport; + (void)intf; return 0; } static int usbh_video_streaming_disconnect(struct usbh_hubport *hport, uint8_t intf) { + (void)hport; + (void)intf; return 0; } __WEAK void usbh_video_run(struct usbh_video *video_class) { + (void)video_class; } __WEAK void usbh_video_stop(struct usbh_video *video_class) { + (void)video_class; } const struct usbh_class_driver video_ctrl_class_driver = { @@ -525,18 +531,18 @@ const struct usbh_class_driver video_streaming_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info video_ctrl_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, - .class = USB_DEVICE_CLASS_VIDEO, - .subclass = VIDEO_SC_VIDEOCONTROL, - .protocol = VIDEO_PC_PROTOCOL_UNDEFINED, + .bInterfaceClass = USB_DEVICE_CLASS_VIDEO, + .bInterfaceSubClass = VIDEO_SC_VIDEOCONTROL, + .bInterfaceProtocol = VIDEO_PC_PROTOCOL_UNDEFINED, .id_table = NULL, .class_driver = &video_ctrl_class_driver }; CLASS_INFO_DEFINE const struct usbh_class_info video_streaming_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, - .class = USB_DEVICE_CLASS_VIDEO, - .subclass = VIDEO_SC_VIDEOSTREAMING, - .protocol = VIDEO_PC_PROTOCOL_UNDEFINED, + .bInterfaceClass = USB_DEVICE_CLASS_VIDEO, + .bInterfaceSubClass = VIDEO_SC_VIDEOSTREAMING, + .bInterfaceProtocol = VIDEO_PC_PROTOCOL_UNDEFINED, .id_table = NULL, .class_driver = &video_streaming_class_driver }; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.c b/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.c index c357b25..4384970 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.c @@ -102,6 +102,8 @@ static void rndis_notify_rsp(void) static int rndis_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) { + (void)busid; + switch (setup->bRequest) { case CDC_REQUEST_SEND_ENCAPSULATED_COMMAND: rndis_encapsulated_cmd_handler(*data, setup->wLength); @@ -152,6 +154,8 @@ static int rndis_init_cmd_handler(uint8_t *data, uint32_t len) rndis_initialize_msg_t *cmd = (rndis_initialize_msg_t *)data; rndis_initialize_cmplt_t *resp; + (void)len; + resp = ((rndis_initialize_cmplt_t *)rndis_encapsulated_resp_buffer); resp->RequestId = cmd->RequestId; resp->MessageType = REMOTE_NDIS_INITIALIZE_CMPLT; @@ -177,6 +181,9 @@ static int rndis_halt_cmd_handler(uint8_t *data, uint32_t len) { rndis_halt_msg_t *resp; + (void)data; + (void)len; + resp = ((rndis_halt_msg_t *)rndis_encapsulated_resp_buffer); resp->MessageLength = 0; @@ -192,6 +199,8 @@ static int rndis_query_cmd_handler(uint8_t *data, uint32_t len) uint8_t *infomation_buffer; uint32_t infomation_len = 0; + (void)len; + resp = ((rndis_query_cmplt_t *)rndis_encapsulated_resp_buffer); resp->MessageType = REMOTE_NDIS_QUERY_CMPLT; resp->RequestId = cmd->RequestId; @@ -338,6 +347,8 @@ static int rndis_set_cmd_handler(uint8_t *data, uint32_t len) rndis_set_cmplt_t *resp; rndis_config_parameter_t *param; + (void)len; + resp = ((rndis_set_cmplt_t *)rndis_encapsulated_resp_buffer); resp->RequestId = cmd->RequestId; resp->MessageType = REMOTE_NDIS_SET_CMPLT; @@ -394,6 +405,9 @@ static int rndis_reset_cmd_handler(uint8_t *data, uint32_t len) // rndis_reset_msg_t *cmd = (rndis_reset_msg_t *)data; rndis_reset_cmplt_t *resp; + (void)data; + (void)len; + resp = ((rndis_reset_cmplt_t *)rndis_encapsulated_resp_buffer); resp->MessageType = REMOTE_NDIS_RESET_CMPLT; resp->MessageLength = sizeof(rndis_reset_cmplt_t); @@ -412,6 +426,8 @@ static int rndis_keepalive_cmd_handler(uint8_t *data, uint32_t len) rndis_keepalive_msg_t *cmd = (rndis_keepalive_msg_t *)data; rndis_keepalive_cmplt_t *resp; + (void)len; + resp = ((rndis_keepalive_cmplt_t *)rndis_encapsulated_resp_buffer); resp->RequestId = cmd->RequestId; resp->MessageType = REMOTE_NDIS_KEEPALIVE_CMPLT; @@ -425,6 +441,9 @@ static int rndis_keepalive_cmd_handler(uint8_t *data, uint32_t len) static void rndis_notify_handler(uint8_t busid, uint8_t event, void *arg) { + (void)busid; + (void)arg; + switch (event) { case USBD_EVENT_RESET: g_usbd_rndis.link_status = NDIS_MEDIA_STATE_DISCONNECTED; @@ -445,6 +464,9 @@ void rndis_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) { rndis_data_packet_t *hdr; + (void)busid; + (void)ep; + hdr = (rndis_data_packet_t *)g_rndis_rx_buffer; g_rndis_rx_data_buffer = g_rndis_rx_buffer; if ((hdr->MessageType != REMOTE_NDIS_PACKET_MSG) || (nbytes < hdr->MessageLength)) { @@ -456,21 +478,28 @@ void rndis_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) g_rndis_rx_data_buffer += hdr->DataOffset + sizeof(rndis_generic_msg_t); g_rndis_rx_data_length = hdr->DataLength; - usbd_rndis_data_recv_done(); + usbd_rndis_data_recv_done(g_rndis_rx_data_length); } void rndis_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) { - if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) { + (void)busid; + + if ((nbytes % usbd_get_ep_mps(0, ep)) == 0 && nbytes) { /* send zlp */ usbd_ep_start_write(0, ep, NULL, 0); } else { + usbd_rndis_data_send_done(g_rndis_tx_data_length); g_rndis_tx_data_length = 0; } } void rndis_int_in(uint8_t busid, uint8_t ep, uint32_t nbytes) { + (void)busid; + (void)ep; + (void)nbytes; + //USB_LOG_DBG("len:%d\r\n", nbytes); } @@ -564,3 +593,13 @@ struct usbd_interface *usbd_rndis_init_intf(struct usbd_interface *intf, return intf; } + +__WEAK void usbd_rndis_data_recv_done(uint32_t len) +{ + (void)len; +} + +__WEAK void usbd_rndis_data_send_done(uint32_t len) +{ + (void)len; +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.h b/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.h index 8a9581f..72b89ea 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.h +++ b/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.h @@ -18,7 +18,8 @@ struct usbd_interface *usbd_rndis_init_intf(struct usbd_interface *intf, const uint8_t in_ep, const uint8_t int_ep, uint8_t mac[6]); -void usbd_rndis_data_recv_done(void); +void usbd_rndis_data_recv_done(uint32_t len); +void usbd_rndis_data_send_done(uint32_t len); #ifdef CONFIG_USBDEV_RNDIS_USING_LWIP struct pbuf *usbd_rndis_eth_rx(void); diff --git a/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbh_bluetooth.c b/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbh_bluetooth.c index e73eeb0..991f095 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbh_bluetooth.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbh_bluetooth.c @@ -365,14 +365,18 @@ delete : __WEAK void usbh_bluetooth_hci_read_callback(uint8_t *data, uint32_t len) { + (void)data; + (void)len; } __WEAK void usbh_bluetooth_run(struct usbh_bluetooth *bluetooth_class) { + (void)bluetooth_class; } __WEAK void usbh_bluetooth_stop(struct usbh_bluetooth *bluetooth_class) { + (void)bluetooth_class; } static const struct usbh_class_driver bluetooth_class_driver = { @@ -389,18 +393,18 @@ static const uint16_t bluetooth_id_table[][2] = { CLASS_INFO_DEFINE const struct usbh_class_info bluetooth_h4_nrf_class_info = { .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, - .class = 0xff, - .subclass = 0x00, - .protocol = 0x00, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, .id_table = bluetooth_id_table, .class_driver = &bluetooth_class_driver }; #else CLASS_INFO_DEFINE const struct usbh_class_info bluetooth_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, - .class = USB_DEVICE_CLASS_WIRELESS, - .subclass = 0x01, - .protocol = 0x01, + .bInterfaceClass = USB_DEVICE_CLASS_WIRELESS, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01, .id_table = NULL, .class_driver = &bluetooth_class_driver }; diff --git a/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.c b/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.c index e722e50..e9eaff0 100644 --- a/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.c +++ b/rt-thread/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.c @@ -13,7 +13,7 @@ #define DEV_FORMAT "/dev/rndis" -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_buf[4096]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_buf[512]; #define CONFIG_USBHOST_RNDIS_ETH_MAX_FRAME_SIZE 1514 #define CONFIG_USBHOST_RNDIS_ETH_MSG_SIZE (CONFIG_USBHOST_RNDIS_ETH_MAX_FRAME_SIZE + 44) @@ -26,6 +26,7 @@ static struct usbh_rndis g_rndis_class; static int usbh_rndis_get_notification(struct usbh_rndis *rndis_class) { + (void)rndis_class; // int ret; // struct usbh_urb *urb = &rndis_class->intin_urb; @@ -79,7 +80,7 @@ static int usbh_rndis_init_msg_transfer(struct usbh_rndis *rndis_class) setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; setup->wValue = 0; setup->wIndex = 0; - setup->wLength = 4096; + setup->wLength = sizeof(g_rndis_buf); ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)resp); if (ret < 0) { @@ -137,7 +138,7 @@ int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; setup->wValue = 0; setup->wIndex = 0; - setup->wLength = 4096; + setup->wLength = sizeof(g_rndis_buf); ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)resp); if (ret < 0) { @@ -194,7 +195,7 @@ static int usbh_rndis_set_msg_transfer(struct usbh_rndis *rndis_class, uint32_t setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; setup->wValue = 0; setup->wIndex = 0; - setup->wLength = 4096; + setup->wLength = sizeof(g_rndis_buf); ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)resp); if (ret < 0) { @@ -261,7 +262,7 @@ int usbh_rndis_keepalive(struct usbh_rndis *rndis_class) setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; setup->wValue = 0; setup->wIndex = 0; - setup->wLength = 4096; + setup->wLength = sizeof(g_rndis_buf); ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)resp); if (ret < 0) { @@ -386,14 +387,14 @@ static int usbh_rndis_connect(struct usbh_hubport *hport, uint8_t intf) } uint32_t packet_filter = 0x0f; - usbh_rndis_set_msg_transfer(rndis_class, OID_GEN_CURRENT_PACKET_FILTER, (uint8_t *)&packet_filter, 4); + ret = usbh_rndis_set_msg_transfer(rndis_class, OID_GEN_CURRENT_PACKET_FILTER, (uint8_t *)&packet_filter, 4); if (ret < 0) { return ret; } USB_LOG_INFO("rndis set OID_GEN_CURRENT_PACKET_FILTER success\r\n"); uint8_t multicast_list[6] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0x01 }; - usbh_rndis_set_msg_transfer(rndis_class, OID_802_3_MULTICAST_LIST, multicast_list, 6); + ret = usbh_rndis_set_msg_transfer(rndis_class, OID_802_3_MULTICAST_LIST, multicast_list, 6); if (ret < 0) { return ret; } @@ -460,6 +461,8 @@ void usbh_rndis_rx_thread(void *argument) uint32_t transfer_size = (16 * 1024); #endif + (void)argument; + USB_LOG_INFO("Create rndis rx thread\r\n"); // clang-format off find_class: @@ -531,7 +534,7 @@ find_class: #else if ((g_rndis_rx_length + (16 * 1024)) > CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE) { #endif - USB_LOG_ERR("Rx packet is overflow, please ruduce tcp window size or increase CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE\r\n"); + USB_LOG_ERR("Rx packet is overflow, please reduce tcp window size or increase CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE\r\n"); while (1) { } } @@ -581,10 +584,12 @@ int usbh_rndis_eth_output(uint32_t buflen) __WEAK void usbh_rndis_run(struct usbh_rndis *rndis_class) { + (void)rndis_class; } __WEAK void usbh_rndis_stop(struct usbh_rndis *rndis_class) { + (void)rndis_class; } static const struct usbh_class_driver rndis_class_driver = { @@ -595,9 +600,9 @@ static const struct usbh_class_driver rndis_class_driver = { CLASS_INFO_DEFINE const struct usbh_class_info rndis_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, - .class = USB_DEVICE_CLASS_WIRELESS, - .subclass = 0x01, - .protocol = 0x03, + .bInterfaceClass = USB_DEVICE_CLASS_WIRELESS, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x03, .id_table = NULL, .class_driver = &rndis_class_driver }; diff --git a/rt-thread/components/drivers/usb/cherryusb/common/usb_dc.h b/rt-thread/components/drivers/usb/cherryusb/common/usb_dc.h index a10869a..1f2fddd 100644 --- a/rt-thread/components/drivers/usb/cherryusb/common/usb_dc.h +++ b/rt-thread/components/drivers/usb/cherryusb/common/usb_dc.h @@ -33,6 +33,13 @@ int usb_dc_deinit(uint8_t busid); */ int usbd_set_address(uint8_t busid, const uint8_t addr); +/** + * @brief Set remote wakeup feature + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_set_remote_wakeup(uint8_t busid); + /** * @brief Get USB device speed * diff --git a/rt-thread/components/drivers/usb/cherryusb/common/usb_def.h b/rt-thread/components/drivers/usb/cherryusb/common/usb_def.h index aea3d6a..27b4d82 100644 --- a/rt-thread/components/drivers/usb/cherryusb/common/usb_def.h +++ b/rt-thread/components/drivers/usb/cherryusb/common/usb_def.h @@ -614,7 +614,7 @@ struct usb_webusb_url_descriptor { char URL[]; } __PACKED; -struct usb_webusb_url_ex_descriptor { +struct usb_webusb_descriptor { uint8_t vendor_code; const uint8_t *string; uint32_t string_len; diff --git a/rt-thread/components/drivers/usb/cherryusb/common/usb_log.h b/rt-thread/components/drivers/usb/cherryusb/common/usb_log.h index 923e800..8c798c7 100644 --- a/rt-thread/components/drivers/usb/cherryusb/common/usb_log.h +++ b/rt-thread/components/drivers/usb/cherryusb/common/usb_log.h @@ -82,4 +82,33 @@ void usb_assert(const char *filename, int linenum); usb_assert(__FILE__, __LINE__); \ } while (0) +#define ___is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static inline void usb_hexdump(const void *ptr, uint32_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + uint32_t i, j; + + (void)buf; + + for (i = 0; i < buflen; i += 16) { + CONFIG_USB_PRINTF("%08X:", i); + + for (j = 0; j < 16; j++) + if (i + j < buflen) { + if ((j % 8) == 0) { + CONFIG_USB_PRINTF(" "); + } + + CONFIG_USB_PRINTF("%02X ", buf[i + j]); + } else + CONFIG_USB_PRINTF(" "); + CONFIG_USB_PRINTF(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + CONFIG_USB_PRINTF("%c", ___is_print(buf[i + j]) ? buf[i + j] : '.'); + CONFIG_USB_PRINTF("\n"); + } +} + #endif /* USB_LOG_H */ diff --git a/rt-thread/components/drivers/usb/cherryusb/common/usb_osal.h b/rt-thread/components/drivers/usb/cherryusb/common/usb_osal.h index f487c48..a3380d1 100644 --- a/rt-thread/components/drivers/usb/cherryusb/common/usb_osal.h +++ b/rt-thread/components/drivers/usb/cherryusb/common/usb_osal.h @@ -58,4 +58,7 @@ void usb_osal_leave_critical_section(size_t flag); void usb_osal_msleep(uint32_t delay); +void *usb_osal_malloc(size_t size); +void usb_osal_free(void *ptr); + #endif /* USB_OSAL_H */ diff --git a/rt-thread/components/drivers/usb/cherryusb/common/usb_version.h b/rt-thread/components/drivers/usb/cherryusb/common/usb_version.h new file mode 100644 index 0000000..d207af9 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/common/usb_version.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_VERSION_H +#define USB_VERSION_H + +#ifdef CHERRYUSB_VERSION +#warning "Please do not define CHERRYUSB_VERSION in usb_config.h" +#undef CHERRYUSB_VERSION +#endif +#ifdef CHERRYUSB_VERSION_STR +#warning "Please do not define CHERRYUSB_VERSION_STR in usb_config.h" +#undef CHERRYUSB_VERSION_STR +#endif + +#define CHERRYUSB_VERSION 0x010402 +#define CHERRYUSB_VERSION_STR "v1.4.2" + +#endif \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/core/usbd_core.c b/rt-thread/components/drivers/usb/cherryusb/core/usbd_core.c index e072d8a..d7fb351 100644 --- a/rt-thread/components/drivers/usb/cherryusb/core/usbd_core.c +++ b/rt-thread/components/drivers/usb/cherryusb/core/usbd_core.c @@ -45,12 +45,18 @@ USB_NOCACHE_RAM_SECTION struct usbd_core_priv { struct usb_msosv1_descriptor *msosv1_desc; struct usb_msosv2_descriptor *msosv2_desc; struct usb_bos_descriptor *bos_desc; + struct usb_webusb_descriptor *webusb_url_desc; #endif /* Buffer used for storing standard, class and vendor request data */ USB_MEM_ALIGNX uint8_t req_data[CONFIG_USBDEV_REQUEST_BUFFER_LEN]; /** Currently selected configuration */ uint8_t configuration; + uint8_t device_address; + bool self_powered; + bool remote_wakeup_support; + bool remote_wakeup_enabled; + bool is_suspend; #ifdef CONFIG_USBDEV_ADVANCE_DESC uint8_t speed; #endif @@ -58,6 +64,7 @@ USB_NOCACHE_RAM_SECTION struct usbd_core_priv { bool test_req; #endif struct usbd_interface *intf[16]; + uint8_t intf_altsetting[16]; uint8_t intf_offset; struct usbd_tx_rx_msg tx_msg[CONFIG_USBDEV_EP_NUM]; @@ -92,6 +99,7 @@ static bool is_device_configured(uint8_t busid) * This function sets endpoint configuration according to one specified in USB * endpoint descriptor and then enables it for data transfers. * + * @param [in] busid busid * @param [in] ep Endpoint descriptor byte array * * @return true if successfully configured and enabled @@ -99,9 +107,9 @@ static bool is_device_configured(uint8_t busid) static bool usbd_set_endpoint(uint8_t busid, const struct usb_endpoint_descriptor *ep) { USB_LOG_DBG("Open ep:0x%02x type:%u mps:%u\r\n", - ep->bEndpointAddress, - USB_GET_ENDPOINT_TYPE(ep->bmAttributes), - USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); + ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(ep->bmAttributes), + USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); if (ep->bEndpointAddress & 0x80) { g_usbd_core[busid].tx_msg[ep->bEndpointAddress & 0x7f].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); @@ -119,6 +127,7 @@ static bool usbd_set_endpoint(uint8_t busid, const struct usb_endpoint_descripto * This function cancels transfers that are associated with endpoint and * disabled endpoint itself. * + * @param [in] busid busid * @param [in] ep Endpoint descriptor byte array * * @return true if successfully deconfigured and disabled @@ -126,8 +135,8 @@ static bool usbd_set_endpoint(uint8_t busid, const struct usb_endpoint_descripto static bool usbd_reset_endpoint(uint8_t busid, const struct usb_endpoint_descriptor *ep) { USB_LOG_DBG("Close ep:0x%02x type:%u\r\n", - ep->bEndpointAddress, - USB_GET_ENDPOINT_TYPE(ep->bmAttributes)); + ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(ep->bmAttributes)); return usbd_ep_close(busid, ep->bEndpointAddress) == 0 ? true : false; } @@ -138,6 +147,7 @@ static bool usbd_reset_endpoint(uint8_t busid, const struct usb_endpoint_descrip * This function parses the list of installed USB descriptors and attempts * to find the specified USB descriptor. * + * @param [in] busid busid * @param [in] type_index Type and index of the descriptor * @param [out] data Descriptor data * @param [out] len Descriptor length @@ -174,6 +184,9 @@ static bool usbd_get_descriptor(uint8_t busid, uint16_t type_index, uint8_t **da break; } desc_len = ((desc[CONF_DESC_wTotalLength]) | (desc[CONF_DESC_wTotalLength + 1] << 8)); + + g_usbd_core[busid].self_powered = (desc[7] & USB_CONFIG_POWERED_MASK) ? true : false; + g_usbd_core[busid].remote_wakeup_support = (desc[7] & USB_CONFIG_REMOTE_WAKEUP) ? true : false; break; case USB_DESCRIPTOR_TYPE_STRING: if (index == USB_OSDESC_STRING_DESC_INDEX) { @@ -336,6 +349,9 @@ static bool usbd_get_descriptor(uint8_t busid, uint16_t type_index, uint8_t **da */ *len = (p[CONF_DESC_wTotalLength]) | (p[CONF_DESC_wTotalLength + 1] << 8); + + g_usbd_core[busid].self_powered = (p[7] & USB_CONFIG_POWERED_MASK) ? true : false; + g_usbd_core[busid].remote_wakeup_support = (p[7] & USB_CONFIG_REMOTE_WAKEUP) ? true : false; } else { /* normally length is at offset 0 */ *len = p[DESC_bLength]; @@ -358,6 +374,7 @@ static bool usbd_get_descriptor(uint8_t busid, uint16_t type_index, uint8_t **da * index and alternate setting by parsing the installed USB descriptor list. * A configuration index of 0 unconfigures the device. * + * @param [in] busid busid * @param [in] config_index Configuration index * @param [in] alt_setting Alternate setting number * @@ -427,6 +444,7 @@ static bool usbd_set_configuration(uint8_t busid, uint8_t config_index, uint8_t /** * @brief set USB interface * + * @param [in] busid busid * @param [in] iface Interface index * @param [in] alt_setting Alternate setting number * @@ -477,10 +495,12 @@ static bool usbd_set_interface(uint8_t busid, uint8_t iface, uint8_t alt_setting if (cur_iface == iface) { ep_desc = (struct usb_endpoint_descriptor *)p; - if (cur_alt_setting != alt_setting) { + if (alt_setting == 0) { ret = usbd_reset_endpoint(busid, ep_desc); - } else { + goto find_end; + } else if (cur_alt_setting == alt_setting) { ret = usbd_set_endpoint(busid, ep_desc); + } else { } } @@ -498,6 +518,7 @@ static bool usbd_set_interface(uint8_t busid, uint8_t iface, uint8_t alt_setting } } +find_end: usbd_class_event_notify_handler(busid, USBD_EVENT_SET_INTERFACE, (void *)if_desc); return ret; @@ -506,6 +527,7 @@ static bool usbd_set_interface(uint8_t busid, uint8_t iface, uint8_t alt_setting /** * @brief handle a standard device request * + * @param [in] busid busid * @param [in] setup The setup packet * @param [in,out] data Data buffer * @param [in,out] len Pointer to data length @@ -522,6 +544,12 @@ static bool usbd_std_device_req_handler(uint8_t busid, struct usb_setup_packet * /* bit 0: self-powered */ /* bit 1: remote wakeup */ (*data)[0] = 0x00; + if (g_usbd_core[busid].self_powered) { + (*data)[0] |= USB_GETSTATUS_SELF_POWERED; + } + if (g_usbd_core[busid].remote_wakeup_enabled) { + (*data)[0] |= USB_GETSTATUS_REMOTE_WAKEUP; + } (*data)[1] = 0x00; *len = 2; break; @@ -530,8 +558,10 @@ static bool usbd_std_device_req_handler(uint8_t busid, struct usb_setup_packet * case USB_REQUEST_SET_FEATURE: if (value == USB_FEATURE_REMOTE_WAKEUP) { if (setup->bRequest == USB_REQUEST_SET_FEATURE) { + g_usbd_core[busid].remote_wakeup_enabled = true; g_usbd_core[busid].event_handler(busid, USBD_EVENT_SET_REMOTE_WAKEUP); } else { + g_usbd_core[busid].remote_wakeup_enabled = false; g_usbd_core[busid].event_handler(busid, USBD_EVENT_CLR_REMOTE_WAKEUP); } } else if (value == USB_FEATURE_TEST_MODE) { @@ -543,6 +573,7 @@ static bool usbd_std_device_req_handler(uint8_t busid, struct usb_setup_packet * break; case USB_REQUEST_SET_ADDRESS: + g_usbd_core[busid].device_address = value; usbd_set_address(busid, value); *len = 0; break; @@ -556,17 +587,20 @@ static bool usbd_std_device_req_handler(uint8_t busid, struct usb_setup_packet * break; case USB_REQUEST_GET_CONFIGURATION: - *data = (uint8_t *)&g_usbd_core[busid].configuration; + (*data)[0] = g_usbd_core[busid].configuration; *len = 1; break; case USB_REQUEST_SET_CONFIGURATION: value &= 0xFF; - if (!usbd_set_configuration(busid, value, 0)) { + if (value == 0) { + g_usbd_core[busid].configuration = 0; + } else if (!usbd_set_configuration(busid, value, 0)) { ret = false; } else { g_usbd_core[busid].configuration = value; + g_usbd_core[busid].is_suspend = false; usbd_class_event_notify_handler(busid, USBD_EVENT_CONFIGURED, NULL); g_usbd_core[busid].event_handler(busid, USBD_EVENT_CONFIGURED); } @@ -589,6 +623,7 @@ static bool usbd_std_device_req_handler(uint8_t busid, struct usb_setup_packet * /** * @brief handle a standard interface request * + * @param [in] busid busid * @param [in] setup The setup packet * @param [in,out] data Data buffer * @param [in,out] len Pointer to data length @@ -600,6 +635,16 @@ static bool usbd_std_interface_req_handler(uint8_t busid, struct usb_setup_packe uint8_t type = HI_BYTE(setup->wValue); uint8_t intf_num = LO_BYTE(setup->wIndex); bool ret = true; + const uint8_t *p; + uint32_t desc_len = 0; + uint32_t current_desc_len = 0; + uint8_t cur_iface = 0xFF; + +#ifdef CONFIG_USBDEV_ADVANCE_DESC + p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); +#else + p = (uint8_t *)g_usbd_core[busid].descriptors; +#endif /* Only when device is configured, then interface requests can be valid. */ if (!is_device_configured(busid)) { @@ -614,7 +659,39 @@ static bool usbd_std_interface_req_handler(uint8_t busid, struct usb_setup_packe break; case USB_REQUEST_GET_DESCRIPTOR: - if (type == 0x22) { /* HID_DESCRIPTOR_TYPE_HID_REPORT */ + if (type == 0x21) { /* HID_DESCRIPTOR_TYPE_HID */ + while (p[DESC_bLength] != 0U) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + current_desc_len = 0; + desc_len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + + break; + + case USB_DESCRIPTOR_TYPE_INTERFACE: + cur_iface = p[INTF_DESC_bInterfaceNumber]; + break; + case 0x21: + if (cur_iface == intf_num) { + *data = (uint8_t *)p; + //memcpy(*data, p, p[DESC_bLength]); + *len = p[DESC_bLength]; + return true; + } + break; + default: + break; + } + + /* skip to next descriptor */ + p += p[DESC_bLength]; + current_desc_len += p[DESC_bLength]; + if (current_desc_len >= desc_len && desc_len) { + break; + } + } + } else if (type == 0x22) { /* HID_DESCRIPTOR_TYPE_HID_REPORT */ for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { struct usbd_interface *intf = g_usbd_core[busid].intf[i]; @@ -633,11 +710,12 @@ static bool usbd_std_interface_req_handler(uint8_t busid, struct usb_setup_packe ret = false; break; case USB_REQUEST_GET_INTERFACE: - (*data)[0] = 0; + (*data)[0] = g_usbd_core[busid].intf_altsetting[intf_num]; *len = 1; break; case USB_REQUEST_SET_INTERFACE: + g_usbd_core[busid].intf_altsetting[intf_num] = LO_BYTE(setup->wValue); usbd_set_interface(busid, setup->wIndex, setup->wValue); *len = 0; break; @@ -653,6 +731,7 @@ static bool usbd_std_interface_req_handler(uint8_t busid, struct usb_setup_packe /** * @brief handle a standard endpoint request * + * @param [in] busid busid * @param [in] setup The setup packet * @param [in,out] data Data buffer * @param [in,out] len Pointer to data length @@ -663,6 +742,7 @@ static bool usbd_std_endpoint_req_handler(uint8_t busid, struct usb_setup_packet { uint8_t ep = (uint8_t)setup->wIndex; bool ret = true; + uint8_t stalled; /* Only when device is configured, then endpoint requests can be valid. */ if (!is_device_configured(busid)) { @@ -671,7 +751,12 @@ static bool usbd_std_endpoint_req_handler(uint8_t busid, struct usb_setup_packet switch (setup->bRequest) { case USB_REQUEST_GET_STATUS: - (*data)[0] = 0x00; + usbd_ep_is_stalled(busid, ep, &stalled); + if (stalled) { + (*data)[0] = 0x01; + } else { + (*data)[0] = 0x00; + } (*data)[1] = 0x00; *len = 2; break; @@ -711,6 +796,7 @@ static bool usbd_std_endpoint_req_handler(uint8_t busid, struct usb_setup_packet /** * @brief handle standard requests (list in chapter 9) * + * @param [in] busid busid * @param [in] setup The setup packet * @param [in,out] data Data buffer * @param [in,out] len Pointer to data length @@ -754,8 +840,7 @@ static int usbd_standard_request_handler(uint8_t busid, struct usb_setup_packet /** * @brief handler for class requests * - * If a custom request handler was installed, this handler is called first. - * + * @param [in] busid busid * @param [in] setup The setup packet * @param [in,out] data Data buffer * @param [in,out] len Pointer to data length @@ -787,8 +872,7 @@ static int usbd_class_request_handler(uint8_t busid, struct usb_setup_packet *se /** * @brief handler for vendor requests * - * If a custom request handler was installed, this handler is called first. - * + * @param [in] busid busid * @param [in] setup The setup packet * @param [in,out] data Data buffer * @param [in,out] len Pointer to data length @@ -841,10 +925,12 @@ static int usbd_vendor_request_handler(uint8_t busid, struct usb_setup_packet *s return -1; } } - } else if (g_usbd_core[busid].descriptors->webusb_url_descriptor) { + } + + if (g_usbd_core[busid].descriptors->webusb_url_descriptor) { if (setup->bRequest == g_usbd_core[busid].descriptors->webusb_url_descriptor->vendor_code) { switch (setup->wIndex) { - case WINUSB_REQUEST_GET_DESCRIPTOR_SET: + case WEBUSB_REQUEST_GET_URL: desclen = g_usbd_core[busid].descriptors->webusb_url_descriptor->string_len; *data = (uint8_t *)g_usbd_core[busid].descriptors->webusb_url_descriptor->string; //memcpy(*data, g_usbd_core[busid].descriptors->webusb_url_descriptor->string, desclen); @@ -897,6 +983,22 @@ static int usbd_vendor_request_handler(uint8_t busid, struct usb_setup_packet *s } } } + + if (g_usbd_core[busid].webusb_url_desc) { + if (setup->bRequest == g_usbd_core[busid].webusb_url_desc->vendor_code) { + switch (setup->wIndex) { + case WEBUSB_REQUEST_GET_URL: + desclen = g_usbd_core[busid].webusb_url_desc->string_len; + *data = (uint8_t *)g_usbd_core[busid].webusb_url_desc->string; + //memcpy(*data, g_usbd_core[busid].webusb_url_desc->string, desclen); + *len = desclen; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } #endif for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { struct usbd_interface *intf = g_usbd_core[busid].intf[i]; @@ -912,6 +1014,7 @@ static int usbd_vendor_request_handler(uint8_t busid, struct usb_setup_packet *s /** * @brief handle setup request( standard/class/vendor/other) * + * @param [in] busid busid * @param [in] setup The setup packet * @param [in,out] data Data buffer * @param [in,out] len Pointer to data length @@ -985,17 +1088,22 @@ void usbd_event_disconnect_handler(uint8_t busid) void usbd_event_resume_handler(uint8_t busid) { + g_usbd_core[busid].is_suspend = false; g_usbd_core[busid].event_handler(busid, USBD_EVENT_RESUME); } void usbd_event_suspend_handler(uint8_t busid) { - g_usbd_core[busid].event_handler(busid, USBD_EVENT_SUSPEND); + if (g_usbd_core[busid].device_address > 0) { + g_usbd_core[busid].is_suspend = true; + g_usbd_core[busid].event_handler(busid, USBD_EVENT_SUSPEND); + } } void usbd_event_reset_handler(uint8_t busid) { usbd_set_address(busid, 0); + g_usbd_core[busid].device_address = 0; g_usbd_core[busid].configuration = 0; #ifdef CONFIG_USBDEV_ADVANCE_DESC g_usbd_core[busid].speed = USB_SPEED_UNKNOWN; @@ -1068,7 +1176,7 @@ void usbd_event_ep0_setup_complete_handler(uint8_t busid, uint8_t *psetup) #ifdef CONFIG_USBDEV_EP0_INDATA_NO_COPY g_usbd_core[busid].ep0_data_buf = buf; #else - memcpy(g_usbd_core[busid].ep0_data_buf, buf, g_usbd_core[busid].ep0_data_buf_residue); + usb_memcpy(g_usbd_core[busid].ep0_data_buf, buf, g_usbd_core[busid].ep0_data_buf_residue); #endif } else { /* use memcpy(*data, xxx, len); has copied into ep0 buffer, we do nothing */ @@ -1091,6 +1199,8 @@ void usbd_event_ep0_in_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbyt { struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + (void)ep; + g_usbd_core[busid].ep0_data_buf += nbytes; g_usbd_core[busid].ep0_data_buf_residue -= nbytes; @@ -1130,6 +1240,8 @@ void usbd_event_ep0_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nby { struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + (void)ep; + if (nbytes > 0) { g_usbd_core[busid].ep0_data_buf += nbytes; g_usbd_core[busid].ep0_data_buf_residue -= nbytes; @@ -1213,6 +1325,11 @@ void usbd_bos_desc_register(uint8_t busid, struct usb_bos_descriptor *desc) { g_usbd_core[busid].bos_desc = desc; } + +void usbd_webusb_desc_register(uint8_t busid, struct usb_webusb_descriptor *desc) +{ + g_usbd_core[busid].webusb_url_desc = desc; +} #endif void usbd_add_interface(uint8_t busid, struct usbd_interface *intf) @@ -1256,7 +1373,30 @@ bool usb_device_is_configured(uint8_t busid) return g_usbd_core[busid].configuration; } -int usbd_initialize(uint8_t busid, uint32_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event)) +bool usb_device_is_suspend(uint8_t busid) +{ + return g_usbd_core[busid].is_suspend; +} + +int usbd_send_remote_wakeup(uint8_t busid) +{ + if (g_usbd_core[busid].remote_wakeup_support && g_usbd_core[busid].remote_wakeup_enabled && g_usbd_core[busid].is_suspend) { + return usbd_set_remote_wakeup(busid); + } else { + if (!g_usbd_core[busid].remote_wakeup_support) { + USB_LOG_ERR("device does not support remote wakeup\r\n"); + } + if (!g_usbd_core[busid].remote_wakeup_enabled) { + USB_LOG_ERR("device remote wakeup is not enabled\r\n"); + } + if (!g_usbd_core[busid].is_suspend) { + USB_LOG_ERR("device is not in suspend state\r\n"); + } + return -1; + } +} + +int usbd_initialize(uint8_t busid, uintptr_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event)) { int ret; struct usbd_bus *bus; @@ -1279,9 +1419,15 @@ int usbd_initialize(uint8_t busid, uint32_t reg_base, void (*event_handler)(uint int usbd_deinitialize(uint8_t busid) { - g_usbd_core[busid].intf_offset = 0; - usb_dc_deinit(busid); - usbd_class_event_notify_handler(busid, USBD_EVENT_DEINIT, NULL); + if (busid >= CONFIG_USBDEV_MAX_BUS) { + USB_LOG_ERR("bus overflow\r\n"); + while (1) { + } + } + g_usbd_core[busid].event_handler(busid, USBD_EVENT_DEINIT); + usbd_class_event_notify_handler(busid, USBD_EVENT_DEINIT, NULL); + usb_dc_deinit(busid); + g_usbd_core[busid].intf_offset = 0; return 0; } diff --git a/rt-thread/components/drivers/usb/cherryusb/core/usbd_core.h b/rt-thread/components/drivers/usb/cherryusb/core/usbd_core.h index 01335f2..71bdb29 100644 --- a/rt-thread/components/drivers/usb/cherryusb/core/usbd_core.h +++ b/rt-thread/components/drivers/usb/cherryusb/core/usbd_core.h @@ -23,6 +23,7 @@ extern "C" { #include "usb_log.h" #include "usb_dc.h" #include "usb_memcpy.h" +#include "usb_version.h" enum usbd_event_type { /* USB DCD IRQ */ @@ -71,13 +72,13 @@ struct usb_descriptor { const char *(*string_descriptor_callback)(uint8_t speed, uint8_t index); const struct usb_msosv1_descriptor *msosv1_descriptor; const struct usb_msosv2_descriptor *msosv2_descriptor; - const struct usb_webusb_url_ex_descriptor *webusb_url_descriptor; + const struct usb_webusb_descriptor *webusb_url_descriptor; const struct usb_bos_descriptor *bos_descriptor; }; struct usbd_bus { uint8_t busid; - uint32_t reg_base; + uintptr_t reg_base; }; extern struct usbd_bus g_usbdev_bus[]; @@ -93,6 +94,7 @@ void usbd_desc_register(uint8_t busid, const uint8_t *desc); void usbd_msosv1_desc_register(uint8_t busid, struct usb_msosv1_descriptor *desc); void usbd_msosv2_desc_register(uint8_t busid, struct usb_msosv2_descriptor *desc); void usbd_bos_desc_register(uint8_t busid, struct usb_bos_descriptor *desc); +void usbd_webusb_desc_register(uint8_t busid, struct usb_webusb_descriptor *desc); #endif void usbd_add_interface(uint8_t busid, struct usbd_interface *intf); @@ -101,8 +103,10 @@ void usbd_add_endpoint(uint8_t busid, struct usbd_endpoint *ep); uint16_t usbd_get_ep_mps(uint8_t busid, uint8_t ep); uint8_t usbd_get_ep_mult(uint8_t busid, uint8_t ep); bool usb_device_is_configured(uint8_t busid); +bool usb_device_is_suspend(uint8_t busid); +int usbd_send_remote_wakeup(uint8_t busid); -int usbd_initialize(uint8_t busid, uint32_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event)); +int usbd_initialize(uint8_t busid, uintptr_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event)); int usbd_deinitialize(uint8_t busid); #ifdef __cplusplus diff --git a/rt-thread/components/drivers/usb/cherryusb/core/usbh_core.c b/rt-thread/components/drivers/usb/cherryusb/core/usbh_core.c index d1fc769..cb36f97 100644 --- a/rt-thread/components/drivers/usb/cherryusb/core/usbh_core.c +++ b/rt-thread/components/drivers/usb/cherryusb/core/usbh_core.c @@ -93,19 +93,22 @@ static const struct usbh_class_driver *usbh_find_class_driver(uint8_t class, uin struct usbh_class_info *index = NULL; for (index = usbh_class_info_table_begin; index < usbh_class_info_table_end; index++) { - if ((index->match_flags & USB_CLASS_MATCH_INTF_CLASS) && !(index->class == class)) { + if ((index->match_flags & USB_CLASS_MATCH_INTF_CLASS) && !(index->bInterfaceClass == class)) { continue; } - if ((index->match_flags & USB_CLASS_MATCH_INTF_SUBCLASS) && !(index->subclass == subclass)) { + if ((index->match_flags & USB_CLASS_MATCH_INTF_SUBCLASS) && !(index->bInterfaceSubClass == subclass)) { continue; } - if ((index->match_flags & USB_CLASS_MATCH_INTF_PROTOCOL) && !(index->protocol == protocol)) { + if ((index->match_flags & USB_CLASS_MATCH_INTF_PROTOCOL) && !(index->bInterfaceProtocol == protocol)) { continue; } if (index->match_flags & USB_CLASS_MATCH_VID_PID && index->id_table) { /* scan id table */ uint32_t i; - for (i = 0; index->id_table[i][0] && index->id_table[i][0] != vid && index->id_table[i][1] != pid; i++) { + for (i = 0; index->id_table[i][0]; i++) { + if (index->id_table[i][0] == vid && index->id_table[i][1] == pid) { + break; + } } /* do not match, continue next */ if (!index->id_table[i][0]) { @@ -486,7 +489,7 @@ int usbh_enumerate(struct usbh_hubport *hport) goto errout; } USB_LOG_INFO("The device has %d interfaces\r\n", ((struct usb_configuration_descriptor *)ep0_request_buffer[hport->bus->busid])->bNumInterfaces); - hport->raw_config_desc = usb_malloc(wTotalLength); + hport->raw_config_desc = usb_osal_malloc(wTotalLength + 1); if (hport->raw_config_desc == NULL) { ret = -USB_ERR_NOMEM; USB_LOG_ERR("No memory to alloc for raw_config_desc\r\n"); @@ -495,6 +498,8 @@ int usbh_enumerate(struct usbh_hubport *hport) config_value = ((struct usb_configuration_descriptor *)ep0_request_buffer[hport->bus->busid])->bConfigurationValue; memcpy(hport->raw_config_desc, ep0_request_buffer[hport->bus->busid], wTotalLength); + hport->raw_config_desc[wTotalLength] = '\0'; + #ifdef CONFIG_USBHOST_GET_STRING_DESC uint8_t string_buffer[128]; @@ -549,7 +554,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wLength = 16; ret = usbh_control_transfer(hport, setup, ep0_request_buffer[hport->bus->busid]); - if (ret < 0 && (ret != -EPERM)) { + if (ret < 0 && (ret != -USB_ERR_STALL)) { USB_LOG_ERR("Failed to get msosv1 compat id,errorcode:%d\r\n", ret); goto errout; } @@ -576,7 +581,7 @@ int usbh_enumerate(struct usbh_hubport *hport) errout: if (hport->raw_config_desc) { - usb_free(hport->raw_config_desc); + usb_osal_free(hport->raw_config_desc); hport->raw_config_desc = NULL; } return ret; @@ -600,7 +605,7 @@ void usbh_hubport_release(struct usbh_hubport *hport) } } -static void usbh_bus_init(struct usbh_bus *bus, uint8_t busid, uint32_t reg_base) +static void usbh_bus_init(struct usbh_bus *bus, uint8_t busid, uintptr_t reg_base) { memset(bus, 0, sizeof(struct usbh_bus)); bus->busid = busid; @@ -613,7 +618,7 @@ static void usbh_bus_init(struct usbh_bus *bus, uint8_t busid, uint32_t reg_base usb_slist_add_tail(&g_bus_head, &bus->list); } -int usbh_initialize(uint8_t busid, uint32_t reg_base) +int usbh_initialize(uint8_t busid, uintptr_t reg_base) { struct usbh_bus *bus; @@ -649,6 +654,12 @@ int usbh_deinitialize(uint8_t busid) { struct usbh_bus *bus; + if (busid >= CONFIG_USBHOST_MAX_BUS) { + USB_LOG_ERR("bus overflow\r\n"); + while (1) { + } + } + bus = &g_usbhost_bus[busid]; usbh_hub_deinitialize(bus); @@ -731,7 +742,7 @@ static void *usbh_list_all_interface_name(struct usbh_hub *hub, const char *devn struct usbh_hub *hub_next; void *priv; - for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + for (uint8_t port = 0; port < hub->nports; port++) { hport = &hub->child[port]; if (hport->connected) { for (uint8_t itf = 0; itf < hport->config.config_desc.bNumInterfaces; itf++) { @@ -760,8 +771,9 @@ static void usbh_list_all_interface_driver(struct usbh_hub *hub) { struct usbh_hubport *hport; struct usbh_hub *hub_next; + const char *speed_table[] = { "error-speed", "low-speed", "full-speed", "high-speed", "wireless-speed", "super-speed", "superplus-speed" }; - for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + for (uint8_t port = 0; port < hub->nports; port++) { hport = &hub->child[port]; if (hport->connected) { for (uint8_t itf = 0; itf < hport->config.config_desc.bNumInterfaces; itf++) { @@ -770,11 +782,12 @@ static void usbh_list_all_interface_driver(struct usbh_hub *hub) USB_LOG_RAW("\t"); } - USB_LOG_RAW("|__Port %u, dev addr:0x%02x, If %u, ClassDriver=%s\r\n", + USB_LOG_RAW("|__Port %u, dev addr:0x%02x, If %u, ClassDriver=%s, %s\r\n", hport->port, hport->dev_addr, itf, - hport->config.intf[itf].class_driver->driver_name); + hport->config.intf[itf].class_driver->driver_name, + speed_table[hport->speed]); if (strcmp(hport->config.intf[itf].class_driver->driver_name, "hub") == 0) { hub_next = hport->config.intf[itf].priv; @@ -794,7 +807,7 @@ static void usbh_list_all_interface_desc(struct usbh_bus *bus, struct usbh_hub * struct usbh_hubport *hport; struct usbh_hub *hub_next; - for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + for (uint8_t port = 0; port < hub->nports; port++) { hport = &hub->child[port]; if (hport->connected) { USB_LOG_RAW("\r\nBus %u, Hub %u, Port %u, dev addr:0x%02x, VID:PID 0x%04x:0x%04x\r\n", @@ -821,6 +834,37 @@ static void usbh_list_all_interface_desc(struct usbh_bus *bus, struct usbh_hub * } } +static struct usbh_hubport *usbh_list_all_hubport(struct usbh_hub *hub, uint8_t hub_index, uint8_t hub_port) +{ + struct usbh_hubport *hport; + struct usbh_hub *hub_next; + + if (hub->index == hub_index) { + hport = &hub->child[hub_port - 1]; + return hport; + } else { + for (uint8_t port = 0; port < hub->nports; port++) { + hport = &hub->child[port]; + if (hport->connected) { + for (uint8_t itf = 0; itf < hport->config.config_desc.bNumInterfaces; itf++) { + if (hport->config.intf[itf].class_driver && hport->config.intf[itf].class_driver->driver_name) { + if (strcmp(hport->config.intf[itf].class_driver->driver_name, "hub") == 0) { + hub_next = hport->config.intf[itf].priv; + + if (hub_next && hub_next->connected) { + hport = usbh_list_all_hubport(hub_next, hub_index, hub_port); + if (hport) { + return hport; + } + } + } + } + } + } + } + } + return NULL; +} void *usbh_find_class_instance(const char *devname) { usb_slist_t *bus_list; @@ -845,6 +889,23 @@ void *usbh_find_class_instance(const char *devname) return NULL; } +struct usbh_hubport *usbh_find_hubport(uint8_t busid, uint8_t hub_index, uint8_t hub_port) +{ + struct usbh_hub *hub; + struct usbh_bus *bus; + struct usbh_hubport *hport; + size_t flags; + + flags = usb_osal_enter_critical_section(); + + bus = &g_usbhost_bus[busid]; + hub = &bus->hcd.roothub; + + hport = usbh_list_all_hubport(hub, hub_index, hub_port); + usb_osal_leave_critical_section(flags); + return hport; +} + int lsusb(int argc, char **argv) { usb_slist_t *bus_list; @@ -888,7 +949,7 @@ int lsusb(int argc, char **argv) USB_LOG_RAW("/: Bus %u, Hub %u, ports=%u, is roothub\r\n", bus->busid, hub->index, - hub->hub_desc.bNbrPorts); + hub->nports); usbh_list_all_interface_driver(hub); } } diff --git a/rt-thread/components/drivers/usb/cherryusb/core/usbh_core.h b/rt-thread/components/drivers/usb/cherryusb/core/usbh_core.h index 3210988..eaddb30 100644 --- a/rt-thread/components/drivers/usb/cherryusb/core/usbh_core.h +++ b/rt-thread/components/drivers/usb/cherryusb/core/usbh_core.h @@ -21,6 +21,7 @@ #include "usb_osal.h" #include "usbh_hub.h" #include "usb_memcpy.h" +#include "usb_version.h" #ifdef __cplusplus extern "C" { @@ -60,9 +61,9 @@ extern "C" { struct usbh_class_info { uint8_t match_flags; /* Used for product specific matches; range is inclusive */ - uint8_t class; /* Base device class code */ - uint8_t subclass; /* Sub-class, depends on base class. Eg. */ - uint8_t protocol; /* Protocol, depends on base class. Eg. */ + uint8_t bInterfaceClass; /* Base device class code */ + uint8_t bInterfaceSubClass; /* Sub-class, depends on base class. Eg. */ + uint8_t bInterfaceProtocol; /* Protocol, depends on base class. Eg. */ const uint16_t (*id_table)[2]; /* List of Vendor/Product ID pairs */ const struct usbh_class_driver *class_driver; }; @@ -101,6 +102,9 @@ struct usbh_hubport { uint8_t port; /* Hub port index */ uint8_t dev_addr; /* device address */ uint8_t speed; /* device speed */ + uint8_t depth; /* distance from root hub */ + uint8_t route; /* route string */ + uint8_t slot_id; /* slot id */ struct usb_device_descriptor device_desc; struct usbh_configuration config; const char *iManufacturer; @@ -109,6 +113,7 @@ struct usbh_hubport { uint8_t *raw_config_desc; struct usb_setup_packet *setup; struct usbh_hub *parent; + struct usbh_hub *self; /* if this hubport is a hub */ struct usbh_bus *bus; struct usb_endpoint_descriptor ep0; struct usbh_urb ep0_urb; @@ -120,7 +125,13 @@ struct usbh_hub { bool is_roothub; uint8_t index; uint8_t hub_addr; - struct usb_hub_descriptor hub_desc; + uint8_t speed; + uint8_t nports; + uint8_t powerdelay; + uint8_t tt_think; + bool ismtt; + struct usb_hub_descriptor hub_desc; /* USB 2.0 only */ + struct usb_hub_ss_descriptor hub_ss_desc; /* USB 3.0 only */ struct usbh_hubport child[CONFIG_USBHOST_MAX_EHPORTS]; struct usbh_hubport *parent; struct usbh_bus *bus; @@ -143,9 +154,9 @@ struct usbh_devaddr_map { }; struct usbh_hcd { - uint32_t reg_base; + uintptr_t reg_base; uint8_t hcd_id; - uint8_t roothub_intbuf[1]; + uint8_t roothub_intbuf[2]; /* at most 15 roothub ports */ struct usbh_hub roothub; }; @@ -261,9 +272,10 @@ int usbh_get_string_desc(struct usbh_hubport *hport, uint8_t index, uint8_t *out */ int usbh_set_interface(struct usbh_hubport *hport, uint8_t intf, uint8_t altsetting); -int usbh_initialize(uint8_t busid, uint32_t reg_base); +int usbh_initialize(uint8_t busid, uintptr_t reg_base); int usbh_deinitialize(uint8_t busid); void *usbh_find_class_instance(const char *devname); +struct usbh_hubport *usbh_find_hubport(uint8_t busid, uint8_t hub_index, uint8_t hub_port); int lsusb(int argc, char **argv); diff --git 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+#include "FreeRTOS.h" +#include "task.h" +#include "event_groups.h" +#include "csh.h" +#include "usbd_core.h" +#include "usbd_adb.h" +#include "chry_ringbuffer.h" + +static chry_ringbuffer_t shell_rb; +static uint8_t mempool[1024]; + +#ifndef task_repl_PRIORITY +#define task_repl_PRIORITY (configMAX_PRIORITIES - 4U) +#endif + +#ifndef task_exec_PRIORITY +#define task_exec_PRIORITY (configMAX_PRIORITIES - 5U) +#endif + +static chry_shell_t csh; +static volatile bool login = false; + +static StaticTask_t task_buffer_repl; +static StaticTask_t task_buffer_exec; + +static StackType_t task_stack_repl[1024]; +static StackType_t task_stack_exec[1024]; + +static TaskHandle_t task_hdl_repl = NULL; +static TaskHandle_t task_hdl_exec = NULL; + +static EventGroupHandle_t event_hdl; +static StaticEventGroup_t event_grp; + +void usbd_adb_notify_shell_read(uint8_t *data, uint32_t len) +{ + chry_ringbuffer_write(&shell_rb, data, len); + + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + xEventGroupSetBitsFromISR(event_hdl, 0x10, &xHigherPriorityTaskWoken); + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); +} + +void usbd_adb_notify_write_done(void) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + xEventGroupSetBitsFromISR(event_hdl, 0x20, &xHigherPriorityTaskWoken); + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); +} + +static uint16_t csh_sput_cb(chry_readline_t *rl, const void *data, uint16_t size) +{ + (void)rl; + + if (!usb_device_is_configured(0)) { + return size; + } + + if (usbd_adb_can_write() && size) { + usbd_abd_write(ADB_SHELL_LOALID, data, size); + xEventGroupWaitBits(event_hdl, 0x20, pdTRUE, pdFALSE, portMAX_DELAY); + } + + return size; +} + +static uint16_t csh_sget_cb(chry_readline_t *rl, void *data, uint16_t size) +{ + (void)rl; + + return chry_ringbuffer_read(&shell_rb, data, size); +} + +static void wait_char(void) +{ + EventBits_t event; +wait: + /* In order to lock the log from being disrupted , wait for REPL task execution to complete */ + event = xEventGroupWaitBits(event_hdl, (0x10 | 0x01 | 0x04), pdTRUE, pdFALSE, portMAX_DELAY); + if ((event & 0x10) == 0) { + if (event & 0x01) { + chry_readline_erase_line(&csh.rl); + xEventGroupSetBits(event_hdl, 0x02); + } + if (event & 0x04) { + chry_readline_edit_refresh(&csh.rl); + xEventGroupSetBits(event_hdl, 0x08); + } + + goto wait; + } +} + +static void task_repl(void *param) +{ + (void)param; + int ret; + volatile uint8_t *pexec = (void *)&csh.exec; + + for (;;) { + restart: + if (login) { + goto repl; + } else { + } + + ret = csh_login(&csh); + if (ret == 0) { + login = true; + } else if (ret == 1) { + /*!< no enough char */ + wait_char(); + continue; + } else { + continue; + } + + repl: + ret = chry_shell_task_repl(&csh); + + if (ret == -1) { + /*!< error */ + goto restart; + } else if (ret == 1) { + /*!< no enough char */ + wait_char(); + } else { + /*!< restart */ + } + + /*!< check flag */ + if (*pexec == CSH_STATUS_EXEC_DONE) { + *pexec = CSH_STATUS_EXEC_IDLE; + chry_readline_auto_refresh(&csh.rl, true); + chry_readline_ignore(&csh.rl, false); + chry_readline_edit_refresh(&csh.rl); + } + + if (login == false) { + chry_readline_erase_line(&csh.rl); + csh.rl.noblock = false; + } + } +} + +static void task_exec(void *param) +{ + (void)param; + + /*!< execute shell command */ + chry_shell_task_exec(&csh); + + /*!< notify REPL task execute done */ + xEventGroupSetBits(event_hdl, 0x10); + + /*!< wait for REPL task delete */ + vTaskSuspend(NULL); +} + +int chry_shell_port_create_context(chry_shell_t *csh, int argc, const char **argv) +{ + volatile TaskHandle_t *p_task_hdl_exec = (void *)&task_hdl_exec; + (void)csh; + (void)argc; + (void)argv; + + if (*p_task_hdl_exec != NULL) { + vTaskDelete(*p_task_hdl_exec); + } + + *p_task_hdl_exec = xTaskCreateStatic(task_exec, "task_exec", 1024U, NULL, task_exec_PRIORITY, task_stack_exec, &task_buffer_exec); + return 0; +} + +void chry_shell_port_default_handler(chry_shell_t *csh, int sig) +{ + volatile uint8_t *pexec = (void *)&csh->exec; + volatile TaskHandle_t *p_task_hdl_exec = (void *)&task_hdl_exec; + + switch (sig) { + case CSH_SIGINT: + case CSH_SIGQUIT: + case CSH_SIGKILL: + case CSH_SIGTERM: + break; + default: + return; + } + + /*!< force delete task */ + if (*p_task_hdl_exec != NULL) { + vTaskDelete(task_hdl_exec); + *p_task_hdl_exec = NULL; + } + + switch (sig) { + case CSH_SIGINT: + csh->rl.sput(&csh->rl, "^SIGINT" CONFIG_CSH_NEWLINE, sizeof("^SIGINT" CONFIG_CSH_NEWLINE) - 1); + break; + case CSH_SIGQUIT: + csh->rl.sput(&csh->rl, "^SIGQUIT" CONFIG_CSH_NEWLINE, sizeof("^SIGQUIT" CONFIG_CSH_NEWLINE) - 1); + break; + case CSH_SIGKILL: + csh->rl.sput(&csh->rl, "^SIGKILL" CONFIG_CSH_NEWLINE, sizeof("^SIGKILL" CONFIG_CSH_NEWLINE) - 1); + break; + case CSH_SIGTERM: + csh->rl.sput(&csh->rl, "^SIGTERM" CONFIG_CSH_NEWLINE, sizeof("^SIGTERM" CONFIG_CSH_NEWLINE) - 1); + break; + default: + return; + } + + *pexec = CSH_STATUS_EXEC_IDLE; + chry_readline_auto_refresh(&csh->rl, true); + chry_readline_ignore(&csh->rl, false); + chry_readline_edit_refresh(&csh->rl); +} + +int shell_init(bool need_login) +{ + chry_shell_init_t csh_init; + + if (chry_ringbuffer_init(&shell_rb, mempool, sizeof(mempool))) { + return -1; + } + + if (need_login) { + login = false; + } else { + login = true; + } + + /*!< I/O callback */ + csh_init.sput = csh_sput_cb; + csh_init.sget = csh_sget_cb; + +#if defined(CONFIG_CSH_SYMTAB) && CONFIG_CSH_SYMTAB + extern const int __fsymtab_start; + extern const int __fsymtab_end; + extern const int __vsymtab_start; + extern const int __vsymtab_end; + + /*!< get table from ld symbol */ + csh_init.command_table_beg = &__fsymtab_start; + csh_init.command_table_end = &__fsymtab_end; + csh_init.variable_table_beg = &__vsymtab_start; + csh_init.variable_table_end = &__vsymtab_end; +#endif + +#if defined(CONFIG_CSH_PROMPTEDIT) && CONFIG_CSH_PROMPTEDIT + static char csh_prompt_buffer[128]; + + /*!< set prompt buffer */ + csh_init.prompt_buffer = csh_prompt_buffer; + csh_init.prompt_buffer_size = sizeof(csh_prompt_buffer); +#endif + +#if defined(CONFIG_CSH_HISTORY) && CONFIG_CSH_HISTORY + static char csh_history_buffer[128]; + + /*!< set history buffer */ + csh_init.history_buffer = csh_history_buffer; + csh_init.history_buffer_size = sizeof(csh_history_buffer); +#endif + +#if defined(CONFIG_CSH_LNBUFF_STATIC) && CONFIG_CSH_LNBUFF_STATIC + static char csh_line_buffer[128]; + + /*!< set linebuffer */ + csh_init.line_buffer = csh_line_buffer; + csh_init.line_buffer_size = sizeof(csh_line_buffer); +#endif + + csh_init.uid = 0; + csh_init.user[0] = "cherry"; + + /*!< The port hash function is required, + and the strcmp attribute is used weakly by default, + int chry_shell_port_hash_strcmp(const char *hash, const char *str); */ + csh_init.hash[0] = "12345678"; /*!< If there is no password, set to NULL */ + csh_init.host = "cherryadb"; + csh_init.user_data = NULL; + + int ret = chry_shell_init(&csh, &csh_init); + if (ret) { + return -1; + } + + task_hdl_exec = NULL; + event_hdl = xEventGroupCreateStatic(&event_grp); + task_hdl_repl = xTaskCreateStatic(task_repl, "task_repl", 1024U, NULL, task_repl_PRIORITY, task_stack_repl, &task_buffer_repl); + + return 0; +} + +void shell_lock(void) +{ + xEventGroupSetBits(event_hdl, 0x01); + xEventGroupWaitBits(event_hdl, 0x02, pdTRUE, pdTRUE, portMAX_DELAY); +} + +void shell_unlock(void) +{ + xEventGroupSetBits(event_hdl, 0x04); + xEventGroupWaitBits(event_hdl, 0x08, pdTRUE, pdTRUE, portMAX_DELAY); +} + +static int csh_exit(int argc, char **argv) +{ + (void)argc; + (void)argv; + + usbd_adb_close(ADB_SHELL_LOALID); + + return 0; +} +CSH_SCMD_EXPORT_ALIAS(csh_exit, exit, ); + +#define __ENV_PATH "/sbin:/bin" +const char ENV_PATH[] = __ENV_PATH; +CSH_RVAR_EXPORT(ENV_PATH, PATH, sizeof(__ENV_PATH)); + +#define __ENV_ZERO "" +const char ENV_ZERO[] = __ENV_ZERO; +CSH_RVAR_EXPORT(ENV_ZERO, ZERO, sizeof(__ENV_ZERO)); diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/adb/usbd_adb_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/adb/usbd_adb_template.c new file mode 100644 index 0000000..2090dae --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/demo/adb/usbd_adb_template.c @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_adb.h" + +/*!< endpoint address */ +#define WINUSB_IN_EP 0x81 +#define WINUSB_OUT_EP 0x02 + +#define USBD_VID 0xFFFF +#define USBD_PID 0xFFFF +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +/*!< config descriptor size */ +#define USB_CONFIG_SIZE (9 + 9 + 7 + 7) + +#ifdef CONFIG_USB_HS +#define WINUSB_MAX_MPS 512 +#else +#define WINUSB_MAX_MPS 64 +#endif + +#define WCID_VENDOR_CODE 0x17 +#define ADB_INTF_NUM 0 + +__ALIGN_BEGIN const uint8_t WCID_StringDescriptor_MSOS[18] __ALIGN_END = { + /////////////////////////////////////// + /// MS OS string descriptor + /////////////////////////////////////// + 0x12, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + /* MSFT100 */ + 'M', 0x00, 'S', 0x00, 'F', 0x00, 'T', 0x00, /* wcChar_7 */ + '1', 0x00, '0', 0x00, '0', 0x00, /* wcChar_7 */ + WCID_VENDOR_CODE, /* bVendorCode */ + 0x00, /* bReserved */ +}; + +__ALIGN_BEGIN const uint8_t WINUSB_WCIDDescriptor[40] __ALIGN_END = { + /////////////////////////////////////// + /// WCID descriptor + /////////////////////////////////////// + 0x28, 0x00, 0x00, 0x00, /* dwLength */ + 0x00, 0x01, /* bcdVersion */ + 0x04, 0x00, /* wIndex */ + 0x01, /* bCount */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bReserved_7 */ + + /////////////////////////////////////// + /// WCID function descriptor + /////////////////////////////////////// + ADB_INTF_NUM, /* bFirstInterfaceNumber */ + 0x01, /* bReserved */ + /* Compatible ID */ + 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, /* cCID_8: WINUSB */ + /* */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* cSubCID_8 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bReserved_6 */ +}; + +__ALIGN_BEGIN const uint8_t WINUSB_IF0_WCIDProperties[142] __ALIGN_END = { + /////////////////////////////////////// + /// WCID property descriptor + /////////////////////////////////////// + 0x8e, 0x00, 0x00, 0x00, /* dwLength */ + 0x00, 0x01, /* bcdVersion */ + 0x05, 0x00, /* wIndex */ + 0x01, 0x00, /* wCount */ + + /////////////////////////////////////// + /// registry propter descriptor + /////////////////////////////////////// + 0x84, 0x00, 0x00, 0x00, /* dwSize */ + 0x01, 0x00, 0x00, 0x00, /* dwPropertyDataType */ + 0x28, 0x00, /* wPropertyNameLength */ + /* DeviceInterfaceGUID */ + 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, /* wcName_20 */ + 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, /* wcName_20 */ + 't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, /* wcName_20 */ + 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, /* wcName_20 */ + 'U', 0x00, 'I', 0x00, 'D', 0x00, 0x00, 0x00, /* wcName_20 */ + 0x4e, 0x00, 0x00, 0x00, /* dwPropertyDataLength */ + /* {1D4B2365-4749-48EA-B38A-7C6FDDDD7E26} */ + '{', 0x00, '1', 0x00, 'D', 0x00, '4', 0x00, /* wcData_39 */ + 'B', 0x00, '2', 0x00, '3', 0x00, '6', 0x00, /* wcData_39 */ + '5', 0x00, '-', 0x00, '4', 0x00, '7', 0x00, /* wcData_39 */ + '4', 0x00, '9', 0x00, '-', 0x00, '4', 0x00, /* wcData_39 */ + '8', 0x00, 'E', 0x00, 'A', 0x00, '-', 0x00, /* wcData_39 */ + 'B', 0x00, '3', 0x00, '8', 0x00, 'A', 0x00, /* wcData_39 */ + '-', 0x00, '7', 0x00, 'C', 0x00, '6', 0x00, /* wcData_39 */ + 'F', 0x00, 'D', 0x00, 'D', 0x00, 'D', 0x00, /* wcData_39 */ + 'D', 0x00, '7', 0x00, 'E', 0x00, '2', 0x00, /* wcData_39 */ + '6', 0x00, '}', 0x00, 0x00, 0x00, /* wcData_39 */ +}; + +const uint8_t *WINUSB_IFx_WCIDProperties[] = { + WINUSB_IF0_WCIDProperties, +}; + +struct usb_msosv1_descriptor msosv1_desc = { + .string = WCID_StringDescriptor_MSOS, + .vendor_code = WCID_VENDOR_CODE, + .compat_id = WINUSB_WCIDDescriptor, + .comp_id_property = WINUSB_IFx_WCIDProperties, +}; + +/*!< global descriptor */ +static const uint8_t adb_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0100, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + ADB_DESCRIPTOR_INIT(ADB_INTF_NUM, WINUSB_IN_EP, WINUSB_OUT_EP, WINUSB_MAX_MPS), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'A', 0x00, /* wcChar6 */ + 'D', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x1C, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'A', 0x00, /* wcChar6 */ + 'D', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + '2', 0x00, /* wcChar9 */ + '0', 0x00, /* wcChar10 */ + '2', 0x00, /* wcChar11 */ + '4', 0x00, /* wcChar12 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x02, + 0x02, + 0x01, + 0x40, + 0x00, + 0x00, +#endif + 0x00 +}; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +static struct usbd_interface intf0; + +extern int shell_init(bool need_login); +void cherryadb_init(uint8_t busid, uint32_t reg_base) +{ + /* default password is : 12345678 */ + /* shell_init() must be called in-task */ + if (0 != shell_init(false)) { + /* shell failed to be initialized */ + printf("Failed to initialize shell\r\n"); + for (;;) { + ; + } + } + + usbd_desc_register(busid, adb_descriptor); + usbd_add_interface(busid, usbd_adb_init_intf(busid, &intf0, WINUSB_IN_EP, WINUSB_OUT_EP)); + usbd_initialize(busid, reg_base, usbd_event_handler); +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/audio_v1_mic_multichan_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/audio_v1_mic_multichan_template.c index a80a221..56684e4 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/audio_v1_mic_multichan_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/audio_v1_mic_multichan_template.c @@ -144,7 +144,7 @@ const uint8_t audio_v1_descriptor[] = { 0x00, 0x00, 0x40, - 0x01, + 0x00, 0x00, #endif 0x00 @@ -212,7 +212,7 @@ struct audio_entity_info audio_entity_table[] = { .ep = AUDIO_IN_EP }, }; -void audio_v1_init(uint8_t busid, uint32_t reg_base) +void audio_v1_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, audio_v1_descriptor); usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0100, audio_entity_table, 1)); diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/audio_v1_mic_speaker_multichan_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/audio_v1_mic_speaker_multichan_template.c index fbd53e3..4beccc6 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/audio_v1_mic_speaker_multichan_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/audio_v1_mic_speaker_multichan_template.c @@ -139,7 +139,7 @@ const uint8_t audio_v1_descriptor[] = { 0x00, 0x00, 0x40, - 0x01, + 0x00, 0x00, #endif 0x00 @@ -238,7 +238,7 @@ struct audio_entity_info audio_entity_table[] = { .ep = AUDIO_OUT_EP }, }; -void audio_v1_init(uint8_t busid, uint32_t reg_base) +void audio_v1_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, audio_v1_descriptor); usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0100, audio_entity_table, 2)); diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/audio_v2_mic_multichan_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/audio_v2_mic_multichan_template.c index bf85762..c00fffa 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/audio_v2_mic_multichan_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/audio_v2_mic_multichan_template.c @@ -149,7 +149,7 @@ const uint8_t audio_v2_descriptor[] = { 0x00, 0x00, 0x40, - 0x01, + 0x00, 0x00, #endif 0x00 @@ -229,7 +229,7 @@ struct audio_entity_info audio_entity_table[] = { .ep = AUDIO_IN_EP }, }; -void audio_v2_init(uint8_t busid, uint32_t reg_base) +void audio_v2_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, audio_v2_descriptor); usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0200, audio_entity_table, 2)); diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/audio_v2_mic_speaker_multichan_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/audio_v2_mic_speaker_multichan_template.c index e8afabe..0aebe57 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/audio_v2_mic_speaker_multichan_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/audio_v2_mic_speaker_multichan_template.c @@ -196,7 +196,7 @@ uint8_t audio_v2_descriptor[] = { 0x00, 0x00, 0x40, - 0x01, + 0x00, 0x00, #endif 0x00 @@ -346,7 +346,7 @@ struct audio_entity_info audio_entity_table[] = { .ep = AUDIO_IN_EP }, }; -void audio_v2_init(uint8_t busid, uint32_t reg_base) +void audio_v2_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, audio_v2_descriptor); usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0200, audio_entity_table, 4)); diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/audio_v2_speaker_multichan_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/audio_v2_speaker_multichan_template.c index 3fc7a48..0abb677 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/audio_v2_speaker_multichan_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/audio_v2_speaker_multichan_template.c @@ -149,7 +149,7 @@ const uint8_t audio_v2_descriptor[] = { 0x00, 0x00, 0x40, - 0x01, + 0x00, 0x00, #endif 0x00 @@ -247,7 +247,7 @@ struct audio_entity_info audio_entity_table[] = { .ep = AUDIO_OUT_EP }, }; -void audio_v2_init(uint8_t busid, uint32_t reg_base) +void audio_v2_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, audio_v2_descriptor); usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0200, audio_entity_table, 2)); diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/bootuf2.c b/rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/bootuf2.c new file mode 100644 index 0000000..c4c6ee5 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/bootuf2.c @@ -0,0 +1,463 @@ +/* + * Copyright (c) 2024, sakumisu + * Copyright (c) 2024, Egahp + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "bootuf2.h" +#include "usbd_core.h" + +char file_INFO[] = { + "CherryUSB UF2 BOOT\r\n" + "Model: " CONFIG_PRODUCT "\r\n" + "Board-ID: " CONFIG_BOARD "\r\n" +}; + +const char file_IDEX[] = { + "\n" + "" + "" + "" + "" + "\n" +}; + +const char file_JOIN[] = { + "\n" + "" + "" + "" + "" + "\n" +}; + +const char file_ID__[12] = BOOTUF2_FAMILYID_ARRAY; + +static struct bootuf2_FILE files[] = { + [0] = { .Name = file_ID__, .Content = NULL, .FileSize = 0 }, + [1] = { .Name = "INFO_UF2TXT", .Content = file_INFO, .FileSize = sizeof(file_INFO) - 1 }, + [2] = { .Name = "INDEX HTM", .Content = file_IDEX, .FileSize = sizeof(file_IDEX) - 1 }, + [3] = { .Name = "JOIN HTM", .Content = file_JOIN, .FileSize = sizeof(file_JOIN) - 1 }, +}; + +struct bootuf2_data { + const struct bootuf2_DBR *const DBR; + struct bootuf2_STATE *const STATE; + uint8_t *const fbuff; + uint8_t *const erase; + size_t page_count; + uint8_t *const cache; + const size_t cache_size; + uint32_t cached_address; + size_t cached_bytes; +}; + +/*!< define DBRs */ +static const struct bootuf2_DBR bootuf2_DBR = { + .JMPInstruction = { 0xEB, 0x3C, 0x90 }, + .OEM = "UF2 UF2 ", + .BPB = { + .BytesPerSector = CONFIG_BOOTUF2_SECTOR_SIZE, + .SectorsPerCluster = CONFIG_BOOTUF2_SECTOR_PER_CLUSTER, + .ReservedSectors = CONFIG_BOOTUF2_SECTOR_RESERVED, + .NumberOfFAT = CONFIG_BOOTUF2_NUM_OF_FAT, + .RootEntries = CONFIG_BOOTUF2_ROOT_ENTRIES, + .Sectors = (BOOTUF2_SECTORS(0) > 0xFFFF) ? 0 : BOOTUF2_SECTORS(0), + .MediaDescriptor = 0xF8, + .SectorsPerFAT = BOOTUF2_SECTORS_PER_FAT(0), + .SectorsPerTrack = 1, + .Heads = 1, + .HiddenSectors = 0, + .SectorsOver32MB = (BOOTUF2_SECTORS(0) > 0xFFFF) ? BOOTUF2_SECTORS(0) : 0, + .BIOSDrive = 0x80, + .Reserved = 0, + .ExtendBootSignature = 0x29, + .VolumeSerialNumber = 0x00420042, + .VolumeLabel = "CHERRYUF2", + .FileSystem = "FAT16 ", + }, +}; + +/*!< define mask */ +static uint8_t __attribute__((aligned(4))) bootuf2_mask[BOOTUF2_BLOCKSMAX / 8 + 1] = { 0 }; + +/*!< define state */ +static struct bootuf2_STATE bootuf2_STATE = { + .NumberOfBlock = 0, + .NumberOfWritten = 0, + .Mask = bootuf2_mask, + .Enable = 1, +}; + +/*!< define flash cache */ +static uint8_t __attribute__((aligned(4))) bootuf2_disk_cache[CONFIG_BOOTUF2_CACHE_SIZE]; + +/*!< define flash buff */ +static uint8_t __attribute__((aligned(4))) bootuf2_disk_fbuff[256]; + +/*!< define erase flag buff */ +static uint8_t __attribute__((aligned(4))) bootuf2_disk_erase[BOOTUF2_DIVCEIL(CONFIG_BOOTUF2_PAGE_COUNTMAX, 8)]; + +/*!< define disk */ +static struct bootuf2_data bootuf2_disk = { + .DBR = &bootuf2_DBR, + .STATE = &bootuf2_STATE, + .fbuff = bootuf2_disk_fbuff, + .erase = bootuf2_disk_erase, + .cache = bootuf2_disk_cache, + .cache_size = sizeof(bootuf2_disk_cache), +}; + +static void fname_copy(char *dst, char const *src, uint16_t len) +{ + for (size_t i = 0; i < len; ++i) { + if (*src) + *dst++ = *src++; + else + *dst++ = ' '; + } +} + +static void fcalculate_cluster(struct bootuf2_data *ctx) +{ + /*!< init files cluster */ + uint16_t cluster_beg = 2; + for (int i = 0; i < ARRAY_SIZE(files); i++) { + files[i].ClusterBeg = cluster_beg; + files[i].ClusterEnd = -1 + cluster_beg + + BOOTUF2_DIVCEIL(files[i].FileSize, + ctx->DBR->BPB.BytesPerSector * + ctx->DBR->BPB.SectorsPerCluster); + cluster_beg = files[i].ClusterEnd + 1; + } +} + +static int ffind_by_cluster(uint32_t cluster) +{ + if (cluster >= 0xFFF0) { + return -1; + } + + for (uint32_t i = 0; i < ARRAY_SIZE(files); i++) { + if ((files[i].ClusterBeg <= cluster) && + (cluster <= files[i].ClusterEnd)) { + return i; + } + } + + return -1; +} + +static bool bootuf2block_check_writable(struct bootuf2_STATE *STATE, + struct bootuf2_BLOCK *uf2, uint32_t block_max) +{ + if (uf2->NumberOfBlock) { + if (uf2->BlockIndex < block_max) { + uint8_t mask = 1 << (uf2->BlockIndex % 8); + uint32_t pos = uf2->BlockIndex / 8; + + if ((STATE->Mask[pos] & mask) == 0) { + return true; + } + } + } + + return false; +} + +static void bootuf2block_state_update(struct bootuf2_STATE *STATE, + struct bootuf2_BLOCK *uf2, uint32_t block_max) +{ + if (uf2->NumberOfBlock) { + if (STATE->NumberOfBlock != uf2->NumberOfBlock) { + if ((uf2->NumberOfBlock >= BOOTUF2_BLOCKSMAX) || + STATE->NumberOfBlock) { + /*!< uf2 block only can be update once */ + /*!< this will cause never auto reboot */ + STATE->NumberOfBlock = 0xffffffff; + } else { + STATE->NumberOfBlock = uf2->NumberOfBlock; + } + } + + if (uf2->BlockIndex < block_max) { + uint8_t mask = 1 << (uf2->BlockIndex % 8); + uint32_t pos = uf2->BlockIndex / 8; + + if ((STATE->Mask[pos] & mask) == 0) { + STATE->Mask[pos] |= mask; + STATE->NumberOfWritten++; + } + } + } + + USB_LOG_DBG("UF2 block total %d written %d index %d\r\n", + uf2->NumberOfBlock, STATE->NumberOfWritten, uf2->BlockIndex); +} + +static bool bootuf2block_state_check(struct bootuf2_STATE *STATE) +{ + return (STATE->NumberOfWritten >= STATE->NumberOfBlock) && + STATE->NumberOfBlock; +} + +static int bootuf2_flash_flush(struct bootuf2_data *ctx) +{ + int err; + + if (ctx->cached_bytes == 0) { + return 0; + } + + err = bootuf2_flash_write(ctx->cached_address, ctx->cache, ctx->cached_bytes); + + if (err) { + USB_LOG_ERR("UF2 slot flash write error %d at offset %08lx len %d\r\n", + err, ctx->cached_address, ctx->cached_bytes); + return -1; + } + + ctx->cached_bytes = 0; + + return 0; +} + +int bootuf2_flash_write_internal(struct bootuf2_data *ctx, struct bootuf2_BLOCK *uf2) +{ + /*!< 1.cache not empty and address not continue */ + /*!< 2.cache full */ + if ((ctx->cached_bytes && ((ctx->cached_address + ctx->cached_bytes) != uf2->TargetAddress)) || + (ctx->cached_bytes == ctx->cache_size)) { + int err = bootuf2_flash_flush(ctx); + if (err) + return err; + } + + /*!< write len always is 256, cache_size always is a multiple of 256 */ + memcpy(ctx->cache + ctx->cached_bytes, uf2->Data, uf2->PayloadSize); + + ctx->cached_address = uf2->TargetAddress - ctx->cached_bytes; + ctx->cached_bytes += uf2->PayloadSize; + + return 0; +} + +void bootuf2_init(void) +{ + struct bootuf2_data *ctx; + + ctx = &bootuf2_disk; + + fcalculate_cluster(ctx); + + ctx->cached_bytes = 0; + ctx->cached_address = 0; +} + +int boot2uf2_read_sector(uint32_t start_sector, uint8_t *buff, uint32_t sector_count) +{ + struct bootuf2_data *ctx; + + ctx = &bootuf2_disk; + + while (sector_count) { + memset(buff, 0, ctx->DBR->BPB.BytesPerSector); + + uint32_t sector_relative = start_sector; + + /*!< DBR sector */ + if (start_sector == BOOTUF2_SECTOR_DBR_END) { + memcpy(buff, ctx->DBR, sizeof(struct bootuf2_DBR)); + buff[510] = 0x55; + buff[511] = 0xaa; + } + /*!< FAT sector */ + else if (start_sector < BOOTUF2_SECTOR_FAT_END(ctx->DBR)) { + uint16_t *buff16 = (uint16_t *)buff; + + sector_relative -= BOOTUF2_SECTOR_RSVD_END(ctx->DBR); + + /*!< Perform the same operation on all FAT tables */ + while (sector_relative >= ctx->DBR->BPB.SectorsPerFAT) { + sector_relative -= ctx->DBR->BPB.SectorsPerFAT; + } + + uint16_t cluster_unused = files[ARRAY_SIZE(files) - 1].ClusterEnd + 1; + uint16_t cluster_absolute_first = sector_relative * + BOOTUF2_FAT16_PER_SECTOR(ctx->DBR); + + /*!< cluster used link to chain, or unsed */ + for (uint16_t i = 0, cluster_absolute = cluster_absolute_first; + i < BOOTUF2_FAT16_PER_SECTOR(ctx->DBR); + i++, cluster_absolute++) { + if (cluster_absolute >= cluster_unused) + buff16[i] = 0; + else + buff16[i] = cluster_absolute + 1; + } + + /*!< cluster 0 and 1 */ + if (sector_relative == 0) { + buff[0] = ctx->DBR->BPB.MediaDescriptor; + buff[1] = 0xff; + buff16[1] = 0xffff; + } + + /*!< cluster end of file */ + for (uint32_t i = 0; i < ARRAY_SIZE(files); i++) { + uint16_t cluster_file_last = files[i].ClusterEnd; + + if (cluster_file_last >= cluster_absolute_first) { + uint16_t idx = cluster_file_last - cluster_absolute_first; + if (idx < BOOTUF2_FAT16_PER_SECTOR(ctx->DBR)) { + buff16[idx] = 0xffff; + } + } + } + } + /*!< root entries */ + else if (start_sector < BOOTUF2_SECTOR_ROOT_END(ctx->DBR)) { + sector_relative -= BOOTUF2_SECTOR_FAT_END(ctx->DBR); + + struct bootuf2_ENTRY *ent = (void *)buff; + int remain_entries = BOOTUF2_ENTRY_PER_SECTOR(ctx->DBR); + + uint32_t file_index_first; + + /*!< volume label entry */ + if (sector_relative == 0) { + fname_copy(ent->Name, (char const *)ctx->DBR->BPB.VolumeLabel, 11); + ent->Attribute = 0x28; + ent++; + remain_entries--; + file_index_first = 0; + } else { + /*!< -1 to account for volume label in first sector */ + file_index_first = sector_relative * BOOTUF2_ENTRY_PER_SECTOR(ctx->DBR) - 1; + } + + for (uint32_t idx = file_index_first; + (remain_entries > 0) && (idx < ARRAY_SIZE(files)); + idx++, ent++) { + const uint32_t cluster_beg = files[idx].ClusterBeg; + + const struct bootuf2_FILE *f = &files[idx]; + + if ((0 == f->FileSize) && + (0 != idx)) { + continue; + } + + fname_copy(ent->Name, f->Name, 11); + ent->Attribute = 0x05; + ent->CreateTimeTeenth = BOOTUF2_SECONDS_INT % 2 * 100; + ent->CreateTime = BOOTUF2_DOS_TIME; + ent->CreateDate = BOOTUF2_DOS_DATE; + ent->LastAccessDate = BOOTUF2_DOS_DATE; + ent->FirstClustH16 = cluster_beg >> 16; + ent->UpdateTime = BOOTUF2_DOS_TIME; + ent->UpdateDate = BOOTUF2_DOS_DATE; + ent->FirstClustL16 = cluster_beg & 0xffff; + ent->FileSize = f->FileSize; + } + } + /*!< data */ + else if (start_sector < BOOTUF2_SECTOR_DATA_END(ctx->DBR)) { + sector_relative -= BOOTUF2_SECTOR_ROOT_END(ctx->DBR); + + int fid = ffind_by_cluster(2 + sector_relative / ctx->DBR->BPB.SectorsPerCluster); + + if (fid >= 0) { + const struct bootuf2_FILE *f = &files[fid]; + + uint32_t sector_relative_file = + sector_relative - + (files[fid].ClusterBeg - 2) * ctx->DBR->BPB.SectorsPerCluster; + + size_t fcontent_offset = sector_relative_file * ctx->DBR->BPB.BytesPerSector; + size_t fcontent_length = f->FileSize; + + if (fcontent_length > fcontent_offset) { + const void *src = (void *)((uint8_t *)(f->Content) + fcontent_offset); + size_t copy_size = fcontent_length - fcontent_offset; + + if (copy_size > ctx->DBR->BPB.BytesPerSector) { + copy_size = ctx->DBR->BPB.BytesPerSector; + } + + memcpy(buff, src, copy_size); + } + } + } + /*!< unknown sector, ignore */ + + start_sector++; + sector_count--; + buff += ctx->DBR->BPB.BytesPerSector; + } + + return 0; +} + +int bootuf2_write_sector(uint32_t start_sector, const uint8_t *buff, uint32_t sector_count) +{ + struct bootuf2_data *ctx; + + ctx = &bootuf2_disk; + + while (sector_count) { + struct bootuf2_BLOCK *uf2 = (void *)buff; + + if (!((uf2->MagicStart0 == BOOTUF2_MAGIC_START0) && + (uf2->MagicStart1 == BOOTUF2_MAGIC_START1) && + (uf2->MagicEnd == BOOTUF2_MAGIC_END) && + (uf2->Flags & BOOTUF2_FLAG_FAMILID_PRESENT) && + !(uf2->Flags & BOOTUF2_FLAG_NOT_MAIN_FLASH))) { + goto next; + } + + if (uf2->FamilyID == CONFIG_BOOTUF2_FAMILYID) { + if (bootuf2block_check_writable(ctx->STATE, uf2, CONFIG_BOOTUF2_FLASHMAX)) { + bootuf2_flash_write_internal(ctx, uf2); + bootuf2block_state_update(ctx->STATE, uf2, CONFIG_BOOTUF2_FLASHMAX); + } else { + USB_LOG_DBG("UF2 block %d already written\r\n", + uf2->BlockIndex); + } + } else { + USB_LOG_DBG("UF2 block illegal id %08x\r\n", uf2->FamilyID); + } + + next: + start_sector++; + sector_count--; + buff += ctx->DBR->BPB.BytesPerSector; + } + + return 0; +} + +uint16_t bootuf2_get_sector_size(void) +{ + return bootuf2_disk.DBR->BPB.BytesPerSector; +} + +uint32_t bootuf2_get_sector_count(void) +{ + return bootuf2_disk.DBR->BPB.SectorsOver32MB + bootuf2_disk.DBR->BPB.Sectors; +} + +bool bootuf2_is_write_done(void) +{ + if (bootuf2block_state_check(bootuf2_disk.STATE)) { + bootuf2_flash_flush(&bootuf2_disk); + USB_LOG_DBG("UF2 update ok\r\n"); + return true; + } else { + return false; + } +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/bootuf2.h b/rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/bootuf2.h new file mode 100644 index 0000000..ec31d3e --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/bootuf2.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2024, sakumisu + * Copyright (c) 2024, Egahp + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef BOOTUF2_H +#define BOOTUF2_H + +#include +#include +#include +#include +#include +#include + +#ifndef __PACKED +#define __PACKED __attribute__((packed)) +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array) \ + ((int)((sizeof(array) / sizeof((array)[0])))) +#endif + +struct bootuf2_BLOCK +{ + // 32 byte header + uint32_t MagicStart0; + uint32_t MagicStart1; + uint32_t Flags; + uint32_t TargetAddress; + uint32_t PayloadSize; + uint32_t BlockIndex; + uint32_t NumberOfBlock; + uint32_t FamilyID; // or file_size + uint8_t Data[476]; + uint32_t MagicEnd; +} __PACKED; +//BUILD_ASSERT(sizeof(struct bootuf2_BLOCK) == 512, "bootuf2_BLOCK not sector sized"); + +struct bootuf2_STATE +{ + uint32_t NumberOfBlock; + uint32_t NumberOfWritten; + uint8_t *const Mask; + uint8_t Enable; +}; + +struct bootuf2_DBR +{ + /*!< offset 0 */ + uint8_t JMPInstruction[3]; + /*!< offset 3 */ + uint8_t OEM[8]; + /*!< offset 11 */ + struct + { + uint16_t BytesPerSector; + uint8_t SectorsPerCluster; + uint16_t ReservedSectors; + uint8_t NumberOfFAT; + uint16_t RootEntries; + uint16_t Sectors; + uint8_t MediaDescriptor; + uint16_t SectorsPerFAT; + uint16_t SectorsPerTrack; + uint16_t Heads; + uint32_t HiddenSectors; + uint32_t SectorsOver32MB; + uint8_t BIOSDrive; + uint8_t Reserved; + uint8_t ExtendBootSignature; + uint32_t VolumeSerialNumber; + uint8_t VolumeLabel[11]; + uint8_t FileSystem[8]; + } __PACKED BPB; + /*!< offset 62 */ + /*!< BootLoader */ + /*!< offset 511 */ + /*!< 0x55 0xAA */ +} __PACKED; +//BUILD_ASSERT(sizeof(struct bootuf2_DBR) == 62, "bootuf2_DBR size must be 62 byte"); + +struct bootuf2_ENTRY +{ + char Name[11]; + uint8_t Attribute; + uint8_t NTReserved; + uint8_t CreateTimeTeenth; + uint16_t CreateTime; + uint16_t CreateDate; + uint16_t LastAccessDate; + uint16_t FirstClustH16; + uint16_t UpdateTime; + uint16_t UpdateDate; + uint16_t FirstClustL16; + uint32_t FileSize; +} __PACKED; +//BUILD_ASSERT(sizeof(struct bootuf2_ENTRY) == 32, "bootuf2_ENTRY size must be 32 byte"); + +struct bootuf2_FILE +{ + const char *const Name; + const void *const Content; + uint32_t FileSize; + uint16_t ClusterBeg; + uint16_t ClusterEnd; +}; + +#define BOOTUF2_DIVCEIL(_v, _d) (((_v) / (_d)) + ((_v) % (_d) ? 1 : 0)) + +#define BOOTUF2_MAGIC_START0 0x0A324655u +#define BOOTUF2_MAGIC_START1 0x9E5D5157u +#define BOOTUF2_MAGIC_SERIAL 0x251B18BDu +#define BOOTUF2_MAGIC_END 0x0AB16F30u + +#define BOOTUF2_FLAG_NOT_MAIN_FLASH 0x00000001u +#define BOOTUF2_FLAG_FILE_CONTAINER 0x00001000u +#define BOOTUF2_FLAG_FAMILID_PRESENT 0x00002000u +#define BOOTUF2_FLAG_MD5_PRESENT 0x00004000u + +#define BOOTUF2_CMD_READ 0 +#define BOOTUF2_CMD_SYNC 1 + +#define BOOTUF2_BLOCKSMAX (((CONFIG_BOOTUF2_FLASHMAX) / 256) + (((CONFIG_BOOTUF2_FLASHMAX) % 256) ? 1 : 0)) + +#define BOOTUF2_FAMILYID_POSNUM(n) (((CONFIG_BOOTUF2_FAMILYID) / (0x10000000 >> ((n) * 4))) % 0x10) +#define BOOTUF2_FAMILYID_ARRAY \ + { \ + ((BOOTUF2_FAMILYID_POSNUM(0) >= 10) ? BOOTUF2_FAMILYID_POSNUM(0) - 10 + 'A' : BOOTUF2_FAMILYID_POSNUM(0) + '0'), \ + ((BOOTUF2_FAMILYID_POSNUM(1) >= 10) ? BOOTUF2_FAMILYID_POSNUM(1) - 10 + 'A' : BOOTUF2_FAMILYID_POSNUM(1) + '0'), \ + ((BOOTUF2_FAMILYID_POSNUM(2) >= 10) ? BOOTUF2_FAMILYID_POSNUM(2) - 10 + 'A' : BOOTUF2_FAMILYID_POSNUM(2) + '0'), \ + ((BOOTUF2_FAMILYID_POSNUM(3) >= 10) ? BOOTUF2_FAMILYID_POSNUM(3) - 10 + 'A' : BOOTUF2_FAMILYID_POSNUM(3) + '0'), \ + ((BOOTUF2_FAMILYID_POSNUM(4) >= 10) ? BOOTUF2_FAMILYID_POSNUM(4) - 10 + 'A' : BOOTUF2_FAMILYID_POSNUM(4) + '0'), \ + ((BOOTUF2_FAMILYID_POSNUM(5) >= 10) ? BOOTUF2_FAMILYID_POSNUM(5) - 10 + 'A' : BOOTUF2_FAMILYID_POSNUM(5) + '0'), \ + ((BOOTUF2_FAMILYID_POSNUM(6) >= 10) ? BOOTUF2_FAMILYID_POSNUM(6) - 10 + 'A' : BOOTUF2_FAMILYID_POSNUM(6) + '0'), \ + ((BOOTUF2_FAMILYID_POSNUM(7) >= 10) ? BOOTUF2_FAMILYID_POSNUM(7) - 10 + 'A' : BOOTUF2_FAMILYID_POSNUM(7) + '0'), \ + ('I'), \ + ('D'), \ + (' '), \ + ('\0'), \ + }; + +#define BOOTUF2_FAT16_PER_SECTOR(pDBR) (pDBR->BPB.BytesPerSector / 2) +#define BOOTUF2_ENTRY_PER_SECTOR(pDBR) (pDBR->BPB.BytesPerSector / sizeof(struct bootuf2_ENTRY)) +#define BOOTUF2_CLUSTERSMAX (0xFFF0 - 2) +#define BOOTUF2_SECTOR_DBR_END (0) +#define BOOTUF2_SECTOR_RSVD_END(pDBR) BOOTUF2_SECTOR_DBR_END + (pDBR->BPB.ReservedSectors) +#define BOOTUF2_SECTOR_FAT_END(pDBR) BOOTUF2_SECTOR_RSVD_END(pDBR) + (pDBR->BPB.SectorsPerFAT * pDBR->BPB.NumberOfFAT) +#define BOOTUF2_SECTOR_ROOT_END(pDBR) BOOTUF2_SECTOR_FAT_END(pDBR) + (pDBR->BPB.RootEntries / (pDBR->BPB.BytesPerSector / sizeof(struct bootuf2_ENTRY))) +#define BOOTUF2_SECTOR_DATA_END(pDBR) (pDBR->BPB.Sectors + pDBR->BPB.SectorsOver32MB) + +#define BOOTUF2_SECTORS_PER_FAT(n) \ + BOOTUF2_DIVCEIL(BOOTUF2_CLUSTERSMAX, (CONFIG_BOOTUF2_SECTOR_SIZE / 2)) +#define BOOTUF2_SECTORS_FOR_ENTRIES(n) \ + (CONFIG_BOOTUF2_ROOT_ENTRIES / (CONFIG_BOOTUF2_SECTOR_SIZE / sizeof(struct bootuf2_ENTRY))) +#define BOOTUF2_SECTORS(n) \ + (CONFIG_BOOTUF2_SECTOR_RESERVED + \ + CONFIG_BOOTUF2_NUM_OF_FAT * BOOTUF2_SECTORS_PER_FAT(n) + \ + BOOTUF2_SECTORS_FOR_ENTRIES(n) + \ + BOOTUF2_CLUSTERSMAX * CONFIG_BOOTUF2_SECTOR_PER_CLUSTER) + +#define BOOTUF2_YEAR_INT ( \ + (__DATE__[7u] - '0') * 1000u + \ + (__DATE__[8u] - '0') * 100u + \ + (__DATE__[9u] - '0') * 10u + \ + (__DATE__[10u] - '0') * 1u) + +#define BOOTUF2_MONTH_INT ( \ + (__DATE__[2u] == 'n' && __DATE__[1u] == 'a') ? 1u /*Jan*/ \ + : (__DATE__[2u] == 'b') ? 2u /*Feb*/ \ + : (__DATE__[2u] == 'r' && __DATE__[1u] == 'a') ? 3u /*Mar*/ \ + : (__DATE__[2u] == 'r') ? 4u /*Apr*/ \ + : (__DATE__[2u] == 'y') ? 5u /*May*/ \ + : (__DATE__[2u] == 'n') ? 6u /*Jun*/ \ + : (__DATE__[2u] == 'l') ? 7u /*Jul*/ \ + : (__DATE__[2u] == 'g') ? 8u /*Aug*/ \ + : (__DATE__[2u] == 'p') ? 9u /*Sep*/ \ + : (__DATE__[2u] == 't') ? 10u /*Oct*/ \ + : (__DATE__[2u] == 'v') ? 11u /*Nov*/ \ + : 12u /*Dec*/) + +#define BOOTUF2_DAY_INT ( \ + (__DATE__[4u] == ' ' ? 0 : __DATE__[4u] - '0') * 10u + \ + (__DATE__[5u] - '0')) + +#define BOOTUF2_HOUR_INT ( \ + (__TIME__[0u] == '?' ? 0 : __TIME__[0u] - '0') * 10u + (__TIME__[1u] == '?' ? 0 : __TIME__[1u] - '0')) + +#define BOOTUF2_MINUTE_INT ( \ + (__TIME__[3u] == '?' ? 0 : __TIME__[3u] - '0') * 10u + (__TIME__[4u] == '?' ? 0 : __TIME__[4u] - '0')) + +#define BOOTUF2_SECONDS_INT ( \ + (__TIME__[6u] == '?' ? 0 : __TIME__[6u] - '0') * 10u + (__TIME__[7u] == '?' ? 0 : __TIME__[7u] - '0')) + +#define BOOTUF2_DOS_DATE ( \ + ((BOOTUF2_YEAR_INT - 1980u) << 9u) | \ + (BOOTUF2_MONTH_INT << 5u) | \ + (BOOTUF2_DAY_INT << 0u)) + +#define BOOTUF2_DOS_TIME ( \ + (BOOTUF2_HOUR_INT << 11u) | \ + (BOOTUF2_MINUTE_INT << 5u) | \ + (BOOTUF2_SECONDS_INT << 0u)) + +void bootuf2_init(void); +int boot2uf2_read_sector(uint32_t start_sector, uint8_t *buff, uint32_t sector_count); +int bootuf2_write_sector(uint32_t start_sector, const uint8_t *buff, uint32_t sector_count); +uint16_t bootuf2_get_sector_size(void); +uint32_t bootuf2_get_sector_count(void); + +bool bootuf2_is_write_done(void); + +void boot2uf2_flash_init(void); +int bootuf2_flash_write(uint32_t address, const uint8_t *data, size_t size); + +#endif /* BOOTUF2_H */ diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/bootuf2_config.h b/rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/bootuf2_config.h new file mode 100644 index 0000000..307d09d --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/bootuf2_config.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef BOOTUF2_CONFIG_H +#define BOOTUF2_CONFIG_H + +#define CONFIG_PRODUCT "CherryUSB" +#define CONFIG_BOARD "CherryUSB BOARD" +#define CONFIG_BOOTUF2_INDEX_URL "https://github.com/cherry-embedded" +#define CONFIG_BOOTUF2_JOIN_URL "http://qm.qq.com/cgi-bin/qm/qr?_wv=1027&k=GyH2M5XfWTHQzmZis4ClpgvfdObPrvtk&authKey=LmcLhfno%2BiW51wmgVC%2F8WoYwUXqiclzWDHMU1Jy1d6S8cECJ4Q7bfJ%2FTe67RLakI&noverify=0&group_code=642693751" + +#define CONFIG_BOOTUF2_CACHE_SIZE 4096 +#define CONFIG_BOOTUF2_SECTOR_SIZE 512 +#define CONFIG_BOOTUF2_SECTOR_PER_CLUSTER 2 +#define CONFIG_BOOTUF2_SECTOR_RESERVED 1 +#define CONFIG_BOOTUF2_NUM_OF_FAT 2 +#define CONFIG_BOOTUF2_ROOT_ENTRIES 64 + +#define CONFIG_BOOTUF2_FAMILYID 0xFFFFFFFF +#define CONFIG_BOOTUF2_FLASHMAX 0x800000 +#define CONFIG_BOOTUF2_PAGE_COUNTMAX 1024 + +#endif \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/cherryuf2.png b/rt-thread/components/drivers/usb/cherryusb/demo/bootuf2/cherryuf2.png new file mode 100644 index 0000000000000000000000000000000000000000..aff7ee4df875678cdcdf79d2485fc35fdaabffee GIT binary patch literal 19847 zcmdpeWmH^Emo9{a1PBlyxH~isAvlE4xVyUtcZURb*Wm8%9$bUFyEP7tH{4F%@0*#m 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zrIPJ-Ti0)$cCKoZ{QTVeFO?VzZhNhXiEgxh^xRrqNy_43*u0|Ur&?k*x(l1lo}RRJ zEjQzxz-N+!ee3v1BB((94a z+mFYb<>?R3zW96MXaCSi#nu;YPCZoiQlz~8khsXNJu&BIvgj&)E57iu+{@wI#3GSx zW(VGXJDTvYaKhq*xEYF#x`Bzj-Nhdt^fkYD$N4Hl(&nMa)CEpeksF>%ysQ4iYxCoa zw8iHwlP6Ta@~n8f{{5p56BkRYzP9(*r~01T_tidI&v;@zU1wo(*3+<-XVSs5+^reK zUTU7-nSFVdQ I&MBb@0Mz5reE CURSOR_WIDTH) { + step_x_y++; + step_x_y = step_x_y % 4; + move_cnt = 0; + } + switch (step_x_y) { + case 0: { + y = 0; + x = CURSOR_STEP; + + } break; + + case 1: { + x = 0; + y = CURSOR_STEP; + + } break; + + case 2: { + y = 0; + x = (int8_t)(-CURSOR_STEP); + + } break; + + case 3: { + x = 0; + y = (int8_t)(-CURSOR_STEP); + + } break; + } + + buf[0] = 0; + buf[1] = x; + buf[2] = y; + buf[3] = 0; +} + +/* https://cps-check.com/cn/polling-rate-check */ void hid_mouse_test(uint8_t busid) { + if(usb_device_is_configured(busid) == false) { + return; + } + int counter = 0; while (counter < 1000) { - /*!< move mouse pointer */ - mouse_cfg.x += 40; - mouse_cfg.y += 0; - - int ret = usbd_ep_start_write(busid, HID_INT_EP, (uint8_t *)&mouse_cfg, 4); - if (ret < 0) { - return; - } + draw_circle((uint8_t *)&mouse_cfg); hid_state = HID_STATE_BUSY; + usbd_ep_start_write(busid, HID_INT_EP, (uint8_t *)&mouse_cfg, 4); while (hid_state == HID_STATE_BUSY) { } diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/hid_remote_wakeup_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/hid_remote_wakeup_template.c new file mode 100644 index 0000000..786c324 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/demo/hid_remote_wakeup_template.c @@ -0,0 +1,331 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_hid.h" + +/*!< endpoint address */ +#define HID_INT_EP 0x81 +#define HID_INT_EP_SIZE 4 +#define HID_INT_EP_INTERVAL 1 + +#define USBD_VID 0xffff +#define USBD_PID 0xffff +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +/*!< config descriptor size */ +#define USB_HID_CONFIG_DESC_SIZ 34 +/*!< report descriptor size */ +#define HID_MOUSE_REPORT_DESC_SIZE 74 + +/*!< global descriptor */ +const uint8_t hid_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x01, 0x01, USB_CONFIG_REMOTE_WAKEUP | USB_CONFIG_SELF_POWERED, USBD_MAX_POWER), + + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ + HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ + 0x00, + HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ + /* 34 */ + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'H', 0x00, /* wcChar10 */ + 'I', 0x00, /* wcChar11 */ + 'D', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x00, + 0x00, +#endif + 0x00 +}; + +/*!< hid mouse report descriptor */ +static const uint8_t hid_mouse_report_desc[HID_MOUSE_REPORT_DESC_SIZE] = { + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x02, // USAGE (Mouse) + 0xA1, 0x01, // COLLECTION (Application) + 0x09, 0x01, // USAGE (Pointer) + + 0xA1, 0x00, // COLLECTION (Physical) + 0x05, 0x09, // USAGE_PAGE (Button) + 0x19, 0x01, // USAGE_MINIMUM (Button 1) + 0x29, 0x03, // USAGE_MAXIMUM (Button 3) + + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x95, 0x03, // REPORT_COUNT (3) + 0x75, 0x01, // REPORT_SIZE (1) + + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x05, // REPORT_SIZE (5) + 0x81, 0x01, // INPUT (Cnst,Var,Abs) + + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x30, // USAGE (X) + 0x09, 0x31, // USAGE (Y) + 0x09, 0x38, + + 0x15, 0x81, // LOGICAL_MINIMUM (-127) + 0x25, 0x7F, // LOGICAL_MAXIMUM (127) + 0x75, 0x08, // REPORT_SIZE (8) + 0x95, 0x03, // REPORT_COUNT (2) + + 0x81, 0x06, // INPUT (Data,Var,Rel) + 0xC0, 0x09, + 0x3c, 0x05, + 0xff, 0x09, + + 0x01, 0x15, + 0x00, 0x25, + 0x01, 0x75, + 0x01, 0x95, + + 0x02, 0xb1, + 0x22, 0x75, + 0x06, 0x95, + 0x01, 0xb1, + + 0x01, 0xc0 // END_COLLECTION +}; + +/*!< mouse report struct */ +struct hid_mouse { + uint8_t buttons; + int8_t x; + int8_t y; + int8_t wheel; +}; + +/*!< mouse report */ +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX struct hid_mouse mouse_cfg; + +#define HID_STATE_IDLE 0 +#define HID_STATE_BUSY 1 + +/*!< hid state ! Data can be sent only when state is idle */ +static volatile uint8_t hid_state = HID_STATE_IDLE; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + hid_state = HID_STATE_IDLE; + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +/* function ------------------------------------------------------------------*/ +static void usbd_hid_int_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + hid_state = HID_STATE_IDLE; +} + +/*!< endpoint call back */ +static struct usbd_endpoint hid_in_ep = { + .ep_cb = usbd_hid_int_callback, + .ep_addr = HID_INT_EP +}; + +static struct usbd_interface intf0; + +void hid_mouse_init(uint8_t busid, uintptr_t reg_base) +{ + usbd_desc_register(busid, hid_descriptor); + usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf0, hid_mouse_report_desc, HID_MOUSE_REPORT_DESC_SIZE)); + usbd_add_endpoint(busid, &hid_in_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); + + /*!< init mouse report data */ + mouse_cfg.buttons = 0; + mouse_cfg.wheel = 0; + mouse_cfg.x = 0; + mouse_cfg.y = 0; +} + +#define CURSOR_STEP 2U +#define CURSOR_WIDTH 20U + +void draw_circle(uint8_t *buf) +{ + static int32_t move_cnt = 0; + static uint8_t step_x_y = 0; + static int8_t x = 0, y = 0; + + move_cnt++; + if (move_cnt > CURSOR_WIDTH) { + step_x_y++; + step_x_y = step_x_y % 4; + move_cnt = 0; + } + switch (step_x_y) { + case 0: { + y = 0; + x = CURSOR_STEP; + + } break; + + case 1: { + x = 0; + y = CURSOR_STEP; + + } break; + + case 2: { + y = 0; + x = (int8_t)(-CURSOR_STEP); + + } break; + + case 3: { + x = 0; + y = (int8_t)(-CURSOR_STEP); + + } break; + } + + buf[0] = 0; + buf[1] = x; + buf[2] = y; + buf[3] = 0; +} + +/* https://cps-check.com/cn/polling-rate-check */ +void hid_mouse_test(uint8_t busid) +{ + static uint32_t count = 1000; + int ret; + + if(usb_device_is_configured(busid) == false) { + return; + } + + // if (gpio_read_pin(GPIO_PIN) == 1) { + // ret = usbd_send_remote_wakeup(busid); + // if (ret < 0) { + // return; + // } + // count = 5000; + // } + + while (count) { + draw_circle((uint8_t *)&mouse_cfg); + hid_state = HID_STATE_BUSY; + usbd_ep_start_write(busid, HID_INT_EP, (uint8_t *)&mouse_cfg, 4); + while (hid_state == HID_STATE_BUSY) { + } + + count--; + } +} diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/midi_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/midi_template.c index d09a943..aa3b2ad 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/midi_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/midi_template.c @@ -145,7 +145,7 @@ const uint8_t midi_descriptor[] = { 0x02, 0x01, 0x40, - 0x01, + 0x00, 0x00, #endif 0x00 @@ -202,7 +202,7 @@ struct usbd_endpoint midi_in_ep = { .ep_cb = usbd_midi_bulk_in }; -void midi_init(uint8_t busid, uint32_t reg_base) +void midi_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, midi_descriptor); usbd_add_interface(busid, &intf0); diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/msc_ram_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/msc_ram_template.c index 933cd88..9021483 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/msc_ram_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/msc_ram_template.c @@ -94,7 +94,7 @@ const uint8_t msc_ram_descriptor[] = { 0x00, 0x00, 0x40, - 0x01, + 0x00, 0x00, #endif 0x00 @@ -154,12 +154,19 @@ int usbd_msc_sector_write(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t * return 0; } -struct usbd_interface intf0; +static struct usbd_interface intf0; -void msc_ram_init(uint8_t busid, uint32_t reg_base) +void msc_ram_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, msc_ram_descriptor); usbd_add_interface(busid, usbd_msc_init_intf(busid, &intf0, MSC_OUT_EP, MSC_IN_EP)); usbd_initialize(busid, reg_base, usbd_event_handler); } + +#if defined(CONFIG_USBDEV_MSC_POLLING) +void msc_ram_polling(uint8_t busid) +{ + usbd_msc_polling(busid); +} +#endif \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/msc_storage_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/msc_storage_template.c index a335164..047bad8 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/msc_storage_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/msc_storage_template.c @@ -97,7 +97,7 @@ const uint8_t msc_storage_descriptor[] = { 0x00, 0x00, 0x40, - 0x01, + 0x00, 0x00, #endif 0x00 @@ -154,7 +154,7 @@ int usbd_msc_sector_write(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t * return 0; } -void msc_storage_init(uint8_t busid, uint32_t reg_base) +void msc_storage_init(uint8_t busid, uintptr_t reg_base) { rt_err_t res; diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/usb_host.c b/rt-thread/components/drivers/usb/cherryusb/demo/usb_host.c index 8c8ac22..817103d 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/usb_host.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/usb_host.c @@ -120,7 +120,7 @@ void usbh_hid_callback(void *arg, int nbytes) struct usbh_hid *hid_class = (struct usbh_hid *)arg; if (nbytes > 0) { - for (size_t i = 0; i < nbytes; i++) { + for (int i = 0; i < nbytes; i++) { USB_LOG_RAW("0x%02x ", hid_buffer[i]); } USB_LOG_RAW("nbytes:%d\r\n", nbytes); @@ -254,38 +254,38 @@ delete: } #endif +#if TEST_USBH_CDC_ACM void usbh_cdc_acm_run(struct usbh_cdc_acm *cdc_acm_class) { -#if TEST_USBH_CDC_ACM usb_osal_thread_create("usbh_cdc", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_cdc_acm_thread, cdc_acm_class); -#endif } void usbh_cdc_acm_stop(struct usbh_cdc_acm *cdc_acm_class) { } +#endif +#if TEST_USBH_HID void usbh_hid_run(struct usbh_hid *hid_class) { -#if TEST_USBH_HID usb_osal_thread_create("usbh_hid", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_hid_thread, hid_class); -#endif } void usbh_hid_stop(struct usbh_hid *hid_class) { } +#endif +#if TEST_USBH_MSC void usbh_msc_run(struct usbh_msc *msc_class) { -#if TEST_USBH_MSC usb_osal_thread_create("usbh_msc", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_msc_thread, msc_class); -#endif } void usbh_msc_stop(struct usbh_msc *msc_class) { } +#endif #if TEST_USBH_AUDIO #error "commercial charge" @@ -294,3 +294,26 @@ void usbh_msc_stop(struct usbh_msc *msc_class) #if TEST_USBH_VIDEO #error "commercial charge" #endif + +#if 0 +#include "usbh_aoa.h" + +static struct aoa_string_info deviceinfo = { + .acc_manufacturer = "CherryUSB", + .acc_model = "CherryUSB", + .acc_description = "Android Open Accessory CherryUSB", + .acc_version = "1.0", + .acc_uri = "http://developer.android.com/tools/adk/index.html", + .acc_serial = "CherryUSB" +}; + +int aoa_switch(int argc, char **argv) +{ + struct usbh_hubport *hport = usbh_find_hubport(0, 1, 1); + + usbh_aoa_switch(hport, &deviceinfo); + return 0; +} + +SHELL_CMD_EXPORT_ALIAS(aoa_switch, aoa_switch, aoa_switch); +#endif \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/video_audiov1_hid_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/video_audiov1_hid_template.c index 97f1743..6a41162 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/video_audiov1_hid_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/video_audiov1_hid_template.c @@ -9,6 +9,8 @@ #include "usbd_hid.h" #include "cherryusb_mjpeg.h" +#define MAX_PACKETS_IN_ONE_TRANSFER 1 + #define VIDEO_IN_EP 0x81 #define VIDEO_INT_EP 0x86 @@ -224,7 +226,7 @@ const uint8_t video_audio_hid_descriptor[] = { 0x00, 0x00, 0x40, - 0x01, + 0x00, 0x00, #endif 0x00 @@ -267,7 +269,7 @@ static const uint8_t hid_keyboard_report_desc[HID_KEYBOARD_REPORT_DESC_SIZE] = { USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t audio_read_buffer[AUDIO_OUT_PACKET]; USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t audio_write_buffer[AUDIO_IN_PACKET]; -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t video_packet_buffer[40 * 1024]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t video_packet_buffer[2][MAX_PACKETS_IN_ONE_TRANSFER * MAX_PAYLOAD_SIZE]; volatile bool video_tx_flag = 0; volatile bool audio_tx_flag = 0; @@ -331,8 +333,10 @@ void usbd_video_close(uint8_t busid, uint8_t intf) void usbd_video_iso_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) { - //USB_LOG_RAW("actual in len:%d\r\n", nbytes); - video_iso_tx_busy = false; + if (usbd_video_stream_split_transfer(busid, ep)) { + /* one frame has done */ + video_iso_tx_busy = false; + } } static struct usbd_endpoint video_in_ep = { @@ -416,7 +420,7 @@ struct audio_entity_info audio_entity_table[] = { .ep = AUDIO_OUT_EP }, }; -void composite_init(uint8_t busid, uint32_t reg_base) +void composite_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, video_audio_hid_descriptor); usbd_add_interface(busid, usbd_video_init_intf(busid, &intf0, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); @@ -458,56 +462,30 @@ void hid_keyboard_test(uint8_t busid) { const uint8_t sendbuffer[8] = { 0x00, 0x00, HID_KBD_USAGE_A, 0x00, 0x00, 0x00, 0x00, 0x00 }; - memcpy(hid_write_buffer, sendbuffer, 8); - int ret = usbd_ep_start_write(busid, HID_INT_EP, hid_write_buffer, 8); - if (ret < 0) { + if(usb_device_is_configured(busid) == false) { return; } + + memcpy(hid_write_buffer, sendbuffer, 8); hid_state = HID_STATE_BUSY; + usbd_ep_start_write(busid, HID_INT_EP, hid_write_buffer, 8); while (hid_state == HID_STATE_BUSY) { } } void video_test(uint8_t busid) { - uint32_t out_len; - uint32_t packets; + memset(video_packet_buffer, 0, sizeof(video_packet_buffer)); - (void)packets; - memset(video_packet_buffer, 0, 40 * 1024); while (1) { if (video_tx_flag) { - packets = usbd_video_payload_fill(busid, (uint8_t *)cherryusb_mjpeg, sizeof(cherryusb_mjpeg), video_packet_buffer, &out_len); -#if 1 video_iso_tx_busy = true; - usbd_ep_start_write(busid, VIDEO_IN_EP, video_packet_buffer, out_len); + usbd_video_stream_start_write(busid, VIDEO_IN_EP, &video_packet_buffer[0][0], &video_packet_buffer[1][0], MAX_PACKETS_IN_ONE_TRANSFER * MAX_PAYLOAD_SIZE, (uint8_t *)cherryusb_mjpeg, sizeof(cherryusb_mjpeg)); while (video_iso_tx_busy) { if (video_tx_flag == 0) { break; } } -#else - /* dwc2 must use this method */ - for (uint32_t i = 0; i < packets; i++) { - if (i == (packets - 1)) { - video_iso_tx_busy = true; - usbd_ep_start_write(busid, VIDEO_IN_EP, &video_packet_buffer[i * MAX_PAYLOAD_SIZE], out_len - (packets - 1) * MAX_PAYLOAD_SIZE); - while (video_iso_tx_busy) { - if (video_tx_flag == 0) { - break; - } - } - } else { - video_iso_tx_busy = true; - usbd_ep_start_write(busid, VIDEO_IN_EP, &video_packet_buffer[i * MAX_PAYLOAD_SIZE], MAX_PAYLOAD_SIZE); - while (video_iso_tx_busy) { - if (video_tx_flag == 0) { - break; - } - } - } - } -#endif } } } \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/video_static_h264_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/video_static_h264_template.c index adfb879..e325964 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/video_static_h264_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/video_static_h264_template.c @@ -7,6 +7,8 @@ #include "usbd_video.h" #include "cherryusb_h264.h" +#define MAX_PACKETS_IN_ONE_TRANSFER 1 + #define VIDEO_IN_EP 0x81 #define VIDEO_INT_EP 0x83 @@ -129,7 +131,7 @@ const uint8_t video_descriptor[] = { 0x00, 0x00, 0x40, - 0x01, + 0x00, 0x00, #endif 0x00 @@ -180,8 +182,10 @@ void usbd_video_close(uint8_t busid, uint8_t intf) void usbd_video_iso_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) { - //USB_LOG_RAW("actual in len:%d\r\n", nbytes); - iso_tx_busy = false; + if (usbd_video_stream_split_transfer(busid, ep)) { + /* one frame has done */ + iso_tx_busy = false; + } } static struct usbd_endpoint video_in_ep = { @@ -192,7 +196,7 @@ static struct usbd_endpoint video_in_ep = { struct usbd_interface intf0; struct usbd_interface intf1; -void video_init(uint8_t busid, uint32_t reg_base) +void video_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, video_descriptor); usbd_add_interface(busid, usbd_video_init_intf(busid, &intf0, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); @@ -202,7 +206,7 @@ void video_init(uint8_t busid, uint32_t reg_base) usbd_initialize(busid, reg_base, usbd_event_handler); } -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t packet_buffer[40 * 1024]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t packet_buffer[2][40 * 1024]; void video_test(uint8_t busid) { @@ -210,40 +214,16 @@ void video_test(uint8_t busid) uint32_t packets; (void)packets; - memset(packet_buffer, 0, 40 * 1024); + memset(packet_buffer, 0, sizeof(packet_buffer)); while (1) { if (tx_flag) { - packets = usbd_video_payload_fill(busid, (uint8_t *)cherryusb_h264, sizeof(cherryusb_h264), packet_buffer, &out_len); -#if 1 iso_tx_busy = true; - usbd_ep_start_write(busid, VIDEO_IN_EP, packet_buffer, out_len); + usbd_video_stream_start_write(busid, VIDEO_IN_EP, &packet_buffer[0][0], &packet_buffer[1][0], MAX_PACKETS_IN_ONE_TRANSFER * MAX_PAYLOAD_SIZE, (uint8_t *)cherryusb_h264, sizeof(cherryusb_h264)); while (iso_tx_busy) { if (tx_flag == 0) { break; } } -#else - /* dwc2 must use this method */ - for (uint32_t i = 0; i < packets; i++) { - if (i == (packets - 1)) { - iso_tx_busy = true; - usbd_ep_start_write(busid, VIDEO_IN_EP, &packet_buffer[i * MAX_PAYLOAD_SIZE], out_len - (packets - 1) * MAX_PAYLOAD_SIZE); - while (iso_tx_busy) { - if (tx_flag == 0) { - break; - } - } - } else { - iso_tx_busy = true; - usbd_ep_start_write(busid, VIDEO_IN_EP, &packet_buffer[i * MAX_PAYLOAD_SIZE], MAX_PAYLOAD_SIZE); - while (iso_tx_busy) { - if (tx_flag == 0) { - break; - } - } - } - } -#endif } } } \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/video_static_mjpeg_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/video_static_mjpeg_template.c index 85b659d..1d2ae01 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/video_static_mjpeg_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/video_static_mjpeg_template.c @@ -7,6 +7,8 @@ #include "usbd_video.h" #include "cherryusb_mjpeg.h" +#define MAX_PACKETS_IN_ONE_TRANSFER 1 + #define VIDEO_IN_EP 0x81 #define VIDEO_INT_EP 0x83 @@ -34,7 +36,7 @@ #define MAX_BIT_RATE (unsigned long)(WIDTH * HEIGHT * 16 * CAM_FPS) #define MAX_FRAME_SIZE (unsigned long)(WIDTH * HEIGHT * 2) -#define VS_HEADER_SIZ (unsigned int)(VIDEO_SIZEOF_VS_INPUT_HEADER_DESC(1,1) + VIDEO_SIZEOF_VS_FORMAT_MJPEG_DESC + VIDEO_SIZEOF_VS_FRAME_MJPEG_DESC(1)) +#define VS_HEADER_SIZ (unsigned int)(VIDEO_SIZEOF_VS_INPUT_HEADER_DESC(1, 1) + VIDEO_SIZEOF_VS_FORMAT_MJPEG_DESC + VIDEO_SIZEOF_VS_FRAME_MJPEG_DESC(1)) #define USB_VIDEO_DESC_SIZ (unsigned long)(9 + \ VIDEO_VC_NOEP_DESCRIPTOR_LEN + \ @@ -129,7 +131,7 @@ const uint8_t video_descriptor[] = { 0x00, 0x00, 0x40, - 0x01, + 0x00, 0x00, #endif 0x00 @@ -180,8 +182,10 @@ void usbd_video_close(uint8_t busid, uint8_t intf) void usbd_video_iso_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) { - //USB_LOG_RAW("actual in len:%d\r\n", nbytes); - iso_tx_busy = false; + if (usbd_video_stream_split_transfer(busid, ep)) { + /* one frame has done */ + iso_tx_busy = false; + } } static struct usbd_endpoint video_in_ep = { @@ -192,7 +196,7 @@ static struct usbd_endpoint video_in_ep = { struct usbd_interface intf0; struct usbd_interface intf1; -void video_init(uint8_t busid, uint32_t reg_base) +void video_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, video_descriptor); usbd_add_interface(busid, usbd_video_init_intf(busid, &intf0, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); @@ -202,48 +206,21 @@ void video_init(uint8_t busid, uint32_t reg_base) usbd_initialize(busid, reg_base, usbd_event_handler); } -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t packet_buffer[40 * 1024]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t packet_buffer[2][MAX_PACKETS_IN_ONE_TRANSFER * MAX_PAYLOAD_SIZE]; void video_test(uint8_t busid) { - uint32_t out_len; - uint32_t packets; + memset(packet_buffer, 0, sizeof(packet_buffer)); - (void)packets; - memset(packet_buffer, 0, 40 * 1024); while (1) { if (tx_flag) { - packets = usbd_video_payload_fill(busid, (uint8_t *)cherryusb_mjpeg, sizeof(cherryusb_mjpeg), packet_buffer, &out_len); -#if 1 iso_tx_busy = true; - usbd_ep_start_write(busid, VIDEO_IN_EP, packet_buffer, out_len); + usbd_video_stream_start_write(busid, VIDEO_IN_EP, &packet_buffer[0][0], &packet_buffer[1][0], MAX_PACKETS_IN_ONE_TRANSFER * MAX_PAYLOAD_SIZE, (uint8_t *)cherryusb_mjpeg, sizeof(cherryusb_mjpeg)); while (iso_tx_busy) { if (tx_flag == 0) { break; } } -#else - /* dwc2 must use this method */ - for (uint32_t i = 0; i < packets; i++) { - if (i == (packets - 1)) { - iso_tx_busy = true; - usbd_ep_start_write(busid, VIDEO_IN_EP, &packet_buffer[i * MAX_PAYLOAD_SIZE], out_len - (packets - 1) * MAX_PAYLOAD_SIZE); - while (iso_tx_busy) { - if (tx_flag == 0) { - break; - } - } - } else { - iso_tx_busy = true; - usbd_ep_start_write(busid, VIDEO_IN_EP, &packet_buffer[i * MAX_PAYLOAD_SIZE], MAX_PAYLOAD_SIZE); - while (iso_tx_busy) { - if (tx_flag == 0) { - break; - } - } - } - } -#endif } } } \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/video_static_yuyv_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/video_static_yuyv_template.c index febbaf9..4ba7170 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/video_static_yuyv_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/video_static_yuyv_template.c @@ -7,6 +7,8 @@ #include "usbd_video.h" #include "cherryusb_yuyv.h" +#define MAX_PACKETS_IN_ONE_TRANSFER 1 + #define VIDEO_IN_EP 0x81 #define VIDEO_INT_EP 0x83 @@ -131,7 +133,7 @@ const uint8_t video_descriptor[] = { 0x00, 0x00, 0x40, - 0x01, + 0x00, 0x00, #endif 0x00 @@ -182,8 +184,10 @@ void usbd_video_close(uint8_t busid, uint8_t intf) void usbd_video_iso_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) { - //USB_LOG_RAW("actual in len:%d\r\n", nbytes); - iso_tx_busy = false; + if (usbd_video_stream_split_transfer(busid, ep)) { + /* one frame has done */ + iso_tx_busy = false; + } } static struct usbd_endpoint video_in_ep = { @@ -194,7 +198,7 @@ static struct usbd_endpoint video_in_ep = { struct usbd_interface intf0; struct usbd_interface intf1; -void video_init(uint8_t busid, uint32_t reg_base) +void video_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, video_descriptor); usbd_add_interface(busid, usbd_video_init_intf(busid, &intf0, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); @@ -204,48 +208,21 @@ void video_init(uint8_t busid, uint32_t reg_base) usbd_initialize(busid, reg_base, usbd_event_handler); } -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t packet_buffer[40 * 1024]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t packet_buffer[2][MAX_PACKETS_IN_ONE_TRANSFER * MAX_PAYLOAD_SIZE]; void video_test(uint8_t busid) { - uint32_t out_len; - uint32_t packets; + memset(packet_buffer, 0, sizeof(packet_buffer)); - (void)packets; - memset(packet_buffer, 0, 40 * 1024); while (1) { if (tx_flag) { - packets = usbd_video_payload_fill(busid, (uint8_t *)cherryusb_yuyv, sizeof(cherryusb_yuyv), packet_buffer, &out_len); -#if 1 iso_tx_busy = true; - usbd_ep_start_write(busid, VIDEO_IN_EP, packet_buffer, out_len); + usbd_video_stream_start_write(busid, VIDEO_IN_EP, &packet_buffer[0][0], &packet_buffer[1][0], MAX_PACKETS_IN_ONE_TRANSFER * MAX_PAYLOAD_SIZE, (uint8_t *)cherryusb_yuyv, sizeof(cherryusb_yuyv)); while (iso_tx_busy) { if (tx_flag == 0) { break; } } -#else - /* dwc2 must use this method */ - for (uint32_t i = 0; i < packets; i++) { - if (i == (packets - 1)) { - iso_tx_busy = true; - usbd_ep_start_write(busid, VIDEO_IN_EP, &packet_buffer[i * MAX_PAYLOAD_SIZE], out_len - (packets - 1) * MAX_PAYLOAD_SIZE); - while (iso_tx_busy) { - if (tx_flag == 0) { - break; - } - } - } else { - iso_tx_busy = true; - usbd_ep_start_write(busid, VIDEO_IN_EP, &packet_buffer[i * MAX_PAYLOAD_SIZE], MAX_PAYLOAD_SIZE); - while (iso_tx_busy) { - if (tx_flag == 0) { - break; - } - } - } - } -#endif } } } \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/webusb_hid_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/webusb_hid_template.c new file mode 100644 index 0000000..5257087 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/demo/webusb_hid_template.c @@ -0,0 +1,383 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_hid.h" + +#define USBD_VID 0xffff +#define USBD_PID 0xffff +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#define HID_INT_EP 0x81 +#define HID_INT_EP_SIZE 8 +#define HID_INT_EP_INTERVAL 10 + +#define USB_HID_CONFIG_DESC_SIZ (34 + 9) +#define HID_KEYBOARD_REPORT_DESC_SIZE 63 + +#define USBD_WEBUSB_VENDOR_CODE (0x22) +#define USBD_WINUSB_VENDOR_CODE (0x21) + +#define USBD_WINUSB_DESC_SET_LEN (0xB2) +#define URL_DESCRIPTOR_LENGTH (3 + 36) + +#define USBD_WEBUSB_INTF_NUM 0x01 + +#define WEBUSB_URL_STRINGS \ + 'g', 'i', 't', 'h', 'u', 'b', '.', 'c', 'o', 'm', '/', \ + 'c', 'h', 'e', 'r', 'r', 'y', '-', 'e', 'm', 'b', 'e', 'd', 'd', 'e', 'd', '/', 'C', 'h', 'e', 'r', 'r', 'y', 'U', 'S', 'B', + +const uint8_t USBD_WinUSBDescriptorSetDescriptor[USBD_WINUSB_DESC_SET_LEN] = { + // Microsoft OS 2.0 描述符集标头 + 0x0A, 0x00, // Descriptor size (10 bytes) + 0x00, 0x00, // MS OS 2.0 descriptor set header + 0x00, 0x00, 0x03, 0x06, // Windows version (8.1) (0x06030000) + USBD_WINUSB_DESC_SET_LEN, 0x00, // Size, MS OS 2.0 descriptor set + + // Microsoft OS 2.0 配置子集标头 + 0x08, 0x00, // wLength + 0x01, 0x00, // wDescriptorType + 0x00, // 适用于配置 1 + 0x00, // bReserved + 0XA8, 0X00, // Size, MS OS 2.0 configuration subset + + // Microsoft OS 2.0 功能子集头 + 0x08, 0x00, // Descriptor size (8 bytes) + 0x02, 0x00, // MS OS 2.0 function subset header + USBD_WEBUSB_INTF_NUM, // bFirstInterface + 0x00, // 必须设置为 0 + 0xA0, 0x00, + + // Microsoft OS 2.0 兼容 ID 描述符 + // 兼容 ID 描述符告诉 Windows 此设备与 WinUSB 驱动程序兼容 + 0x14, 0x00, // wLength 20 + 0x03, 0x00, // MS_OS_20_FEATURE_COMPATIBLE_ID + 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + // Microsoft OS 2.0 注册表属性描述符 + // 注册表属性分配设备接口 GUID + 0x84, 0x00, //wLength: 132 + 0x04, 0x00, // wDescriptorType: MS_OS_20_FEATURE_REG_PROPERTY: 0x04 (Table 9) + 0x07, 0x00, //wPropertyDataType: REG_MULTI_SZ (Table 15) + 0x2a, 0x00, //wPropertyNameLength: + //bPropertyName: “DeviceInterfaceGUID” + 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, + 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, 'U', 0x00, 'I', 0x00, 'D', 0x00, 's', 0x00, + 0x00, 0x00, + 0x50, 0x00, // wPropertyDataLength + //bPropertyData: “{975F44D9-0D08-43FD-8B3E-127CA8AFFF9D}”. + '{', 0x00, '9', 0x00, 'd', 0x00, '7', 0x00, 'd', 0x00, 'e', 0x00, 'b', 0x00, 'b', 0x00, 'c', 0x00, '-', 0x00, + 'c', 0x00, '8', 0x00, '5', 0x00, 'd', 0x00, '-', 0x00, '1', 0x00, '1', 0x00, 'd', 0x00, '1', 0x00, '-', 0x00, + '9', 0x00, 'e', 0x00, 'b', 0x00, '4', 0x00, '-', 0x00, '0', 0x00, '0', 0x00, '6', 0x00, '0', 0x00, '0', 0x00, + '8', 0x00, 'c', 0x00, '3', 0x00, 'a', 0x00, '1', 0x00, '9', 0x00, 'a', 0x00, '}', 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +const uint8_t USBD_WebUSBURLDescriptor[URL_DESCRIPTOR_LENGTH] = { + URL_DESCRIPTOR_LENGTH, + WEBUSB_URL_TYPE, + WEBUSB_URL_SCHEME_HTTPS, + WEBUSB_URL_STRINGS +}; + +#define USBD_BOS_WTOTALLENGTH 0x39 + +#define LANDING_PAGE 0x01 +uint8_t USBD_BinaryObjectStoreDescriptor[USBD_BOS_WTOTALLENGTH] = { + // BOS描述符 + 0x05, // bLength 固长为5 + 0x0F, // bDescriptorType 固定为15 + USBD_BOS_WTOTALLENGTH, 0x00, // wTotalLength BOS描述符的总大小 + 0x02, // bNumDeviceCaps BOS描述符中独立设备功能特性描述符的数量 + + // WebUSB 平台功能描述符 + 0x18, // Descriptor size (24 bytes) + 0x10, // Descriptor type (Device Capability) 设备功能描述符 + 0x05, // Capability type (Platform) 平台描述符 + 0x00, // Reserved + + // WebUSB Platform Capability ID (3408b638-09a9-47a0-8bfd-a0768815b665) + // 平台功能 UUID 将此标识为WebUSB 平台功能描述符，它提供有关设备的基本信息 + 0x38, 0xB6, 0x08, 0x34, + 0xA9, 0x09, + 0xA0, 0x47, + 0x8B, 0xFD, + 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65, + + 0x00, 0x01, // WebUSB version 1.0 + USBD_WEBUSB_VENDOR_CODE, // Vendor-assigned WebUSB request code + LANDING_PAGE, // Landing page + + // Microsoft 平台功能描述符 + // 标头 + 0x1C, // Descriptor size (28 bytes) + 0x10, // Descriptor type (Device Capability) + 0x05, // Capability type (Platform) + 0x00, // Reserved + + 0xDF, 0x60, 0xDD, 0xD8, /* PlatformCapabilityUUID */ + 0x89, 0x45, 0xC7, 0x4C, + 0x9C, 0xD2, 0x65, 0x9D, + 0x9E, 0x64, 0x8A, 0x9F, + + // 描述符集信息结构 + 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 * dwWindowsVersion 最低兼容 Windows 版本 */ + + USBD_WINUSB_DESC_SET_LEN, 0X00, /* wDescriptorSetTotalLength */ + + USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ + 0X00 /* bAltEnumCode */ +}; + +struct usb_webusb_descriptor webusb_url_desc = { + .vendor_code = USBD_WEBUSB_VENDOR_CODE, + .string = USBD_WebUSBURLDescriptor, + .string_len = USBD_WINUSB_DESC_SET_LEN +}; + +struct usb_msosv2_descriptor msosv2_desc = { + .vendor_code = USBD_WINUSB_VENDOR_CODE, + .compat_id = USBD_WinUSBDescriptorSetDescriptor, + .compat_id_len = USBD_WINUSB_DESC_SET_LEN, +}; + +struct usb_bos_descriptor bos_desc = { + .string = USBD_BinaryObjectStoreDescriptor, + .string_len = USBD_BOS_WTOTALLENGTH +}; + +static const uint8_t webusb_hid_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_1, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ + HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ + 0x00, + HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ + /* 34 */ + USB_INTERFACE_DESCRIPTOR_INIT(USBD_WEBUSB_INTF_NUM, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'H', 0x00, /* wcChar10 */ + 'I', 0x00, /* wcChar11 */ + 'D', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x00, + 0x00, +#endif + 0x00 +}; + +/* USB HID device Configuration Descriptor */ +static uint8_t hid_desc[9] __ALIGN_END = { + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, +}; + +static const uint8_t hid_keyboard_report_desc[HID_KEYBOARD_REPORT_DESC_SIZE] = { + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x06, // USAGE (Keyboard) + 0xa1, 0x01, // COLLECTION (Application) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + 0x19, 0xe0, // USAGE_MINIMUM (Keyboard LeftControl) + 0x29, 0xe7, // USAGE_MAXIMUM (Keyboard Right GUI) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x75, 0x01, // REPORT_SIZE (1) + 0x95, 0x08, // REPORT_COUNT (8) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x08, // REPORT_SIZE (8) + 0x81, 0x03, // INPUT (Cnst,Var,Abs) + 0x95, 0x05, // REPORT_COUNT (5) + 0x75, 0x01, // REPORT_SIZE (1) + 0x05, 0x08, // USAGE_PAGE (LEDs) + 0x19, 0x01, // USAGE_MINIMUM (Num Lock) + 0x29, 0x05, // USAGE_MAXIMUM (Kana) + 0x91, 0x02, // OUTPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x03, // REPORT_SIZE (3) + 0x91, 0x03, // OUTPUT (Cnst,Var,Abs) + 0x95, 0x06, // REPORT_COUNT (6) + 0x75, 0x08, // REPORT_SIZE (8) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0xFF, // LOGICAL_MAXIMUM (255) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + 0x19, 0x00, // USAGE_MINIMUM (Reserved (no event indicated)) + 0x29, 0x65, // USAGE_MAXIMUM (Keyboard Application) + 0x81, 0x00, // INPUT (Data,Ary,Abs) + 0xc0 // END_COLLECTION +}; + +#define HID_STATE_IDLE 0 +#define HID_STATE_BUSY 1 + +/*!< hid state ! Data can be sent only when state is idle */ +static volatile uint8_t hid_state = HID_STATE_IDLE; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + hid_state = HID_STATE_IDLE; + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_hid_int_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + hid_state = HID_STATE_IDLE; +} + +static struct usbd_endpoint hid_in_ep = { + .ep_cb = usbd_hid_int_callback, + .ep_addr = HID_INT_EP +}; + +static struct usbd_interface intf0; + +void webusb_hid_keyboard_init(uint8_t busid, uintptr_t reg_base) +{ + usbd_desc_register(busid, webusb_hid_descriptor); + usbd_bos_desc_register(busid, &bos_desc); + usbd_msosv2_desc_register(busid, &msosv2_desc); + usbd_webusb_desc_register(busid, &webusb_url_desc); + usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf0, hid_keyboard_report_desc, HID_KEYBOARD_REPORT_DESC_SIZE)); + usbd_add_endpoint(busid, &hid_in_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[64]; + +void hid_keyboard_test(uint8_t busid) +{ + const uint8_t sendbuffer[8] = { 0x00, 0x00, HID_KBD_USAGE_A, 0x00, 0x00, 0x00, 0x00, 0x00 }; + + if(usb_device_is_configured(busid) == false) { + return; + } + + memcpy(write_buffer, sendbuffer, 8); + hid_state = HID_STATE_BUSY; + usbd_ep_start_write(busid, HID_INT_EP, write_buffer, 8); + while (hid_state == HID_STATE_BUSY) { + } +} diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/webusb_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/webusb_template.c deleted file mode 100644 index dc8bc57..0000000 --- a/rt-thread/components/drivers/usb/cherryusb/demo/webusb_template.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2024, sakumisu - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "usbd_core.h" - -#define MS_OS_20_DESCRIPTOR_LENGTH (0xB2) - -#define WEBUSB_URL_STRINGS \ - 'd', 'e', 'v', 'a', 'n', 'l', 'a', 'i', '.', 'g', 'i', 't', 'h', 'u', 'b', '.', 'i', 'o', '/', 'w', 'e', 'b', 'd', 'f', 'u', '/', 'd', 'f', 'u', '-', 'u', 't', 'i', 'l' - -#define WL_REQUEST_WEBUSB (0x22) -#define WL_REQUEST_WINUSB (0x21) - -#define URL_DESCRIPTOR_LENGTH 0x2C - -// 描述符集信息 -const uint8_t MS_OS_20_DESCRIPTOR_SET[MS_OS_20_DESCRIPTOR_LENGTH] = { - // Microsoft OS 2.0 描述符集标头 - 0x0A, 0x00, // Descriptor size (10 bytes) - 0x00, 0x00, // MS OS 2.0 descriptor set header - 0x00, 0x00, 0x03, 0x06, // Windows version (8.1) (0x06030000) - MS_OS_20_DESCRIPTOR_LENGTH, 0x00, // Size, MS OS 2.0 descriptor set - - // Microsoft OS 2.0 配置子集标头 - 0x08, 0x00, // wLength - 0x01, 0x00, // wDescriptorType - 0x00, // 适用于配置 1 - 0x00, // bReserved - 0XA8, 0X00, // Size, MS OS 2.0 configuration subset - - // Microsoft OS 2.0 功能子集头 - 0x08, 0x00, // Descriptor size (8 bytes) - 0x02, 0x00, // MS OS 2.0 function subset header - 0x01, // 第2个接口 - 0x00, // 必须设置为 0 - 0xA0, 0x00, - - // Microsoft OS 2.0 兼容 ID 描述符 - // 兼容 ID 描述符告诉 Windows 此设备与 WinUSB 驱动程序兼容 - 0x14, 0x00, // wLength 20 - 0x03, 0x00, // MS_OS_20_FEATURE_COMPATIBLE_ID - 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - // Microsoft OS 2.0 注册表属性描述符 - // 注册表属性分配设备接口 GUID - 0x84, 0x00, //wLength: 132 - 0x04, 0x00, // wDescriptorType: MS_OS_20_FEATURE_REG_PROPERTY: 0x04 (Table 9) - 0x07, 0x00, //wPropertyDataType: REG_MULTI_SZ (Table 15) - 0x2a, 0x00, //wPropertyNameLength: - //bPropertyName: “DeviceInterfaceGUID” - 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, - 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, 'U', 0x00, 'I', 0x00, 'D', 0x00, 's', 0x00, - 0x00, 0x00, - 0x50, 0x00, // wPropertyDataLength - //bPropertyData: “{975F44D9-0D08-43FD-8B3E-127CA8AFFF9D}”. - '{', 0x00, '9', 0x00, 'd', 0x00, '7', 0x00, 'd', 0x00, 'e', 0x00, 'b', 0x00, 'b', 0x00, 'c', 0x00, '-', 0x00, - 'c', 0x00, '8', 0x00, '5', 0x00, 'd', 0x00, '-', 0x00, '1', 0x00, '1', 0x00, 'd', 0x00, '1', 0x00, '-', 0x00, - '9', 0x00, 'e', 0x00, 'b', 0x00, '4', 0x00, '-', 0x00, '0', 0x00, '0', 0x00, '6', 0x00, '0', 0x00, '0', 0x00, - '8', 0x00, 'c', 0x00, '3', 0x00, 'a', 0x00, '1', 0x00, '9', 0x00, 'a', 0x00, '}', 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -const uint8_t USBD_WebUSBURLDescriptor[URL_DESCRIPTOR_LENGTH] = { - URL_DESCRIPTOR_LENGTH, - WEBUSB_URL_TYPE, - WEBUSB_URL_SCHEME_HTTPS, - WEBUSB_URL_STRINGS -}; - -struct usb_webusb_url_ex_descriptor webusb_url_desc = { - .vendor_code = WL_REQUEST_WEBUSB, - .string = MS_OS_20_DESCRIPTOR_SET, - .string_len = MS_OS_20_DESCRIPTOR_LENGTH -}; \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/winusb1.0_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/winusb1.0_template.c index c1fbba9..1eb390b 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/winusb1.0_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/winusb1.0_template.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "usbd_core.h" -#include "usbd_cdc.h" +#include "usbd_cdc_acm.h" #define WCID_VENDOR_CODE 0x17 @@ -151,18 +151,16 @@ __ALIGN_BEGIN const uint8_t WINUSB_IF1_WCIDProperties [142] __ALIGN_END = { const uint8_t *WINUSB_IFx_WCIDProperties[] = { WINUSB_IF0_WCIDProperties, +#if DOUBLE_WINUSB == 1 WINUSB_IF1_WCIDProperties, +#endif }; struct usb_msosv1_descriptor msosv1_desc = { .string = WCID_StringDescriptor_MSOS, .vendor_code = WCID_VENDOR_CODE, .compat_id = WINUSB_WCIDDescriptor, -#if DOUBLE_WINUSB == 0 - .comp_id_property = &WINUSB_IF0_WCIDProperties, -#else .comp_id_property = WINUSB_IFx_WCIDProperties, -#endif }; #define WINUSB_IN_EP 0x81 @@ -328,7 +326,7 @@ const uint8_t winusb_descriptor[] = { 0x02, 0x01, 0x40, - 0x01, + 0x00, 0x00, #endif 0x00 @@ -446,7 +444,7 @@ struct usbd_interface intf1; #endif -void winusb_init(uint8_t busid, uint32_t reg_base) +void winusb_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, winusb_descriptor); usbd_msosv1_desc_register(busid, &msosv1_desc); diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/winusb2.0_cdc_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/winusb2.0_cdc_template.c index 8fe6e99..493668e 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/winusb2.0_cdc_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/winusb2.0_cdc_template.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "usbd_core.h" -#include "usbd_cdc.h" +#include "usbd_cdc_acm.h" #define WINUSB_IN_EP 0x81 #define WINUSB_OUT_EP 0x02 @@ -219,7 +219,7 @@ const uint8_t winusbv2_descriptor[] = { 0x00, 0x00, 0x40, - 0x01, + 0x00, 0x00, #endif /* End */ @@ -318,7 +318,7 @@ struct usb_bos_descriptor bos_desc = { .string_len = USBD_BOS_WTOTALLENGTH }; -void winusbv2_init(uint8_t busid, uint32_t reg_base) +void winusbv2_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, winusbv2_descriptor); usbd_bos_desc_register(busid, &bos_desc); diff --git a/rt-thread/components/drivers/usb/cherryusb/demo/winusb2.0_hid_template.c b/rt-thread/components/drivers/usb/cherryusb/demo/winusb2.0_hid_template.c index 8df623e..a209dbd 100644 --- a/rt-thread/components/drivers/usb/cherryusb/demo/winusb2.0_hid_template.c +++ b/rt-thread/components/drivers/usb/cherryusb/demo/winusb2.0_hid_template.c @@ -255,7 +255,7 @@ const uint8_t winusbv2_descriptor[] = { 0x00, 0x00, 0x40, - 0x01, + 0x00, 0x00, #endif /* End */ @@ -422,7 +422,7 @@ struct usb_bos_descriptor bos_desc = { .string_len = USBD_BOS_WTOTALLENGTH }; -void winusbv2_init(uint8_t busid, uint32_t reg_base) +void winusbv2_init(uint8_t busid, uintptr_t reg_base) { usbd_desc_register(busid, winusbv2_descriptor); usbd_bos_desc_register(busid, &bos_desc); diff --git a/rt-thread/components/drivers/usb/cherryusb/idf_component.yml b/rt-thread/components/drivers/usb/cherryusb/idf_component.yml new file mode 100644 index 0000000..a500a24 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/idf_component.yml @@ -0,0 +1,25 @@ +version: "1.4.2" +description: CherryUSB is a tiny and portable USB Stack (device & host) for embedded system with USB IP +tags: + - usb + - usb-device + - usb-host + - cdc_acm + - cdc_ecm + - cdc_ncm + - hid + - msc + - rndis + - uvc + - uac + - winusb +url: https://github.com/cherry-embedded/CherryUSB +repository: https://github.com/cherry-embedded/CherryUSB.git +documentation: https://cherryusb.readthedocs.io/ +issues: https://github.com/cherry-embedded/CherryUSB/issues +dependencies: + idf: ">=5.0" +targets: + - esp32s2 + - esp32s3 + - esp32p4 \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/osal/usb_osal_rtthread.c b/rt-thread/components/drivers/usb/cherryusb/osal/usb_osal_rtthread.c index 18b66a4..d355699 100644 --- a/rt-thread/components/drivers/usb/cherryusb/osal/usb_osal_rtthread.c +++ b/rt-thread/components/drivers/usb/cherryusb/osal/usb_osal_rtthread.c @@ -5,6 +5,8 @@ */ #include "usb_osal.h" #include "usb_errno.h" +#include "usb_config.h" +#include "usb_log.h" #include #include @@ -12,6 +14,11 @@ usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, { rt_thread_t htask; htask = rt_thread_create(name, entry, args, stack_size, prio, 10); + if (htask == NULL) { + USB_LOG_ERR("Create thread %s failed\r\n", name); + while (1) { + } + } rt_thread_startup(htask); return (usb_osal_thread_t)htask; } @@ -27,7 +34,13 @@ void usb_osal_thread_delete(usb_osal_thread_t thread) usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count) { - return (usb_osal_sem_t)rt_sem_create("usbh_sem", initial_count, RT_IPC_FLAG_FIFO); + usb_osal_sem_t sem = (usb_osal_sem_t)rt_sem_create("usbh_sem", initial_count, RT_IPC_FLAG_FIFO); + if (sem == NULL) { + USB_LOG_ERR("Create semaphore failed\r\n"); + while (1) { + } + } + return sem; } void usb_osal_sem_delete(usb_osal_sem_t sem) @@ -68,7 +81,13 @@ void usb_osal_sem_reset(usb_osal_sem_t sem) usb_osal_mutex_t usb_osal_mutex_create(void) { - return (usb_osal_mutex_t)rt_mutex_create("usbh_mutex", RT_IPC_FLAG_FIFO); + usb_osal_mutex_t mutex = (usb_osal_mutex_t)rt_mutex_create("usbh_mutex", RT_IPC_FLAG_FIFO); + if (mutex == NULL) { + USB_LOG_ERR("Create mutex failed\r\n"); + while (1) { + } + } + return mutex; } void usb_osal_mutex_delete(usb_osal_mutex_t mutex) @@ -127,11 +146,18 @@ struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ struct usb_osal_timer *timer; timer = rt_malloc(sizeof(struct usb_osal_timer)); + if (timer == NULL) { + USB_LOG_ERR("Create usb_osal_timer failed\r\n"); + while (1) { + } + } memset(timer, 0, sizeof(struct usb_osal_timer)); - timer->timer = (void *)rt_timer_create("usb_tim", handler, argument, timeout_ms, is_period ? (RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER) : (RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_SOFT_TIMER)); + timer->timer = (void *)rt_timer_create(name, handler, argument, timeout_ms, is_period ? (RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER) : (RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_SOFT_TIMER)); if (timer->timer == NULL) { - return NULL; + USB_LOG_ERR("Create timer failed\r\n"); + while (1) { + } } return timer; } @@ -167,3 +193,13 @@ void usb_osal_msleep(uint32_t delay) { rt_thread_mdelay(delay); } + +void *usb_osal_malloc(size_t size) +{ + return rt_malloc(size); +} + +void usb_osal_free(void *ptr) +{ + rt_free(ptr); +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/platform/rtthread/usb_check.c b/rt-thread/components/drivers/usb/cherryusb/platform/rtthread/usb_check.c index d4baf03..b20e17d 100644 --- a/rt-thread/components/drivers/usb/cherryusb/platform/rtthread/usb_check.c +++ b/rt-thread/components/drivers/usb/cherryusb/platform/rtthread/usb_check.c @@ -1,17 +1,13 @@ #include "rtthread.h" -#ifdef PKG_CHERRYUSB_HOST +#ifdef RT_CHERRYUSB_HOST #ifndef RT_USING_TIMER_SOFT #error must enable RT_USING_TIMER_SOFT to support timer callback in thread #endif -#if IDLE_THREAD_STACK_SIZE < 2048 -#error "IDLE_THREAD_STACK_SIZE must be greater than 2048" -#endif - #if RT_TIMER_THREAD_STACK_SIZE < 2048 -#error "RT_TIMER_THREAD_STACK_SIZE must be greater than 2048" +#error "RT_TIMER_THREAD_STACK_SIZE must be >= 2048" #endif #endif diff --git a/rt-thread/components/drivers/usb/cherryusb/platform/rtthread/usbh_dfs.c b/rt-thread/components/drivers/usb/cherryusb/platform/rtthread/usbh_dfs.c index 12799e6..073d52e 100644 --- a/rt-thread/components/drivers/usb/cherryusb/platform/rtthread/usbh_dfs.c +++ b/rt-thread/components/drivers/usb/cherryusb/platform/rtthread/usbh_dfs.c @@ -9,7 +9,7 @@ #include "rtthread.h" #include -#define DEV_FORMAT "/sd%c" +#define DEV_FORMAT "/dev/sd%c" #ifndef CONFIG_USB_DFS_MOUNT_POINT #define CONFIG_USB_DFS_MOUNT_POINT "/" @@ -36,17 +36,6 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) bflb_l1c_dcache_invalidate_range(addr, size); } } -#elif defined(SOC_HPM5000) || defined(SOC_HPM6000) -#include "hpm_l1c_drv.h" - -void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) -{ - if (ops == RT_HW_CACHE_FLUSH) { - l1c_dc_flush((uint32_t)addr, size); - } else { - l1c_dc_invalidate((uint32_t)addr, size); - } -} #endif USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t msc_sector[512]; @@ -57,7 +46,7 @@ static rt_err_t rt_udisk_init(rt_device_t dev) } static ssize_t rt_udisk_read(rt_device_t dev, rt_off_t pos, void *buffer, - rt_size_t size) + rt_size_t size) { struct usbh_msc *msc_class = (struct usbh_msc *)dev->user_data; int ret; @@ -96,7 +85,7 @@ static ssize_t rt_udisk_read(rt_device_t dev, rt_off_t pos, void *buffer, } static ssize_t rt_udisk_write(rt_device_t dev, rt_off_t pos, const void *buffer, - rt_size_t size) + rt_size_t size) { struct usbh_msc *msc_class = (struct usbh_msc *)dev->user_data; int ret; @@ -186,15 +175,17 @@ int udisk_init(struct usbh_msc *msc_class) ret = usbh_msc_scsi_read10(msc_class, 0, msc_sector, 1); if (ret != RT_EOK) { rt_kprintf("usb mass_storage read failed\n"); + rt_free(dev); return ret; } - for (i = 0; i < 16; i++) { + for (i = 0; i < 4; i++) { /* Get the first partition */ ret = dfs_filesystem_get_partition(&part0, msc_sector, i); if (ret == RT_EOK) { rt_kprintf("Found partition %d: type = %d, offet=0x%x, size=0x%x\n", i, part0.type, part0.offset, part0.size); + break; } else { break; } @@ -230,6 +221,8 @@ void usbh_msc_run(struct usbh_msc *msc_class) void usbh_msc_stop(struct usbh_msc *msc_class) { + struct rt_device *dev; + char name[CONFIG_USBHOST_DEV_NAMELEN]; char mount_point[CONFIG_USBHOST_DEV_NAMELEN]; @@ -237,5 +230,9 @@ void usbh_msc_stop(struct usbh_msc *msc_class) snprintf(mount_point, CONFIG_USBHOST_DEV_NAMELEN, CONFIG_USB_DFS_MOUNT_POINT, msc_class->sdchar); dfs_unmount(mount_point); - rt_device_unregister(rt_device_find(name)); + dev = rt_device_find(name); + if (dev) { + rt_device_unregister(dev); + rt_free(dev); + } } diff --git a/rt-thread/components/drivers/usb/cherryusb/platform/rtthread/usbh_lwip.c b/rt-thread/components/drivers/usb/cherryusb/platform/rtthread/usbh_lwip.c index 360a848..34dc385 100644 --- a/rt-thread/components/drivers/usb/cherryusb/platform/rtthread/usbh_lwip.c +++ b/rt-thread/components/drivers/usb/cherryusb/platform/rtthread/usbh_lwip.c @@ -44,6 +44,10 @@ #error PBUF_POOL_BUFSIZE must be larger than 1600 #endif +#if RT_LWIP_TCPTHREAD_STACKSIZE < 2048 +#error RT_LWIP_TCPTHREAD_STACKSIZE must be >= 2048 +#endif + // #define CONFIG_USBHOST_PLATFORM_CDC_ECM // #define CONFIG_USBHOST_PLATFORM_CDC_RNDIS // #define CONFIG_USBHOST_PLATFORM_CDC_NCM @@ -118,6 +122,7 @@ static rt_err_t rt_usbh_cdc_ecm_control(rt_device_t dev, int cmd, void *args) static rt_err_t rt_usbh_cdc_ecm_eth_tx(rt_device_t dev, struct pbuf *p) { int ret; + (void)dev; usbh_lwip_eth_output_common(p, usbh_cdc_ecm_get_eth_txbuf()); ret = usbh_cdc_ecm_eth_output(p->tot_len); @@ -150,6 +155,8 @@ void usbh_cdc_ecm_run(struct usbh_cdc_ecm *cdc_ecm_class) void usbh_cdc_ecm_stop(struct usbh_cdc_ecm *cdc_ecm_class) { + (void)cdc_ecm_class; + eth_device_deinit(&g_cdc_ecm_dev); } #endif @@ -204,6 +211,7 @@ static rt_err_t rt_usbh_rndis_control(rt_device_t dev, int cmd, void *args) static rt_err_t rt_usbh_rndis_eth_tx(rt_device_t dev, struct pbuf *p) { int ret; + (void)dev; usbh_lwip_eth_output_common(p, usbh_rndis_get_eth_txbuf()); ret = usbh_rndis_eth_output(p->tot_len); @@ -237,6 +245,8 @@ void usbh_rndis_run(struct usbh_rndis *rndis_class) void usbh_rndis_stop(struct usbh_rndis *rndis_class) { + (void)rndis_class; + eth_device_deinit(&g_rndis_dev); // rt_timer_stop(keep_timer); // rt_timer_delete(keep_timer); @@ -273,6 +283,7 @@ static rt_err_t rt_usbh_cdc_ncm_control(rt_device_t dev, int cmd, void *args) static rt_err_t rt_usbh_cdc_ncm_eth_tx(rt_device_t dev, struct pbuf *p) { int ret; + (void)dev; usbh_lwip_eth_output_common(p, usbh_cdc_ncm_get_eth_txbuf()); ret = usbh_cdc_ncm_eth_output(p->tot_len); @@ -305,6 +316,8 @@ void usbh_cdc_ncm_run(struct usbh_cdc_ncm *cdc_ncm_class) void usbh_cdc_ncm_stop(struct usbh_cdc_ncm *cdc_ncm_class) { + (void)cdc_ncm_class; + eth_device_deinit(&g_cdc_ncm_dev); } #endif @@ -339,6 +352,7 @@ static rt_err_t rt_usbh_asix_control(rt_device_t dev, int cmd, void *args) static rt_err_t rt_usbh_asix_eth_tx(rt_device_t dev, struct pbuf *p) { int ret; + (void)dev; usbh_lwip_eth_output_common(p, usbh_asix_get_eth_txbuf()); ret = usbh_asix_eth_output(p->tot_len); @@ -371,6 +385,8 @@ void usbh_asix_run(struct usbh_asix *asix_class) void usbh_asix_stop(struct usbh_asix *asix_class) { + (void)asix_class; + eth_device_deinit(&g_asix_dev); } #endif @@ -405,6 +421,7 @@ static rt_err_t rt_usbh_rtl8152_control(rt_device_t dev, int cmd, void *args) static rt_err_t rt_usbh_rtl8152_eth_tx(rt_device_t dev, struct pbuf *p) { int ret; + (void)dev; usbh_lwip_eth_output_common(p, usbh_rtl8152_get_eth_txbuf()); ret = usbh_rtl8152_eth_output(p->tot_len); @@ -437,6 +454,8 @@ void usbh_rtl8152_run(struct usbh_rtl8152 *rtl8152_class) void usbh_rtl8152_stop(struct usbh_rtl8152 *rtl8152_class) { + (void)rtl8152_class; + eth_device_deinit(&g_rtl8152_dev); } #endif diff --git a/rt-thread/components/drivers/usb/cherryusb/port/bouffalolab/usb_dc_bl.c b/rt-thread/components/drivers/usb/cherryusb/port/bouffalolab/usb_dc_bl.c index 6f45329..b6859f8 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/bouffalolab/usb_dc_bl.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/bouffalolab/usb_dc_bl.c @@ -613,6 +613,23 @@ int usbd_set_address(uint8_t busid, const uint8_t addr) return 0; } +int usbd_set_remote_wakeup(uint8_t busid) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval |= USB_CAP_RMWAKUP; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + bflb_mtimer_delay_ms(10); + + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval &= ~USB_CAP_RMWAKUP; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + return 0; +} + uint8_t usbd_get_port_speed(uint8_t busid) { uint8_t speed = 3; @@ -638,7 +655,7 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) uint8_t ep_idx = USB_EP_GET_IDX(ep_addr); - if ((ep_idx > 4) && (ep_idx < 9)) { + if (ep_idx > 4) { return 0; } @@ -822,6 +839,29 @@ int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) { + uint32_t regval; + + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (ep_idx == 0) { + } else { + if (USB_EP_DIR_IS_OUT(ep)) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); + if (regval & USB_STL_OEP1) { + *stalled = 1; + } else { + *stalled = 0; + } + } else { + regval = getreg32(BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + if (regval & USB_STL_IEP1) { + *stalled = 1; + } else { + *stalled = 0; + } + } + } + return 0; } @@ -1019,12 +1059,11 @@ void USBD_IRQHandler(uint8_t busid) } #ifdef CONFIG_USBDEV_TEST_MODE -void usbd_execute_test_mode(struct usb_setup_packet *setup) +void usbd_execute_test_mode(uint8_t busid, uint8_t test_mode) { uint32_t regval; - uint8_t index = setup->wIndex >> 8; - switch (index) { + switch (test_mode) { case 1: // Test_J { regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbfs.c b/rt-thread/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbfs.c index 4b4b72d..7aabd41 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbfs.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbfs.c @@ -101,6 +101,11 @@ int usbd_set_address(uint8_t busid, const uint8_t addr) return 0; } +int usbd_set_remote_wakeup(uint8_t busid) +{ + return -1; +} + uint8_t usbd_get_port_speed(uint8_t busid) { return USB_SPEED_FULL; diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbhs.c b/rt-thread/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbhs.c index 758ffd7..a8d3036 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbhs.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbhs.c @@ -101,6 +101,11 @@ int usbd_set_address(uint8_t busid, const uint8_t addr) return 0; } +int usbd_set_remote_wakeup(uint8_t busid) +{ + return -1; +} + uint8_t usbd_get_port_speed(uint8_t busid) { return USB_SPEED_HIGH; diff --git a/rt-thread/components/drivers/usb/cherryusb/port/chipidea/README.md b/rt-thread/components/drivers/usb/cherryusb/port/chipidea/README.md new file mode 100644 index 0000000..6a43f79 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/chipidea/README.md @@ -0,0 +1,14 @@ +# Note + +## Support Chip List + +### NXP + +Modify USB_NOCACHE_RAM_SECTION + +``` +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".NonCacheable"))) +``` + +- IMRT10XX/IMRT11XX +- MCXN9XX/MCXN236 diff --git a/rt-thread/components/drivers/usb/cherryusb/port/chipidea/usb_chipidea_reg.h b/rt-thread/components/drivers/usb/cherryusb/port/chipidea/usb_chipidea_reg.h new file mode 100644 index 0000000..4867ef5 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/chipidea/usb_chipidea_reg.h @@ -0,0 +1,2249 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_USB_H +#define HPM_USB_H + +#define __R volatile const /* Define "read-only" permission */ +#define __RW volatile /* Define "read-write" permission */ +#define __W volatile /* Define "write-only" permission */ + +typedef struct { + __R uint8_t RESERVED0[128]; /* 0x0 - 0x7F: Reserved */ + __RW uint32_t GPTIMER0LD; /* 0x80: General Purpose Timer #0 Load Register */ + __RW uint32_t GPTIMER0CTRL; /* 0x84: General Purpose Timer #0 Controller Register */ + __RW uint32_t GPTIMER1LD; /* 0x88: General Purpose Timer #1 Load Register */ + __RW uint32_t GPTIMER1CTRL; /* 0x8C: General Purpose Timer #1 Controller Register */ + __RW uint32_t SBUSCFG; /* 0x90: System Bus Config Register */ + __R uint8_t RESERVED1[172]; /* 0x94 - 0x13F: Reserved */ + __RW uint32_t USBCMD; /* 0x140: USB Command Register */ + __RW uint32_t USBSTS; /* 0x144: USB Status Register */ + __RW uint32_t USBINTR; /* 0x148: Interrupt Enable Register */ + __RW uint32_t FRINDEX; /* 0x14C: USB Frame Index Register */ + __R uint8_t RESERVED2[4]; /* 0x150 - 0x153: Reserved */ + union { + __RW uint32_t DEVICEADDR; /* 0x154: Device Address Register */ + __RW uint32_t PERIODICLISTBASE; /* 0x154: Frame List Base Address Register */ + }; + union { + __RW uint32_t ASYNCLISTADDR; /* 0x158: Next Asynch. Address Register */ + __RW uint32_t ENDPTLISTADDR; /* 0x158: Endpoint List Address Register */ + }; + __R uint8_t RESERVED3[4]; /* 0x15C - 0x15F: Reserved */ + __RW uint32_t BURSTSIZE; /* 0x160: Programmable Burst Size Register */ + __RW uint32_t TXFILLTUNING; /* 0x164: TX FIFO Fill Tuning Register */ + __R uint8_t RESERVED4[16]; /* 0x168 - 0x177: Reserved */ + __RW uint32_t ENDPTNAK; /* 0x178: Endpoint NAK Register */ + __RW uint32_t ENDPTNAKEN; /* 0x17C: Endpoint NAK Enable Register */ + __R uint8_t RESERVED5[4]; /* 0x180 - 0x183: Reserved */ + __RW uint32_t PORTSC1; /* 0x184: Port Status & Control */ + __R uint8_t RESERVED6[28]; /* 0x188 - 0x1A3: Reserved */ + __RW uint32_t OTGSC; /* 0x1A4: On-The-Go Status & control Register */ + __RW uint32_t USBMODE; /* 0x1A8: USB Device Mode Register */ + __RW uint32_t ENDPTSETUPSTAT; /* 0x1AC: Endpoint Setup Status Register */ + __RW uint32_t ENDPTPRIME; /* 0x1B0: Endpoint Prime Register */ + __RW uint32_t ENDPTFLUSH; /* 0x1B4: Endpoint Flush Register */ + __R uint32_t ENDPTSTAT; /* 0x1B8: Endpoint Status Register */ + __RW uint32_t ENDPTCOMPLETE; /* 0x1BC: Endpoint Complete Register */ + __RW uint32_t ENDPTCTRL[8]; /* 0x1C0 - 0x1DC: Endpoint Control0 Register... Endpoint Control7 Register */ +} CHIPIDEA_TypeDef; + + +/* Bitfield definition for register: GPTIMER0LD */ +/* + * GPTLD (RW) + * + * GPTLD + * General Purpose Timer Load Value + * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. + * This value represents the time in microseconds minus 1 for the timer duration. + * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. + * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + */ +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFUL) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER0LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER0LD_GPTLD_SHIFT) & USB_GPTIMER0LD_GPTLD_MASK) +#define USB_GPTIMER0LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER0LD_GPTLD_MASK) >> USB_GPTIMER0LD_GPTLD_SHIFT) + +/* Bitfield definition for register: GPTIMER0CTRL */ +/* + * GPTRUN (RW) + * + * GPTRUN + * General Purpose Timer Run + * GPTCNT bits are not effected when setting or clearing this bit. + * 0 - Stop counting + * 1 - Run + */ +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000UL) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER0CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRUN_SHIFT) & USB_GPTIMER0CTRL_GPTRUN_MASK) +#define USB_GPTIMER0CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRUN_MASK) >> USB_GPTIMER0CTRL_GPTRUN_SHIFT) + +/* + * GPTRST (WO) + * + * GPTRST + * General Purpose Timer Reset + * 0 - No action + * 1 - Load counter value from GPTLD bits in n_GPTIMER0LD + */ +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000UL) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER0CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRST_SHIFT) & USB_GPTIMER0CTRL_GPTRST_MASK) +#define USB_GPTIMER0CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRST_MASK) >> USB_GPTIMER0CTRL_GPTRST_SHIFT) + +/* + * GPTMODE (RW) + * + * GPTMODE + * General Purpose Timer Mode + * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is + * reset by software; + * In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the + * counter value from GPTLD bits to start again. + * 0 - One Shot Mode + * 1 - Repeat Mode + */ +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000UL) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER0CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTMODE_SHIFT) & USB_GPTIMER0CTRL_GPTMODE_MASK) +#define USB_GPTIMER0CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTMODE_MASK) >> USB_GPTIMER0CTRL_GPTMODE_SHIFT) + +/* + * GPTCNT (RO) + * + * GPTCNT + * General Purpose Timer Counter. + * This field is the count value of the countdown timer. + */ +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFUL) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER0CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTCNT_MASK) >> USB_GPTIMER0CTRL_GPTCNT_SHIFT) + +/* Bitfield definition for register: GPTIMER1LD */ +/* + * GPTLD (RW) + * + * GPTLD + * General Purpose Timer Load Value + * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. + * This value represents the time in microseconds minus 1 for the timer duration. + * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. + * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + */ +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFUL) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER1LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER1LD_GPTLD_SHIFT) & USB_GPTIMER1LD_GPTLD_MASK) +#define USB_GPTIMER1LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER1LD_GPTLD_MASK) >> USB_GPTIMER1LD_GPTLD_SHIFT) + +/* Bitfield definition for register: GPTIMER1CTRL */ +/* + * GPTRUN (RW) + * + * GPTRUN + * General Purpose Timer Run + * GPTCNT bits are not effected when setting or clearing this bit. + * 0 - Stop counting + * 1 - Run + */ +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000UL) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER1CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRUN_SHIFT) & USB_GPTIMER1CTRL_GPTRUN_MASK) +#define USB_GPTIMER1CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRUN_MASK) >> USB_GPTIMER1CTRL_GPTRUN_SHIFT) + +/* + * GPTRST (WO) + * + * GPTRST + * General Purpose Timer Reset + * 0 - No action + * 1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + */ +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000UL) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER1CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRST_SHIFT) & USB_GPTIMER1CTRL_GPTRST_MASK) +#define USB_GPTIMER1CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRST_MASK) >> USB_GPTIMER1CTRL_GPTRST_SHIFT) + +/* + * GPTMODE (RW) + * + * GPTMODE + * General Purpose Timer Mode + * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is + * reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and + * automatically reload the counter value from GPTLD bits to start again. + * 0 - One Shot Mode + * 1 - Repeat Mode + */ +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000UL) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER1CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTMODE_SHIFT) & USB_GPTIMER1CTRL_GPTMODE_MASK) +#define USB_GPTIMER1CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTMODE_MASK) >> USB_GPTIMER1CTRL_GPTMODE_SHIFT) + +/* + * GPTCNT (RO) + * + * GPTCNT + * General Purpose Timer Counter. + * This field is the count value of the countdown timer. + */ +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFUL) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER1CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTCNT_MASK) >> USB_GPTIMER1CTRL_GPTCNT_SHIFT) + +/* Bitfield definition for register: SBUSCFG */ +/* + * AHBBRST (RW) + * + * AHBBRST + * AHB master interface Burst configuration + * These bits control AHB master transfer type sequence (or priority). + * NOTE: This register overrides n_BURSTSIZE register when its value is not zero. + * 000 - Incremental burst of unspecified length only + * 001 - INCR4 burst, then single transfer + * 010 - INCR8 burst, INCR4 burst, then single transfer + * 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 100 - Reserved, don't use + * 101 - INCR4 burst, then incremental burst of unspecified length + * 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +#define USB_SBUSCFG_AHBBRST_SET(x) (((uint32_t)(x) << USB_SBUSCFG_AHBBRST_SHIFT) & USB_SBUSCFG_AHBBRST_MASK) +#define USB_SBUSCFG_AHBBRST_GET(x) (((uint32_t)(x) & USB_SBUSCFG_AHBBRST_MASK) >> USB_SBUSCFG_AHBBRST_SHIFT) + +/* Bitfield definition for register: USBCMD */ +/* + * ITC (RW) + * + * ITC + * Interrupt Threshold Control -Read/Write. + * The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. + * ITC contains the maximum interrupt interval measured in micro-frames. Valid values are + * shown below. + * Value Maximum Interrupt Interval + * 00000000 - Immediate (no threshold) + * 00000001 - 1 micro-frame + * 00000010 - 2 micro-frames + * 00000100 - 4 micro-frames + * 00001000 - 8 micro-frames + * 00010000 - 16 micro-frames + * 00100000 - 32 micro-frames + * 01000000 - 64 micro-frames + */ +#define USB_USBCMD_ITC_MASK (0xFF0000UL) +#define USB_USBCMD_ITC_SHIFT (16U) +#define USB_USBCMD_ITC_SET(x) (((uint32_t)(x) << USB_USBCMD_ITC_SHIFT) & USB_USBCMD_ITC_MASK) +#define USB_USBCMD_ITC_GET(x) (((uint32_t)(x) & USB_USBCMD_ITC_MASK) >> USB_USBCMD_ITC_SHIFT) + +/* + * FS_2 (RW) + * + * FS_2 + * Frame List Size - (Read/Write or Read Only). [host mode only] + * This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. + * This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. + * NOTE: This field is made up from USBCMD bits 15, 3 and 2. + * Value Meaning + * 0b000 - 1024 elements (4096 bytes) Default value + * 0b001 - 512 elements (2048 bytes) + * 0b010 - 256 elements (1024 bytes) + * 0b011 - 128 elements (512 bytes) + * 0b100 - 64 elements (256 bytes) + * 0b101 - 32 elements (128 bytes) + * 0b110 - 16 elements (64 bytes) + * 0b111 - 8 elements (32 bytes) + */ +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +#define USB_USBCMD_FS_2_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_2_SHIFT) & USB_USBCMD_FS_2_MASK) +#define USB_USBCMD_FS_2_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_2_MASK) >> USB_USBCMD_FS_2_SHIFT) + +/* + * ATDTW (RW) + * + * ATDTW + * Add dTD TripWire - Read/Write. [device mode only] + * This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's + * linked list. This bit is set and cleared by software. + * This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD + * to a primed endpoint may go unrecognized. + */ +#define USB_USBCMD_ATDTW_MASK (0x4000U) +#define USB_USBCMD_ATDTW_SHIFT (14U) +#define USB_USBCMD_ATDTW_SET(x) (((uint32_t)(x) << USB_USBCMD_ATDTW_SHIFT) & USB_USBCMD_ATDTW_MASK) +#define USB_USBCMD_ATDTW_GET(x) (((uint32_t)(x) & USB_USBCMD_ATDTW_MASK) >> USB_USBCMD_ATDTW_SHIFT) + +/* + * SUTW (RW) + * + * SUTW + * Setup TripWire - Read/Write. [device mode only] + * This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. + * If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then + * there is a hazard when new setup data arrives while the DCD is copying the setup data payload + * from the QH for a previous setup packet. This bit is set and cleared by software. + * This bit would also be cleared by hardware when a hazard detected. + */ +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +#define USB_USBCMD_SUTW_SET(x) (((uint32_t)(x) << USB_USBCMD_SUTW_SHIFT) & USB_USBCMD_SUTW_MASK) +#define USB_USBCMD_SUTW_GET(x) (((uint32_t)(x) & USB_USBCMD_SUTW_MASK) >> USB_USBCMD_SUTW_SHIFT) + +/* + * ASPE (RW) + * + * ASPE + * Asynchronous Schedule Park Mode Enable - Read/Write. + * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. + * Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. + * When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. + * NOTE: ASPE bit reset value: '0b' for OTG controller . + */ +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +#define USB_USBCMD_ASPE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASPE_SHIFT) & USB_USBCMD_ASPE_MASK) +#define USB_USBCMD_ASPE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASPE_MASK) >> USB_USBCMD_ASPE_SHIFT) + +/* + * ASP (RW) + * + * ASP + * Asynchronous Schedule Park Mode Count - Read/Write. + * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. + * It contains a count of the number of successive transactions the host controller is allowed to + * execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. + * Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. + * This field is set to 3h in all controller core. + */ +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +#define USB_USBCMD_ASP_SET(x) (((uint32_t)(x) << USB_USBCMD_ASP_SHIFT) & USB_USBCMD_ASP_MASK) +#define USB_USBCMD_ASP_GET(x) (((uint32_t)(x) & USB_USBCMD_ASP_MASK) >> USB_USBCMD_ASP_SHIFT) + +/* + * IAA (RW) + * + * IAA + * Interrupt on Async Advance Doorbell - Read/Write. + * This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. + * When the host controller has evicted all appropriate cached schedule states, + * it sets the Interrupt on Async Advance status bit in the USBSTS register. + * If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. + * The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. + * Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. + * This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. + */ +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +#define USB_USBCMD_IAA_SET(x) (((uint32_t)(x) << USB_USBCMD_IAA_SHIFT) & USB_USBCMD_IAA_MASK) +#define USB_USBCMD_IAA_GET(x) (((uint32_t)(x) & USB_USBCMD_IAA_MASK) >> USB_USBCMD_IAA_SHIFT) + +/* + * ASE (RW) + * + * ASE + * Asynchronous Schedule Enable - Read/Write. Default 0b. + * This bit controls whether the host controller skips processing the Asynchronous Schedule. + * Only the host controller uses this bit. + * Values Meaning + * 0 - Do not process the Asynchronous Schedule. + * 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + */ +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +#define USB_USBCMD_ASE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASE_SHIFT) & USB_USBCMD_ASE_MASK) +#define USB_USBCMD_ASE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASE_MASK) >> USB_USBCMD_ASE_SHIFT) + +/* + * PSE (RW) + * + * PSE + * Periodic Schedule Enable- Read/Write. Default 0b. + * This bit controls whether the host controller skips processing the Periodic Schedule. + * Only the host controller uses this bit. + * Values Meaning + * 0 - Do not process the Periodic Schedule + * 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. + */ +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +#define USB_USBCMD_PSE_SET(x) (((uint32_t)(x) << USB_USBCMD_PSE_SHIFT) & USB_USBCMD_PSE_MASK) +#define USB_USBCMD_PSE_GET(x) (((uint32_t)(x) & USB_USBCMD_PSE_MASK) >> USB_USBCMD_PSE_SHIFT) + +/* + * FS_1 (RW) + * + * FS_1 + * See description at bit 15 + */ +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +#define USB_USBCMD_FS_1_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_1_SHIFT) & USB_USBCMD_FS_1_MASK) +#define USB_USBCMD_FS_1_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_1_MASK) >> USB_USBCMD_FS_1_SHIFT) + +/* + * RST (RW) + * + * RST + * Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. + * This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. + * Host operation mode: + * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. + * Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. + * Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. + * Attempting to reset an actively running host controller will result in undefined behavior. + * Device operation mode: + * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. + * Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. + * In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + */ +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +#define USB_USBCMD_RST_SET(x) (((uint32_t)(x) << USB_USBCMD_RST_SHIFT) & USB_USBCMD_RST_MASK) +#define USB_USBCMD_RST_GET(x) (((uint32_t)(x) & USB_USBCMD_RST_MASK) >> USB_USBCMD_RST_SHIFT) + +/* + * RS (RW) + * + * RS + * Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. + * Host operation mode: + * When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. + * When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. + * The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. + * Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). + * Device operation mode: + * Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. + * This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. + * Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + */ +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +#define USB_USBCMD_RS_SET(x) (((uint32_t)(x) << USB_USBCMD_RS_SHIFT) & USB_USBCMD_RS_MASK) +#define USB_USBCMD_RS_GET(x) (((uint32_t)(x) & USB_USBCMD_RS_MASK) >> USB_USBCMD_RS_SHIFT) + +/* Bitfield definition for register: USBSTS */ +/* + * TI1 (RWC) + * + * TI1 + * General Purpose Timer Interrupt 1(GPTINT1)--R/WC. + * This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this + * bit will clear it. + */ +#define USB_USBSTS_TI1_MASK (0x2000000UL) +#define USB_USBSTS_TI1_SHIFT (25U) +#define USB_USBSTS_TI1_SET(x) (((uint32_t)(x) << USB_USBSTS_TI1_SHIFT) & USB_USBSTS_TI1_MASK) +#define USB_USBSTS_TI1_GET(x) (((uint32_t)(x) & USB_USBSTS_TI1_MASK) >> USB_USBSTS_TI1_SHIFT) + +/* + * TI0 (RWC) + * + * TI0 + * General Purpose Timer Interrupt 0(GPTINT0)--R/WC. + * This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this + * bit clears it. + */ +#define USB_USBSTS_TI0_MASK (0x1000000UL) +#define USB_USBSTS_TI0_SHIFT (24U) +#define USB_USBSTS_TI0_SET(x) (((uint32_t)(x) << USB_USBSTS_TI0_SHIFT) & USB_USBSTS_TI0_MASK) +#define USB_USBSTS_TI0_GET(x) (((uint32_t)(x) & USB_USBSTS_TI0_MASK) >> USB_USBSTS_TI0_SHIFT) + +/* + * UPI (RWC) + * + * USB Host Periodic Interrupt – RWC. Default = 0b. + * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction + * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. + * This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. + * A short packet is when the actual number of bytes received was less than expected. + * This bit is not used by the device controller and will always be zero. + */ +#define USB_USBSTS_UPI_MASK (0x80000UL) +#define USB_USBSTS_UPI_SHIFT (19U) +#define USB_USBSTS_UPI_SET(x) (((uint32_t)(x) << USB_USBSTS_UPI_SHIFT) & USB_USBSTS_UPI_MASK) +#define USB_USBSTS_UPI_GET(x) (((uint32_t)(x) & USB_USBSTS_UPI_MASK) >> USB_USBSTS_UPI_SHIFT) + +/* + * UAI (RWC) + * + * USB Host Asynchronous Interrupt – RWC. Default = 0b. + * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction + * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. + * This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. + * A short packet is when the actual number of bytes received was less than expected. + * This bit is not used by the device controller and will always be zero + */ +#define USB_USBSTS_UAI_MASK (0x40000UL) +#define USB_USBSTS_UAI_SHIFT (18U) +#define USB_USBSTS_UAI_SET(x) (((uint32_t)(x) << USB_USBSTS_UAI_SHIFT) & USB_USBSTS_UAI_MASK) +#define USB_USBSTS_UAI_GET(x) (((uint32_t)(x) & USB_USBSTS_UAI_MASK) >> USB_USBSTS_UAI_SHIFT) + +/* + * NAKI (RO) + * + * NAKI + * NAK Interrupt Bit--RO. + * This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and + * corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware + * when all Enabled TX/RX Endpoint NAK bits are cleared. + */ +#define USB_USBSTS_NAKI_MASK (0x10000UL) +#define USB_USBSTS_NAKI_SHIFT (16U) +#define USB_USBSTS_NAKI_GET(x) (((uint32_t)(x) & USB_USBSTS_NAKI_MASK) >> USB_USBSTS_NAKI_SHIFT) + +/* + * AS (RO) + * + * AS + * Asynchronous Schedule Status - Read Only. + * This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. + * The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. + * When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). + * Only used in the host operation mode. + */ +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +#define USB_USBSTS_AS_GET(x) (((uint32_t)(x) & USB_USBSTS_AS_MASK) >> USB_USBSTS_AS_SHIFT) + +/* + * PS (RO) + * + * PS + * Periodic Schedule Status - Read Only. + * This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. + * The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. + * When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). + * Only used in the host operation mode. + */ +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +#define USB_USBSTS_PS_GET(x) (((uint32_t)(x) & USB_USBSTS_PS_MASK) >> USB_USBSTS_PS_SHIFT) + +/* + * RCL (RO) + * + * RCL + * Reclamation - Read Only. + * This is a read-only status bit used to detect an empty asynchronous schedule. + * Only used in the host operation mode. + */ +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +#define USB_USBSTS_RCL_GET(x) (((uint32_t)(x) & USB_USBSTS_RCL_MASK) >> USB_USBSTS_RCL_SHIFT) + +/* + * HCH (RO) + * + * HCH + * HCHaIted - Read Only. + * This bit is a zero whenever the Run/Stop bit is a one. + * The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, + * either by software or by the Controller hardware (for example, an internal error). + * Only used in the host operation mode. + * Default value is '0b' for OTG core . + * This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE + * register. + * NOTE: HCH bit reset value: '0b' for OTG controller core . + */ +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +#define USB_USBSTS_HCH_GET(x) (((uint32_t)(x) & USB_USBSTS_HCH_MASK) >> USB_USBSTS_HCH_SHIFT) + +/* + * SLI (RWC) + * + * SLI + * DCSuspend - R/WC. + * When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. + * Only used in device operation mode. + */ +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +#define USB_USBSTS_SLI_SET(x) (((uint32_t)(x) << USB_USBSTS_SLI_SHIFT) & USB_USBSTS_SLI_MASK) +#define USB_USBSTS_SLI_GET(x) (((uint32_t)(x) & USB_USBSTS_SLI_MASK) >> USB_USBSTS_SLI_SHIFT) + +/* + * SRI (RWC) + * + * SRI + * SOF Received - R/WC. + * When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. + * When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. + * Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. + * Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. + * In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. + * Software writes a 1 to this bit to clear it. + */ +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +#define USB_USBSTS_SRI_SET(x) (((uint32_t)(x) << USB_USBSTS_SRI_SHIFT) & USB_USBSTS_SRI_MASK) +#define USB_USBSTS_SRI_GET(x) (((uint32_t)(x) & USB_USBSTS_SRI_MASK) >> USB_USBSTS_SRI_SHIFT) + +/* + * URI (RWC) + * + * URI + * USB Reset Received - R/WC. + * When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. + * Software can write a 1 to this bit to clear the USB Reset Received status bit. + * Only used in device operation mode. + */ +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +#define USB_USBSTS_URI_SET(x) (((uint32_t)(x) << USB_USBSTS_URI_SHIFT) & USB_USBSTS_URI_MASK) +#define USB_USBSTS_URI_GET(x) (((uint32_t)(x) & USB_USBSTS_URI_MASK) >> USB_USBSTS_URI_SHIFT) + +/* + * AAI (RWC) + * + * AAI + * Interrupt on Async Advance - R/WC. + * System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule + * by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. + * Only used in host operation mode. + */ +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +#define USB_USBSTS_AAI_SET(x) (((uint32_t)(x) << USB_USBSTS_AAI_SHIFT) & USB_USBSTS_AAI_MASK) +#define USB_USBSTS_AAI_GET(x) (((uint32_t)(x) & USB_USBSTS_AAI_MASK) >> USB_USBSTS_AAI_SHIFT) + +/* + * SEI (RWC) + * + * System Error – RWC. Default = 0b. + * In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. + * In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + */ +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +#define USB_USBSTS_SEI_SET(x) (((uint32_t)(x) << USB_USBSTS_SEI_SHIFT) & USB_USBSTS_SEI_MASK) +#define USB_USBSTS_SEI_GET(x) (((uint32_t)(x) & USB_USBSTS_SEI_MASK) >> USB_USBSTS_SEI_SHIFT) + +/* + * FRI (RWC) + * + * FRI + * Frame List Rollover - R/WC. + * The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to + * zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the + * frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the + * Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host + * Controller sets this bit to a one every time FHINDEX [12] toggles. + * Only used in host operation mode. + */ +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +#define USB_USBSTS_FRI_SET(x) (((uint32_t)(x) << USB_USBSTS_FRI_SHIFT) & USB_USBSTS_FRI_MASK) +#define USB_USBSTS_FRI_GET(x) (((uint32_t)(x) & USB_USBSTS_FRI_MASK) >> USB_USBSTS_FRI_SHIFT) + +/* + * PCI (RWC) + * + * PCI + * Port Change Detect - R/WC. + * The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, + * or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. + * The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. + * When the port controller exits the full or high-speed operation states due to Reset or Suspend events, + * the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + */ +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +#define USB_USBSTS_PCI_SET(x) (((uint32_t)(x) << USB_USBSTS_PCI_SHIFT) & USB_USBSTS_PCI_MASK) +#define USB_USBSTS_PCI_GET(x) (((uint32_t)(x) & USB_USBSTS_PCI_MASK) >> USB_USBSTS_PCI_SHIFT) + +/* + * UEI (RWC) + * + * UEI + * USB Error Interrupt (USBERRINT) - R/WC. + * When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. + * This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + */ +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +#define USB_USBSTS_UEI_SET(x) (((uint32_t)(x) << USB_USBSTS_UEI_SHIFT) & USB_USBSTS_UEI_MASK) +#define USB_USBSTS_UEI_GET(x) (((uint32_t)(x) & USB_USBSTS_UEI_MASK) >> USB_USBSTS_UEI_SHIFT) + +/* + * UI (RWC) + * + * UI + * USB Interrupt (USBINT) - R/WC. + * This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB + * transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. + * This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when + * the actual number of bytes received was less than the expected number of bytes. + */ +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +#define USB_USBSTS_UI_SET(x) (((uint32_t)(x) << USB_USBSTS_UI_SHIFT) & USB_USBSTS_UI_MASK) +#define USB_USBSTS_UI_GET(x) (((uint32_t)(x) & USB_USBSTS_UI_MASK) >> USB_USBSTS_UI_SHIFT) + +/* Bitfield definition for register: USBINTR */ +/* + * TIE1 (RW) + * + * TIE1 + * General Purpose Timer #1 Interrupt Enable + * When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_TIE1_MASK (0x2000000UL) +#define USB_USBINTR_TIE1_SHIFT (25U) +#define USB_USBINTR_TIE1_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE1_SHIFT) & USB_USBINTR_TIE1_MASK) +#define USB_USBINTR_TIE1_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE1_MASK) >> USB_USBINTR_TIE1_SHIFT) + +/* + * TIE0 (RW) + * + * TIE0 + * General Purpose Timer #0 Interrupt Enable + * When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_TIE0_MASK (0x1000000UL) +#define USB_USBINTR_TIE0_SHIFT (24U) +#define USB_USBINTR_TIE0_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE0_SHIFT) & USB_USBINTR_TIE0_MASK) +#define USB_USBINTR_TIE0_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE0_MASK) >> USB_USBINTR_TIE0_SHIFT) + +/* + * UPIE (RW) + * + * UPIE + * USB Host Periodic Interrupt Enable + * When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an + * interrupt at the next interrupt threshold. + */ +#define USB_USBINTR_UPIE_MASK (0x80000UL) +#define USB_USBINTR_UPIE_SHIFT (19U) +#define USB_USBINTR_UPIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UPIE_SHIFT) & USB_USBINTR_UPIE_MASK) +#define USB_USBINTR_UPIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UPIE_MASK) >> USB_USBINTR_UPIE_SHIFT) + +/* + * UAIE (RW) + * + * UAIE + * USB Host Asynchronous Interrupt Enable + * When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an + * interrupt at the next interrupt threshold. + */ +#define USB_USBINTR_UAIE_MASK (0x40000UL) +#define USB_USBINTR_UAIE_SHIFT (18U) +#define USB_USBINTR_UAIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UAIE_SHIFT) & USB_USBINTR_UAIE_MASK) +#define USB_USBINTR_UAIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UAIE_MASK) >> USB_USBINTR_UAIE_SHIFT) + +/* + * NAKE (RO) + * + * NAKE + * NAK Interrupt Enable + * When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_NAKE_MASK (0x10000UL) +#define USB_USBINTR_NAKE_SHIFT (16U) +#define USB_USBINTR_NAKE_GET(x) (((uint32_t)(x) & USB_USBINTR_NAKE_MASK) >> USB_USBINTR_NAKE_SHIFT) + +/* + * SLE (RW) + * + * SLE + * Sleep Interrupt Enable + * When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. + * Only used in device operation mode. + */ +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +#define USB_USBINTR_SLE_SET(x) (((uint32_t)(x) << USB_USBINTR_SLE_SHIFT) & USB_USBINTR_SLE_MASK) +#define USB_USBINTR_SLE_GET(x) (((uint32_t)(x) & USB_USBINTR_SLE_MASK) >> USB_USBINTR_SLE_SHIFT) + +/* + * SRE (RW) + * + * SRE + * SOF Received Interrupt Enable + * When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +#define USB_USBINTR_SRE_SET(x) (((uint32_t)(x) << USB_USBINTR_SRE_SHIFT) & USB_USBINTR_SRE_MASK) +#define USB_USBINTR_SRE_GET(x) (((uint32_t)(x) & USB_USBINTR_SRE_MASK) >> USB_USBINTR_SRE_SHIFT) + +/* + * URE (RW) + * + * URE + * USB Reset Interrupt Enable + * When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. + * Only used in device operation mode. + */ +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +#define USB_USBINTR_URE_SET(x) (((uint32_t)(x) << USB_USBINTR_URE_SHIFT) & USB_USBINTR_URE_MASK) +#define USB_USBINTR_URE_GET(x) (((uint32_t)(x) & USB_USBINTR_URE_MASK) >> USB_USBINTR_URE_SHIFT) + +/* + * AAE (RW) + * + * AAE + * Async Advance Interrupt Enable + * When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. + * Only used in host operation mode. + */ +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +#define USB_USBINTR_AAE_SET(x) (((uint32_t)(x) << USB_USBINTR_AAE_SHIFT) & USB_USBINTR_AAE_MASK) +#define USB_USBINTR_AAE_GET(x) (((uint32_t)(x) & USB_USBINTR_AAE_MASK) >> USB_USBINTR_AAE_SHIFT) + +/* + * SEE (RW) + * + * SEE + * System Error Interrupt Enable + * When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. + * Only used in host operation mode. + */ +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +#define USB_USBINTR_SEE_SET(x) (((uint32_t)(x) << USB_USBINTR_SEE_SHIFT) & USB_USBINTR_SEE_MASK) +#define USB_USBINTR_SEE_GET(x) (((uint32_t)(x) & USB_USBINTR_SEE_MASK) >> USB_USBINTR_SEE_SHIFT) + +/* + * FRE (RW) + * + * FRE + * Frame List Rollover Interrupt Enable + * When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. + * Only used in host operation mode. + */ +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +#define USB_USBINTR_FRE_SET(x) (((uint32_t)(x) << USB_USBINTR_FRE_SHIFT) & USB_USBINTR_FRE_MASK) +#define USB_USBINTR_FRE_GET(x) (((uint32_t)(x) & USB_USBINTR_FRE_MASK) >> USB_USBINTR_FRE_SHIFT) + +/* + * PCE (RW) + * + * PCE + * Port Change Detect Interrupt Enable + * When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +#define USB_USBINTR_PCE_SET(x) (((uint32_t)(x) << USB_USBINTR_PCE_SHIFT) & USB_USBINTR_PCE_MASK) +#define USB_USBINTR_PCE_GET(x) (((uint32_t)(x) & USB_USBINTR_PCE_MASK) >> USB_USBINTR_PCE_SHIFT) + +/* + * UEE (RWC) + * + * UEE + * USB Error Interrupt Enable + * When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +#define USB_USBINTR_UEE_SET(x) (((uint32_t)(x) << USB_USBINTR_UEE_SHIFT) & USB_USBINTR_UEE_MASK) +#define USB_USBINTR_UEE_GET(x) (((uint32_t)(x) & USB_USBINTR_UEE_MASK) >> USB_USBINTR_UEE_SHIFT) + +/* + * UE (RW) + * + * UE + * USB Interrupt Enable + * When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +#define USB_USBINTR_UE_SET(x) (((uint32_t)(x) << USB_USBINTR_UE_SHIFT) & USB_USBINTR_UE_MASK) +#define USB_USBINTR_UE_GET(x) (((uint32_t)(x) & USB_USBINTR_UE_MASK) >> USB_USBINTR_UE_SHIFT) + +/* Bitfield definition for register: FRINDEX */ +/* + * FRINDEX (RW) + * + * FRINDEX + * Frame Index. + * The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. + * This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. + * The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. + * USBCMD [Frame List Size] Number Elements N + * In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. + * In either mode bits 2:0 indicate the current microframe. + * The bit field values description below is represented as (Frame List Size) Number Elements N. + * 00000000000000 - (1024) 12 + * 00000000000001 - (512) 11 + * 00000000000010 - (256) 10 + * 00000000000011 - (128) 9 + * 00000000000100 - (64) 8 + * 00000000000101 - (32) 7 + * 00000000000110 - (16) 6 + * 00000000000111 - (8) 5 + */ +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +#define USB_FRINDEX_FRINDEX_SET(x) (((uint32_t)(x) << USB_FRINDEX_FRINDEX_SHIFT) & USB_FRINDEX_FRINDEX_MASK) +#define USB_FRINDEX_FRINDEX_GET(x) (((uint32_t)(x) & USB_FRINDEX_FRINDEX_MASK) >> USB_FRINDEX_FRINDEX_SHIFT) + +/* Bitfield definition for register: DEVICEADDR */ +/* + * USBADR (RW) + * + * USBADR + * Device Address. + * These bits correspond to the USB device address + */ +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000UL) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +#define USB_DEVICEADDR_USBADR_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADR_SHIFT) & USB_DEVICEADDR_USBADR_MASK) +#define USB_DEVICEADDR_USBADR_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADR_MASK) >> USB_DEVICEADDR_USBADR_SHIFT) + +/* + * USBADRA (RW) + * + * USBADRA + * Device Address Advance. Default=0. + * When this bit is '0', any writes to USBADR are instantaneous. + * When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. + * After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. + * Hardware will automatically clear this bit on the following conditions: + * 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). + * 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). + * 3) Device Reset occurs (USBADR is reset to 0). + * NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. + * This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. + * If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), + * the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + */ +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000UL) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +#define USB_DEVICEADDR_USBADRA_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADRA_SHIFT) & USB_DEVICEADDR_USBADRA_MASK) +#define USB_DEVICEADDR_USBADRA_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADRA_MASK) >> USB_DEVICEADDR_USBADRA_SHIFT) + +/* Bitfield definition for register: PERIODICLISTBASE */ +/* + * BASEADR (RW) + * + * BASEADR + * Base Address (Low). + * These bits correspond to memory address signals [31:12], respectively. + * Only used by the host controller. + */ +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000UL) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +#define USB_PERIODICLISTBASE_BASEADR_SET(x) (((uint32_t)(x) << USB_PERIODICLISTBASE_BASEADR_SHIFT) & USB_PERIODICLISTBASE_BASEADR_MASK) +#define USB_PERIODICLISTBASE_BASEADR_GET(x) (((uint32_t)(x) & USB_PERIODICLISTBASE_BASEADR_MASK) >> USB_PERIODICLISTBASE_BASEADR_SHIFT) + +/* Bitfield definition for register: ASYNCLISTADDR */ +/* + * ASYBASE (RW) + * + * ASYBASE + * Link Pointer Low (LPL). + * These bits correspond to memory address signals [31:5], respectively. This field may only reference a + * Queue Head (QH). + * Only used by the host controller. + */ +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0UL) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +#define USB_ASYNCLISTADDR_ASYBASE_SET(x) (((uint32_t)(x) << USB_ASYNCLISTADDR_ASYBASE_SHIFT) & USB_ASYNCLISTADDR_ASYBASE_MASK) +#define USB_ASYNCLISTADDR_ASYBASE_GET(x) (((uint32_t)(x) & USB_ASYNCLISTADDR_ASYBASE_MASK) >> USB_ASYNCLISTADDR_ASYBASE_SHIFT) + +/* Bitfield definition for register: ENDPTLISTADDR */ +/* + * EPBASE (RW) + * + * EPBASE + * Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. + * This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + */ +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800UL) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +#define USB_ENDPTLISTADDR_EPBASE_SET(x) (((uint32_t)(x) << USB_ENDPTLISTADDR_EPBASE_SHIFT) & USB_ENDPTLISTADDR_EPBASE_MASK) +#define USB_ENDPTLISTADDR_EPBASE_GET(x) (((uint32_t)(x) & USB_ENDPTLISTADDR_EPBASE_MASK) >> USB_ENDPTLISTADDR_EPBASE_SHIFT) + +/* Bitfield definition for register: BURSTSIZE */ +/* + * TXPBURST (RW) + * + * TXPBURST + * Programmable TX Burst Size. + * Default value is determined by TXBURST bits in n_HWTXBUF. + * This register represents the maximum length of a the burst in 32-bit words while moving data from system + * memory to the USB bus. + */ +#define USB_BURSTSIZE_TXPBURST_MASK (0xFF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +#define USB_BURSTSIZE_TXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_TXPBURST_SHIFT) & USB_BURSTSIZE_TXPBURST_MASK) +#define USB_BURSTSIZE_TXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_TXPBURST_MASK) >> USB_BURSTSIZE_TXPBURST_SHIFT) + +/* + * RXPBURST (RW) + * + * RXPBURST + * Programmable RX Burst Size. + * Default value is determined by TXBURST bits in n_HWRXBUF. + * This register represents the maximum length of a the burst in 32-bit words while moving data from the + * USB bus to system memory. + */ +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +#define USB_BURSTSIZE_RXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_RXPBURST_SHIFT) & USB_BURSTSIZE_RXPBURST_MASK) +#define USB_BURSTSIZE_RXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_RXPBURST_MASK) >> USB_BURSTSIZE_RXPBURST_SHIFT) + +/* Bitfield definition for register: TXFILLTUNING */ +/* + * TXFIFOTHRES (RW) + * + * TXFIFOTHRES + * FIFO Burst Threshold. (Read/Write) + * This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. + * The minimum value is 2 and this value should be a low as possible to maximize USB performance. + * A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth + * where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. + * This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + */ +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000UL) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) +#define USB_TXFILLTUNING_TXFIFOTHRES_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) >> USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) + +/* + * TXSCHHEALTH (RWC) + * + * TXSCHHEALTH + * Scheduler Health Counter. (Read/Write To Clear) + * Table continues on the next page + * This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES + * before running out of time to send the packet before the next Start-Of-Frame. + * This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. + * Writing to this register will clear the counter and this counter will max. at 31. + */ +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) +#define USB_TXFILLTUNING_TXSCHHEALTH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) >> USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) + +/* + * TXSCHOH (RW) + * + * TXSCHOH + * Scheduler Overhead. (Read/Write) [Default = 0] + * This register adds an additional fixed offset to the schedule time estimator described above as Tff. + * As an approximation, the value chosen for this register should limit the number of back-off events captured + * in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. + * Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. + * The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. + * The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. + * Default value is '08h' for OTG controller core . + */ +#define USB_TXFILLTUNING_TXSCHOH_MASK (0x7FU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +#define USB_TXFILLTUNING_TXSCHOH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHOH_SHIFT) & USB_TXFILLTUNING_TXSCHOH_MASK) +#define USB_TXFILLTUNING_TXSCHOH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHOH_MASK) >> USB_TXFILLTUNING_TXSCHOH_SHIFT) + +/* Bitfield definition for register: ENDPTNAK */ +/* + * EPTN (RWC) + * + * EPTN + * TX Endpoint NAK - R/WC. + * Each TX endpoint has 1 bit in this field. The bit is set when the + * device sends a NAK handshake on a received IN token for the corresponding endpoint. + * Bit [N] - Endpoint #[N], N is 0-7 + */ +#define USB_ENDPTNAK_EPTN_MASK (0xFFFF0000UL) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +#define USB_ENDPTNAK_EPTN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPTN_SHIFT) & USB_ENDPTNAK_EPTN_MASK) +#define USB_ENDPTNAK_EPTN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPTN_MASK) >> USB_ENDPTNAK_EPTN_SHIFT) + +/* + * EPRN (RWC) + * + * EPRN + * RX Endpoint NAK - R/WC. + * Each RX endpoint has 1 bit in this field. The bit is set when the + * device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. + * Bit [N] - Endpoint #[N], N is 0-7 + */ +#define USB_ENDPTNAK_EPRN_MASK (0xFFFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +#define USB_ENDPTNAK_EPRN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPRN_SHIFT) & USB_ENDPTNAK_EPRN_MASK) +#define USB_ENDPTNAK_EPRN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPRN_MASK) >> USB_ENDPTNAK_EPRN_SHIFT) + +/* Bitfield definition for register: ENDPTNAKEN */ +/* + * EPTNE (RW) + * + * EPTNE + * TX Endpoint NAK Enable - R/W. + * Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the + * corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. + * Bit [N] - Endpoint #[N], N is 0-7 + */ +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFFFF0000UL) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +#define USB_ENDPTNAKEN_EPTNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPTNE_SHIFT) & USB_ENDPTNAKEN_EPTNE_MASK) +#define USB_ENDPTNAKEN_EPTNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPTNE_MASK) >> USB_ENDPTNAKEN_EPTNE_SHIFT) + +/* + * EPRNE (RW) + * + * EPRNE + * RX Endpoint NAK Enable - R/W. + * Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the + * corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. + * Bit [N] - Endpoint #[N], N is 0-7 + */ +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +#define USB_ENDPTNAKEN_EPRNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPRNE_SHIFT) & USB_ENDPTNAKEN_EPRNE_MASK) +#define USB_ENDPTNAKEN_EPRNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPRNE_MASK) >> USB_ENDPTNAKEN_EPRNE_SHIFT) + +/* Bitfield definition for register: PORTSC1 */ +/* + * STS (RW) + * + * STS + * Serial Transceiver Select + * 1 Serial Interface Engine is selected + * 0 Parallel Interface signals is selected + * Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. + * When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + */ +#define USB_PORTSC1_STS_MASK (0x20000000UL) +#define USB_PORTSC1_STS_SHIFT (29U) +#define USB_PORTSC1_STS_SET(x) (((uint32_t)(x) << USB_PORTSC1_STS_SHIFT) & USB_PORTSC1_STS_MASK) +#define USB_PORTSC1_STS_GET(x) (((uint32_t)(x) & USB_PORTSC1_STS_MASK) >> USB_PORTSC1_STS_SHIFT) + +/* + * PTW (RW) + * + * PTW + * Parallel Transceiver Width + * This bit has no effect if serial interface engine is used. + * 0 - Select the 8-bit UTMI interface [60MHz] + * 1 - Select the 16-bit UTMI interface [30MHz] + */ +#define USB_PORTSC1_PTW_MASK (0x10000000UL) +#define USB_PORTSC1_PTW_SHIFT (28U) +#define USB_PORTSC1_PTW_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTW_SHIFT) & USB_PORTSC1_PTW_MASK) +#define USB_PORTSC1_PTW_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTW_MASK) >> USB_PORTSC1_PTW_SHIFT) + +/* + * PSPD (RO) + * + * PSPD + * Port Speed - Read Only. + * This register field indicates the speed at which the port is operating. + * 00 - Full Speed + * 01 - Low Speed + * 10 - High Speed + * 11 - Undefined + */ +#define USB_PORTSC1_PSPD_MASK (0xC000000UL) +#define USB_PORTSC1_PSPD_SHIFT (26U) +#define USB_PORTSC1_PSPD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PSPD_MASK) >> USB_PORTSC1_PSPD_SHIFT) + +/* + * PFSC (RW) + * + * PFSC + * Port Force Full Speed Connect - Read/Write. Default = 0b. + * When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp + * sequence that allows the port to identify itself as High Speed. + * 0 - Normal operation + * 1 - Forced to full speed + */ +#define USB_PORTSC1_PFSC_MASK (0x1000000UL) +#define USB_PORTSC1_PFSC_SHIFT (24U) +#define USB_PORTSC1_PFSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PFSC_SHIFT) & USB_PORTSC1_PFSC_MASK) +#define USB_PORTSC1_PFSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PFSC_MASK) >> USB_PORTSC1_PFSC_SHIFT) + +/* + * PHCD (RW) + * + * PHCD + * PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. + * When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY + * clock. + * NOTE: The PHY clock cannot be disabled if it is being used as the system clock. + * In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD + * Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend + * will be cleared automatically when the host initials resume. Before forcing a resume from the device, the + * device controller driver must clear this bit. + * In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put + * into suspend mode or when no downstream device is connected. Low power suspend is completely + * under the control of software. + * 0 - Enable PHY clock + * 1 - Disable PHY clock + */ +#define USB_PORTSC1_PHCD_MASK (0x800000UL) +#define USB_PORTSC1_PHCD_SHIFT (23U) +#define USB_PORTSC1_PHCD_SET(x) (((uint32_t)(x) << USB_PORTSC1_PHCD_SHIFT) & USB_PORTSC1_PHCD_MASK) +#define USB_PORTSC1_PHCD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PHCD_MASK) >> USB_PORTSC1_PHCD_SHIFT) + +/* + * WKOC (RW) + * + * WKOC + * Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. + * Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. + * This field is zero if Port Power(PORTSC1) is zero. + */ +#define USB_PORTSC1_WKOC_MASK (0x400000UL) +#define USB_PORTSC1_WKOC_SHIFT (22U) +#define USB_PORTSC1_WKOC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKOC_SHIFT) & USB_PORTSC1_WKOC_MASK) +#define USB_PORTSC1_WKOC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKOC_MASK) >> USB_PORTSC1_WKOC_SHIFT) + +/* + * WKDC (RW) + * + * WKDC + * Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables + * the port to be sensitive to device disconnects as wake-up events. + * This field is zero if Port Power(PORTSC1) is zero or in device mode. + */ +#define USB_PORTSC1_WKDC_MASK (0x200000UL) +#define USB_PORTSC1_WKDC_SHIFT (21U) +#define USB_PORTSC1_WKDC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKDC_SHIFT) & USB_PORTSC1_WKDC_MASK) +#define USB_PORTSC1_WKDC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKDC_MASK) >> USB_PORTSC1_WKDC_SHIFT) + +/* + * WKCN (RW) + * + * WKCN + * Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. + * Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. + * This field is zero if Port Power(PORTSC1) is zero or in device mode. + */ +#define USB_PORTSC1_WKCN_MASK (0x100000UL) +#define USB_PORTSC1_WKCN_SHIFT (20U) +#define USB_PORTSC1_WKCN_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKCN_SHIFT) & USB_PORTSC1_WKCN_MASK) +#define USB_PORTSC1_WKCN_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKCN_MASK) >> USB_PORTSC1_WKCN_SHIFT) + +/* + * PTC (RW) + * + * PTC + * Port Test Control - Read/Write. Default = 0000b. + * Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. + * The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. + * Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. + * Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. + * NOTE: Low speed operations are not supported as a peripheral device. + * Any other value than zero indicates that the port is operating in test mode. + * Value Specific Test + * 0000 - TEST_MODE_DISABLE + * 0001 - J_STATE + * 0010 - K_STATE + * 0011 - SE0 (host) / NAK (device) + * 0100 - Packet + * 0101 - FORCE_ENABLE_HS + * 0110 - FORCE_ENABLE_FS + * 0111 - FORCE_ENABLE_LS + * 1000-1111 - Reserved + */ +#define USB_PORTSC1_PTC_MASK (0xF0000UL) +#define USB_PORTSC1_PTC_SHIFT (16U) +#define USB_PORTSC1_PTC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTC_SHIFT) & USB_PORTSC1_PTC_MASK) +#define USB_PORTSC1_PTC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTC_MASK) >> USB_PORTSC1_PTC_SHIFT) + +/* + * PP (RW) + * + * PP + * Port Power (PP)-Read/Write or Read Only. + * The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: + * PPC + * PP Operation + * 0 + * 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. + * 1 + * 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). + * When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. + * When an over-current condition is detected on a powered port and PPC is a one, + * the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). + * This feature is implemented in all controller cores (PPC = 1). + */ +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +#define USB_PORTSC1_PP_SET(x) (((uint32_t)(x) << USB_PORTSC1_PP_SHIFT) & USB_PORTSC1_PP_MASK) +#define USB_PORTSC1_PP_GET(x) (((uint32_t)(x) & USB_PORTSC1_PP_MASK) >> USB_PORTSC1_PP_SHIFT) + +/* + * LS (RO) + * + * LS + * Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal + * lines. + * In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because + * the port controller state machine and the port routing manage the connection of LS and FS. + * In device mode, the use of linestate by the device controller driver is not necessary. + * The encoding of the bits are: + * Bits [11:10] Meaning + * 00 - SE0 + * 01 - K-state + * 10 - J-state + * 11 - Undefined + */ +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +#define USB_PORTSC1_LS_GET(x) (((uint32_t)(x) & USB_PORTSC1_LS_MASK) >> USB_PORTSC1_LS_SHIFT) + +/* + * HSP (RO) + * + * HSP + * High-Speed Port - Read Only. Default = 0b. + * When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the + * host/device connected to the port is not in a high-speed mode. + * NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + */ +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +#define USB_PORTSC1_HSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_HSP_MASK) >> USB_PORTSC1_HSP_SHIFT) + +/* + * PR (RW) + * + * PR + * Port Reset - Read/Write or Read Only. Default = 0b. + * In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. + * When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. + * This bit will automatically change to zero after the reset sequence is complete. + * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. + * In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + */ +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +#define USB_PORTSC1_PR_SET(x) (((uint32_t)(x) << USB_PORTSC1_PR_SHIFT) & USB_PORTSC1_PR_MASK) +#define USB_PORTSC1_PR_GET(x) (((uint32_t)(x) & USB_PORTSC1_PR_MASK) >> USB_PORTSC1_PR_SHIFT) + +/* + * SUSP (RW) + * + * SUSP + * Suspend - Read/Write or Read Only. Default = 0b. + * 1=Port in suspend state. 0=Port not in suspend state. + * In Host Mode: Read/Write. + * Port Enabled Bit and Suspend bit of this register define the port states as follows: + * Bits [Port Enabled, Suspend] Port State + * 0x Disable + * 10 Enable + * 11 Suspend + * When in suspend state, downstream propagation of data is blocked on this port, except for port reset. + * The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. + * In the suspend state, the port is sensitive to resume detection. + * Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. + * The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. + * If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * In Device Mode: Read Only. + * In device mode this bit is a read only status bit. + */ +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +#define USB_PORTSC1_SUSP_SET(x) (((uint32_t)(x) << USB_PORTSC1_SUSP_SHIFT) & USB_PORTSC1_SUSP_MASK) +#define USB_PORTSC1_SUSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_SUSP_MASK) >> USB_PORTSC1_SUSP_SHIFT) + +/* + * FPR (RW) + * + * FPR + * Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. + * In Host Mode: + * Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. + * When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. + * This bit will automatically change to zero after the resume sequence is complete. + * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. + * Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. + * The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. + * Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * This bit is not-EHCI compatible. + * In Device mode: + * After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. + * The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. + * The bit will be cleared when the device returns to normal operation. + * Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. + */ +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +#define USB_PORTSC1_FPR_SET(x) (((uint32_t)(x) << USB_PORTSC1_FPR_SHIFT) & USB_PORTSC1_FPR_MASK) +#define USB_PORTSC1_FPR_GET(x) (((uint32_t)(x) & USB_PORTSC1_FPR_MASK) >> USB_PORTSC1_FPR_SHIFT) + +/* + * OCC (RW) + * + * OCC + * Over-current Change-R/WC. Default=0. + * This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. + */ +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +#define USB_PORTSC1_OCC_SET(x) (((uint32_t)(x) << USB_PORTSC1_OCC_SHIFT) & USB_PORTSC1_OCC_MASK) +#define USB_PORTSC1_OCC_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCC_MASK) >> USB_PORTSC1_OCC_SHIFT) + +/* + * OCA (RO) + * + * OCA + * Over-current Active-Read Only. Default 0. + * This bit will automatically transition from one to zero when the over current condition is removed. + * 0 - This port does not have an over-current condition. + * 1 - This port currently has an over-current condition + */ +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +#define USB_PORTSC1_OCA_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCA_MASK) >> USB_PORTSC1_OCA_SHIFT) + +/* + * PEC (RWC) + * + * PEC + * Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. + * In Host Mode: + * For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or + * due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). + * Software clears this by writing a one to it. + * This field is zero if Port Power(PORTSC1) is zero. + * In Device mode: + * The device port is always enabled, so this bit is always '0b'. + */ +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +#define USB_PORTSC1_PEC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PEC_SHIFT) & USB_PORTSC1_PEC_MASK) +#define USB_PORTSC1_PEC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PEC_MASK) >> USB_PORTSC1_PEC_SHIFT) + +/* + * PE (RWC) + * + * PE + * Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. + * In Host Mode: + * Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. + * Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. + * Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. + * When the port is disabled, (0b) downstream propagation of data is blocked except for reset. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * In Device Mode: + * The device port is always enabled, so this bit is always '1b'. + */ +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +#define USB_PORTSC1_PE_SET(x) (((uint32_t)(x) << USB_PORTSC1_PE_SHIFT) & USB_PORTSC1_PE_MASK) +#define USB_PORTSC1_PE_GET(x) (((uint32_t)(x) & USB_PORTSC1_PE_MASK) >> USB_PORTSC1_PE_SHIFT) + +/* + * CSC (RWC) + * + * CSC + * Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. + * In Host Mode: + * Indicates a change has occurred in the port's Current Connect Status. + * The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. + * For example, the insertion status changes twice before system software has cleared the changed condition, + * hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * In Device Mode: + * This bit is undefined in device controller mode. + */ +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +#define USB_PORTSC1_CSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_CSC_SHIFT) & USB_PORTSC1_CSC_MASK) +#define USB_PORTSC1_CSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_CSC_MASK) >> USB_PORTSC1_CSC_SHIFT) + +/* + * CCS (RWC) + * + * CCS + * Current Connect Status-Read Only. + * In Host Mode: + * 1=Device is present on port. 0=No device is present. Default = 0. + * This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * In Device Mode: + * 1=Attached. 0=Not Attached. Default=0. + * A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. + * A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. + * It does not state the device being disconnected or Suspended. + */ +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +#define USB_PORTSC1_CCS_SET(x) (((uint32_t)(x) << USB_PORTSC1_CCS_SHIFT) & USB_PORTSC1_CCS_MASK) +#define USB_PORTSC1_CCS_GET(x) (((uint32_t)(x) & USB_PORTSC1_CCS_MASK) >> USB_PORTSC1_CCS_SHIFT) + +/* Bitfield definition for register: OTGSC */ +/* + * ASVIE (RW) + * + * ASVIE + * A Session Valid Interrupt Enable - Read/Write. + */ +#define USB_OTGSC_ASVIE_MASK (0x4000000UL) +#define USB_OTGSC_ASVIE_SHIFT (26U) +#define USB_OTGSC_ASVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIE_SHIFT) & USB_OTGSC_ASVIE_MASK) +#define USB_OTGSC_ASVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIE_MASK) >> USB_OTGSC_ASVIE_SHIFT) + +/* + * AVVIE (RW) + * + * AVVIE + * A VBus Valid Interrupt Enable - Read/Write. + * Setting this bit enables the A VBus valid interrupt. + */ +#define USB_OTGSC_AVVIE_MASK (0x2000000UL) +#define USB_OTGSC_AVVIE_SHIFT (25U) +#define USB_OTGSC_AVVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIE_SHIFT) & USB_OTGSC_AVVIE_MASK) +#define USB_OTGSC_AVVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIE_MASK) >> USB_OTGSC_AVVIE_SHIFT) + +/* + * IDIE (RW) + * + * IDIE + * USB ID Interrupt Enable - Read/Write. + * Setting this bit enables the USB ID interrupt. + */ +#define USB_OTGSC_IDIE_MASK (0x1000000UL) +#define USB_OTGSC_IDIE_SHIFT (24U) +#define USB_OTGSC_IDIE_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIE_SHIFT) & USB_OTGSC_IDIE_MASK) +#define USB_OTGSC_IDIE_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIE_MASK) >> USB_OTGSC_IDIE_SHIFT) + +/* + * ASVIS (RWC) + * + * ASVIS + * A Session Valid Interrupt Status - Read/Write to Clear. + * This bit is set when VBus has either risen above or fallen below the A session valid threshold. + * Software must write a one to clear this bit. + */ +#define USB_OTGSC_ASVIS_MASK (0x40000UL) +#define USB_OTGSC_ASVIS_SHIFT (18U) +#define USB_OTGSC_ASVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIS_SHIFT) & USB_OTGSC_ASVIS_MASK) +#define USB_OTGSC_ASVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIS_MASK) >> USB_OTGSC_ASVIS_SHIFT) + +/* + * AVVIS (RWC) + * + * AVVIS + * A VBus Valid Interrupt Status - Read/Write to Clear. + * This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. + * Software must write a one to clear this bit. + */ +#define USB_OTGSC_AVVIS_MASK (0x20000UL) +#define USB_OTGSC_AVVIS_SHIFT (17U) +#define USB_OTGSC_AVVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIS_SHIFT) & USB_OTGSC_AVVIS_MASK) +#define USB_OTGSC_AVVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIS_MASK) >> USB_OTGSC_AVVIS_SHIFT) + +/* + * IDIS (RWC) + * + * IDIS + * USB ID Interrupt Status - Read/Write. + * This bit is set when a change on the ID input has been detected. + * Software must write a one to clear this bit. + */ +#define USB_OTGSC_IDIS_MASK (0x10000UL) +#define USB_OTGSC_IDIS_SHIFT (16U) +#define USB_OTGSC_IDIS_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIS_SHIFT) & USB_OTGSC_IDIS_MASK) +#define USB_OTGSC_IDIS_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIS_MASK) >> USB_OTGSC_IDIS_SHIFT) + +/* + * ASV (RO) + * + * ASV + * A Session Valid - Read Only. + * Indicates VBus is above the A session valid threshold. + */ +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +#define USB_OTGSC_ASV_GET(x) (((uint32_t)(x) & USB_OTGSC_ASV_MASK) >> USB_OTGSC_ASV_SHIFT) + +/* + * AVV (RO) + * + * AVV + * A VBus Valid - Read Only. + * Indicates VBus is above the A VBus valid threshold. + */ +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +#define USB_OTGSC_AVV_GET(x) (((uint32_t)(x) & USB_OTGSC_AVV_MASK) >> USB_OTGSC_AVV_SHIFT) + +/* + * ID (RO) + * + * ID + * USB ID - Read Only. + * 0 = A device, 1 = B device + */ +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +#define USB_OTGSC_ID_GET(x) (((uint32_t)(x) & USB_OTGSC_ID_MASK) >> USB_OTGSC_ID_SHIFT) + +/* + * IDPU (RW) + * + * IDPU + * ID Pullup - Read/Write + * This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input + * will not be sampled. + */ +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +#define USB_OTGSC_IDPU_SET(x) (((uint32_t)(x) << USB_OTGSC_IDPU_SHIFT) & USB_OTGSC_IDPU_MASK) +#define USB_OTGSC_IDPU_GET(x) (((uint32_t)(x) & USB_OTGSC_IDPU_MASK) >> USB_OTGSC_IDPU_SHIFT) + +/* + * VC (RW) + * + * VC + * VBUS Charge - Read/Write. + * Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + */ +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +#define USB_OTGSC_VC_SET(x) (((uint32_t)(x) << USB_OTGSC_VC_SHIFT) & USB_OTGSC_VC_MASK) +#define USB_OTGSC_VC_GET(x) (((uint32_t)(x) & USB_OTGSC_VC_MASK) >> USB_OTGSC_VC_SHIFT) + +/* + * VD (RW) + * + * VD + * VBUS_Discharge - Read/Write. + * Setting this bit causes VBus to discharge through a resistor. + */ +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +#define USB_OTGSC_VD_SET(x) (((uint32_t)(x) << USB_OTGSC_VD_SHIFT) & USB_OTGSC_VD_MASK) +#define USB_OTGSC_VD_GET(x) (((uint32_t)(x) & USB_OTGSC_VD_MASK) >> USB_OTGSC_VD_SHIFT) + +/* Bitfield definition for register: USBMODE */ +/* + * SDIS (RW) + * + * SDIS + * Stream Disable Mode. (0 - Inactive [default]; 1 - Active) + * Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. + * This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. + * Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. + * Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems + * where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. + * NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for + * the scheduler when using this feature. + * NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + */ +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +#define USB_USBMODE_SDIS_SET(x) (((uint32_t)(x) << USB_USBMODE_SDIS_SHIFT) & USB_USBMODE_SDIS_MASK) +#define USB_USBMODE_SDIS_GET(x) (((uint32_t)(x) & USB_USBMODE_SDIS_MASK) >> USB_USBMODE_SDIS_SHIFT) + +/* + * SLOM (RW) + * + * SLOM + * Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . + * 0 - Setup Lockouts On (default); + * 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + */ +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +#define USB_USBMODE_SLOM_SET(x) (((uint32_t)(x) << USB_USBMODE_SLOM_SHIFT) & USB_USBMODE_SLOM_MASK) +#define USB_USBMODE_SLOM_GET(x) (((uint32_t)(x) & USB_USBMODE_SLOM_MASK) >> USB_USBMODE_SLOM_SHIFT) + +/* + * ES (RW) + * + * ES + * Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the + * host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected + * by the value of this bit because they are based upon the 32-bit word. + * Bit Meaning + * 0 - Little Endian [Default] + * 1 - Big Endian + */ +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +#define USB_USBMODE_ES_SET(x) (((uint32_t)(x) << USB_USBMODE_ES_SHIFT) & USB_USBMODE_ES_MASK) +#define USB_USBMODE_ES_GET(x) (((uint32_t)(x) & USB_USBMODE_ES_MASK) >> USB_USBMODE_ES_SHIFT) + +/* + * CM (RW) + * + * CM + * Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only + * implementations. For those designs that contain both host & device capability, the controller defaults to + * an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ + * device controllers, this register can only be written once after reset. If it is necessary to switch modes, + * software must reset the controller by writing to the RESET bit in the USBCMD register before + * reprogramming this register. + * For OTG controller core, reset value is '00b'. + * 00 - Idle [Default for combination host/device] + * 01 - Reserved + * 10 - Device Controller [Default for device only controller] + * 11 - Host Controller [Default for host only controller] + */ +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +#define USB_USBMODE_CM_SET(x) (((uint32_t)(x) << USB_USBMODE_CM_SHIFT) & USB_USBMODE_CM_MASK) +#define USB_USBMODE_CM_GET(x) (((uint32_t)(x) & USB_USBMODE_CM_MASK) >> USB_USBMODE_CM_SHIFT) + +/* Bitfield definition for register: ENDPTSETUPSTAT */ +/* + * ENDPTSETUPSTAT (RWC) + * + * ENDPTSETUPSTAT + * Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. + * Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. + * The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. + * This register is only used in device mode. + */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SET(x) (((uint32_t)(x) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_GET(x) (((uint32_t)(x) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) >> USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) + +/* Bitfield definition for register: ENDPTPRIME */ +/* + * PETB (RWS) + * + * PETB + * Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a + * buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. + * Software should write a one to the corresponding bit when posting a new transfer descriptor to an + * endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor + * from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated + * endpoint(s) is (are) successfully primed. + * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD + * is retired, and the dQH is updated. + * PETB[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTPRIME_PETB_MASK (0xFFFF0000UL) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +#define USB_ENDPTPRIME_PETB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PETB_SHIFT) & USB_ENDPTPRIME_PETB_MASK) +#define USB_ENDPTPRIME_PETB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PETB_MASK) >> USB_ENDPTPRIME_PETB_SHIFT) + +/* + * PERB (RWS) + * + * PERB + * Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. + * Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. + * Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. + * Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. + * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD + * is retired, and the dQH is updated. + * PERB[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTPRIME_PERB_MASK (0xFFFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +#define USB_ENDPTPRIME_PERB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PERB_SHIFT) & USB_ENDPTPRIME_PERB_MASK) +#define USB_ENDPTPRIME_PERB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PERB_MASK) >> USB_ENDPTPRIME_PERB_SHIFT) + +/* Bitfield definition for register: ENDPTFLUSH */ +/* + * FETB (RWS) + * + * FETB + * Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. + * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. + * Hardware clears this register after the endpoint flush operation is successful. + * FETB[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTFLUSH_FETB_MASK (0xFFFF0000UL) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +#define USB_ENDPTFLUSH_FETB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FETB_SHIFT) & USB_ENDPTFLUSH_FETB_MASK) +#define USB_ENDPTFLUSH_FETB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FETB_MASK) >> USB_ENDPTFLUSH_FETB_SHIFT) + +/* + * FERB (RWS) + * + * FERB + * Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. + * Hardware clears this register after the endpoint flush operation is successful. + * FERB[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTFLUSH_FERB_MASK (0xFFFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +#define USB_ENDPTFLUSH_FERB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FERB_SHIFT) & USB_ENDPTFLUSH_FERB_MASK) +#define USB_ENDPTFLUSH_FERB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FERB_MASK) >> USB_ENDPTFLUSH_FERB_SHIFT) + +/* Bitfield definition for register: ENDPTSTAT */ +/* + * ETBR (RO) + * + * ETBR + * Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. + * This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. + * There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. + * This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. + * Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. + * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. + * ETBR[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTSTAT_ETBR_MASK (0xFFFF0000UL) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +#define USB_ENDPTSTAT_ETBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ETBR_MASK) >> USB_ENDPTSTAT_ETBR_SHIFT) + +/* + * ERBR (RO) + * + * ERBR + * Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective + * endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a + * corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the + * ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB + * traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the + * USB DMA system, or through the ENDPTFLUSH register. + * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations + * when a dTD is retired, and the dQH is updated. + * ERBR[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTSTAT_ERBR_MASK (0xFFFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +#define USB_ENDPTSTAT_ERBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ERBR_MASK) >> USB_ENDPTSTAT_ERBR_SHIFT) + +/* Bitfield definition for register: ENDPTCOMPLETE */ +/* + * ETCE (RWC) + * + * ETCE + * Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. + * If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. + * ETCE[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFFFF0000UL) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +#define USB_ENDPTCOMPLETE_ETCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ETCE_SHIFT) & USB_ENDPTCOMPLETE_ETCE_MASK) +#define USB_ENDPTCOMPLETE_ETCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ETCE_MASK) >> USB_ENDPTCOMPLETE_ETCE_SHIFT) + +/* + * ERCE (RWC) + * + * ERCE + * Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred + * and software should read the corresponding endpoint queue to determine the transfer status. If the + * corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the + * USBINT . Writing one clears the corresponding bit in this register. + * ERCE[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +#define USB_ENDPTCOMPLETE_ERCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ERCE_SHIFT) & USB_ENDPTCOMPLETE_ERCE_MASK) +#define USB_ENDPTCOMPLETE_ERCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ERCE_MASK) >> USB_ENDPTCOMPLETE_ERCE_SHIFT) + +/* Bitfield definition for register array: ENDPTCTRL */ +/* + * TXE (RW) + * + * TXE + * TX Endpoint Enable + * 0 Disabled [Default] + * 1 Enabled + * An Endpoint should be enabled only after it has been configured. + */ +#define USB_ENDPTCTRL_TXE_MASK (0x800000UL) +#define USB_ENDPTCTRL_TXE_SHIFT (23U) +#define USB_ENDPTCTRL_TXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXE_SHIFT) & USB_ENDPTCTRL_TXE_MASK) +#define USB_ENDPTCTRL_TXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXE_MASK) >> USB_ENDPTCTRL_TXE_SHIFT) + +/* + * TXR (WS) + * + * TXR + * TX Data Toggle Reset (WS) + * Write 1 - Reset PID Sequence + * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order + * to synchronize the data PID's between the Host and device. + */ +#define USB_ENDPTCTRL_TXR_MASK (0x400000UL) +#define USB_ENDPTCTRL_TXR_SHIFT (22U) +#define USB_ENDPTCTRL_TXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXR_SHIFT) & USB_ENDPTCTRL_TXR_MASK) +#define USB_ENDPTCTRL_TXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXR_MASK) >> USB_ENDPTCTRL_TXR_SHIFT) + +/* + * TXT (RW) + * + * TXT + * TX Endpoint Type - Read/Write + * 00 Control + * 01 Isochronous + * 10 Bulk + * 11 Interrupt + */ +#define USB_ENDPTCTRL_TXT_MASK (0xC0000UL) +#define USB_ENDPTCTRL_TXT_SHIFT (18U) +#define USB_ENDPTCTRL_TXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXT_SHIFT) & USB_ENDPTCTRL_TXT_MASK) +#define USB_ENDPTCTRL_TXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXT_MASK) >> USB_ENDPTCTRL_TXT_SHIFT) + +/* + * TXS (RW) + * + * TXS + * TX Endpoint Stall - Read/Write + * 0 End Point OK + * 1 End Point Stalled + * This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured + * as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. + * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. + * This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. + * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. + * In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: + * continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + */ +#define USB_ENDPTCTRL_TXS_MASK (0x10000UL) +#define USB_ENDPTCTRL_TXS_SHIFT (16U) +#define USB_ENDPTCTRL_TXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXS_SHIFT) & USB_ENDPTCTRL_TXS_MASK) +#define USB_ENDPTCTRL_TXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXS_MASK) >> USB_ENDPTCTRL_TXS_SHIFT) + +/* + * RXE (RW) + * + * RXE + * RX Endpoint Enable + * 0 Disabled [Default] + * 1 Enabled + * An Endpoint should be enabled only after it has been configured. + */ +#define USB_ENDPTCTRL_RXE_MASK (0x80U) +#define USB_ENDPTCTRL_RXE_SHIFT (7U) +#define USB_ENDPTCTRL_RXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXE_SHIFT) & USB_ENDPTCTRL_RXE_MASK) +#define USB_ENDPTCTRL_RXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXE_MASK) >> USB_ENDPTCTRL_RXE_SHIFT) + +/* + * RXR (WS) + * + * RXR + * RX Data Toggle Reset (WS) + * Write 1 - Reset PID Sequence + * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order + * to synchronize the data PID's between the host and device. + */ +#define USB_ENDPTCTRL_RXR_MASK (0x40U) +#define USB_ENDPTCTRL_RXR_SHIFT (6U) +#define USB_ENDPTCTRL_RXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXR_SHIFT) & USB_ENDPTCTRL_RXR_MASK) +#define USB_ENDPTCTRL_RXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXR_MASK) >> USB_ENDPTCTRL_RXR_SHIFT) + +/* + * RXT (RW) + * + * RXT + * RX Endpoint Type - Read/Write + * 00 Control + * 01 Isochronous + * 10 Bulk + * 11 Interrupt + */ +#define USB_ENDPTCTRL_RXT_MASK (0xCU) +#define USB_ENDPTCTRL_RXT_SHIFT (2U) +#define USB_ENDPTCTRL_RXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXT_SHIFT) & USB_ENDPTCTRL_RXT_MASK) +#define USB_ENDPTCTRL_RXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXT_MASK) >> USB_ENDPTCTRL_RXT_SHIFT) + +/* + * RXS (RW) + * + * RXS + * RX Endpoint Stall - Read/Write + * 0 End Point OK. [Default] + * 1 End Point Stalled + * This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control + * Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit + * is cleared. + * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This + * control will continue to STALL until this bit is either cleared by software or automatically cleared as above + * for control endpoints. + * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the + * ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it + * is unlikely the DCD software will observe this delay. However, should the DCD observe that the + * stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit + * until it is set or until a new setup has been received by checking the associated endptsetupstat + * Bit. + */ +#define USB_ENDPTCTRL_RXS_MASK (0x1U) +#define USB_ENDPTCTRL_RXS_SHIFT (0U) +#define USB_ENDPTCTRL_RXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXS_SHIFT) & USB_ENDPTCTRL_RXS_MASK) +#define USB_ENDPTCTRL_RXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXS_MASK) >> USB_ENDPTCTRL_RXS_SHIFT) + +/* Bitfield definition for register: OTG_CTRL0 */ +/* + * OTG_WKDPDMCHG_EN (RW) + * + */ +#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK (0x2000000UL) +#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT (25U) +#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) +#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) >> USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) + +/* + * AUTORESUME_EN (RW) + * + */ +#define USB_OTG_CTRL0_AUTORESUME_EN_MASK (0x80000UL) +#define USB_OTG_CTRL0_AUTORESUME_EN_SHIFT (19U) +#define USB_OTG_CTRL0_AUTORESUME_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) +#define USB_OTG_CTRL0_AUTORESUME_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) >> USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) + +/* + * OTG_VBUS_WAKEUP_EN (RW) + * + */ +#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK (0x20000UL) +#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT (17U) +#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) +#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) + +/* + * OTG_ID_WAKEUP_EN (RW) + * + */ +#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK (0x10000UL) +#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT (16U) +#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) +#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) + +/* + * OTG_VBUS_SOURCE_SEL (RW) + * + */ +#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK (0x2000U) +#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT (13U) +#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) +#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) >> USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) + +/* + * OTG_UTMI_SUSPENDM_SW (RW) + * + * default 0 for naneng usbphy + */ +#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK (0x1000U) +#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT (12U) +#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) +#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) + +/* + * OTG_UTMI_RESET_SW (RW) + * + * default 1 for naneng usbphy + */ +#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK (0x800U) +#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT (11U) +#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) +#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) + +/* + * OTG_WAKEUP_INT_ENABLE (RW) + * + */ +#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK (0x400U) +#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT (10U) +#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) +#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) >> USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) + +/* + * OTG_POWER_MASK (RW) + * + */ +#define USB_OTG_CTRL0_OTG_POWER_MASK_MASK (0x200U) +#define USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT (9U) +#define USB_OTG_CTRL0_OTG_POWER_MASK_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) +#define USB_OTG_CTRL0_OTG_POWER_MASK_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) >> USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) + +/* + * OTG_OVER_CUR_POL (RW) + * + */ +#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK (0x100U) +#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT (8U) +#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) +#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) + +/* + * OTG_OVER_CUR_DIS (RW) + * + */ +#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK (0x80U) +#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT (7U) +#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) +#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) + +/* + * SER_MODE_SUSPEND_EN (RW) + * + * for naneng usbphy, only switch to serial mode when suspend + */ +#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK (0x10U) +#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT (4U) +#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) +#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) >> USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) + +/* Bitfield definition for register: PHY_CTRL0 */ +/* + * GPIO_ID_SEL_N (RW) + * + */ +#define USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK (0x2000000UL) +#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT (25U) +#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) +#define USB_PHY_CTRL0_GPIO_ID_SEL_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) >> USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) + +/* + * ID_DIG_OVERRIDE (RW) + * + */ +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK (0x4000U) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT (14U) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) + +/* + * SESS_VALID_OVERRIDE (RW) + * + */ +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK (0x2000U) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT (13U) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) + +/* + * VBUS_VALID_OVERRIDE (RW) + * + */ +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK (0x1000U) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT (12U) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) + +/* + * ID_DIG_OVERRIDE_EN (RW) + * + */ +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK (0x4U) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT (2U) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) + +/* + * SESS_VALID_OVERRIDE_EN (RW) + * + */ +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK (0x2U) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT (1U) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) + +/* + * VBUS_VALID_OVERRIDE_EN (RW) + * + */ +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK (0x1U) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT (0U) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) + +/* Bitfield definition for register: PHY_CTRL1 */ +/* + * UTMI_CFG_RST_N (RW) + * + */ +#define USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK (0x100000UL) +#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT (20U) +#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) +#define USB_PHY_CTRL1_UTMI_CFG_RST_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) >> USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) + +/* + * UTMI_OTG_SUSPENDM (RW) + * + * OTG suspend, not utmi_suspendm + */ +#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK (0x2U) +#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT (1U) +#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) +#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) >> USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) + +/* Bitfield definition for register: TOP_STATUS */ +/* + * WAKEUP_INT_STATUS (RW) + * + */ +#define USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK (0x80000000UL) +#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT (31U) +#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SET(x) (((uint32_t)(x) << USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) +#define USB_TOP_STATUS_WAKEUP_INT_STATUS_GET(x) (((uint32_t)(x) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) >> USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) + +/* Bitfield definition for register: PHY_STATUS */ +/* + * UTMI_CLK_VALID (RW) + * + */ +#define USB_PHY_STATUS_UTMI_CLK_VALID_MASK (0x80000000UL) +#define USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT (31U) +#define USB_PHY_STATUS_UTMI_CLK_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) +#define USB_PHY_STATUS_UTMI_CLK_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) >> USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) + +/* + * LINE_STATE (RW) + * + */ +#define USB_PHY_STATUS_LINE_STATE_MASK (0xC0U) +#define USB_PHY_STATUS_LINE_STATE_SHIFT (6U) +#define USB_PHY_STATUS_LINE_STATE_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_LINE_STATE_SHIFT) & USB_PHY_STATUS_LINE_STATE_MASK) +#define USB_PHY_STATUS_LINE_STATE_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_LINE_STATE_MASK) >> USB_PHY_STATUS_LINE_STATE_SHIFT) + +/* + * HOST_DISCONNECT (RW) + * + */ +#define USB_PHY_STATUS_HOST_DISCONNECT_MASK (0x20U) +#define USB_PHY_STATUS_HOST_DISCONNECT_SHIFT (5U) +#define USB_PHY_STATUS_HOST_DISCONNECT_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) +#define USB_PHY_STATUS_HOST_DISCONNECT_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) >> USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) + +/* + * ID_DIG (RW) + * + */ +#define USB_PHY_STATUS_ID_DIG_MASK (0x10U) +#define USB_PHY_STATUS_ID_DIG_SHIFT (4U) +#define USB_PHY_STATUS_ID_DIG_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_ID_DIG_SHIFT) & USB_PHY_STATUS_ID_DIG_MASK) +#define USB_PHY_STATUS_ID_DIG_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_ID_DIG_MASK) >> USB_PHY_STATUS_ID_DIG_SHIFT) + +/* + * UTMI_SESS_VALID (RW) + * + */ +#define USB_PHY_STATUS_UTMI_SESS_VALID_MASK (0x4U) +#define USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT (2U) +#define USB_PHY_STATUS_UTMI_SESS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) +#define USB_PHY_STATUS_UTMI_SESS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) >> USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) + +/* + * VBUS_VALID (RW) + * + */ +#define USB_PHY_STATUS_VBUS_VALID_MASK (0x1U) +#define USB_PHY_STATUS_VBUS_VALID_SHIFT (0U) +#define USB_PHY_STATUS_VBUS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_VBUS_VALID_SHIFT) & USB_PHY_STATUS_VBUS_VALID_MASK) +#define USB_PHY_STATUS_VBUS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_VBUS_VALID_MASK) >> USB_PHY_STATUS_VBUS_VALID_SHIFT) + + + +/* ENDPTCTRL register group index macro definition */ +#define USB_ENDPTCTRL_ENDPTCTRL0 (0UL) +#define USB_ENDPTCTRL_ENDPTCTRL1 (1UL) +#define USB_ENDPTCTRL_ENDPTCTRL2 (2UL) +#define USB_ENDPTCTRL_ENDPTCTRL3 (3UL) +#define USB_ENDPTCTRL_ENDPTCTRL4 (4UL) +#define USB_ENDPTCTRL_ENDPTCTRL5 (5UL) +#define USB_ENDPTCTRL_ENDPTCTRL6 (6UL) +#define USB_ENDPTCTRL_ENDPTCTRL7 (7UL) + + +#endif /* HPM_USB_H */ diff --git a/rt-thread/components/drivers/usb/cherryusb/port/chipidea/usb_dc_chipidea.c b/rt-thread/components/drivers/usb/cherryusb/port/chipidea/usb_dc_chipidea.c new file mode 100644 index 0000000..c6b6c0f --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/chipidea/usb_dc_chipidea.c @@ -0,0 +1,718 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_chipidea_reg.h" + +#define USB_OTG_DEV ((CHIPIDEA_TypeDef *)g_usbdev_bus[busid].reg_base) + +#define CHIPIDEA_BITSMASK(val, offset) ((uint32_t)(val) << (offset)) +#define QTD_COUNT_EACH_ENDPOINT (8U) + +/* ENDPTCTRL */ +enum { + ENDPTCTRL_STALL = CHIPIDEA_BITSMASK(1, 0), + ENDPTCTRL_TYPE = CHIPIDEA_BITSMASK(3, 2), + ENDPTCTRL_TOGGLE_INHIBIT = CHIPIDEA_BITSMASK(1, 5), + ENDPTCTRL_TOGGLE_RESET = CHIPIDEA_BITSMASK(1, 6), + ENDPTCTRL_ENABLE = CHIPIDEA_BITSMASK(1, 7), +}; + +/* USBSTS, USBINTR */ +enum { + intr_usb = CHIPIDEA_BITSMASK(1, 0), + intr_error = CHIPIDEA_BITSMASK(1, 1), + intr_port_change = CHIPIDEA_BITSMASK(1, 2), + intr_reset = CHIPIDEA_BITSMASK(1, 6), + intr_sof = CHIPIDEA_BITSMASK(1, 7), + intr_suspend = CHIPIDEA_BITSMASK(1, 8), + intr_nak = CHIPIDEA_BITSMASK(1, 16) +}; + +/* Queue Transfer Descriptor */ +typedef struct { + /* Word 0: Next QTD Pointer */ + volatile uint32_t next; /* Next link pointer This field contains the physical memory address of the next dTD to be processed */ + + /* Word 1: qTQ Token */ + volatile uint32_t : 3; + volatile uint32_t xact_err : 1; + volatile uint32_t : 1; + volatile uint32_t buffer_err : 1; + volatile uint32_t halted : 1; + volatile uint32_t active : 1; + volatile uint32_t : 2; + volatile uint32_t iso_mult_override : 2; /* This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO. */ + volatile uint32_t : 3; + volatile uint32_t int_on_complete : 1; + volatile uint32_t total_bytes : 15; + volatile uint32_t : 0; + + /* Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page */ + volatile uint32_t buffer[5]; + + /*------------- DCD Area -------------*/ + volatile uint16_t expected_bytes; + volatile uint8_t reserved[2]; +} dcd_qtd_t; + +/* Queue Head */ +typedef struct { + /* Word 0: Capabilities and Characteristics */ + + volatile uint32_t : 15; /* Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed. */ + volatile uint32_t int_on_setup : 1; /* Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received. */ + volatile uint32_t max_packet_size : 11; /* This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize) */ + volatile uint32_t : 2; + volatile uint32_t zero_length_termination : 1; /* This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length. */ + volatile uint32_t iso_mult : 2; + volatile uint32_t : 0; + + /* Word 1: Current qTD Pointer */ + volatile uint32_t qtd_addr; + + /* Word 2-9: Transfer Overlay */ + volatile dcd_qtd_t qtd_overlay; + + /* Word 10-11: Setup request (control OUT only) */ + volatile struct usb_setup_packet setup_request; + + /*-------------------------------------------------------------------- + * Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes + * thus there are 16 bytes padding free that we can make use of. + *-------------------------------------------------------------------- + */ + volatile uint8_t reserved[16]; +} dcd_qhd_t; + +typedef struct { + dcd_qhd_t qhd[CONFIG_USBDEV_EP_NUM * 2]; + dcd_qtd_t qtd[CONFIG_USBDEV_EP_NUM * 2 * QTD_COUNT_EACH_ENDPOINT]; +} dcd_data_t; + +/* Endpoint state */ +struct chipidea_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct chipidea_udc { + dcd_data_t *dcd_data; + bool is_suspend; + struct chipidea_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/ + struct chipidea_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */ +} g_chipidea_udc[CONFIG_USBDEV_MAX_BUS]; + +static USB_NOCACHE_RAM_SECTION __attribute__((aligned(2048))) dcd_data_t _dcd_data0; +#if CONFIG_USBDEV_MAX_BUS == 2 +static USB_NOCACHE_RAM_SECTION __attribute__((aligned(2048))) dcd_data_t _dcd_data1; +#endif + +static dcd_data_t *g_dcd_data[CONFIG_USBDEV_MAX_BUS] = { + &_dcd_data0, +#if CONFIG_USBDEV_MAX_BUS == 2 + &_dcd_data1 +#endif +}; + +/* Index to bit position in register */ +static inline uint8_t ep_idx2bit(uint8_t ep_idx) +{ + return ep_idx / 2 + ((ep_idx % 2) ? 16 : 0); +} + +static void __chipidea_bus_reset(CHIPIDEA_TypeDef *ptr) +{ + /* The reset value for all endpoint types is the control endpoint. If one endpoint + * direction is enabled and the paired endpoint of opposite direction is disabled, then the + * endpoint type of the unused direction must be changed from the control type to any other + * type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior + * for the data PID tracking on the active endpoint. + */ + + for (uint32_t i = 1; i < CONFIG_USBDEV_EP_NUM; i++) { + ptr->ENDPTCTRL[i] = USB_ENDPTCTRL_TXT_SET(USB_ENDPOINT_TYPE_BULK) | USB_ENDPTCTRL_RXT_SET(USB_ENDPOINT_TYPE_BULK); + } + + /* Clear All Registers */ + ptr->ENDPTNAK = ptr->ENDPTNAK; + ptr->ENDPTNAKEN = 0; + ptr->USBSTS = ptr->USBSTS; + ptr->ENDPTSETUPSTAT = ptr->ENDPTSETUPSTAT; + ptr->ENDPTCOMPLETE = ptr->ENDPTCOMPLETE; + + while (ptr->ENDPTPRIME) { + } + ptr->ENDPTFLUSH = 0xFFFFFFFF; + while (ptr->ENDPTFLUSH) { + } +} + +static void chipidea_init(CHIPIDEA_TypeDef *ptr) +{ + /* Reset controller */ + ptr->USBCMD |= USB_USBCMD_RST_MASK; + while (USB_USBCMD_RST_GET(ptr->USBCMD)) { + } + + /* Set mode to device, must be set immediately after reset */ + ptr->USBMODE &= ~USB_USBMODE_CM_MASK; + ptr->USBMODE |= USB_USBMODE_CM_SET(2); + + /* Disable setup lockout, please refer to "Control Endpoint Operation" section in RM. */ + ptr->USBMODE &= ~USB_USBMODE_SLOM_MASK; + + /* Set the endian */ + ptr->USBMODE &= ~USB_USBMODE_ES_MASK; + + /* Set parallel interface signal */ + ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; + + /* Set parallel transceiver width */ + ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; + + /* Set usb forced to full speed mode */ + //ptr->PORTSC1 |= USB_PORTSC1_PFSC_MASK; + + /* Not use interrupt threshold. */ + ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; + + /* Enable VBUS discharge */ + ptr->OTGSC |= USB_OTGSC_VD_MASK; +} + +static void chipidea_deinit(CHIPIDEA_TypeDef *ptr) +{ + /* Stop */ + ptr->USBCMD &= ~USB_USBCMD_RS_MASK; + + /* Reset controller */ + ptr->USBCMD |= USB_USBCMD_RST_MASK; + while (USB_USBCMD_RST_GET(ptr->USBCMD)) { + } + + /* Reset endpoint list address register */ + ptr->ENDPTLISTADDR = 0; + + /* Reset status register */ + ptr->USBSTS = ptr->USBSTS; + + /* Reset interrupt enable register */ + ptr->USBINTR = 0; +} + +/*--------------------------------------------------------------------- + * Endpoint API + *--------------------------------------------------------------------- + */ +static void __chipidea_edpt_open(CHIPIDEA_TypeDef *ptr, uint8_t ep_addr, uint8_t ep_type) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + /* Enable EP Control */ + uint32_t temp = ptr->ENDPTCTRL[epnum]; + temp &= ~((0x03 << 2) << (dir ? 16 : 0)); + temp |= ((ep_type << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0); + ptr->ENDPTCTRL[epnum] = temp; +} + +static void chipidea_edpt_xfer(CHIPIDEA_TypeDef *ptr, uint8_t ep_idx) +{ + uint32_t offset = ep_idx / 2 + ((ep_idx % 2) ? 16 : 0); + + /* Start transfer */ + ptr->ENDPTPRIME = 1 << offset; +} + +static void chipidea_edpt_stall(CHIPIDEA_TypeDef *ptr, uint8_t ep_addr) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + ptr->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0); +} + +static void chipidea_edpt_clear_stall(CHIPIDEA_TypeDef *ptr, uint8_t ep_addr) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + /* data toggle also need to be reset */ + ptr->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << (dir ? 16 : 0); + ptr->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << (dir ? 16 : 0)); +} + +static bool chipidea_edpt_check_stall(CHIPIDEA_TypeDef *ptr, uint8_t ep_addr) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + return (ptr->ENDPTCTRL[epnum] & (ENDPTCTRL_STALL << (dir ? 16 : 0))) ? true : false; +} + +static void chipidea_edpt_close(CHIPIDEA_TypeDef *ptr, uint8_t ep_addr) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + uint32_t primebit = CHIPIDEA_BITSMASK(1, epnum) << (dir ? 16 : 0); + + /* Flush the endpoint to stop a transfer. */ + do { + /* Set the corresponding bit(s) in the ENDPTFLUSH register */ + ptr->ENDPTFLUSH |= primebit; + + /* Wait until all bits in the ENDPTFLUSH register are cleared. */ + while (0U != (ptr->ENDPTFLUSH & primebit)) { + } + /* + * Read the ENDPTSTAT register to ensure that for all endpoints + * commanded to be flushed, that the corresponding bits + * are now cleared. + */ + } while (0U != (ptr->ENDPTSTAT & primebit)); + + /* Disable the endpoint */ + ptr->ENDPTCTRL[epnum] &= ~((ENDPTCTRL_TYPE | ENDPTCTRL_ENABLE | ENDPTCTRL_STALL) << (dir ? 16 : 0)); + ptr->ENDPTCTRL[epnum] |= (USB_ENDPOINT_TYPE_BULK << 2) << (dir ? 16 : 0); +} + +/* Initialize qtd */ +static void usb_qtd_init(dcd_qtd_t *p_qtd, void *data_ptr, uint16_t total_bytes) +{ + memset(p_qtd, 0, sizeof(dcd_qtd_t)); + + p_qtd->next = 1; + p_qtd->active = 1; + p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; + + if (data_ptr != NULL) { + p_qtd->buffer[0] = (uint32_t)data_ptr; + for (uint8_t i = 1; i < 5; i++) { + p_qtd->buffer[i] |= ((p_qtd->buffer[i - 1]) & 0xFFFFF000UL) + 4096U; + } + } +} + +static dcd_qhd_t *chipidea_qhd_get(uint8_t busid, uint8_t ep_idx) +{ + dcd_data_t *dcd_data; + + dcd_data = g_chipidea_udc[busid].dcd_data; + return &dcd_data->qhd[ep_idx]; +} + +static dcd_qtd_t *chipidea_qtd_get(uint8_t busid, uint8_t ep_idx) +{ + dcd_data_t *dcd_data; + + dcd_data = g_chipidea_udc[busid].dcd_data; + return &dcd_data->qtd[ep_idx * QTD_COUNT_EACH_ENDPOINT]; +} + +static void chipidea_bus_reset(uint8_t busid, uint16_t ep0_max_packet_size) +{ + dcd_data_t *dcd_data; + + dcd_data = g_chipidea_udc[busid].dcd_data; + __chipidea_bus_reset(USB_OTG_DEV); + + /* Queue Head & Queue TD */ + memset(dcd_data, 0, sizeof(dcd_data_t)); + + /* Set up Control Endpoints (0 OUT, 1 IN) */ + dcd_data->qhd[0].zero_length_termination = dcd_data->qhd[1].zero_length_termination = 1; + dcd_data->qhd[0].max_packet_size = dcd_data->qhd[1].max_packet_size = ep0_max_packet_size; + dcd_data->qhd[0].qtd_overlay.next = dcd_data->qhd[1].qtd_overlay.next = 1; + + /* OUT only */ + dcd_data->qhd[0].int_on_setup = 1; +} + +static void chipidea_edpt_open(uint8_t busid, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + uint8_t const ep_idx = 2 * epnum + dir; + dcd_data_t *dcd_data; + dcd_qhd_t *p_qhd; + + /* Prepare Queue Head */ + dcd_data = g_chipidea_udc[busid].dcd_data; + p_qhd = &dcd_data->qhd[ep_idx]; + memset(p_qhd, 0, sizeof(dcd_qhd_t)); + + p_qhd->zero_length_termination = 1; + p_qhd->max_packet_size = ep_mps & 0x7FFu; + p_qhd->qtd_overlay.next = 1; + if (ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + p_qhd->iso_mult = ((ep_mps >> 11u) & 0x3u) + 1u; + } + + __chipidea_edpt_open(USB_OTG_DEV, ep_addr, ep_type); +} + +static bool chipidea_start_xfer(uint8_t busid, uint8_t ep_addr, uint8_t *buffer, uint32_t total_bytes) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + uint8_t const ep_idx = 2 * epnum + dir; + uint8_t qtd_num; + uint8_t i; + uint32_t xfer_len; + dcd_qhd_t *p_qhd; + dcd_qtd_t *p_qtd; + dcd_qtd_t *first_p_qtd = NULL; + dcd_qtd_t *prev_p_qtd = NULL; + dcd_data_t *dcd_data; + + dcd_data = g_chipidea_udc[busid].dcd_data; + + if (epnum == 0) { + /* follows UM Setup packet handling using setup lockout mechanism + * wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out + */ + while (USB_OTG_DEV->ENDPTSETUPSTAT & CHIPIDEA_BITSMASK(1, 0)) { + } + } + + qtd_num = (total_bytes + 0x3fff) / 0x4000; + if (qtd_num > QTD_COUNT_EACH_ENDPOINT) { + return false; + } + + if (buffer != NULL) { + buffer = (uint8_t *)buffer; + } + p_qhd = &dcd_data->qhd[ep_idx]; + i = 0; + do { + p_qtd = &dcd_data->qtd[ep_idx * QTD_COUNT_EACH_ENDPOINT + i]; + i++; + + if (total_bytes > 0x4000) { + xfer_len = 0x4000; + total_bytes -= 0x4000; + } else { + xfer_len = total_bytes; + total_bytes = 0; + } + + usb_qtd_init(p_qtd, (void *)buffer, xfer_len); + if (total_bytes == 0) { + p_qtd->int_on_complete = true; + } + buffer += xfer_len; + + if (prev_p_qtd) { + prev_p_qtd->next = (uint32_t)p_qtd; + } else { + first_p_qtd = p_qtd; + } + prev_p_qtd = p_qtd; + } while (total_bytes > 0); + + p_qhd->qtd_overlay.next = (uint32_t)first_p_qtd; /* link qtd to qhd */ + + chipidea_edpt_xfer(USB_OTG_DEV, ep_idx); + + return true; +} + +__WEAK void usb_dc_low_level_init(uint8_t busid) +{ +} + +__WEAK void usb_dc_low_level_deinit(uint8_t busid) +{ +} + +int usb_dc_init(uint8_t busid) +{ + uint32_t int_mask; + int_mask = (USB_USBINTR_UE_MASK | USB_USBINTR_UEE_MASK | USB_USBINTR_SLE_MASK | + USB_USBINTR_PCE_MASK | USB_USBINTR_URE_MASK); + + usb_dc_low_level_init(busid); + + memset(&g_chipidea_udc[busid], 0, sizeof(struct chipidea_udc)); + g_chipidea_udc[busid].dcd_data = g_dcd_data[busid]; + memset(g_chipidea_udc[busid].dcd_data, 0, sizeof(dcd_data_t)); + + chipidea_init(USB_OTG_DEV); + + /* Set endpoint list address */ + USB_OTG_DEV->ENDPTLISTADDR = ((uint32_t)g_chipidea_udc[busid].dcd_data->qhd) & USB_ENDPTLISTADDR_EPBASE_MASK; + + /* Clear status */ + USB_OTG_DEV->USBSTS = USB_OTG_DEV->USBSTS; + + /* Enable interrupt mask */ + USB_OTG_DEV->USBINTR |= int_mask; + + /* Connect by enabling internal pull-up resistor on D+/D- */ + USB_OTG_DEV->USBCMD |= USB_USBCMD_RS_MASK; + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + chipidea_deinit(USB_OTG_DEV); + + for (uint32_t i = 0; i < CONFIG_USBDEV_EP_NUM; i++) { + chipidea_edpt_close(USB_OTG_DEV, (i | 0x80)); + chipidea_edpt_close(USB_OTG_DEV, (i | 0x00)); + } + + usb_dc_low_level_deinit(busid); + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + USB_OTG_DEV->DEVICEADDR = USB_DEVICEADDR_USBADR_SET(addr) | USB_DEVICEADDR_USBADRA_MASK; + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + if (!USB_PORTSC1_SUSP_GET(USB_OTG_DEV->PORTSC1)) { + return -1; + } + + USB_OTG_DEV->PORTSC1 |= USB_PORTSC1_FPR_MASK; + while (USB_OTG_DEV->PORTSC1 & USB_PORTSC1_FPR_MASK) { + } + + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + uint8_t speed; + + speed = USB_PORTSC1_PSPD_GET(USB_OTG_DEV->PORTSC1); + + if (speed == 0x00) { + return USB_SPEED_FULL; + } + if (speed == 0x01) { + return USB_SPEED_LOW; + } + if (speed == 0x02) { + return USB_SPEED_HIGH; + } + + return 0; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + /* Must not exceed max endpoint number */ + if (ep_idx >= CONFIG_USBDEV_EP_NUM) { + return -1; + } + + chipidea_edpt_open(busid, ep->bEndpointAddress, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), ep->wMaxPacketSize); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_chipidea_udc[busid].out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_chipidea_udc[busid].out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_chipidea_udc[busid].out_ep[ep_idx].ep_enable = true; + } else { + g_chipidea_udc[busid].in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_chipidea_udc[busid].in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_chipidea_udc[busid].in_ep[ep_idx].ep_enable = true; + } + + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + g_chipidea_udc[busid].out_ep[ep_idx].ep_enable = false; + } else { + g_chipidea_udc[busid].in_ep[ep_idx].ep_enable = false; + } + + chipidea_edpt_close(USB_OTG_DEV, ep); + + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + chipidea_edpt_stall(USB_OTG_DEV, ep); + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + chipidea_edpt_clear_stall(USB_OTG_DEV, ep); + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + *stalled = chipidea_edpt_check_stall(USB_OTG_DEV, ep); + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_chipidea_udc[busid].in_ep[ep_idx].ep_enable) { + return -2; + } + + g_chipidea_udc[busid].in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_chipidea_udc[busid].in_ep[ep_idx].xfer_len = data_len; + g_chipidea_udc[busid].in_ep[ep_idx].actual_xfer_len = 0; + + chipidea_start_xfer(busid, ep, (uint8_t *)data, data_len); + + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_chipidea_udc[busid].out_ep[ep_idx].ep_enable) { + return -2; + } + + g_chipidea_udc[busid].out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_chipidea_udc[busid].out_ep[ep_idx].xfer_len = data_len; + g_chipidea_udc[busid].out_ep[ep_idx].actual_xfer_len = 0; + + chipidea_start_xfer(busid, ep, data, data_len); + + return 0; +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t int_status; + uint32_t transfer_len; + bool ep_cb_req; + + /* Acknowledge handled interrupt */ + int_status = USB_OTG_DEV->USBSTS; + int_status &= USB_OTG_DEV->USBINTR; + USB_OTG_DEV->USBSTS = int_status; + + if (int_status & intr_error) { + USB_LOG_ERR("usbd intr error!\r\n"); + } + + if (int_status & intr_reset) { + g_chipidea_udc[busid].is_suspend = false; + memset(g_chipidea_udc[busid].in_ep, 0, sizeof(struct chipidea_ep_state) * CONFIG_USBDEV_EP_NUM); + memset(g_chipidea_udc[busid].out_ep, 0, sizeof(struct chipidea_ep_state) * CONFIG_USBDEV_EP_NUM); + usbd_event_reset_handler(busid); + chipidea_bus_reset(busid, 64); + } + + if (int_status & intr_suspend) { + if (USB_PORTSC1_SUSP_GET(USB_OTG_DEV->PORTSC1)) { + /* Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration. */ + if (USB_DEVICEADDR_USBADR_GET(USB_OTG_DEV->DEVICEADDR)) { + g_chipidea_udc[busid].is_suspend = true; + usbd_event_suspend_handler(busid); + } + } else { + } + } + + if (int_status & intr_port_change) { + if (!USB_PORTSC1_CCS_GET(USB_OTG_DEV->PORTSC1)) { + usbd_event_disconnect_handler(busid); + } else { + if (g_chipidea_udc[busid].is_suspend) { + g_chipidea_udc[busid].is_suspend = false; + usbd_event_resume_handler(busid); + } + usbd_event_connect_handler(busid); + } + } + + if (int_status & intr_usb) { + uint32_t const edpt_complete = USB_OTG_DEV->ENDPTCOMPLETE; + USB_OTG_DEV->ENDPTCOMPLETE = edpt_complete; + uint32_t edpt_setup_status = USB_OTG_DEV->ENDPTSETUPSTAT; + + if (edpt_setup_status) { + /*------------- Set up Received -------------*/ + USB_OTG_DEV->ENDPTSETUPSTAT = edpt_setup_status; + dcd_qhd_t *qhd0 = chipidea_qhd_get(busid, 0); + usbd_event_ep0_setup_complete_handler(busid, (uint8_t *)&qhd0->setup_request); + } + + if (edpt_complete) { + for (uint8_t ep_idx = 0; ep_idx < (CONFIG_USBDEV_EP_NUM * 2); ep_idx++) { + if (edpt_complete & (1 << ep_idx2bit(ep_idx))) { + transfer_len = 0; + ep_cb_req = true; + + /* Failed QTD also get ENDPTCOMPLETE set */ + dcd_qtd_t *p_qtd = chipidea_qtd_get(busid, ep_idx); + while (1) { + if (p_qtd->halted || p_qtd->xact_err || p_qtd->buffer_err) { + USB_LOG_ERR("usbd transfer error!\r\n"); + ep_cb_req = false; + break; + } else if (p_qtd->active) { + ep_cb_req = false; + break; + } else { + transfer_len += p_qtd->expected_bytes - p_qtd->total_bytes; + } + + if (p_qtd->next == 1) { + break; + } else { + p_qtd = (dcd_qtd_t *)p_qtd->next; + } + } + + if (ep_cb_req) { + uint8_t const ep_addr = (ep_idx / 2) | ((ep_idx & 0x01) ? 0x80 : 0); + if (ep_addr & 0x80) { + usbd_event_ep_in_complete_handler(busid, ep_addr, transfer_len); + } else { + usbd_event_ep_out_complete_handler(busid, ep_addr, transfer_len); + } + } + } + } + } + } +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/chipidea/usb_glue_mcx.c b/rt-thread/components/drivers/usb/cherryusb/port/chipidea/usb_glue_mcx.c new file mode 100644 index 0000000..3f9b46b --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/chipidea/usb_glue_mcx.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "fsl_common.h" + +/*! @brief USB controller ID */ +typedef enum _usb_controller_index { + kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */ + kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved + to be used in the future. */ + kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */ + kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U */ +} usb_controller_index_t; + +#define USB_DEVICE_CONFIG_EHCI 1 + +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x04U) +#define BOARD_USB_PHY_TXCAL45DP (0x07U) +#define BOARD_USB_PHY_TXCAL45DM (0x07U) +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) +#include "usb_phy.h" +#endif + +#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) +void USB1_HS_IRQHandler(void) +{ + extern void USBD_IRQHandler(uint8_t busid); + USBD_IRQHandler(0); +} +#endif + +void USB_ClockInit(void) +{ +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; +#endif +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) + SPC0->ACTIVE_VDELAY = 0x0500; + /* Change the power DCDC to 1.8v (By deafult, DCDC is 1.8V), CORELDO to 1.1v (By deafult, CORELDO is 1.0V) */ + SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK; + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) | + SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u); + /* Wait until it is done */ + while (SPC0->SC & SPC_SC_BUSY_MASK) + ; + if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) { + SCG0->TRIM_LOCK = 0x5a5a0001U; + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + /* wait LDO ready */ + while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK)) + ; + } + SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK; + SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK); + /* xtal = 20 ~ 30MHz */ + SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT); + SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK; + while (1) { + if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) { + break; + } + } + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK; + CLOCK_EnableClock(kCLOCK_UsbHs); + CLOCK_EnableClock(kCLOCK_UsbHsPhy); + CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, 24000000U); + CLOCK_EnableUsbhsClock(); + USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &phyConfig); +#endif +#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0U) + CLOCK_AttachClk(kCLK_48M_to_USB0); + CLOCK_EnableClock(kCLOCK_Usb0Ram); + CLOCK_EnableClock(kCLOCK_Usb0Fs); + CLOCK_EnableUsbfsClock(); +#endif +} + +void usb_dc_low_level_init(uint8_t busid) +{ + USB_ClockInit(); + /* Install isr, set priority, and enable IRQ. */ + NVIC_SetPriority((IRQn_Type)USB1_HS_IRQn, 3); + EnableIRQ((IRQn_Type)USB1_HS_IRQn); +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + DisableIRQ((IRQn_Type)USB1_HS_IRQn); +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/README.md b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/README.md index 2111008..3218b31 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/README.md +++ b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/README.md @@ -1,5 +1,7 @@ # Note +If you are using more than one port, all ip parameters must be the same(like fifo num, endpoint num, dma support and so on), otherwise give up using multi ports. + ## Support Chip List ## STM32 @@ -18,6 +20,11 @@ ## GD32 +CONFIG_USBDEV_EP_NUM 必须为4 或者 6，并删除 usb_dc_dwc2.c 中 while(1){} + +当 CONFIG_USBDEV_EP_NUM 为4 时，fifo_num 不得大于 320 字 +当 CONFIG_USBDEV_EP_NUM 为6 时，fifo_num 不得大于 1280 字 + - GD32F30X_CL - GD32F405、GD32F407 - GD32F450 diff --git a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_dc_dwc2.c b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_dc_dwc2.c index 9dee5c1..6054a33 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_dc_dwc2.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_dc_dwc2.c @@ -51,8 +51,6 @@ #endif // clang-format on -//#define CONFIG_USB_DWC2_DMA_ENABLE - #ifndef CONFIG_USB_DWC2_RXALL_FIFO_SIZE #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4) #endif @@ -62,7 +60,7 @@ #endif #ifndef CONFIG_USB_DWC2_TX1_FIFO_SIZE -#define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4) +#define CONFIG_USB_DWC2_TX1_FIFO_SIZE (1024 / 4) #endif #ifndef CONFIG_USB_DWC2_TX2_FIFO_SIZE @@ -93,7 +91,7 @@ #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4) #endif -#define USBD_BASE (g_usbdev_bus[0].reg_base) +#define USBD_BASE (g_usbdev_bus[busid].reg_base) #define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(USBD_BASE)) #define USB_OTG_DEV ((DWC2_DeviceTypeDef *)(USBD_BASE + USB_OTG_DEVICE_BASE)) @@ -119,9 +117,9 @@ USB_NOCACHE_RAM_SECTION struct dwc2_udc { __attribute__((aligned(32))) struct usb_setup_packet setup; struct dwc2_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/ struct dwc2_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */ -} g_dwc2_udc; +} g_dwc2_udc[CONFIG_USBDEV_MAX_BUS]; -static inline int dwc2_reset(void) +static inline int dwc2_reset(uint8_t busid) { volatile uint32_t count = 0U; @@ -138,14 +136,16 @@ static inline int dwc2_reset(void) do { if (++count > 200000U) { - return -1; + break; } } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + USB_OTG_GLB->GRSTCTL &= ~USB_OTG_GRSTCTL_CSRST; + return 0; } -static inline int dwc2_core_init(void) +static inline int dwc2_core_init(uint8_t busid) { int ret; #if defined(CONFIG_USB_HS) @@ -156,18 +156,18 @@ static inline int dwc2_core_init(void) USB_OTG_GLB->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); /* Reset after a PHY select */ - ret = dwc2_reset(); + ret = dwc2_reset(busid); #else /* Select FS Embedded PHY */ USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; /* Reset after a PHY select */ - ret = dwc2_reset(); + ret = dwc2_reset(busid); #endif return ret; } -static inline void dwc2_set_mode(uint8_t mode) +static inline void dwc2_set_mode(uint8_t busid, uint8_t mode) { USB_OTG_GLB->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); @@ -176,12 +176,22 @@ static inline void dwc2_set_mode(uint8_t mode) } else if (mode == USB_OTG_MODE_DEVICE) { USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; } + + usbd_dwc2_delay_ms(50); } -static inline int dwc2_flush_rxfifo(void) +static inline int dwc2_flush_rxfifo(uint8_t busid) { - volatile uint32_t count = 0; + volatile uint32_t count = 0U; + /* Wait for AHB master IDLE state. */ + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + count = 0; USB_OTG_GLB->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; do { @@ -193,10 +203,18 @@ static inline int dwc2_flush_rxfifo(void) return 0; } -static inline int dwc2_flush_txfifo(uint32_t num) +static inline int dwc2_flush_txfifo(uint8_t busid, uint32_t num) { volatile uint32_t count = 0U; + /* Wait for AHB master IDLE state. */ + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + count = 0; USB_OTG_GLB->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); do { @@ -208,7 +226,7 @@ static inline int dwc2_flush_txfifo(uint32_t num) return 0; } -static void dwc2_set_turnaroundtime(uint32_t hclk, uint8_t speed) +static void dwc2_set_turnaroundtime(uint8_t busid, uint32_t hclk, uint8_t speed) { uint32_t UsbTrd; @@ -261,7 +279,7 @@ static void dwc2_set_turnaroundtime(uint32_t hclk, uint8_t speed) USB_OTG_GLB->GUSBCFG |= (uint32_t)((UsbTrd << USB_OTG_GUSBCFG_TRDT_Pos) & USB_OTG_GUSBCFG_TRDT); } -static void dwc2_set_txfifo(uint8_t fifo, uint16_t size) +static void dwc2_set_txfifo(uint8_t busid, uint8_t fifo, uint16_t size) { uint8_t i; uint32_t tx_offset; @@ -293,7 +311,7 @@ static void dwc2_set_txfifo(uint8_t fifo, uint16_t size) USB_LOG_INFO("fifo%d size:%04x, offset:%04x\r\n", fifo, size, tx_offset); } -static uint8_t dwc2_get_devspeed(void) +static uint8_t dwc2_get_devspeed(uint8_t busid) { uint8_t speed; uint32_t DevEnumSpeed = USB_OTG_DEV->DSTS & USB_OTG_DSTS_ENUMSPD; @@ -310,7 +328,7 @@ static uint8_t dwc2_get_devspeed(void) return speed; } -static void dwc2_ep0_start_read_setup(uint8_t *psetup) +static void dwc2_ep0_start_read_setup(uint8_t busid, uint8_t *psetup) { USB_OTG_OUTEP(0U)->DOEPTSIZ = 0U; USB_OTG_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); @@ -324,7 +342,7 @@ static void dwc2_ep0_start_read_setup(uint8_t *psetup) #endif } -void dwc2_ep_write(uint8_t ep_idx, uint8_t *src, uint16_t len) +void dwc2_ep_write(uint8_t busid, uint8_t ep_idx, uint8_t *src, uint16_t len) { uint32_t *pSrc = (uint32_t *)src; uint32_t count32b, i; @@ -336,7 +354,7 @@ void dwc2_ep_write(uint8_t ep_idx, uint8_t *src, uint16_t len) } } -void dwc2_ep_read(uint8_t *dest, uint16_t len) +void dwc2_ep_read(uint8_t busid, uint8_t *dest, uint16_t len) { uint32_t *pDest = (uint32_t *)dest; uint32_t i; @@ -348,33 +366,44 @@ void dwc2_ep_read(uint8_t *dest, uint16_t len) } } -static void dwc2_tx_fifo_empty_procecss(uint8_t ep_idx) +static void dwc2_tx_fifo_empty_procecss(uint8_t busid, uint8_t ep_idx) { uint32_t len; uint32_t len32b; uint32_t fifoemptymsk; - len = g_dwc2_udc.in_ep[ep_idx].xfer_len - g_dwc2_udc.in_ep[ep_idx].actual_xfer_len; - if (len > g_dwc2_udc.in_ep[ep_idx].ep_mps) { - len = g_dwc2_udc.in_ep[ep_idx].ep_mps; + len = g_dwc2_udc[busid].in_ep[ep_idx].xfer_len - g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len; + if (len > g_dwc2_udc[busid].in_ep[ep_idx].ep_mps) { + len = g_dwc2_udc[busid].in_ep[ep_idx].ep_mps; } len32b = (len + 3U) / 4U; while (((USB_OTG_INEP(ep_idx)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && - (g_dwc2_udc.in_ep[ep_idx].actual_xfer_len < g_dwc2_udc.in_ep[ep_idx].xfer_len) && (g_dwc2_udc.in_ep[ep_idx].xfer_len != 0U)) { + (g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len < g_dwc2_udc[busid].in_ep[ep_idx].xfer_len) && (g_dwc2_udc[busid].in_ep[ep_idx].xfer_len != 0U)) { /* Write the FIFO */ - len = g_dwc2_udc.in_ep[ep_idx].xfer_len - g_dwc2_udc.in_ep[ep_idx].actual_xfer_len; - if (len > g_dwc2_udc.in_ep[ep_idx].ep_mps) { - len = g_dwc2_udc.in_ep[ep_idx].ep_mps; + len = g_dwc2_udc[busid].in_ep[ep_idx].xfer_len - g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len; + if (len > g_dwc2_udc[busid].in_ep[ep_idx].ep_mps) { + len = g_dwc2_udc[busid].in_ep[ep_idx].ep_mps; + } + if (g_dwc2_udc[busid].in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + if ((USB_OTG_DEV->DSTS & (1U << 8)) == 0U) { + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } else { + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_SODDFRM; + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + USB_OTG_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); } - dwc2_ep_write(ep_idx, g_dwc2_udc.in_ep[ep_idx].xfer_buf, len); - g_dwc2_udc.in_ep[ep_idx].xfer_buf += len; - g_dwc2_udc.in_ep[ep_idx].actual_xfer_len += len; + dwc2_ep_write(busid, ep_idx, g_dwc2_udc[busid].in_ep[ep_idx].xfer_buf, len); + g_dwc2_udc[busid].in_ep[ep_idx].xfer_buf += len; + g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len += len; } - if (g_dwc2_udc.in_ep[ep_idx].xfer_len <= g_dwc2_udc.in_ep[ep_idx].actual_xfer_len) { + if (g_dwc2_udc[busid].in_ep[ep_idx].xfer_len <= g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len) { fifoemptymsk = (uint32_t)(0x1UL << (ep_idx & 0x0f)); USB_OTG_DEV->DIEPEMPMSK &= ~fifoemptymsk; } @@ -384,7 +413,7 @@ static void dwc2_tx_fifo_empty_procecss(uint8_t ep_idx) * @brief dwc2_get_glb_intstatus: return the global USB interrupt status * @retval status */ -static inline uint32_t dwc2_get_glb_intstatus(void) +static inline uint32_t dwc2_get_glb_intstatus(uint8_t busid) { uint32_t tmpreg; @@ -398,7 +427,7 @@ static inline uint32_t dwc2_get_glb_intstatus(void) * @brief dwc2_get_outeps_intstatus: return the USB device OUT endpoints interrupt status * @retval status */ -static inline uint32_t dwc2_get_outeps_intstatus(void) +static inline uint32_t dwc2_get_outeps_intstatus(uint8_t busid) { uint32_t tmpreg; @@ -412,7 +441,7 @@ static inline uint32_t dwc2_get_outeps_intstatus(void) * @brief dwc2_get_ineps_intstatus: return the USB device IN endpoints interrupt status * @retval status */ -static inline uint32_t dwc2_get_ineps_intstatus(void) +static inline uint32_t dwc2_get_ineps_intstatus(uint8_t busid) { uint32_t tmpreg; @@ -428,12 +457,13 @@ static inline uint32_t dwc2_get_ineps_intstatus(void) * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ -static inline uint32_t dwc2_get_outep_intstatus(uint8_t epnum) +static inline uint32_t dwc2_get_outep_intstatus(uint8_t busid, uint8_t epnum) { uint32_t tmpreg; tmpreg = USB_OTG_OUTEP((uint32_t)epnum)->DOEPINT; - tmpreg &= USB_OTG_DEV->DOEPMSK; + USB_OTG_OUTEP((uint32_t)epnum)->DOEPINT = tmpreg; + tmpreg = tmpreg & USB_OTG_DEV->DOEPMSK; return tmpreg; } @@ -444,26 +474,21 @@ static inline uint32_t dwc2_get_outep_intstatus(uint8_t epnum) * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ -static inline uint32_t dwc2_get_inep_intstatus(uint8_t epnum) +static inline uint32_t dwc2_get_inep_intstatus(uint8_t busid, uint8_t epnum) { uint32_t tmpreg, msk, emp; msk = USB_OTG_DEV->DIEPMSK; emp = USB_OTG_DEV->DIEPEMPMSK; - msk |= ((emp >> (epnum & 0x07)) & 0x1U) << 7; - tmpreg = USB_OTG_INEP((uint32_t)epnum)->DIEPINT & msk; + msk |= ((emp >> (epnum & 0x0F)) & 0x1U) << 7; + + tmpreg = USB_OTG_INEP((uint32_t)epnum)->DIEPINT; + USB_OTG_INEP((uint32_t)epnum)->DIEPINT = tmpreg; + tmpreg = tmpreg & msk; return tmpreg; } -__WEAK void usb_dc_low_level_init(void) -{ -} - -__WEAK void usb_dc_low_level_deinit(void) -{ -} - int usb_dc_init(uint8_t busid) { int ret; @@ -473,9 +498,9 @@ int usb_dc_init(uint8_t busid) uint8_t endpoints; uint32_t fifo_num; - memset(&g_dwc2_udc, 0, sizeof(struct dwc2_udc)); + memset(&g_dwc2_udc[busid], 0, sizeof(struct dwc2_udc)); - usb_dc_low_level_init(); + usb_dc_low_level_init(busid); /* Full-Speed PHY Interface Type (FSPhyType) @@ -526,14 +551,10 @@ int usb_dc_init(uint8_t busid) /* This is vendor register */ USB_OTG_GLB->GCCFG = usbd_get_dwc2_gccfg_conf(USBD_BASE); - ret = dwc2_core_init(); + ret = dwc2_core_init(busid); /* Force Device Mode*/ - dwc2_set_mode(USB_OTG_MODE_DEVICE); - - /* B-peripheral session valid override enable */ - // USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; - // USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + dwc2_set_mode(busid, USB_OTG_MODE_DEVICE); for (uint8_t i = 0U; i < 15U; i++) { USB_OTG_GLB->DIEPTXF[i] = 0U; @@ -567,7 +588,7 @@ int usb_dc_init(uint8_t busid) /* Enable interrupts matching to the Device mode ONLY */ USB_OTG_GLB->GINTMSK = USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT | - USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM; + USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM; #ifdef CONFIG_USB_DWC2_DMA_ENABLE if (((USB_OTG_GLB->GHWCFG2 & (0x3U << 3)) >> 3) != 2) { @@ -577,6 +598,7 @@ int usb_dc_init(uint8_t busid) } USB_OTG_DEV->DCFG &= ~USB_OTG_DCFG_DESCDMA; + USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_HBSTLEN; USB_OTG_GLB->GAHBCFG |= (USB_OTG_GAHBCFG_DMAEN | USB_OTG_GAHBCFG_HBSTLEN_4); #else USB_OTG_GLB->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; @@ -590,10 +612,10 @@ int usb_dc_init(uint8_t busid) USB_OTG_GLB->GRXFSIZ = (CONFIG_USB_DWC2_RXALL_FIFO_SIZE); - dwc2_set_txfifo(0, CONFIG_USB_DWC2_TX0_FIFO_SIZE); - dwc2_set_txfifo(1, CONFIG_USB_DWC2_TX1_FIFO_SIZE); - dwc2_set_txfifo(2, CONFIG_USB_DWC2_TX2_FIFO_SIZE); - dwc2_set_txfifo(3, CONFIG_USB_DWC2_TX3_FIFO_SIZE); + dwc2_set_txfifo(busid, 0, CONFIG_USB_DWC2_TX0_FIFO_SIZE); + dwc2_set_txfifo(busid, 1, CONFIG_USB_DWC2_TX1_FIFO_SIZE); + dwc2_set_txfifo(busid, 2, CONFIG_USB_DWC2_TX2_FIFO_SIZE); + dwc2_set_txfifo(busid, 3, CONFIG_USB_DWC2_TX3_FIFO_SIZE); fifo_num = CONFIG_USB_DWC2_RXALL_FIFO_SIZE; fifo_num += CONFIG_USB_DWC2_TX0_FIFO_SIZE; @@ -601,23 +623,23 @@ int usb_dc_init(uint8_t busid) fifo_num += CONFIG_USB_DWC2_TX2_FIFO_SIZE; fifo_num += CONFIG_USB_DWC2_TX3_FIFO_SIZE; #if CONFIG_USBDEV_EP_NUM > 4 - dwc2_set_txfifo(4, CONFIG_USB_DWC2_TX4_FIFO_SIZE); + dwc2_set_txfifo(busid, 4, CONFIG_USB_DWC2_TX4_FIFO_SIZE); fifo_num += CONFIG_USB_DWC2_TX4_FIFO_SIZE; #endif #if CONFIG_USBDEV_EP_NUM > 5 - dwc2_set_txfifo(5, CONFIG_USB_DWC2_TX5_FIFO_SIZE); + dwc2_set_txfifo(busid, 5, CONFIG_USB_DWC2_TX5_FIFO_SIZE); fifo_num += CONFIG_USB_DWC2_TX5_FIFO_SIZE; #endif #if CONFIG_USBDEV_EP_NUM > 6 - dwc2_set_txfifo(6, CONFIG_USB_DWC2_TX6_FIFO_SIZE); + dwc2_set_txfifo(busid, 6, CONFIG_USB_DWC2_TX6_FIFO_SIZE); fifo_num += CONFIG_USB_DWC2_TX6_FIFO_SIZE; #endif #if CONFIG_USBDEV_EP_NUM > 7 - dwc2_set_txfifo(7, CONFIG_USB_DWC2_TX7_FIFO_SIZE); + dwc2_set_txfifo(busid, 7, CONFIG_USB_DWC2_TX7_FIFO_SIZE); fifo_num += CONFIG_USB_DWC2_TX7_FIFO_SIZE; #endif #if CONFIG_USBDEV_EP_NUM > 8 - dwc2_set_txfifo(8, CONFIG_USB_DWC2_TX8_FIFO_SIZE); + dwc2_set_txfifo(busid, 8, CONFIG_USB_DWC2_TX8_FIFO_SIZE); fifo_num += CONFIG_USB_DWC2_TX8_FIFO_SIZE; #endif @@ -634,8 +656,8 @@ int usb_dc_init(uint8_t busid) } } - ret = dwc2_flush_txfifo(0x10U); - ret = dwc2_flush_rxfifo(); + ret = dwc2_flush_txfifo(busid, 0x10U); + ret = dwc2_flush_rxfifo(busid); USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_GINT; USB_OTG_DEV->DCTL &= ~USB_OTG_DCTL_SDIS; @@ -660,10 +682,10 @@ int usb_dc_deinit(uint8_t busid) USB_OTG_DEV->DAINTMSK = 0U; /* Flush the FIFO */ - dwc2_flush_txfifo(0x10U); - dwc2_flush_rxfifo(); + dwc2_flush_txfifo(busid, 0x10U); + dwc2_flush_rxfifo(busid); - usb_dc_low_level_deinit(); + usb_dc_low_level_deinit(busid); return 0; } @@ -674,6 +696,17 @@ int usbd_set_address(uint8_t busid, const uint8_t addr) return 0; } +int usbd_set_remote_wakeup(uint8_t busid) +{ + if (!(USB_OTG_DEV->DSTS & USB_OTG_DSTS_SUSPSTS)) { + return -1; + } + USB_OTG_DEV->DCTL |= USB_OTG_DCTL_RWUSIG; + usbd_dwc2_delay_ms(10); + USB_OTG_DEV->DCTL &= ~USB_OTG_DCTL_RWUSIG; + return 0; +} + uint8_t usbd_get_port_speed(uint8_t busid) { uint8_t speed; @@ -701,8 +734,8 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) } if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { - g_dwc2_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); - g_dwc2_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_dwc2_udc[busid].out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_dwc2_udc[busid].out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & (uint32_t)(1UL << (16 + ep_idx)); @@ -724,8 +757,8 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) return -2; } - g_dwc2_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); - g_dwc2_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_dwc2_udc[busid].in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_dwc2_udc[busid].in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << ep_idx); @@ -735,7 +768,7 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_USBAEP; } - dwc2_flush_txfifo(ep_idx); + dwc2_flush_txfifo(busid, ep_idx); } return 0; } @@ -759,7 +792,7 @@ int usbd_ep_close(uint8_t busid, const uint8_t ep) } while ((USB_OTG_OUTEP(ep_idx)->DOEPINT & USB_OTG_DOEPINT_EPDISD) != USB_OTG_DOEPINT_EPDISD); /* Clear and unmask endpoint disabled interrupt */ - USB_OTG_OUTEP(ep_idx)->DOEPINT |= USB_OTG_DOEPINT_EPDISD; + USB_OTG_OUTEP(ep_idx)->DOEPINT = USB_OTG_DOEPINT_EPDISD; } USB_OTG_DEV->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep_idx & 0x07)) << 16)); @@ -779,7 +812,7 @@ int usbd_ep_close(uint8_t busid, const uint8_t ep) } while ((USB_OTG_INEP(ep_idx)->DIEPINT & USB_OTG_DIEPINT_EPDISD) != USB_OTG_DIEPINT_EPDISD); /* Clear and unmask endpoint disabled interrupt */ - USB_OTG_INEP(ep_idx)->DIEPINT |= USB_OTG_DIEPINT_EPDISD; + USB_OTG_INEP(ep_idx)->DIEPINT = USB_OTG_DIEPINT_EPDISD; } USB_OTG_DEV->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep_idx & 0x07))); @@ -806,7 +839,7 @@ int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) } #ifdef CONFIG_USB_DWC2_DMA_ENABLE if (ep_idx == 0) { - dwc2_ep0_start_read_setup((uint8_t *)&g_dwc2_udc.setup); + dwc2_ep0_start_read_setup(busid, (uint8_t *)&g_dwc2_udc[busid].setup); } #endif return 0; @@ -818,14 +851,14 @@ int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) if (USB_EP_DIR_IS_OUT(ep)) { USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - if ((g_dwc2_udc.out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_INTERRUPT) || - (g_dwc2_udc.out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_BULK)) { + if ((g_dwc2_udc[busid].out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_INTERRUPT) || + (g_dwc2_udc[busid].out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_BULK)) { USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ } } else { USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - if ((g_dwc2_udc.in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_INTERRUPT) || - (g_dwc2_udc.in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_BULK)) { + if ((g_dwc2_udc[busid].in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_INTERRUPT) || + (g_dwc2_udc[busid].in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_BULK)) { USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ } } @@ -834,8 +867,20 @@ int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) { + uint8_t ep_idx = USB_EP_GET_IDX(ep); + if (USB_EP_DIR_IS_OUT(ep)) { + if (USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } } else { + if (USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } } return 0; } @@ -860,9 +905,9 @@ int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, ui return -4; } - g_dwc2_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; - g_dwc2_udc.in_ep[ep_idx].xfer_len = data_len; - g_dwc2_udc.in_ep[ep_idx].actual_xfer_len = 0; + g_dwc2_udc[busid].in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_dwc2_udc[busid].in_ep[ep_idx].xfer_len = data_len; + g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len = 0; USB_OTG_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); USB_OTG_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); @@ -874,20 +919,20 @@ int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, ui } if (ep_idx == 0) { - if (data_len > g_dwc2_udc.in_ep[ep_idx].ep_mps) { - data_len = g_dwc2_udc.in_ep[ep_idx].ep_mps; + if (data_len > g_dwc2_udc[busid].in_ep[ep_idx].ep_mps) { + data_len = g_dwc2_udc[busid].in_ep[ep_idx].ep_mps; } - g_dwc2_udc.in_ep[ep_idx].xfer_len = data_len; + g_dwc2_udc[busid].in_ep[ep_idx].xfer_len = data_len; USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & data_len); } else { - pktcnt = (uint16_t)((data_len + g_dwc2_udc.in_ep[ep_idx].ep_mps - 1U) / g_dwc2_udc.in_ep[ep_idx].ep_mps); + pktcnt = (uint16_t)((data_len + g_dwc2_udc[busid].in_ep[ep_idx].ep_mps - 1U) / g_dwc2_udc[busid].in_ep[ep_idx].ep_mps); USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (pktcnt << 19)); USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & data_len); } - if (g_dwc2_udc.in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + if (g_dwc2_udc[busid].in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { if ((USB_OTG_DEV->DSTS & (1U << 8)) == 0U) { USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_SD0PID_SEVNFRM; USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; @@ -933,28 +978,28 @@ int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t return -4; } - g_dwc2_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; - g_dwc2_udc.out_ep[ep_idx].xfer_len = data_len; - g_dwc2_udc.out_ep[ep_idx].actual_xfer_len = 0; + g_dwc2_udc[busid].out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_dwc2_udc[busid].out_ep[ep_idx].xfer_len = data_len; + g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len = 0; USB_OTG_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); USB_OTG_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); if (data_len == 0) { USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); - USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & g_dwc2_udc.out_ep[ep_idx].ep_mps); + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & g_dwc2_udc[busid].out_ep[ep_idx].ep_mps); USB_OTG_OUTEP(ep_idx)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); return 0; } if (ep_idx == 0) { - if (data_len > g_dwc2_udc.out_ep[ep_idx].ep_mps) { - data_len = g_dwc2_udc.out_ep[ep_idx].ep_mps; + if (data_len > g_dwc2_udc[busid].out_ep[ep_idx].ep_mps) { + data_len = g_dwc2_udc[busid].out_ep[ep_idx].ep_mps; } - g_dwc2_udc.out_ep[ep_idx].xfer_len = data_len; + g_dwc2_udc[busid].out_ep[ep_idx].xfer_len = data_len; USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & data_len); } else { - pktcnt = (uint16_t)((data_len + g_dwc2_udc.out_ep[ep_idx].ep_mps - 1U) / g_dwc2_udc.out_ep[ep_idx].ep_mps); + pktcnt = (uint16_t)((data_len + g_dwc2_udc[busid].out_ep[ep_idx].ep_mps - 1U) / g_dwc2_udc[busid].out_ep[ep_idx].ep_mps); USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & data_len); @@ -963,7 +1008,7 @@ int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t #ifdef CONFIG_USB_DWC2_DMA_ENABLE USB_OTG_OUTEP(ep_idx)->DOEPDMA = (uint32_t)data; #endif - if (g_dwc2_udc.out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + if (g_dwc2_udc[busid].out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { if ((USB_OTG_DEV->DSTS & (1U << 8)) == 0U) { USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_SD0PID_SEVNFRM; USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; @@ -979,7 +1024,7 @@ int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t void USBD_IRQHandler(uint8_t busid) { uint32_t gint_status, temp, ep_idx, ep_intr, epint, read_count, daintmask; - gint_status = dwc2_get_glb_intstatus(); + gint_status = dwc2_get_glb_intstatus(busid); if ((USB_OTG_GLB->GINTSTS & 0x1U) == USB_OTG_MODE_DEVICE) { /* Avoid spurious interrupt */ @@ -998,12 +1043,12 @@ void USBD_IRQHandler(uint8_t busid) if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> USB_OTG_GRXSTSP_PKTSTS_Pos) == STS_DATA_UPDT) { read_count = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; if (read_count != 0) { - dwc2_ep_read(g_dwc2_udc.out_ep[ep_idx].xfer_buf, read_count); - g_dwc2_udc.out_ep[ep_idx].xfer_buf += read_count; + dwc2_ep_read(busid, g_dwc2_udc[busid].out_ep[ep_idx].xfer_buf, read_count); + g_dwc2_udc[busid].out_ep[ep_idx].xfer_buf += read_count; } } else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> USB_OTG_GRXSTSP_PKTSTS_Pos) == STS_SETUP_UPDT) { read_count = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - dwc2_ep_read((uint8_t *)&g_dwc2_udc.setup, read_count); + dwc2_ep_read(busid, (uint8_t *)&g_dwc2_udc[busid].setup, read_count); } else { /* ... */ } @@ -1012,32 +1057,30 @@ void USBD_IRQHandler(uint8_t busid) #endif if (gint_status & USB_OTG_GINTSTS_OEPINT) { ep_idx = 0; - ep_intr = dwc2_get_outeps_intstatus(); + ep_intr = dwc2_get_outeps_intstatus(busid); while (ep_intr != 0U) { if ((ep_intr & 0x1U) != 0U) { - epint = dwc2_get_outep_intstatus(ep_idx); - uint32_t DoepintReg = USB_OTG_OUTEP(ep_idx)->DOEPINT; - USB_OTG_OUTEP(ep_idx)->DOEPINT = DoepintReg; + epint = dwc2_get_outep_intstatus(busid, ep_idx); if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) { if (ep_idx == 0) { - if (g_dwc2_udc.out_ep[ep_idx].xfer_len == 0) { + if (g_dwc2_udc[busid].out_ep[ep_idx].xfer_len == 0) { /* Out status, start reading setup */ - dwc2_ep0_start_read_setup((uint8_t *)&g_dwc2_udc.setup); + dwc2_ep0_start_read_setup(busid, (uint8_t *)&g_dwc2_udc[busid].setup); } else { - g_dwc2_udc.out_ep[ep_idx].actual_xfer_len = g_dwc2_udc.out_ep[ep_idx].xfer_len - ((USB_OTG_OUTEP(ep_idx)->DOEPTSIZ) & USB_OTG_DOEPTSIZ_XFRSIZ); - g_dwc2_udc.out_ep[ep_idx].xfer_len = 0; - usbd_event_ep_out_complete_handler(0, 0x00, g_dwc2_udc.out_ep[ep_idx].actual_xfer_len); + g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len = g_dwc2_udc[busid].out_ep[ep_idx].xfer_len - ((USB_OTG_OUTEP(ep_idx)->DOEPTSIZ) & USB_OTG_DOEPTSIZ_XFRSIZ); + g_dwc2_udc[busid].out_ep[ep_idx].xfer_len = 0; + usbd_event_ep_out_complete_handler(busid, 0x00, g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len); } } else { - g_dwc2_udc.out_ep[ep_idx].actual_xfer_len = g_dwc2_udc.out_ep[ep_idx].xfer_len - ((USB_OTG_OUTEP(ep_idx)->DOEPTSIZ) & USB_OTG_DOEPTSIZ_XFRSIZ); - g_dwc2_udc.out_ep[ep_idx].xfer_len = 0; - usbd_event_ep_out_complete_handler(0, ep_idx, g_dwc2_udc.out_ep[ep_idx].actual_xfer_len); + g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len = g_dwc2_udc[busid].out_ep[ep_idx].xfer_len - ((USB_OTG_OUTEP(ep_idx)->DOEPTSIZ) & USB_OTG_DOEPTSIZ_XFRSIZ); + g_dwc2_udc[busid].out_ep[ep_idx].xfer_len = 0; + usbd_event_ep_out_complete_handler(busid, ep_idx, g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len); } } if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) { - usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_dwc2_udc.setup); + usbd_event_ep0_setup_complete_handler(busid, (uint8_t *)&g_dwc2_udc[busid].setup); } } ep_intr >>= 1U; @@ -1046,34 +1089,32 @@ void USBD_IRQHandler(uint8_t busid) } if (gint_status & USB_OTG_GINTSTS_IEPINT) { ep_idx = 0U; - ep_intr = dwc2_get_ineps_intstatus(); + ep_intr = dwc2_get_ineps_intstatus(busid); while (ep_intr != 0U) { if ((ep_intr & 0x1U) != 0U) { - epint = dwc2_get_inep_intstatus(ep_idx); - uint32_t DiepintReg = USB_OTG_INEP(ep_idx)->DIEPINT; - USB_OTG_INEP(ep_idx)->DIEPINT = DiepintReg; + epint = dwc2_get_inep_intstatus(busid, ep_idx); if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) { if (ep_idx == 0) { - g_dwc2_udc.in_ep[ep_idx].actual_xfer_len = g_dwc2_udc.in_ep[ep_idx].xfer_len - ((USB_OTG_INEP(ep_idx)->DIEPTSIZ) & USB_OTG_DIEPTSIZ_XFRSIZ); - g_dwc2_udc.in_ep[ep_idx].xfer_len = 0; - usbd_event_ep_in_complete_handler(0, 0x80, g_dwc2_udc.in_ep[ep_idx].actual_xfer_len); + g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len = g_dwc2_udc[busid].in_ep[ep_idx].xfer_len - ((USB_OTG_INEP(ep_idx)->DIEPTSIZ) & USB_OTG_DIEPTSIZ_XFRSIZ); + g_dwc2_udc[busid].in_ep[ep_idx].xfer_len = 0; + usbd_event_ep_in_complete_handler(busid, 0x80, g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len); - if (g_dwc2_udc.setup.wLength && ((g_dwc2_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { + if (g_dwc2_udc[busid].setup.wLength && ((g_dwc2_udc[busid].setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { /* In status, start reading setup */ - dwc2_ep0_start_read_setup((uint8_t *)&g_dwc2_udc.setup); - } else if (g_dwc2_udc.setup.wLength == 0) { + dwc2_ep0_start_read_setup(busid, (uint8_t *)&g_dwc2_udc[busid].setup); + } else if (g_dwc2_udc[busid].setup.wLength == 0) { /* In status, start reading setup */ - dwc2_ep0_start_read_setup((uint8_t *)&g_dwc2_udc.setup); + dwc2_ep0_start_read_setup(busid, (uint8_t *)&g_dwc2_udc[busid].setup); } } else { - g_dwc2_udc.in_ep[ep_idx].actual_xfer_len = g_dwc2_udc.in_ep[ep_idx].xfer_len - ((USB_OTG_INEP(ep_idx)->DIEPTSIZ) & USB_OTG_DIEPTSIZ_XFRSIZ); - g_dwc2_udc.in_ep[ep_idx].xfer_len = 0; - usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_dwc2_udc.in_ep[ep_idx].actual_xfer_len); + g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len = g_dwc2_udc[busid].in_ep[ep_idx].xfer_len - ((USB_OTG_INEP(ep_idx)->DIEPTSIZ) & USB_OTG_DIEPTSIZ_XFRSIZ); + g_dwc2_udc[busid].in_ep[ep_idx].xfer_len = 0; + usbd_event_ep_in_complete_handler(busid, ep_idx | 0x80, g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len); } } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) { - dwc2_tx_fifo_empty_procecss(ep_idx); + dwc2_tx_fifo_empty_procecss(busid, ep_idx); } } ep_intr >>= 1U; @@ -1081,11 +1122,11 @@ void USBD_IRQHandler(uint8_t busid) } } if (gint_status & USB_OTG_GINTSTS_USBRST) { - USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_USBRST; + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_USBRST; USB_OTG_DEV->DCTL &= ~USB_OTG_DCTL_RWUSIG; - dwc2_flush_txfifo(0x10U); - dwc2_flush_rxfifo(); + dwc2_flush_txfifo(busid, 0x10U); + dwc2_flush_rxfifo(busid); for (uint8_t i = 0U; i < CONFIG_USBDEV_EP_NUM; i++) { if (i == 0U) { @@ -1116,69 +1157,35 @@ void USBD_IRQHandler(uint8_t busid) USB_OTG_DEV->DIEPMSK = USB_OTG_DIEPMSK_XFRCM; - memset(&g_dwc2_udc, 0, sizeof(struct dwc2_udc)); - usbd_event_reset_handler(0); + memset(&g_dwc2_udc[busid], 0, sizeof(struct dwc2_udc)); + usbd_event_reset_handler(busid); /* Start reading setup */ - dwc2_ep0_start_read_setup((uint8_t *)&g_dwc2_udc.setup); + dwc2_ep0_start_read_setup(busid, (uint8_t *)&g_dwc2_udc[busid].setup); } if (gint_status & USB_OTG_GINTSTS_ENUMDNE) { - USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_ENUMDNE; - dwc2_set_turnaroundtime(SystemCoreClock, dwc2_get_devspeed()); + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_ENUMDNE; + dwc2_set_turnaroundtime(busid, SystemCoreClock, dwc2_get_devspeed(busid)); USB_OTG_DEV->DCTL |= USB_OTG_DCTL_CGINAK; } if (gint_status & USB_OTG_GINTSTS_PXFR_INCOMPISOOUT) { - daintmask = USB_OTG_DEV->DAINTMSK; - daintmask >>= 16; - - for (ep_idx = 1; ep_idx < CONFIG_USBDEV_EP_NUM; ep_idx++) { - if ((BIT(ep_idx) & ~daintmask) || (g_dwc2_udc.out_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS)) - continue; - if (!(USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_USBAEP)) - continue; - - if ((USB_OTG_DEV->DSTS & (1U << 8)) != 0U) { - USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; - USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_SODDFRM; - } else { - USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_SD0PID_SEVNFRM; - USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; - } - } - - USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_PXFR_INCOMPISOOUT; + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_PXFR_INCOMPISOOUT; } if (gint_status & USB_OTG_GINTSTS_IISOIXFR) { - daintmask = USB_OTG_DEV->DAINTMSK; - daintmask >>= 16; - - for (ep_idx = 1; ep_idx < CONFIG_USBDEV_EP_NUM; ep_idx++) { - if (((BIT(ep_idx) & ~daintmask)) || (g_dwc2_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS)) - continue; - - if (!(USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP)) - continue; - - if ((USB_OTG_DEV->DSTS & (1U << 8)) != 0U) { - USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_SODDFRM; - } else { - USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; - } - } - USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_IISOIXFR; + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_IISOIXFR; } if (gint_status & USB_OTG_GINTSTS_SOF) { - USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_SOF; + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_SOF; } if (gint_status & USB_OTG_GINTSTS_USBSUSP) { - USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_USBSUSP; + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_USBSUSP; + usbd_event_suspend_handler(busid); } if (gint_status & USB_OTG_GINTSTS_WKUINT) { - USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_WKUINT; + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_WKUINT; + usbd_event_resume_handler(busid); } if (gint_status & USB_OTG_GINTSTS_OTGINT) { temp = USB_OTG_GLB->GOTGINT; diff --git a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_dwc2_reg.h b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_dwc2_reg.h index c3bd75d..5f9b5f9 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_dwc2_reg.h +++ b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_dwc2_reg.h @@ -1716,6 +1716,9 @@ typedef struct #define USB_UNMASK_HALT_HC_INT(chnum) (USB_OTG_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) #define CLEAR_HC_INT(chnum, __INTERRUPT__) (USB_OTG_HC(chnum)->HCINT = (__INTERRUPT__)) +void usb_dc_low_level_init(uint8_t busid); +void usb_dc_low_level_deinit(uint8_t busid); uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base); uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base); +void usbd_dwc2_delay_ms(uint8_t ms); #endif diff --git a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_at.c b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_at.c index d9c2626..8d45f65 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_at.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_at.c @@ -7,16 +7,20 @@ #include "stdint.h" #include "usb_dwc2_reg.h" +extern unsigned int system_core_clock; + +uint32_t SystemCoreClock; /* you can find this config in function: usb_global_init, file:at32fxxx_usb.c, for example: * * usbx->gccfg_bit.pwrdown = TRUE; * usbx->gccfg_bit.avalidsesen = TRUE; * usbx->gccfg_bit.bvalidsesen = TRUE; - * + * */ uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base) { + SystemCoreClock = system_core_clock; #ifdef CONFIG_USB_HS return ((1 << 16) | (1 << 21)); #else @@ -35,6 +39,7 @@ uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base) uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) { + SystemCoreClock = system_core_clock; #ifdef CONFIG_USB_HS return ((1 << 16) | (1 << 21)); #else @@ -49,4 +54,9 @@ uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) return ((1 << 16) | (1 << 21)); #endif #endif +} + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + /* implement later */ } \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_esp.c b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_esp.c index 8c63234..76abb19 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_esp.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_esp.c @@ -8,13 +8,19 @@ #include "esp_intr_alloc.h" #include "esp_private/usb_phy.h" #include "soc/periph_defs.h" +#include "freertos/FreeRTOS.h" #include "usbd_core.h" #include "usbh_core.h" #ifdef CONFIG_IDF_TARGET_ESP32S2 #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ +#define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE #elif CONFIG_IDF_TARGET_ESP32S3 #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ +#define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE +#elif CONFIG_IDF_TARGET_ESP32P4 +#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ +#define DEFAULT_USB_INTR_SOURCE ETS_USB_OTG_INTR_SOURCE #else #define DEFAULT_CPU_FREQ_MHZ 160 #endif @@ -29,7 +35,7 @@ static void usb_dc_interrupt_cb(void *arg_pv) USBD_IRQHandler(0); } -void usb_dc_low_level_init(void) +void usb_dc_low_level_init(uint8_t busid) { usb_phy_config_t phy_config = { .controller = USB_PHY_CTRL_OTG, @@ -44,15 +50,15 @@ void usb_dc_low_level_init(void) } // TODO: Check when to enable interrupt - ret = esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LEVEL2, usb_dc_interrupt_cb, 0, &s_interrupt_handle); + ret = esp_intr_alloc(DEFAULT_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, usb_dc_interrupt_cb, 0, &s_interrupt_handle); if (ret != ESP_OK) { USB_LOG_ERR("USB Interrupt Init Failed!\r\n"); return; } - USB_LOG_INFO("cherryusb, version: 0x%06x\r\n", CHERRYUSB_VERSION); + USB_LOG_INFO("cherryusb, version: "CHERRYUSB_VERSION_STR"\r\n"); } -void usb_dc_low_level_deinit(void) +void usb_dc_low_level_deinit(uint8_t busid) { if (s_interrupt_handle) { esp_intr_free(s_interrupt_handle); @@ -94,12 +100,12 @@ void usb_hc_low_level_init(struct usbh_bus *bus) } // TODO: Check when to enable interrupt - ret = esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LEVEL2, usb_hc_interrupt_cb, 0, &s_interrupt_handle); + ret = esp_intr_alloc(DEFAULT_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, usb_hc_interrupt_cb, 0, &s_interrupt_handle); if (ret != ESP_OK) { USB_LOG_ERR("USB Interrupt Init Failed!\r\n"); return; } - USB_LOG_INFO("cherryusb, version: 0x%06x\r\n", CHERRYUSB_VERSION); + USB_LOG_INFO("cherryusb, version: "CHERRYUSB_VERSION_STR"\r\n"); } void usb_hc_low_level_deinit(struct usbh_bus *bus) @@ -118,3 +124,8 @@ uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) { return 0; } + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + vTaskDelay(pdMS_TO_TICKS(ms)); +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_gd.c b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_gd.c index bdc0d68..f3fa4d9 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_gd.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_gd.c @@ -7,10 +7,14 @@ #include "stdint.h" #include "usb_dwc2_reg.h" +#if CONFIG_USBDEV_EP_NUM != 4 && CONFIG_USBDEV_EP_NUM != 6 +#error "gd32 only has 4 endpoints for pa11/pa12 and 6 endpoints for pb14/pb15" +#endif + /* you can find this config in function:usb_core_init, file:drv_usb_core.c, for example: * * usb_regs->gr->GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; - * + * */ uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base) @@ -29,4 +33,9 @@ uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) #else return ((1 << 16) | (1 << 18) | (1 << 19) | (1 << 21)); #endif +} + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + /* implement later */ } \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_hc.c b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_hc.c index 9bebe6d..431b5db 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_hc.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_hc.c @@ -24,3 +24,8 @@ uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL; return 0; } + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + /* implement later */ +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_kendryte.c b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_kendryte.c new file mode 100644 index 0000000..de10352 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_kendryte.c @@ -0,0 +1,157 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "usbd_core.h" +#include "usbh_core.h" + +#define DEFAULT_USB_HCLK_FREQ_MHZ 200 + +uint32_t SystemCoreClock = (DEFAULT_USB_HCLK_FREQ_MHZ * 1000 * 1000); +uintptr_t g_usb_otg0_base = (uintptr_t)0x91500000UL; +uintptr_t g_usb_otg1_base = (uintptr_t)0x91540000UL; + +static void sysctl_reset_hw_done(volatile uint32_t *reset_reg, uint8_t reset_bit, uint8_t done_bit) +{ + *reset_reg |= (1 << done_bit); /* clear done bit */ + rt_thread_mdelay(1); + + *reset_reg |= (1 << reset_bit); /* set reset bit */ + rt_thread_mdelay(1); + /* check done bit */ + while (*reset_reg & (1 << done_bit) == 0) + ; +} + +#define USB_IDPULLUP0 (1 << 4) +#define USB_DMPULLDOWN0 (1 << 8) +#define USB_DPPULLDOWN0 (1 << 9) + +#ifdef PKG_CHERRYUSB_HOST +static void usb_hc_interrupt_cb(int irq, void *arg_pv) +{ + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler((uint8_t)(uintptr_t)arg_pv); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + uint32_t *hs_reg; + uint32_t usb_ctl3; + + if (bus->hcd.hcd_id == 0) { + sysctl_reset_hw_done((volatile uint32_t *)0x9110103c, 0, 28); + + hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x7C), 0x1000); + usb_ctl3 = *hs_reg | USB_IDPULLUP0; + + *hs_reg = usb_ctl3 | (USB_DMPULLDOWN0 | USB_DPPULLDOWN0); + + rt_iounmap(hs_reg); + + rt_hw_interrupt_install(173, usb_hc_interrupt_cb, NULL, "usbh0"); + rt_hw_interrupt_umask(173); + + } else { + sysctl_reset_hw_done((volatile uint32_t *)0x9110103c, 1, 29); + + hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x9C), 0x1000); + usb_ctl3 = *hs_reg | USB_IDPULLUP0; + + *hs_reg = usb_ctl3 | (USB_DMPULLDOWN0 | USB_DPPULLDOWN0); + + rt_iounmap(hs_reg); + + rt_hw_interrupt_install(174, usb_hc_interrupt_cb, 1, "usbh1"); + rt_hw_interrupt_umask(174); + } +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + if (bus->hcd.hcd_id == 0) { + rt_hw_interrupt_mask(173); + } else { + rt_hw_interrupt_mask(174); + } +} + +uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) +{ + return 0; +} +#endif + +#ifdef PKG_CHERRYUSB_DEVICE +static void usb_dc_interrupt_cb(int irq, void *arg_pv) +{ + extern void USBD_IRQHandler(uint8_t busid); + USBD_IRQHandler(0); +} + +#ifdef CHERRYUSB_DEVICE_USING_USB0 +void usb_dc_low_level_init(uint8_t busid) +{ + sysctl_reset_hw_done((volatile uint32_t *)0x9110103c, 0, 28); + uint32_t *hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x7C), 0x1000); + *hs_reg = 0x37; + rt_iounmap(hs_reg); + + rt_hw_interrupt_install(173, usb_dc_interrupt_cb, NULL, "usbd"); + rt_hw_interrupt_umask(173); +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + rt_hw_interrupt_mask(173); +} +#else +void usb_dc_low_level_init(uint8_t busid) +{ + sysctl_reset_hw_done((volatile uint32_t *)0x9110103c, 1, 29); + uint32_t *hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x9C), 0x1000); + *hs_reg = 0x37; + rt_iounmap(hs_reg); + + rt_hw_interrupt_install(174, usb_dc_interrupt_cb, NULL, "usbd"); + rt_hw_interrupt_umask(174); +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + rt_hw_interrupt_mask(174); +} +#endif +uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base) +{ + return 0; +} + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + /* implement later */ +} +#endif \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_st.c b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_st.c index 94293d2..4dff31f 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_st.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_glue_st.c @@ -13,9 +13,11 @@ * USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; * USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; * USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; - * + * */ +extern void HAL_Delay(uint32_t Delay); + #if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx) /** * @brief USB_HS_PHY_Registers @@ -164,6 +166,8 @@ uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base) USB_OTG_GLB->GCCFG = (1 << 23); usb_hsphy_init(25000000U); return (1 << 23); /* Enable USB HS PHY USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;*/ +#elif __has_include("stm32h7rsxx.h") + return (1 << 21); #else return 0; #endif @@ -190,6 +194,8 @@ uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) USB_OTG_GLB->GCCFG = (1 << 23); usb_hsphy_init(25000000U); return (1 << 23); /* Enable USB HS PHY USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;*/ +#elif __has_include("stm32h7rsxx.h") + return (1 << 21); #else return 0; #endif @@ -201,3 +207,8 @@ uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) #endif #endif } + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + HAL_Delay(ms); +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c index ddcbaf2..09f5517 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c @@ -26,7 +26,7 @@ * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario */ #ifndef CONFIG_USB_DWC2_RX_FIFO_SIZE -#define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4) +#define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE)) #endif #define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(bus->hcd.reg_base)) @@ -114,12 +114,22 @@ static inline void dwc2_set_mode(struct usbh_bus *bus, uint8_t mode) } else if (mode == USB_OTG_MODE_DEVICE) { USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; } + + usb_osal_msleep(50); } static inline int dwc2_flush_rxfifo(struct usbh_bus *bus) { - volatile uint32_t count = 0; + volatile uint32_t count = 0U; + /* Wait for AHB master IDLE state. */ + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + count = 0; USB_OTG_GLB->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; do { @@ -135,6 +145,14 @@ static inline int dwc2_flush_txfifo(struct usbh_bus *bus, uint32_t num) { volatile uint32_t count = 0U; + /* Wait for AHB master IDLE state. */ + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + count = 0; USB_OTG_GLB->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); do { @@ -197,6 +215,12 @@ static inline void dwc2_chan_char_init(struct usbh_bus *bus, uint8_t ch_num, uin regval |= USB_OTG_HCCHAR_EPDIR; } + if ((usbh_get_port_speed(bus, 0) == USB_SPEED_HIGH) && (speed != USB_SPEED_HIGH)) { + USB_LOG_ERR("Do not support LS/FS device on HS hub\r\n"); + while (1) { + } + } + /* LS device plugged to HUB */ if ((speed == USB_SPEED_LOW) && (usbh_get_port_speed(bus, 0) != USB_SPEED_LOW)) { regval |= USB_OTG_HCCHAR_LSDEV; @@ -424,10 +448,12 @@ static void dwc2_iso_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_u __WEAK void usb_hc_low_level_init(struct usbh_bus *bus) { + (void)bus; } __WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus) { + (void)bus; } int usb_hc_init(struct usbh_bus *bus) @@ -478,9 +504,6 @@ int usb_hc_init(struct usbh_bus *bus) /* Restart the Phy Clock */ USB_OTG_PCGCCTL = 0U; - dwc2_drivebus(bus, 1); - usb_osal_msleep(200); - /* Set default Max speed support */ USB_OTG_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); @@ -504,6 +527,7 @@ int usb_hc_init(struct usbh_bus *bus) ret = dwc2_flush_txfifo(bus, 0x10U); ret = dwc2_flush_rxfifo(bus); + USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_HBSTLEN; USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_4; USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; @@ -511,6 +535,9 @@ int usb_hc_init(struct usbh_bus *bus) USB_OTG_GLB->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | USB_OTG_GINTSTS_DISCINT); + dwc2_drivebus(bus, 1); + usb_osal_msleep(200); + USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_GINT; return ret; @@ -627,6 +654,7 @@ int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, u case HUB_PORT_FEATURE_C_SUSPEND: break; case HUB_PORT_FEATURE_POWER: + dwc2_drivebus(bus, 0); break; case HUB_PORT_FEATURE_C_CONNECTION: g_dwc2_hcd[bus->hcd.hcd_id].port_csc = 0; @@ -652,7 +680,7 @@ int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, u case HUB_PORT_FEATURE_SUSPEND: break; case HUB_PORT_FEATURE_POWER: - USB_OTG_HPRT &= ~USB_OTG_HPRT_PPWR; + dwc2_drivebus(bus, 1); break; case HUB_PORT_FEATURE_RESET: usbh_reset_port(bus, port); @@ -748,8 +776,8 @@ int usbh_submit_urb(struct usbh_urb *urb) } } else { /* Check if intr and iso pipe tx fifo is overflow */ - if (((USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize) == USB_ENDPOINT_TYPE_ISOCHRONOUS) || - (USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize) == USB_ENDPOINT_TYPE_INTERRUPT)) && + if (((USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_ISOCHRONOUS) || + (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT)) && USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize) > (CONFIG_USB_DWC2_PTX_FIFO_SIZE * 4)) { return -USB_ERR_RANGE; } else { @@ -874,6 +902,7 @@ static void dwc2_inchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num) //printf("s1:%08x\r\n", chan_intstatus); if (chan_intstatus & USB_OTG_HCINT_CHH) { + USB_OTG_HC(ch_num)->HCINT = chan_intstatus; if (chan_intstatus & USB_OTG_HCINT_XFRC) { urb->errorcode = 0; @@ -927,7 +956,6 @@ static void dwc2_inchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num) urb->errorcode = -USB_ERR_IO; dwc2_urb_waitup(urb); } - USB_OTG_HC(ch_num)->HCINT = chan_intstatus; } } @@ -944,6 +972,7 @@ static void dwc2_outchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num) //printf("s2:%08x\r\n", chan_intstatus); if (chan_intstatus & USB_OTG_HCINT_CHH) { + USB_OTG_HC(ch_num)->HCINT = chan_intstatus; if (chan_intstatus & USB_OTG_HCINT_XFRC) { urb->errorcode = 0; @@ -1008,7 +1037,6 @@ static void dwc2_outchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num) urb->errorcode = -USB_ERR_IO; dwc2_urb_waitup(urb); } - USB_OTG_HC(ch_num)->HCINT = chan_intstatus; } } diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ehci/README.md b/rt-thread/components/drivers/usb/cherryusb/port/ehci/README.md index 48b9a2b..8160c65 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/ehci/README.md +++ b/rt-thread/components/drivers/usb/cherryusb/port/ehci/README.md @@ -22,6 +22,17 @@ - d13x, d21x +### NXP + +Modify USB_NOCACHE_RAM_SECTION + +``` +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".NonCacheable"))) +``` + +- IMRT10XX/IMRT11XX +- MCXN9XX/MCXN236 + ### Intel - Intel 6 Series Chipset and Intel C200 Series Chipset diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_ehci_priv.h b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_ehci_priv.h deleted file mode 100644 index ba1d351..0000000 --- a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_ehci_priv.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2022, sakumisu - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _USB_EHCI_PRIV_H -#define _USB_EHCI_PRIV_H - -#include "usbh_core.h" -#include "usbh_hub.h" -#include "usb_hc_ehci.h" - -#define EHCI_HCCR ((struct ehci_hccr *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_EHCI_HCCR_OFFSET)) -#define EHCI_HCOR ((struct ehci_hcor *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_EHCI_HCCR_OFFSET + g_ehci_hcd[bus->hcd.hcd_id].hcor_offset)) - -#define EHCI_PTR2ADDR(x) ((uint32_t)(uintptr_t)(x) & ~0x1F) -#define EHCI_ADDR2QH(x) ((struct ehci_qh_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F)) -#define EHCI_ADDR2QTD(x) ((struct ehci_qtd_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F)) -#define EHCI_ADDR2ITD(x) ((struct ehci_itd_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F)) - -#ifndef CONFIG_USB_EHCI_QH_NUM -#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM -#endif -#ifndef CONFIG_USB_EHCI_QTD_NUM -#define CONFIG_USB_EHCI_QTD_NUM 3 -#endif -#ifndef CONFIG_USB_EHCI_ITD_NUM -#define CONFIG_USB_EHCI_ITD_NUM 5 -#endif -#ifndef CONFIG_USB_EHCI_ISO_NUM -#define CONFIG_USB_EHCI_ISO_NUM 4 -#endif - -extern uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port); - -struct ehci_qtd_hw { - struct ehci_qtd hw; - struct usbh_urb *urb; - uint32_t length; -} __attribute__((aligned(32))); - -struct ehci_qh_hw { - struct ehci_qh hw; - struct ehci_qtd_hw qtd_pool[CONFIG_USB_EHCI_QTD_NUM]; - uint32_t first_qtd; - struct usbh_urb *urb; - usb_osal_sem_t waitsem; - uint8_t remove_in_iaad; -} __attribute__((aligned(32))); - -struct ehci_itd_hw { - struct ehci_itd hw; - struct usbh_urb *urb; - uint16_t start_frame; - uint8_t mf_unmask; - uint8_t mf_valid; - uint32_t pkt_idx[8]; -} __attribute__((aligned(32))); - -struct ehci_iso_hw -{ - struct ehci_itd_hw itd_pool[CONFIG_USB_EHCI_ITD_NUM]; - uint32_t itd_num; -}; - -struct ehci_hcd { - bool ehci_qh_used[CONFIG_USB_EHCI_QH_NUM]; - bool ehci_iso_used[CONFIG_USB_EHCI_ISO_NUM]; - bool ppc; /* Port Power Control */ - bool has_tt; /* if use tt instead of Companion Controller */ - uint8_t n_cc; /* Number of Companion Controller */ - uint8_t n_pcc; /* Number of ports supported per companion host controller */ - uint8_t n_ports; - uint8_t hcor_offset; -}; - -extern struct ehci_hcd g_ehci_hcd[CONFIG_USBHOST_MAX_BUS]; -extern uint32_t g_framelist[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(CONFIG_USB_EHCI_FRAME_LIST_SIZE, 1024)]; - -int ehci_iso_urb_init(struct usbh_bus *bus, struct usbh_urb *urb); -void ehci_kill_iso_urb(struct usbh_bus *bus, struct usbh_urb *urb); -void ehci_scan_isochronous_list(struct usbh_bus *bus); - -#endif diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_ehci_reg.h b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_ehci_reg.h new file mode 100644 index 0000000..741eef6 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_ehci_reg.h @@ -0,0 +1,393 @@ +/**************************************************************************** + * include/nuttx/usb/ehci.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ +/* + * Copyright 2022 sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __INCLUDE_NUTTX_USB_EHCI_H +#define __INCLUDE_NUTTX_USB_EHCI_H + +#define EHCI_FULL_SPEED (0) /* Full-Speed (12Mbs) */ +#define EHCI_LOW_SPEED (1) /* Low-Speed (1.5Mbs) */ +#define EHCI_HIGH_SPEED (2) /* High-Speed (480 Mb/s) */ + +/* Host Controller Capability Register Bit Definitions **********************/ + +/* Structural Parameters. Paragraph 2.2.3 */ + +#define EHCI_HCSPARAMS_NPORTS_SHIFT (0) /* Bit 0-3: Number of physical downstream ports */ +#define EHCI_HCSPARAMS_NPORTS_MASK (15 << EHCI_HCSPARAMS_NPORTS_SHIFT) +#define EHCI_HCSPARAMS_PPC (1 << 4) /* Bit 4: Port Power Control */ +#define EHCI_HCSPARAMS_PRR (1 << 7) /* Bit 7: Port Routing Rules */ +#define EHCI_HCSPARAMS_NPCC_SHIFT (8) /* Bit 8-11: Number of Ports per Companion Controller */ +#define EHCI_HCSPARAMS_NPCC_MASK (15 << EHCI_HCSPARAMS_NPCC_SHIFT) +#define EHCI_HCSPARAMS_NCC_SHIFT (12) /* Bit 12-15: Number of Companion Controllers */ +#define EHCI_HCSPARAMS_NCC_MASK (15 << EHCI_HCSPARAMS_NCC_SHIFT) +#define EHCI_HCSPARAMS_PIND (1 << 16) /* Bit 16: Port Indicators */ +#define EHCI_HCSPARAMS_DBGPORT_SHIFT (20) /* Bit 20-23: Debug Port Number */ +#define EHCI_HCSPARAMS_DBGPORT_MASK (15 << EHCI_HCSPARAMS_DBGPORT_SHIFT) + +/* Capability Parameters. Paragraph 2.2.4 */ + +#define EHCI_HCCPARAMS_64BIT (1 << 0) /* Bit 0: 64-bit Addressing Capability */ +#define EHCI_HCCPARAMS_PFLF (1 << 1) /* Bit 1: Programmable Frame List Flag */ +#define EHCI_HCCPARAMS_ASPC (1 << 2) /* Bit 2: Asynchronous Schedule Park Capability */ +#define EHCI_HCCPARAMS_IST_SHIFT (4) /* Bits 4-7: Isochronous Scheduling Threshold */ +#define EHCI_HCCPARAMS_IST_MASK (15 << EHCI_HCCPARAMS_IST_SHIFT) +#define EHCI_HCCPARAMS_EECP_SHIFT (8) /* Bits 8-15: EHCI Extended Capabilities Pointer */ +#define EHCI_HCCPARAMS_EECP_MASK (0xff << EHCI_HCCPARAMS_EECP_SHIFT) + +/* Host Controller Operational Register Bit Definitions *********************/ + +/* USB Command. Paragraph 2.3.1 */ + +#define EHCI_USBCMD_RUN (1 << 0) /* Bit 0: Run/Stop */ +#define EHCI_USBCMD_HCRESET (1 << 1) /* Bit 1: Host Controller Reset */ +#define EHCI_USBCMD_FLSIZE_SHIFT (2) /* Bits 2-3: Frame List Size */ +#define EHCI_USBCMD_FLSIZE_MASK (3 << EHCI_USBCMD_FLSIZE_SHIFT) +#define EHCI_USBCMD_FLSIZE_1024 (0 << EHCI_USBCMD_FLSIZE_SHIFT) /* 1024 elements (4096 bytes) */ +#define EHCI_USBCMD_FLSIZE_512 (1 << EHCI_USBCMD_FLSIZE_SHIFT) /* 512 elements (2048 bytes) */ +#define EHCI_USBCMD_FLSIZE_256 (2 << EHCI_USBCMD_FLSIZE_SHIFT) /* 256 elements (1024 bytes) */ +#define EHCI_USBCMD_PSEN (1 << 4) /* Bit 4: Periodic Schedule Enable */ +#define EHCI_USBCMD_ASEN (1 << 5) /* Bit 5: Asynchronous Schedule Enable */ +#define EHCI_USBCMD_IAAD (1 << 6) /* Bit 6: Interrupt on Async Advance Doorbell */ +#define EHCI_USBCMD_LRESET (1 << 7) /* Bit 7: Light Host Controller Reset */ +#define EHCI_USBCMD_ASYNC_PARKCNT_SHIFT (8) /* Bits 8-9: Asynchronous Schedule Park Mode Count */ +#define EHCI_USBCMD_ASYNC_PARKCNT_MASK (3 << EHCI_USBCMD_ASYNC_PARKCNT_SHIFT) +#define EHCI_USBCMD_ASYNC_PARK (1 << 11) /* Bit 11: Asynchronous Schedule Park Mode Enable */ +#define EHCI_USBCMD_ITHRE_SHIFT (16) /* Bits 16-23: Interrupt Threshold Control */ +#define EHCI_USBCMD_ITHRE_MASK (0xff << EHCI_USBCMD_ITHRE_SHIFT) +#define EHCI_USBCMD_ITHRE_1MF (0x01 << EHCI_USBCMD_ITHRE_SHIFT) /* 1 micro-frame */ +#define EHCI_USBCMD_ITHRE_2MF (0x02 << EHCI_USBCMD_ITHRE_SHIFT) /* 2 micro-frames */ +#define EHCI_USBCMD_ITHRE_4MF (0x04 << EHCI_USBCMD_ITHRE_SHIFT) /* 4 micro-frames */ +#define EHCI_USBCMD_ITHRE_8MF (0x08 << EHCI_USBCMD_ITHRE_SHIFT) /* 8 micro-frames (default, 1 ms) */ +#define EHCI_USBCMD_ITHRE_16MF (0x10 << EHCI_USBCMD_ITHRE_SHIFT) /* 16 micro-frames (2 ms) */ +#define EHCI_USBCMD_ITHRE_32MF (0x20 << EHCI_USBCMD_ITHRE_SHIFT) /* 32 micro-frames (4 ms) */ +#define EHCI_USBCMD_ITHRE_64MF (0x40 << EHCI_USBCMD_ITHRE_SHIFT) /* 64 micro-frames (8 ms) */ + +/* USB Status. Paragraph 2.3.2 */ + +#define EHCI_USBSTS_INT (1 << 0) /* Bit 0: USB Interrupt */ +#define EHCI_USBSTS_ERR (1 << 1) /* Bit 1: USB Error Interrupt */ +#define EHCI_USBSTS_PCD (1 << 2) /* Bit 2: Port Change Detect */ +#define EHCI_USBSTS_FLR (1 << 3) /* Bit 3: Frame List Rollover */ +#define EHCI_USBSTS_FATAL (1 << 4) /* Bit 4: Host System Error */ +#define EHCI_USBSTS_IAA (1 << 5) /* Bit 5: Interrupt on Async Advance */ +#define EHCI_USBSTS_HALTED (1 << 12) /* Bit 12: HC Halted */ +#define EHCI_USBSTS_RECLAM (1 << 13) /* Bit 13: Reclamation */ +#define EHCI_USBSTS_PSS (1 << 14) /* Bit 14: Periodic Schedule Status */ +#define EHCI_USBSTS_ASS (1 << 15) /* Bit 15: Asynchronous Schedule Status */ + /* Bits 16-31: Reserved */ + +/* USB Interrupt Enable. Paragraph 2.3.3 */ + +#define EHCI_USBIE_INT (1 << 0) /* Bit 0: USB Interrupt */ +#define EHCI_USBIE_ERR (1 << 1) /* Bit 1: USB Error Interrupt */ +#define EHCI_USBIE_PCD (1 << 2) /* Bit 2: Port Change Detect */ +#define EHCI_USBIE_FLROLL (1 << 3) /* Bit 3: Frame List Rollover */ +#define EHCI_USBIE_FATAL (1 << 4) /* Bit 4: Host System Error */ +#define EHCI_USBIE_IAA (1 << 5) /* Bit 5: Interrupt on Async Advance */ +#define EHCI_USBIE_ALLINTS (0x3f) /* Bits 0-5: All interrupts */ + +/* USB Frame Index. Paragraph 2.3.4 */ + +#define EHCI_FRINDEX_MASK (0x3fff) /* Bits 0-13: Frame index */ + +/* 4G Segment Selector. + * Paragraph 2.3.5, Bits[64:32] of data structure addresses + */ + +/* Frame List Base Address. Paragraph 2.3.6 */ +#define EHCI_PERIODICLISTBASE_MASK (0xfffff000) /* Bits 12-31: Base Address (Low) */ + +/* Next Asynchronous List Address. Paragraph 2.3.7 */ + +#define EHCI_ASYNCLISTADDR_MASK (0xffffffe0) /* Bits 5-31: Link Pointer Low (LPL) */ + +/* Configured Flag Register. Paragraph 2.3.8 */ + +#define EHCI_CONFIGFLAG (1 << 0) /* Bit 0: Configure Flag */ + +/* Port Status/Control, Port 1-n. Paragraph 2.3.9 */ + +#define EHCI_PORTSC_CCS (1 << 0) /* Bit 0: Current Connect Status */ +#define EHCI_PORTSC_CSC (1 << 1) /* Bit 1: Connect Status Change */ +#define EHCI_PORTSC_PE (1 << 2) /* Bit 2: Port Enable */ +#define EHCI_PORTSC_PEC (1 << 3) /* Bit 3: Port Enable/Disable Change */ +#define EHCI_PORTSC_OCA (1 << 4) /* Bit 4: Over-current Active */ +#define EHCI_PORTSC_OCC (1 << 5) /* Bit 5: Over-current Change */ +#define EHCI_PORTSC_RESUME (1 << 6) /* Bit 6: Force Port Resume */ +#define EHCI_PORTSC_SUSPEND (1 << 7) /* Bit 7: Suspend */ +#define EHCI_PORTSC_RESET (1 << 8) /* Bit 8: Port Reset */ +#define EHCI_PORTSC_LSTATUS_SHIFT (10) /* Bits 10-11: Line Status */ +#define EHCI_PORTSC_LSTATUS_MASK (3 << EHCI_PORTSC_LSTATUS_SHIFT) +#define EHCI_PORTSC_LSTATUS_SE0 (0 << EHCI_PORTSC_LSTATUS_SHIFT) /* SE0 Not Low-speed device, perform EHCI reset */ +#define EHCI_PORTSC_LSTATUS_KSTATE (1 << EHCI_PORTSC_LSTATUS_SHIFT) /* K-state Low-speed device, release ownership of port */ +#define EHCI_PORTSC_LSTATUS_JSTATE (2 << EHCI_PORTSC_LSTATUS_SHIFT) /* J-state Not Low-speed device, perform EHCI reset */ +#define EHCI_PORTSC_PP (1 << 12) /* Bit 12: Port Power */ +#define EHCI_PORTSC_OWNER (1 << 13) /* Bit 13: Port Owner */ +#define EHCI_PORTSC_PIC_SHIFT (14) /* Bits 14-15: Port Indicator Control */ +#define EHCI_PORTSC_PIC_MASK (3 << EHCI_PORTSC_PIC_SHIFT) +#define EHCI_PORTSC_PIC_OFF (0 << EHCI_PORTSC_PIC_SHIFT) /* Port indicators are off */ +#define EHCI_PORTSC_PIC_AMBER (1 << EHCI_PORTSC_PIC_SHIFT) /* Amber */ +#define EHCI_PORTSC_PIC_GREEN (2 << EHCI_PORTSC_PIC_SHIFT) /* Green */ +#define EHCI_PORTSC_PTC_SHIFT (16) /* Bits 16-19: Port Test Control */ +#define EHCI_PORTSC_PTC_MASK (15 << EHCI_PORTSC_PTC_SHIFT) +#define EHCI_PORTSC_PTC_DISABLED (0 << EHCI_PORTSC_PTC_SHIFT) /* Test mode not enabled */ +#define EHCI_PORTSC_PTC_JSTATE (1 << EHCI_PORTSC_PTC_SHIFT) /* Test J_STATE */ +#define EHCI_PORTSC_PTC_KSTATE (2 << EHCI_PORTSC_PTC_SHIFT) /* Test K_STATE */ +#define EHCI_PORTSC_PTC_SE0NAK (3 << EHCI_PORTSC_PTC_SHIFT) /* Test SE0_NAK */ +#define EHCI_PORTSC_PTC_PACKET (4 << EHCI_PORTSC_PTC_SHIFT) /* Test Packet */ +#define EHCI_PORTSC_PTC_ENABLE (5 << EHCI_PORTSC_PTC_SHIFT) /* Test FORCE_ENABLE */ +#define EHCI_PORTSC_WKCCNTE (1 << 20) /* Bit 20: Wake on Connect Enable */ +#define EHCI_PORTSC_WKDSCNNTE (1 << 21) /* Bit 21: Wake on Disconnect Enable */ +#define EHCI_PORTSC_WKOCE (1 << 22) /* Bit 22: Wake on Over-current Enable */ + /* Bits 23-31: Reserved */ + +#define EHCI_PORTSC_ALLINTS (EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | \ + EHCI_PORTSC_OCC | EHCI_PORTSC_RESUME) + +/* Queue Head. Paragraph 3.6 */ + +/* Queue Head Horizontal Link Pointer: Queue Head DWord 0. Table 3-19 */ + +#define QH_HLP_END 0x1 + +#define QH_HLP_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0) /* Isochronous Transfer Descriptor */ +#define QH_HLP_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2) /* Queue Head */ +#define QH_HLP_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4) /* Split Transaction Isochronous Transfer Descriptor */ +#define QH_HLP_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6) /* Frame Span Traversal Node */ + +/* Endpoint Characteristics: Queue Head DWord 1. Table 3-19 */ + +#define QH_EPCHAR_DEVADDR_SHIFT (0) /* Bitx 0-6: Device Address */ +#define QH_EPCHAR_DEVADDR_MASK (0x7f << QH_EPCHAR_DEVADDR_SHIFT) +#define QH_EPCHAR_I (1 << 7) /* Bit 7: Inactivate on Next Transaction */ +#define QH_EPCHAR_ENDPT_SHIFT (8) /* Bitx 8-11: Endpoint Number */ +#define QH_EPCHAR_ENDPT_MASK (15 << QH_EPCHAR_ENDPT_SHIFT) +#define QH_EPCHAR_EPS_SHIFT (12) /* Bitx 12-13: Endpoint Speed */ +#define QH_EPCHAR_EPS_MASK (3 << QH_EPCHAR_EPS_SHIFT) +#define QH_EPCHAR_EPS_FULL (0 << QH_EPCHAR_EPS_SHIFT) /* Full-Speed (12Mbs) */ +#define QH_EPCHAR_EPS_LOW (1 << QH_EPCHAR_EPS_SHIFT) /* Low-Speed (1.5Mbs) */ +#define QH_EPCHAR_EPS_HIGH (2 << QH_EPCHAR_EPS_SHIFT) /* High-Speed (480 Mb/s) */ +#define QH_EPCHAR_DTC (1 << 14) /* Bit 14: Data Toggle Control */ +#define QH_EPCHAR_H (1 << 15) /* Bit 15: Head of Reclamation List Flag */ +#define QH_EPCHAR_MAXPKT_SHIFT (16) /* Bitx 16-26: Maximum Packet Length */ +#define QH_EPCHAR_MAXPKT_MASK (0x7ff << QH_EPCHAR_MAXPKT_SHIFT) +#define QH_EPCHAR_C (1 << 27) /* Bit 27: Control Endpoint Flag */ +#define QH_EPCHAR_RL_SHIFT (28) /* Bitx 28-31: Nak Count Reload */ +#define QH_EPCHAR_RL_MASK (15 << QH_EPCHAR_RL_SHIFT) + +/* Endpoint Capabilities: Queue Head DWord 2. Table 3-20 */ + +#define QH_EPCAPS_SSMASK_SHIFT (0) /* Bitx 0-7: Interrupt Schedule Mask (Frame S-mask) */ +#define QH_EPCAPS_SSMASK_MASK (0xff << QH_EPCAPS_SSMASK_SHIFT) +#define QH_EPCAPS_SSMASK(n) ((n) << QH_EPCAPS_SSMASK_SHIFT) +#define QH_EPCAPS_SCMASK_SHIFT (8) /* Bitx 8-15: Split Completion Mask (Frame C-Mask) */ +#define QH_EPCAPS_SCMASK_MASK (0xff << QH_EPCAPS_SCMASK_SHIFT) +#define QH_EPCAPS_SCMASK(n) ((n) << QH_EPCAPS_SCMASK_SHIFT) +#define QH_EPCAPS_HUBADDR_SHIFT (16) /* Bitx 16-22: Hub Address */ +#define QH_EPCAPS_HUBADDR_MASK (0x7f << QH_EPCAPS_HUBADDR_SHIFT) +#define QH_EPCAPS_HUBADDR(n) ((n) << QH_EPCAPS_HUBADDR_SHIFT) +#define QH_EPCAPS_PORT_SHIFT (23) /* Bit 23-29: Port Number */ +#define QH_EPCAPS_PORT_MASK (0x7f << QH_EPCAPS_PORT_SHIFT) +#define QH_EPCAPS_PORT(n) ((n) << QH_EPCAPS_PORT_SHIFT) +#define QH_EPCAPS_MULT_SHIFT (30) /* Bit 30-31: High-Bandwidth Pipe Multiplier */ +#define QH_EPCAPS_MULT_MASK (3 << QH_EPCAPS_MULT_SHIFT) +#define QH_EPCAPS_MULT(n) ((n) << QH_EPCAPS_MULT_SHIFT) + +/* qTD Token. Paragraph 3.5.3 */ + +#define QTD_LIST_END 1 + +#define QTD_TOKEN_STATUS_SHIFT (0) /* Bits 0-7: Status */ +#define QTD_TOKEN_STATUS_MASK (0xff << QTD_TOKEN_STATUS_SHIFT) +#define QTD_TOKEN_STATUS_PINGSTATE (1 << 0) /* Bit 0 Ping State */ +#define QTD_TOKEN_STATUS_ERR (1 << 0) /* Bit 0 Error */ +#define QTD_TOKEN_STATUS_SPLITXSTATE (1 << 1) /* Bit 1 Split Transaction State */ +#define QTD_TOKEN_STATUS_MMF (1 << 2) /* Bit 2 Missed Micro-Frame */ +#define QTD_TOKEN_STATUS_XACTERR (1 << 3) /* Bit 3 Transaction Error */ +#define QTD_TOKEN_STATUS_BABBLE (1 << 4) /* Bit 4 Babble Detected */ +#define QTD_TOKEN_STATUS_DBERR (1 << 5) /* Bit 5 Data Buffer Error */ +#define QTD_TOKEN_STATUS_HALTED (1 << 6) /* Bit 6 Halted */ +#define QTD_TOKEN_STATUS_ACTIVE (1 << 7) /* Bit 7 Active */ +#define QTD_TOKEN_STATUS_ERRORS (0x78 << QTD_TOKEN_STATUS_SHIFT) +#define QTD_TOKEN_PID_SHIFT (8) /* Bits 8-9: PID Code */ +#define QTD_TOKEN_PID_MASK (3 << QTD_TOKEN_PID_SHIFT) +#define QTD_TOKEN_PID_OUT (0 << QTD_TOKEN_PID_SHIFT) /* OUT Token generates token (E1H) */ +#define QTD_TOKEN_PID_IN (1 << QTD_TOKEN_PID_SHIFT) /* IN Token generates token (69H) */ +#define QTD_TOKEN_PID_SETUP (2 << QTD_TOKEN_PID_SHIFT) /* SETUP Token generates token (2DH) */ +#define QTD_TOKEN_CERR_SHIFT (10) /* Bits 10-11: Error Counter */ +#define QTD_TOKEN_CERR_MASK (3 << QTD_TOKEN_CERR_SHIFT) +#define QTD_TOKEN_CPAGE_SHIFT (12) /* Bits 12-14: Current Page */ +#define QTD_TOKEN_CPAGE_MASK (7 << QTD_TOKEN_CPAGE_SHIFT) +#define QTD_TOKEN_IOC (1 << 15) /* Bit 15: Interrupt On Complete */ +#define QTD_TOKEN_NBYTES_SHIFT (16) /* Bits 16-30: Total Bytes to Transfer */ +#define QTD_TOKEN_NBYTES_MASK (0x7fff << QTD_TOKEN_NBYTES_SHIFT) +#define QTD_TOKEN_TOGGLE (1 << 31) /* Bit 31: Data Toggle */ + +/* Isochronous (High-Speed) Transfer Descriptor (iTD). Paragraph 3.3 */ + +/* iTD Next Link Pointer. Paragraph 3.3.1 */ + +#define ITD_NLP_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0) +#define ITD_NLP_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2) +#define ITD_NLP_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4) +#define ITD_NLP_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6) + +/* iTD Transaction Status and Control List. Paragraph 3.3.2 */ +#define ITD_TSCL_XOFFS_SHIFT (0) /* Bits 0-11: Transaction X offset */ +#define ITD_TSCL_XOFFS_MASK (0xfff << ITD_TSCL_XOFFS_SHIFT) +#define ITD_TSCL_PG_SHIFT (12) /* Bits 12-14: Page select */ +#define ITD_TSCL_PG_MASK (7 << ITD_TSCL_PG_SHIFT) +#define ITD_TSCL_IOC (1 << 15) /* Bit 15: Interrupt On Comp */ +#define ITD_TSCL_LENGTH_SHIFT (16) /* Bits 16-27: Transaction length */ +#define ITD_TSCL_LENGTH_MASK (0xfff << ITD_TSCL_LENGTH_SHIFT) +#define ITD_TSCL_STATUS_SHIFT (28) /* Bits 28-31: Transaction status */ +#define ITD_TSCL_STATUS_MASK (15 << ITD_TSCL_STATUS_SHIFT) +#define ITD_TSCL_STATUS_XACTERR (1 << 28) /* Bit 28: Transaction error */ +#define ITD_TSCL_STATUS_BABBLE (1 << 29) /* Bit 29: Babble Detected */ +#define ITD_TSCL_STATUS_DBERROR (1 << 30) /* Bit 30: Data Buffer Error */ +#define ITD_TSCL_STATUS_ACTIVE (1 << 31) /* Bit 31: Active error */ + +/* iTD Buffer Page Pointer List. Paragraph 3.3.4 */ + +/* iTD Buffer Pointer Page 0. Table 3-4 */ + +#define ITD_BUFPTR0_DEVADDR_SHIFT (0) /* Bits 0-6: Device Address */ +#define ITD_BUFPTR0_DEVADDR_MASK (0x7f << ITD_BUFPTR0_DEVADDR_SHIFT) +#define ITD_BUFPTR0_ENDPT_SHIFT (8) /* Bits 8-11: Endpoint Number */ +#define ITD_BUFPTR0_ENDPT_MASK (15 << ITD_BUFPTR0_ENDPT_SHIFT) + +/* iTD Buffer Pointer Page 1. Table 3-5 */ + +#define ITD_BUFPTR1_MAXPKT_SHIFT (0) /* Bits 0-10: Maximum Packet Size */ +#define ITD_BUFPTR1_MAXPKT_MASK (0x7ff << ITD_BUFPTR1_MAXPKT_SHIFT) +#define ITD_BUFPTR1_DIRIN (1 << 11) /* Bit 11: Direction 1=IN */ +#define ITD_BUFPTR1_DIROUT (0) /* Bit 11: Direction 0=OUT */ + +/* iTD Buffer Pointer Page 2. Table 3-6 */ + +#define ITD_BUFPTR2_MULTI_SHIFT (0) /* Bits 0-1: Multi */ +#define ITD_BUFPTR2_MULTI_MASK (3 << ITD_BUFPTR2_MULTI_SHIFT) +#define ITD_BUFPTR2_MULTI_1 (1 << ITD_BUFPTR2_MULTI_SHIFT) /* One transaction per micro-frame */ +#define ITD_BUFPTR2_MULTI_2 (2 << ITD_BUFPTR2_MULTI_SHIFT) /* Two transactions per micro-frame */ +#define ITD_BUFPTR2_MULTI_3 (3 << ITD_BUFPTR2_MULTI_SHIFT) /* Three transactions per micro-frame */ + +/* Registers ****************************************************************/ + +/* Host Controller Capability Registers. + * This register block must be positioned at a well known address. + */ + +struct ehci_hccr { + volatile uint8_t caplength; /* 0x00: Capability Register Length */ + volatile uint8_t reserved; /* 0x01: reserved */ + volatile uint16_t hciversion; /* 0x02: Interface Version Number */ + volatile uint32_t hcsparams; /* 0x04: Structural Parameters */ + volatile uint32_t hccparams; /* 0x08: Capability Parameters */ + volatile uint8_t hcspportroute[8]; /* 0x0c: Companion Port Route Description */ +}; + +/* Host Controller Operational Registers. + * This register block is positioned at an offset of 'caplength' from the + * beginning of the Host Controller Capability Registers. + */ + +struct ehci_hcor { + volatile uint32_t usbcmd; /* 0x00: USB Command */ + volatile uint32_t usbsts; /* 0x04: USB Status */ + volatile uint32_t usbintr; /* 0x08: USB Interrupt Enable */ + volatile uint32_t frindex; /* 0x0c: USB Frame Index */ + volatile uint32_t ctrldssegment; /* 0x10: 4G Segment Selector */ + volatile uint32_t periodiclistbase; /* 0x14: Frame List Base Address */ + volatile uint32_t asynclistaddr; /* 0x18: Next Asynchronous List Address */ +#ifndef CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE + uint32_t reserved[9]; +#endif + volatile uint32_t configflag; /* 0x40: Configured Flag Register */ + volatile uint32_t portsc[15]; /* 0x44: Port Status/Control */ +}; + +/* USB2 Debug Port Register Interface. + * This register block is normally found via the PCI capabalities. + * In non-PCI implementions, you need apriori information about the + * location of these registers. + */ + +struct ehci_debug { + uint32_t psc; /* 0x00: Debug Port Control/Status Register */ + uint32_t pids; /* 0x04: Debug USB PIDs Register */ + uint32_t data[2]; /* 0x08: Debug Data buffer Registers */ + uint32_t addr; /* 0x10: Device Address Register */ +}; + +/* Data Structures **********************************************************/ + +/* Queue Element Transfer Descriptor (qTD). Paragraph 3.5 */ + +struct ehci_qtd { + uint32_t next_qtd; /* 0x00-0x03: Next qTD Pointer */ + uint32_t alt_next_qtd; /* 0x04-0x07: Alternate Next qTD Pointer */ + uint32_t token; /* 0x08-0x0b: qTD Token */ + uint32_t bpl[5]; /* 0x0c-0x1c: Buffer Page Pointer List */ +}; + +#define SIZEOF_EHCI_QTD (32) /* 8*sizeof(uint32_t) */ + +/* Queue Head. Paragraph 3.6 */ + +struct ehci_qh { + uint32_t hlp; /* 0x00-0x03: Queue Head Horizontal Link Pointer */ + uint32_t epchar; /* 0x04-0x07: Endpoint Characteristics */ + uint32_t epcap; /* 0x08-0x0b: Endpoint Capabilities */ + uint32_t curr_qtd; /* 0x0c-0x0f: Current qTD Pointer */ + struct ehci_qtd overlay; /* 0x10-0x2c: Transfer overlay */ +}; + +#define SIZEOF_EHCI_QH (48) /* 4*sizeof(uint32_t) + 32 */ + +/* Isochronous (High-Speed) Transfer Descriptor (iTD). + * Paragraph 3.3. Must be aligned to 32-byte boundaries. + */ + +struct ehci_itd { + uint32_t nlp; /* 0x00-0x03: Next link pointer */ + uint32_t tscl[8]; /* 0x04-0x23: Transaction Status and Control List */ + uint32_t bpl[7]; /* 0x24-0x3c: Buffer Page Pointer List */ +}; + +#define SIZEOF_EHCI_ITD (64) /* 16*sizeof(uint32_t) */ + +/* Split Transaction Isochronous Transfer Descriptor (siTD). Paragraph 3.4 */ + +struct ehci_sitd { + uint32_t nlp; /* 0x00-0x03: Next link pointer */ + uint32_t epchar; /* 0x04-0x07: Endpoint and Transaction Translator Characteristics */ + uint32_t mfsc; /* 0x08-0x0b: Micro-frame Schedule Control */ + uint32_t tsc; /* 0x0c-0x0f: Transfer Status and Control */ + uint32_t bpl[2]; /* 0x10-0x17: Buffer Pointer List */ + uint32_t blp; /* 0x18-0x1b: Back link pointer */ +}; + +#define SIZEOF_EHCI_SITD (28) /* 7*sizeof(uint32_t) */ + +#endif /* __INCLUDE_NUTTX_USB_EHCI_H */ diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_aic.c b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_aic.c index 5445b53..500bc02 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_aic.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_aic.c @@ -8,7 +8,20 @@ #include #include #include "usbh_core.h" -#include "usb_ehci_priv.h" +#include "usb_hc_ehci.h" +#include "usb_hc_ohci.h" + +#if !defined(CONFIG_USB_EHCI_CONFIGFLAG) +#error "aic ehci must define CONFIG_USB_EHCI_CONFIGFLAG" +#endif + +#if !defined(CONFIG_USB_EHCI_WITH_OHCI) +#error "aic must define CONFIG_USB_EHCI_WITH_OHCI for ls/fs device" +#endif + +#if CONFIG_USB_OHCI_HCOR_OFFSET != 0x400 +#error "aic CONFIG_USB_OHCI_HCOR_OFFSET must be 0x400" +#endif extern void USBH_IRQHandler(uint8_t busid); @@ -117,21 +130,12 @@ void usb_hc_low_level_init(struct usbh_bus *bus) aicos_request_irq(config[i].irq_num + 1, (irq_handler_t)aic_ohci_isr, 0, "usb_host_ohci", bus); aicos_irq_enable(config[i].irq_num); + aicos_irq_enable(config[i].irq_num + 1); } uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) { - /* Defined by individual manufacturers */ - uint32_t regval; - - regval = EHCI_HCOR->portsc[port-1]; - if ((regval & EHCI_PORTSC_LSTATUS_MASK) == EHCI_PORTSC_LSTATUS_KSTATE) - return USB_SPEED_LOW; - - if (regval & EHCI_PORTSC_PE) - return USB_SPEED_HIGH; - else - return USB_SPEED_FULL; + return USB_SPEED_HIGH; } void usb_ehci_dcache_clean(uintptr_t addr, uint32_t len) @@ -149,7 +153,7 @@ void usb_ehci_dcache_clean_invalidate(uintptr_t addr, uint32_t len) aicos_dcache_clean_invalid_range((size_t *)addr, len); } -int usbh_init(void) +int __usbh_init(void) { #if defined(AIC_USING_USB0_HOST) || defined(AIC_USING_USB1_HOST) int bus_id = 0; @@ -171,11 +175,5 @@ int usbh_init(void) #include #include -INIT_ENV_EXPORT(usbh_init); - -#if defined (RT_USING_FINSH) -#include - -MSH_CMD_EXPORT_ALIAS(lsusb, lsusb, list usb device); -#endif +INIT_ENV_EXPORT(__usbh_init); #endif \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_hpm.c b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_hpm.c index f616f2c..40105a9 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_hpm.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_hpm.c @@ -35,6 +35,11 @@ static void usb_host_mode_init(USB_Type *ptr) /* Set parallel transceiver width */ ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; +#ifdef CONFIG_USB_HOST_FORCE_FULL_SPEED + /* Set usb forced to full speed mode */ + ptr->PORTSC1 |= USB_PORTSC1_PFSC_MASK; +#endif + /* Not use interrupt threshold. */ ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; } @@ -53,7 +58,7 @@ void usb_hc_low_level_init(struct usbh_bus *bus) #endif } - usb_phy_init((USB_Type *)(bus->hcd.reg_base)); + usb_phy_init((USB_Type *)(bus->hcd.reg_base), true); intc_m_enable_irq(_hcd_irqnum[bus->hcd.hcd_id]); } @@ -82,18 +87,22 @@ uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) return 0; } +#if !defined(USBH_USE_CUSTOM_ISR) || !USBH_USE_CUSTOM_ISR + extern void USBH_IRQHandler(uint8_t busid); +SDK_DECLARE_EXT_ISR_M(IRQn_USB0, isr_usbh0) void isr_usbh0(void) { USBH_IRQHandler(_hcd_busid[0]); } -SDK_DECLARE_EXT_ISR_M(IRQn_USB0, isr_usbh0) #ifdef HPM_USB1_BASE +SDK_DECLARE_EXT_ISR_M(IRQn_USB1, isr_usbh1) void isr_usbh1(void) { USBH_IRQHandler(_hcd_busid[1]); } -SDK_DECLARE_EXT_ISR_M(IRQn_USB1, isr_usbh1) +#endif + #endif diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_ma35d0.c b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_ma35d0.c index 76e621e..3e03bbd 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_ma35d0.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_ma35d0.c @@ -57,7 +57,7 @@ void usb_hc_low_level_init(struct usbh_bus *bus) SYS->MISCFCR0 &= ~SYS_MISCFCR0_UHOVRCURH_Msk; while (1) { rt_thread_mdelay(1); - if ((SYS->USBPMISCR & SYS_USBPMISCR_PHY0HSTCKSTB_Msk) &&) + if (SYS->USBPMISCR & SYS_USBPMISCR_PHY0HSTCKSTB_Msk) break; /* both USB PHY0 and PHY1 clock 60MHz UTMI clock stable */ timeout--; @@ -88,7 +88,7 @@ void usb_hc_low_level_init(struct usbh_bus *bus) SYS->MISCFCR0 &= ~SYS_MISCFCR0_UHOVRCURH_Msk; while (1) { rt_thread_mdelay(1); - if ((SYS->USBPMISCR & SYS_USBPMISCR_PHY1HSTCKSTB_Msk)) + if (SYS->USBPMISCR & SYS_USBPMISCR_PHY1HSTCKSTB_Msk) break; /* both USB PHY0 and PHY1 clock 60MHz UTMI clock stable */ timeout--; diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_mcx.c b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_mcx.c new file mode 100644 index 0000000..92b2c25 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_glue_mcx.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "fsl_common.h" +#include "usb_chipidea_reg.h" + +#define USB_DEVICE_CONFIG_EHCI 1 + +/*! @brief USB controller ID */ +typedef enum _usb_controller_index +{ + kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */ + kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved + to be used in the future. */ + kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */ + kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U */ +} usb_controller_index_t; + +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x04U) +#define BOARD_USB_PHY_TXCAL45DP (0x07U) +#define BOARD_USB_PHY_TXCAL45DM (0x07U) +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#if !defined(CONFIG_USB_EHCI_NXP) +#error "mcx ehci must config CONFIG_USB_EHCI_NXP" +#endif + +#if !defined(CONFIG_USB_EHCI_HCCR_OFFSET) || CONFIG_USB_EHCI_HCCR_OFFSET != 0x100 +#error "mcx ehci must config CONFIG_USB_EHCI_HCCR_OFFSET to 0x100" +#endif + +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) +#include "usb_phy.h" +#endif + +#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) +void USB1_HS_IRQHandler(void) +{ + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler(0); +} +#endif + +void USB_ClockInit(void) +{ +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; +#endif +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) + SPC0->ACTIVE_VDELAY = 0x0500; + /* Change the power DCDC to 1.8v (By deafult, DCDC is 1.8V), CORELDO to 1.1v (By deafult, CORELDO is 1.0V) */ + SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK; + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) | + SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u); + /* Wait until it is done */ + while (SPC0->SC & SPC_SC_BUSY_MASK) + ; + if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) { + SCG0->TRIM_LOCK = 0x5a5a0001U; + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + /* wait LDO ready */ + while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK)) + ; + } + SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK; + SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK); + /* xtal = 20 ~ 30MHz */ + SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT); + SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK; + while (1) { + if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) { + break; + } + } + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK; + CLOCK_EnableClock(kCLOCK_UsbHs); + CLOCK_EnableClock(kCLOCK_UsbHsPhy); + CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, 24000000U); + CLOCK_EnableUsbhsClock(); + USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &phyConfig); +#endif +#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0U) + CLOCK_AttachClk(kCLK_48M_to_USB0); + CLOCK_EnableClock(kCLOCK_Usb0Ram); + CLOCK_EnableClock(kCLOCK_Usb0Fs); + CLOCK_EnableUsbfsClock(); +#endif +} + +static void usb_host_mode_init(CHIPIDEA_TypeDef *ptr) +{ + /* Set mode to host, must be set immediately after reset */ + ptr->USBMODE &= ~USB_USBMODE_CM_MASK; + ptr->USBMODE |= USB_USBMODE_CM_SET(3); + + /* Set the endian */ + ptr->USBMODE &= ~USB_USBMODE_ES_MASK; + + /* Set parallel interface signal */ + ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; + + /* Set parallel transceiver width */ + ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; + + /* Not use interrupt threshold. */ + ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + USB_ClockInit(); + /* Install isr, set priority, and enable IRQ. */ + NVIC_SetPriority((IRQn_Type)USB1_HS_IRQn, 3); + EnableIRQ((IRQn_Type)USB1_HS_IRQn); +} + +void usb_hc_low_level2_init(struct usbh_bus *bus) +{ + usb_host_mode_init((CHIPIDEA_TypeDef *)(bus->hcd.reg_base)); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + DisableIRQ((IRQn_Type)USB1_HS_IRQn); +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + (void)port; + uint8_t speed; + + CHIPIDEA_TypeDef *ptr = (CHIPIDEA_TypeDef *)bus->hcd.reg_base; + + speed = USB_PORTSC1_PSPD_GET(ptr->PORTSC1); + + if (speed == 0x00) { + return USB_SPEED_FULL; + } + if (speed == 0x01) { + return USB_SPEED_LOW; + } + if (speed == 0x02) { + USB_EhcihostPhyDisconnectDetectCmd(kUSB_ControllerEhci0, 1); + return USB_SPEED_HIGH; + } + + return 0; +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.c b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.c index d837012..4f61854 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.c @@ -3,9 +3,9 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include "usb_ehci_priv.h" +#include "usb_hc_ehci.h" #ifdef CONFIG_USB_EHCI_WITH_OHCI -#include "usb_ohci_priv.h" +#include "usb_hc_ohci.h" #endif #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ @@ -167,6 +167,7 @@ static void ehci_qh_fill(struct ehci_qh_hw *qh, switch (speed) { case USB_SPEED_LOW: epchar |= QH_EPCHAR_EPS_LOW; + __attribute__((fallthrough)); case USB_SPEED_FULL: if (ep_type == USB_ENDPOINT_TYPE_CONTROL) { epchar |= QH_EPCHAR_C; /* for TT */ @@ -379,7 +380,7 @@ static struct ehci_qh_hw *ehci_bulk_urb_init(struct usbh_bus *bus, struct usbh_u urb->hport->parent->hub_addr, urb->hport->port); - while (buflen >= 0) { + while (1) { qtd = &qh->qtd_pool[qtd_num]; if (buflen > 0x4000) { @@ -480,7 +481,7 @@ static struct ehci_qh_hw *ehci_intr_urb_init(struct usbh_bus *bus, struct usbh_u urb->hport->parent->hub_addr, urb->hport->port); - while (buflen >= 0) { + while (1) { qtd = &qh->qtd_pool[qtd_num]; if (buflen > 0x4000) { @@ -583,6 +584,8 @@ static void ehci_qh_scan_qtds(struct usbh_bus *bus, struct ehci_qh_hw *qhead, st { struct ehci_qtd_hw *qtd; + (void)bus; + ehci_qh_remove(qhead, qh); qtd = EHCI_ADDR2QTD(qh->first_qtd); @@ -655,6 +658,8 @@ static void ehci_kill_qh(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct { struct ehci_qtd_hw *qtd; + (void)bus; + ehci_qh_remove(qhead, qh); qtd = EHCI_ADDR2QTD(qh->first_qtd); @@ -697,14 +702,17 @@ static int usbh_reset_port(struct usbh_bus *bus, const uint8_t port) __WEAK void usb_hc_low_level_init(struct usbh_bus *bus) { + (void)bus; } __WEAK void usb_hc_low_level2_init(struct usbh_bus *bus) { + (void)bus; } __WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus) { + (void)bus; } int usb_hc_init(struct usbh_bus *bus) @@ -777,6 +785,8 @@ int usb_hc_init(struct usbh_bus *bus) g_ehci_hcd[bus->hcd.hcd_id].n_cc, g_ehci_hcd[bus->hcd.hcd_id].n_pcc); + EHCI_HCOR->usbcmd &= ~EHCI_USBCMD_RUN; + usb_osal_msleep(2); EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET; while (EHCI_HCOR->usbcmd & EHCI_USBCMD_HCRESET) { usb_osal_msleep(1); @@ -830,6 +840,7 @@ int usb_hc_init(struct usbh_bus *bus) for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) { regval = EHCI_HCOR->portsc[port]; regval |= EHCI_PORTSC_PP; + regval &= ~(EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | EHCI_PORTSC_OCC); EHCI_HCOR->portsc[port] = regval; } } @@ -872,7 +883,7 @@ int usb_hc_deinit(struct usbh_bus *bus) regval &= ~EHCI_USBCMD_RUN; EHCI_HCOR->usbcmd = regval; - while ((EHCI_HCOR->usbsts & (EHCI_USBSTS_PSS | EHCI_USBSTS_ASS))) { + while ((EHCI_HCOR->usbsts & (EHCI_USBSTS_PSS | EHCI_USBSTS_ASS)) || ((EHCI_HCOR->usbsts & EHCI_USBSTS_HALTED) == 0)) { usb_osal_msleep(1); timeout++; if (timeout > 100) { @@ -893,6 +904,7 @@ int usb_hc_deinit(struct usbh_bus *bus) #endif EHCI_HCOR->usbsts = EHCI_HCOR->usbsts; + EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET; for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) { qh = &ehci_qh_pool[bus->hcd.hcd_id][index]; @@ -940,6 +952,7 @@ int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, u while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) { } + USB_LOG_INFO("Switch port %u to OHCI\r\n", port); return ohci_roothub_control(bus, setup, buf); } #endif @@ -1051,7 +1064,9 @@ int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, u while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) { } - return ohci_roothub_control(bus, setup, buf); + + USB_LOG_INFO("Switch port %u to OHCI\r\n", port); + return -USB_ERR_NOTSUPP; } #endif break; @@ -1098,7 +1113,7 @@ int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, u if (temp & EHCI_PORTSC_RESET) { status |= (1 << HUB_PORT_FEATURE_RESET); } - if (temp & EHCI_PORTSC_PP) { + if (temp & EHCI_PORTSC_PP || !(EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_PPC)) { status |= (1 << HUB_PORT_FEATURE_POWER); } memcpy(buf, &status, 4); @@ -1341,6 +1356,11 @@ void USBH_IRQHandler(uint8_t busid) if (portsc & EHCI_PORTSC_CSC) { if ((portsc & EHCI_PORTSC_CCS) == EHCI_PORTSC_CCS) { } else { +#if defined(CONFIG_USB_EHCI_NXP) + /* kUSB_ControllerEhci0 and kUSB_ControllerEhci1*/ + extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable); + USB_EhcihostPhyDisconnectDetectCmd(2 + busid, 0); +#endif for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) { g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[index] = false; } diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.h b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.h index 7f3febc..714128b 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.h +++ b/rt-thread/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.h @@ -1,375 +1,84 @@ /* - * Copyright 2020 The Apache Software Foundation - * Copyright 2022 sakumisu - * + * Copyright (c) 2022, sakumisu + * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef USB_HC_EHCI_H -#define USB_HC_EHCI_H +#ifndef _USB_EHCI_PRIV_H +#define _USB_EHCI_PRIV_H -#define EHCI_FULL_SPEED (0) /* Full-Speed (12Mbs) */ -#define EHCI_LOW_SPEED (1) /* Low-Speed (1.5Mbs) */ -#define EHCI_HIGH_SPEED (2) /* High-Speed (480 Mb/s) */ +#include "usbh_core.h" +#include "usbh_hub.h" +#include "usb_ehci_reg.h" -/* Host Controller Capability Register Bit Definitions **********************/ +#define EHCI_HCCR ((struct ehci_hccr *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_EHCI_HCCR_OFFSET)) +#define EHCI_HCOR ((struct ehci_hcor *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_EHCI_HCCR_OFFSET + g_ehci_hcd[bus->hcd.hcd_id].hcor_offset)) -/* Structural Parameters. Paragraph 2.2.3 */ +#define EHCI_PTR2ADDR(x) ((uint32_t)(uintptr_t)(x) & ~0x1F) +#define EHCI_ADDR2QH(x) ((struct ehci_qh_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F)) +#define EHCI_ADDR2QTD(x) ((struct ehci_qtd_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F)) +#define EHCI_ADDR2ITD(x) ((struct ehci_itd_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F)) -#define EHCI_HCSPARAMS_NPORTS_SHIFT (0) /* Bit 0-3: Number of physical downstream ports */ -#define EHCI_HCSPARAMS_NPORTS_MASK (15 << EHCI_HCSPARAMS_NPORTS_SHIFT) -#define EHCI_HCSPARAMS_PPC (1 << 4) /* Bit 4: Port Power Control */ -#define EHCI_HCSPARAMS_PRR (1 << 7) /* Bit 7: Port Routing Rules */ -#define EHCI_HCSPARAMS_NPCC_SHIFT (8) /* Bit 8-11: Number of Ports per Companion Controller */ -#define EHCI_HCSPARAMS_NPCC_MASK (15 << EHCI_HCSPARAMS_NPCC_SHIFT) -#define EHCI_HCSPARAMS_NCC_SHIFT (12) /* Bit 12-15: Number of Companion Controllers */ -#define EHCI_HCSPARAMS_NCC_MASK (15 << EHCI_HCSPARAMS_NCC_SHIFT) -#define EHCI_HCSPARAMS_PIND (1 << 16) /* Bit 16: Port Indicators */ -#define EHCI_HCSPARAMS_DBGPORT_SHIFT (20) /* Bit 20-23: Debug Port Number */ -#define EHCI_HCSPARAMS_DBGPORT_MASK (15 << EHCI_HCSPARAMS_DBGPORT_SHIFT) - -/* Capability Parameters. Paragraph 2.2.4 */ - -#define EHCI_HCCPARAMS_64BIT (1 << 0) /* Bit 0: 64-bit Addressing Capability */ -#define EHCI_HCCPARAMS_PFLF (1 << 1) /* Bit 1: Programmable Frame List Flag */ -#define EHCI_HCCPARAMS_ASPC (1 << 2) /* Bit 2: Asynchronous Schedule Park Capability */ -#define EHCI_HCCPARAMS_IST_SHIFT (4) /* Bits 4-7: Isochronous Scheduling Threshold */ -#define EHCI_HCCPARAMS_IST_MASK (15 << EHCI_HCCPARAMS_IST_SHIFT) -#define EHCI_HCCPARAMS_EECP_SHIFT (8) /* Bits 8-15: EHCI Extended Capabilities Pointer */ -#define EHCI_HCCPARAMS_EECP_MASK (0xff << EHCI_HCCPARAMS_EECP_SHIFT) - -/* Host Controller Operational Register Bit Definitions *********************/ - -/* USB Command. Paragraph 2.3.1 */ - -#define EHCI_USBCMD_RUN (1 << 0) /* Bit 0: Run/Stop */ -#define EHCI_USBCMD_HCRESET (1 << 1) /* Bit 1: Host Controller Reset */ -#define EHCI_USBCMD_FLSIZE_SHIFT (2) /* Bits 2-3: Frame List Size */ -#define EHCI_USBCMD_FLSIZE_MASK (3 << EHCI_USBCMD_FLSIZE_SHIFT) -#define EHCI_USBCMD_FLSIZE_1024 (0 << EHCI_USBCMD_FLSIZE_SHIFT) /* 1024 elements (4096 bytes) */ -#define EHCI_USBCMD_FLSIZE_512 (1 << EHCI_USBCMD_FLSIZE_SHIFT) /* 512 elements (2048 bytes) */ -#define EHCI_USBCMD_FLSIZE_256 (2 << EHCI_USBCMD_FLSIZE_SHIFT) /* 256 elements (1024 bytes) */ -#define EHCI_USBCMD_PSEN (1 << 4) /* Bit 4: Periodic Schedule Enable */ -#define EHCI_USBCMD_ASEN (1 << 5) /* Bit 5: Asynchronous Schedule Enable */ -#define EHCI_USBCMD_IAAD (1 << 6) /* Bit 6: Interrupt on Async Advance Doorbell */ -#define EHCI_USBCMD_LRESET (1 << 7) /* Bit 7: Light Host Controller Reset */ -#define EHCI_USBCMD_ASYNC_PARKCNT_SHIFT (8) /* Bits 8-9: Asynchronous Schedule Park Mode Count */ -#define EHCI_USBCMD_ASYNC_PARKCNT_MASK (3 << EHCI_USBCMD_ASYNC_PARKCNT_SHIFT) -#define EHCI_USBCMD_ASYNC_PARK (1 << 11) /* Bit 11: Asynchronous Schedule Park Mode Enable */ -#define EHCI_USBCMD_ITHRE_SHIFT (16) /* Bits 16-23: Interrupt Threshold Control */ -#define EHCI_USBCMD_ITHRE_MASK (0xff << EHCI_USBCMD_ITHRE_SHIFT) -#define EHCI_USBCMD_ITHRE_1MF (0x01 << EHCI_USBCMD_ITHRE_SHIFT) /* 1 micro-frame */ -#define EHCI_USBCMD_ITHRE_2MF (0x02 << EHCI_USBCMD_ITHRE_SHIFT) /* 2 micro-frames */ -#define EHCI_USBCMD_ITHRE_4MF (0x04 << EHCI_USBCMD_ITHRE_SHIFT) /* 4 micro-frames */ -#define EHCI_USBCMD_ITHRE_8MF (0x08 << EHCI_USBCMD_ITHRE_SHIFT) /* 8 micro-frames (default, 1 ms) */ -#define EHCI_USBCMD_ITHRE_16MF (0x10 << EHCI_USBCMD_ITHRE_SHIFT) /* 16 micro-frames (2 ms) */ -#define EHCI_USBCMD_ITHRE_32MF (0x20 << EHCI_USBCMD_ITHRE_SHIFT) /* 32 micro-frames (4 ms) */ -#define EHCI_USBCMD_ITHRE_64MF (0x40 << EHCI_USBCMD_ITHRE_SHIFT) /* 64 micro-frames (8 ms) */ - -/* USB Status. Paragraph 2.3.2 */ - -#define EHCI_USBSTS_INT (1 << 0) /* Bit 0: USB Interrupt */ -#define EHCI_USBSTS_ERR (1 << 1) /* Bit 1: USB Error Interrupt */ -#define EHCI_USBSTS_PCD (1 << 2) /* Bit 2: Port Change Detect */ -#define EHCI_USBSTS_FLR (1 << 3) /* Bit 3: Frame List Rollover */ -#define EHCI_USBSTS_FATAL (1 << 4) /* Bit 4: Host System Error */ -#define EHCI_USBSTS_IAA (1 << 5) /* Bit 5: Interrupt on Async Advance */ -#define EHCI_USBSTS_HALTED (1 << 12) /* Bit 12: HC Halted */ -#define EHCI_USBSTS_RECLAM (1 << 13) /* Bit 13: Reclamation */ -#define EHCI_USBSTS_PSS (1 << 14) /* Bit 14: Periodic Schedule Status */ -#define EHCI_USBSTS_ASS (1 << 15) /* Bit 15: Asynchronous Schedule Status */ - /* Bits 16-31: Reserved */ - -/* USB Interrupt Enable. Paragraph 2.3.3 */ - -#define EHCI_USBIE_INT (1 << 0) /* Bit 0: USB Interrupt */ -#define EHCI_USBIE_ERR (1 << 1) /* Bit 1: USB Error Interrupt */ -#define EHCI_USBIE_PCD (1 << 2) /* Bit 2: Port Change Detect */ -#define EHCI_USBIE_FLROLL (1 << 3) /* Bit 3: Frame List Rollover */ -#define EHCI_USBIE_FATAL (1 << 4) /* Bit 4: Host System Error */ -#define EHCI_USBIE_IAA (1 << 5) /* Bit 5: Interrupt on Async Advance */ -#define EHCI_USBIE_ALLINTS (0x3f) /* Bits 0-5: All interrupts */ - -/* USB Frame Index. Paragraph 2.3.4 */ - -#define EHCI_FRINDEX_MASK (0x3fff) /* Bits 0-13: Frame index */ - -/* 4G Segment Selector. - * Paragraph 2.3.5, Bits[64:32] of data structure addresses - */ - -/* Frame List Base Address. Paragraph 2.3.6 */ -#define EHCI_PERIODICLISTBASE_MASK (0xfffff000) /* Bits 12-31: Base Address (Low) */ - -/* Next Asynchronous List Address. Paragraph 2.3.7 */ - -#define EHCI_ASYNCLISTADDR_MASK (0xffffffe0) /* Bits 5-31: Link Pointer Low (LPL) */ - -/* Configured Flag Register. Paragraph 2.3.8 */ - -#define EHCI_CONFIGFLAG (1 << 0) /* Bit 0: Configure Flag */ - -/* Port Status/Control, Port 1-n. Paragraph 2.3.9 */ - -#define EHCI_PORTSC_CCS (1 << 0) /* Bit 0: Current Connect Status */ -#define EHCI_PORTSC_CSC (1 << 1) /* Bit 1: Connect Status Change */ -#define EHCI_PORTSC_PE (1 << 2) /* Bit 2: Port Enable */ -#define EHCI_PORTSC_PEC (1 << 3) /* Bit 3: Port Enable/Disable Change */ -#define EHCI_PORTSC_OCA (1 << 4) /* Bit 4: Over-current Active */ -#define EHCI_PORTSC_OCC (1 << 5) /* Bit 5: Over-current Change */ -#define EHCI_PORTSC_RESUME (1 << 6) /* Bit 6: Force Port Resume */ -#define EHCI_PORTSC_SUSPEND (1 << 7) /* Bit 7: Suspend */ -#define EHCI_PORTSC_RESET (1 << 8) /* Bit 8: Port Reset */ -#define EHCI_PORTSC_LSTATUS_SHIFT (10) /* Bits 10-11: Line Status */ -#define EHCI_PORTSC_LSTATUS_MASK (3 << EHCI_PORTSC_LSTATUS_SHIFT) -#define EHCI_PORTSC_LSTATUS_SE0 (0 << EHCI_PORTSC_LSTATUS_SHIFT) /* SE0 Not Low-speed device, perform EHCI reset */ -#define EHCI_PORTSC_LSTATUS_KSTATE (1 << EHCI_PORTSC_LSTATUS_SHIFT) /* K-state Low-speed device, release ownership of port */ -#define EHCI_PORTSC_LSTATUS_JSTATE (2 << EHCI_PORTSC_LSTATUS_SHIFT) /* J-state Not Low-speed device, perform EHCI reset */ -#define EHCI_PORTSC_PP (1 << 12) /* Bit 12: Port Power */ -#define EHCI_PORTSC_OWNER (1 << 13) /* Bit 13: Port Owner */ -#define EHCI_PORTSC_PIC_SHIFT (14) /* Bits 14-15: Port Indicator Control */ -#define EHCI_PORTSC_PIC_MASK (3 << EHCI_PORTSC_PIC_SHIFT) -#define EHCI_PORTSC_PIC_OFF (0 << EHCI_PORTSC_PIC_SHIFT) /* Port indicators are off */ -#define EHCI_PORTSC_PIC_AMBER (1 << EHCI_PORTSC_PIC_SHIFT) /* Amber */ -#define EHCI_PORTSC_PIC_GREEN (2 << EHCI_PORTSC_PIC_SHIFT) /* Green */ -#define EHCI_PORTSC_PTC_SHIFT (16) /* Bits 16-19: Port Test Control */ -#define EHCI_PORTSC_PTC_MASK (15 << EHCI_PORTSC_PTC_SHIFT) -#define EHCI_PORTSC_PTC_DISABLED (0 << EHCI_PORTSC_PTC_SHIFT) /* Test mode not enabled */ -#define EHCI_PORTSC_PTC_JSTATE (1 << EHCI_PORTSC_PTC_SHIFT) /* Test J_STATE */ -#define EHCI_PORTSC_PTC_KSTATE (2 << EHCI_PORTSC_PTC_SHIFT) /* Test K_STATE */ -#define EHCI_PORTSC_PTC_SE0NAK (3 << EHCI_PORTSC_PTC_SHIFT) /* Test SE0_NAK */ -#define EHCI_PORTSC_PTC_PACKET (4 << EHCI_PORTSC_PTC_SHIFT) /* Test Packet */ -#define EHCI_PORTSC_PTC_ENABLE (5 << EHCI_PORTSC_PTC_SHIFT) /* Test FORCE_ENABLE */ -#define EHCI_PORTSC_WKCCNTE (1 << 20) /* Bit 20: Wake on Connect Enable */ -#define EHCI_PORTSC_WKDSCNNTE (1 << 21) /* Bit 21: Wake on Disconnect Enable */ -#define EHCI_PORTSC_WKOCE (1 << 22) /* Bit 22: Wake on Over-current Enable */ - /* Bits 23-31: Reserved */ - -#define EHCI_PORTSC_ALLINTS (EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | \ - EHCI_PORTSC_OCC | EHCI_PORTSC_RESUME) - -/* Queue Head. Paragraph 3.6 */ - -/* Queue Head Horizontal Link Pointer: Queue Head DWord 0. Table 3-19 */ - -#define QH_HLP_END 0x1 - -#define QH_HLP_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0) /* Isochronous Transfer Descriptor */ -#define QH_HLP_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2) /* Queue Head */ -#define QH_HLP_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4) /* Split Transaction Isochronous Transfer Descriptor */ -#define QH_HLP_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6) /* Frame Span Traversal Node */ - -/* Endpoint Characteristics: Queue Head DWord 1. Table 3-19 */ - -#define QH_EPCHAR_DEVADDR_SHIFT (0) /* Bitx 0-6: Device Address */ -#define QH_EPCHAR_DEVADDR_MASK (0x7f << QH_EPCHAR_DEVADDR_SHIFT) -#define QH_EPCHAR_I (1 << 7) /* Bit 7: Inactivate on Next Transaction */ -#define QH_EPCHAR_ENDPT_SHIFT (8) /* Bitx 8-11: Endpoint Number */ -#define QH_EPCHAR_ENDPT_MASK (15 << QH_EPCHAR_ENDPT_SHIFT) -#define QH_EPCHAR_EPS_SHIFT (12) /* Bitx 12-13: Endpoint Speed */ -#define QH_EPCHAR_EPS_MASK (3 << QH_EPCHAR_EPS_SHIFT) -#define QH_EPCHAR_EPS_FULL (0 << QH_EPCHAR_EPS_SHIFT) /* Full-Speed (12Mbs) */ -#define QH_EPCHAR_EPS_LOW (1 << QH_EPCHAR_EPS_SHIFT) /* Low-Speed (1.5Mbs) */ -#define QH_EPCHAR_EPS_HIGH (2 << QH_EPCHAR_EPS_SHIFT) /* High-Speed (480 Mb/s) */ -#define QH_EPCHAR_DTC (1 << 14) /* Bit 14: Data Toggle Control */ -#define QH_EPCHAR_H (1 << 15) /* Bit 15: Head of Reclamation List Flag */ -#define QH_EPCHAR_MAXPKT_SHIFT (16) /* Bitx 16-26: Maximum Packet Length */ -#define QH_EPCHAR_MAXPKT_MASK (0x7ff << QH_EPCHAR_MAXPKT_SHIFT) -#define QH_EPCHAR_C (1 << 27) /* Bit 27: Control Endpoint Flag */ -#define QH_EPCHAR_RL_SHIFT (28) /* Bitx 28-31: Nak Count Reload */ -#define QH_EPCHAR_RL_MASK (15 << QH_EPCHAR_RL_SHIFT) - -/* Endpoint Capabilities: Queue Head DWord 2. Table 3-20 */ - -#define QH_EPCAPS_SSMASK_SHIFT (0) /* Bitx 0-7: Interrupt Schedule Mask (Frame S-mask) */ -#define QH_EPCAPS_SSMASK_MASK (0xff << QH_EPCAPS_SSMASK_SHIFT) -#define QH_EPCAPS_SSMASK(n) ((n) << QH_EPCAPS_SSMASK_SHIFT) -#define QH_EPCAPS_SCMASK_SHIFT (8) /* Bitx 8-15: Split Completion Mask (Frame C-Mask) */ -#define QH_EPCAPS_SCMASK_MASK (0xff << QH_EPCAPS_SCMASK_SHIFT) -#define QH_EPCAPS_SCMASK(n) ((n) << QH_EPCAPS_SCMASK_SHIFT) -#define QH_EPCAPS_HUBADDR_SHIFT (16) /* Bitx 16-22: Hub Address */ -#define QH_EPCAPS_HUBADDR_MASK (0x7f << QH_EPCAPS_HUBADDR_SHIFT) -#define QH_EPCAPS_HUBADDR(n) ((n) << QH_EPCAPS_HUBADDR_SHIFT) -#define QH_EPCAPS_PORT_SHIFT (23) /* Bit 23-29: Port Number */ -#define QH_EPCAPS_PORT_MASK (0x7f << QH_EPCAPS_PORT_SHIFT) -#define QH_EPCAPS_PORT(n) ((n) << QH_EPCAPS_PORT_SHIFT) -#define QH_EPCAPS_MULT_SHIFT (30) /* Bit 30-31: High-Bandwidth Pipe Multiplier */ -#define QH_EPCAPS_MULT_MASK (3 << QH_EPCAPS_MULT_SHIFT) -#define QH_EPCAPS_MULT(n) ((n) << QH_EPCAPS_MULT_SHIFT) - -/* qTD Token. Paragraph 3.5.3 */ - -#define QTD_LIST_END 1 - -#define QTD_TOKEN_STATUS_SHIFT (0) /* Bits 0-7: Status */ -#define QTD_TOKEN_STATUS_MASK (0xff << QTD_TOKEN_STATUS_SHIFT) -#define QTD_TOKEN_STATUS_PINGSTATE (1 << 0) /* Bit 0 Ping State */ -#define QTD_TOKEN_STATUS_ERR (1 << 0) /* Bit 0 Error */ -#define QTD_TOKEN_STATUS_SPLITXSTATE (1 << 1) /* Bit 1 Split Transaction State */ -#define QTD_TOKEN_STATUS_MMF (1 << 2) /* Bit 2 Missed Micro-Frame */ -#define QTD_TOKEN_STATUS_XACTERR (1 << 3) /* Bit 3 Transaction Error */ -#define QTD_TOKEN_STATUS_BABBLE (1 << 4) /* Bit 4 Babble Detected */ -#define QTD_TOKEN_STATUS_DBERR (1 << 5) /* Bit 5 Data Buffer Error */ -#define QTD_TOKEN_STATUS_HALTED (1 << 6) /* Bit 6 Halted */ -#define QTD_TOKEN_STATUS_ACTIVE (1 << 7) /* Bit 7 Active */ -#define QTD_TOKEN_STATUS_ERRORS (0x78 << QTD_TOKEN_STATUS_SHIFT) -#define QTD_TOKEN_PID_SHIFT (8) /* Bits 8-9: PID Code */ -#define QTD_TOKEN_PID_MASK (3 << QTD_TOKEN_PID_SHIFT) -#define QTD_TOKEN_PID_OUT (0 << QTD_TOKEN_PID_SHIFT) /* OUT Token generates token (E1H) */ -#define QTD_TOKEN_PID_IN (1 << QTD_TOKEN_PID_SHIFT) /* IN Token generates token (69H) */ -#define QTD_TOKEN_PID_SETUP (2 << QTD_TOKEN_PID_SHIFT) /* SETUP Token generates token (2DH) */ -#define QTD_TOKEN_CERR_SHIFT (10) /* Bits 10-11: Error Counter */ -#define QTD_TOKEN_CERR_MASK (3 << QTD_TOKEN_CERR_SHIFT) -#define QTD_TOKEN_CPAGE_SHIFT (12) /* Bits 12-14: Current Page */ -#define QTD_TOKEN_CPAGE_MASK (7 << QTD_TOKEN_CPAGE_SHIFT) -#define QTD_TOKEN_IOC (1 << 15) /* Bit 15: Interrupt On Complete */ -#define QTD_TOKEN_NBYTES_SHIFT (16) /* Bits 16-30: Total Bytes to Transfer */ -#define QTD_TOKEN_NBYTES_MASK (0x7fff << QTD_TOKEN_NBYTES_SHIFT) -#define QTD_TOKEN_TOGGLE (1 << 31) /* Bit 31: Data Toggle */ - -/* Isochronous (High-Speed) Transfer Descriptor (iTD). Paragraph 3.3 */ - -/* iTD Next Link Pointer. Paragraph 3.3.1 */ - -#define ITD_NLP_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0) -#define ITD_NLP_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2) -#define ITD_NLP_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4) -#define ITD_NLP_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6) - -/* iTD Transaction Status and Control List. Paragraph 3.3.2 */ -#define ITD_TSCL_XOFFS_SHIFT (0) /* Bits 0-11: Transaction X offset */ -#define ITD_TSCL_XOFFS_MASK (0xfff << ITD_TSCL_XOFFS_SHIFT) -#define ITD_TSCL_PG_SHIFT (12) /* Bits 12-14: Page select */ -#define ITD_TSCL_PG_MASK (7 << ITD_TSCL_PG_SHIFT) -#define ITD_TSCL_IOC (1 << 15) /* Bit 15: Interrupt On Comp */ -#define ITD_TSCL_LENGTH_SHIFT (16) /* Bits 16-27: Transaction length */ -#define ITD_TSCL_LENGTH_MASK (0xfff << ITD_TSCL_LENGTH_SHIFT) -#define ITD_TSCL_STATUS_SHIFT (28) /* Bits 28-31: Transaction status */ -#define ITD_TSCL_STATUS_MASK (15 << ITD_TSCL_STATUS_SHIFT) -#define ITD_TSCL_STATUS_XACTERR (1 << 28) /* Bit 28: Transaction error */ -#define ITD_TSCL_STATUS_BABBLE (1 << 29) /* Bit 29: Babble Detected */ -#define ITD_TSCL_STATUS_DBERROR (1 << 30) /* Bit 30: Data Buffer Error */ -#define ITD_TSCL_STATUS_ACTIVE (1 << 31) /* Bit 31: Active error */ - -/* iTD Buffer Page Pointer List. Paragraph 3.3.4 */ - -/* iTD Buffer Pointer Page 0. Table 3-4 */ - -#define ITD_BUFPTR0_DEVADDR_SHIFT (0) /* Bits 0-6: Device Address */ -#define ITD_BUFPTR0_DEVADDR_MASK (0x7f << ITD_BUFPTR0_DEVADDR_SHIFT) -#define ITD_BUFPTR0_ENDPT_SHIFT (8) /* Bits 8-11: Endpoint Number */ -#define ITD_BUFPTR0_ENDPT_MASK (15 << ITD_BUFPTR0_ENDPT_SHIFT) - -/* iTD Buffer Pointer Page 1. Table 3-5 */ - -#define ITD_BUFPTR1_MAXPKT_SHIFT (0) /* Bits 0-10: Maximum Packet Size */ -#define ITD_BUFPTR1_MAXPKT_MASK (0x7ff << ITD_BUFPTR1_MAXPKT_SHIFT) -#define ITD_BUFPTR1_DIRIN (1 << 11) /* Bit 11: Direction 1=IN */ -#define ITD_BUFPTR1_DIROUT (0) /* Bit 11: Direction 0=OUT */ - -/* iTD Buffer Pointer Page 2. Table 3-6 */ - -#define ITD_BUFPTR2_MULTI_SHIFT (0) /* Bits 0-1: Multi */ -#define ITD_BUFPTR2_MULTI_MASK (3 << ITD_BUFPTR2_MULTI_SHIFT) -#define ITD_BUFPTR2_MULTI_1 (1 << ITD_BUFPTR2_MULTI_SHIFT) /* One transaction per micro-frame */ -#define ITD_BUFPTR2_MULTI_2 (2 << ITD_BUFPTR2_MULTI_SHIFT) /* Two transactions per micro-frame */ -#define ITD_BUFPTR2_MULTI_3 (3 << ITD_BUFPTR2_MULTI_SHIFT) /* Three transactions per micro-frame */ - -/* Registers ****************************************************************/ - -/* Host Controller Capability Registers. - * This register block must be positioned at a well known address. - */ - -struct ehci_hccr { - volatile uint8_t caplength; /* 0x00: Capability Register Length */ - volatile uint8_t reserved; /* 0x01: reserved */ - volatile uint16_t hciversion; /* 0x02: Interface Version Number */ - volatile uint32_t hcsparams; /* 0x04: Structural Parameters */ - volatile uint32_t hccparams; /* 0x08: Capability Parameters */ - volatile uint8_t hcspportroute[8]; /* 0x0c: Companion Port Route Description */ -}; - -/* Host Controller Operational Registers. - * This register block is positioned at an offset of 'caplength' from the - * beginning of the Host Controller Capability Registers. - */ - -struct ehci_hcor { - volatile uint32_t usbcmd; /* 0x00: USB Command */ - volatile uint32_t usbsts; /* 0x04: USB Status */ - volatile uint32_t usbintr; /* 0x08: USB Interrupt Enable */ - volatile uint32_t frindex; /* 0x0c: USB Frame Index */ - volatile uint32_t ctrldssegment; /* 0x10: 4G Segment Selector */ - volatile uint32_t periodiclistbase; /* 0x14: Frame List Base Address */ - volatile uint32_t asynclistaddr; /* 0x18: Next Asynchronous List Address */ -#ifndef CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE - uint32_t reserved[9]; +#ifndef CONFIG_USB_EHCI_QH_NUM +#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM #endif - volatile uint32_t configflag; /* 0x40: Configured Flag Register */ - volatile uint32_t portsc[15]; /* 0x44: Port Status/Control */ +#ifndef CONFIG_USB_EHCI_QTD_NUM +#define CONFIG_USB_EHCI_QTD_NUM 3 +#endif +#ifndef CONFIG_USB_EHCI_ITD_NUM +#define CONFIG_USB_EHCI_ITD_NUM 5 +#endif +#ifndef CONFIG_USB_EHCI_ISO_NUM +#define CONFIG_USB_EHCI_ISO_NUM 4 +#endif + +extern uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port); + +struct ehci_qtd_hw { + struct ehci_qtd hw; + struct usbh_urb *urb; + uint32_t length; +} __attribute__((aligned(32))); + +struct ehci_qh_hw { + struct ehci_qh hw; + struct ehci_qtd_hw qtd_pool[CONFIG_USB_EHCI_QTD_NUM]; + uint32_t first_qtd; + struct usbh_urb *urb; + usb_osal_sem_t waitsem; + uint8_t remove_in_iaad; +} __attribute__((aligned(32))); + +struct ehci_itd_hw { + struct ehci_itd hw; + struct usbh_urb *urb; + uint16_t start_frame; + uint8_t mf_unmask; + uint8_t mf_valid; + uint32_t pkt_idx[8]; +} __attribute__((aligned(32))); + +struct ehci_iso_hw +{ + struct ehci_itd_hw itd_pool[CONFIG_USB_EHCI_ITD_NUM]; + uint32_t itd_num; }; -/* USB2 Debug Port Register Interface. - * This register block is normally found via the PCI capabalities. - * In non-PCI implementions, you need apriori information about the - * location of these registers. - */ - -struct ehci_debug { - uint32_t psc; /* 0x00: Debug Port Control/Status Register */ - uint32_t pids; /* 0x04: Debug USB PIDs Register */ - uint32_t data[2]; /* 0x08: Debug Data buffer Registers */ - uint32_t addr; /* 0x10: Device Address Register */ +struct ehci_hcd { + bool ehci_qh_used[CONFIG_USB_EHCI_QH_NUM]; + bool ehci_iso_used[CONFIG_USB_EHCI_ISO_NUM]; + bool ppc; /* Port Power Control */ + bool has_tt; /* if use tt instead of Companion Controller */ + uint8_t n_cc; /* Number of Companion Controller */ + uint8_t n_pcc; /* Number of ports supported per companion host controller */ + uint8_t n_ports; + uint8_t hcor_offset; }; -/* Data Structures **********************************************************/ +extern struct ehci_hcd g_ehci_hcd[CONFIG_USBHOST_MAX_BUS]; +extern uint32_t g_framelist[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(CONFIG_USB_EHCI_FRAME_LIST_SIZE, 1024)]; -/* Queue Element Transfer Descriptor (qTD). Paragraph 3.5 */ +int ehci_iso_urb_init(struct usbh_bus *bus, struct usbh_urb *urb); +void ehci_kill_iso_urb(struct usbh_bus *bus, struct usbh_urb *urb); +void ehci_scan_isochronous_list(struct usbh_bus *bus); -struct ehci_qtd { - uint32_t next_qtd; /* 0x00-0x03: Next qTD Pointer */ - uint32_t alt_next_qtd; /* 0x04-0x07: Alternate Next qTD Pointer */ - uint32_t token; /* 0x08-0x0b: qTD Token */ - uint32_t bpl[5]; /* 0x0c-0x1c: Buffer Page Pointer List */ -}; - -#define SIZEOF_EHCI_QTD (32) /* 8*sizeof(uint32_t) */ - -/* Queue Head. Paragraph 3.6 */ - -struct ehci_qh { - uint32_t hlp; /* 0x00-0x03: Queue Head Horizontal Link Pointer */ - uint32_t epchar; /* 0x04-0x07: Endpoint Characteristics */ - uint32_t epcap; /* 0x08-0x0b: Endpoint Capabilities */ - uint32_t curr_qtd; /* 0x0c-0x0f: Current qTD Pointer */ - struct ehci_qtd overlay; /* 0x10-0x2c: Transfer overlay */ -}; - -#define SIZEOF_EHCI_QH (48) /* 4*sizeof(uint32_t) + 32 */ - -/* Isochronous (High-Speed) Transfer Descriptor (iTD). - * Paragraph 3.3. Must be aligned to 32-byte boundaries. - */ - -struct ehci_itd { - uint32_t nlp; /* 0x00-0x03: Next link pointer */ - uint32_t tscl[8]; /* 0x04-0x23: Transaction Status and Control List */ - uint32_t bpl[7]; /* 0x24-0x3c: Buffer Page Pointer List */ -}; - -#define SIZEOF_EHCI_ITD (64) /* 16*sizeof(uint32_t) */ - -/* Split Transaction Isochronous Transfer Descriptor (siTD). Paragraph 3.4 */ - -struct ehci_sitd { - uint32_t nlp; /* 0x00-0x03: Next link pointer */ - uint32_t epchar; /* 0x04-0x07: Endpoint and Transaction Translator Characteristics */ - uint32_t mfsc; /* 0x08-0x0b: Micro-frame Schedule Control */ - uint32_t tsc; /* 0x0c-0x0f: Transfer Status and Control */ - uint32_t bpl[2]; /* 0x10-0x17: Buffer Pointer List */ - uint32_t blp; /* 0x18-0x1b: Back link pointer */ -}; - -#define SIZEOF_EHCI_SITD (28) /* 7*sizeof(uint32_t) */ - -#endif /* USB_HC_EHCI_H */ +#endif diff --git a/rt-thread/components/drivers/usb/cherryusb/port/fsdev/usb_dc_fsdev.c b/rt-thread/components/drivers/usb/cherryusb/port/fsdev/usb_dc_fsdev.c index b3bfb5c..f27e8c6 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/fsdev/usb_dc_fsdev.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/fsdev/usb_dc_fsdev.c @@ -117,6 +117,11 @@ int usbd_set_address(uint8_t busid, const uint8_t addr) return 0; } +int usbd_set_remote_wakeup(uint8_t busid) +{ + return -1; +} + uint8_t usbd_get_port_speed(uint8_t busid) { return USB_SPEED_FULL; @@ -149,7 +154,8 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) case USB_ENDPOINT_TYPE_ISOCHRONOUS: wEpRegVal = USB_EP_ISOCHRONOUS; - break; + USB_LOG_ERR("Do not support iso in fsdev\r\n"); + return -1; default: break; @@ -255,8 +261,20 @@ int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) { + uint8_t ep_idx = USB_EP_GET_IDX(ep); + if (USB_EP_DIR_IS_OUT(ep)) { + if (PCD_GET_EP_RX_STATUS(USB, ep_idx) & USB_EP_RX_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } } else { + if (PCD_GET_EP_TX_STATUS(USB, ep_idx) & USB_EP_TX_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } } return 0; } diff --git a/rt-thread/components/drivers/usb/cherryusb/port/hpm/usb_dc_hpm.c b/rt-thread/components/drivers/usb/cherryusb/port/hpm/usb_dc_hpm.c index 31ad5b7..b663fd9 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/hpm/usb_dc_hpm.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/hpm/usb_dc_hpm.c @@ -39,6 +39,7 @@ struct hpm_ep_state { /* Driver state */ struct hpm_udc { usb_device_handle_t *handle; + bool is_suspend; struct hpm_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/ struct hpm_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */ } g_hpm_udc[CONFIG_USBDEV_MAX_BUS]; @@ -91,7 +92,7 @@ int usb_dc_init(uint8_t busid) } uint32_t int_mask; - int_mask = (USB_USBINTR_UE_MASK | USB_USBINTR_UEE_MASK | + int_mask = (USB_USBINTR_UE_MASK | USB_USBINTR_UEE_MASK | USB_USBINTR_SLE_MASK | USB_USBINTR_PCE_MASK | USB_USBINTR_URE_MASK); usb_device_init(g_hpm_udc[busid].handle, int_mask); @@ -116,6 +117,21 @@ int usbd_set_address(uint8_t busid, const uint8_t addr) return 0; } +int usbd_set_remote_wakeup(uint8_t busid) +{ + USB_Type *ptr; + + ptr = g_hpm_udc[busid].handle->regs; + + if (!usb_get_suspend_status(ptr)) { + return -1; + } + + usb_force_port_resume(ptr); + + return 0; +} + uint8_t usbd_get_port_speed(uint8_t busid) { uint8_t speed; @@ -259,6 +275,7 @@ void USBD_IRQHandler(uint8_t busid) } if (int_status & intr_reset) { + g_hpm_udc[busid].is_suspend = false; memset(g_hpm_udc[busid].in_ep, 0, sizeof(struct hpm_ep_state) * USB_NUM_BIDIR_ENDPOINTS); memset(g_hpm_udc[busid].out_ep, 0, sizeof(struct hpm_ep_state) * USB_NUM_BIDIR_ENDPOINTS); usbd_event_reset_handler(busid); @@ -267,10 +284,12 @@ void USBD_IRQHandler(uint8_t busid) if (int_status & intr_suspend) { if (usb_device_get_suspend_status(handle)) { - usbd_event_suspend_handler(busid); /* Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration. */ if (usb_device_get_address(handle)) { + g_hpm_udc[busid].is_suspend = true; + usbd_event_suspend_handler(busid); } + } else { } } @@ -278,6 +297,10 @@ void USBD_IRQHandler(uint8_t busid) if (!usb_device_get_port_ccs(handle)) { usbd_event_disconnect_handler(busid); } else { + if (g_hpm_udc[busid].is_suspend) { + g_hpm_udc[busid].is_suspend = false; + usbd_event_resume_handler(busid); + } usbd_event_connect_handler(busid); } } @@ -314,7 +337,7 @@ void USBD_IRQHandler(uint8_t busid) transfer_len += p_qtd->expected_bytes - p_qtd->total_bytes; } - if (p_qtd->next == USB_SOC_DCD_QTD_NEXT_INVALID){ + if (p_qtd->next == USB_SOC_DCD_QTD_NEXT_INVALID) { break; } else { p_qtd = (dcd_qtd_t *)p_qtd->next; @@ -335,16 +358,20 @@ void USBD_IRQHandler(uint8_t busid) } } +#if !defined(USBD_USE_CUSTOM_ISR) || !USBD_USE_CUSTOM_ISR + +SDK_DECLARE_EXT_ISR_M(IRQn_USB0, isr_usbd0) void isr_usbd0(void) { USBD_IRQHandler(_dcd_busid[0]); } -SDK_DECLARE_EXT_ISR_M(IRQn_USB0, isr_usbd0) #ifdef HPM_USB1_BASE +SDK_DECLARE_EXT_ISR_M(IRQn_USB1, isr_usbd1) void isr_usbd1(void) { USBD_IRQHandler(_dcd_busid[1]); } -SDK_DECLARE_EXT_ISR_M(IRQn_USB1, isr_usbd1) -#endif \ No newline at end of file +#endif + +#endif diff --git a/rt-thread/components/drivers/usb/cherryusb/port/kinetis/README.md b/rt-thread/components/drivers/usb/cherryusb/port/kinetis/README.md new file mode 100644 index 0000000..f51c9a6 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/kinetis/README.md @@ -0,0 +1,18 @@ +# Note + +## Support Chip List + +### NXP + +Modify USB_NOCACHE_RAM_SECTION + +``` +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".NonCacheable"))) +``` + +- MCXC444/MCXA153 (device only) +- MCXN947 + +### MM32 + +- MM32F3/MM32F5 diff --git a/rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_dc_kinetis.c b/rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_dc_kinetis.c new file mode 100644 index 0000000..bd2b287 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_dc_kinetis.c @@ -0,0 +1,448 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_kinetis_reg.h" + +#define USB_OTG_DEV ((KINETIS_TypeDef *)g_usbdev_bus[busid].reg_base) + +/* Endpoint state */ +struct kinetis_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + bool ep_odd; /* Endpoint odd */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct kinetis_udc { + uint8_t dev_addr; + struct kinetis_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/ + struct kinetis_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */ +} g_kinetis_udc[CONFIG_USBDEV_MAX_BUS]; + +USB_NOCACHE_RAM_SECTION __attribute__((aligned(512))) kinetis_bd_table_t g_kinetis_bdt[CONFIG_USBDEV_MAX_BUS]; +USB_NOCACHE_RAM_SECTION __attribute__((aligned(32))) uint8_t setup_packet[CONFIG_USBDEV_MAX_BUS][8]; + +static int kinetis_start_transfer(uint8_t busid, uint8_t ep, uint8_t *buffer, uint16_t buflen) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t dir; + uint8_t odd; + uint16_t ep_mps; + kinetis_bd_t *bd; + kinetis_bd_t *next; + + if (USB_EP_DIR_IS_OUT(ep)) { + dir = 0; + odd = g_kinetis_udc[busid].out_ep[ep_idx].ep_odd; + ep_mps = g_kinetis_udc[busid].out_ep[ep_idx].ep_mps; + } else { + dir = 1; + odd = g_kinetis_udc[busid].in_ep[ep_idx].ep_odd; + ep_mps = g_kinetis_udc[busid].in_ep[ep_idx].ep_mps; + } + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd]; + + if (bd->own) { + USB_LOG_INFO("ep%02x is busy\r\n", ep); + return -1; + } + + bd->bc = buflen >= ep_mps ? ep_mps : buflen; + bd->addr = (uint32_t)buffer; + bd->own = 1; + return 0; +} + +static void kinetis_read_setup(uint8_t busid) +{ + uint8_t out_odd = g_kinetis_udc[busid].out_ep[0].ep_odd; + uint8_t in_odd = g_kinetis_udc[busid].in_ep[0].ep_odd; + + if (g_kinetis_bdt[busid].table[0][0][out_odd].own) { + USB_LOG_INFO("ep0 is busy\r\n"); + return; + } + + g_kinetis_bdt[busid].table[0][0][out_odd].data = 0; + g_kinetis_bdt[busid].table[0][0][out_odd ^ 1].data = 1; + g_kinetis_bdt[busid].table[0][1][in_odd].data = 1; + g_kinetis_bdt[busid].table[0][1][in_odd ^ 1].data = 0; + + kinetis_start_transfer(busid, USB_CONTROL_OUT_EP0, setup_packet[busid], 8); +} + +__WEAK void usb_dc_low_level_init(uint8_t busid) +{ +} + +__WEAK void usb_dc_low_level_deinit(uint8_t busid) +{ +} + +int usb_dc_init(uint8_t busid) +{ + usb_dc_low_level_init(busid); + + memset(&g_kinetis_udc[busid], 0, sizeof(g_kinetis_udc[busid])); + + USB_OTG_DEV->BDTPAGE1 = (uint8_t)((uintptr_t)&g_kinetis_bdt[busid] >> 8); + USB_OTG_DEV->BDTPAGE2 = (uint8_t)((uintptr_t)&g_kinetis_bdt[busid] >> 16); + USB_OTG_DEV->BDTPAGE3 = (uint8_t)((uintptr_t)&g_kinetis_bdt[busid] >> 24); + + USB_OTG_DEV->INTEN = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK | + USB_INTEN_SLEEPEN_MASK | USB_INTEN_RESUMEEN_MASK | + USB_INTEN_ERROREN_MASK; + + USB_OTG_DEV->CTL |= USB_CTL_USBENSOFEN_MASK; + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + usb_dc_low_level_deinit(busid); + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + g_kinetis_udc[busid].dev_addr = addr; + + if (addr == 0) { + USB_OTG_DEV->ADDR = 0; + } + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + USB_OTG_DEV->CTL |= USB_CTL_RESUME_MASK; + + usbd_kinetis_delay_ms(10); + + USB_OTG_DEV->CTL &= ~USB_CTL_RESUME_MASK; + + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_FULL; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + uint8_t odd; + uint8_t dir; + kinetis_bd_t *bd; + uint8_t regval; + + /* Must not exceed max endpoint number */ + if (ep_idx >= CONFIG_USBDEV_EP_NUM) { + return -1; + } + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_kinetis_udc[busid].out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_kinetis_udc[busid].out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_kinetis_udc[busid].out_ep[ep_idx].ep_enable = true; + + dir = 0; + odd = g_kinetis_udc[busid].out_ep[ep_idx].ep_odd; + } else { + g_kinetis_udc[busid].in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_kinetis_udc[busid].in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_kinetis_udc[busid].in_ep[ep_idx].ep_enable = true; + + dir = 1; + odd = g_kinetis_udc[busid].in_ep[ep_idx].ep_odd; + } + + if (ep_idx != 0) { + regval = USB_ENDPT_EPCTLDIS_MASK; + regval |= (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK : 0; + regval |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; + USB_OTG_DEV->ENDPOINT[ep_idx].ENDPT |= regval; + + if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd]; + bd->dts = 1; + bd->data = 0; + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd ^ 1]; + bd->dts = 1; + bd->data = 1; + } + } + + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t dir; + kinetis_bd_t *bd; + + if (USB_EP_DIR_IS_OUT(ep)) { + g_kinetis_udc[busid].out_ep[ep_idx].ep_enable = false; + dir = 0; + } else { + g_kinetis_udc[busid].in_ep[ep_idx].ep_enable = false; + dir = 1; + } + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][0]; + bd->head = 0; + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][1]; + bd->head = 0; + + USB_OTG_DEV->ENDPOINT[ep_idx].ENDPT &= ~(dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK); + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + kinetis_bd_t *bd; + uint8_t odd; + uint8_t dir; + + if (0 == ep_idx) { + USB_OTG_DEV->ENDPOINT[ep_idx].ENDPT |= USB_ENDPT_EPSTALL_MASK; + + if (ep_idx == 0) { + kinetis_read_setup(busid); + } + } else { + if (USB_EP_DIR_IS_OUT(ep)) { + dir = 0; + odd = g_kinetis_udc[busid].out_ep[ep_idx].ep_odd; + } else { + dir = 1; + odd = g_kinetis_udc[busid].in_ep[ep_idx].ep_odd; + } + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd]; + + bd->bdt_stall = 1; + bd->own = 1; + } + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + kinetis_bd_t *bd; + uint8_t odd; + uint8_t dir; + + if (USB_EP_DIR_IS_OUT(ep)) { + dir = 0; + odd = g_kinetis_udc[busid].out_ep[ep_idx].ep_odd; + } else { + dir = 1; + odd = g_kinetis_udc[busid].in_ep[ep_idx].ep_odd; + } + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd]; + + bd->own = 0; + bd->bdt_stall = 0; + bd->data = 0; + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd ^ 1]; + bd->data = 1; + + uint8_t regval = USB_OTG_DEV->ENDPOINT[ep_idx].ENDPT; + if (regval & USB_ENDPT_EPSTALL_MASK) { + USB_OTG_DEV->ENDPOINT[ep_idx].ENDPT = regval & ~USB_ENDPT_EPSTALL_MASK; + } + + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + uint8_t regval = USB_OTG_DEV->ENDPOINT[ep_idx].ENDPT; + if (regval & USB_ENDPT_EPSTALL_MASK) { + *stalled = 1; + } else { + *stalled = 0; + } + + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, + uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_kinetis_udc[busid].in_ep[ep_idx].ep_enable) { + return -2; + } + + g_kinetis_udc[busid].in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_kinetis_udc[busid].in_ep[ep_idx].xfer_len = data_len; + g_kinetis_udc[busid].in_ep[ep_idx].actual_xfer_len = 0; + + return kinetis_start_transfer(busid, ep, (uint8_t *)data, MIN(data_len, g_kinetis_udc[busid].in_ep[ep_idx].ep_mps)); +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, + uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_kinetis_udc[busid].out_ep[ep_idx].ep_enable) { + return -2; + } + + g_kinetis_udc[busid].out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_kinetis_udc[busid].out_ep[ep_idx].xfer_len = data_len; + g_kinetis_udc[busid].out_ep[ep_idx].actual_xfer_len = 0; + + return kinetis_start_transfer(busid, ep, (uint8_t *)data, MIN(data_len, g_kinetis_udc[busid].out_ep[ep_idx].ep_mps)); +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint8_t s; + uint8_t pid; + uint8_t ep_idx; + uint8_t dir; + uint8_t odd; + uint16_t bc; + uint8_t is = USB_OTG_DEV->ISTAT; + uint8_t mask = USB_OTG_DEV->INTEN; + kinetis_bd_t *bd; + + USB_OTG_DEV->ISTAT = is & ~mask; + is &= mask; + + if (is & USB_ISTAT_ERROR_MASK) { + uint32_t es = USB_OTG_DEV->ERRSTAT; + USB_OTG_DEV->ERRSTAT = es; + USB_OTG_DEV->ISTAT = is; + } + + if (is & USB_ISTAT_USBRST_MASK) { + USB_OTG_DEV->ISTAT = is; + USB_OTG_DEV->CTL |= USB_CTL_ODDRST_MASK; + USB_OTG_DEV->ADDR = 0; + + USB_OTG_DEV->ENDPOINT[0].ENDPT = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK; + for (uint8_t i = 1; i < 16; i++) { + USB_OTG_DEV->ENDPOINT[i].ENDPT = 0; + } + + memset(&g_kinetis_bdt[busid], 0, sizeof(g_kinetis_bdt[busid])); + memset(g_kinetis_udc[busid].in_ep, 0, sizeof(struct kinetis_ep_state) * CONFIG_USBDEV_EP_NUM); + memset(g_kinetis_udc[busid].out_ep, 0, sizeof(struct kinetis_ep_state) * CONFIG_USBDEV_EP_NUM); + usbd_event_reset_handler(busid); + + kinetis_read_setup(busid); + + USB_OTG_DEV->CTL &= ~USB_CTL_ODDRST_MASK; + } + + if (is & USB_ISTAT_SLEEP_MASK) { + USB_OTG_DEV->ISTAT = USB_ISTAT_SLEEP_MASK; + } + + if (is & USB_ISTAT_RESUME_MASK) { + USB_OTG_DEV->ISTAT = USB_ISTAT_RESUME_MASK; + } + + if (is & USB_ISTAT_SOFTOK_MASK) { + USB_OTG_DEV->ISTAT = USB_ISTAT_SOFTOK_MASK; + } + + if (is & USB_ISTAT_STALL_MASK) { + USB_OTG_DEV->ISTAT = USB_ISTAT_STALL_MASK; + } + + if (is & USB_ISTAT_TOKDNE_MASK) { + s = USB_OTG_DEV->STAT; + USB_OTG_DEV->ISTAT = USB_ISTAT_TOKDNE_MASK; /* must be cleared after get STAT */ + + ep_idx = (s & USB_STAT_ENDP_MASK) >> USB_STAT_ENDP_SHIFT; + dir = (s & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT; + odd = (s & USB_STAT_ODD_MASK) >> USB_STAT_ODD_SHIFT; + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd]; + + pid = bd->tok_pid; + bc = bd->bc; + + bd->bdt_stall = 0; + bd->dts = 1; + bd->ninc = 0; + bd->keep = 0; + + if (dir) { + g_kinetis_udc[busid].in_ep[ep_idx].ep_odd = odd ^ 1; + } else { + g_kinetis_udc[busid].out_ep[ep_idx].ep_odd = odd ^ 1; + } + + if (pid == USB_TOKEN_PID_SETUP) { + USB_OTG_DEV->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + usbd_event_ep0_setup_complete_handler(busid, (uint8_t *)bd->addr); + return; + } + + if (dir) { + g_kinetis_udc[busid].in_ep[ep_idx].xfer_buf += bc; + g_kinetis_udc[busid].in_ep[ep_idx].xfer_len -= bc; + g_kinetis_udc[busid].in_ep[ep_idx].actual_xfer_len += bc; + + if (g_kinetis_udc[busid].in_ep[ep_idx].xfer_len == 0) { + usbd_event_ep_in_complete_handler(busid, ep_idx | 0x80, g_kinetis_udc[busid].in_ep[ep_idx].actual_xfer_len); + } else { + kinetis_start_transfer(busid, ep_idx | 0x80, g_kinetis_udc[busid].in_ep[ep_idx].xfer_buf, + MIN(g_kinetis_udc[busid].in_ep[ep_idx].xfer_len, g_kinetis_udc[busid].in_ep[ep_idx].ep_mps)); + } + } else { + g_kinetis_udc[busid].out_ep[ep_idx].xfer_buf += bc; + g_kinetis_udc[busid].out_ep[ep_idx].xfer_len -= bc; + g_kinetis_udc[busid].out_ep[ep_idx].actual_xfer_len += bc; + + if ((bc < g_kinetis_udc[busid].out_ep[ep_idx].ep_mps) || (g_kinetis_udc[busid].out_ep[ep_idx].xfer_len == 0)) { + usbd_event_ep_out_complete_handler(busid, ep_idx, g_kinetis_udc[busid].out_ep[ep_idx].actual_xfer_len); + } else { + kinetis_start_transfer(busid, ep_idx, g_kinetis_udc[busid].out_ep[ep_idx].xfer_buf, + MIN(g_kinetis_udc[busid].out_ep[ep_idx].xfer_len, g_kinetis_udc[busid].out_ep[ep_idx].ep_mps)); + } + } + + if ((bc == 0) && (ep_idx == 0)) { + if ((g_kinetis_udc[busid].dev_addr > 0) && dir) { + USB_OTG_DEV->ADDR = g_kinetis_udc[busid].dev_addr; + g_kinetis_udc[busid].dev_addr = 0; + } + + kinetis_read_setup(busid); + } + } +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_glue_mcx.c b/rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_glue_mcx.c new file mode 100644 index 0000000..4460779 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_glue_mcx.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "fsl_common.h" +#include "usb_kinetis_reg.h" + +#define USB_OTG_DEV ((KINETIS_MCX_TypeDef *)g_usbdev_bus[busid].reg_base) + +#if defined(MCXC444_H_) +#define USBD_IRQ USB0_IRQHandler +void USB_ClockInit(void) +{ + SystemCoreClockUpdate(); + CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U); +} +#elif defined(MCXA153_H_) +#define USBD_IRQ USB0_IRQHandler +void USB_ClockInit(void) +{ + RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn); + CLOCK_EnableUsbfsClock(); +} +#elif defined(MCXN947_CM33_CORE0_H_) +#define USBD_IRQ USB0_FS_IRQHandler +void USB_ClockInit(void) +{ + CLOCK_AttachClk(kCLK_48M_to_USB0); + CLOCK_EnableClock(kCLOCK_Usb0Ram); + CLOCK_EnableClock(kCLOCK_Usb0Fs); + CLOCK_EnableUsbfsClock(); +} +#else +#error "Unsupported MCU with Kinetis IP" +#endif + +void USBD_IRQ(void) +{ + extern void USBD_IRQHandler(uint8_t busid); + USBD_IRQHandler(0); +} + +void usb_dc_low_level_init(uint8_t busid) +{ + USB_ClockInit(); + + uint8_t irqNumber; + + uint8_t usbDeviceKhciIrq[] = USB_IRQS; + irqNumber = usbDeviceKhciIrq[0]; + + /* Install isr, set priority, and enable IRQ. */ + NVIC_SetPriority((IRQn_Type)irqNumber, 3); + EnableIRQ((IRQn_Type)irqNumber); + + USB_OTG_DEV->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; + while (USB_OTG_DEV->USBTRC0 & USB_USBTRC0_USBRESET_MASK) + ; + + USB_OTG_DEV->USBTRC0 |= USB_USBTRC0_VREGIN_STS(1); /* software must set this bit to 1 */ + USB_OTG_DEV->USBCTRL = 0; + USB_OTG_DEV->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK; +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + USB_OTG_DEV->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK; + DisableIRQ((IRQn_Type)USB0_FS_IRQn); +} + +void usbd_kinetis_delay_ms(uint8_t ms) +{ +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_hc_kinetis.c b/rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_hc_kinetis.c new file mode 100644 index 0000000..30404ce --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_hc_kinetis.c @@ -0,0 +1 @@ +TODO \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_kinetis_reg.h b/rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_kinetis_reg.h new file mode 100644 index 0000000..b2720a6 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/kinetis/usb_kinetis_reg.h @@ -0,0 +1,1487 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __USB_KINETIS_REG_H__ +#define __USB_KINETIS_REG_H__ + +#define __I volatile const /* Define "read-only" permission */ +#define __IO volatile /* Define "read-write" permission */ + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint8_t PERID; /**< Peripheral ID, offset: 0x0 */ + uint8_t RESERVED_0[3]; + __I uint8_t IDCOMP; /**< Peripheral ID Complement, offset: 0x4 */ + uint8_t RESERVED_1[3]; + __I uint8_t REV; /**< Peripheral Revision, offset: 0x8 */ + uint8_t RESERVED_2[3]; + __I uint8_t ADDINFO; /**< Peripheral Additional Information, offset: 0xC */ + uint8_t RESERVED_3[3]; + __IO uint8_t OTGISTAT; /**< OTG Interrupt Status, offset: 0x10 */ + uint8_t RESERVED_4[3]; + __IO uint8_t OTGICR; /**< OTG Interrupt Control, offset: 0x14 */ + uint8_t RESERVED_5[3]; + __I uint8_t OTGSTAT; /**< OTG Status, offset: 0x18 */ + uint8_t RESERVED_6[3]; + __IO uint8_t OTGCTL; /**< OTG Control, offset: 0x1C */ + uint8_t RESERVED_7[99]; + __IO uint8_t ISTAT; /**< Interrupt Status, offset: 0x80 */ + uint8_t RESERVED_8[3]; + __IO uint8_t INTEN; /**< Interrupt Enable, offset: 0x84 */ + uint8_t RESERVED_9[3]; + __IO uint8_t ERRSTAT; /**< Error Interrupt Status, offset: 0x88 */ + uint8_t RESERVED_10[3]; + __IO uint8_t ERREN; /**< Error Interrupt Enable, offset: 0x8C */ + uint8_t RESERVED_11[3]; + __I uint8_t STAT; /**< Status, offset: 0x90 */ + uint8_t RESERVED_12[3]; + __IO uint8_t CTL; /**< Control, offset: 0x94 */ + uint8_t RESERVED_13[3]; + __IO uint8_t ADDR; /**< Address, offset: 0x98 */ + uint8_t RESERVED_14[3]; + __IO uint8_t BDTPAGE1; /**< BDT Page 1, offset: 0x9C */ + uint8_t RESERVED_15[3]; + __I uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ + uint8_t RESERVED_16[3]; + __I uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ + uint8_t RESERVED_17[3]; + __IO uint8_t TOKEN; /**< Token, offset: 0xA8 */ + uint8_t RESERVED_18[3]; + __IO uint8_t SOFTHLD; /**< SOF Threshold, offset: 0xAC */ + uint8_t RESERVED_19[3]; + __IO uint8_t BDTPAGE2; /**< BDT Page 2, offset: 0xB0 */ + uint8_t RESERVED_20[3]; + __IO uint8_t BDTPAGE3; /**< BDT Page 3, offset: 0xB4 */ + uint8_t RESERVED_21[11]; + struct { /* offset: 0xC0, array step: 0x4 */ + __IO uint8_t ENDPT; /**< Endpoint Control, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_0[3]; + } ENDPOINT[16]; +} KINETIS_TypeDef; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name PERID - Peripheral ID */ +/*! @{ */ + +#define USB_PERID_ID_MASK (0x3FU) +#define USB_PERID_ID_SHIFT (0U) +/*! ID - Peripheral Identification */ +#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) +/*! @} */ + +/*! @name IDCOMP - Peripheral ID Complement */ +/*! @{ */ + +#define USB_IDCOMP_NID_MASK (0x3FU) +#define USB_IDCOMP_NID_SHIFT (0U) +/*! NID - Negative Peripheral ID */ +#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) +/*! @} */ + +/*! @name REV - Peripheral Revision */ +/*! @{ */ + +#define USB_REV_REV_MASK (0xFFU) +#define USB_REV_REV_SHIFT (0U) +/*! REV - Revision */ +#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) +/*! @} */ + +/*! @name ADDINFO - Peripheral Additional Information */ +/*! @{ */ + +#define USB_ADDINFO_IEHOST_MASK (0x1U) +#define USB_ADDINFO_IEHOST_SHIFT (0U) +/*! IEHOST - Host Mode Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) +/*! @} */ + +/*! @name OTGISTAT - OTG Interrupt Status */ +/*! @{ */ + +#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) +#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) +/*! LINE_STATE_CHG - Line State Change Interrupt Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) + +#define USB_OTGISTAT_ONEMSEC_MASK (0x40U) +#define USB_OTGISTAT_ONEMSEC_SHIFT (6U) +/*! ONEMSEC - One Millisecond Timer Timeout Flag + * 0b0..Not timed out + * 0b1..Timed out + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) +/*! @} */ + +/*! @name OTGICR - OTG Interrupt Control */ +/*! @{ */ + +#define USB_OTGICR_LINESTATEEN_MASK (0x20U) +#define USB_OTGICR_LINESTATEEN_SHIFT (5U) +/*! LINESTATEEN - Line State Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) + +#define USB_OTGICR_ONEMSECEN_MASK (0x40U) +#define USB_OTGICR_ONEMSECEN_SHIFT (6U) +/*! ONEMSECEN - 1-Millisecond Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) +/*! @} */ + +/*! @name OTGSTAT - OTG Status */ +/*! @{ */ + +#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) +#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) +/*! LINESTATESTABLE - Line State Stable + * 0b0..Unstable + * 0b1..Stable + */ +#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) + +#define USB_OTGSTAT_ONEMSEC_MASK (0x40U) +#define USB_OTGSTAT_ONEMSEC_SHIFT (6U) +/*! ONEMSEC - Reserved for 1 ms count */ +#define USB_OTGSTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSEC_SHIFT)) & USB_OTGSTAT_ONEMSEC_MASK) +/*! @} */ + +/*! @name OTGCTL - OTG Control */ +/*! @{ */ + +#define USB_OTGCTL_OTGEN_MASK (0x4U) +#define USB_OTGCTL_OTGEN_SHIFT (2U) +/*! OTGEN - On-The-Go Pullup and Pulldown Resistor Enable + * 0b0..If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup + * resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged. + * 0b1..Uses the pullup and pulldown controls in this register. + */ +#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) + +#define USB_OTGCTL_DMLOW_MASK (0x10U) +#define USB_OTGCTL_DMLOW_SHIFT (4U) +/*! DMLOW - D- Data Line Pulldown Resistor Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) + +#define USB_OTGCTL_DPLOW_MASK (0x20U) +#define USB_OTGCTL_DPLOW_SHIFT (5U) +/*! DPLOW - D+ Data Line pulldown Resistor Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) + +#define USB_OTGCTL_DPHIGH_MASK (0x80U) +#define USB_OTGCTL_DPHIGH_SHIFT (7U) +/*! DPHIGH - D+ Data Line Pullup Resistor Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) +/*! @} */ + +/*! @name ISTAT - Interrupt Status */ +/*! @{ */ + +#define USB_ISTAT_USBRST_MASK (0x1U) +#define USB_ISTAT_USBRST_SHIFT (0U) +/*! USBRST - USB Reset Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) + +#define USB_ISTAT_ERROR_MASK (0x2U) +#define USB_ISTAT_ERROR_SHIFT (1U) +/*! ERROR - Error Flag + * 0b0..Error did not occur + * 0b1..Error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) + +#define USB_ISTAT_SOFTOK_MASK (0x4U) +#define USB_ISTAT_SOFTOK_SHIFT (2U) +/*! SOFTOK - Start Of Frame (SOF) Token Flag + * 0b0..Did not receive + * 0b1..Received + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) + +#define USB_ISTAT_TOKDNE_MASK (0x8U) +#define USB_ISTAT_TOKDNE_SHIFT (3U) +/*! TOKDNE - Current Token Processing Flag + * 0b0..Not processed + * 0b1..Processed + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) + +#define USB_ISTAT_SLEEP_MASK (0x10U) +#define USB_ISTAT_SLEEP_SHIFT (4U) +/*! SLEEP - Sleep Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) + +#define USB_ISTAT_RESUME_MASK (0x20U) +#define USB_ISTAT_RESUME_SHIFT (5U) +/*! RESUME - Resume Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) + +#define USB_ISTAT_ATTACH_MASK (0x40U) +#define USB_ISTAT_ATTACH_SHIFT (6U) +/*! ATTACH - Attach Interrupt Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) + +#define USB_ISTAT_STALL_MASK (0x80U) +#define USB_ISTAT_STALL_SHIFT (7U) +/*! STALL - Stall Interrupt Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt Enable */ +/*! @{ */ + +#define USB_INTEN_USBRSTEN_MASK (0x1U) +#define USB_INTEN_USBRSTEN_SHIFT (0U) +/*! USBRSTEN - USBRST Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) + +#define USB_INTEN_ERROREN_MASK (0x2U) +#define USB_INTEN_ERROREN_SHIFT (1U) +/*! ERROREN - ERROR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) + +#define USB_INTEN_SOFTOKEN_MASK (0x4U) +#define USB_INTEN_SOFTOKEN_SHIFT (2U) +/*! SOFTOKEN - SOFTOK Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) + +#define USB_INTEN_TOKDNEEN_MASK (0x8U) +#define USB_INTEN_TOKDNEEN_SHIFT (3U) +/*! TOKDNEEN - TOKDNE Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) + +#define USB_INTEN_SLEEPEN_MASK (0x10U) +#define USB_INTEN_SLEEPEN_SHIFT (4U) +/*! SLEEPEN - SLEEP Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) + +#define USB_INTEN_RESUMEEN_MASK (0x20U) +#define USB_INTEN_RESUMEEN_SHIFT (5U) +/*! RESUMEEN - RESUME Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) + +#define USB_INTEN_ATTACHEN_MASK (0x40U) +#define USB_INTEN_ATTACHEN_SHIFT (6U) +/*! ATTACHEN - ATTACH Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) + +#define USB_INTEN_STALLEN_MASK (0x80U) +#define USB_INTEN_STALLEN_SHIFT (7U) +/*! STALLEN - STALL Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) +/*! @} */ + +/*! @name ERRSTAT - Error Interrupt Status */ +/*! @{ */ + +#define USB_ERRSTAT_PIDERR_MASK (0x1U) +#define USB_ERRSTAT_PIDERR_SHIFT (0U) +/*! PIDERR - PID Error Flag + * 0b0..Did not fail + * 0b1..Failed + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) + +#define USB_ERRSTAT_CRC5EOF_MASK (0x2U) +#define USB_ERRSTAT_CRC5EOF_SHIFT (1U) +/*! CRC5EOF - CRC5 Error or End of Frame Error Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) + +#define USB_ERRSTAT_CRC16_MASK (0x4U) +#define USB_ERRSTAT_CRC16_SHIFT (2U) +/*! CRC16 - CRC16 Error Flag + * 0b0..Not rejected + * 0b1..Rejected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) + +#define USB_ERRSTAT_DFN8_MASK (0x8U) +#define USB_ERRSTAT_DFN8_SHIFT (3U) +/*! DFN8 - Data Field Not 8 Bits Flag + * 0b0..Integer number of bytes + * 0b1..Not an integer number of bytes + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) + +#define USB_ERRSTAT_BTOERR_MASK (0x10U) +#define USB_ERRSTAT_BTOERR_SHIFT (4U) +/*! BTOERR - Bus Turnaround Timeout Error Flag + * 0b0..Not timed out + * 0b1..Timed out + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) + +#define USB_ERRSTAT_DMAERR_MASK (0x20U) +#define USB_ERRSTAT_DMAERR_SHIFT (5U) +/*! DMAERR - DMA Access Error Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) + +#define USB_ERRSTAT_OWNERR_MASK (0x40U) +#define USB_ERRSTAT_OWNERR_SHIFT (6U) +/*! OWNERR - BD Unavailable Error Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK) + +#define USB_ERRSTAT_BTSERR_MASK (0x80U) +#define USB_ERRSTAT_BTSERR_SHIFT (7U) +/*! BTSERR - Bit Stuff Error Flag + * 0b0..Packet not rejected due to the error + * 0b1..Packet rejected due to the error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) +/*! @} */ + +/*! @name ERREN - Error Interrupt Enable */ +/*! @{ */ + +#define USB_ERREN_PIDERREN_MASK (0x1U) +#define USB_ERREN_PIDERREN_SHIFT (0U) +/*! PIDERREN - PIDERR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) + +#define USB_ERREN_CRC5EOFEN_MASK (0x2U) +#define USB_ERREN_CRC5EOFEN_SHIFT (1U) +/*! CRC5EOFEN - CRC5/EOF Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) + +#define USB_ERREN_CRC16EN_MASK (0x4U) +#define USB_ERREN_CRC16EN_SHIFT (2U) +/*! CRC16EN - CRC16 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) + +#define USB_ERREN_DFN8EN_MASK (0x8U) +#define USB_ERREN_DFN8EN_SHIFT (3U) +/*! DFN8EN - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) + +#define USB_ERREN_BTOERREN_MASK (0x10U) +#define USB_ERREN_BTOERREN_SHIFT (4U) +/*! BTOERREN - BTOERR (Bus Timeout Error) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) + +#define USB_ERREN_DMAERREN_MASK (0x20U) +#define USB_ERREN_DMAERREN_SHIFT (5U) +/*! DMAERREN - DMAERR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) + +#define USB_ERREN_OWNERREN_MASK (0x40U) +#define USB_ERREN_OWNERREN_SHIFT (6U) +/*! OWNERREN - OWNERR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK) + +#define USB_ERREN_BTSERREN_MASK (0x80U) +#define USB_ERREN_BTSERREN_SHIFT (7U) +/*! BTSERREN - BTSERR (Bit Stuff Error) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define USB_STAT_ODD_MASK (0x4U) +#define USB_STAT_ODD_SHIFT (2U) +/*! ODD - Odd Bank + * 0b0..Not in the odd bank + * 0b1..In the odd bank + */ +#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) + +#define USB_STAT_TX_MASK (0x8U) +#define USB_STAT_TX_SHIFT (3U) +/*! TX - Transmit Indicator + * 0b0..Receive + * 0b1..Transmit + */ +#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) + +#define USB_STAT_ENDP_MASK (0xF0U) +#define USB_STAT_ENDP_SHIFT (4U) +/*! ENDP - Endpoint address */ +#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) +/*! @} */ + +/*! @name CTL - Control */ +/*! @{ */ + +#define USB_CTL_USBENSOFEN_MASK (0x1U) +#define USB_CTL_USBENSOFEN_SHIFT (0U) +/*! USBENSOFEN - USB Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) + +#define USB_CTL_ODDRST_MASK (0x2U) +#define USB_CTL_ODDRST_SHIFT (1U) +/*! ODDRST - Odd Reset */ +#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) + +#define USB_CTL_RESUME_MASK (0x4U) +#define USB_CTL_RESUME_SHIFT (2U) +/*! RESUME - Resume */ +#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) + +#define USB_CTL_HOSTMODEEN_MASK (0x8U) +#define USB_CTL_HOSTMODEEN_SHIFT (3U) +/*! HOSTMODEEN - Host Mode Enable + * 0b0..USBFS operates in Device mode. + * 0b1..USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor. + */ +#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) + +#define USB_CTL_RESET_MASK (0x10U) +#define USB_CTL_RESET_SHIFT (4U) +/*! RESET - Reset Signaling Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) + +#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) +#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) +/*! TXSUSPENDTOKENBUSY - TXD Suspend And Token Busy */ +#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) + +#define USB_CTL_SE0_MASK (0x40U) +#define USB_CTL_SE0_SHIFT (6U) +/*! SE0 - Live USB Single-Ended Zero signal */ +#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) + +#define USB_CTL_JSTATE_MASK (0x80U) +#define USB_CTL_JSTATE_SHIFT (7U) +/*! JSTATE - Live USB Differential Receiver JSTATE Signal */ +#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) +/*! @} */ + +/*! @name ADDR - Address */ +/*! @{ */ + +#define USB_ADDR_ADDR_MASK (0x7FU) +#define USB_ADDR_ADDR_SHIFT (0U) +/*! ADDR - USB Address */ +#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) + +#define USB_ADDR_LSEN_MASK (0x80U) +#define USB_ADDR_LSEN_SHIFT (7U) +/*! LSEN - Low Speed Enable */ +#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) +/*! @} */ + +/*! @name BDTPAGE1 - BDT Page 1 */ +/*! @{ */ + +#define USB_BDTPAGE1_BDTBA_MASK (0xFEU) +#define USB_BDTPAGE1_BDTBA_SHIFT (1U) +/*! BDTBA - BDT Base Address */ +#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) +/*! @} */ + +/*! @name FRMNUML - Frame Number Register Low */ +/*! @{ */ + +#define USB_FRMNUML_FRM_MASK (0xFFU) +#define USB_FRMNUML_FRM_SHIFT (0U) +/*! FRM - Frame Number, Bits 0-7 */ +#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) +/*! @} */ + +/*! @name FRMNUMH - Frame Number Register High */ +/*! @{ */ + +#define USB_FRMNUMH_FRM_MASK (0x7U) +#define USB_FRMNUMH_FRM_SHIFT (0U) +/*! FRM - Frame Number, Bits 8-10 */ +#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) +/*! @} */ + +/*! @name TOKEN - Token */ +/*! @{ */ + +#define USB_TOKEN_TOKENENDPT_MASK (0xFU) +#define USB_TOKEN_TOKENENDPT_SHIFT (0U) +/*! TOKENENDPT - Token Endpoint Address */ +#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) + +#define USB_TOKEN_TOKENPID_MASK (0xF0U) +#define USB_TOKEN_TOKENPID_SHIFT (4U) +/*! TOKENPID - Token Type + * 0b0001..OUT token. USBFS performs an OUT (TX) transaction. + * 0b1001..IN token. USBFS performs an IN (RX) transaction. + * 0b1101..SETUP token. USBFS performs a SETUP (TX) transaction + */ +#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) +/*! @} */ + +/*! @name SOFTHLD - SOF Threshold */ +/*! @{ */ + +#define USB_SOFTHLD_CNT_MASK (0xFFU) +#define USB_SOFTHLD_CNT_SHIFT (0U) +/*! CNT - SOF Count Threshold */ +#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) +/*! @} */ + +/*! @name BDTPAGE2 - BDT Page 2 */ +/*! @{ */ + +#define USB_BDTPAGE2_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE2_BDTBA_SHIFT (0U) +/*! BDTBA - BDT Base Address */ +#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) +/*! @} */ + +/*! @name BDTPAGE3 - BDT Page 3 */ +/*! @{ */ + +#define USB_BDTPAGE3_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE3_BDTBA_SHIFT (0U) +/*! BDTBA - BDT Base Address */ +#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) +/*! @} */ + +/*! @name ENDPT - Endpoint Control */ +/*! @{ */ + +#define USB_ENDPT_EPHSHK_MASK (0x1U) +#define USB_ENDPT_EPHSHK_SHIFT (0U) +/*! EPHSHK - Endpoint Handshaking Enable */ +#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) + +#define USB_ENDPT_EPSTALL_MASK (0x2U) +#define USB_ENDPT_EPSTALL_SHIFT (1U) +/*! EPSTALL - Endpoint Stalled */ +#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) + +#define USB_ENDPT_EPTXEN_MASK (0x4U) +#define USB_ENDPT_EPTXEN_SHIFT (2U) +/*! EPTXEN - Endpoint for TX transfers enable */ +#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) + +#define USB_ENDPT_EPRXEN_MASK (0x8U) +#define USB_ENDPT_EPRXEN_SHIFT (3U) +/*! EPRXEN - Endpoint for RX transfers enable */ +#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) + +#define USB_ENDPT_EPCTLDIS_MASK (0x10U) +#define USB_ENDPT_EPCTLDIS_SHIFT (4U) +/*! EPCTLDIS - Control Transfer Disable + * 0b0..Enable + * 0b1..Disable + */ +#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) + +#define USB_ENDPT_RETRYDIS_MASK (0x40U) +#define USB_ENDPT_RETRYDIS_SHIFT (6U) +/*! RETRYDIS - Retry Disable + * 0b0..Retried NAK'ed transactions in hardware. + * 0b1..Do not retry NAK'ed transactions. When a transaction is NAK'ed, the BDT PID field is updated with the NAK + * PID, and the TOKEN_DNE interrupt becomes 1. + */ +#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) + +#define USB_ENDPT_HOSTWOHUB_MASK (0x80U) +#define USB_ENDPT_HOSTWOHUB_SHIFT (7U) +/*! HOSTWOHUB - Host Without A Hub + * 0b0..Connected using a hub (USBFS generates PRE_PID as required) + * 0b1..Connected directly to host without a hub, or was used to attach + */ +#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) +/*! @} */ + +/* The count of USB_ENDPT */ +#define USB_ENDPT_COUNT (16U) + +/*! @name USBCTRL - USB Control */ +/*! @{ */ + +#define USB_USBCTRL_DPDM_LANE_REVERSE_MASK (0x4U) +#define USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT (2U) +/*! DPDM_LANE_REVERSE - DP and DM Lane Reversal Control + * 0b0..Standard USB DP and DM package pin assignment + * 0b1..Reverse roles of USB DP and DM package pins + */ +#define USB_USBCTRL_DPDM_LANE_REVERSE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT)) & USB_USBCTRL_DPDM_LANE_REVERSE_MASK) + +#define USB_USBCTRL_HOST_LS_EOP_MASK (0x8U) +#define USB_USBCTRL_HOST_LS_EOP_SHIFT (3U) +/*! HOST_LS_EOP - Host-Mode-Only Low-Speed Device EOP Signaling + * 0b0..Full-speed device or a low-speed device through a hub + * 0b1..Directly-connected low-speed device + */ +#define USB_USBCTRL_HOST_LS_EOP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_HOST_LS_EOP_SHIFT)) & USB_USBCTRL_HOST_LS_EOP_MASK) + +#define USB_USBCTRL_UARTSEL_MASK (0x10U) +#define USB_USBCTRL_UARTSEL_SHIFT (4U) +/*! UARTSEL - UART Select + * 0b0..USB DP and DM external package pins are used for USB signaling. + * 0b1..USB DP and DM external package pins are used for UART signaling. + */ +#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK) + +#define USB_USBCTRL_UARTCHLS_MASK (0x20U) +#define USB_USBCTRL_UARTCHLS_SHIFT (5U) +/*! UARTCHLS - UART Signal Channel Select + * 0b0..USB DP and DM signals are used as UART TX/RX. + * 0b1..USB DP and DM signals are used as UART RX/TX. + */ +#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK) + +#define USB_USBCTRL_PDE_MASK (0x40U) +#define USB_USBCTRL_PDE_SHIFT (6U) +/*! PDE - Pulldown Enable + * 0b0..Disable on D+ and D- + * 0b1..Enable on D+ and D- + */ +#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) + +#define USB_USBCTRL_SUSP_MASK (0x80U) +#define USB_USBCTRL_SUSP_SHIFT (7U) +/*! SUSP - Suspend + * 0b0..Not in Suspend state + * 0b1..In Suspend state + */ +#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) +/*! @} */ + +/*! @name OBSERVE - USB OTG Observe */ +/*! @{ */ + +#define USB_OBSERVE_DMPD_MASK (0x10U) +#define USB_OBSERVE_DMPD_SHIFT (4U) +/*! DMPD - D- Pulldown + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) + +#define USB_OBSERVE_DPPD_MASK (0x40U) +#define USB_OBSERVE_DPPD_SHIFT (6U) +/*! DPPD - D+ Pulldown + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) + +#define USB_OBSERVE_DPPU_MASK (0x80U) +#define USB_OBSERVE_DPPU_SHIFT (7U) +/*! DPPU - D+ Pullup + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) +/*! @} */ + +/*! @name CONTROL - USB OTG Control */ +/*! @{ */ + +#define USB_CONTROL_VBUS_SOURCE_SEL_MASK (0x1U) +#define USB_CONTROL_VBUS_SOURCE_SEL_SHIFT (0U) +/*! VBUS_SOURCE_SEL - VBUS Monitoring Source Select + * 0b0..Reserved + * 0b1..Resistive divider attached to a GPIO pin + */ +#define USB_CONTROL_VBUS_SOURCE_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_VBUS_SOURCE_SEL_SHIFT)) & USB_CONTROL_VBUS_SOURCE_SEL_MASK) + +#define USB_CONTROL_SESS_VLD_MASK (0x2U) +#define USB_CONTROL_SESS_VLD_SHIFT (1U) +/*! SESS_VLD - VBUS Session Valid status + * 0b1..Above + * 0b0..Below + */ +#define USB_CONTROL_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_SESS_VLD_SHIFT)) & USB_CONTROL_SESS_VLD_MASK) + +#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) +#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) +/*! DPPULLUPNONOTG - DP Pullup in Non-OTG Device Mode + * 0b0..Disable + * 0b1..Enabled + */ +#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) +/*! @} */ + +/*! @name USBTRC0 - USB Transceiver Control 0 */ +/*! @{ */ + +#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) +#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) +/*! USB_RESUME_INT - USB Asynchronous Interrupt + * 0b0..Not generated + * 0b1..Generated because of the USB asynchronous interrupt + */ +#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) + +#define USB_USBTRC0_SYNC_DET_MASK (0x2U) +#define USB_USBTRC0_SYNC_DET_SHIFT (1U) +/*! SYNC_DET - Synchronous USB Interrupt Detect + * 0b0..Not detected + * 0b1..Detected + */ +#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) + +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) +/*! USB_CLK_RECOVERY_INT - Combined USB Clock Recovery interrupt status */ +#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) + +#define USB_USBTRC0_VREDG_DET_MASK (0x8U) +#define USB_USBTRC0_VREDG_DET_SHIFT (3U) +/*! VREDG_DET - VREGIN Rising Edge Interrupt Detect + * 0b0..Not detected + * 0b1..Detected + */ +#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK) + +#define USB_USBTRC0_VFEDG_DET_MASK (0x10U) +#define USB_USBTRC0_VFEDG_DET_SHIFT (4U) +/*! VFEDG_DET - VREGIN Falling Edge Interrupt Detect + * 0b0..Not detected + * 0b1..Detected + */ +#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK) + +#define USB_USBTRC0_USBRESMEN_MASK (0x20U) +#define USB_USBTRC0_USBRESMEN_SHIFT (5U) +/*! USBRESMEN - Asynchronous Resume Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) + +#define USB_USBTRC0_VREGIN_STS_MASK (0x40U) +#define USB_USBTRC0_VREGIN_STS_SHIFT (6U) +/*! VREGIN_STS - VREGIN Status */ +#define USB_USBTRC0_VREGIN_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREGIN_STS_SHIFT)) & USB_USBTRC0_VREGIN_STS_MASK) + +#define USB_USBTRC0_USBRESET_MASK (0x80U) +#define USB_USBTRC0_USBRESET_SHIFT (7U) +/*! USBRESET - USB Reset + * 0b0..Normal USBFS operation + * 0b1..Returns USBFS to its reset state + */ +#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) +/*! @} */ + +/*! @name USBFRMADJUST - Frame Adjust */ +/*! @{ */ + +#define USB_USBFRMADJUST_ADJ_MASK (0xFFU) +#define USB_USBFRMADJUST_ADJ_SHIFT (0U) +/*! ADJ - Frame Adjustment */ +#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) +/*! @} */ + +/*! @name KEEP_ALIVE_CTRL - Keep Alive Mode Control */ +/*! @{ */ + +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK (0x1U) +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT (0U) +/*! KEEP_ALIVE_EN - Keep Alive Mode Enable + * 0b0..Everything remains same as before. + * 0b1..USB shall enter USB_KEEP_ALIVE mode after asserting ipg_stop. + */ +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK) + +#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK (0x2U) +#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT (1U) +/*! OWN_OVERRD_EN - OWN Bit Override Enable */ +#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK) + +#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK (0x4U) +#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT (2U) +/*! STOP_ACK_DLY_EN - Stop Acknowledge Delay Enable + * 0b0..Enter KEEP_ALIVE mode immediately when there is no USB AHB transfer. + * 0b1..Enter KEEP_ALIVE mode until the USB core is idle and there is no USB AHB transfer. + */ +#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK) + +#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK (0x8U) +#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT (3U) +/*! WAKE_REQ_EN - Wakeup Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) + +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK (0x10U) +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT (4U) +/*! WAKE_INT_EN - Wakeup Interrupt Enable */ +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK) + +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK (0x40U) +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT (6U) +/*! KEEP_ALIVE_STS - Keep Alive Status + * 0b0..Not in Keep Alive mode + * 0b1..In Keep Alive mode + */ +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK) + +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK (0x80U) +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT (7U) +/*! WAKE_INT_STS - Wakeup Interrupt Status Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK) +/*! @} */ + +/*! @name KEEP_ALIVE_WKCTRL - Keep Alive Mode Wakeup Control */ +/*! @{ */ + +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK (0xFU) +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U) +/*! WAKE_ON_THIS - Token PID for the wakeup request + * 0b0001..Wake up after receiving OUT or SETUP token packet. + * 0b1101..Wake up after receiving SETUP token packet. All other values are reserved. + */ +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK) + +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK (0xF0U) +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT (4U) +/*! WAKE_ENDPT - Endpoint address for the wakeup request */ +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK) +/*! @} */ + +/*! @name MISCCTRL - Miscellaneous Control */ +/*! @{ */ + +#define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U) +#define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U) +/*! SOFDYNTHLD - Dynamic SOF Threshold Compare mode + * 0b0..When the byte-times SOF threshold is reached + * 0b1..When 8 byte-times SOF threshold is reached or overstepped + */ +#define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK) + +#define USB_MISCCTRL_SOFBUSSET_MASK (0x2U) +#define USB_MISCCTRL_SOFBUSSET_SHIFT (1U) +/*! SOFBUSSET - SOF_TOK Interrupt Generation Mode Select + * 0b0..According to the SOF threshold value + * 0b1..When the SOF counter reaches 0 + */ +#define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK) + +#define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U) +#define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U) +/*! OWNERRISODIS - OWN Error Detect for ISO IN and ISO OUT Disable + * 0b0..Enable + * 0b1..Disable + */ +#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK) + +#define USB_MISCCTRL_VREDG_EN_MASK (0x8U) +#define USB_MISCCTRL_VREDG_EN_SHIFT (3U) +/*! VREDG_EN - VREGIN Rising Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK) + +#define USB_MISCCTRL_VFEDG_EN_MASK (0x10U) +#define USB_MISCCTRL_VFEDG_EN_SHIFT (4U) +/*! VFEDG_EN - VREGIN Falling Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK) + +#define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U) +#define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U) +/*! STL_ADJ_EN - USB Peripheral Mode Stall Adjust Enable + * 0b0..If ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint stalls. + * 0b1..If ENDPTn[END_STALL] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls. + */ +#define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK) +/*! @} */ + +/*! @name STALL_IL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction */ +/*! @{ */ + +#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U) +#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U) +/*! STALL_I_DIS0 - Disable Endpoint 0 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U) +#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U) +/*! STALL_I_DIS1 - Disable Endpoint 1 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U) +#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U) +/*! STALL_I_DIS2 - Disable Endpoint 2 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U) +#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U) +/*! STALL_I_DIS3 - Disable Endpoint 3 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U) +#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U) +/*! STALL_I_DIS4 - Disable Endpoint 4 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U) +#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U) +/*! STALL_I_DIS5 - Disable Endpoint 5 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U) +#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U) +/*! STALL_I_DIS6 - Disable Endpoint 6 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U) +#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U) +/*! STALL_I_DIS7 - Disable Endpoint 7 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK) +/*! @} */ + +/*! @name STALL_IH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction */ +/*! @{ */ + +#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U) +#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U) +/*! STALL_I_DIS8 - Disable Endpoint 8 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U) +#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U) +/*! STALL_I_DIS9 - Disable Endpoint 9 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U) +#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U) +/*! STALL_I_DIS10 - Disable Endpoint 10 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U) +#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U) +/*! STALL_I_DIS11 - Disable Endpoint 11 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U) +#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U) +/*! STALL_I_DIS12 - Disable Endpoint 12 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U) +#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U) +/*! STALL_I_DIS13 - Disable Endpoint 13 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U) +#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U) +/*! STALL_I_DIS14 - Disable Endpoint 14 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U) +#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U) +/*! STALL_I_DIS15 - Disable Endpoint 15 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK) +/*! @} */ + +/*! @name STALL_OL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction */ +/*! @{ */ + +#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U) +#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U) +/*! STALL_O_DIS0 - Disable Endpoint 0 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U) +#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U) +/*! STALL_O_DIS1 - Disable Endpoint 1 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U) +#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U) +/*! STALL_O_DIS2 - Disable Endpoint 2 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U) +#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U) +/*! STALL_O_DIS3 - Disable Endpoint 3 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U) +#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U) +/*! STALL_O_DIS4 - Disable Endpoint 4 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U) +#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U) +/*! STALL_O_DIS5 - Disable Endpoint 5 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U) +#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U) +/*! STALL_O_DIS6 - Disable Endpoint 6 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U) +#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U) +/*! STALL_O_DIS7 - Disable Endpoint 7 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK) +/*! @} */ + +/*! @name STALL_OH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction */ +/*! @{ */ + +#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U) +#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U) +/*! STALL_O_DIS8 - Disable Endpoint 8 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U) +#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U) +/*! STALL_O_DIS9 - Disable Endpoint 9 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U) +#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U) +/*! STALL_O_DIS10 - Disable Endpoint 10 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U) +#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U) +/*! STALL_O_DIS11 - Disable Endpoint 11 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U) +#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U) +/*! STALL_O_DIS12 - Disable endpoint 12 OUT direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U) +#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U) +/*! STALL_O_DIS13 - Disable Endpoint 13 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U) +#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U) +/*! STALL_O_DIS14 - Disable Endpoint 14 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U) +#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U) +/*! STALL_O_DIS15 - Disable Endpoint 15 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_CTRL - USB Clock Recovery Control */ +/*! @{ */ + +#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK (0x8U) +#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT (3U) +/*! TRIM_INIT_VAL_SEL - Selects the source for the initial FIRC trim fine value used after a reset. + * 0b0..Mid-scale + * 0b1..IFR + */ +#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT)) & USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK) + +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) +/*! RESTART_IFRTRIM_EN - Restart from IFR Trim Value + * 0b0..Trim fine adjustment always works based on the previous updated trim fine value. + * 0b1..Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable. + */ +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) + +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) +/*! RESET_RESUME_ROUGH_EN - Reset or Resume to Rough Phase Enable + * 0b0..Always works in tracking phase after the first time rough phase, to track transition. + * 0b1..Go back to rough stage whenever a bus reset or bus resume occurs. + */ +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) + +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) +/*! CLOCK_RECOVER_EN - Crystal-Less USB Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_IRC_EN - FIRC Oscillator Enable */ +/*! @{ */ + +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) +/*! IRC_EN - Fast IRC enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_INT_EN - Clock Recovery Combined Interrupt Enable */ +/*! @{ */ + +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) +/*! OVF_ERROR_EN - Overflow error interrupt enable + * 0b0..The interrupt is masked + * 0b1..The interrupt is enabled + */ +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_INT_STATUS - Clock Recovery Separated Interrupt Status */ +/*! @{ */ + +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) +/*! OVF_ERROR - Overflow Error Interrupt Status Flag + * 0b0..Interrupt did not occur + * 0b1..Unmasked interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) +/*! @} */ + +/*! + * @} + */ +/* end of group USB_Register_Masks */ + +/*! + * @brief This type of structure instance is used to implement the buffer descriptor for USB. + */ +typedef struct +{ + union { + uint32_t head; /*!< Head. */ + struct + { + uint32_t reserved0 : 2; /*!< RESEVED. */ + uint32_t bdt_stall : 1; /*!< Stall. */ + uint32_t dts : 1; /*!< Data shift sync. */ + uint32_t ninc : 1; /*!< DMA addr cannot increasing. */ + uint32_t keep : 1; /*!< Keep BD held by USB. */ + uint32_t data : 1; /*!< DATA0 or DATA1. */ + uint32_t own : 1; /*!< Owner, 0 is CPU, 1 is USB. */ + uint32_t reserved1 : 8; /*!< RESEVED. */ + uint32_t bc : 10; /*!< Packet size. */ + uint32_t reserved2 : 6; /*!< RESEVED. */ + }; + struct + { + uint32_t reserved3 : 2; /*!< RESEVED. */ + uint32_t tok_pid : 4; /*!< Token pid. */ + uint32_t reserved4 : 26; /*!< RESEVED. */ + }; + }; + uint32_t addr; /*!< Buffer addr. */ +} kinetis_bd_t; + +/*! + * @brief This type of structure instance is used to implement the buffer descriptor table for USB. + */ +typedef union { + kinetis_bd_t table[16][2][2]; /*!< [EndPoint] [Direction] [Odd_Even]. */ + uint8_t buffer[512]; /*!< buffer. */ +} kinetis_bd_table_t; + +/** + * @brief USBFS TokenPid type. + */ +typedef enum { + USB_TOKEN_PID_OUT = 0x1u, /*!< USB Token Pid: OUT. */ + USB_TOKEN_PID_IN = 0x9u, /*!< USB Token Pid: IN. */ + USB_TOKEN_PID_SETUP = 0xDu, /*!< USB Token Pid: SETUP. */ + USB_TOKEN_PID_DATA0 = 0x03, /*!< USB Token Pid: DATA0. */ + USB_TOKEN_PID_DATA1 = 0x0B, /*!< USB Token Pid: DATA1. */ + USB_TOKEN_PID_ACK = 0x02, /*!< USB Token Pid: ACK. */ + USB_TOKEN_PID_STALL = 0x0E, /*!< USB Token Pid: STALL. */ + USB_TOKEN_PID_NAK = 0x0A, /*!< USB Token Pid: NAK. */ + USB_TOKEN_PID_BUSTIMEOUT = 0x00, /*!< USB Token Pid: BUSTO. */ + USB_TOKEN_PID_ERR = 0x0f, /*!< USB Token Pid: ERR. */ +} USB_TOKEN_PID_Type; + +typedef struct { + KINETIS_TypeDef base; + __IO uint8_t USBCTRL; /**< USB Control, offset: 0x100 */ + uint8_t RESERVED_22[3]; + __I uint8_t OBSERVE; /**< USB OTG Observe, offset: 0x104 */ + uint8_t RESERVED_23[3]; + __IO uint8_t CONTROL; /**< USB OTG Control, offset: 0x108 */ + uint8_t RESERVED_24[3]; + __IO uint8_t USBTRC0; /**< USB Transceiver Control 0, offset: 0x10C */ + uint8_t RESERVED_25[7]; + __IO uint8_t USBFRMADJUST; /**< Frame Adjust, offset: 0x114 */ + uint8_t RESERVED_26[15]; + __IO uint8_t KEEP_ALIVE_CTRL; /**< Keep Alive Mode Control, offset: 0x124 */ + uint8_t RESERVED_27[3]; + __IO uint8_t KEEP_ALIVE_WKCTRL; /**< Keep Alive Mode Wakeup Control, offset: 0x128 */ + uint8_t RESERVED_28[3]; + __IO uint8_t MISCCTRL; /**< Miscellaneous Control, offset: 0x12C */ + uint8_t RESERVED_29[3]; + __IO uint8_t STALL_IL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction, offset: 0x130 */ + uint8_t RESERVED_30[3]; + __IO uint8_t STALL_IH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction, offset: 0x134 */ + uint8_t RESERVED_31[3]; + __IO uint8_t STALL_OL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction, offset: 0x138 */ + uint8_t RESERVED_32[3]; + __IO uint8_t STALL_OH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction, offset: 0x13C */ + uint8_t RESERVED_33[3]; + __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock Recovery Control, offset: 0x140 */ + uint8_t RESERVED_34[3]; + __IO uint8_t CLK_RECOVER_IRC_EN; /**< FIRC Oscillator Enable, offset: 0x144 */ + uint8_t RESERVED_35[15]; + __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock Recovery Combined Interrupt Enable, offset: 0x154 */ + uint8_t RESERVED_36[7]; + __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock Recovery Separated Interrupt Status, offset: 0x15C */ +} KINETIS_MCX_TypeDef; + +void usb_dc_low_level_init(uint8_t busid); +void usb_dc_low_level_deinit(uint8_t busid); + +void usbd_kinetis_delay_ms(uint8_t ms); +#endif \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_dc_musb.c b/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_dc_musb.c index d66ec39..845e583 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_dc_musb.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_dc_musb.c @@ -273,7 +273,7 @@ int usb_dc_init(uint8_t busid) } /* Enable USB interrupts */ - HWREGB(USB_BASE + MUSB_IE_OFFSET) = USB_IE_RESET; + HWREGB(USB_BASE + MUSB_IE_OFFSET) = USB_IE_RESET | USB_IE_SUSPND | USB_IE_RESUME; HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = USB_TXIE_EP0; HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0; @@ -296,6 +296,14 @@ int usbd_set_address(uint8_t busid, const uint8_t addr) return 0; } +int usbd_set_remote_wakeup(uint8_t busid) +{ + HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_RESUME; + usbd_musb_delay_ms(10); + HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~USB_POWER_RESUME; + return 0; +} + uint8_t usbd_get_port_speed(uint8_t busid) { uint8_t speed = USB_SPEED_UNKNOWN; @@ -501,6 +509,26 @@ int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) { + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (USB_EP_DIR_IS_OUT(ep)) { + if(HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } + } else { + if(HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } + } + musb_set_active_ep(old_ep_idx); return 0; } @@ -706,9 +734,11 @@ void USBD_IRQHandler(uint8_t busid) } if (is & USB_IS_RESUME) { + usbd_event_resume_handler(0); } if (is & USB_IS_SUSPEND) { + usbd_event_suspend_handler(0); } txis &= HWREGH(USB_BASE + MUSB_TXIE_OFFSET); diff --git a/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_glue_bk.c b/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_glue_bk.c index 7eb987f..2af1e36 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_glue_bk.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_glue_bk.c @@ -277,6 +277,11 @@ void usb_dc_low_level_deinit(void) sys_drv_dev_clk_pwr_up(CLK_PWR_ID_USB_1, CLK_PWR_CTRL_PWR_DOWN); } +void usbd_musb_delay_ms(uint8_t ms) +{ + /* implement later */ +} + extern void USBH_IRQHandler(uint8_t busid); void USBH_IRQ(void) diff --git a/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_glue_es.c b/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_glue_es.c index adfc293..b1a8f8e 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_glue_es.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_glue_es.c @@ -50,4 +50,9 @@ uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) uint32_t usb_get_musb_ram_size(void) { return 4096; -} \ No newline at end of file +} + +void usbd_musb_delay_ms(uint8_t ms) +{ + /* implement later */ +} diff --git a/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_glue_sunxi.c b/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_glue_sunxi.c index 4339230..706a60c 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_glue_sunxi.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_glue_sunxi.c @@ -56,4 +56,9 @@ uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) uint32_t usb_get_musb_ram_size(void) { return 8192; -} \ No newline at end of file +} + +void usbd_musb_delay_ms(uint8_t ms) +{ + /* implement later */ +} diff --git a/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_hc_musb.c b/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_hc_musb.c index b5d7e36..39c787f 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_hc_musb.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_hc_musb.c @@ -475,10 +475,12 @@ static void musb_pipe_free(struct musb_pipe *pipe) __WEAK void usb_hc_low_level_init(struct usbh_bus *bus) { + (void)bus; } __WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus) { + (void)bus; } int usb_hc_init(struct usbh_bus *bus) @@ -653,6 +655,7 @@ int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, u } } + status |= (1 << HUB_PORT_FEATURE_POWER); memcpy(buf, &status, 4); break; default: diff --git a/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_musb_reg.h b/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_musb_reg.h index 885bdd4..1776537 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_musb_reg.h +++ b/rt-thread/components/drivers/usb/cherryusb/port/musb/usb_musb_reg.h @@ -3882,5 +3882,6 @@ struct musb_fifo_cfg { uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg); uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg); uint32_t usb_get_musb_ram_size(void); +void usbd_musb_delay_ms(uint8_t ms); #endif diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ohci/README.md b/rt-thread/components/drivers/usb/cherryusb/port/ohci/README.md index 34e753c..928eb0c 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/ohci/README.md +++ b/rt-thread/components/drivers/usb/cherryusb/port/ohci/README.md @@ -1,18 +1,23 @@ # Note -This OHCI is a companion controller of EHCI. +This OHCI is a companion controller of EHCI. But you can use OHCI only without CONFIG_USB_EHCI_WITH_OHCI definition. + +**And you need to pay for using OHCI driver**. ## Support Chip List ### AllwinnerTech -- F133 +- F133(EHCI + OHCI) ### Nuvoton -- Nuvoton all series +- Nuvoton all series(EHCI + OHCI, OHCI only) ### Artinchip -- d13x, d21x +- d13x, d21x(EHCI + OHCI) +### NXP + +- LPC4X/LPC5X(OHCI only) \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_glue_lpc.c b/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_glue_lpc.c new file mode 100644 index 0000000..51ab781 --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_glue_lpc.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "fsl_device_registers.h" +#include "fsl_power.h" +#include "usbh_core.h" + +#if defined(CONFIG_USB_EHCI_WITH_OHCI) +#error "lpc does not have ehci" +#endif + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ +#if ((defined FSL_FEATURE_SOC_SYSMPU_COUNT) && (FSL_FEATURE_SOC_SYSMPU_COUNT)) + SYSMPU_Enable(SYSMPU, 0); +#endif /* FSL_FEATURE_SOC_SYSMPU_COUNT */ + + NVIC_ClearPendingIRQ(USB0_IRQn); + NVIC_ClearPendingIRQ(USB0_NEEDCLK_IRQn); + + POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*< Turn on USB0 Phy */ + + RESET_PeripheralReset(kUSB0D_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSB0HSL_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSB0HMR_RST_SHIFT_RSTn); + + CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbfsSrcPll1, 48000000U); + + NVIC_SetPriority(USB0_IRQn, 3); + EnableIRQ(USB0_IRQn); +} + + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + DisableIRQ(USB0_IRQn); +} + +void USB0_IRQHandler(void) +{ + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler(0); +} \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.c b/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.c index b3d6582..2bec2a0 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.c +++ b/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.c @@ -3,19 +3,59 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include "usb_ohci_priv.h" -#include "usb_ehci_priv.h" +#include "usb_hc_ohci.h" + +/* Frame Interval / Periodic Start. + * + * At 12Mbps, there are 12000 bit time in each 1Msec frame. + */ + +#define OHCI_FMINTERVAL_FI (12000 - 1) +#define OHCI_FMINTERVAL_FSMPS ((6 * (OHCI_FMINTERVAL_FI - 210)) / 7) +#define DEFAULT_FMINTERVAL ((OHCI_FMINTERVAL_FSMPS << OHCI_FMINT_FSMPS_SHIFT) | OHCI_FMINTERVAL_FI) +#define DEFAULT_PERSTART ((OHCI_FMINTERVAL_FI * 9) / 10) + +struct ohci_hcd g_ohci_hcd[CONFIG_USBHOST_MAX_BUS]; + +USB_NOCACHE_RAM_SECTION struct ohci_ed_hw g_ohci_ed_pool[CONFIG_USBHOST_MAX_BUS][CONFIG_USB_OHCI_ED_NUM]; +USB_NOCACHE_RAM_SECTION struct ohci_hcca ohci_hcca[CONFIG_USBHOST_MAX_BUS]; int ohci_init(struct usbh_bus *bus) { volatile uint32_t timeout = 0; uint32_t regval; + struct ohci_ed_hw *ed; + + memset(&g_ohci_hcd[bus->hcd.hcd_id], 0, sizeof(struct ohci_hcd)); + memset(g_ohci_ed_pool[bus->hcd.hcd_id], 0, sizeof(struct ohci_ed_hw) * CONFIG_USB_OHCI_ED_NUM); + + for (uint32_t i = 0; i < 32; i++) { + ohci_hcca[bus->hcd.hcd_id].inttbl[i] = 0; + } + + for (uint8_t index = 0; index < CONFIG_USB_OHCI_ED_NUM; index++) { + ed = &g_ohci_ed_pool[bus->hcd.hcd_id][index]; + if ((uint32_t)&ed->hw % 32) { + USB_LOG_ERR("struct ohci_ed_hw is not align 32\r\n"); + return -USB_ERR_INVAL; + } + for (uint8_t i = 0; i < CONFIG_USB_OHCI_TD_NUM; i++) { + if ((uint32_t)&ed->td_pool[i] % 32) { + USB_LOG_ERR("struct ohci_td_hw is not align 32\r\n"); + return -USB_ERR_INVAL; + } + } + } + + for (uint8_t index = 0; index < CONFIG_USB_OHCI_ED_NUM; index++) { + ed = &g_ohci_ed_pool[bus->hcd.hcd_id][index]; + ed->waitsem = usb_osal_sem_create(0); + } USB_LOG_INFO("OHCI hcrevision:0x%02x\r\n", (unsigned int)OHCI_HCOR->hcrevision); + OHCI_HCOR->hcintdis = OHCI_INT_MIE; OHCI_HCOR->hccontrol = 0; - OHCI_HCOR->hccontrolheaded = 0; - OHCI_HCOR->hcbulkheaded = 0; OHCI_HCOR->hccmdsts = OHCI_CMDST_HCR; while (OHCI_HCOR->hccmdsts & OHCI_CMDST_HCR) { @@ -26,45 +66,39 @@ int ohci_init(struct usbh_bus *bus) } } - /* Frame Interval / Periodic Start. - * - * At 12Mbps, there are 12000 bit time in each 1Msec frame. - */ - -#define BITS_PER_FRAME 12000 -#define FI (BITS_PER_FRAME - 1) -#define FSMPS ((6 * (FI - 210)) / 7) -#define DEFAULT_FMINTERVAL ((FSMPS << OHCI_FMINT_FSMPS_SHIFT) | FI) -#define DEFAULT_PERSTART (((9 * BITS_PER_FRAME) / 10) - 1) - OHCI_HCOR->hcfminterval = DEFAULT_FMINTERVAL; OHCI_HCOR->hcperiodicstart = DEFAULT_PERSTART; + OHCI_HCOR->hclsthreshold = 0x628; - /* Put HC in operational state */ - regval = OHCI_HCOR->hccontrol; - regval &= ~OHCI_CTRL_HCFS_MASK; - regval |= OHCI_CTRL_HCFS_OPER; - OHCI_HCOR->hccontrol = regval; - - /* Set global power in HcRhStatus */ - OHCI_HCOR->hcrhsts = OHCI_RHSTATUS_SGP; - - /* Set HCCA base address */ - OHCI_HCOR->hchcca = 0; + OHCI_HCOR->hccontrolheaded = 0; + OHCI_HCOR->hcbulkheaded = 0; + OHCI_HCOR->hchcca = (uintptr_t)&ohci_hcca[bus->hcd.hcd_id]; /* Clear pending interrupts */ regval = OHCI_HCOR->hcintsts; OHCI_HCOR->hcintsts = regval; - for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_pcc; port++) { - regval = OHCI_HCOR->hcrhportsts[port]; - regval |= OHCI_RHPORTST_PPS; - OHCI_HCOR->hcrhportsts[port] = regval; - } + /* Put HC in operational state */ + regval = OHCI_HCOR->hccontrol; + regval &= ~OHCI_CTRL_CBSR; + regval &= ~OHCI_CTRL_HCFS_MASK; + regval |= OHCI_CTRL_HCFS_OPER; + regval |= OHCI_CTRL_CBSR; + regval |= OHCI_CTRL_CLE; + OHCI_HCOR->hccontrol = regval; + + g_ohci_hcd[bus->hcd.hcd_id].n_ports = OHCI_HCOR->hcrhdescriptora & OHCI_RHDESCA_NDP_MASK; + USB_LOG_INFO("OHCI n_ports:%d\r\n", g_ohci_hcd[bus->hcd.hcd_id].n_ports); + + OHCI_HCOR->hcrhdescriptora &= ~OHCI_RHDESCA_PSM; + OHCI_HCOR->hcrhdescriptora &= ~OHCI_RHDESCA_NPS; + + /* Set global power in HcRhStatus */ + OHCI_HCOR->hcrhsts = OHCI_RHSTATUS_SGP; + usb_osal_msleep(20); /* Enable OHCI interrupts */ - OHCI_HCOR->hcinten = OHCI_INT_SO | OHCI_INT_RD | OHCI_INT_UE | OHCI_INT_OC | - OHCI_INT_WDH | OHCI_INT_RHSC | OHCI_INT_MIE; + OHCI_HCOR->hcinten = OHCI_INT_WDH | OHCI_INT_RHSC | OHCI_INT_MIE; return 0; } @@ -72,15 +106,25 @@ int ohci_init(struct usbh_bus *bus) int ohci_deinit(struct usbh_bus *bus) { uint32_t regval; + struct ohci_ed_hw *ed; /* Disable OHCI interrupts */ - OHCI_HCOR->hcintdis = OHCI_INT_SO | OHCI_INT_RD | OHCI_INT_UE | OHCI_INT_OC | - OHCI_INT_WDH | OHCI_INT_RHSC | OHCI_INT_MIE; + OHCI_HCOR->hcintdis = OHCI_INT_WDH | OHCI_INT_RHSC | OHCI_INT_MIE; - for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_pcc; port++) { - regval = OHCI_HCOR->hcrhportsts[port]; - regval &= ~OHCI_RHPORTST_PPS; - OHCI_HCOR->hcrhportsts[port] = regval; + /* Clear pending interrupts */ + regval = OHCI_HCOR->hcintsts; + OHCI_HCOR->hcintsts = regval; + + OHCI_HCOR->hcrhsts &= ~OHCI_RHSTATUS_SGP; + + regval = OHCI_HCOR->hccontrol; + regval &= ~OHCI_CTRL_HCFS_MASK; + regval |= OHCI_CTRL_HCFS_SUSPEND; + OHCI_HCOR->hccontrol = regval; + + for (uint8_t index = 0; index < CONFIG_USB_OHCI_ED_NUM; index++) { + ed = &g_ohci_ed_pool[bus->hcd.hcd_id][index]; + usb_osal_sem_delete(ed->waitsem); } return 0; @@ -97,7 +141,7 @@ int ohci_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, u uint8_t port; uint32_t temp; - nports = g_ehci_hcd[bus->hcd.hcd_id].n_pcc; + nports = g_ohci_hcd[bus->hcd.hcd_id].n_ports; port = setup->wIndex; if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) { @@ -139,28 +183,46 @@ int ohci_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, u switch (setup->wValue) { case HUB_PORT_FEATURE_ENABLE: + temp = OHCI_RHPORTST_CCS; break; case HUB_PORT_FEATURE_SUSPEND: + temp = OHCI_HCOR->hccontrol; + temp &= ~OHCI_CTRL_HCFS_MASK; + temp |= OHCI_CTRL_HCFS_RESUME; + OHCI_HCOR->hccontrol = temp; + usb_osal_msleep(20); + + temp = OHCI_HCOR->hccontrol; + temp &= ~OHCI_CTRL_HCFS_MASK; + temp |= OHCI_CTRL_HCFS_OPER; + OHCI_HCOR->hccontrol = temp; + + temp = OHCI_RHPORTST_POCI; + break; case HUB_PORT_FEATURE_C_SUSPEND: + temp = OHCI_RHPORTST_PSSC; break; case HUB_PORT_FEATURE_POWER: + OHCI_HCOR->hcrhsts = OHCI_RHSTATUS_CGP; + temp = OHCI_RHPORTST_LSDA; break; case HUB_PORT_FEATURE_C_CONNECTION: - OHCI_HCOR->hcrhportsts[port - 1] |= OHCI_RHPORTST_CSC; + temp = OHCI_RHPORTST_CSC; break; case HUB_PORT_FEATURE_C_ENABLE: - OHCI_HCOR->hcrhportsts[port - 1] |= OHCI_RHPORTST_PESC; + temp = OHCI_RHPORTST_PESC; break; case HUB_PORT_FEATURE_C_OVER_CURREN: - OHCI_HCOR->hcrhportsts[port - 1] |= OHCI_RHPORTST_OCIC; + temp = OHCI_RHPORTST_OCIC; break; case HUB_PORT_FEATURE_C_RESET: - OHCI_HCOR->hcrhportsts[port - 1] |= OHCI_RHPORTST_PRSC; + temp = OHCI_RHPORTST_PRSC; break; default: return -USB_ERR_NOTSUPP; } + OHCI_HCOR->hcrhportsts[port - 1] = temp; break; case HUB_REQUEST_SET_FEATURE: if (!port || port > nports) { @@ -169,11 +231,17 @@ int ohci_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, u switch (setup->wValue) { case HUB_PORT_FEATURE_SUSPEND: + temp = OHCI_HCOR->hccontrol; + temp &= ~OHCI_CTRL_HCFS_MASK; + temp |= OHCI_CTRL_HCFS_SUSPEND; + OHCI_HCOR->hccontrol = temp; + break; case HUB_PORT_FEATURE_POWER: + OHCI_HCOR->hcrhsts = OHCI_RHSTATUS_SGP; break; case HUB_PORT_FEATURE_RESET: - OHCI_HCOR->hcrhportsts[port - 1] |= OHCI_RHPORTST_PRS; + OHCI_HCOR->hcrhportsts[port - 1] = OHCI_RHPORTST_PRS; while (OHCI_HCOR->hcrhportsts[port - 1] & OHCI_RHPORTST_PRS) { } @@ -188,7 +256,6 @@ int ohci_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, u return -USB_ERR_INVAL; } temp = OHCI_HCOR->hcrhportsts[port - 1]; - memcpy(buf, &temp, 4); break; default: @@ -216,9 +283,9 @@ void OHCI_IRQHandler(uint8_t busid) bus = &g_usbhost_bus[busid]; usbsts = OHCI_HCOR->hcintsts & OHCI_HCOR->hcinten; - OHCI_HCOR->hcintsts = usbsts; if (usbsts & OHCI_INT_RHSC) { + OHCI_HCOR->hcintsts = OHCI_INT_RHSC; for (int port = 0; port < CONFIG_USBHOST_MAX_RHPORTS; port++) { uint32_t portsc = OHCI_HCOR->hcrhportsts[port]; @@ -236,5 +303,51 @@ void OHCI_IRQHandler(uint8_t busid) } } if (usbsts & OHCI_INT_WDH) { + OHCI_HCOR->hcintsts = OHCI_INT_WDH; } -} \ No newline at end of file +} + +#ifndef CONFIG_USB_EHCI_WITH_OHCI +__WEAK void usb_hc_low_level_init(struct usbh_bus *bus) +{ + (void)bus; +} + +__WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + (void)bus; +} + +int usb_hc_init(struct usbh_bus *bus) +{ + usb_hc_low_level_init(bus); + return ohci_init(bus); +} + +int usb_hc_deinit(struct usbh_bus *bus) +{ + ohci_deinit(bus); + usb_hc_low_level_deinit(bus); + return 0; +} + +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf) +{ + return ohci_roothub_control(bus, setup, buf); +} + +int usbh_submit_urb(struct usbh_urb *urb) +{ + return ohci_submit_urb(urb); +} + +int usbh_kill_urb(struct usbh_urb *urb) +{ + return ohci_kill_urb(urb); +} + +void USBH_IRQHandler(uint8_t busid) +{ + OHCI_IRQHandler(busid); +} +#endif \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.h b/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.h index 030350e..19d5190 100644 --- a/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.h +++ b/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.h @@ -1,484 +1,56 @@ -/**************************************************************************** - * include/nuttx/usb/ohci.h +/* + * Copyright (c) 2024, sakumisu * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __INCLUDE_NUTTX_USB_OHCI_H -#define __INCLUDE_NUTTX_USB_OHCI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register offsets *********************************************************/ - -/* Control and status registers (section 7.1) */ - -#define OHCI_HCIREV_OFFSET 0x0000 /* HcRevision: Version of HCI specification */ -#define OHCI_CTRL_OFFSET 0x0004 /* HcControl: HC control */ -#define OHCI_CMDST_OFFSET 0x0008 /* HcCommandStatus: HC command status */ -#define OHCI_INTST_OFFSET 0x000c /* HcInterruptStatus: HC interrupt status */ -#define OHCI_INTEN_OFFSET 0x0010 /* HcInterruptEnable: HC interrupt enable */ -#define OHCI_INTDIS_OFFSET 0x0014 /* HcInterruptDisable: HC interrupt disable */ - -/* Memory pointer registers (section 7.2) */ - -#define OHCI_HCCA_OFFSET 0x0018 /* HcHCCA: HC communication area */ -#define OHCI_PERED_OFFSET 0x001c /* HcPeriodCurrentED: Current isoc or int endpoint desc */ -#define OHCI_CTRLHEADED_OFFSET 0x0020 /* HcControlHeadED: First EP desc in the control list */ -#define OHCI_CTRLED_OFFSET 0x0024 /* HcControlCurrentED: Current EP desc in the control list */ -#define OHCI_BULKHEADED_OFFSET 0x0028 /* HcBulkHeadED: First EP desc in the bulk list */ -#define OHCI_BULKED_OFFSET 0x002c /* HcBulkCurrentED: Current EP desc in the bulk list */ -#define OHCI_DONEHEAD_OFFSET 0x0030 /* HcDoneHead: Last transfer desc added to DONE queue */ - -/* Frame counter registers (section 7.3) */ - -#define OHCI_FMINT_OFFSET 0x0034 /* HcFmInterval: Bit time interval that would not cause overrun */ -#define OHCI_FMREM_OFFSET 0x0038 /* HcFmRemaining: Bit time remaining in current frame */ -#define OHCI_FMNO_OFFSET 0x003c /* HcFmNumber: Frame number counter */ -#define OHCI_PERSTART_OFFSET 0x0040 /* HcPeriodicStart: Time to start processing periodic list */ - -/* Root hub registers (section 7.4) */ - -#define OHCI_LSTHRES_OFFSET 0x0044 /* HcLSThreshold: Commit to transfer threshold */ -#define OHCI_RHDESCA_OFFSET 0x0048 /* HcRhDescriptorA: Describes root hub (part A) */ -#define OHCI_RHDESCB_OFFSET 0x004c /* HcRhDescriptorB: Describes root hub (part B) */ -#define OHCI_RHSTATUS_OFFSET 0x0050 /* HcRhStatus: Root hub status */ - -#define OHCI_MAX_RHPORT 15 /* Maximum number of OHCI root hub ports */ - -#define OHCI_RHPORTST_OFFSET(n) (0x0054 + (((n) - 1) << 2)) -#define OHCI_RHPORTST1_OFFSET 0x0054 /* HcRhPort1Status: Root hub port status 1 */ -#define OHCI_RHPORTST2_OFFSET 0x0058 /* HcRhPort2Status: Root hub port status 2 */ -#define OHCI_RHPORTST3_OFFSET 0x005c /* HcRhPort3Status: Root hub port status 3 */ -#define OHCI_RHPORTST4_OFFSET 0x0060 /* HcRhPort4Status: Root hub port status 4 */ -#define OHCI_RHPORTST5_OFFSET 0x0064 /* HcRhPort5Status: Root hub port status 5 */ -#define OHCI_RHPORTST6_OFFSET 0x0068 /* HcRhPort6Status: Root hub port status 6 */ -#define OHCI_RHPORTST7_OFFSET 0x006c /* HcRhPort7Status: Root hub port status 7 */ -#define OHCI_RHPORTST8_OFFSET 0x0070 /* HcRhPort8Status: Root hub port status 8 */ -#define OHCI_RHPORTST9_OFFSET 0x0074 /* HcRhPort9Status: Root hub port status 9 */ -#define OHCI_RHPORTST10_OFFSET 0x0078 /* HcRhPort10Status: Root hub port status 10 */ -#define OHCI_RHPORTST11_OFFSET 0x007c /* HcRhPort11Status: Root hub port status 11 */ -#define OHCI_RHPORTST12_OFFSET 0x0080 /* HcRhPort12Status: Root hub port status 12 */ -#define OHCI_RHPORTST13_OFFSET 0x0084 /* HcRhPort13Status: Root hub port status 13 */ -#define OHCI_RHPORTST14_OFFSET 0x0088 /* HcRhPort14Status: Root hub port status 14 */ -#define OHCI_RHPORTST15_OFFSET 0x008c /* HcRhPort15Status: Root hub port status 15 */ - -/* Register bit definitions *************************************************/ - -/* HcRevision: Version of HCI specification (7.1.1) */ - -#define OHCI_HCIREV_SHIFT (0) /* Bits 0-7: HCI spec version (BCD) */ -#define OHCI_HCIREV_MASK (0xff << OHCI_HCIREV_SHIFT) - -/* HcControl: HC control (7.1.2) */ - -#define OHCI_CTRL_CBSR (3 << 0) /* Bit 0: Control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* Bit 1: Periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* Bit 2: Isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* Bit 3: Control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* Bit 4: Bulk list enable */ -#define OHCI_CTRL_HCFS_SHIFT (6) /* Bits 6-7: Host controller functional state */ -#define OHCI_CTRL_HCFS_MASK (3 << OHCI_CTRL_HCFS_SHIFT) -# define OHCI_CTRL_HCFS_RESET (0 << OHCI_CTRL_HCFS_SHIFT) -# define OHCI_CTRL_HCFS_RESUME (1 << OHCI_CTRL_HCFS_SHIFT) -# define OHCI_CTRL_HCFS_OPER (2 << OHCI_CTRL_HCFS_SHIFT) -# define OHCI_CTRL_HCFS_SUSPEND (3 << OHCI_CTRL_HCFS_SHIFT) -#define OHCI_CTRL_IR (1 << 8) /* Bit 8: Interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* Bit 9: Remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* Bit 10: Remote wakeup enable */ - /* Bits 11-31: Reserved */ - -/* HcCommandStatus: HC command status (7.1.3) */ - -#define OHCI_CMDST_HCR (1 << 0) /* Bit 0: Host controller reset */ -#define OHCI_CMDST_CLF (1 << 1) /* Bit 1: Control list filled */ -#define OHCI_CMDST_BLF (1 << 2) /* Bit 2: Bulk list filled */ -#define OHCI_CMDST_OCR (1 << 3) /* Bit 3: Ownership change request */ - /* Bits 4-15: Reserved */ -#define OHCI_CMDST_SOC (3 << 16) /* Bit 16: Scheduling overrun count */ - /* Bits 17-31: Reserved */ - -/* HcInterruptStatus: HC interrupt status (7.1.4), - * HcInterruptEnable: HC interrupt enable (7.1.5), and - * HcInterruptDisable: HC interrupt disable (7.1.6) + * SPDX-License-Identifier: Apache-2.0 */ +#ifndef _USB_OHCI_PRIV_H +#define _USB_OHCI_PRIV_H -#define OHCI_INT_SO (1 << 0) /* Bit 0: Scheduling overrun */ -#define OHCI_INT_WDH (1 << 1) /* Bit 1: Writeback done head */ -#define OHCI_INT_SF (1 << 2) /* Bit 2: Start of frame */ -#define OHCI_INT_RD (1 << 3) /* Bit 3: Resume detected */ -#define OHCI_INT_UE (1 << 4) /* Bit 4: Unrecoverable error */ -#define OHCI_INT_FNO (1 << 5) /* Bit 5: Frame number overflow */ -#define OHCI_INT_RHSC (1 << 6) /* Bit 6: Root hub status change */ - /* Bits 7-29: Reserved */ -#define OHCI_INT_OC (1 << 30) /* Bit 30: Ownership change */ -#define OHCI_INT_MIE (1 << 31) /* Bit 31: Master interrupt enable - * (Enable/disable only) */ +#include "usbh_core.h" +#include "usbh_hub.h" +#include "usb_ohci_reg.h" -/* HcHCCA: HC communication area (7.2.1): - * - * 32-bits aligned to 256 byte boundary. - */ +#define OHCI_HCOR ((struct ohci_hcor *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_OHCI_HCOR_OFFSET)) -/* HcPeriodCurrentED: Current isoc or int endpoint desc (7.2.2), - * HcControlHeadED: First EP desc in the control list (7.2.3), - * HcControlCurrentED: Current EP desc in the control list (7.2.4), - * HcBulkHeadED: First EP desc in the bulk list (7.2.5), - * HcBulkCurrentED: Current EP desc in the bulk list (7.2.6), and - * HcDoneHead: Last transfer desc added to DONE queue (7.2.7): - * - * All 32-bits aligned to an 8-byte boundary - */ +#define OHCI_PTR2ADDR(x) ((uint32_t)(uintptr_t)(x) & ~0x0F) +#define OHCI_ADDR2ED(x) ((struct ohci_ed_hw *)(uintptr_t)((uint32_t)(x) & ~0x0F)) +#define OHCI_ADDR2TD(x) ((struct ohci_td_hw *)(uintptr_t)((uint32_t)(x) & ~0x0F)) -/* HcFmInterval: Bit time interval that would not cause overrun (7.3.1) */ - -#define OHCI_FMINT_FI_SHIFT (0) /* Bits 0-13: Frame interval */ -#define OHCI_FMINT_FI_MASK (0x3fff << OHCI_FMINT_FI_SHIFT) - /* Bits 14-15: Reserved */ -#define OHCI_FMINT_FSMPS_SHIFT (16) /* Bits 16-30: FS largest packet data */ -#define OHCI_FMINT_FSMPS_MASK (0x7fff << OHCI_FMINT_FSMPS_SHIFT) -#define OHCI_FMINT_FIT (1 << 31) /* Bit 31: Frame interval toggle */ - -/* HcFmRemaining: Bit time remaining in current frame (7.3.2) */ - -#define OHCI_FMREM_FR_SHIFT (0) /* Bits 0-13: Frame remaining */ -#define OHCI_FMREM_FR_MASK (0x3fff << OHCI_FMREM_FR_SHIFT) - /* Bits 16-30: Reserved */ -#define OHCI_FMINT_FRT (1 << 31) /* Bit 31: Frame remaining toggle */ - -/* HcFmNumber: Frame number counter (7.3.3) */ - -#define OHCI_FMNO_FI_SHIFT (0) /* Bits 0-15: Frame number */ -#define OHCI_FMNO_FI_MASK (0xffff << OHCI_FMINT_FI_SHIFT) - /* Bits 16-31: Reserved */ - -/* HcPeriodicStart: Time to start processing periodic list (7.3.4) */ - -#define OHCI_PERSTART_SHIFT (0) /* Bits 0-13: Periodic start */ -#define OHCI_PERSTART_MASK (0x3fff << OHCI_PERSTART_SHIFT) - /* Bits 14-31: Reserved */ - -/* HcLSThreshold: Commit to transfer threshold (7.3.5) */ - -#define OHCI_LSTHRES_SHIFT (0) /* Bits 0-11: LS threshold */ -#define OHCI_LSTHRES_MASK (0x0fff << OHCI_PERSTART_SHIFT) - /* Bits 12-31: Reserved */ - -/* HcRhDescriptorN: Describes root hub (part A) (7.4.1) */ - -#define OHCI_RHDESCA_NDP_SHIFT (0) /* Bits 0-7: Number downstream ports */ -#define OHCI_RHDESCA_NDP_MASK (0xff << OHCI_RHDESCA_NDP_SHIFT) -#define OHCI_RHDESCA_PSM (1 << 8) /* Bit 8: Power switching mode */ -#define OHCI_RHDESCA_NPS (1 << 9) /* Bit 9: No power switching */ -#define OHCI_RHDESCA_DT (1 << 10) /* Bit 10: Device type */ -#define OHCI_RHDESCA_OCPM (1 << 11) /* Bit 11: Over current protection mode */ -#define OHCI_RHDESCA_NOCP (1 << 12) /* Bit 12: No over current protection */ - /* Bits 13-23: Reserved */ -#define OHCI_RHDESCA_POTPGT_SHIFT (24) /* Bits 24-31: Power on to power good time */ -#define OHCI_RHDESCA_POTPGT_MASK (0xff << OHCI_RHDESCA_POTPGT_SHIFT) - -/* HcRhDescriptorB: Describes root hub (part B) (7.4.2) */ - -#define OHCI_RHDESCB_DR_SHIFT (0) /* Bits 0-15: Device removable */ -#define OHCI_RHDESCB_DR_MASK (0xffff << OHCI_RHDESCB_DR_SHIFT) -# define OHCI_RHDESCB_ATTACHED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n))) -#define OHCI_RHDESCB_PPCM_SHIFT (16) /* Bits 16-31: Port power control mask */ -#define OHCI_RHDESCB_PPCM_MASK (0xffff << OHCI_RHDESCB_PPCM_SHIFT) -# define OHCI_RHDESCB_POWERED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n))) - -/* HcRhStatus: Root hub status (7.4.3) */ - -#define OHCI_RHSTATUS_LPS (1 << 0) /* Bit 0: Local power status (read)*/ -#define OHCI_RHSTATUS_CGP (1 << 0) /* Bit 0: Clear global power (write)*/ -#define OHCI_RHSTATUS_OCI (1 << 1) /* Bit 1: Over current indicator */ - /* Bits 2-14: Reserved */ -#define OHCI_RHSTATUS_DRWE (1 << 15) /* Bit 15: Device remote wakeup enable */ -#define OHCI_RHSTATUS_LPSC (1 << 16) /* Bit 16: Local power status change (read) */ -#define OHCI_RHSTATUS_SGP (1 << 16) /* Bit 16: Set global power (write) */ -#define OHCI_RHSTATUS_OCIC (1 << 17) /* Bit 17: Overcurrent indicator change */ - /* Bits 18-30: Reserved */ -#define OHCI_RHSTATUS_CRWE (1 << 31) /* Bit 31: Clear remote wakeup enable */ - -/* HcRhPortStatus: Root hub port status (7.4.4) */ - -#define OHCI_RHPORTST_CCS (1 << 0) /* Bit 0: Current connect status */ -#define OHCI_RHPORTST_PES (1 << 1) /* Bit 1: Port enable status */ -#define OHCI_RHPORTST_PSS (1 << 2) /* Bit 2: Port suspend status */ -#define OHCI_RHPORTST_POCI (1 << 3) /* Bit 3: Port over current indicator */ -#define OHCI_RHPORTST_PRS (1 << 4) /* Bit 4: Port reset status */ - /* Bits 5-7: Reserved */ -#define OHCI_RHPORTST_PPS (1 << 8) /* Bit 8: Port power status */ -#define OHCI_RHPORTST_LSDA (1 << 9) /* Bit 9: Low speed device attached */ - /* Bits 10-15: Reserved */ -#define OHCI_RHPORTST_CSC (1 << 16) /* Bit 16: Connect status change */ -#define OHCI_RHPORTST_PESC (1 << 17) /* Bit 17: Port enable status change */ -#define OHCI_RHPORTST_PSSC (1 << 18) /* Bit 18: Port suspend status change */ -#define OHCI_RHPORTST_OCIC (1 << 19) /* Bit 19: Port over current indicator change */ -#define OHCI_RHPORTST_PRSC (1 << 20) /* Bit 20: Port reset status change */ - /* Bits 21-31: Reserved */ - -/* Transfer Descriptors *****************************************************/ - -/* Endpoint Descriptor Offsets (4.2.1) */ - -#define ED_CONTROL_OFFSET (0x00) /* ED status/control bits */ -#define ED_TAILP_OFFSET (0x04) /* TD Queue Tail Pointer (TailP) */ -#define ED_HEADP_OFFSET (0x08) /* TD Queue Head Pointer (HeadP) */ -#define ED_NEXTED_OFFSET (0x0c) /* Next Endpoint Descriptor (NextED) */ - -/* Endpoint Descriptor Bit Definitions (4.2.2) */ - -#define ED_CONTROL_FA_SHIFT (0) /* Bits 0-6: Function Address */ -#define ED_CONTROL_FA_MASK (0x7f << ED_CONTROL_FA_SHIFT) -#define ED_CONTROL_EN_SHIFT (7) /* Bits 7-10: Endpoint number */ -#define ED_CONTROL_EN_MASK (15 << ED_CONTROL_EN_SHIFT) -#define ED_CONTROL_D_SHIFT (11) /* Bits 11-12: Direction */ -#define ED_CONTROL_D_MASK (3 << ED_CONTROL_D_SHIFT) -# define ED_CONTROL_D_TD1 (0 << ED_CONTROL_D_SHIFT) /* Get direction from TD */ -# define ED_CONTROL_D_OUT (1 << ED_CONTROL_D_SHIFT) /* OUT */ -# define ED_CONTROL_D_IN (2 << ED_CONTROL_D_SHIFT) /* IN */ -# define ED_CONTROL_D_TD2 (3 << ED_CONTROL_D_SHIFT) /* Get direction from TD */ - -#define ED_CONTROL_S (1 << 13) /* Bit 13: Speed (low) */ -#define ED_CONTROL_K (1 << 14) /* Bit 14: Skip */ -#define ED_CONTROL_F (1 << 15) /* Bit 15: Format (isochronous) */ -#define ED_CONTROL_MPS_SHIFT (16) /* Bits 16-26: Maximum packet size */ -#define ED_CONTROL_MPS_MASK (0x7ff << ED_CONTROL_MPS_SHIFT) - -#define ED_HEADP_ADDR_SHIFT (0) -#define ED_HEADP_ADDR_MASK 0xfffffff0 -#define ED_HEADP_H (1 << 0) /* Bit 0: Halted */ -#define ED_HEADP_C (1 << 1) /* Bit 1: Toggle carry */ - -/* General Transfer Descriptor Offsets (4.3.1) */ - -#define GTD_STATUS_OFFSET (0x00) /* TD status bits */ -#define GTD_CBP_OFFSET (0x04) /* Current Buffer Pointer (CBP) */ -#define GTD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */ -#define GTD_BE_OFFSET (0x0c) /* Buffer End (BE) */ - -/* General Transfer Descriptor Bit Definitions */ - - /* Bits 0-17: Reserved */ - -#define GTD_STATUS_R (1 << 18) /* Bit 18: Buffer rounding */ -#define GTD_STATUS_DP_SHIFT (19) /* Bits 19-20: Direction/PID */ -#define GTD_STATUS_DP_MASK (3 << GTD_STATUS_DP_SHIFT) -# define GTD_STATUS_DP_SETUP (0 << GTD_STATUS_DP_SHIFT) /* To endpoint */ -# define GTD_STATUS_DP_OUT (1 << GTD_STATUS_DP_SHIFT) /* To endpoint */ -# define GTD_STATUS_DP_IN (2 << GTD_STATUS_DP_SHIFT) /* From endpoint */ - -#define GTD_STATUS_DI_SHIFT (21) /* Bits 21-23: Delay input */ -#define GTD_STATUS_DI_MASK (7 << GTD_STATUS_DI_SHIFT) -#define GTD_STATUS_T_SHIFT (24) /* Bits 24-25: Data Toggle */ -#define GTD_STATUS_T_MASK (3 << GTD_STATUS_T_SHIFT) -# define GTD_STATUS_T_TOGGLE (0 << GTD_STATUS_T_SHIFT) -# define GTD_STATUS_T_DATA0 (2 << GTD_STATUS_T_SHIFT) -# define GTD_STATUS_T_DATA1 (3 << GTD_STATUS_T_SHIFT) -#define GTD_STATUS_EC_SHIFT (26) /* Bits 26-27: Error count */ -#define GTD_STATUS_EC_MASK (3 << GTD_STATUS_EC_SHIFT) -#define GTD_STATUS_CC_SHIFT (28) /* Bits 28-31: Condition code */ -#define GTD_STATUS_CC_MASK (15 << GTD_STATUS_CC_SHIFT) - -/* Isochronous Transfer Descriptor Offsets (4.3.2) */ - -#define ITD_STATUS_OFFSET (0x00) /* TD status bits */ -#define ITD_BP0_OFFSET (0x04) /* Buffer page 0 (BP0) */ -#define ITD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */ -#define ITD_BE_OFFSET (0x0c) /* Buffer End (BE) */ - -#define ITD_NPSW (8) -#define ITD_PSW0_OFFSET (0x10) /* Offset0/PSW0 */ -#define ITD_PSW1_OFFSET (0x12) /* Offset1/PSW1 */ -#define ITD_PSW2_OFFSET (0x14) /* Offset2/PSW2 */ -#define ITD_PSW3_OFFSET (0x16) /* Offset3/PSW3 */ -#define ITD_PSW4_OFFSET (0x18) /* Offset4/PSW4 */ -#define ITD_PSW5_OFFSET (0x1a) /* Offset5/PSW5 */ -#define ITD_PSW6_OFFSET (0x1c) /* Offset6/PSW6 */ -#define ITD_PSW7_OFFSET (0x1e) /* Offset7/PSW7 */ - -/* Condition codes (Table 4-7) */ - -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEMISMATCH 0x03 -#define TD_CC_STALL 0x04 -#define TD_CC_DEVNOTRESPONDING 0x05 -#define TD_CC_PIDCHECKFAILURE 0x06 -#define TD_CC_UNEXPECTEDPID 0x07 -#define TD_CC_DATAOVERRUN 0x08 -#define TD_CC_DATAUNDERRUN 0x09 -#define TD_CC_BUFFEROVERRUN 0x0c -#define TD_CC_BUFFERUNDERRUN 0x0d -#define TD_CC_NOTACCESSED 0x0f - -#define TD_CC_USER 0x10 /* For use by OHCI drivers */ - -/* Host Controller Communications Area Format (4.4.1) ***********************/ - -/* HccaInterruptTable: 32x32-bit pointers to interrupt EDs */ - -#define HCCA_INTTBL_OFFSET (0x00) -#define HCCA_INTTBL_WSIZE (32) -#define HCCA_INTTBL_BSIZE (HCCA_INTTBL_WSIZE * 4) - -/* HccaFrameNumber: Current frame number */ - -#define HCCA_FMNO_OFFSET (0x80) -#define HCCA_FMNO_BSIZE (2) - -/* HccaPad1: Zero when frame no. updated */ - -#define HCCA_PAD1_OFFSET (0x82) -#define HCCA_PAD1_BSIZE (2) - -/* HccaDoneHead: When the HC reaches the end of a frame and its deferred - * interrupt register is 0, it writes the current value of its HcDoneHead to - * this location and generates an interrupt. - * - * The LSB of HCCADoneHead may be set to 1 to indicate that an unmasked - * HcInterruptStatus was set when HccaDoneHead was written. - */ - -#define HCCA_DONEHEAD_OFFSET (0x84) -#define HCCA_DONEHEAD_BSIZE (4) - -#define HCCA_DONEHEAD_MASK 0xfffffffe -#define HCCA_DONEHEAD_INTSTA (1 << 0) - -/* 0x88: 116 bytes reserved */ - -#define HCCA_RESERVED_OFFSET (0x88) -#define HCCA_RESERVED_BSIZE (116) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -struct ohci_hcor -{ - volatile uint32_t hcrevision; /* 0x00 */ - volatile uint32_t hccontrol; /* 0x04 */ - volatile uint32_t hccmdsts; /* 0x08 */ - volatile uint32_t hcintsts; /* 0x0c */ - volatile uint32_t hcinten; /* 0x10 */ - volatile uint32_t hcintdis; /* 0x14 */ - volatile uint32_t hchcca; /* 0x18 */ - volatile uint32_t hcperiodcurrented; /* 0x1c */ - volatile uint32_t hccontrolheaded; /* 0x20 */ - volatile uint32_t hccontrolcurrented; /* 0x24 */ - volatile uint32_t hcbulkheaded; /* 0x28 */ - volatile uint32_t hcbulkcurrented; /* 0x2c */ - volatile uint32_t hcdonehead; /* 0x30 */ - volatile uint32_t hcfminterval; /* 0x34 */ - volatile uint32_t hcfmremaining; /* 0x38 */ - volatile uint32_t hcfmnumber; /* 0x3c */ - volatile uint32_t hcperiodicstart; /* 0x40 */ - volatile uint32_t hclsthreshold; /* 0x44 */ - volatile uint32_t hcrhdescriptora; /* 0x48 */ - volatile uint32_t hcrhdescriptorb; /* 0x4c */ - volatile uint32_t hcrhsts; /* 0x50 */ - volatile uint32_t hcrhportsts[15]; /* 0x54 */ -}; - -/* Endpoint Descriptor Offsets (4.2.1) */ - -struct ohci_ed_s -{ - volatile uint32_t ctrl; /* ED status/control bits */ - volatile uint32_t tailp; /* TD Queue Tail Pointer (TailP) */ - volatile uint32_t headp; /* TD Queue Head Pointer (HeadP) */ - volatile uint32_t nexted; /* Next Endpoint Descriptor (NextED) */ -}; - -/* General Transfer Descriptor (4.3.1) */ - -struct ohci_gtd_s -{ - volatile uint32_t ctrl; /* TD status/control bits */ - volatile uint32_t cbp; /* Current Buffer Pointer (CBP) */ - volatile uint32_t nexttd; /* Next TD (NextTD) */ - volatile uint32_t be; /* Buffer End (BE) */ -}; - -/* Isochronous Transfer Descriptor Offsets (4.3.2) */ - -struct ohci_itd_s -{ - volatile uint32_t ctrl; /* TD status/control bits */ - volatile uint32_t bp0; /* Buffer page 0 (BP0 */ - volatile uint32_t nexttd; /* Next TD (NextTD) */ - volatile uint32_t be; /* Buffer End (BE) */ - volatile uint16_t psw[ITD_NPSW]; /* Offset/PSW */ -}; - -/* Host Controller Communications Area Format (4.4.1) */ - -struct ohci_hcca_s -{ - /* HccaInterruptTable: 32x32-bit pointers to interrupt EDs */ - - volatile uint32_t inttbl[HCCA_INTTBL_WSIZE]; - - /* HccaFrameNumber: Current frame number and - * HccaPad1: Zero when frame no. updated - */ - - volatile uint16_t fmno; - volatile uint16_t pad1; - - /* HccaDoneHead: When the HC reaches the end of a frame and its deferred - * interrupt register is 0, it writes the current value of its HcDoneHead - * to this location and generates an interrupt. - */ - - volatile uint32_t donehead; - volatile uint8_t reserved[HCCA_RESERVED_BSIZE]; - volatile uint32_t extra; -} __attribute__((aligned(256))); - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern +#ifndef CONFIG_USB_OHCI_ED_NUM +#define CONFIG_USB_OHCI_ED_NUM CONFIG_USBHOST_PIPE_NUM +#endif +#ifndef CONFIG_USB_OHCI_TD_NUM +#define CONFIG_USB_OHCI_TD_NUM 3 #endif -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ +struct ohci_ed_hw; +struct ohci_td_hw { + struct ohci_gtd hw; + struct usbh_urb *urb; + uint32_t buf_start; + uint32_t length; +} __attribute__((aligned(32))); /* min is 16bytes, we use 32 for cacheline */ -#undef EXTERN -#ifdef __cplusplus -} -#endif +struct ohci_ed_hw { + struct ohci_ed hw; + struct ohci_td_hw td_pool[CONFIG_USB_OHCI_TD_NUM]; + uint32_t td_count; + uint8_t ed_type; + usb_osal_sem_t waitsem; +} __attribute__((aligned(32))); /* min is 16bytes, we use 32 for cacheline */ -#endif /* __INCLUDE_NUTTX_USB_OHCI_H */ +struct ohci_hcd { + bool ohci_ed_used[CONFIG_USB_OHCI_ED_NUM]; + uint8_t n_ports; +}; + +int ohci_init(struct usbh_bus *bus); +int ohci_deinit(struct usbh_bus *bus); +uint16_t ohci_get_frame_number(struct usbh_bus *bus); +int ohci_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf); +int ohci_submit_urb(struct usbh_urb *urb); +int ohci_kill_urb(struct usbh_urb *urb); + +void OHCI_IRQHandler(uint8_t busid); + +#endif \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_ohci_priv.h b/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_ohci_priv.h deleted file mode 100644 index 4404dc2..0000000 --- a/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_ohci_priv.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2024, sakumisu - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _USB_OHCI_PRIV_H -#define _USB_OHCI_PRIV_H - -#include "usbh_core.h" -#include "usbh_hub.h" -#include "usb_hc_ohci.h" - -#define OHCI_HCOR ((struct ohci_hcor *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_OHCI_HCOR_OFFSET)) - -int ohci_init(struct usbh_bus *bus); -int ohci_deinit(struct usbh_bus *bus); -uint16_t ohci_get_frame_number(struct usbh_bus *bus); -int ohci_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf); -int ohci_submit_urb(struct usbh_urb *urb); -int ohci_kill_urb(struct usbh_urb *urb); - -void OHCI_IRQHandler(uint8_t busid); - -#endif \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_ohci_reg.h b/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_ohci_reg.h new file mode 100644 index 0000000..61f7f4b --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/ohci/usb_ohci_reg.h @@ -0,0 +1,484 @@ +/**************************************************************************** + * include/nuttx/usb/ohci.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_USB_OHCI_H +#define __INCLUDE_NUTTX_USB_OHCI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +/* Control and status registers (section 7.1) */ + +#define OHCI_HCIREV_OFFSET 0x0000 /* HcRevision: Version of HCI specification */ +#define OHCI_CTRL_OFFSET 0x0004 /* HcControl: HC control */ +#define OHCI_CMDST_OFFSET 0x0008 /* HcCommandStatus: HC command status */ +#define OHCI_INTST_OFFSET 0x000c /* HcInterruptStatus: HC interrupt status */ +#define OHCI_INTEN_OFFSET 0x0010 /* HcInterruptEnable: HC interrupt enable */ +#define OHCI_INTDIS_OFFSET 0x0014 /* HcInterruptDisable: HC interrupt disable */ + +/* Memory pointer registers (section 7.2) */ + +#define OHCI_HCCA_OFFSET 0x0018 /* HcHCCA: HC communication area */ +#define OHCI_PERED_OFFSET 0x001c /* HcPeriodCurrentED: Current isoc or int endpoint desc */ +#define OHCI_CTRLHEADED_OFFSET 0x0020 /* HcControlHeadED: First EP desc in the control list */ +#define OHCI_CTRLED_OFFSET 0x0024 /* HcControlCurrentED: Current EP desc in the control list */ +#define OHCI_BULKHEADED_OFFSET 0x0028 /* HcBulkHeadED: First EP desc in the bulk list */ +#define OHCI_BULKED_OFFSET 0x002c /* HcBulkCurrentED: Current EP desc in the bulk list */ +#define OHCI_DONEHEAD_OFFSET 0x0030 /* HcDoneHead: Last transfer desc added to DONE queue */ + +/* Frame counter registers (section 7.3) */ + +#define OHCI_FMINT_OFFSET 0x0034 /* HcFmInterval: Bit time interval that would not cause overrun */ +#define OHCI_FMREM_OFFSET 0x0038 /* HcFmRemaining: Bit time remaining in current frame */ +#define OHCI_FMNO_OFFSET 0x003c /* HcFmNumber: Frame number counter */ +#define OHCI_PERSTART_OFFSET 0x0040 /* HcPeriodicStart: Time to start processing periodic list */ + +/* Root hub registers (section 7.4) */ + +#define OHCI_LSTHRES_OFFSET 0x0044 /* HcLSThreshold: Commit to transfer threshold */ +#define OHCI_RHDESCA_OFFSET 0x0048 /* HcRhDescriptorA: Describes root hub (part A) */ +#define OHCI_RHDESCB_OFFSET 0x004c /* HcRhDescriptorB: Describes root hub (part B) */ +#define OHCI_RHSTATUS_OFFSET 0x0050 /* HcRhStatus: Root hub status */ + +#define OHCI_MAX_RHPORT 15 /* Maximum number of OHCI root hub ports */ + +#define OHCI_RHPORTST_OFFSET(n) (0x0054 + (((n) - 1) << 2)) +#define OHCI_RHPORTST1_OFFSET 0x0054 /* HcRhPort1Status: Root hub port status 1 */ +#define OHCI_RHPORTST2_OFFSET 0x0058 /* HcRhPort2Status: Root hub port status 2 */ +#define OHCI_RHPORTST3_OFFSET 0x005c /* HcRhPort3Status: Root hub port status 3 */ +#define OHCI_RHPORTST4_OFFSET 0x0060 /* HcRhPort4Status: Root hub port status 4 */ +#define OHCI_RHPORTST5_OFFSET 0x0064 /* HcRhPort5Status: Root hub port status 5 */ +#define OHCI_RHPORTST6_OFFSET 0x0068 /* HcRhPort6Status: Root hub port status 6 */ +#define OHCI_RHPORTST7_OFFSET 0x006c /* HcRhPort7Status: Root hub port status 7 */ +#define OHCI_RHPORTST8_OFFSET 0x0070 /* HcRhPort8Status: Root hub port status 8 */ +#define OHCI_RHPORTST9_OFFSET 0x0074 /* HcRhPort9Status: Root hub port status 9 */ +#define OHCI_RHPORTST10_OFFSET 0x0078 /* HcRhPort10Status: Root hub port status 10 */ +#define OHCI_RHPORTST11_OFFSET 0x007c /* HcRhPort11Status: Root hub port status 11 */ +#define OHCI_RHPORTST12_OFFSET 0x0080 /* HcRhPort12Status: Root hub port status 12 */ +#define OHCI_RHPORTST13_OFFSET 0x0084 /* HcRhPort13Status: Root hub port status 13 */ +#define OHCI_RHPORTST14_OFFSET 0x0088 /* HcRhPort14Status: Root hub port status 14 */ +#define OHCI_RHPORTST15_OFFSET 0x008c /* HcRhPort15Status: Root hub port status 15 */ + +/* Register bit definitions *************************************************/ + +/* HcRevision: Version of HCI specification (7.1.1) */ + +#define OHCI_HCIREV_SHIFT (0) /* Bits 0-7: HCI spec version (BCD) */ +#define OHCI_HCIREV_MASK (0xff << OHCI_HCIREV_SHIFT) + +/* HcControl: HC control (7.1.2) */ + +#define OHCI_CTRL_CBSR (3 << 0) /* Bit 0: Control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* Bit 2: Periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* Bit 3: Isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* Bit 4: Control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* Bit 5: Bulk list enable */ +#define OHCI_CTRL_HCFS_SHIFT (6) /* Bits 6-7: Host controller functional state */ +#define OHCI_CTRL_HCFS_MASK (3 << OHCI_CTRL_HCFS_SHIFT) +# define OHCI_CTRL_HCFS_RESET (0 << OHCI_CTRL_HCFS_SHIFT) +# define OHCI_CTRL_HCFS_RESUME (1 << OHCI_CTRL_HCFS_SHIFT) +# define OHCI_CTRL_HCFS_OPER (2 << OHCI_CTRL_HCFS_SHIFT) +# define OHCI_CTRL_HCFS_SUSPEND (3 << OHCI_CTRL_HCFS_SHIFT) +#define OHCI_CTRL_IR (1 << 8) /* Bit 8: Interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* Bit 9: Remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* Bit 10: Remote wakeup enable */ + /* Bits 11-31: Reserved */ + +/* HcCommandStatus: HC command status (7.1.3) */ + +#define OHCI_CMDST_HCR (1 << 0) /* Bit 0: Host controller reset */ +#define OHCI_CMDST_CLF (1 << 1) /* Bit 1: Control list filled */ +#define OHCI_CMDST_BLF (1 << 2) /* Bit 2: Bulk list filled */ +#define OHCI_CMDST_OCR (1 << 3) /* Bit 3: Ownership change request */ + /* Bits 4-15: Reserved */ +#define OHCI_CMDST_SOC (3 << 16) /* Bit 16: Scheduling overrun count */ + /* Bits 17-31: Reserved */ + +/* HcInterruptStatus: HC interrupt status (7.1.4), + * HcInterruptEnable: HC interrupt enable (7.1.5), and + * HcInterruptDisable: HC interrupt disable (7.1.6) + */ + +#define OHCI_INT_SO (1 << 0) /* Bit 0: Scheduling overrun */ +#define OHCI_INT_WDH (1 << 1) /* Bit 1: Writeback done head */ +#define OHCI_INT_SF (1 << 2) /* Bit 2: Start of frame */ +#define OHCI_INT_RD (1 << 3) /* Bit 3: Resume detected */ +#define OHCI_INT_UE (1 << 4) /* Bit 4: Unrecoverable error */ +#define OHCI_INT_FNO (1 << 5) /* Bit 5: Frame number overflow */ +#define OHCI_INT_RHSC (1 << 6) /* Bit 6: Root hub status change */ + /* Bits 7-29: Reserved */ +#define OHCI_INT_OC (1 << 30) /* Bit 30: Ownership change */ +#define OHCI_INT_MIE (1 << 31) /* Bit 31: Master interrupt enable + * (Enable/disable only) */ + +/* HcHCCA: HC communication area (7.2.1): + * + * 32-bits aligned to 256 byte boundary. + */ + +/* HcPeriodCurrentED: Current isoc or int endpoint desc (7.2.2), + * HcControlHeadED: First EP desc in the control list (7.2.3), + * HcControlCurrentED: Current EP desc in the control list (7.2.4), + * HcBulkHeadED: First EP desc in the bulk list (7.2.5), + * HcBulkCurrentED: Current EP desc in the bulk list (7.2.6), and + * HcDoneHead: Last transfer desc added to DONE queue (7.2.7): + * + * All 32-bits aligned to an 8-byte boundary + */ + +/* HcFmInterval: Bit time interval that would not cause overrun (7.3.1) */ + +#define OHCI_FMINT_FI_SHIFT (0) /* Bits 0-13: Frame interval */ +#define OHCI_FMINT_FI_MASK (0x3fff << OHCI_FMINT_FI_SHIFT) + /* Bits 14-15: Reserved */ +#define OHCI_FMINT_FSMPS_SHIFT (16) /* Bits 16-30: FS largest packet data */ +#define OHCI_FMINT_FSMPS_MASK (0x7fff << OHCI_FMINT_FSMPS_SHIFT) +#define OHCI_FMINT_FIT (1 << 31) /* Bit 31: Frame interval toggle */ + +/* HcFmRemaining: Bit time remaining in current frame (7.3.2) */ + +#define OHCI_FMREM_FR_SHIFT (0) /* Bits 0-13: Frame remaining */ +#define OHCI_FMREM_FR_MASK (0x3fff << OHCI_FMREM_FR_SHIFT) + /* Bits 16-30: Reserved */ +#define OHCI_FMINT_FRT (1 << 31) /* Bit 31: Frame remaining toggle */ + +/* HcFmNumber: Frame number counter (7.3.3) */ + +#define OHCI_FMNO_FI_SHIFT (0) /* Bits 0-15: Frame number */ +#define OHCI_FMNO_FI_MASK (0xffff << OHCI_FMINT_FI_SHIFT) + /* Bits 16-31: Reserved */ + +/* HcPeriodicStart: Time to start processing periodic list (7.3.4) */ + +#define OHCI_PERSTART_SHIFT (0) /* Bits 0-13: Periodic start */ +#define OHCI_PERSTART_MASK (0x3fff << OHCI_PERSTART_SHIFT) + /* Bits 14-31: Reserved */ + +/* HcLSThreshold: Commit to transfer threshold (7.3.5) */ + +#define OHCI_LSTHRES_SHIFT (0) /* Bits 0-11: LS threshold */ +#define OHCI_LSTHRES_MASK (0x0fff << OHCI_PERSTART_SHIFT) + /* Bits 12-31: Reserved */ + +/* HcRhDescriptorN: Describes root hub (part A) (7.4.1) */ + +#define OHCI_RHDESCA_NDP_SHIFT (0) /* Bits 0-7: Number downstream ports */ +#define OHCI_RHDESCA_NDP_MASK (0xff << OHCI_RHDESCA_NDP_SHIFT) +#define OHCI_RHDESCA_PSM (1 << 8) /* Bit 8: Power switching mode */ +#define OHCI_RHDESCA_NPS (1 << 9) /* Bit 9: No power switching */ +#define OHCI_RHDESCA_DT (1 << 10) /* Bit 10: Device type */ +#define OHCI_RHDESCA_OCPM (1 << 11) /* Bit 11: Over current protection mode */ +#define OHCI_RHDESCA_NOCP (1 << 12) /* Bit 12: No over current protection */ + /* Bits 13-23: Reserved */ +#define OHCI_RHDESCA_POTPGT_SHIFT (24) /* Bits 24-31: Power on to power good time */ +#define OHCI_RHDESCA_POTPGT_MASK (0xff << OHCI_RHDESCA_POTPGT_SHIFT) + +/* HcRhDescriptorB: Describes root hub (part B) (7.4.2) */ + +#define OHCI_RHDESCB_DR_SHIFT (0) /* Bits 0-15: Device removable */ +#define OHCI_RHDESCB_DR_MASK (0xffff << OHCI_RHDESCB_DR_SHIFT) +# define OHCI_RHDESCB_ATTACHED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n))) +#define OHCI_RHDESCB_PPCM_SHIFT (16) /* Bits 16-31: Port power control mask */ +#define OHCI_RHDESCB_PPCM_MASK (0xffff << OHCI_RHDESCB_PPCM_SHIFT) +# define OHCI_RHDESCB_POWERED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n))) + +/* HcRhStatus: Root hub status (7.4.3) */ + +#define OHCI_RHSTATUS_LPS (1 << 0) /* Bit 0: Local power status (read)*/ +#define OHCI_RHSTATUS_CGP (1 << 0) /* Bit 0: Clear global power (write)*/ +#define OHCI_RHSTATUS_OCI (1 << 1) /* Bit 1: Over current indicator */ + /* Bits 2-14: Reserved */ +#define OHCI_RHSTATUS_DRWE (1 << 15) /* Bit 15: Device remote wakeup enable */ +#define OHCI_RHSTATUS_LPSC (1 << 16) /* Bit 16: Local power status change (read) */ +#define OHCI_RHSTATUS_SGP (1 << 16) /* Bit 16: Set global power (write) */ +#define OHCI_RHSTATUS_OCIC (1 << 17) /* Bit 17: Overcurrent indicator change */ + /* Bits 18-30: Reserved */ +#define OHCI_RHSTATUS_CRWE (1 << 31) /* Bit 31: Clear remote wakeup enable */ + +/* HcRhPortStatus: Root hub port status (7.4.4) */ + +#define OHCI_RHPORTST_CCS (1 << 0) /* Bit 0: Current connect status */ +#define OHCI_RHPORTST_PES (1 << 1) /* Bit 1: Port enable status */ +#define OHCI_RHPORTST_PSS (1 << 2) /* Bit 2: Port suspend status */ +#define OHCI_RHPORTST_POCI (1 << 3) /* Bit 3: Port over current indicator */ +#define OHCI_RHPORTST_PRS (1 << 4) /* Bit 4: Port reset status */ + /* Bits 5-7: Reserved */ +#define OHCI_RHPORTST_PPS (1 << 8) /* Bit 8: Port power status */ +#define OHCI_RHPORTST_LSDA (1 << 9) /* Bit 9: Low speed device attached */ + /* Bits 10-15: Reserved */ +#define OHCI_RHPORTST_CSC (1 << 16) /* Bit 16: Connect status change */ +#define OHCI_RHPORTST_PESC (1 << 17) /* Bit 17: Port enable status change */ +#define OHCI_RHPORTST_PSSC (1 << 18) /* Bit 18: Port suspend status change */ +#define OHCI_RHPORTST_OCIC (1 << 19) /* Bit 19: Port over current indicator change */ +#define OHCI_RHPORTST_PRSC (1 << 20) /* Bit 20: Port reset status change */ + /* Bits 21-31: Reserved */ + +/* Transfer Descriptors *****************************************************/ + +/* Endpoint Descriptor Offsets (4.2.1) */ + +#define ED_CONTROL_OFFSET (0x00) /* ED status/control bits */ +#define ED_TAILP_OFFSET (0x04) /* TD Queue Tail Pointer (TailP) */ +#define ED_HEADP_OFFSET (0x08) /* TD Queue Head Pointer (HeadP) */ +#define ED_NEXTED_OFFSET (0x0c) /* Next Endpoint Descriptor (NextED) */ + +/* Endpoint Descriptor Bit Definitions (4.2.2) */ + +#define ED_CONTROL_FA_SHIFT (0) /* Bits 0-6: Function Address */ +#define ED_CONTROL_FA_MASK (0x7f << ED_CONTROL_FA_SHIFT) +#define ED_CONTROL_EN_SHIFT (7) /* Bits 7-10: Endpoint number */ +#define ED_CONTROL_EN_MASK (15 << ED_CONTROL_EN_SHIFT) +#define ED_CONTROL_D_SHIFT (11) /* Bits 11-12: Direction */ +#define ED_CONTROL_D_MASK (3 << ED_CONTROL_D_SHIFT) +# define ED_CONTROL_D_TD1 (0 << ED_CONTROL_D_SHIFT) /* Get direction from TD */ +# define ED_CONTROL_D_OUT (1 << ED_CONTROL_D_SHIFT) /* OUT */ +# define ED_CONTROL_D_IN (2 << ED_CONTROL_D_SHIFT) /* IN */ +# define ED_CONTROL_D_TD2 (3 << ED_CONTROL_D_SHIFT) /* Get direction from TD */ + +#define ED_CONTROL_SPPED_LOW (1 << 13) /* Bit 13: Speed (low) */ +#define ED_CONTROL_SKIP (1 << 14) /* Bit 14: Skip */ +#define ED_CONTROL_FORMAT_ISO (1 << 15) /* Bit 15: Format (isochronous) */ +#define ED_CONTROL_MPS_SHIFT (16) /* Bits 16-26: Maximum packet size */ +#define ED_CONTROL_MPS_MASK (0x7ff << ED_CONTROL_MPS_SHIFT) + +#define ED_HEADP_ADDR_SHIFT (0) +#define ED_HEADP_ADDR_MASK 0xfffffff0 +#define ED_HEADP_H (1 << 0) /* Bit 0: Halted */ +#define ED_HEADP_C (1 << 1) /* Bit 1: Toggle carry */ + +/* General Transfer Descriptor Offsets (4.3.1) */ + +#define GTD_STATUS_OFFSET (0x00) /* TD status bits */ +#define GTD_CBP_OFFSET (0x04) /* Current Buffer Pointer (CBP) */ +#define GTD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */ +#define GTD_BE_OFFSET (0x0c) /* Buffer End (BE) */ + +/* General Transfer Descriptor Bit Definitions */ + + /* Bits 0-17: Reserved */ + +#define GTD_STATUS_R (1 << 18) /* Bit 18: Buffer rounding */ +#define GTD_STATUS_DP_SHIFT (19) /* Bits 19-20: Direction/PID */ +#define GTD_STATUS_DP_MASK (3 << GTD_STATUS_DP_SHIFT) +# define GTD_STATUS_DP_SETUP (0 << GTD_STATUS_DP_SHIFT) /* To endpoint */ +# define GTD_STATUS_DP_OUT (1 << GTD_STATUS_DP_SHIFT) /* To endpoint */ +# define GTD_STATUS_DP_IN (2 << GTD_STATUS_DP_SHIFT) /* From endpoint */ + +#define GTD_STATUS_DI_SHIFT (21) /* Bits 21-23: Delay input */ +#define GTD_STATUS_DI_MASK (7 << GTD_STATUS_DI_SHIFT) +#define GTD_STATUS_T_SHIFT (24) /* Bits 24-25: Data Toggle */ +#define GTD_STATUS_T_MASK (3 << GTD_STATUS_T_SHIFT) +# define GTD_STATUS_T_TOGGLE (0 << GTD_STATUS_T_SHIFT) +# define GTD_STATUS_T_DATA0 (2 << GTD_STATUS_T_SHIFT) +# define GTD_STATUS_T_DATA1 (3 << GTD_STATUS_T_SHIFT) +#define GTD_STATUS_EC_SHIFT (26) /* Bits 26-27: Error count */ +#define GTD_STATUS_EC_MASK (3 << GTD_STATUS_EC_SHIFT) +#define GTD_STATUS_CC_SHIFT (28) /* Bits 28-31: Condition code */ +#define GTD_STATUS_CC_MASK (15 << GTD_STATUS_CC_SHIFT) + +/* Isochronous Transfer Descriptor Offsets (4.3.2) */ + +#define ITD_STATUS_OFFSET (0x00) /* TD status bits */ +#define ITD_BP0_OFFSET (0x04) /* Buffer page 0 (BP0) */ +#define ITD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */ +#define ITD_BE_OFFSET (0x0c) /* Buffer End (BE) */ + +#define ITD_NPSW (8) +#define ITD_PSW0_OFFSET (0x10) /* Offset0/PSW0 */ +#define ITD_PSW1_OFFSET (0x12) /* Offset1/PSW1 */ +#define ITD_PSW2_OFFSET (0x14) /* Offset2/PSW2 */ +#define ITD_PSW3_OFFSET (0x16) /* Offset3/PSW3 */ +#define ITD_PSW4_OFFSET (0x18) /* Offset4/PSW4 */ +#define ITD_PSW5_OFFSET (0x1a) /* Offset5/PSW5 */ +#define ITD_PSW6_OFFSET (0x1c) /* Offset6/PSW6 */ +#define ITD_PSW7_OFFSET (0x1e) /* Offset7/PSW7 */ + +/* Condition codes (Table 4-7) */ + +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEMISMATCH 0x03 +#define TD_CC_STALL 0x04 +#define TD_CC_DEVNOTRESPONDING 0x05 +#define TD_CC_PIDCHECKFAILURE 0x06 +#define TD_CC_UNEXPECTEDPID 0x07 +#define TD_CC_DATAOVERRUN 0x08 +#define TD_CC_DATAUNDERRUN 0x09 +#define TD_CC_BUFFEROVERRUN 0x0c +#define TD_CC_BUFFERUNDERRUN 0x0d +#define TD_CC_NOTACCESSED 0x0f + +#define TD_CC_USER 0x10 /* For use by OHCI drivers */ + +/* Host Controller Communications Area Format (4.4.1) ***********************/ + +/* HccaInterruptTable: 32x32-bit pointers to interrupt EDs */ + +#define HCCA_INTTBL_OFFSET (0x00) +#define HCCA_INTTBL_WSIZE (32) +#define HCCA_INTTBL_BSIZE (HCCA_INTTBL_WSIZE * 4) + +/* HccaFrameNumber: Current frame number */ + +#define HCCA_FMNO_OFFSET (0x80) +#define HCCA_FMNO_BSIZE (2) + +/* HccaPad1: Zero when frame no. updated */ + +#define HCCA_PAD1_OFFSET (0x82) +#define HCCA_PAD1_BSIZE (2) + +/* HccaDoneHead: When the HC reaches the end of a frame and its deferred + * interrupt register is 0, it writes the current value of its HcDoneHead to + * this location and generates an interrupt. + * + * The LSB of HCCADoneHead may be set to 1 to indicate that an unmasked + * HcInterruptStatus was set when HccaDoneHead was written. + */ + +#define HCCA_DONEHEAD_OFFSET (0x84) +#define HCCA_DONEHEAD_BSIZE (4) + +#define HCCA_DONEHEAD_MASK 0xfffffffe +#define HCCA_DONEHEAD_INTSTA (1 << 0) + +/* 0x88: 116 bytes reserved */ + +#define HCCA_RESERVED_OFFSET (0x88) +#define HCCA_RESERVED_BSIZE (116) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct ohci_hcor +{ + volatile uint32_t hcrevision; /* 0x00 */ + volatile uint32_t hccontrol; /* 0x04 */ + volatile uint32_t hccmdsts; /* 0x08 */ + volatile uint32_t hcintsts; /* 0x0c */ + volatile uint32_t hcinten; /* 0x10 */ + volatile uint32_t hcintdis; /* 0x14 */ + volatile uint32_t hchcca; /* 0x18 */ + volatile uint32_t hcperiodcurrented; /* 0x1c */ + volatile uint32_t hccontrolheaded; /* 0x20 */ + volatile uint32_t hccontrolcurrented; /* 0x24 */ + volatile uint32_t hcbulkheaded; /* 0x28 */ + volatile uint32_t hcbulkcurrented; /* 0x2c */ + volatile uint32_t hcdonehead; /* 0x30 */ + volatile uint32_t hcfminterval; /* 0x34 */ + volatile uint32_t hcfmremaining; /* 0x38 */ + volatile uint32_t hcfmnumber; /* 0x3c */ + volatile uint32_t hcperiodicstart; /* 0x40 */ + volatile uint32_t hclsthreshold; /* 0x44 */ + volatile uint32_t hcrhdescriptora; /* 0x48 */ + volatile uint32_t hcrhdescriptorb; /* 0x4c */ + volatile uint32_t hcrhsts; /* 0x50 */ + volatile uint32_t hcrhportsts[15]; /* 0x54 */ +}; + +/* Endpoint Descriptor Offsets (4.2.1) */ + +struct ohci_ed +{ + volatile uint32_t ctrl; /* ED status/control bits */ + volatile uint32_t tailp; /* TD Queue Tail Pointer (TailP) */ + volatile uint32_t headp; /* TD Queue Head Pointer (HeadP) */ + volatile uint32_t nexted; /* Next Endpoint Descriptor (NextED) */ +}; + +/* General Transfer Descriptor (4.3.1) */ + +struct ohci_gtd +{ + volatile uint32_t ctrl; /* TD status/control bits */ + volatile uint32_t cbp; /* Current Buffer Pointer (CBP) */ + volatile uint32_t nexttd; /* Next TD (NextTD) */ + volatile uint32_t be; /* Buffer End (BE) */ +}; + +/* Isochronous Transfer Descriptor Offsets (4.3.2) */ + +struct ohci_itd +{ + volatile uint32_t ctrl; /* TD status/control bits */ + volatile uint32_t bp0; /* Buffer page 0 (BP0 */ + volatile uint32_t nexttd; /* Next TD (NextTD) */ + volatile uint32_t be; /* Buffer End (BE) */ + volatile uint16_t psw[ITD_NPSW]; /* Offset/PSW */ +}; + +/* Host Controller Communications Area Format (4.4.1) */ + +struct ohci_hcca +{ + /* HccaInterruptTable: 32x32-bit pointers to interrupt EDs */ + + volatile uint32_t inttbl[HCCA_INTTBL_WSIZE]; + + /* HccaFrameNumber: Current frame number and + * HccaPad1: Zero when frame no. updated + */ + + volatile uint16_t fmno; + volatile uint16_t pad1; + + /* HccaDoneHead: When the HC reaches the end of a frame and its deferred + * interrupt register is 0, it writes the current value of its HcDoneHead + * to this location and generates an interrupt. + */ + + volatile uint32_t donehead; + volatile uint8_t reserved[HCCA_RESERVED_BSIZE]; + volatile uint32_t extra; +} __attribute__((aligned(256))); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_USB_OHCI_H */ diff --git a/rt-thread/components/drivers/usb/cherryusb/port/pusb2/README.md b/rt-thread/components/drivers/usb/cherryusb/port/pusb2/README.md new file mode 100644 index 0000000..f8137af --- /dev/null +++ b/rt-thread/components/drivers/usb/cherryusb/port/pusb2/README.md @@ -0,0 +1,66 @@ +# USB 2.0 OTG 控制器 (PUSB2) + +- Phytium PI 和 Phyium E2000 系列开发板提供了兼容 USB2.0 的 OTG 接口 +- 相关的使用例程可以在 Phytium PI（飞腾派）和 E2000 D/Q Demo 板上运行，例程包括 + +--------------------------------------------- + +- Host 模式 + +- - 1. [FreeRTOS 上作为主机使用键盘/鼠标/U盘](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_host/README.md) +- - 5. [RT-Thread 上作为主机识别键盘/鼠标/U盘](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md) + +--------------------------------------------- + +- Device 模式 + +- - 1. [裸机上模拟为一个 U 盘](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md) +- - 2. [裸机上模拟为一个虚拟串口](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md) +- - 3. [FreeRTOS 上模拟为一个 U 盘](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md) +- - 4. [FreeRTOS 上模拟为虚拟串口](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md) +- - 5. [RT-Thread 上模拟为一个 U 盘](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md) + +--------------------------------------------- + +- PUSB2 的驱动功能以静态库的方式提供， +- - libpusb2_hc_a64.a : AARCH64 主机模式驱动库 +- - libpusb2_dc_a64.a : AARCH64 从机模式驱动库 +- - libpusb2_hc_a32_hardfp.a ：AARCH32 主机模式驱动库，使用硬浮点 +- - libpusb2_hc_a32_softfp.a ：AARCH32 主机模式驱动库，使用软浮点 +- - libpusb2_dc_a32_hardfp.a ：AARCH32 从机模式驱动库，使用硬浮点 +- - libpusb2_dc_a32_softfp.a ：AARCH32 从机模式驱动库，使用软浮点 + +需要获取源代码请联系 `opensource_embedded@phytium.com.cn` 获取 + +# USB 2.0 OTG Controller (PUSB2) + +- Phytium PI and the Phytium E2000 series development boards offer OTG interfaces compatible with USB 2.0. +- Relevant usage examples can be run on the Phytium PI and E2000 D/Q Demo boards, including: + +--------------------------------------------- + +- Host Mode + + - 1. [Using a keyboard/mouse/USB flash drive as a host on FreeRTOS](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_host/README.md) + - 5. [Recognizing a keyboard/mouse/USB flash drive as a host on RT-Thread](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md) + +--------------------------------------------- + +- Device Mode + - 1. [Simulating as a USB flash drive on a standalone system](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md) + - 2. [Simulating as a virtual serial port on a standalone system](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md) + - 3. [Simulating as a USB flash drive on FreeRTOS](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md) + - 4. [Simulating as a virtual serial port on FreeRTOS](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md) + - 5. [Simulating as a USB flash drive on RT-Thread](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md) + +--------------------------------------------- + +- The driver functionality of PUSB2 is provided as static libraries: + - - `libpusb2_hc_a64.a` : Host mode driver library for AARCH64 + - - `libpusb2_dc_a64.a` : Device mode driver library for AARCH64 + - - `libpusb2_hc_a32_hardfp.a` : Host mode driver library for AARCH32, using hard floating point + - - `libpusb2_hc_a32_softfp.a` : Host mode driver library for AARCH32, using soft floating point + - - `libpusb2_dc_a32_hardfp.a` : Device mode driver library for AARCH32, using hard floating point + - - `libpusb2_dc_a32_softfp.a` : Device mode driver library for AARCH32, using soft floating point + +- To obtain the source code, please contact `opensource_embedded@phytium.com.cn`. \ No newline at end of file diff --git a/rt-thread/components/drivers/usb/cherryusb/port/pusb2/libpusb2_dc_a32_hardfp.a b/rt-thread/components/drivers/usb/cherryusb/port/pusb2/libpusb2_dc_a32_hardfp.a new file mode 100644 index 0000000000000000000000000000000000000000..685de412406a29a865b6f584d1e81a1d91c2f0e3 GIT binary patch literal 171332 zcmdqK4}6uynJ+%)oB%OKIY3lOQ$1*?7$Y1sDplGBk|4N<$RD+>Z3xK`urY~AP_(v< zfGyj_tyTIf+r>6rx&67;wzSK2yIpJP!tT%8YA>sF>+Ry25U`eVTiWZk-CbAi_d7Gs zd**$3PZGP`KcC-xILtdU&wQWfnR(`!KkuBA>GN89+Sa|RVsxmw~62jypSoR9k1CPxbb-_7zOyvK1|>I@?;?))m^97h2oro{}@?ic_*K zyEK+{Q_uRoLcF5QQZ;R!uexBvt+y6>8oRphwn)o*y4DnybhUl3*CrQtuJ2>YCKmP- zY?0}0-_YLH+&Rh#Ti=G( zjuqX7LOW$x*Va^M>uN7t-?w&!ZBU!HqR@Banhm{xnYQlUSzUp%D&?oHsIRx~>GI32a1XiF6(4P0vM`lO z!CkqKGBZsvWz3dJn?J7JMl;P7aBJ;&&K|h#aG81FXj%S|qbC2t(TVxz@OkNI#taN) z4?J-A+>^71SY`L_On*qbJO9Ga)A{G{d1+`gT9beHXl4EZd>%=}E%!2{@&iK|@TV-9 z+)GDIZr@RJA~#$flOxq1(tjN?kpAnrmxgxd_6?0hZ?ay`9CXcXPQ)%7yyR#V(OsLFEE~`qNl{zOgHT9O%v{ZHK-0|n9 zYEw-at5*15XiH`07bnBAOw7`Z$(VFljC33?W6I2g7)4nul`-Q~`8ZWRUX_nm5CQK#j5-gg?EW6=h!cXjG3+QW)}YMk zHJ|qBnTRKwDuczd4K6*^Jmu4_eziH^(|N>`P0qaR(~QXP6`!W%PBt^lKgQA*nY4F! z94V6x+LM!Wo2h9xHLZR<{5x4Zx3pOI+_ItbuJxVmEp6T1E!{o&*lL-pY_&3G*6(yp zeS6{dwl}l1wyjkwZq0XYt+*XYpW_=<(lV?iJzbT*y_nA7vHCift`&2adhApNNn?j* zgQUgyn4Z;p_w9YHYY_MKxOkmB^%XYunOW^z6VF`m zZZsqz8x3g;>RG5!^s_W$P%uUp^;@v}Oj128F43nUNrKA3ezsJ@g(L|G(H6K={USj^ z?P$+js&os%_e3sQ? zDLT%sT)~Y-$2m&ValVou&kK;D`AQjS<@rWDhj?6UOIb*_evEWmKu5mPF2t+BM}lDA zgACHiD*F~8@G;962Jpdix6GxaqrChu2;NRSbH&?$4?{NyI7eQF4_CURW1VO53FT`? zx&|K!g7;U*2<6)<1U?q|e&XmN`AA1TvU(Q0qsR;8>j#m@$CWebSnq5Ahw?p$yd?Q5 zJ)N}Q9?*qBo3e8`(YEEYNHj_X;2;PmJPUJfx z1U^Qw4Ig%Nk$j}1d{wSElJ9QNh4Kvq@^NJ^@;&bPihRdWmL%VRrxW?AkPd?+pK)}N ze59j%TyrsqzWb3M%C|d^k2?jC?^g~l8Xwh2*H|R?pWq$$bRu5^(qWKf6$tPg$wxZM zSM7-fFAKU*zP*8bTnCGM?{j#Oe2ajW4;TyHT!nW4c;w6RmcvKzZt!@BY}g3AFi5h` z(M5WYj(9mwEPT5a-xmWtxZ@GNk9fXf2mQd4J|m>yJ?!Za*|0+d@@Yvv>F6T)NJsf( z7bSRK2VL0CuLknb$BTR~d%hyyKneMN;OP+A@C^~jrzQC-M;FOQI?8vErxW>p3A#|e z-vsh;i7N8F4HFTuMZUdA$e1Lg;7###BHuv~h(rjItao&ge59j%vda^^Jm^CC%8?L1 z$sL}^cZ26Ews{D6vSb#%E?{JUyf02)|=)i(yNMy$uQ;+BQ_>eE< zplra4!fG7LOcW60$|FxVLb|D_cw3MmboL}ZI58ddy!6T|>mAML=cNZ9wPHr+rGJq6 zL`u#bdEUq~L7pMXb6JV=M4p+(&Jt0#5_L(>^H9OzbGgqi_cU@wsn20~Mp^04OnIhh zh=Vg$gZi25z)+bfo>NxF&MDK;IVI)hxh(mYjE6D3?JVW$jJl`$FTh52&%=})o*KP0Kd^nZge3-J@ z^I@E0e>9&tENAIuz=bcUV2t(DcT+x{MoiuqD#tQ7H^w+QmPU-cV>k_%w~+R9oVTZ8JCP0vXWV#UW4bou38w z-=Q-RXCco-$Z$W-{P}z)ol+TrB^I_th37w5^XH3S! zCf_g&|8Y#7O&&5q29rZsu3@-6J21>X(DOP#jEc0-)2Vb>v_D}hU&al;(P2kkYDK9YO}s4IA%9^{et%u#ql)?s9>$u(MgN%PLq|`ZwCx~1 zDCyl_te=2Ozc$_5&H&o>A&l)0V2bha3%$9Je=9)6-hji ze~fmWK|gVh;WOzt4~k{~CnMdQxzGJ&m2KL?m8}!{seuDkOcA_4%*(qKp zK2P?~)OC`7o{Bldt~J#BC-t+QZt3(FET-UH@6%PjJPk}s>&F=DbA53xY_}m>oL?lr zfbpRHcUTtANs_%aZcjQ0M0f{JBOV|Lh25-6NE(R%P^qDYU^C;Nwe; zFWxJV@x`@E)K6$9?g{8`ur`6eace>9#x=V5H{{#(*+^?aYiH4xZ2Q&$JQR3u&ku>AnKp!t}>f`d+3zACUuRdB=jhA>i8k8nhLWk^YbC zW9m!0mv;H*i7SSGe)1%@rglx9q_^yYL>IvoduRSFbKuj#16xQtH!@9`?ED9RsP{

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