修正但仍有误
This commit is contained in:
@@ -1,75 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2012-10-27 heyuanjie87 first version.
|
||||
* 2013-05-17 aozima initial alarm event & mutex in system init.
|
||||
* 2020-10-15 zhangsz add alarm flags hour minute second.
|
||||
*/
|
||||
|
||||
#ifndef __ALARM_H__
|
||||
#define __ALARM_H__
|
||||
|
||||
#include <sys/time.h>
|
||||
#include <rtdef.h>
|
||||
|
||||
#define RT_ALARM_TM_NOW -1 /* set the alarm tm_day,tm_mon,tm_sec,etc.
|
||||
to now.we also call it "don't care" value */
|
||||
|
||||
/* alarm flags */
|
||||
#define RT_ALARM_ONESHOT 0x000 /* only alarm once */
|
||||
#define RT_ALARM_DAILY 0x100 /* alarm everyday */
|
||||
#define RT_ALARM_WEEKLY 0x200 /* alarm weekly at Monday or Friday etc. */
|
||||
#define RT_ALARM_MONTHLY 0x400 /* alarm monthly at someday */
|
||||
#define RT_ALARM_YAERLY 0x800 /* alarm yearly at a certain date */
|
||||
#define RT_ALARM_HOUR 0x1000 /* alarm each hour at a certain min:second */
|
||||
#define RT_ALARM_MINUTE 0x2000 /* alarm each minute at a certain second */
|
||||
#define RT_ALARM_SECOND 0x4000 /* alarm each second */
|
||||
|
||||
#define RT_ALARM_STATE_INITED 0x02
|
||||
#define RT_ALARM_STATE_START 0x01
|
||||
#define RT_ALARM_STATE_STOP 0x00
|
||||
|
||||
/* alarm control cmd */
|
||||
#define RT_ALARM_CTRL_MODIFY 1 /* modify alarm time or alarm flag */
|
||||
|
||||
typedef struct rt_alarm *rt_alarm_t;
|
||||
typedef void (*rt_alarm_callback_t)(rt_alarm_t alarm, time_t timestamp);
|
||||
|
||||
struct rt_alarm
|
||||
{
|
||||
rt_list_t list;
|
||||
rt_uint32_t flag;
|
||||
rt_alarm_callback_t callback;
|
||||
struct tm wktime;
|
||||
|
||||
void *user_data;
|
||||
};
|
||||
|
||||
struct rt_alarm_setup
|
||||
{
|
||||
rt_uint32_t flag; /* alarm flag */
|
||||
struct tm wktime; /* when will the alarm wake up user */
|
||||
};
|
||||
|
||||
struct rt_alarm_container
|
||||
{
|
||||
rt_list_t head;
|
||||
struct rt_mutex mutex;
|
||||
struct rt_event event;
|
||||
struct rt_alarm *current;
|
||||
};
|
||||
|
||||
rt_alarm_t rt_alarm_create(rt_alarm_callback_t callback,
|
||||
struct rt_alarm_setup *setup);
|
||||
rt_err_t rt_alarm_control(rt_alarm_t alarm, int cmd, void *arg);
|
||||
void rt_alarm_update(rt_device_t dev, rt_uint32_t event);
|
||||
rt_err_t rt_alarm_delete(rt_alarm_t alarm);
|
||||
rt_err_t rt_alarm_start(rt_alarm_t alarm);
|
||||
rt_err_t rt_alarm_stop(rt_alarm_t alarm);
|
||||
int rt_alarm_system_init(void);
|
||||
|
||||
#endif /* __ALARM_H__ */
|
||||
@@ -1,176 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-05-09 Urey first version
|
||||
* 2019-07-09 Zero-Free improve device ops interface and data flows
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __AUDIO_H__
|
||||
#define __AUDIO_H__
|
||||
|
||||
#include "audio_pipe.h"
|
||||
|
||||
/* AUDIO command */
|
||||
#define _AUDIO_CTL(a) (RT_DEVICE_CTRL_BASE(Sound) + a)
|
||||
|
||||
#define AUDIO_CTL_GETCAPS _AUDIO_CTL(1)
|
||||
#define AUDIO_CTL_CONFIGURE _AUDIO_CTL(2)
|
||||
#define AUDIO_CTL_START _AUDIO_CTL(3)
|
||||
#define AUDIO_CTL_STOP _AUDIO_CTL(4)
|
||||
#define AUDIO_CTL_GETBUFFERINFO _AUDIO_CTL(5)
|
||||
|
||||
/* Audio Device Types */
|
||||
#define AUDIO_TYPE_QUERY 0x00
|
||||
#define AUDIO_TYPE_INPUT 0x01
|
||||
#define AUDIO_TYPE_OUTPUT 0x02
|
||||
#define AUDIO_TYPE_MIXER 0x04
|
||||
|
||||
/* Supported Sampling Rates */
|
||||
#define AUDIO_SAMP_RATE_8K 0x0001
|
||||
#define AUDIO_SAMP_RATE_11K 0x0002
|
||||
#define AUDIO_SAMP_RATE_16K 0x0004
|
||||
#define AUDIO_SAMP_RATE_22K 0x0008
|
||||
#define AUDIO_SAMP_RATE_32K 0x0010
|
||||
#define AUDIO_SAMP_RATE_44K 0x0020
|
||||
#define AUDIO_SAMP_RATE_48K 0x0040
|
||||
#define AUDIO_SAMP_RATE_96K 0x0080
|
||||
#define AUDIO_SAMP_RATE_128K 0x0100
|
||||
#define AUDIO_SAMP_RATE_160K 0x0200
|
||||
#define AUDIO_SAMP_RATE_172K 0x0400
|
||||
#define AUDIO_SAMP_RATE_192K 0x0800
|
||||
|
||||
/* Supported Bit Rates */
|
||||
#define AUDIO_BIT_RATE_22K 0x01
|
||||
#define AUDIO_BIT_RATE_44K 0x02
|
||||
#define AUDIO_BIT_RATE_48K 0x04
|
||||
#define AUDIO_BIT_RATE_96K 0x08
|
||||
#define AUDIO_BIT_RATE_128K 0x10
|
||||
#define AUDIO_BIT_RATE_160K 0x20
|
||||
#define AUDIO_BIT_RATE_172K 0x40
|
||||
#define AUDIO_BIT_RATE_192K 0x80
|
||||
|
||||
/* Support Dsp(input/output) Units controls */
|
||||
#define AUDIO_DSP_PARAM 0 /* get/set all params */
|
||||
#define AUDIO_DSP_SAMPLERATE 1 /* samplerate */
|
||||
#define AUDIO_DSP_CHANNELS 2 /* channels */
|
||||
#define AUDIO_DSP_SAMPLEBITS 3 /* sample bits width */
|
||||
|
||||
/* Supported Mixer Units controls */
|
||||
#define AUDIO_MIXER_QUERY 0x0000
|
||||
#define AUDIO_MIXER_MUTE 0x0001
|
||||
#define AUDIO_MIXER_VOLUME 0x0002
|
||||
#define AUDIO_MIXER_BASS 0x0004
|
||||
#define AUDIO_MIXER_MID 0x0008
|
||||
#define AUDIO_MIXER_TREBLE 0x0010
|
||||
#define AUDIO_MIXER_EQUALIZER 0x0020
|
||||
#define AUDIO_MIXER_LINE 0x0040
|
||||
#define AUDIO_MIXER_DIGITAL 0x0080
|
||||
#define AUDIO_MIXER_MIC 0x0100
|
||||
#define AUDIO_MIXER_VITURAL 0x0200
|
||||
#define AUDIO_MIXER_EXTEND 0x8000 /* extend mixer command */
|
||||
|
||||
#define AUDIO_VOLUME_MAX (100)
|
||||
#define AUDIO_VOLUME_MIN (0)
|
||||
|
||||
#define CFG_AUDIO_REPLAY_QUEUE_COUNT 4
|
||||
|
||||
enum
|
||||
{
|
||||
AUDIO_STREAM_REPLAY = 0,
|
||||
AUDIO_STREAM_RECORD,
|
||||
AUDIO_STREAM_LAST = AUDIO_STREAM_RECORD,
|
||||
};
|
||||
|
||||
/* the preferred number and size of audio pipeline buffer for the audio device */
|
||||
struct rt_audio_buf_info
|
||||
{
|
||||
rt_uint8_t *buffer;
|
||||
rt_uint16_t block_size;
|
||||
rt_uint16_t block_count;
|
||||
rt_uint32_t total_size;
|
||||
};
|
||||
|
||||
struct rt_audio_device;
|
||||
struct rt_audio_caps;
|
||||
struct rt_audio_configure;
|
||||
struct rt_audio_ops
|
||||
{
|
||||
rt_err_t (*getcaps)(struct rt_audio_device *audio, struct rt_audio_caps *caps);
|
||||
rt_err_t (*configure)(struct rt_audio_device *audio, struct rt_audio_caps *caps);
|
||||
rt_err_t (*init)(struct rt_audio_device *audio);
|
||||
rt_err_t (*start)(struct rt_audio_device *audio, int stream);
|
||||
rt_err_t (*stop)(struct rt_audio_device *audio, int stream);
|
||||
rt_ssize_t (*transmit)(struct rt_audio_device *audio, const void *writeBuf, void *readBuf, rt_size_t size);
|
||||
/* get page size of codec or private buffer's info */
|
||||
void (*buffer_info)(struct rt_audio_device *audio, struct rt_audio_buf_info *info);
|
||||
};
|
||||
|
||||
struct rt_audio_configure
|
||||
{
|
||||
rt_uint32_t samplerate;
|
||||
rt_uint16_t channels;
|
||||
rt_uint16_t samplebits;
|
||||
};
|
||||
|
||||
struct rt_audio_caps
|
||||
{
|
||||
int main_type;
|
||||
int sub_type;
|
||||
|
||||
union
|
||||
{
|
||||
rt_uint32_t mask;
|
||||
int value;
|
||||
struct rt_audio_configure config;
|
||||
} udata;
|
||||
};
|
||||
|
||||
struct rt_audio_replay
|
||||
{
|
||||
struct rt_mempool *mp;
|
||||
struct rt_data_queue queue;
|
||||
struct rt_mutex lock;
|
||||
struct rt_completion cmp;
|
||||
struct rt_audio_buf_info buf_info;
|
||||
rt_uint8_t *write_data;
|
||||
rt_uint16_t write_index;
|
||||
rt_uint16_t read_index;
|
||||
rt_uint32_t pos;
|
||||
rt_uint8_t event;
|
||||
rt_bool_t activated;
|
||||
};
|
||||
|
||||
struct rt_audio_record
|
||||
{
|
||||
struct rt_audio_pipe pipe;
|
||||
rt_bool_t activated;
|
||||
};
|
||||
|
||||
struct rt_audio_device
|
||||
{
|
||||
struct rt_device parent;
|
||||
struct rt_audio_ops *ops;
|
||||
struct rt_audio_replay *replay;
|
||||
struct rt_audio_record *record;
|
||||
};
|
||||
|
||||
rt_err_t rt_audio_register(struct rt_audio_device *audio, const char *name, rt_uint32_t flag, void *data);
|
||||
void rt_audio_tx_complete(struct rt_audio_device *audio);
|
||||
void rt_audio_rx_done(struct rt_audio_device *audio, rt_uint8_t *pbuf, rt_size_t len);
|
||||
|
||||
/* Device Control Commands */
|
||||
#define CODEC_CMD_RESET 0
|
||||
#define CODEC_CMD_SET_VOLUME 1
|
||||
#define CODEC_CMD_GET_VOLUME 2
|
||||
#define CODEC_CMD_SAMPLERATE 3
|
||||
#define CODEC_CMD_EQ 4
|
||||
#define CODEC_CMD_3D 5
|
||||
|
||||
#define CODEC_VOLUME_MAX (63)
|
||||
|
||||
#endif /* __AUDIO_H__ */
|
||||
@@ -1,364 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2015-05-14 aubrcool@qq.com first version
|
||||
* 2015-07-06 Bernard remove RT_CAN_USING_LED.
|
||||
* 2022-05-08 hpmicro add CANFD support, fixed typos
|
||||
*/
|
||||
|
||||
#ifndef CAN_H_
|
||||
#define CAN_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifndef RT_CANMSG_BOX_SZ
|
||||
#define RT_CANMSG_BOX_SZ 16
|
||||
#endif
|
||||
#ifndef RT_CANSND_BOX_NUM
|
||||
#define RT_CANSND_BOX_NUM 1
|
||||
#endif
|
||||
|
||||
enum CAN_DLC
|
||||
{
|
||||
CAN_MSG_0BYTE = 0,
|
||||
CAN_MSG_1BYTE,
|
||||
CAN_MSG_2BYTES,
|
||||
CAN_MSG_3BYTES,
|
||||
CAN_MSG_4BYTES,
|
||||
CAN_MSG_5BYTES,
|
||||
CAN_MSG_6BYTES,
|
||||
CAN_MSG_7BYTES,
|
||||
CAN_MSG_8BYTES,
|
||||
CAN_MSG_12BYTES,
|
||||
CAN_MSG_16BYTES,
|
||||
CAN_MSG_20BYTES,
|
||||
CAN_MSG_24BYTES,
|
||||
CAN_MSG_32BYTES,
|
||||
CAN_MSG_48BYTES,
|
||||
CAN_MSG_64BYTES,
|
||||
};
|
||||
|
||||
enum CANBAUD
|
||||
{
|
||||
CAN1MBaud = 1000UL * 1000,/* 1 MBit/sec */
|
||||
CAN800kBaud = 1000UL * 800, /* 800 kBit/sec */
|
||||
CAN500kBaud = 1000UL * 500, /* 500 kBit/sec */
|
||||
CAN250kBaud = 1000UL * 250, /* 250 kBit/sec */
|
||||
CAN125kBaud = 1000UL * 125, /* 125 kBit/sec */
|
||||
CAN100kBaud = 1000UL * 100, /* 100 kBit/sec */
|
||||
CAN50kBaud = 1000UL * 50, /* 50 kBit/sec */
|
||||
CAN20kBaud = 1000UL * 20, /* 20 kBit/sec */
|
||||
CAN10kBaud = 1000UL * 10 /* 10 kBit/sec */
|
||||
};
|
||||
|
||||
#define RT_CAN_MODE_NORMAL 0
|
||||
#define RT_CAN_MODE_LISTEN 1
|
||||
#define RT_CAN_MODE_LOOPBACK 2
|
||||
#define RT_CAN_MODE_LOOPBACKANLISTEN 3
|
||||
|
||||
#define RT_CAN_MODE_PRIV 0x01
|
||||
#define RT_CAN_MODE_NOPRIV 0x00
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */
|
||||
#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */
|
||||
|
||||
struct rt_can_filter_item
|
||||
{
|
||||
rt_uint32_t id : 29;
|
||||
rt_uint32_t ide : 1;
|
||||
rt_uint32_t rtr : 1;
|
||||
rt_uint32_t mode : 1;
|
||||
rt_uint32_t mask;
|
||||
rt_int32_t hdr_bank;/*Should be defined as:rx.FilterBank,which should be changed to rt_int32_t hdr_bank*/
|
||||
rt_uint32_t rxfifo;/*Add a configuration item that CAN_RX_FIFO0/CAN_RX_FIFO1*/
|
||||
#ifdef RT_CAN_USING_HDR
|
||||
rt_err_t (*ind)(rt_device_t dev, void *args , rt_int32_t hdr, rt_size_t size);
|
||||
void *args;
|
||||
#endif /*RT_CAN_USING_HDR*/
|
||||
};
|
||||
|
||||
|
||||
#ifdef RT_CAN_USING_HDR
|
||||
#define RT_CAN_FILTER_ITEM_INIT(id,ide,rtr,mode,mask,ind,args) \
|
||||
{(id), (ide), (rtr), (mode),(mask), -1, CAN_RX_FIFO0,(ind), (args)}/*0:CAN_RX_FIFO0*/
|
||||
#define RT_CAN_FILTER_STD_INIT(id,ind,args) \
|
||||
RT_CAN_FILTER_ITEM_INIT(id,0,0,0,0xFFFFFFFF,ind,args)
|
||||
#define RT_CAN_FILTER_EXT_INIT(id,ind,args) \
|
||||
RT_CAN_FILTER_ITEM_INIT(id,1,0,0,0xFFFFFFFF,ind,args)
|
||||
#define RT_CAN_STD_RMT_FILTER_INIT(id,ind,args) \
|
||||
RT_CAN_FILTER_ITEM_INIT(id,0,1,0,0xFFFFFFFF,ind,args)
|
||||
#define RT_CAN_EXT_RMT_FILTER_INIT(id,ind,args) \
|
||||
RT_CAN_FILTER_ITEM_INIT(id,1,1,0,0xFFFFFFFF,ind,args)
|
||||
#define RT_CAN_STD_RMT_DATA_FILTER_INIT(id,ind,args) \
|
||||
RT_CAN_FILTER_ITEM_INIT(id,0,0,1,0xFFFFFFFF,ind,args)
|
||||
#define RT_CAN_EXT_RMT_DATA_FILTER_INIT(id,ind,args) \
|
||||
RT_CAN_FILTER_ITEM_INIT(id,1,0,1,0xFFFFFFFF,ind,args)
|
||||
#else
|
||||
|
||||
#define RT_CAN_FILTER_ITEM_INIT(id,ide,rtr,mode,mask) \
|
||||
{(id), (ide), (rtr), (mode), (mask), -1, CAN_RX_FIFO0 }/*0:CAN_RX_FIFO0*/
|
||||
#define RT_CAN_FILTER_STD_INIT(id) \
|
||||
RT_CAN_FILTER_ITEM_INIT(id,0,0,0,0xFFFFFFFF)
|
||||
#define RT_CAN_FILTER_EXT_INIT(id) \
|
||||
RT_CAN_FILTER_ITEM_INIT(id,1,0,0,0xFFFFFFFF)
|
||||
#define RT_CAN_STD_RMT_FILTER_INIT(id) \
|
||||
RT_CAN_FILTER_ITEM_INIT(id,0,1,0,0xFFFFFFFF)
|
||||
#define RT_CAN_EXT_RMT_FILTER_INIT(id) \
|
||||
RT_CAN_FILTER_ITEM_INIT(id,1,1,0,0xFFFFFFFF)
|
||||
#define RT_CAN_STD_RMT_DATA_FILTER_INIT(id) \
|
||||
RT_CAN_FILTER_ITEM_INIT(id,0,0,1,0xFFFFFFFF)
|
||||
#define RT_CAN_EXT_RMT_DATA_FILTER_INIT(id) \
|
||||
RT_CAN_FILTER_ITEM_INIT(id,1,0,1,0xFFFFFFFF)
|
||||
#endif
|
||||
|
||||
struct rt_can_filter_config
|
||||
{
|
||||
rt_uint32_t count;
|
||||
rt_uint32_t actived;
|
||||
struct rt_can_filter_item *items;
|
||||
};
|
||||
|
||||
struct rt_can_bit_timing
|
||||
{
|
||||
rt_uint16_t prescaler; /* Pre-scaler */
|
||||
rt_uint16_t num_seg1; /* Bit Timing Segment 1, in terms of Tq */
|
||||
rt_uint16_t num_seg2; /* Bit Timing Segment 2, in terms of Tq */
|
||||
rt_uint8_t num_sjw; /* Synchronization Jump Width, in terms of Tq */
|
||||
rt_uint8_t num_sspoff; /* Secondary Sample Point Offset, in terms of Tq */
|
||||
};
|
||||
|
||||
/**
|
||||
* CAN bit timing configuration list
|
||||
* NOTE:
|
||||
* items[0] always for CAN2.0/CANFD Arbitration Phase
|
||||
* items[1] always for CANFD (if it exists)
|
||||
*/
|
||||
struct rt_can_bit_timing_config
|
||||
{
|
||||
rt_uint32_t count;
|
||||
struct rt_can_bit_timing *items;
|
||||
};
|
||||
|
||||
struct can_configure
|
||||
{
|
||||
rt_uint32_t baud_rate;
|
||||
rt_uint32_t msgboxsz;
|
||||
rt_uint32_t sndboxnumber;
|
||||
rt_uint32_t mode : 8;
|
||||
rt_uint32_t privmode : 8;
|
||||
rt_uint32_t reserved : 16;
|
||||
rt_uint32_t ticks;
|
||||
#ifdef RT_CAN_USING_HDR
|
||||
rt_uint32_t maxhdr;
|
||||
#endif
|
||||
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
rt_uint32_t baud_rate_fd; /* CANFD data bit rate*/
|
||||
rt_uint32_t use_bit_timing: 8; /* Use the bit timing for CAN timing configuration */
|
||||
rt_uint32_t enable_canfd : 8; /* Enable CAN-FD mode */
|
||||
rt_uint32_t reserved1 : 16;
|
||||
|
||||
/* The below fields take effect only if use_bit_timing is non-zero */
|
||||
struct rt_can_bit_timing can_timing; /* CAN bit-timing /CANFD bit-timing for arbitration phase */
|
||||
struct rt_can_bit_timing canfd_timing; /* CANFD bit-timing for datat phase */
|
||||
#endif
|
||||
};
|
||||
|
||||
#define CANDEFAULTCONFIG \
|
||||
{\
|
||||
CAN1MBaud,\
|
||||
RT_CANMSG_BOX_SZ,\
|
||||
RT_CANSND_BOX_NUM,\
|
||||
RT_CAN_MODE_NORMAL,\
|
||||
};
|
||||
|
||||
struct rt_can_ops;
|
||||
#define RT_CAN_CMD_SET_FILTER 0x13
|
||||
#define RT_CAN_CMD_SET_BAUD 0x14
|
||||
#define RT_CAN_CMD_SET_MODE 0x15
|
||||
#define RT_CAN_CMD_SET_PRIV 0x16
|
||||
#define RT_CAN_CMD_GET_STATUS 0x17
|
||||
#define RT_CAN_CMD_SET_STATUS_IND 0x18
|
||||
#define RT_CAN_CMD_SET_BUS_HOOK 0x19
|
||||
#define RT_CAN_CMD_SET_CANFD 0x1A
|
||||
#define RT_CAN_CMD_SET_BAUD_FD 0x1B
|
||||
#define RT_CAN_CMD_SET_BITTIMING 0x1C
|
||||
|
||||
#define RT_DEVICE_CAN_INT_ERR 0x1000
|
||||
|
||||
enum RT_CAN_STATUS_MODE
|
||||
{
|
||||
NORMAL = 0,
|
||||
ERRWARNING = 1,
|
||||
ERRPASSIVE = 2,
|
||||
BUSOFF = 4,
|
||||
};
|
||||
enum RT_CAN_BUS_ERR
|
||||
{
|
||||
RT_CAN_BUS_NO_ERR = 0,
|
||||
RT_CAN_BUS_BIT_PAD_ERR = 1,
|
||||
RT_CAN_BUS_FORMAT_ERR = 2,
|
||||
RT_CAN_BUS_ACK_ERR = 3,
|
||||
RT_CAN_BUS_IMPLICIT_BIT_ERR = 4,
|
||||
RT_CAN_BUS_EXPLICIT_BIT_ERR = 5,
|
||||
RT_CAN_BUS_CRC_ERR = 6,
|
||||
};
|
||||
|
||||
struct rt_can_status
|
||||
{
|
||||
rt_uint32_t rcverrcnt;
|
||||
rt_uint32_t snderrcnt;
|
||||
rt_uint32_t errcode;
|
||||
rt_uint32_t rcvpkg;
|
||||
rt_uint32_t dropedrcvpkg;
|
||||
rt_uint32_t sndpkg;
|
||||
rt_uint32_t dropedsndpkg;
|
||||
rt_uint32_t bitpaderrcnt;
|
||||
rt_uint32_t formaterrcnt;
|
||||
rt_uint32_t ackerrcnt;
|
||||
rt_uint32_t biterrcnt;
|
||||
rt_uint32_t crcerrcnt;
|
||||
rt_uint32_t rcvchange;
|
||||
rt_uint32_t sndchange;
|
||||
rt_uint32_t lasterrtype;
|
||||
};
|
||||
|
||||
#ifdef RT_CAN_USING_HDR
|
||||
struct rt_can_hdr
|
||||
{
|
||||
rt_uint32_t connected;
|
||||
rt_uint32_t msgs;
|
||||
struct rt_can_filter_item filter;
|
||||
struct rt_list_node list;
|
||||
};
|
||||
#endif
|
||||
struct rt_can_device;
|
||||
typedef rt_err_t (*rt_canstatus_ind)(struct rt_can_device *, void *);
|
||||
typedef struct rt_can_status_ind_type
|
||||
{
|
||||
rt_canstatus_ind ind;
|
||||
void *args;
|
||||
} *rt_can_status_ind_type_t;
|
||||
typedef void (*rt_can_bus_hook)(struct rt_can_device *);
|
||||
struct rt_can_device
|
||||
{
|
||||
struct rt_device parent;
|
||||
|
||||
const struct rt_can_ops *ops;
|
||||
struct can_configure config;
|
||||
struct rt_can_status status;
|
||||
|
||||
rt_uint32_t timerinitflag;
|
||||
struct rt_timer timer;
|
||||
|
||||
struct rt_can_status_ind_type status_indicate;
|
||||
#ifdef RT_CAN_USING_HDR
|
||||
struct rt_can_hdr *hdr;
|
||||
#endif
|
||||
#ifdef RT_CAN_USING_BUS_HOOK
|
||||
rt_can_bus_hook bus_hook;
|
||||
#endif /*RT_CAN_USING_BUS_HOOK*/
|
||||
struct rt_mutex lock;
|
||||
void *can_rx;
|
||||
void *can_tx;
|
||||
};
|
||||
typedef struct rt_can_device *rt_can_t;
|
||||
|
||||
#define RT_CAN_STDID 0
|
||||
#define RT_CAN_EXTID 1
|
||||
#define RT_CAN_DTR 0
|
||||
#define RT_CAN_RTR 1
|
||||
|
||||
typedef struct rt_can_status *rt_can_status_t;
|
||||
|
||||
struct rt_can_msg
|
||||
{
|
||||
rt_uint32_t id : 29;
|
||||
rt_uint32_t ide : 1;
|
||||
rt_uint32_t rtr : 1;
|
||||
rt_uint32_t rsv : 1;
|
||||
rt_uint32_t len : 8;
|
||||
rt_uint32_t priv : 8;
|
||||
rt_int32_t hdr_index : 8;/*Should be defined as:rx.FilterMatchIndex,which should be changed to rt_int32_t hdr_index : 8*/
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
rt_uint32_t fd_frame : 1;
|
||||
rt_uint32_t brs : 1;
|
||||
rt_uint32_t rxfifo : 2;/*Redefined to return :CAN RX FIFO0/CAN RX FIFO1*/
|
||||
rt_uint32_t reserved : 4;
|
||||
#else
|
||||
rt_uint32_t rxfifo : 2;/*Redefined to return :CAN RX FIFO0/CAN RX FIFO1*/
|
||||
rt_uint32_t reserved : 6;
|
||||
#endif
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
rt_uint8_t data[64];
|
||||
#else
|
||||
rt_uint8_t data[8];
|
||||
#endif
|
||||
};
|
||||
typedef struct rt_can_msg *rt_can_msg_t;
|
||||
|
||||
struct rt_can_msg_list
|
||||
{
|
||||
struct rt_list_node list;
|
||||
#ifdef RT_CAN_USING_HDR
|
||||
struct rt_list_node hdrlist;
|
||||
struct rt_can_hdr *owner;
|
||||
#endif
|
||||
struct rt_can_msg data;
|
||||
};
|
||||
|
||||
struct rt_can_rx_fifo
|
||||
{
|
||||
/* software fifo */
|
||||
struct rt_can_msg_list *buffer;
|
||||
rt_uint32_t freenumbers;
|
||||
struct rt_list_node freelist;
|
||||
struct rt_list_node uselist;
|
||||
};
|
||||
|
||||
#define RT_CAN_SND_RESULT_OK 0
|
||||
#define RT_CAN_SND_RESULT_ERR 1
|
||||
#define RT_CAN_SND_RESULT_WAIT 2
|
||||
|
||||
#define RT_CAN_EVENT_RX_IND 0x01 /* Rx indication */
|
||||
#define RT_CAN_EVENT_TX_DONE 0x02 /* Tx complete */
|
||||
#define RT_CAN_EVENT_TX_FAIL 0x03 /* Tx fail */
|
||||
#define RT_CAN_EVENT_RX_TIMEOUT 0x05 /* Rx timeout */
|
||||
#define RT_CAN_EVENT_RXOF_IND 0x06 /* Rx overflow */
|
||||
|
||||
struct rt_can_sndbxinx_list
|
||||
{
|
||||
struct rt_list_node list;
|
||||
struct rt_completion completion;
|
||||
rt_uint32_t result;
|
||||
};
|
||||
|
||||
struct rt_can_tx_fifo
|
||||
{
|
||||
struct rt_can_sndbxinx_list *buffer;
|
||||
struct rt_semaphore sem;
|
||||
struct rt_list_node freelist;
|
||||
};
|
||||
|
||||
struct rt_can_ops
|
||||
{
|
||||
rt_err_t (*configure)(struct rt_can_device *can, struct can_configure *cfg);
|
||||
rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg);
|
||||
rt_ssize_t (*sendmsg)(struct rt_can_device *can, const void *buf, rt_uint32_t boxno);
|
||||
rt_ssize_t (*recvmsg)(struct rt_can_device *can, void *buf, rt_uint32_t boxno);
|
||||
};
|
||||
|
||||
rt_err_t rt_hw_can_register(struct rt_can_device *can,
|
||||
const char *name,
|
||||
const struct rt_can_ops *ops,
|
||||
void *data);
|
||||
void rt_hw_can_isr(struct rt_can_device *can, int event);
|
||||
#endif /*_CAN_H*/
|
||||
|
||||
@@ -1,132 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-05-05 linzhenxing first version
|
||||
*/
|
||||
#ifndef __GPT_H
|
||||
#define __GPT_H
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t b[16]; /* GUID 16 bytes*/
|
||||
} guid_t;
|
||||
|
||||
#define MSDOS_MBR_SIGNATURE 0xaa55
|
||||
#define EFI_PMBR_OSTYPE_EFI 0xEF
|
||||
#define EFI_PMBR_OSTYPE_EFI_GPT 0xEE
|
||||
|
||||
#define GPT_MBR_PROTECTIVE 1
|
||||
#define GPT_MBR_HYBRID 2
|
||||
|
||||
#define GPT_HEADER_SIGNATURE 0x5452415020494645ULL
|
||||
#define GPT_HEADER_REVISION_V1 0x00010000
|
||||
#define GPT_PRIMARY_PARTITION_TABLE_LBA 1
|
||||
|
||||
typedef guid_t gpt_guid_t __attribute__ ((aligned (4)));
|
||||
#define EFI_GUID(a, b, c, d...) (gpt_guid_t){ { \
|
||||
(a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
|
||||
(b) & 0xff, ((b) >> 8) & 0xff, \
|
||||
(c) & 0xff, ((c) >> 8) & 0xff, d } }
|
||||
|
||||
#define NULL_GUID \
|
||||
EFI_GUID(0x00000000, 0x0000, 0x0000,\
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
|
||||
#define PARTITION_SYSTEM_GUID \
|
||||
EFI_GUID( 0xC12A7328, 0xF81F, 0x11d2, \
|
||||
0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B)
|
||||
#define LEGACY_MBR_PARTITION_GUID \
|
||||
EFI_GUID( 0x024DEE41, 0x33E7, 0x11d3, \
|
||||
0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F)
|
||||
#define PARTITION_MSFT_RESERVED_GUID \
|
||||
EFI_GUID( 0xE3C9E316, 0x0B5C, 0x4DB8, \
|
||||
0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE)
|
||||
#define PARTITION_BASIC_DATA_GUID \
|
||||
EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \
|
||||
0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7)
|
||||
#define PARTITION_LINUX_RAID_GUID \
|
||||
EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \
|
||||
0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e)
|
||||
#define PARTITION_LINUX_SWAP_GUID \
|
||||
EFI_GUID( 0x0657fd6d, 0xa4ab, 0x43c4, \
|
||||
0x84, 0xe5, 0x09, 0x33, 0xc8, 0x4b, 0x4f, 0x4f)
|
||||
#define PARTITION_LINUX_LVM_GUID \
|
||||
EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
|
||||
0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
|
||||
#pragma pack(push, 1)
|
||||
typedef struct _gpt_header
|
||||
{
|
||||
uint64_t signature;
|
||||
uint32_t revision;
|
||||
uint32_t header_size;
|
||||
uint32_t header_crc32;
|
||||
uint32_t reserved1;
|
||||
uint64_t start_lba; /*GPT head start sector*/
|
||||
uint64_t alternate_lba; /*GPT head alternate sector*/
|
||||
uint64_t first_usable_lba;
|
||||
uint64_t last_usable_lba;
|
||||
gpt_guid_t disk_guid;
|
||||
uint64_t partition_entry_lba;
|
||||
uint32_t num_partition_entries;
|
||||
uint32_t sizeof_partition_entry;
|
||||
uint32_t partition_entry_array_crc32;
|
||||
|
||||
/* The rest of the logical block is reserved by UEFI and must be zero.
|
||||
* EFI standard handles this by:
|
||||
*
|
||||
* uint8_t reserved2[ BlockSize - 92 ];
|
||||
*/
|
||||
} gpt_header;
|
||||
|
||||
typedef struct _gpt_entry_attributes
|
||||
{
|
||||
uint64_t required_to_function:1;
|
||||
uint64_t reserved:47;
|
||||
uint64_t type_guid_specific:16;
|
||||
} gpt_entry_attributes;
|
||||
|
||||
typedef struct _gpt_entry
|
||||
{
|
||||
gpt_guid_t partition_type_guid;
|
||||
gpt_guid_t unique_partition_guid;
|
||||
uint64_t starting_lba;
|
||||
uint64_t ending_lba;
|
||||
gpt_entry_attributes attributes;
|
||||
uint16_t partition_name[72/sizeof(uint16_t)];
|
||||
} gpt_entry;
|
||||
|
||||
typedef struct _gpt_mbr_record
|
||||
{
|
||||
uint8_t boot_indicator; /* unused by EFI, set to 0x80 for bootable */
|
||||
uint8_t start_head; /* unused by EFI, pt start in CHS */
|
||||
uint8_t start_sector; /* unused by EFI, pt start in CHS */
|
||||
uint8_t start_track;
|
||||
uint8_t os_type; /* EFI and legacy non-EFI OS types */
|
||||
uint8_t end_head; /* unused by EFI, pt end in CHS */
|
||||
uint8_t end_sector; /* unused by EFI, pt end in CHS */
|
||||
uint8_t end_track; /* unused by EFI, pt end in CHS */
|
||||
uint32_t starting_lba; /* used by EFI - start addr of the on disk pt */
|
||||
uint32_t size_in_lba; /* used by EFI - size of pt in LBA */
|
||||
} gpt_mbr_record;
|
||||
|
||||
|
||||
typedef struct _legacy_mbr
|
||||
{
|
||||
uint8_t boot_code[440];
|
||||
uint32_t unique_mbr_signature;
|
||||
uint16_t unknown;
|
||||
gpt_mbr_record partition_record[4];
|
||||
uint16_t signature;
|
||||
} legacy_mbr;
|
||||
#pragma pack(pop)
|
||||
|
||||
int check_gpt(struct rt_mmcsd_card *card);
|
||||
int gpt_get_partition_param(struct rt_mmcsd_card *card, struct dfs_partition *part, uint32_t pindex);
|
||||
void gpt_free(void);
|
||||
#endif /*__GPT_H*/
|
||||
@@ -1,42 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2012-04-25 weety first version
|
||||
*/
|
||||
|
||||
#ifndef __I2C_BIT_OPS_H__
|
||||
#define __I2C_BIT_OPS_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct rt_i2c_bit_ops
|
||||
{
|
||||
void *data; /* private data for lowlevel routines */
|
||||
void (*set_sda)(void *data, rt_int32_t state);
|
||||
void (*set_scl)(void *data, rt_int32_t state);
|
||||
rt_int32_t (*get_sda)(void *data);
|
||||
rt_int32_t (*get_scl)(void *data);
|
||||
|
||||
void (*udelay)(rt_uint32_t us);
|
||||
|
||||
rt_uint32_t delay_us; /* scl and sda line delay */
|
||||
rt_uint32_t timeout; /* in tick */
|
||||
|
||||
void (*pin_init)(void);
|
||||
rt_bool_t i2c_pin_init_flag;
|
||||
};
|
||||
|
||||
rt_err_t rt_i2c_bit_add_bus(struct rt_i2c_bus_device *bus,
|
||||
const char *bus_name);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,136 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2012-04-25 weety first version
|
||||
* 2021-04-20 RiceChen added support for bus control api
|
||||
*/
|
||||
|
||||
#ifndef __I2C_H__
|
||||
#define __I2C_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define RT_I2C_WR 0x0000
|
||||
#define RT_I2C_RD (1u << 0)
|
||||
#define RT_I2C_ADDR_10BIT (1u << 2) /* this is a ten bit chip address */
|
||||
#define RT_I2C_NO_START (1u << 4)
|
||||
#define RT_I2C_IGNORE_NACK (1u << 5)
|
||||
#define RT_I2C_NO_READ_ACK (1u << 6) /* when I2C reading, we do not ACK */
|
||||
#define RT_I2C_NO_STOP (1u << 7)
|
||||
|
||||
struct rt_i2c_msg
|
||||
{
|
||||
rt_uint16_t addr;
|
||||
rt_uint16_t flags;
|
||||
rt_uint16_t len;
|
||||
rt_uint8_t *buf;
|
||||
};
|
||||
|
||||
struct rt_i2c_bus_device;
|
||||
|
||||
struct rt_i2c_bus_device_ops
|
||||
{
|
||||
rt_ssize_t (*master_xfer)(struct rt_i2c_bus_device *bus,
|
||||
struct rt_i2c_msg msgs[],
|
||||
rt_uint32_t num);
|
||||
rt_ssize_t (*slave_xfer)(struct rt_i2c_bus_device *bus,
|
||||
struct rt_i2c_msg msgs[],
|
||||
rt_uint32_t num);
|
||||
rt_err_t (*i2c_bus_control)(struct rt_i2c_bus_device *bus,
|
||||
int cmd,
|
||||
void *args);
|
||||
};
|
||||
|
||||
/*for i2c bus driver*/
|
||||
struct rt_i2c_bus_device
|
||||
{
|
||||
struct rt_device parent;
|
||||
const struct rt_i2c_bus_device_ops *ops;
|
||||
rt_uint16_t flags;
|
||||
struct rt_mutex lock;
|
||||
rt_uint32_t timeout;
|
||||
rt_uint32_t retries;
|
||||
void *priv;
|
||||
};
|
||||
|
||||
struct rt_i2c_client
|
||||
{
|
||||
#ifdef RT_USING_DM
|
||||
struct rt_device parent;
|
||||
|
||||
const char *name;
|
||||
const struct rt_i2c_device_id *id;
|
||||
const struct rt_ofw_node_id *ofw_id;
|
||||
#endif
|
||||
struct rt_i2c_bus_device *bus;
|
||||
rt_uint16_t client_addr;
|
||||
};
|
||||
|
||||
#ifdef RT_USING_DM
|
||||
struct rt_i2c_device_id
|
||||
{
|
||||
char name[20];
|
||||
void *data;
|
||||
};
|
||||
|
||||
struct rt_i2c_driver
|
||||
{
|
||||
struct rt_driver parent;
|
||||
|
||||
const struct rt_i2c_device_id *ids;
|
||||
const struct rt_ofw_node_id *ofw_ids;
|
||||
|
||||
rt_err_t (*probe)(struct rt_i2c_client *client);
|
||||
rt_err_t (*remove)(struct rt_i2c_client *client);
|
||||
rt_err_t (*shutdown)(struct rt_i2c_client *client);
|
||||
};
|
||||
|
||||
rt_err_t rt_i2c_driver_register(struct rt_i2c_driver *driver);
|
||||
rt_err_t rt_i2c_device_register(struct rt_i2c_client *client);
|
||||
|
||||
#define RT_I2C_DRIVER_EXPORT(driver) RT_DRIVER_EXPORT(driver, i2c, BUILIN)
|
||||
#endif /* RT_USING_DM */
|
||||
|
||||
rt_err_t rt_i2c_bus_device_register(struct rt_i2c_bus_device *bus,
|
||||
const char *bus_name);
|
||||
struct rt_i2c_bus_device *rt_i2c_bus_device_find(const char *bus_name);
|
||||
rt_ssize_t rt_i2c_transfer(struct rt_i2c_bus_device *bus,
|
||||
struct rt_i2c_msg msgs[],
|
||||
rt_uint32_t num);
|
||||
rt_err_t rt_i2c_control(struct rt_i2c_bus_device *bus,
|
||||
int cmd,
|
||||
void *args);
|
||||
rt_ssize_t rt_i2c_master_send(struct rt_i2c_bus_device *bus,
|
||||
rt_uint16_t addr,
|
||||
rt_uint16_t flags,
|
||||
const rt_uint8_t *buf,
|
||||
rt_uint32_t count);
|
||||
rt_ssize_t rt_i2c_master_recv(struct rt_i2c_bus_device *bus,
|
||||
rt_uint16_t addr,
|
||||
rt_uint16_t flags,
|
||||
rt_uint8_t *buf,
|
||||
rt_uint32_t count);
|
||||
|
||||
rt_inline rt_err_t rt_i2c_bus_lock(struct rt_i2c_bus_device *bus, rt_tick_t timeout)
|
||||
{
|
||||
return rt_mutex_take(&bus->lock, timeout);
|
||||
}
|
||||
|
||||
rt_inline rt_err_t rt_i2c_bus_unlock(struct rt_i2c_bus_device *bus)
|
||||
{
|
||||
return rt_mutex_release(&bus->lock);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,44 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2012-04-25 weety first version
|
||||
* 2021-04-20 RiceChen added bus clock command
|
||||
*/
|
||||
|
||||
#ifndef __I2C_DEV_H__
|
||||
#define __I2C_DEV_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define RT_I2C_DEV_CTRL_10BIT (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x01)
|
||||
#define RT_I2C_DEV_CTRL_ADDR (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x02)
|
||||
#define RT_I2C_DEV_CTRL_TIMEOUT (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x03)
|
||||
#define RT_I2C_DEV_CTRL_RW (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x04)
|
||||
#define RT_I2C_DEV_CTRL_CLK (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x05)
|
||||
#define RT_I2C_DEV_CTRL_UNLOCK (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x06)
|
||||
#define RT_I2C_DEV_CTRL_GET_STATE (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x07)
|
||||
#define RT_I2C_DEV_CTRL_GET_MODE (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x08)
|
||||
#define RT_I2C_DEV_CTRL_GET_ERROR (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x09)
|
||||
|
||||
struct rt_i2c_priv_data
|
||||
{
|
||||
struct rt_i2c_msg *msgs;
|
||||
rt_size_t number;
|
||||
};
|
||||
|
||||
rt_err_t rt_i2c_bus_device_device_init(struct rt_i2c_bus_device *bus,
|
||||
const char *name);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,51 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-11-26 GuEe-GUI first version
|
||||
*/
|
||||
|
||||
#ifndef __I2C_DM_H__
|
||||
#define __I2C_DM_H__
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <drivers/core/bus.h>
|
||||
|
||||
/* I2C Frequency Modes */
|
||||
#define I2C_MAX_STANDARD_MODE_FREQ 100000
|
||||
#define I2C_MAX_FAST_MODE_FREQ 400000
|
||||
#define I2C_MAX_FAST_MODE_PLUS_FREQ 1000000
|
||||
#define I2C_MAX_TURBO_MODE_FREQ 1400000
|
||||
#define I2C_MAX_HIGH_SPEED_MODE_FREQ 3400000
|
||||
#define I2C_MAX_ULTRA_FAST_MODE_FREQ 5000000
|
||||
|
||||
struct i2c_timings
|
||||
{
|
||||
rt_uint32_t bus_freq_hz; /* the bus frequency in Hz */
|
||||
rt_uint32_t scl_rise_ns; /* time SCL signal takes to rise in ns; t(r) in the I2C specification */
|
||||
rt_uint32_t scl_fall_ns; /* time SCL signal takes to fall in ns; t(f) in the I2C specification */
|
||||
rt_uint32_t scl_int_delay_ns; /* time IP core additionally needs to setup SCL in ns */
|
||||
rt_uint32_t sda_fall_ns; /* time SDA signal takes to fall in ns; t(f) in the I2C specification */
|
||||
rt_uint32_t sda_hold_ns; /* time IP core additionally needs to hold SDA in ns */
|
||||
rt_uint32_t digital_filter_width_ns; /* width in ns of spikes on i2c lines that the IP core digital filter can filter out */
|
||||
rt_uint32_t analog_filter_cutoff_freq_hz; /* threshold frequency for the low pass IP core analog filter */
|
||||
};
|
||||
|
||||
#ifdef RT_USING_OFW
|
||||
rt_err_t i2c_timings_ofw_parse(struct rt_ofw_node *dev_np, struct i2c_timings *timings,
|
||||
rt_bool_t use_defaults);
|
||||
#else
|
||||
rt_inline rt_err_t i2c_timings_ofw_parse(struct rt_ofw_node *dev_np, struct i2c_timings *timings,
|
||||
rt_bool_t use_defaults)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
#endif /* RT_USING_OFW */
|
||||
|
||||
void i2c_bus_scan_clients(struct rt_i2c_bus_device *bus);
|
||||
|
||||
#endif /* __I2C_DM_H__ */
|
||||
@@ -1,195 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2015-06-15 hichard first version
|
||||
* 2024-05-25 HPMicro add strobe support
|
||||
*/
|
||||
|
||||
#ifndef __MMC_H__
|
||||
#define __MMC_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/mmcsd_host.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* EXT_CSD fields
|
||||
*/
|
||||
|
||||
#define EXT_CSD_FLUSH_CACHE 32 /* W */
|
||||
#define EXT_CSD_CACHE_CTRL 33 /* R/W */
|
||||
#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
|
||||
#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
|
||||
#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
|
||||
#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
|
||||
#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
|
||||
#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
|
||||
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
|
||||
#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
|
||||
#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
|
||||
#define EXT_CSD_HPI_MGMT 161 /* R/W */
|
||||
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
|
||||
#define EXT_CSD_BKOPS_EN 163 /* R/W */
|
||||
#define EXT_CSD_BKOPS_START 164 /* W */
|
||||
#define EXT_CSD_SANITIZE_START 165 /* W */
|
||||
#define EXT_CSD_WR_REL_PARAM 166 /* RO */
|
||||
#define EXT_CSD_RPMB_MULT 168 /* RO */
|
||||
#define EXT_CSD_BOOT_WP 173 /* R/W */
|
||||
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
|
||||
#define EXT_CSD_PART_CONFIG 179 /* R/W */
|
||||
#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
|
||||
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
|
||||
#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
|
||||
#define EXT_CSD_HS_TIMING 185 /* R/W */
|
||||
#define EXT_CSD_POWER_CLASS 187 /* R/W */
|
||||
#define EXT_CSD_REV 192 /* RO */
|
||||
#define EXT_CSD_STRUCTURE 194 /* RO */
|
||||
#define EXT_CSD_CARD_TYPE 196 /* RO */
|
||||
#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
|
||||
#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
|
||||
#define EXT_CSD_PWR_CL_52_195 200 /* RO */
|
||||
#define EXT_CSD_PWR_CL_26_195 201 /* RO */
|
||||
#define EXT_CSD_PWR_CL_52_360 202 /* RO */
|
||||
#define EXT_CSD_PWR_CL_26_360 203 /* RO */
|
||||
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
|
||||
#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
|
||||
#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
|
||||
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
|
||||
#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
|
||||
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
|
||||
#define EXT_CSD_BOOT_MULT 226 /* RO */
|
||||
#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
|
||||
#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
|
||||
#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
|
||||
#define EXT_CSD_TRIM_MULT 232 /* RO */
|
||||
#define EXT_CSD_PWR_CL_200_195 236 /* RO */
|
||||
#define EXT_CSD_PWR_CL_200_360 237 /* RO */
|
||||
#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
|
||||
#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
|
||||
#define EXT_CSD_BKOPS_STATUS 246 /* RO */
|
||||
#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
|
||||
#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
|
||||
#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
|
||||
#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
|
||||
#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
|
||||
#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
|
||||
#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
|
||||
#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
|
||||
#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
|
||||
#define EXT_CSD_HPI_FEATURES 503 /* RO */
|
||||
|
||||
/*
|
||||
* EXT_CSD field definitions
|
||||
*/
|
||||
|
||||
#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
|
||||
|
||||
#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
|
||||
#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
|
||||
#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
|
||||
#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
|
||||
|
||||
#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
|
||||
|
||||
#define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
|
||||
|
||||
#define EXT_CSD_CMD_SET_NORMAL (1<<0)
|
||||
#define EXT_CSD_CMD_SET_SECURE (1<<1)
|
||||
#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
|
||||
|
||||
#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \
|
||||
EXT_CSD_CARD_TYPE_HS_52)
|
||||
#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
|
||||
/* DDR mode @1.8V or 3V I/O */
|
||||
#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
|
||||
/* DDR mode @1.2V I/O */
|
||||
#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
|
||||
| EXT_CSD_CARD_TYPE_DDR_1_2V)
|
||||
#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
|
||||
/* SDR mode @1.2V I/O */
|
||||
#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
|
||||
EXT_CSD_CARD_TYPE_HS200_1_2V)
|
||||
#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
|
||||
#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
|
||||
#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
|
||||
EXT_CSD_CARD_TYPE_HS400_1_2V)
|
||||
|
||||
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
|
||||
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
|
||||
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
|
||||
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
|
||||
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
|
||||
#define EXT_CSD_DDR_BUS_WIDTH_8_EH_DS 0x86/* Card is in 8 bit DDR mode with Enhanced Data Strobe */
|
||||
|
||||
#define EXT_CSD_TIMING_BC 0 /* Backwards compatibility */
|
||||
#define EXT_CSD_TIMING_HS 1 /* High speed */
|
||||
#define EXT_CSD_TIMING_HS200 2 /* HS200 */
|
||||
#define EXT_CSD_TIMING_HS400 3 /* HS400 */
|
||||
|
||||
#define EXT_CSD_SEC_ER_EN BIT(0)
|
||||
#define EXT_CSD_SEC_BD_BLK_EN BIT(2)
|
||||
#define EXT_CSD_SEC_GB_CL_EN BIT(4)
|
||||
#define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
|
||||
|
||||
#define EXT_CSD_RST_N_EN_MASK 0x3
|
||||
#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
|
||||
|
||||
#define EXT_CSD_NO_POWER_NOTIFICATION 0
|
||||
#define EXT_CSD_POWER_ON 1
|
||||
#define EXT_CSD_POWER_OFF_SHORT 2
|
||||
#define EXT_CSD_POWER_OFF_LONG 3
|
||||
|
||||
#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
|
||||
#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
|
||||
#define EXT_CSD_PWR_CL_8BIT_SHIFT 4
|
||||
#define EXT_CSD_PWR_CL_4BIT_SHIFT 0
|
||||
|
||||
#define EXT_CSD_PACKED_EVENT_EN BIT(3)
|
||||
|
||||
/*
|
||||
* EXCEPTION_EVENT_STATUS field
|
||||
*/
|
||||
#define EXT_CSD_URGENT_BKOPS BIT(0)
|
||||
#define EXT_CSD_DYNCAP_NEEDED BIT(1)
|
||||
#define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2)
|
||||
#define EXT_CSD_PACKED_FAILURE BIT(3)
|
||||
|
||||
#define EXT_CSD_PACKED_GENERIC_ERROR BIT(0)
|
||||
#define EXT_CSD_PACKED_INDEXED_ERROR BIT(1)
|
||||
|
||||
/*
|
||||
* BKOPS status level
|
||||
*/
|
||||
#define EXT_CSD_BKOPS_LEVEL_2 0x2
|
||||
/*
|
||||
* MMC_SWITCH access modes
|
||||
*/
|
||||
#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
|
||||
#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
|
||||
#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
|
||||
#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
|
||||
|
||||
/*
|
||||
* extern function
|
||||
*/
|
||||
rt_err_t mmc_send_op_cond(struct rt_mmcsd_host *host, rt_uint32_t ocr, rt_uint32_t *rocr);
|
||||
rt_int32_t init_mmc(struct rt_mmcsd_host *host, rt_uint32_t ocr);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,262 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-07-25 weety first version
|
||||
*/
|
||||
|
||||
#ifndef __CORE_H__
|
||||
#define __CORE_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/mmcsd_host.h>
|
||||
#include <drivers/mmcsd_card.h>
|
||||
#include <drivers/mmcsd_cmd.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef RT_MMCSD_DBG
|
||||
#define mmcsd_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__)
|
||||
#else
|
||||
#define mmcsd_dbg(fmt, ...)
|
||||
#endif
|
||||
|
||||
struct rt_mmcsd_data
|
||||
{
|
||||
rt_uint32_t blksize;
|
||||
rt_uint32_t blks;
|
||||
rt_uint32_t *buf;
|
||||
rt_int32_t err;
|
||||
rt_uint32_t flags;
|
||||
#define DATA_DIR_WRITE (1 << 0)
|
||||
#define DATA_DIR_READ (1 << 1)
|
||||
#define DATA_STREAM (1 << 2)
|
||||
|
||||
unsigned int bytes_xfered;
|
||||
|
||||
struct rt_mmcsd_cmd *stop; /* stop command */
|
||||
struct rt_mmcsd_req *mrq; /* associated request */
|
||||
|
||||
rt_uint32_t timeout_ns;
|
||||
rt_uint32_t timeout_clks;
|
||||
|
||||
void *sg; /* scatter list */
|
||||
rt_uint16_t sg_len; /* size of scatter list */
|
||||
rt_int16_t sg_count; /* mapped sg entries */
|
||||
rt_ubase_t host_cookie; /* host driver private data */
|
||||
};
|
||||
|
||||
struct rt_mmcsd_cmd
|
||||
{
|
||||
rt_uint32_t cmd_code;
|
||||
rt_uint32_t arg;
|
||||
rt_uint32_t resp[4];
|
||||
rt_uint32_t flags;
|
||||
/*rsponse types
|
||||
*bits:0~3
|
||||
*/
|
||||
#define RESP_MASK (0xF)
|
||||
#define RESP_NONE (0)
|
||||
#define RESP_R1 (1 << 0)
|
||||
#define RESP_R1B (2 << 0)
|
||||
#define RESP_R2 (3 << 0)
|
||||
#define RESP_R3 (4 << 0)
|
||||
#define RESP_R4 (5 << 0)
|
||||
#define RESP_R6 (6 << 0)
|
||||
#define RESP_R7 (7 << 0)
|
||||
#define RESP_R5 (8 << 0) /*SDIO command response type*/
|
||||
/*command types
|
||||
*bits:4~5
|
||||
*/
|
||||
#define CMD_MASK (3 << 4) /* command type */
|
||||
#define CMD_AC (0 << 4)
|
||||
#define CMD_ADTC (1 << 4)
|
||||
#define CMD_BC (2 << 4)
|
||||
#define CMD_BCR (3 << 4)
|
||||
|
||||
#define resp_type(cmd) ((cmd)->flags & RESP_MASK)
|
||||
|
||||
/*spi rsponse types
|
||||
*bits:6~8
|
||||
*/
|
||||
#define RESP_SPI_MASK (0x7 << 6)
|
||||
#define RESP_SPI_R1 (1 << 6)
|
||||
#define RESP_SPI_R1B (2 << 6)
|
||||
#define RESP_SPI_R2 (3 << 6)
|
||||
#define RESP_SPI_R3 (4 << 6)
|
||||
#define RESP_SPI_R4 (5 << 6)
|
||||
#define RESP_SPI_R5 (6 << 6)
|
||||
#define RESP_SPI_R7 (7 << 6)
|
||||
|
||||
#define spi_resp_type(cmd) ((cmd)->flags & RESP_SPI_MASK)
|
||||
/*
|
||||
* These are the command types.
|
||||
*/
|
||||
#define cmd_type(cmd) ((cmd)->flags & CMD_MASK)
|
||||
|
||||
rt_int32_t retries; /* max number of retries */
|
||||
rt_int32_t err;
|
||||
unsigned int busy_timeout; /* busy detect timeout in ms */
|
||||
|
||||
struct rt_mmcsd_data *data;
|
||||
struct rt_mmcsd_req *mrq; /* associated request */
|
||||
};
|
||||
|
||||
struct rt_mmcsd_req
|
||||
{
|
||||
struct rt_mmcsd_data *data;
|
||||
struct rt_mmcsd_cmd *cmd;
|
||||
struct rt_mmcsd_cmd *stop;
|
||||
struct rt_mmcsd_cmd *sbc; /* SET_BLOCK_COUNT for multiblock */
|
||||
/* Allow other commands during this ongoing data transfer or busy wait */
|
||||
int cap_cmd_during_tfr;
|
||||
};
|
||||
|
||||
/*the following is response bit*/
|
||||
#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
|
||||
#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
|
||||
#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
|
||||
#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
|
||||
#define R1_ERASE_PARAM (1 << 27) /* ex, c */
|
||||
#define R1_WP_VIOLATION (1 << 26) /* erx, c */
|
||||
#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
|
||||
#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
|
||||
#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
|
||||
#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
|
||||
#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
|
||||
#define R1_CC_ERROR (1 << 20) /* erx, c */
|
||||
#define R1_ERROR (1 << 19) /* erx, c */
|
||||
#define R1_UNDERRUN (1 << 18) /* ex, c */
|
||||
#define R1_OVERRUN (1 << 17) /* ex, c */
|
||||
#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
|
||||
#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
|
||||
#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
|
||||
#define R1_ERASE_RESET (1 << 13) /* sr, c */
|
||||
#define R1_STATUS(x) (x & 0xFFFFE000)
|
||||
#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
|
||||
#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
|
||||
#define R1_APP_CMD (1 << 5) /* sr, c */
|
||||
|
||||
|
||||
#define R1_SPI_IDLE (1 << 0)
|
||||
#define R1_SPI_ERASE_RESET (1 << 1)
|
||||
#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
|
||||
#define R1_SPI_COM_CRC (1 << 3)
|
||||
#define R1_SPI_ERASE_SEQ (1 << 4)
|
||||
#define R1_SPI_ADDRESS (1 << 5)
|
||||
#define R1_SPI_PARAMETER (1 << 6)
|
||||
/* R1 bit 7 is always zero */
|
||||
#define R2_SPI_CARD_LOCKED (1 << 8)
|
||||
#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
|
||||
#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
|
||||
#define R2_SPI_ERROR (1 << 10)
|
||||
#define R2_SPI_CC_ERROR (1 << 11)
|
||||
#define R2_SPI_CARD_ECC_ERROR (1 << 12)
|
||||
#define R2_SPI_WP_VIOLATION (1 << 13)
|
||||
#define R2_SPI_ERASE_PARAM (1 << 14)
|
||||
#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
|
||||
#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
|
||||
|
||||
#define CARD_BUSY 0x80000000 /* Card Power up status bit */
|
||||
|
||||
/* R5 response bits */
|
||||
#define R5_COM_CRC_ERROR (1 << 15)
|
||||
#define R5_ILLEGAL_COMMAND (1 << 14)
|
||||
#define R5_ERROR (1 << 11)
|
||||
#define R5_FUNCTION_NUMBER (1 << 9)
|
||||
#define R5_OUT_OF_RANGE (1 << 8)
|
||||
#define R5_STATUS(x) (x & 0xCB00)
|
||||
#define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12)
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* fls - find last (most-significant) bit set
|
||||
* @x: the word to search
|
||||
*
|
||||
* This is defined the same way as ffs.
|
||||
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
|
||||
*/
|
||||
|
||||
rt_inline rt_uint32_t __rt_fls(rt_uint32_t val)
|
||||
{
|
||||
rt_uint32_t bit = 32;
|
||||
|
||||
if (!val)
|
||||
return 0;
|
||||
if (!(val & 0xffff0000u))
|
||||
{
|
||||
val <<= 16;
|
||||
bit -= 16;
|
||||
}
|
||||
if (!(val & 0xff000000u))
|
||||
{
|
||||
val <<= 8;
|
||||
bit -= 8;
|
||||
}
|
||||
if (!(val & 0xf0000000u))
|
||||
{
|
||||
val <<= 4;
|
||||
bit -= 4;
|
||||
}
|
||||
if (!(val & 0xc0000000u))
|
||||
{
|
||||
val <<= 2;
|
||||
bit -= 2;
|
||||
}
|
||||
if (!(val & 0x80000000u))
|
||||
{
|
||||
bit -= 1;
|
||||
}
|
||||
|
||||
return bit;
|
||||
}
|
||||
|
||||
#define MMCSD_HOST_PLUGED 0
|
||||
#define MMCSD_HOST_UNPLUGED 1
|
||||
|
||||
rt_int32_t mmcsd_excute_tuning(struct rt_mmcsd_card *card);
|
||||
int mmcsd_wait_cd_changed(rt_int32_t timeout);
|
||||
void mmcsd_host_lock(struct rt_mmcsd_host *host);
|
||||
void mmcsd_host_unlock(struct rt_mmcsd_host *host);
|
||||
void mmcsd_req_complete(struct rt_mmcsd_host *host);
|
||||
void mmcsd_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req);
|
||||
rt_int32_t mmcsd_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd, int retries);
|
||||
rt_int32_t mmcsd_go_idle(struct rt_mmcsd_host *host);
|
||||
rt_int32_t mmcsd_spi_read_ocr(struct rt_mmcsd_host *host, rt_int32_t high_capacity, rt_uint32_t *ocr);
|
||||
rt_int32_t mmcsd_all_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid);
|
||||
rt_int32_t mmcsd_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid);
|
||||
rt_int32_t mmcsd_get_csd(struct rt_mmcsd_card *card, rt_uint32_t *csd);
|
||||
rt_int32_t mmcsd_select_card(struct rt_mmcsd_card *card);
|
||||
rt_int32_t mmcsd_deselect_cards(struct rt_mmcsd_card *host);
|
||||
rt_int32_t mmcsd_spi_use_crc(struct rt_mmcsd_host *host, rt_int32_t use_crc);
|
||||
void mmcsd_set_chip_select(struct rt_mmcsd_host *host, rt_int32_t mode);
|
||||
void mmcsd_set_clock(struct rt_mmcsd_host *host, rt_uint32_t clk);
|
||||
void mmcsd_set_bus_mode(struct rt_mmcsd_host *host, rt_uint32_t mode);
|
||||
void mmcsd_set_bus_width(struct rt_mmcsd_host *host, rt_uint32_t width);
|
||||
void mmcsd_set_timing(struct rt_mmcsd_host *host, rt_uint32_t timing);
|
||||
void mmcsd_set_data_timeout(struct rt_mmcsd_data *data, const struct rt_mmcsd_card *card);
|
||||
rt_uint32_t mmcsd_select_voltage(struct rt_mmcsd_host *host, rt_uint32_t ocr);
|
||||
void mmcsd_change(struct rt_mmcsd_host *host);
|
||||
void mmcsd_detect(void *param);
|
||||
void mmcsd_host_init(struct rt_mmcsd_host *host);
|
||||
struct rt_mmcsd_host *mmcsd_alloc_host(void);
|
||||
void mmcsd_free_host(struct rt_mmcsd_host *host);
|
||||
int rt_mmcsd_core_init(void);
|
||||
|
||||
int rt_mmcsd_blk_init(void);
|
||||
rt_int32_t read_lba(struct rt_mmcsd_card *card, size_t lba, uint8_t *buffer, size_t count);
|
||||
rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card);
|
||||
void rt_mmcsd_blk_remove(struct rt_mmcsd_card *card);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,43 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-10-14 wangqiang the first version
|
||||
*/
|
||||
|
||||
#ifndef __MDIO_H__
|
||||
#define __MDIO_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
struct rt_mdio_bus_ops
|
||||
{
|
||||
rt_bool_t (*init)(void *bus, rt_uint32_t src_clock_hz);
|
||||
rt_size_t (*read)(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size);
|
||||
rt_size_t (*write)(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size);
|
||||
rt_bool_t (*uninit)(void *bus);
|
||||
};
|
||||
|
||||
struct rt_mdio_bus
|
||||
{
|
||||
void *hw_obj;
|
||||
char *name;
|
||||
struct rt_mdio_bus_ops *ops;
|
||||
};
|
||||
|
||||
typedef struct rt_mdio_bus rt_mdio_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,178 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2015-01-20 Bernard the first version
|
||||
* 2017-10-20 ZYH add mode open drain and input pull down
|
||||
*/
|
||||
|
||||
#ifndef PIN_H__
|
||||
#define PIN_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_DM
|
||||
#include <drivers/pic.h>
|
||||
|
||||
struct rt_pin_irqchip
|
||||
{
|
||||
struct rt_pic parent;
|
||||
|
||||
int irq;
|
||||
rt_base_t pin_range[2];
|
||||
};
|
||||
#endif /* RT_USING_DM */
|
||||
|
||||
/* pin device and operations for RT-Thread */
|
||||
struct rt_device_pin
|
||||
{
|
||||
struct rt_device parent;
|
||||
#ifdef RT_USING_DM
|
||||
struct rt_pin_irqchip irqchip;
|
||||
#endif /* RT_USING_DM */
|
||||
const struct rt_pin_ops *ops;
|
||||
};
|
||||
|
||||
#define PIN_NONE (-1)
|
||||
|
||||
#define PIN_LOW 0x00
|
||||
#define PIN_HIGH 0x01
|
||||
|
||||
#define PIN_MODE_OUTPUT 0x00
|
||||
#define PIN_MODE_INPUT 0x01
|
||||
#define PIN_MODE_INPUT_PULLUP 0x02
|
||||
#define PIN_MODE_INPUT_PULLDOWN 0x03
|
||||
#define PIN_MODE_OUTPUT_OD 0x04
|
||||
|
||||
#ifdef RT_USING_PINCTRL
|
||||
enum
|
||||
{
|
||||
PIN_CONFIG_BIAS_BUS_HOLD,
|
||||
PIN_CONFIG_BIAS_DISABLE,
|
||||
PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
|
||||
PIN_CONFIG_BIAS_PULL_DOWN,
|
||||
PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
|
||||
PIN_CONFIG_BIAS_PULL_UP,
|
||||
PIN_CONFIG_DRIVE_OPEN_DRAIN,
|
||||
PIN_CONFIG_DRIVE_OPEN_SOURCE,
|
||||
PIN_CONFIG_DRIVE_PUSH_PULL,
|
||||
PIN_CONFIG_DRIVE_STRENGTH,
|
||||
PIN_CONFIG_DRIVE_STRENGTH_UA,
|
||||
PIN_CONFIG_INPUT_DEBOUNCE,
|
||||
PIN_CONFIG_INPUT_ENABLE,
|
||||
PIN_CONFIG_INPUT_SCHMITT,
|
||||
PIN_CONFIG_INPUT_SCHMITT_ENABLE,
|
||||
PIN_CONFIG_MODE_LOW_POWER,
|
||||
PIN_CONFIG_MODE_PWM,
|
||||
PIN_CONFIG_OUTPUT,
|
||||
PIN_CONFIG_OUTPUT_ENABLE,
|
||||
PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS,
|
||||
PIN_CONFIG_PERSIST_STATE,
|
||||
PIN_CONFIG_POWER_SOURCE,
|
||||
PIN_CONFIG_SKEW_DELAY,
|
||||
PIN_CONFIG_SLEEP_HARDWARE_STATE,
|
||||
PIN_CONFIG_SLEW_RATE,
|
||||
PIN_CONFIG_END = 0x7f,
|
||||
PIN_CONFIG_MAX = 0xff,
|
||||
};
|
||||
#endif /* RT_USING_PINCTRL */
|
||||
|
||||
#define PIN_IRQ_MODE_RISING 0x00
|
||||
#define PIN_IRQ_MODE_FALLING 0x01
|
||||
#define PIN_IRQ_MODE_RISING_FALLING 0x02
|
||||
#define PIN_IRQ_MODE_HIGH_LEVEL 0x03
|
||||
#define PIN_IRQ_MODE_LOW_LEVEL 0x04
|
||||
|
||||
#define PIN_IRQ_DISABLE 0x00
|
||||
#define PIN_IRQ_ENABLE 0x01
|
||||
|
||||
#define PIN_IRQ_PIN_NONE PIN_NONE
|
||||
|
||||
struct rt_device_pin_mode
|
||||
{
|
||||
rt_base_t pin;
|
||||
rt_uint8_t mode; /* e.g. PIN_MODE_OUTPUT */
|
||||
};
|
||||
|
||||
struct rt_device_pin_value
|
||||
{
|
||||
rt_base_t pin;
|
||||
rt_uint8_t value; /* PIN_LOW or PIN_HIGH */
|
||||
};
|
||||
|
||||
struct rt_pin_irq_hdr
|
||||
{
|
||||
rt_base_t pin;
|
||||
rt_uint8_t mode; /* e.g. PIN_IRQ_MODE_RISING */
|
||||
void (*hdr)(void *args);
|
||||
void *args;
|
||||
};
|
||||
|
||||
#ifdef RT_USING_PINCTRL
|
||||
struct rt_pin_ctrl_conf_params
|
||||
{
|
||||
const char *propname;
|
||||
rt_uint32_t param;
|
||||
rt_uint32_t default_value;
|
||||
};
|
||||
#endif /* RT_USING_PINCTRL */
|
||||
|
||||
struct rt_pin_ops
|
||||
{
|
||||
void (*pin_mode)(struct rt_device *device, rt_base_t pin, rt_uint8_t mode);
|
||||
void (*pin_write)(struct rt_device *device, rt_base_t pin, rt_uint8_t value);
|
||||
rt_ssize_t (*pin_read)(struct rt_device *device, rt_base_t pin);
|
||||
rt_err_t (*pin_attach_irq)(struct rt_device *device, rt_base_t pin,
|
||||
rt_uint8_t mode, void (*hdr)(void *args), void *args);
|
||||
rt_err_t (*pin_detach_irq)(struct rt_device *device, rt_base_t pin);
|
||||
rt_err_t (*pin_irq_enable)(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled);
|
||||
rt_base_t (*pin_get)(const char *name);
|
||||
#ifdef RT_USING_DM
|
||||
rt_err_t (*pin_irq_mode)(struct rt_device *device, rt_base_t pin, rt_uint8_t mode);
|
||||
rt_ssize_t (*pin_parse)(struct rt_device *device, struct rt_ofw_cell_args *args, rt_uint32_t *flags);
|
||||
#endif
|
||||
#ifdef RT_USING_PINCTRL
|
||||
rt_err_t (*pin_ctrl_confs_apply)(struct rt_device *device, void *fw_conf_np);
|
||||
#endif /* RT_USING_PINCTRL */
|
||||
};
|
||||
|
||||
int rt_device_pin_register(const char *name, const struct rt_pin_ops *ops, void *user_data);
|
||||
void rt_pin_mode(rt_base_t pin, rt_uint8_t mode);
|
||||
void rt_pin_write(rt_base_t pin, rt_ssize_t value);
|
||||
rt_ssize_t rt_pin_read(rt_base_t pin);
|
||||
rt_base_t rt_pin_get(const char *name);
|
||||
rt_err_t rt_pin_attach_irq(rt_base_t pin, rt_uint8_t mode,
|
||||
void (*hdr)(void *args), void *args);
|
||||
rt_err_t rt_pin_detach_irq(rt_base_t pin);
|
||||
rt_err_t rt_pin_irq_enable(rt_base_t pin, rt_uint8_t enabled);
|
||||
|
||||
#ifdef RT_USING_DM
|
||||
rt_ssize_t rt_pin_get_named_pin(struct rt_device *dev, const char *propname, int index,
|
||||
rt_uint8_t *out_mode, rt_uint8_t *out_value);
|
||||
rt_ssize_t rt_pin_get_named_pin_count(struct rt_device *dev, const char *propname);
|
||||
|
||||
#ifdef RT_USING_OFW
|
||||
rt_ssize_t rt_ofw_get_named_pin(struct rt_ofw_node *np, const char *propname, int index,
|
||||
rt_uint8_t *out_mode, rt_uint8_t *out_value);
|
||||
rt_ssize_t rt_ofw_get_named_pin_count(struct rt_ofw_node *np, const char *propname);
|
||||
#endif
|
||||
#endif /* RT_USING_DM */
|
||||
|
||||
#ifdef RT_USING_PINCTRL
|
||||
rt_ssize_t rt_pin_ctrl_confs_lookup(struct rt_device *device, const char *name);
|
||||
rt_err_t rt_pin_ctrl_confs_apply(struct rt_device *device, int index);
|
||||
rt_err_t rt_pin_ctrl_confs_apply_by_name(struct rt_device *device, const char *name);
|
||||
#endif /* RT_USING_PINCTRL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,66 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-05-07 aozima the first version
|
||||
* 2022-09-24 yuqi add phase and dead time configuration
|
||||
*/
|
||||
|
||||
#ifndef __DRV_PWM_H_INCLUDE__
|
||||
#define __DRV_PWM_H_INCLUDE__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#define PWM_CMD_ENABLE (RT_DEVICE_CTRL_BASE(PWM) + 0)
|
||||
#define PWM_CMD_DISABLE (RT_DEVICE_CTRL_BASE(PWM) + 1)
|
||||
#define PWM_CMD_SET (RT_DEVICE_CTRL_BASE(PWM) + 2)
|
||||
#define PWM_CMD_GET (RT_DEVICE_CTRL_BASE(PWM) + 3)
|
||||
#define PWMN_CMD_ENABLE (RT_DEVICE_CTRL_BASE(PWM) + 4)
|
||||
#define PWMN_CMD_DISABLE (RT_DEVICE_CTRL_BASE(PWM) + 5)
|
||||
#define PWM_CMD_SET_PERIOD (RT_DEVICE_CTRL_BASE(PWM) + 6)
|
||||
#define PWM_CMD_SET_PULSE (RT_DEVICE_CTRL_BASE(PWM) + 7)
|
||||
#define PWM_CMD_SET_DEAD_TIME (RT_DEVICE_CTRL_BASE(PWM) + 8)
|
||||
#define PWM_CMD_SET_PHASE (RT_DEVICE_CTRL_BASE(PWM) + 9)
|
||||
#define PWM_CMD_ENABLE_IRQ (RT_DEVICE_CTRL_BASE(PWM) + 10)
|
||||
#define PWM_CMD_DISABLE_IRQ (RT_DEVICE_CTRL_BASE(PWM) + 11)
|
||||
|
||||
struct rt_pwm_configuration
|
||||
{
|
||||
rt_uint32_t channel; /* 0 ~ n or 0 ~ -n, which depends on specific MCU requirements */
|
||||
rt_uint32_t period; /* unit:ns 1ns~4.29s:1Ghz~0.23hz */
|
||||
rt_uint32_t pulse; /* unit:ns (pulse<=period) */
|
||||
rt_uint32_t dead_time; /* unit:ns */
|
||||
rt_uint32_t phase; /*unit: degree, 0~360, which is the phase of pwm output, */
|
||||
/*
|
||||
* RT_TRUE : The channel of pwm is complememtary.
|
||||
* RT_FALSE : The channel of pwm is nomal.
|
||||
*/
|
||||
rt_bool_t complementary;
|
||||
};
|
||||
|
||||
struct rt_device_pwm;
|
||||
struct rt_pwm_ops
|
||||
{
|
||||
rt_err_t (*control)(struct rt_device_pwm *device, int cmd, void *arg);
|
||||
};
|
||||
|
||||
struct rt_device_pwm
|
||||
{
|
||||
struct rt_device parent;
|
||||
const struct rt_pwm_ops *ops;
|
||||
};
|
||||
|
||||
rt_err_t rt_device_pwm_register(struct rt_device_pwm *device, const char *name, const struct rt_pwm_ops *ops, const void *user_data);
|
||||
|
||||
rt_err_t rt_pwm_enable(struct rt_device_pwm *device, int channel);
|
||||
rt_err_t rt_pwm_disable(struct rt_device_pwm *device, int channel);
|
||||
rt_err_t rt_pwm_set(struct rt_device_pwm *device, int channel, rt_uint32_t period, rt_uint32_t pulse);
|
||||
rt_err_t rt_pwm_set_period(struct rt_device_pwm *device, int channel, rt_uint32_t period);
|
||||
rt_err_t rt_pwm_set_pulse(struct rt_device_pwm *device, int channel, rt_uint32_t pulse);
|
||||
rt_err_t rt_pwm_set_dead_time(struct rt_device_pwm *device, int channel, rt_uint32_t dead_time);
|
||||
rt_err_t rt_pwm_set_phase(struct rt_device_pwm *device, int channel, rt_uint32_t phase);
|
||||
|
||||
#endif /* __DRV_PWM_H_INCLUDE__ */
|
||||
@@ -1,82 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2012-10-10 aozima first version.
|
||||
* 2021-06-11 iysheng implement RTC framework V2.0
|
||||
* 2021-07-30 Meco Man move rtc_core.h to rtc.h
|
||||
* 2022-04-05 tyx add timestamp function
|
||||
*/
|
||||
|
||||
#ifndef __RTC_H__
|
||||
#define __RTC_H__
|
||||
|
||||
#include <rtdef.h>
|
||||
#include <sys/time.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define RT_DEVICE_CTRL_RTC_GET_TIME (RT_DEVICE_CTRL_BASE(RTC) + 0x01) /**< get second time */
|
||||
#define RT_DEVICE_CTRL_RTC_SET_TIME (RT_DEVICE_CTRL_BASE(RTC) + 0x02) /**< set second time */
|
||||
#define RT_DEVICE_CTRL_RTC_GET_TIMEVAL (RT_DEVICE_CTRL_BASE(RTC) + 0x03) /**< get timeval for gettimeofday */
|
||||
#define RT_DEVICE_CTRL_RTC_SET_TIMEVAL (RT_DEVICE_CTRL_BASE(RTC) + 0x04) /**< set timeval for gettimeofday */
|
||||
#define RT_DEVICE_CTRL_RTC_GET_ALARM (RT_DEVICE_CTRL_BASE(RTC) + 0x05) /**< get alarm */
|
||||
#define RT_DEVICE_CTRL_RTC_SET_ALARM (RT_DEVICE_CTRL_BASE(RTC) + 0x06) /**< set alarm */
|
||||
#define RT_DEVICE_CTRL_RTC_GET_TIMESPEC (RT_DEVICE_CTRL_BASE(RTC) + 0x07) /**< get timespec for clock_gettime */
|
||||
#define RT_DEVICE_CTRL_RTC_SET_TIMESPEC (RT_DEVICE_CTRL_BASE(RTC) + 0x08) /**< set timespec for clock_settime */
|
||||
#define RT_DEVICE_CTRL_RTC_GET_TIMERES (RT_DEVICE_CTRL_BASE(RTC) + 0x09) /**< get resolution for clock_getres */
|
||||
|
||||
/* used for alarm function */
|
||||
struct rt_rtc_wkalarm
|
||||
{
|
||||
rt_bool_t enable; /* 0 = alarm disabled, 1 = alarm enabled */
|
||||
rt_int32_t tm_sec; /* alarm at tm_sec */
|
||||
rt_int32_t tm_min; /* alarm at tm_min */
|
||||
rt_int32_t tm_hour; /* alarm at tm_hour */
|
||||
rt_int32_t tm_mday; /* alarm at tm_mday */
|
||||
rt_int32_t tm_mon; /* alarm at tm_mon */
|
||||
rt_int32_t tm_year; /* alarm at tm_year */
|
||||
};
|
||||
|
||||
struct rt_rtc_ops
|
||||
{
|
||||
rt_err_t (*init)(void);
|
||||
rt_err_t (*get_secs)(time_t *sec);
|
||||
rt_err_t (*set_secs)(time_t *sec);
|
||||
rt_err_t (*get_alarm)(struct rt_rtc_wkalarm *alarm);
|
||||
rt_err_t (*set_alarm)(struct rt_rtc_wkalarm *alarm);
|
||||
rt_err_t (*get_timeval)(struct timeval *tv);
|
||||
rt_err_t (*set_timeval)(struct timeval *tv);
|
||||
};
|
||||
|
||||
typedef struct rt_rtc_device
|
||||
{
|
||||
struct rt_device parent;
|
||||
const struct rt_rtc_ops *ops;
|
||||
} rt_rtc_dev_t;
|
||||
|
||||
rt_err_t rt_hw_rtc_register(rt_rtc_dev_t *rtc,
|
||||
const char *name,
|
||||
rt_uint32_t flag,
|
||||
void *data);
|
||||
|
||||
rt_err_t set_date(rt_uint32_t year, rt_uint32_t month, rt_uint32_t day);
|
||||
rt_err_t set_time(rt_uint32_t hour, rt_uint32_t minute, rt_uint32_t second);
|
||||
rt_err_t set_timestamp(time_t timestamp);
|
||||
rt_err_t get_timestamp(time_t *timestamp);
|
||||
|
||||
#ifdef RT_USING_SYSTEM_WORKQUEUE
|
||||
rt_err_t rt_soft_rtc_sync(void);
|
||||
rt_err_t rt_soft_rtc_set_source(const char *name);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __RTC_H__ */
|
||||
@@ -1,45 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-07-25 weety first version
|
||||
* 2024-05-26 HPMicro Add UHS-I support
|
||||
*/
|
||||
|
||||
#ifndef __SD_H__
|
||||
#define __SD_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/mmcsd_host.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* SWITCH_FUNC timing
|
||||
*/
|
||||
#define SD_SWITCH_FUNC_TIMING_DEFAULT 0
|
||||
#define SD_SWITCH_FUNC_TIMING_HS 1
|
||||
#define SD_SWITCH_FUNC_TIMING_SDR50 2
|
||||
#define SD_SWITCH_FUNC_TIMING_SDR104 3
|
||||
#define SD_SWITCH_FUNC_TIMING_DDR50 4
|
||||
|
||||
|
||||
rt_err_t mmcsd_send_if_cond(struct rt_mmcsd_host *host, rt_uint32_t ocr);
|
||||
rt_err_t mmcsd_send_app_op_cond(struct rt_mmcsd_host *host, rt_uint32_t ocr, rt_uint32_t *rocr);
|
||||
|
||||
rt_err_t mmcsd_get_card_addr(struct rt_mmcsd_host *host, rt_uint32_t *rca);
|
||||
rt_int32_t mmcsd_get_scr(struct rt_mmcsd_card *card, rt_uint32_t *scr);
|
||||
|
||||
rt_int32_t init_sd(struct rt_mmcsd_host *host, rt_uint32_t ocr);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,231 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2012-01-15 weety first version
|
||||
*/
|
||||
|
||||
#ifndef __SDIO_H__
|
||||
#define __SDIO_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/mmcsd_host.h>
|
||||
#include <drivers/mmcsd_card.h>
|
||||
#include <drivers/sdio_func_ids.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Card Common Control Registers (CCCR)
|
||||
*/
|
||||
|
||||
#define SDIO_REG_CCCR_CCCR_REV 0x00
|
||||
|
||||
#define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */
|
||||
#define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */
|
||||
#define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */
|
||||
#define SDIO_CCCR_REV_3_00 3 /* CCCR/FBR Version 2.00 */
|
||||
|
||||
#define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */
|
||||
#define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */
|
||||
#define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */
|
||||
#define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */
|
||||
|
||||
#define SDIO_REG_CCCR_SD_REV 0x01
|
||||
|
||||
#define SDIO_SD_REV_1_01 0 /* SD Physical Spec Version 1.01 */
|
||||
#define SDIO_SD_REV_1_10 1 /* SD Physical Spec Version 1.10 */
|
||||
#define SDIO_SD_REV_2_00 2 /* SD Physical Spec Version 2.00 */
|
||||
|
||||
#define SDIO_REG_CCCR_IO_EN 0x02
|
||||
#define SDIO_REG_CCCR_IO_RDY 0x03
|
||||
|
||||
#define SDIO_REG_CCCR_INT_EN 0x04 /* Function/Master Interrupt Enable */
|
||||
#define SDIO_REG_CCCR_INT_PEND 0x05 /* Function Interrupt Pending */
|
||||
|
||||
#define SDIO_REG_CCCR_IO_ABORT 0x06 /* function abort/card reset */
|
||||
|
||||
#define SDIO_REG_CCCR_BUS_IF 0x07 /* bus interface controls */
|
||||
|
||||
#define SDIO_BUS_WIDTH_1BIT 0x00
|
||||
#define SDIO_BUS_WIDTH_4BIT 0x02
|
||||
#define SDIO_BUS_ECSI 0x20 /* Enable continuous SPI interrupt */
|
||||
#define SDIO_BUS_SCSI 0x40 /* Support continuous SPI interrupt */
|
||||
|
||||
#define SDIO_BUS_ASYNC_INT 0x20
|
||||
|
||||
#define SDIO_BUS_CD_DISABLE 0x80 /* disable pull-up on DAT3 (pin 1) */
|
||||
|
||||
#define SDIO_REG_CCCR_CARD_CAPS 0x08
|
||||
|
||||
#define SDIO_CCCR_CAP_SDC 0x01 /* can do CMD52 while data transfer */
|
||||
#define SDIO_CCCR_CAP_SMB 0x02 /* can do multi-block xfers (CMD53) */
|
||||
#define SDIO_CCCR_CAP_SRW 0x04 /* supports read-wait protocol */
|
||||
#define SDIO_CCCR_CAP_SBS 0x08 /* supports suspend/resume */
|
||||
#define SDIO_CCCR_CAP_S4MI 0x10 /* interrupt during 4-bit CMD53 */
|
||||
#define SDIO_CCCR_CAP_E4MI 0x20 /* enable ints during 4-bit CMD53 */
|
||||
#define SDIO_CCCR_CAP_LSC 0x40 /* low speed card */
|
||||
#define SDIO_CCCR_CAP_4BLS 0x80 /* 4 bit low speed card */
|
||||
|
||||
#define SDIO_REG_CCCR_CIS_PTR 0x09 /* common CIS pointer (3 bytes) */
|
||||
|
||||
/* Following 4 regs are valid only if SBS is set */
|
||||
#define SDIO_REG_CCCR_BUS_SUSPEND 0x0c
|
||||
#define SDIO_REG_CCCR_FUNC_SEL 0x0d
|
||||
#define SDIO_REG_CCCR_EXEC_FLAG 0x0e
|
||||
#define SDIO_REG_CCCR_READY_FLAG 0x0f
|
||||
|
||||
#define SDIO_REG_CCCR_FN0_BLKSIZE 0x10 /* 2bytes, 0x10~0x11 */
|
||||
|
||||
#define SDIO_REG_CCCR_POWER_CTRL 0x12
|
||||
|
||||
#define SDIO_POWER_SMPC 0x01 /* Supports Master Power Control */
|
||||
#define SDIO_POWER_EMPC 0x02 /* Enable Master Power Control */
|
||||
|
||||
#define SDIO_REG_CCCR_SPEED 0x13
|
||||
|
||||
#define SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */
|
||||
#define SDIO_SPEED_EHS 0x02 /* Enable High-Speed mode */
|
||||
|
||||
/*
|
||||
* Function Basic Registers (FBR)
|
||||
*/
|
||||
|
||||
#define SDIO_REG_FBR_BASE(f) ((f) * 0x100) /* base of function f's FBRs */
|
||||
|
||||
#define SDIO_REG_FBR_STD_FUNC_IF 0x00
|
||||
|
||||
#define SDIO_FBR_SUPPORTS_CSA 0x40 /* supports Code Storage Area */
|
||||
#define SDIO_FBR_ENABLE_CSA 0x80 /* enable Code Storage Area */
|
||||
|
||||
#define SDIO_REG_FBR_STD_IF_EXT 0x01
|
||||
|
||||
#define SDIO_REG_FBR_POWER 0x02
|
||||
|
||||
#define SDIO_FBR_POWER_SPS 0x01 /* Supports Power Selection */
|
||||
#define SDIO_FBR_POWER_EPS 0x02 /* Enable (low) Power Selection */
|
||||
|
||||
#define SDIO_REG_FBR_CIS 0x09 /* CIS pointer (3 bytes) */
|
||||
|
||||
|
||||
#define SDIO_REG_FBR_CSA 0x0C /* CSA pointer (3 bytes) */
|
||||
|
||||
#define SDIO_REG_FBR_CSA_DATA 0x0F
|
||||
|
||||
#define SDIO_REG_FBR_BLKSIZE 0x10 /* block size (2 bytes) */
|
||||
|
||||
/* SDIO CIS Tuple code */
|
||||
#define CISTPL_NULL 0x00
|
||||
#define CISTPL_CHECKSUM 0x10
|
||||
#define CISTPL_VERS_1 0x15
|
||||
#define CISTPL_ALTSTR 0x16
|
||||
#define CISTPL_MANFID 0x20
|
||||
#define CISTPL_FUNCID 0x21
|
||||
#define CISTPL_FUNCE 0x22
|
||||
#define CISTPL_SDIO_STD 0x91
|
||||
#define CISTPL_SDIO_EXT 0x92
|
||||
#define CISTPL_END 0xff
|
||||
|
||||
/* SDIO device id */
|
||||
#define SDIO_ANY_FUNC_ID 0xff
|
||||
#define SDIO_ANY_MAN_ID 0xffff
|
||||
#define SDIO_ANY_PROD_ID 0xffff
|
||||
|
||||
struct rt_sdio_device_id
|
||||
{
|
||||
rt_uint8_t func_code;
|
||||
rt_uint16_t manufacturer;
|
||||
rt_uint16_t product;
|
||||
};
|
||||
|
||||
struct rt_sdio_driver
|
||||
{
|
||||
char *name;
|
||||
rt_int32_t (*probe)(struct rt_mmcsd_card *card);
|
||||
rt_int32_t (*remove)(struct rt_mmcsd_card *card);
|
||||
struct rt_sdio_device_id *id;
|
||||
};
|
||||
|
||||
rt_int32_t sdio_io_send_op_cond(struct rt_mmcsd_host *host,
|
||||
rt_uint32_t ocr,
|
||||
rt_uint32_t *cmd5_resp);
|
||||
rt_int32_t sdio_io_rw_direct(struct rt_mmcsd_card *card,
|
||||
rt_int32_t rw,
|
||||
rt_uint32_t fn,
|
||||
rt_uint32_t reg_addr,
|
||||
rt_uint8_t *pdata,
|
||||
rt_uint8_t raw);
|
||||
rt_int32_t sdio_io_rw_extended(struct rt_mmcsd_card *card,
|
||||
rt_int32_t rw,
|
||||
rt_uint32_t fn,
|
||||
rt_uint32_t addr,
|
||||
rt_int32_t op_code,
|
||||
rt_uint8_t *buf,
|
||||
rt_uint32_t blocks,
|
||||
rt_uint32_t blksize);
|
||||
rt_int32_t sdio_io_rw_extended_block(struct rt_sdio_function *func,
|
||||
rt_int32_t rw,
|
||||
rt_uint32_t addr,
|
||||
rt_int32_t op_code,
|
||||
rt_uint8_t *buf,
|
||||
rt_uint32_t len);
|
||||
rt_uint8_t sdio_io_readb(struct rt_sdio_function *func,
|
||||
rt_uint32_t reg,
|
||||
rt_int32_t *err);
|
||||
rt_int32_t sdio_io_writeb(struct rt_sdio_function *func,
|
||||
rt_uint32_t reg,
|
||||
rt_uint8_t data);
|
||||
rt_uint16_t sdio_io_readw(struct rt_sdio_function *func,
|
||||
rt_uint32_t addr,
|
||||
rt_int32_t *err);
|
||||
rt_int32_t sdio_io_writew(struct rt_sdio_function *func,
|
||||
rt_uint16_t data,
|
||||
rt_uint32_t addr);
|
||||
rt_uint32_t sdio_io_readl(struct rt_sdio_function *func,
|
||||
rt_uint32_t addr,
|
||||
rt_int32_t *err);
|
||||
rt_int32_t sdio_io_writel(struct rt_sdio_function *func,
|
||||
rt_uint32_t data,
|
||||
rt_uint32_t addr);
|
||||
rt_int32_t sdio_io_read_multi_fifo_b(struct rt_sdio_function *func,
|
||||
rt_uint32_t addr,
|
||||
rt_uint8_t *buf,
|
||||
rt_uint32_t len);
|
||||
rt_int32_t sdio_io_write_multi_fifo_b(struct rt_sdio_function *func,
|
||||
rt_uint32_t addr,
|
||||
rt_uint8_t *buf,
|
||||
rt_uint32_t len);
|
||||
rt_int32_t sdio_io_read_multi_incr_b(struct rt_sdio_function *func,
|
||||
rt_uint32_t addr,
|
||||
rt_uint8_t *buf,
|
||||
rt_uint32_t len);
|
||||
rt_int32_t sdio_io_write_multi_incr_b(struct rt_sdio_function *func,
|
||||
rt_uint32_t addr,
|
||||
rt_uint8_t *buf,
|
||||
rt_uint32_t len);
|
||||
rt_int32_t init_sdio(struct rt_mmcsd_host *host, rt_uint32_t ocr);
|
||||
rt_int32_t sdio_attach_irq(struct rt_sdio_function *func,
|
||||
rt_sdio_irq_handler_t *handler);
|
||||
rt_int32_t sdio_detach_irq(struct rt_sdio_function *func);
|
||||
void sdio_irq_wakeup(struct rt_mmcsd_host *host);
|
||||
rt_int32_t sdio_enable_func(struct rt_sdio_function *func);
|
||||
rt_int32_t sdio_disable_func(struct rt_sdio_function *func);
|
||||
void sdio_set_drvdata(struct rt_sdio_function *func, void *data);
|
||||
void* sdio_get_drvdata(struct rt_sdio_function *func);
|
||||
rt_int32_t sdio_set_block_size(struct rt_sdio_function *func,
|
||||
rt_uint32_t blksize);
|
||||
rt_int32_t sdio_register_driver(struct rt_sdio_driver *driver);
|
||||
rt_int32_t sdio_unregister_driver(struct rt_sdio_driver *driver);
|
||||
void rt_sdio_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,198 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2012-05-15 lgnq first version.
|
||||
* 2012-05-28 bernard change interfaces
|
||||
* 2013-02-20 bernard use RT_SERIAL_RB_BUFSZ to define
|
||||
* the size of ring buffer.
|
||||
*/
|
||||
|
||||
#ifndef __SERIAL_H__
|
||||
#define __SERIAL_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#define BAUD_RATE_2400 2400
|
||||
#define BAUD_RATE_4800 4800
|
||||
#define BAUD_RATE_9600 9600
|
||||
#define BAUD_RATE_19200 19200
|
||||
#define BAUD_RATE_38400 38400
|
||||
#define BAUD_RATE_57600 57600
|
||||
#define BAUD_RATE_115200 115200
|
||||
#define BAUD_RATE_230400 230400
|
||||
#define BAUD_RATE_460800 460800
|
||||
#define BAUD_RATE_500000 500000
|
||||
#define BAUD_RATE_576000 576000
|
||||
#define BAUD_RATE_921600 921600
|
||||
#define BAUD_RATE_1000000 1000000
|
||||
#define BAUD_RATE_1152000 1152000
|
||||
#define BAUD_RATE_1500000 1500000
|
||||
#define BAUD_RATE_2000000 2000000
|
||||
#define BAUD_RATE_2500000 2500000
|
||||
#define BAUD_RATE_3000000 3000000
|
||||
#define BAUD_RATE_3500000 3500000
|
||||
#define BAUD_RATE_4000000 4000000
|
||||
|
||||
#define DATA_BITS_5 5
|
||||
#define DATA_BITS_6 6
|
||||
#define DATA_BITS_7 7
|
||||
#define DATA_BITS_8 8
|
||||
#define DATA_BITS_9 9
|
||||
|
||||
#define STOP_BITS_1 0
|
||||
#define STOP_BITS_2 1
|
||||
#define STOP_BITS_3 2
|
||||
#define STOP_BITS_4 3
|
||||
|
||||
#ifdef _WIN32
|
||||
#include <windows.h>
|
||||
#else
|
||||
#define PARITY_NONE 0
|
||||
#define PARITY_ODD 1
|
||||
#define PARITY_EVEN 2
|
||||
#endif
|
||||
|
||||
#define BIT_ORDER_LSB 0
|
||||
#define BIT_ORDER_MSB 1
|
||||
|
||||
#define NRZ_NORMAL 0 /* Non Return to Zero : normal mode */
|
||||
#define NRZ_INVERTED 1 /* Non Return to Zero : inverted mode */
|
||||
|
||||
#ifndef RT_SERIAL_RB_BUFSZ
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#endif
|
||||
|
||||
#define RT_SERIAL_EVENT_RX_IND 0x01 /* Rx indication */
|
||||
#define RT_SERIAL_EVENT_TX_DONE 0x02 /* Tx complete */
|
||||
#define RT_SERIAL_EVENT_RX_DMADONE 0x03 /* Rx DMA transfer done */
|
||||
#define RT_SERIAL_EVENT_TX_DMADONE 0x04 /* Tx DMA transfer done */
|
||||
#define RT_SERIAL_EVENT_RX_TIMEOUT 0x05 /* Rx timeout */
|
||||
|
||||
#define RT_SERIAL_DMA_RX 0x01
|
||||
#define RT_SERIAL_DMA_TX 0x02
|
||||
|
||||
#define RT_SERIAL_RX_INT 0x01
|
||||
#define RT_SERIAL_TX_INT 0x02
|
||||
|
||||
#define RT_SERIAL_ERR_OVERRUN 0x01
|
||||
#define RT_SERIAL_ERR_FRAMING 0x02
|
||||
#define RT_SERIAL_ERR_PARITY 0x03
|
||||
|
||||
#define RT_SERIAL_TX_DATAQUEUE_SIZE 2048
|
||||
#define RT_SERIAL_TX_DATAQUEUE_LWM 30
|
||||
|
||||
#define RT_SERIAL_FLOWCONTROL_CTSRTS 1
|
||||
#define RT_SERIAL_FLOWCONTROL_NONE 0
|
||||
|
||||
/* Default config for serial_configure structure */
|
||||
#define RT_SERIAL_CONFIG_DEFAULT \
|
||||
{ \
|
||||
BAUD_RATE_115200, /* 115200 bits/s */ \
|
||||
DATA_BITS_8, /* 8 databits */ \
|
||||
STOP_BITS_1, /* 1 stopbit */ \
|
||||
PARITY_NONE, /* No parity */ \
|
||||
BIT_ORDER_LSB, /* LSB first sent */ \
|
||||
NRZ_NORMAL, /* Normal mode */ \
|
||||
RT_SERIAL_RB_BUFSZ, /* Buffer size */ \
|
||||
RT_SERIAL_FLOWCONTROL_NONE, /* Off flowcontrol */ \
|
||||
0 \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets a hook function when RX indicate is called
|
||||
*
|
||||
* @param thread is the target thread that initializing
|
||||
*/
|
||||
typedef void (*rt_hw_serial_rxind_hookproto_t)(rt_device_t dev, rt_size_t size);
|
||||
RT_OBJECT_HOOKLIST_DECLARE(rt_hw_serial_rxind_hookproto_t, rt_hw_serial_rxind);
|
||||
|
||||
struct serial_configure
|
||||
{
|
||||
rt_uint32_t baud_rate;
|
||||
|
||||
rt_uint32_t data_bits :4;
|
||||
rt_uint32_t stop_bits :2;
|
||||
rt_uint32_t parity :2;
|
||||
rt_uint32_t bit_order :1;
|
||||
rt_uint32_t invert :1;
|
||||
rt_uint32_t bufsz :16;
|
||||
rt_uint32_t flowcontrol :1;
|
||||
rt_uint32_t reserved :5;
|
||||
};
|
||||
|
||||
/*
|
||||
* Serial FIFO mode
|
||||
*/
|
||||
struct rt_serial_rx_fifo
|
||||
{
|
||||
/* software fifo */
|
||||
rt_uint8_t *buffer;
|
||||
|
||||
rt_uint16_t put_index, get_index;
|
||||
|
||||
rt_bool_t is_full;
|
||||
};
|
||||
|
||||
struct rt_serial_tx_fifo
|
||||
{
|
||||
struct rt_completion completion;
|
||||
};
|
||||
|
||||
/*
|
||||
* Serial DMA mode
|
||||
*/
|
||||
struct rt_serial_rx_dma
|
||||
{
|
||||
rt_bool_t activated;
|
||||
};
|
||||
|
||||
struct rt_serial_tx_dma
|
||||
{
|
||||
rt_bool_t activated;
|
||||
struct rt_data_queue data_queue;
|
||||
};
|
||||
|
||||
struct rt_serial_device
|
||||
{
|
||||
struct rt_device parent;
|
||||
|
||||
const struct rt_uart_ops *ops;
|
||||
struct serial_configure config;
|
||||
|
||||
void *serial_rx;
|
||||
void *serial_tx;
|
||||
|
||||
struct rt_spinlock spinlock;
|
||||
|
||||
struct rt_device_notify rx_notify;
|
||||
};
|
||||
typedef struct rt_serial_device rt_serial_t;
|
||||
|
||||
/**
|
||||
* uart operators
|
||||
*/
|
||||
struct rt_uart_ops
|
||||
{
|
||||
rt_err_t (*configure)(struct rt_serial_device *serial, struct serial_configure *cfg);
|
||||
rt_err_t (*control)(struct rt_serial_device *serial, int cmd, void *arg);
|
||||
|
||||
int (*putc)(struct rt_serial_device *serial, char c);
|
||||
int (*getc)(struct rt_serial_device *serial);
|
||||
|
||||
rt_ssize_t (*dma_transmit)(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction);
|
||||
};
|
||||
|
||||
void rt_hw_serial_isr(struct rt_serial_device *serial, int event);
|
||||
|
||||
rt_err_t rt_hw_serial_register(struct rt_serial_device *serial,
|
||||
const char *name,
|
||||
rt_uint32_t flag,
|
||||
void *data);
|
||||
|
||||
rt_err_t rt_hw_serial_register_tty(struct rt_serial_device *serial);
|
||||
|
||||
#endif
|
||||
@@ -1,203 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-06-01 KyleChan first version
|
||||
*/
|
||||
|
||||
#ifndef __SERIAL_V2_H__
|
||||
#define __SERIAL_V2_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#define BAUD_RATE_2400 2400
|
||||
#define BAUD_RATE_4800 4800
|
||||
#define BAUD_RATE_9600 9600
|
||||
#define BAUD_RATE_19200 19200
|
||||
#define BAUD_RATE_38400 38400
|
||||
#define BAUD_RATE_57600 57600
|
||||
#define BAUD_RATE_115200 115200
|
||||
#define BAUD_RATE_230400 230400
|
||||
#define BAUD_RATE_460800 460800
|
||||
#define BAUD_RATE_500000 500000
|
||||
#define BAUD_RATE_921600 921600
|
||||
#define BAUD_RATE_2000000 2000000
|
||||
#define BAUD_RATE_2500000 2500000
|
||||
#define BAUD_RATE_3000000 3000000
|
||||
|
||||
#define DATA_BITS_5 5
|
||||
#define DATA_BITS_6 6
|
||||
#define DATA_BITS_7 7
|
||||
#define DATA_BITS_8 8
|
||||
#define DATA_BITS_9 9
|
||||
|
||||
#define STOP_BITS_1 0
|
||||
#define STOP_BITS_2 1
|
||||
#define STOP_BITS_3 2
|
||||
#define STOP_BITS_4 3
|
||||
|
||||
#ifdef _WIN32
|
||||
#include <windows.h>
|
||||
#else
|
||||
#define PARITY_NONE 0
|
||||
#define PARITY_ODD 1
|
||||
#define PARITY_EVEN 2
|
||||
#endif
|
||||
|
||||
#define BIT_ORDER_LSB 0
|
||||
#define BIT_ORDER_MSB 1
|
||||
|
||||
#define NRZ_NORMAL 0 /* Non Return to Zero : normal mode */
|
||||
#define NRZ_INVERTED 1 /* Non Return to Zero : inverted mode */
|
||||
|
||||
#define RT_DEVICE_FLAG_RX_BLOCKING 0x1000
|
||||
#define RT_DEVICE_FLAG_RX_NON_BLOCKING 0x2000
|
||||
|
||||
#define RT_DEVICE_FLAG_TX_BLOCKING 0x4000
|
||||
#define RT_DEVICE_FLAG_TX_NON_BLOCKING 0x8000
|
||||
|
||||
#define RT_SERIAL_RX_BLOCKING RT_DEVICE_FLAG_RX_BLOCKING
|
||||
#define RT_SERIAL_RX_NON_BLOCKING RT_DEVICE_FLAG_RX_NON_BLOCKING
|
||||
#define RT_SERIAL_TX_BLOCKING RT_DEVICE_FLAG_TX_BLOCKING
|
||||
#define RT_SERIAL_TX_NON_BLOCKING RT_DEVICE_FLAG_TX_NON_BLOCKING
|
||||
|
||||
#define RT_DEVICE_CHECK_OPTMODE 0x20
|
||||
|
||||
#define RT_SERIAL_EVENT_RX_IND 0x01 /* Rx indication */
|
||||
#define RT_SERIAL_EVENT_TX_DONE 0x02 /* Tx complete */
|
||||
#define RT_SERIAL_EVENT_RX_DMADONE 0x03 /* Rx DMA transfer done */
|
||||
#define RT_SERIAL_EVENT_TX_DMADONE 0x04 /* Tx DMA transfer done */
|
||||
#define RT_SERIAL_EVENT_RX_TIMEOUT 0x05 /* Rx timeout */
|
||||
|
||||
#define RT_SERIAL_ERR_OVERRUN 0x01
|
||||
#define RT_SERIAL_ERR_FRAMING 0x02
|
||||
#define RT_SERIAL_ERR_PARITY 0x03
|
||||
|
||||
#define RT_SERIAL_TX_DATAQUEUE_SIZE 2048
|
||||
#define RT_SERIAL_TX_DATAQUEUE_LWM 30
|
||||
|
||||
#define RT_SERIAL_RX_MINBUFSZ 64
|
||||
#define RT_SERIAL_TX_MINBUFSZ 64
|
||||
|
||||
#define RT_SERIAL_TX_BLOCKING_BUFFER 1
|
||||
#define RT_SERIAL_TX_BLOCKING_NO_BUFFER 0
|
||||
|
||||
#define RT_SERIAL_FLOWCONTROL_CTSRTS 1
|
||||
#define RT_SERIAL_FLOWCONTROL_NONE 0
|
||||
|
||||
/* Default config for serial_configure structure */
|
||||
#define RT_SERIAL_CONFIG_DEFAULT \
|
||||
{ \
|
||||
BAUD_RATE_115200, /* 115200 bits/s */ \
|
||||
DATA_BITS_8, /* 8 databits */ \
|
||||
STOP_BITS_1, /* 1 stopbit */ \
|
||||
PARITY_NONE, /* No parity */ \
|
||||
BIT_ORDER_LSB, /* LSB first sent */ \
|
||||
NRZ_NORMAL, /* Normal mode */ \
|
||||
RT_SERIAL_RX_MINBUFSZ, /* rxBuf size */ \
|
||||
RT_SERIAL_TX_MINBUFSZ, /* txBuf size */ \
|
||||
RT_SERIAL_FLOWCONTROL_NONE, /* Off flowcontrol */ \
|
||||
0 \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets a hook function when RX indicate is called
|
||||
*
|
||||
* @param thread is the target thread that initializing
|
||||
*/
|
||||
typedef void (*rt_hw_serial_rxind_hookproto_t)(rt_device_t dev, rt_size_t size);
|
||||
RT_OBJECT_HOOKLIST_DECLARE(rt_hw_serial_rxind_hookproto_t, rt_hw_serial_rxind);
|
||||
|
||||
struct serial_configure
|
||||
{
|
||||
rt_uint32_t baud_rate;
|
||||
|
||||
rt_uint32_t data_bits :4;
|
||||
rt_uint32_t stop_bits :2;
|
||||
rt_uint32_t parity :2;
|
||||
rt_uint32_t bit_order :1;
|
||||
rt_uint32_t invert :1;
|
||||
rt_uint32_t rx_bufsz :16;
|
||||
rt_uint32_t tx_bufsz :16;
|
||||
rt_uint32_t flowcontrol :1;
|
||||
rt_uint32_t reserved :5;
|
||||
};
|
||||
|
||||
/*
|
||||
* Serial Receive FIFO mode
|
||||
*/
|
||||
struct rt_serial_rx_fifo
|
||||
{
|
||||
struct rt_ringbuffer rb;
|
||||
|
||||
struct rt_completion rx_cpt;
|
||||
|
||||
rt_uint16_t rx_cpt_index;
|
||||
|
||||
/* software fifo */
|
||||
rt_uint8_t buffer[];
|
||||
};
|
||||
|
||||
/*
|
||||
* Serial Transmit FIFO mode
|
||||
*/
|
||||
struct rt_serial_tx_fifo
|
||||
{
|
||||
struct rt_ringbuffer rb;
|
||||
|
||||
rt_size_t put_size;
|
||||
|
||||
rt_bool_t activated;
|
||||
|
||||
struct rt_completion tx_cpt;
|
||||
|
||||
/* software fifo */
|
||||
rt_uint8_t buffer[];
|
||||
};
|
||||
|
||||
struct rt_serial_device
|
||||
{
|
||||
struct rt_device parent;
|
||||
|
||||
const struct rt_uart_ops *ops;
|
||||
struct serial_configure config;
|
||||
|
||||
void *serial_rx;
|
||||
void *serial_tx;
|
||||
|
||||
struct rt_device_notify rx_notify;
|
||||
};
|
||||
|
||||
/**
|
||||
* uart operators
|
||||
*/
|
||||
struct rt_uart_ops
|
||||
{
|
||||
rt_err_t (*configure)(struct rt_serial_device *serial,
|
||||
struct serial_configure *cfg);
|
||||
|
||||
rt_err_t (*control)(struct rt_serial_device *serial,
|
||||
int cmd,
|
||||
void *arg);
|
||||
|
||||
int (*putc)(struct rt_serial_device *serial, char c);
|
||||
int (*getc)(struct rt_serial_device *serial);
|
||||
|
||||
rt_ssize_t (*transmit)(struct rt_serial_device *serial,
|
||||
rt_uint8_t *buf,
|
||||
rt_size_t size,
|
||||
rt_uint32_t tx_flag);
|
||||
};
|
||||
|
||||
void rt_hw_serial_isr(struct rt_serial_device *serial, int event);
|
||||
|
||||
rt_err_t rt_hw_serial_register(struct rt_serial_device *serial,
|
||||
const char *name,
|
||||
rt_uint32_t flag,
|
||||
void *data);
|
||||
|
||||
rt_err_t rt_hw_serial_register_tty(struct rt_serial_device *serial);
|
||||
#endif
|
||||
@@ -1,373 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2012-11-23 Bernard Add extern "C"
|
||||
* 2020-06-13 armink fix the 3 wires issue
|
||||
* 2022-09-01 liYony fix api rt_spi_sendrecv16 about MSB and LSB bug
|
||||
*/
|
||||
|
||||
#ifndef __SPI_H__
|
||||
#define __SPI_H__
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <rtthread.h>
|
||||
#include <drivers/pin.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* At CPOL=0 the base value of the clock is zero
|
||||
* - For CPHA=0, data are captured on the clock's rising edge (low->high transition)
|
||||
* and data are propagated on a falling edge (high->low clock transition).
|
||||
* - For CPHA=1, data are captured on the clock's falling edge and data are
|
||||
* propagated on a rising edge.
|
||||
* At CPOL=1 the base value of the clock is one (inversion of CPOL=0)
|
||||
* - For CPHA=0, data are captured on clock's falling edge and data are propagated
|
||||
* on a rising edge.
|
||||
* - For CPHA=1, data are captured on clock's rising edge and data are propagated
|
||||
* on a falling edge.
|
||||
*/
|
||||
#define RT_SPI_CPHA (1<<0) /* bit[0]:CPHA, clock phase */
|
||||
#define RT_SPI_CPOL (1<<1) /* bit[1]:CPOL, clock polarity */
|
||||
|
||||
#define RT_SPI_LSB (0<<2) /* bit[2]: 0-LSB */
|
||||
#define RT_SPI_MSB (1<<2) /* bit[2]: 1-MSB */
|
||||
|
||||
#define RT_SPI_MASTER (0<<3) /* SPI master device */
|
||||
#define RT_SPI_SLAVE (1<<3) /* SPI slave device */
|
||||
|
||||
#define RT_SPI_CS_HIGH (1<<4) /* Chipselect active high */
|
||||
#define RT_SPI_NO_CS (1<<5) /* No chipselect */
|
||||
#define RT_SPI_3WIRE (1<<6) /* SI/SO pin shared */
|
||||
#define RT_SPI_READY (1<<7) /* Slave pulls low to pause */
|
||||
|
||||
#define RT_SPI_MODE_MASK (RT_SPI_CPHA | RT_SPI_CPOL | RT_SPI_MSB | RT_SPI_SLAVE | RT_SPI_CS_HIGH | RT_SPI_NO_CS | RT_SPI_3WIRE | RT_SPI_READY)
|
||||
|
||||
#define RT_SPI_MODE_0 (0 | 0) /* CPOL = 0, CPHA = 0 */
|
||||
#define RT_SPI_MODE_1 (0 | RT_SPI_CPHA) /* CPOL = 0, CPHA = 1 */
|
||||
#define RT_SPI_MODE_2 (RT_SPI_CPOL | 0) /* CPOL = 1, CPHA = 0 */
|
||||
#define RT_SPI_MODE_3 (RT_SPI_CPOL | RT_SPI_CPHA) /* CPOL = 1, CPHA = 1 */
|
||||
|
||||
#define RT_SPI_BUS_MODE_SPI (1<<0)
|
||||
#define RT_SPI_BUS_MODE_QSPI (1<<1)
|
||||
|
||||
/**
|
||||
* SPI message structure
|
||||
*/
|
||||
struct rt_spi_message
|
||||
{
|
||||
const void *send_buf;
|
||||
void *recv_buf;
|
||||
rt_size_t length;
|
||||
struct rt_spi_message *next;
|
||||
|
||||
unsigned cs_take : 1;
|
||||
unsigned cs_release : 1;
|
||||
};
|
||||
|
||||
/**
|
||||
* SPI configuration structure
|
||||
*/
|
||||
struct rt_spi_configuration
|
||||
{
|
||||
rt_uint8_t mode;
|
||||
rt_uint8_t data_width;
|
||||
rt_uint16_t reserved;
|
||||
|
||||
rt_uint32_t max_hz;
|
||||
};
|
||||
|
||||
struct rt_spi_ops;
|
||||
struct rt_spi_bus
|
||||
{
|
||||
struct rt_device parent;
|
||||
rt_uint8_t mode;
|
||||
const struct rt_spi_ops *ops;
|
||||
|
||||
struct rt_mutex lock;
|
||||
struct rt_spi_device *owner;
|
||||
};
|
||||
|
||||
/**
|
||||
* SPI operators
|
||||
*/
|
||||
struct rt_spi_ops
|
||||
{
|
||||
rt_err_t (*configure)(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
|
||||
rt_ssize_t (*xfer)(struct rt_spi_device *device, struct rt_spi_message *message);
|
||||
};
|
||||
|
||||
/**
|
||||
* SPI Virtual BUS, one device must connected to a virtual BUS
|
||||
*/
|
||||
struct rt_spi_device
|
||||
{
|
||||
struct rt_device parent;
|
||||
struct rt_spi_bus *bus;
|
||||
|
||||
struct rt_spi_configuration config;
|
||||
rt_base_t cs_pin;
|
||||
void *user_data;
|
||||
};
|
||||
|
||||
struct rt_qspi_message
|
||||
{
|
||||
struct rt_spi_message parent;
|
||||
|
||||
/* instruction stage */
|
||||
struct
|
||||
{
|
||||
rt_uint8_t content;
|
||||
rt_uint8_t qspi_lines;
|
||||
} instruction;
|
||||
|
||||
/* address and alternate_bytes stage */
|
||||
struct
|
||||
{
|
||||
rt_uint32_t content;
|
||||
rt_uint8_t size;
|
||||
rt_uint8_t qspi_lines;
|
||||
} address, alternate_bytes;
|
||||
|
||||
/* dummy_cycles stage */
|
||||
rt_uint32_t dummy_cycles;
|
||||
|
||||
/* number of lines in qspi data stage, the other configuration items are in parent */
|
||||
rt_uint8_t qspi_data_lines;
|
||||
};
|
||||
|
||||
struct rt_qspi_configuration
|
||||
{
|
||||
struct rt_spi_configuration parent;
|
||||
/* The size of medium */
|
||||
rt_uint32_t medium_size;
|
||||
/* double data rate mode */
|
||||
rt_uint8_t ddr_mode;
|
||||
/* the data lines max width which QSPI bus supported, such as 1, 2, 4 */
|
||||
rt_uint8_t qspi_dl_width ;
|
||||
};
|
||||
|
||||
struct rt_qspi_device
|
||||
{
|
||||
struct rt_spi_device parent;
|
||||
|
||||
struct rt_qspi_configuration config;
|
||||
|
||||
void (*enter_qspi_mode)(struct rt_qspi_device *device);
|
||||
|
||||
void (*exit_qspi_mode)(struct rt_qspi_device *device);
|
||||
};
|
||||
|
||||
#define SPI_DEVICE(dev) ((struct rt_spi_device *)(dev))
|
||||
|
||||
/* register a SPI bus */
|
||||
rt_err_t rt_spi_bus_register(struct rt_spi_bus *bus,
|
||||
const char *name,
|
||||
const struct rt_spi_ops *ops);
|
||||
|
||||
/* attach a device on SPI bus */
|
||||
rt_err_t rt_spi_bus_attach_device(struct rt_spi_device *device,
|
||||
const char *name,
|
||||
const char *bus_name,
|
||||
void *user_data);
|
||||
|
||||
/* attach a device on SPI bus with CS pin */
|
||||
rt_err_t rt_spi_bus_attach_device_cspin(struct rt_spi_device *device,
|
||||
const char *name,
|
||||
const char *bus_name,
|
||||
rt_base_t cs_pin,
|
||||
void *user_data);
|
||||
|
||||
/* re-configure SPI bus */
|
||||
rt_err_t rt_spi_bus_configure(struct rt_spi_device *device);
|
||||
|
||||
/**
|
||||
* This function takes SPI bus.
|
||||
*
|
||||
* @param device the SPI device attached to SPI bus
|
||||
*
|
||||
* @return RT_EOK on taken SPI bus successfully. others on taken SPI bus failed.
|
||||
*/
|
||||
rt_err_t rt_spi_take_bus(struct rt_spi_device *device);
|
||||
|
||||
/**
|
||||
* This function releases SPI bus.
|
||||
*
|
||||
* @param device the SPI device attached to SPI bus
|
||||
*
|
||||
* @return RT_EOK on release SPI bus successfully.
|
||||
*/
|
||||
rt_err_t rt_spi_release_bus(struct rt_spi_device *device);
|
||||
|
||||
/**
|
||||
* This function take SPI device (takes CS of SPI device).
|
||||
*
|
||||
* @param device the SPI device attached to SPI bus
|
||||
*
|
||||
* @return RT_EOK on release SPI bus successfully. others on taken SPI bus failed.
|
||||
*/
|
||||
rt_err_t rt_spi_take(struct rt_spi_device *device);
|
||||
|
||||
/**
|
||||
* This function releases SPI device (releases CS of SPI device).
|
||||
*
|
||||
* @param device the SPI device attached to SPI bus
|
||||
*
|
||||
* @return RT_EOK on release SPI device successfully.
|
||||
*/
|
||||
rt_err_t rt_spi_release(struct rt_spi_device *device);
|
||||
|
||||
/* set configuration on SPI device */
|
||||
rt_err_t rt_spi_configure(struct rt_spi_device *device,
|
||||
struct rt_spi_configuration *cfg);
|
||||
|
||||
/* send data then receive data from SPI device */
|
||||
rt_err_t rt_spi_send_then_recv(struct rt_spi_device *device,
|
||||
const void *send_buf,
|
||||
rt_size_t send_length,
|
||||
void *recv_buf,
|
||||
rt_size_t recv_length);
|
||||
|
||||
rt_err_t rt_spi_send_then_send(struct rt_spi_device *device,
|
||||
const void *send_buf1,
|
||||
rt_size_t send_length1,
|
||||
const void *send_buf2,
|
||||
rt_size_t send_length2);
|
||||
|
||||
/**
|
||||
* This function transmits data to SPI device.
|
||||
*
|
||||
* @param device the SPI device attached to SPI bus
|
||||
* @param send_buf the buffer to be transmitted to SPI device.
|
||||
* @param recv_buf the buffer to save received data from SPI device.
|
||||
* @param length the length of transmitted data.
|
||||
*
|
||||
* @return the actual length of transmitted.
|
||||
*/
|
||||
rt_ssize_t rt_spi_transfer(struct rt_spi_device *device,
|
||||
const void *send_buf,
|
||||
void *recv_buf,
|
||||
rt_size_t length);
|
||||
|
||||
rt_err_t rt_spi_sendrecv8(struct rt_spi_device *device,
|
||||
rt_uint8_t senddata,
|
||||
rt_uint8_t *recvdata);
|
||||
|
||||
rt_err_t rt_spi_sendrecv16(struct rt_spi_device *device,
|
||||
rt_uint16_t senddata,
|
||||
rt_uint16_t *recvdata);
|
||||
|
||||
/**
|
||||
* This function transfers a message list to the SPI device.
|
||||
*
|
||||
* @param device the SPI device attached to SPI bus
|
||||
* @param message the message list to be transmitted to SPI device
|
||||
*
|
||||
* @return RT_NULL if transmits message list successfully,
|
||||
* SPI message which be transmitted failed.
|
||||
*/
|
||||
struct rt_spi_message *rt_spi_transfer_message(struct rt_spi_device *device,
|
||||
struct rt_spi_message *message);
|
||||
|
||||
rt_inline rt_size_t rt_spi_recv(struct rt_spi_device *device,
|
||||
void *recv_buf,
|
||||
rt_size_t length)
|
||||
{
|
||||
return rt_spi_transfer(device, RT_NULL, recv_buf, length);
|
||||
}
|
||||
|
||||
rt_inline rt_size_t rt_spi_send(struct rt_spi_device *device,
|
||||
const void *send_buf,
|
||||
rt_size_t length)
|
||||
{
|
||||
return rt_spi_transfer(device, send_buf, RT_NULL, length);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function appends a message to the SPI message list.
|
||||
*
|
||||
* @param list the SPI message list header.
|
||||
* @param message the message pointer to be appended to the message list.
|
||||
*/
|
||||
rt_inline void rt_spi_message_append(struct rt_spi_message *list,
|
||||
struct rt_spi_message *message)
|
||||
{
|
||||
RT_ASSERT(list != RT_NULL);
|
||||
if (message == RT_NULL)
|
||||
return; /* not append */
|
||||
|
||||
while (list->next != RT_NULL)
|
||||
{
|
||||
list = list->next;
|
||||
}
|
||||
|
||||
list->next = message;
|
||||
message->next = RT_NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function can set configuration on QSPI device.
|
||||
*
|
||||
* @param device the QSPI device attached to QSPI bus.
|
||||
* @param cfg the configuration pointer.
|
||||
*
|
||||
* @return the actual length of transmitted.
|
||||
*/
|
||||
rt_err_t rt_qspi_configure(struct rt_qspi_device *device, struct rt_qspi_configuration *cfg);
|
||||
|
||||
/**
|
||||
* This function can register a SPI bus for QSPI mode.
|
||||
*
|
||||
* @param bus the SPI bus for QSPI mode.
|
||||
* @param name The name of the spi bus.
|
||||
* @param ops the SPI bus instance to be registered.
|
||||
*
|
||||
* @return the actual length of transmitted.
|
||||
*/
|
||||
rt_err_t rt_qspi_bus_register(struct rt_spi_bus *bus, const char *name, const struct rt_spi_ops *ops);
|
||||
|
||||
/**
|
||||
* This function transmits data to QSPI device.
|
||||
*
|
||||
* @param device the QSPI device attached to QSPI bus.
|
||||
* @param message the message pointer.
|
||||
*
|
||||
* @return the actual length of transmitted.
|
||||
*/
|
||||
rt_size_t rt_qspi_transfer_message(struct rt_qspi_device *device, struct rt_qspi_message *message);
|
||||
|
||||
/**
|
||||
* This function can send data then receive data from QSPI device
|
||||
*
|
||||
* @param device the QSPI device attached to QSPI bus.
|
||||
* @param send_buf the buffer to be transmitted to QSPI device.
|
||||
* @param send_length the number of data to be transmitted.
|
||||
* @param recv_buf the buffer to be recivied from QSPI device.
|
||||
* @param recv_length the data to be recivied.
|
||||
*
|
||||
* @return the status of transmit.
|
||||
*/
|
||||
rt_err_t rt_qspi_send_then_recv(struct rt_qspi_device *device, const void *send_buf, rt_size_t send_length,void *recv_buf, rt_size_t recv_length);
|
||||
|
||||
/**
|
||||
* This function can send data to QSPI device
|
||||
*
|
||||
* @param device the QSPI device attached to QSPI bus.
|
||||
* @param send_buf the buffer to be transmitted to QSPI device.
|
||||
* @param send_length the number of data to be transmitted.
|
||||
*
|
||||
* @return the status of transmit.
|
||||
*/
|
||||
rt_err_t rt_qspi_send(struct rt_qspi_device *device, const void *send_buf, rt_size_t length);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,113 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-05-20 tyustli the first version
|
||||
*/
|
||||
|
||||
#ifndef __TOUCH_H__
|
||||
#define __TOUCH_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "pin.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_RTC
|
||||
#define rt_touch_get_ts() time(RT_NULL) /* API for the touch to get the timestamp */
|
||||
#else
|
||||
#define rt_touch_get_ts() rt_tick_get() /* API for the touch to get the timestamp */
|
||||
#endif
|
||||
|
||||
/* Touch vendor types */
|
||||
#define RT_TOUCH_VENDOR_UNKNOWN (0) /* unknown */
|
||||
#define RT_TOUCH_VENDOR_GT (1) /* GTxx series */
|
||||
#define RT_TOUCH_VENDOR_FT (2) /* FTxx series */
|
||||
|
||||
/* Touch ic type*/
|
||||
#define RT_TOUCH_TYPE_NONE (0) /* touch ic none */
|
||||
#define RT_TOUCH_TYPE_CAPACITANCE (1) /* capacitance ic */
|
||||
#define RT_TOUCH_TYPE_RESISTANCE (2) /* resistance ic */
|
||||
|
||||
/* Touch control cmd types */
|
||||
#define RT_TOUCH_CTRL_GET_ID (RT_DEVICE_CTRL_BASE(Touch) + 0) /* Get device id */
|
||||
#define RT_TOUCH_CTRL_GET_INFO (RT_DEVICE_CTRL_BASE(Touch) + 1) /* Get touch info */
|
||||
#define RT_TOUCH_CTRL_SET_MODE (RT_DEVICE_CTRL_BASE(Touch) + 2) /* Set touch's work mode. ex. RT_TOUCH_MODE_POLLING,RT_TOUCH_MODE_INT */
|
||||
#define RT_TOUCH_CTRL_SET_X_RANGE (RT_DEVICE_CTRL_BASE(Touch) + 3) /* Set x coordinate range */
|
||||
#define RT_TOUCH_CTRL_SET_Y_RANGE (RT_DEVICE_CTRL_BASE(Touch) + 4) /* Set y coordinate range */
|
||||
#define RT_TOUCH_CTRL_SET_X_TO_Y (RT_DEVICE_CTRL_BASE(Touch) + 5) /* Set X Y coordinate exchange */
|
||||
#define RT_TOUCH_CTRL_DISABLE_INT (RT_DEVICE_CTRL_BASE(Touch) + 6) /* Disable interrupt */
|
||||
#define RT_TOUCH_CTRL_ENABLE_INT (RT_DEVICE_CTRL_BASE(Touch) + 7) /* Enable interrupt */
|
||||
#define RT_TOUCH_CTRL_POWER_ON (RT_DEVICE_CTRL_BASE(Touch) + 8) /* Touch Power On */
|
||||
#define RT_TOUCH_CTRL_POWER_OFF (RT_DEVICE_CTRL_BASE(Touch) + 9) /* Touch Power Off */
|
||||
#define RT_TOUCH_CTRL_GET_STATUS (RT_DEVICE_CTRL_BASE(Touch) + 10) /* Get Touch Power Status */
|
||||
|
||||
/* Touch event */
|
||||
#define RT_TOUCH_EVENT_NONE (0) /* Touch none */
|
||||
#define RT_TOUCH_EVENT_UP (1) /* Touch up event */
|
||||
#define RT_TOUCH_EVENT_DOWN (2) /* Touch down event */
|
||||
#define RT_TOUCH_EVENT_MOVE (3) /* Touch move event */
|
||||
|
||||
struct rt_touch_info
|
||||
{
|
||||
rt_uint8_t type; /* The touch type */
|
||||
rt_uint8_t vendor; /* Vendor of touchs */
|
||||
rt_uint8_t point_num; /* Support point num */
|
||||
rt_int32_t range_x; /* X coordinate range */
|
||||
rt_int32_t range_y; /* Y coordinate range */
|
||||
};
|
||||
|
||||
struct rt_touch_config
|
||||
{
|
||||
#ifdef RT_TOUCH_PIN_IRQ
|
||||
struct rt_device_pin_mode irq_pin; /* Interrupt pin, The purpose of this pin is to notification read data */
|
||||
#endif
|
||||
char *dev_name; /* The name of the communication device */
|
||||
void *user_data;
|
||||
};
|
||||
|
||||
typedef struct rt_touch_device *rt_touch_t;
|
||||
struct rt_touch_device
|
||||
{
|
||||
struct rt_device parent; /* The standard device */
|
||||
struct rt_touch_info info; /* The touch info data */
|
||||
struct rt_touch_config config; /* The touch config data */
|
||||
|
||||
const struct rt_touch_ops *ops; /* The touch ops */
|
||||
rt_err_t (*irq_handle)(rt_touch_t touch); /* Called when an interrupt is generated, registered by the driver */
|
||||
};
|
||||
|
||||
struct rt_touch_data
|
||||
{
|
||||
rt_uint8_t event; /* The touch event of the data */
|
||||
rt_uint8_t track_id; /* Track id of point */
|
||||
rt_uint8_t width; /* Point of width */
|
||||
rt_uint16_t x_coordinate; /* Point of x coordinate */
|
||||
rt_uint16_t y_coordinate; /* Point of y coordinate */
|
||||
rt_tick_t timestamp; /* The timestamp when the data was received */
|
||||
};
|
||||
|
||||
struct rt_touch_ops
|
||||
{
|
||||
rt_size_t (*touch_readpoint)(struct rt_touch_device *touch, void *buf, rt_size_t touch_num);
|
||||
rt_err_t (*touch_control)(struct rt_touch_device *touch, int cmd, void *arg);
|
||||
};
|
||||
|
||||
int rt_hw_touch_register(rt_touch_t touch,
|
||||
const char *name,
|
||||
rt_uint32_t flag,
|
||||
void *data);
|
||||
|
||||
/* if you doesn't use pin device. you must call this function in your touch irq callback */
|
||||
void rt_hw_touch_isr(rt_touch_t touch);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __TOUCH_H__ */
|
||||
@@ -1,42 +0,0 @@
|
||||
/*
|
||||
* COPYRIGHT (C) 2011-2023, Real-Thread Information Technology Ltd
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2012-09-12 heyuanjie87 first version.
|
||||
*/
|
||||
|
||||
#ifndef __WATCHDOG_H__
|
||||
#define __WATCHDOG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#define RT_DEVICE_CTRL_WDT_GET_TIMEOUT (RT_DEVICE_CTRL_BASE(WDT) + 1) /* get timeout(in seconds) */
|
||||
#define RT_DEVICE_CTRL_WDT_SET_TIMEOUT (RT_DEVICE_CTRL_BASE(WDT) + 2) /* set timeout(in seconds) */
|
||||
#define RT_DEVICE_CTRL_WDT_GET_TIMELEFT (RT_DEVICE_CTRL_BASE(WDT) + 3) /* get the left time before reboot(in seconds) */
|
||||
#define RT_DEVICE_CTRL_WDT_KEEPALIVE (RT_DEVICE_CTRL_BASE(WDT) + 4) /* refresh watchdog */
|
||||
#define RT_DEVICE_CTRL_WDT_START (RT_DEVICE_CTRL_BASE(WDT) + 5) /* start watchdog */
|
||||
#define RT_DEVICE_CTRL_WDT_STOP (RT_DEVICE_CTRL_BASE(WDT) + 6) /* stop watchdog */
|
||||
|
||||
struct rt_watchdog_ops;
|
||||
struct rt_watchdog_device
|
||||
{
|
||||
struct rt_device parent;
|
||||
const struct rt_watchdog_ops *ops;
|
||||
};
|
||||
typedef struct rt_watchdog_device rt_watchdog_t;
|
||||
|
||||
struct rt_watchdog_ops
|
||||
{
|
||||
rt_err_t (*init)(rt_watchdog_t *wdt);
|
||||
rt_err_t (*control)(rt_watchdog_t *wdt, int cmd, void *arg);
|
||||
};
|
||||
|
||||
rt_err_t rt_hw_watchdog_register(rt_watchdog_t *wdt,
|
||||
const char *name,
|
||||
rt_uint32_t flag,
|
||||
void *data);
|
||||
|
||||
#endif /* __WATCHDOG_H__ */
|
||||
Reference in New Issue
Block a user