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james
2024-08-05 20:57:09 +08:00
commit 46d9ee7795
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23
rt-thread/libcpu/arm/s3c24x0/SConscript Normal file
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# RT-Thread building script for component
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd]
if rtconfig.PLATFORM in ['armcc', 'armclang']:
src += Glob('*_rvds.S')
if rtconfig.PLATFORM in ['gcc']:
src += Glob('*_init.S')
src += Glob('*_gcc.S')
if rtconfig.PLATFORM in ['iccarm']:
src += Glob('*_iar.S')
group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

95
rt-thread/libcpu/arm/s3c24x0/context_gcc.S Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2006-09-06 XuXinming first version
*/
/*!
* \addtogroup S3C24X0
*/
/*@{*/
#define NOINT 0xc0
/*
* rt_base_t rt_hw_interrupt_disable();
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mrs r0, cpsr
orr r1, r0, #NOINT
msr cpsr_c, r1
mov pc, lr
/*
* void rt_hw_interrupt_enable(rt_base_t level);
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
msr cpsr, r0
mov pc, lr
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
* r0 --> from
* r1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC)
stmfd sp!, {r0-r12, lr} @ push lr & register file
mrs r4, cpsr
stmfd sp!, {r4} @ push cpsr
mrs r4, spsr
stmfd sp!, {r4} @ push spsr
str sp, [r0] @ store sp in preempted tasks TCB
ldr sp, [r1] @ get new task stack pointer
ldmfd sp!, {r4} @ pop new task spsr
msr spsr_cxsf, r4
ldmfd sp!, {r4} @ pop new task cpsr
msr spsr_cxsf, r4
ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc
/*
* void rt_hw_context_switch_to(rt_uint32 to);
* r0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
ldr sp, [r0] @ get new task stack pointer
ldmfd sp!, {r4} @ pop new task spsr
msr spsr_cxsf, r4
ldmfd sp!, {r4} @ pop new task cpsr
msr cpsr_cxsf, r4
ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
ldr r2, =rt_thread_switch_interrupt_flag
ldr r3, [r2]
cmp r3, #1
beq _reswitch
mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1
str r3, [r2]
ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread
str r0, [r2]
_reswitch:
ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread
str r1, [r2]
mov pc, lr

103
rt-thread/libcpu/arm/s3c24x0/context_rvds.S Normal file
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;/*
; * Copyright (c) 2006-2022, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-20 Bernard first version
; */
NOINT EQU 0xc0 ; disable interrupt in psr
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, cpsr
ORR r1, r0, #NOINT
MSR cpsr_c, r1
BX lr
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR cpsr_c, r0
BX lr
ENDP
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
rt_hw_context_switch PROC
EXPORT rt_hw_context_switch
STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC)
STMFD sp!, {r0-r12, lr} ; push lr & register file
MRS r4, cpsr
STMFD sp!, {r4} ; push cpsr
MRS r4, spsr
STMFD sp!, {r4} ; push spsr
STR sp, [r0] ; store sp in preempted tasks TCB
LDR sp, [r1] ; get new task stack pointer
LDMFD sp!, {r4} ; pop new task spsr
MSR spsr_cxsf, r4
LDMFD sp!, {r4} ; pop new task cpsr
MSR spsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; */
rt_hw_context_switch_to PROC
EXPORT rt_hw_context_switch_to
LDR sp, [r0] ; get new task stack pointer
LDMFD sp!, {r4} ; pop new task spsr
MSR spsr_cxsf, r4
LDMFD sp!, {r4} ; pop new task cpsr
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
ENDP
;/*
; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
; */
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
rt_hw_context_switch_interrupt PROC
EXPORT rt_hw_context_switch_interrupt
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
BX lr
ENDP
END

171
rt-thread/libcpu/arm/s3c24x0/cpu.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
*/
#include <rthw.h>
#include <rtthread.h>
#include "s3c24x0.h"
/**
* @addtogroup S3C24X0
*/
/*@{*/
#define ICACHE_MASK (rt_uint32_t)(1 << 12)
#define DCACHE_MASK (rt_uint32_t)(1 << 2)
#ifdef __GNUC__
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
#endif
#ifdef __CC_ARM
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
__asm
{
mrc p15, 0, i, c1, c0, 0
}
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
orr value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
rt_inline void cache_disable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
bic value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
#endif
/**
* enable I-Cache
*
*/
void rt_hw_cpu_icache_enable()
{
cache_enable(ICACHE_MASK);
}
/**
* disable I-Cache
*
*/
void rt_hw_cpu_icache_disable()
{
cache_disable(ICACHE_MASK);
}
/**
* return the status of I-Cache
*
*/
rt_base_t rt_hw_cpu_icache_status()
{
return (cp15_rd() & ICACHE_MASK);
}
/**
* enable D-Cache
*
*/
void rt_hw_cpu_dcache_enable()
{
cache_enable(DCACHE_MASK);
}
/**
* disable D-Cache
*
*/
void rt_hw_cpu_dcache_disable()
{
cache_disable(DCACHE_MASK);
}
/**
* return the status of D-Cache
*
*/
rt_base_t rt_hw_cpu_dcache_status()
{
return (cp15_rd() & DCACHE_MASK);
}
/**
* reset cpu by dog's time-out
*
*/
void rt_hw_cpu_reset()
{
/* Disable all interrupt except the WDT */
INTMSK = (~((rt_uint32_t)1 << INTWDT));
/* Disable watchdog */
WTCON = 0x0000;
/* Initialize watchdog timer count register */
WTCNT = 0x0001;
/* Enable watchdog timer; assert reset at timer timeout */
WTCON = 0x0021;
while(1); /* loop forever and wait for reset to happen */
/* NEVER REACHED */
}
/*@}*/

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rt-thread/libcpu/arm/s3c24x0/cpuport.h Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef CPUPORT_H__
#define CPUPORT_H__
#ifdef RT_USING_SMP
typedef union {
unsigned long slock;
struct __arch_tickets {
unsigned short owner;
unsigned short next;
} tickets;
} rt_hw_spinlock_t;
#endif
#endif /*CPUPORT_H__*/

128
rt-thread/libcpu/arm/s3c24x0/interrupt.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
* 2013-03-29 aozima Modify the interrupt interface implementations.
*/
#include <rtthread.h>
#include <rthw.h>
#include "s3c24x0.h"
#define MAX_HANDLERS 32
extern rt_uint32_t rt_interrupt_nest;
/* exception and interrupt handler table */
struct rt_irq_desc isr_table[MAX_HANDLERS];
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
/**
* @addtogroup S3C24X0
*/
/*@{*/
static void rt_hw_interrupt_handle(int vector, void *param)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
register rt_uint32_t idx;
/* all clear source pending */
SRCPND = 0x0;
/* all clear sub source pending */
SUBSRCPND = 0x0;
/* all=IRQ mode */
INTMOD = 0x0;
/* all interrupt disabled include global bit */
INTMSK = BIT_ALLMSK;
/* all sub interrupt disable */
INTSUBMSK = BIT_SUB_ALLMSK;
/* all clear interrupt pending */
INTPND = BIT_ALLMSK;
/* init exceptions table */
rt_memset(isr_table, 0x00, sizeof(isr_table));
for(idx=0; idx < MAX_HANDLERS; idx++)
{
isr_table[idx].handler = rt_hw_interrupt_handle;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
INTMSK |= 1 << vector;
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
if (vector == INTNOTUSED6)
{
rt_kprintf("Interrupt vec %d is not used!\n", vector);
// while(1);
}
else if (vector == INTGLOBAL)
INTMSK = 0x0;
else
INTMSK &= ~(1 << vector);
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if(vector < MAX_HANDLERS)
{
old_handler = isr_table[vector].handler;
if (handler != RT_NULL)
{
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
isr_table[vector].handler = handler;
isr_table[vector].param = param;
}
}
return old_handler;
}
/*@}*/

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rt-thread/libcpu/arm/s3c24x0/mmu.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2008-04-25 Yi.qiu first version
* 2009-12-18 Bernard port to armcc
*/
#include <rtthread.h>
#include "s3c24x0.h"
#define _MMUTT_STARTADDRESS 0x33FF0000
#define DESC_SEC (0x2|(1<<4))
#define CB (3<<2) //cache_on, write_back
#define CNB (2<<2) //cache_on, write_through
#define NCB (1<<2) //cache_off,WR_BUF on
#define NCNB (0<<2) //cache_off,WR_BUF off
#define AP_RW (3<<10) //supervisor=RW, user=RW
#define AP_RO (2<<10) //supervisor=RW, user=RO
#define DOMAIN_FAULT (0x0)
#define DOMAIN_CHK (0x1)
#define DOMAIN_NOTCHK (0x3)
#define DOMAIN0 (0x0<<5)
#define DOMAIN1 (0x1<<5)
#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
#ifdef __GNUC__
void mmu_setttbase(register rt_uint32_t i)
{
asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i));
}
void mmu_set_domain(register rt_uint32_t i)
{
asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
}
void mmu_enable()
{
register rt_uint32_t i;
/* read control register */
asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
i |= 0x1;
/* write back to control register */
asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_disable()
{
register rt_uint32_t i;
/* read control register */
asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
i &= ~0x1;
/* write back to control register */
asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_enable_icache()
{
register rt_uint32_t i;
/* read control register */
asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
i |= (1 << 12);
/* write back to control register */
asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_enable_dcache()
{
register rt_uint32_t i;
/* read control register */
asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
i |= (1 << 2);
/* write back to control register */
asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_disable_icache()
{
register rt_uint32_t i;
/* read control register */
asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
i &= ~(1 << 12);
/* write back to control register */
asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_disable_dcache()
{
register rt_uint32_t i;
/* read control register */
asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
i &= ~(1 << 2);
/* write back to control register */
asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_enable_alignfault()
{
register rt_uint32_t i;
/* read control register */
asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
i |= (1 << 1);
/* write back to control register */
asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_disable_alignfault()
{
register rt_uint32_t i;
/* read control register */
asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
i &= ~(1 << 1);
/* write back to control register */
asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}
void mmu_clean_invalidated_cache_index(int index)
{
asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
}
void mmu_invalidate_tlb()
{
asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
}
void mmu_invalidate_icache()
{
asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
}
#endif
#ifdef __CC_ARM
void mmu_setttbase(rt_uint32_t i)
{
__asm volatile
{
mcr p15, 0, i, c2, c0, 0
}
}
void mmu_set_domain(rt_uint32_t i)
{
__asm volatile
{
mcr p15,0, i, c3, c0, 0
}
}
void mmu_enable()
{
register rt_uint32_t value;
__asm volatile
{
mrc p15, 0, value, c1, c0, 0
orr value, value, #0x01
mcr p15, 0, value, c1, c0, 0
}
}
void mmu_disable()
{
register rt_uint32_t value;
__asm volatile
{
mrc p15, 0, value, c1, c0, 0
bic value, value, #0x01
mcr p15, 0, value, c1, c0, 0
}
}
void mmu_enable_icache()
{
register rt_uint32_t value;
__asm volatile
{
mrc p15, 0, value, c1, c0, 0
orr value, value, #0x1000
mcr p15, 0, value, c1, c0, 0
}
}
void mmu_enable_dcache()
{
register rt_uint32_t value;
__asm volatile
{
mrc p15, 0, value, c1, c0, 0
orr value, value, #0x04
mcr p15, 0, value, c1, c0, 0
}
}
void mmu_disable_icache()
{
register rt_uint32_t value;
__asm volatile
{
mrc p15, 0, value, c1, c0, 0
bic value, value, #0x1000
mcr p15, 0, value, c1, c0, 0
}
}
void mmu_disable_dcache()
{
register rt_uint32_t value;
__asm volatile
{
mrc p15, 0, value, c1, c0, 0
bic value, value, #0x04
mcr p15, 0, value, c1, c0, 0
}
}
void mmu_enable_alignfault()
{
register rt_uint32_t value;
__asm volatile
{
mrc p15, 0, value, c1, c0, 0
orr value, value, #0x02
mcr p15, 0, value, c1, c0, 0
}
}
void mmu_disable_alignfault()
{
register rt_uint32_t value;
__asm volatile
{
mrc p15, 0, value, c1, c0, 0
bic value, value, #0x02
mcr p15, 0, value, c1, c0, 0
}
}
void mmu_clean_invalidated_cache_index(int index)
{
__asm volatile
{
mcr p15, 0, index, c7, c14, 2
}
}
void mmu_invalidate_tlb()
{
register rt_uint32_t value;
value = 0;
__asm volatile
{
mcr p15, 0, value, c8, c7, 0
}
}
void mmu_invalidate_icache()
{
register rt_uint32_t value;
value = 0;
__asm volatile
{
mcr p15, 0, value, c7, c5, 0
}
}
#endif
void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
{
volatile rt_uint32_t *pTT;
volatile int i,nSec;
pTT=(rt_uint32_t *)_MMUTT_STARTADDRESS+(vaddrStart>>20);
nSec=(vaddrEnd>>20)-(vaddrStart>>20);
for(i=0;i<=nSec;i++)
{
*pTT = attr |(((paddrStart>>20)+i)<<20);
pTT++;
}
}
void rt_hw_mmu_init(void)
{
int i,j;
//========================== IMPORTANT NOTE =========================
//The current stack and code area can't be re-mapped in this routine.
//If you want memory map mapped freely, your own sophiscated mmu
//initialization code is needed.
//===================================================================
mmu_disable_dcache();
mmu_disable_icache();
//If write-back is used,the DCache should be cleared.
for(i=0;i<64;i++)
for(j=0;j<8;j++)
mmu_clean_invalidated_cache_index((i<<26)|(j<<5));
mmu_invalidate_icache();
//To complete mmu_Init() fast, Icache may be turned on here.
mmu_enable_icache();
mmu_disable();
mmu_invalidate_tlb();
//mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr);
mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0
mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0
mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0
mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1
mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
//mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000
mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
//30f00000->30100000, 31000000->30200000
mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1
mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2
mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3
mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used
mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR
mmu_setttbase(_MMUTT_STARTADDRESS);
/* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */
mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
mmu_enable_alignfault();
mmu_enable();
/* ICache enable */
mmu_enable_icache();
/* DCache should be turned on after mmu is turned on. */
mmu_enable_dcache();
}

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2009-04-26 yi.qiu first version
* 2010-03-18 Gary Lee add functions such as GregorianDay
* and rtc_time_to_tm
* 2009-03-20 yi.qiu clean up
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <sys/time.h>
#include <s3c24x0.h>
// #define RTC_DEBUG
#ifdef RT_USING_RTC
#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */
#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */
#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F))
#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10))
/**
* This function get rtc time
*/
void rt_hw_rtc_get(struct tm *ti)
{
rt_uint8_t sec, min, hour, mday, wday, mon, year;
/* enable access to RTC registers */
RTCCON |= RTC_ENABLE;
/* read RTC registers */
do
{
sec = BCDSEC;
min = BCDMIN;
hour = BCDHOUR;
mday = BCDDATE;
wday = BCDDAY;
mon = BCDMON;
year = BCDYEAR;
} while (sec != BCDSEC);
#ifdef RTC_DEBUG
rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n",
sec, min, hour, mday, wday, mon, year);
#endif
/* disable access to RTC registers */
RTC_DISABLE
ti->tm_sec = BCD2BIN(sec & 0x7F);
ti->tm_min = BCD2BIN(min & 0x7F);
ti->tm_hour = BCD2BIN(hour & 0x3F);
ti->tm_mday = BCD2BIN(mday & 0x3F);
ti->tm_mon = BCD2BIN(mon & 0x1F);
ti->tm_year = BCD2BIN(year);
ti->tm_wday = BCD2BIN(wday & 0x07);
ti->tm_yday = 0;
ti->tm_isdst = 0;
}
/**
* This function set rtc time
*/
void rt_hw_rtc_set(struct tm *ti)
{
rt_uint8_t sec, min, hour, mday, wday, mon, year;
year = BIN2BCD(ti->tm_year);
mon = BIN2BCD(ti->tm_mon);
wday = BIN2BCD(ti->tm_wday);
mday = BIN2BCD(ti->tm_mday);
hour = BIN2BCD(ti->tm_hour);
min = BIN2BCD(ti->tm_min);
sec = BIN2BCD(ti->tm_sec);
/* enable access to RTC registers */
RTC_ENABLE
do{
/* write RTC registers */
BCDSEC = sec;
BCDMIN = min;
BCDHOUR = hour;
BCDDATE = mday;
BCDDAY = wday;
BCDMON = mon;
BCDYEAR = year;
}while (sec != BCDSEC);
/* disable access to RTC registers */
RTC_DISABLE
}
/**
* This function reset rtc
*/
void rt_hw_rtc_reset (void)
{
RTCCON = (RTCCON & ~0x06) | 0x08;
RTCCON &= ~(0x08|0x01);
}
static struct rt_device rtc;
static rt_err_t rtc_open(rt_device_t dev, rt_uint16_t oflag)
{
RTC_ENABLE
return RT_EOK;
}
static rt_err_t rtc_close(rt_device_t dev)
{
RTC_DISABLE
return RT_EOK;
}
static rt_ssize_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
return RT_EOK;
}
static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args)
{
struct tm tmp;
time_t *time;
RT_ASSERT(dev != RT_NULL);
time = (time_t *)args;
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
/* read device */
rt_hw_rtc_get(&tmp);
*((rt_time_t *)args) = timegm(&tmp);
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
/* write device */
gmtime_r(time, &tmp);
rt_hw_rtc_set(&tmp);
break;
}
return RT_EOK;
}
void rt_hw_rtc_init(void)
{
rtc.type = RT_Device_Class_RTC;
/* register rtc device */
rtc.init = RT_NULL;
rtc.open = rtc_open;
rtc.close = rtc_close;
rtc.read = rtc_read;
rtc.write = RT_NULL;
rtc.control = rtc_control;
/* no private */
rtc.user_data = RT_NULL;
rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
}
#ifdef RT_USING_FINSH
#include <finsh.h>
void list_date()
{
time_t time;
rt_device_t device;
device = rt_device_find("rtc");
if (device != RT_NULL)
{
rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time);
rt_kprintf("%d, %s\n", time, ctime(&time));
}
}
FINSH_FUNCTION_EXPORT(list_date, list date);
#endif
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-03-20 yi.qiu the first version
*/
#ifndef __RTC_H__
#define __RTC_H__
void rt_hw_rtc_init(void);
#endif

607
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2009-12-11 Bernard first version
*/
#ifndef __S3C24X0_H__
#define __S3C24X0_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <rtthread.h>
/**
* @addtogroup S3C24X0
*/
/*@{*/
// Memory control
#define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status
#define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control
#define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control
#define BANKCON2 (*(volatile unsigned *)0x4800000c) //BANK2 cControl
#define BANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control
#define BANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control
#define BANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control
#define BANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control
#define BANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control
#define REFRESH (*(volatile unsigned *)0x48000024) //DRAM/SDRAM efresh
#define BANKSIZE (*(volatile unsigned *)0x48000028) //Flexible Bank Size
#define MRSRB6 (*(volatile unsigned *)0x4800002c) //Mode egister set for SDRAM
#define MRSRB7 (*(volatile unsigned *)0x48000030) //Mode egister set for SDRAM
// USB Host
// INTERRUPT
#define SRCPND (*(volatile unsigned *)0x4a000000) //Interrupt request status
#define INTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control
#define INTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control
#define PRIORITY (*(volatile unsigned *)0x4a00000c) //IRQ priority control
#define INTPND (*(volatile unsigned *)0x4a000010) //Interrupt request status
#define INTOFFSET (*(volatile unsigned *)0x4a000014) //Interruot request source offset
#define SUBSRCPND (*(volatile unsigned *)0x4a000018) //Sub source pending
#define INTSUBMSK (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask
// DMA
#define DISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source
#define DISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control
#define DIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination
#define DIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control
#define DCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control
#define DSTAT0 (*(volatile unsigned *)0x4b000014) //DMA 0 Status
#define DCSRC0 (*(volatile unsigned *)0x4b000018) //DMA 0 Current source
#define DCDST0 (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination
#define DMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger
#define DISRC1 (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source
#define DISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control
#define DIDST1 (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination
#define DIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control
#define DCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control
#define DSTAT1 (*(volatile unsigned *)0x4b000054) //DMA 1 Status
#define DCSRC1 (*(volatile unsigned *)0x4b000058) //DMA 1 Current source
#define DCDST1 (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination
#define DMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger
#define DISRC2 (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source
#define DISRCC2 (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control
#define DIDST2 (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination
#define DIDSTC2 (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control
#define DCON2 (*(volatile unsigned *)0x4b000090) //DMA 2 Control
#define DSTAT2 (*(volatile unsigned *)0x4b000094) //DMA 2 Status
#define DCSRC2 (*(volatile unsigned *)0x4b000098) //DMA 2 Current source
#define DCDST2 (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination
#define DMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger
#define DISRC3 (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source
#define DISRCC3 (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control
#define DIDST3 (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination
#define DIDSTC3 (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control
#define DCON3 (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control
#define DSTAT3 (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status
#define DCSRC3 (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source
#define DCDST3 (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination
#define DMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger
// CLOCK & POWER MANAGEMENT
#define LOCKTIME (*(volatile unsigned *)0x4c000000) //PLL lock time counter
#define MPLLCON (*(volatile unsigned *)0x4c000004) //MPLL Control
#define UPLLCON (*(volatile unsigned *)0x4c000008) //UPLL Control
#define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control
#define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control
#define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control
#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control
// LCD CONTROLLER
#define LCDCON1 (*(volatile unsigned *)0x4d000000) //LCD control 1
#define LCDCON2 (*(volatile unsigned *)0x4d000004) //LCD control 2
#define LCDCON3 (*(volatile unsigned *)0x4d000008) //LCD control 3
#define LCDCON4 (*(volatile unsigned *)0x4d00000c) //LCD control 4
#define LCDCON5 (*(volatile unsigned *)0x4d000010) //LCD control 5
#define LCDSADDR1 (*(volatile unsigned *)0x4d000014) //STN/TFT Frame buffer start address 1
#define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2
#define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set
#define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table
#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table
#define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table
#define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode
#define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette
#define LCDINTPND (*(volatile unsigned *)0x4d000054) //LCD Interrupt pending
#define LCDSRCPND (*(volatile unsigned *)0x4d000058) //LCD Interrupt source
#define LCDINTMSK (*(volatile unsigned *)0x4d00005c) //LCD Interrupt mask
#define LPCSEL (*(volatile unsigned *)0x4d000060) //LPC3600 Control
#define PALETTE 0x4d000400 //Palette start address
// NAND flash
#define NFCONF (*(volatile unsigned *)0x4e000000) //NAND Flash configuration
#define NFCMD (*(volatile unsigned *)0x4e000004) //NADD Flash command
#define NFADDR (*(volatile unsigned *)0x4e000008) //NAND Flash address
#define NFDATA (*(volatile unsigned *)0x4e00000c) //NAND Flash data
#define NFSTAT (*(volatile unsigned *)0x4e000010) //NAND Flash operation status
#define NFECC (*(volatile unsigned *)0x4e000014) //NAND Flash ECC
#define NFECC0 (*(volatile unsigned *)0x4e000014)
#define NFECC1 (*(volatile unsigned *)0x4e000015)
#define NFECC2 (*(volatile unsigned *)0x4e000016)
// UART
#define U0BASE (*(volatile unsigned *)0x50000000) //UART 0 Line control
#define ULCON0 (*(volatile unsigned *)0x50000000) //UART 0 Line control
#define UCON0 (*(volatile unsigned *)0x50000004) //UART 0 Control
#define UFCON0 (*(volatile unsigned *)0x50000008) //UART 0 FIFO control
#define UMCON0 (*(volatile unsigned *)0x5000000c) //UART 0 Modem control
#define USTAT0 (*(volatile unsigned *)0x50000010) //UART 0 Tx/Rx status
#define URXB0 (*(volatile unsigned *)0x50000014) //UART 0 Rx error status
#define UFSTAT0 (*(volatile unsigned *)0x50000018) //UART 0 FIFO status
#define UMSTAT0 (*(volatile unsigned *)0x5000001c) //UART 0 Modem status
#define UBRD0 (*(volatile unsigned *)0x50000028) //UART 0 Baud ate divisor
#define U1BASE (*(volatile unsigned *)0x50004000) //UART 1 Line control
#define ULCON1 (*(volatile unsigned *)0x50004000) //UART 1 Line control
#define UCON1 (*(volatile unsigned *)0x50004004) //UART 1 Control
#define UFCON1 (*(volatile unsigned *)0x50004008) //UART 1 FIFO control
#define UMCON1 (*(volatile unsigned *)0x5000400c) //UART 1 Modem control
#define USTAT1 (*(volatile unsigned *)0x50004010) //UART 1 Tx/Rx status
#define URXB1 (*(volatile unsigned *)0x50004014) //UART 1 Rx error status
#define UFSTAT1 (*(volatile unsigned *)0x50004018) //UART 1 FIFO status
#define UMSTAT1 (*(volatile unsigned *)0x5000401c) //UART 1 Modem status
#define UBRD1 (*(volatile unsigned *)0x50004028) //UART 1 Baud ate divisor
#define U2BASE *(volatile unsigned *)0x50008000 //UART 2 Line control
#define ULCON2 (*(volatile unsigned *)0x50008000) //UART 2 Line control
#define UCON2 (*(volatile unsigned *)0x50008004) //UART 2 Control
#define UFCON2 (*(volatile unsigned *)0x50008008) //UART 2 FIFO control
#define UMCON2 (*(volatile unsigned *)0x5000800c) //UART 2 Modem control
#define USTAT2 (*(volatile unsigned *)0x50008010) //UART 2 Tx/Rx status
#define URXB2 (*(volatile unsigned *)0x50008014) //UART 2 Rx error status
#define UFSTAT2 (*(volatile unsigned *)0x50008018) //UART 2 FIFO status
#define UMSTAT2 (*(volatile unsigned *)0x5000801c) //UART 2 Modem status
#define UBRD2 (*(volatile unsigned *)0x50008028) //UART 2 Baud ate divisor
#ifdef __BIG_ENDIAN
#define UTXH0 (*(volatile unsigned char *)0x50000023) //UART 0 Transmission Hold
#define URXH0 (*(volatile unsigned char *)0x50000027) //UART 0 Receive buffer
#define UTXH1 (*(volatile unsigned char *)0x50004023) //UART 1 Transmission Hold
#define URXH1 (*(volatile unsigned char *)0x50004027) //UART 1 Receive buffer
#define UTXH2 (*(volatile unsigned char *)0x50008023) //UART 2 Transmission Hold
#define URXH2 (*(volatile unsigned char *)0x50008027) //UART 2 Receive buffer
#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
#define RdURXH0() (*(volatile unsigned char *)0x50000027)
#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
#define RdURXH1() (*(volatile unsigned char *)0x50004027)
#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
#define RdURXH2() (*(volatile unsigned char *)0x50008027)
#else //Little Endian
#define UTXH0 (*(volatile unsigned char *)0x50000020) //UART 0 Transmission Hold
#define URXH0 (*(volatile unsigned char *)0x50000024) //UART 0 Receive buffer
#define UTXH1 (*(volatile unsigned char *)0x50004020) //UART 1 Transmission Hold
#define URXH1 (*(volatile unsigned char *)0x50004024) //UART 1 Receive buffer
#define UTXH2 (*(volatile unsigned char *)0x50008020) //UART 2 Transmission Hold
#define URXH2 (*(volatile unsigned char *)0x50008024) //UART 2 Receive buffer
#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
#define RdURXH0() (*(volatile unsigned char *)0x50000024)
#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
#define RdURXH1() (*(volatile unsigned char *)0x50004024)
#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
#define RdURXH2() (*(volatile unsigned char *)0x50008024)
#endif
// PWM TIMER
#define TCFG0 (*(volatile unsigned *)0x51000000) //Timer 0 configuration
#define TCFG1 (*(volatile unsigned *)0x51000004) //Timer 1 configuration
#define TCON (*(volatile unsigned *)0x51000008) //Timer control
#define TCNTB0 (*(volatile unsigned *)0x5100000c) //Timer count buffer 0
#define TCMPB0 (*(volatile unsigned *)0x51000010) //Timer compare buffer 0
#define TCNTO0 (*(volatile unsigned *)0x51000014) //Timer count observation 0
#define TCNTB1 (*(volatile unsigned *)0x51000018) //Timer count buffer 1
#define TCMPB1 (*(volatile unsigned *)0x5100001c) //Timer compare buffer 1
#define TCNTO1 (*(volatile unsigned *)0x51000020) //Timer count observation 1
#define TCNTB2 (*(volatile unsigned *)0x51000024) //Timer count buffer 2
#define TCMPB2 (*(volatile unsigned *)0x51000028) //Timer compare buffer 2
#define TCNTO2 (*(volatile unsigned *)0x5100002c) //Timer count observation 2
#define TCNTB3 (*(volatile unsigned *)0x51000030) //Timer count buffer 3
#define TCMPB3 (*(volatile unsigned *)0x51000034) //Timer compare buffer 3
#define TCNTO3 (*(volatile unsigned *)0x51000038) //Timer count observation 3
#define TCNTB4 (*(volatile unsigned *)0x5100003c) //Timer count buffer 4
#define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4
// Added for 2440
#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only)
#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0
#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1
#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register
// USB DEVICE
#ifdef __BIG_ENDIAN
#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address
#define PWR_REG (*(volatile unsigned char *)0x52000147) //Power management
#define EP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear
#define USB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear
#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable
#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016f)
#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte
#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte
#define INDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index
#define MAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet
#define EP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status
#define IN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status
#define IN_CSR2_REG (*(volatile unsigned char *)0x5200018b)
#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status
#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000197)
#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count
#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f)
#define EP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO
#define EP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO
#define EP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO
#define EP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO
#define EP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO
#define EP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control
#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter
#define EP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter
#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter
#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213)
#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217)
#define EP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control
#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter
#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter
#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter
#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b)
#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f)
#define EP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control
#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter
#define EP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter
#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter
#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253)
#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257)
#define EP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control
#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter
#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter
#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter
#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b)
#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f)
#else // Little Endian
#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address
#define PWR_REG (*(volatile unsigned char *)0x52000144) //Power management
#define EP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear
#define USB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear
#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable
#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016c)
#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte
#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte
#define INDEX_REG (*(volatile unsigned char *)0x52000178) //Register index
#define MAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet
#define EP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status
#define IN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status
#define IN_CSR2_REG (*(volatile unsigned char *)0x52000188)
#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status
#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000194)
#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count
#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c)
#define EP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO
#define EP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO
#define EP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO
#define EP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO
#define EP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO
#define EP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control
#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter
#define EP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter
#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter
#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210)
#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214)
#define EP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control
#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter
#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter
#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter
#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228)
#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c)
#define EP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control
#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter
#define EP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter
#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter
#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250)
#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254)
#define EP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control
#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter
#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter
#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter
#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268)
#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c)
#endif // __BIG_ENDIAN
// WATCH DOG TIMER
#define WTCON (*(volatile unsigned *)0x53000000) //Watch-dog timer mode
#define WTDAT (*(volatile unsigned *)0x53000004) //Watch-dog timer data
#define WTCNT (*(volatile unsigned *)0x53000008) //Eatch-dog timer count
// IIC
#define IICCON (*(volatile unsigned *)0x54000000) //IIC control
#define IICSTAT (*(volatile unsigned *)0x54000004) //IIC status
#define IICADD (*(volatile unsigned *)0x54000008) //IIC address
#define IICDS (*(volatile unsigned *)0x5400000c) //IIC data shift
// IIS
#define IISCON (*(volatile unsigned *)0x55000000) //IIS Control
#define IISMOD (*(volatile unsigned *)0x55000004) //IIS Mode
#define IISPSR (*(volatile unsigned *)0x55000008) //IIS Prescaler
#define IISFCON (*(volatile unsigned *)0x5500000c) //IIS FIFO control
#ifdef __BIG_ENDIAN
#define IISFIFO ((volatile unsigned short *)0x55000012) //IIS FIFO entry
#else //Little Endian
#define IISFIFO ((volatile unsigned short *)0x55000010) //IIS FIFO entry
#endif
// I/O PORT
#define GPACON (*(volatile unsigned *)0x56000000) //Port A control
#define GPADAT (*(volatile unsigned *)0x56000004) //Port A data
#define GPBCON (*(volatile unsigned *)0x56000010) //Port B control
#define GPBDAT (*(volatile unsigned *)0x56000014) //Port B data
#define GPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B
#define GPCCON (*(volatile unsigned *)0x56000020) //Port C control
#define GPCDAT (*(volatile unsigned *)0x56000024) //Port C data
#define GPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C
#define GPDCON (*(volatile unsigned *)0x56000030) //Port D control
#define GPDDAT (*(volatile unsigned *)0x56000034) //Port D data
#define GPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D
#define GPECON (*(volatile unsigned *)0x56000040) //Port E control
#define GPEDAT (*(volatile unsigned *)0x56000044) //Port E data
#define GPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E
#define GPFCON (*(volatile unsigned *)0x56000050) //Port F control
#define GPFDAT (*(volatile unsigned *)0x56000054) //Port F data
#define GPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F
#define GPGCON (*(volatile unsigned *)0x56000060) //Port G control
#define GPGDAT (*(volatile unsigned *)0x56000064) //Port G data
#define GPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G
#define GPHCON (*(volatile unsigned *)0x56000070) //Port H control
#define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data
#define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H
#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control
#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data
#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J
#define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control
#define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control
#define EXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control egister 0
#define EXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control egister 1
#define EXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control egister 2
#define EINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved
#define EINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved
#define EINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control egister 2
#define EINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control egister 3
#define EINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask
#define EINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending
#define GSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status
#define GSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32410000)
#define GSTATUS2 (*(volatile unsigned *)0x560000b4) //Reset type
#define GSTATUS3 (*(volatile unsigned *)0x560000b8) //Saved data0(32-bit) before entering POWER_OFF mode
#define GSTATUS4 (*(volatile unsigned *)0x560000bc) //Saved data0(32-bit) before entering POWER_OFF mode
// RTC
#ifdef __BIG_ENDIAN
#define RTCCON (*(volatile unsigned char *)0x57000043) //RTC control
#define TICNT (*(volatile unsigned char *)0x57000047) //Tick time count
#define RTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control
#define ALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second
#define ALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute
#define ALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour
#define ALMDATE (*(volatile unsigned char *)0x57000063) //Alarm day <-- May 06, 2002 SOP
#define ALMMON (*(volatile unsigned char *)0x57000067) //Alarm month
#define ALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year
#define RTCRST (*(volatile unsigned char *)0x5700006f) //RTC ound eset
#define BCDSEC (*(volatile unsigned char *)0x57000073) //BCD second
#define BCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute
#define BCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour
#define BCDDATE (*(volatile unsigned char *)0x5700007f) //BCD day <-- May 06, 2002 SOP
#define BCDDAY (*(volatile unsigned char *)0x57000083) //BCD date <-- May 06, 2002 SOP
#define BCDMON (*(volatile unsigned char *)0x57000087) //BCD month
#define BCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year
#else //Little Endian
#define RTCCON (*(volatile unsigned char *)0x57000040) //RTC control
#define TICNT (*(volatile unsigned char *)0x57000044) //Tick time count
#define RTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control
#define ALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second
#define ALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute
#define ALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour
#define ALMDATE (*(volatile unsigned char *)0x57000060) //Alarm day <-- May 06, 2002 SOP
#define ALMMON (*(volatile unsigned char *)0x57000064) //Alarm month
#define ALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year
#define RTCRST (*(volatile unsigned char *)0x5700006c) //RTC ound eset
#define BCDSEC (*(volatile unsigned char *)0x57000070) //BCD second
#define BCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute
#define BCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour
#define BCDDATE (*(volatile unsigned char *)0x5700007c) //BCD day <-- May 06, 2002 SOP
#define BCDDAY (*(volatile unsigned char *)0x57000080) //BCD date <-- May 06, 2002 SOP
#define BCDMON (*(volatile unsigned char *)0x57000084) //BCD month
#define BCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year
#endif //RTC
// ADC
#define ADCCON (*(volatile unsigned *)0x58000000) //ADC control
#define ADCTSC (*(volatile unsigned *)0x58000004) //ADC touch screen control
#define ADCDLY (*(volatile unsigned *)0x58000008) //ADC start or Interval Delay
#define ADCDAT0 (*(volatile unsigned *)0x5800000c) //ADC conversion data 0
#define ADCDAT1 (*(volatile unsigned *)0x58000010) //ADC conversion data 1
// SPI
#define SPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control
#define SPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status
#define SPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control
#define SPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud ate prescaler
#define SPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data
#define SPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data
#define SPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control
#define SPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status
#define SPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control
#define SPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud ate prescaler
#define SPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data
#define SPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data
// SD Interface
#define SDICON (*(volatile unsigned *)0x5a000000) //SDI control
#define SDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud ate prescaler
#define SDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument
#define SDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control
#define SDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status
#define SDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI esponse 0
#define SDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI esponse 1
#define SDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI esponse 2
#define SDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI esponse 3
#define SDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer
#define SDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size
#define SDIDCON (*(volatile unsigned *)0x5a00002c) //SDI data control
#define SDIDCNT (*(volatile unsigned *)0x5a000030) //SDI data emain counter
#define SDIDSTA (*(volatile unsigned *)0x5a000034) //SDI data status
#define SDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status
#define SDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask
#ifdef __BIG_ENDIAN /* edited for 2440A */
#define SDIDAT (*(volatile unsigned *)0x5a00004c)
#else // Little Endian
#define SDIDAT (*(volatile unsigned *)0x5a000040)
#endif //SD Interface
// PENDING BIT
#define INTEINT0 (0)
#define INTEINT1 (1)
#define INTEINT2 (2)
#define INTEINT3 (3)
#define INTEINT4_7 (4)
#define INTEINT8_23 (5)
#define INTNOTUSED6 (6)
#define INTBAT_FLT (7)
#define INTTICK (8)
#define INTWDT (9)
#define INTTIMER0 (10)
#define INTTIMER1 (11)
#define INTTIMER2 (12)
#define INTTIMER3 (13)
#define INTTIMER4 (14)
#define INTUART2 (15)
#define INTLCD (16)
#define INTDMA0 (17)
#define INTDMA1 (18)
#define INTDMA2 (19)
#define INTDMA3 (20)
#define INTSDI (21)
#define INTSPI0 (22)
#define INTUART1 (23)
//#define INTNOTUSED24 (24)
#define INTNIC (24)
#define INTUSBD (25)
#define INTUSBH (26)
#define INTIIC (27)
#define INTUART0 (28)
#define INTSPI1 (29)
#define INTRTC (30)
#define INTADC (31)
#define BIT_ALLMSK (0xffffffff)
#define BIT_SUB_ALLMSK (0x7ff)
#define INTSUB_ADC (10)
#define INTSUB_TC (9)
#define INTSUB_ERR2 (8)
#define INTSUB_TXD2 (7)
#define INTSUB_RXD2 (6)
#define INTSUB_ERR1 (5)
#define INTSUB_TXD1 (4)
#define INTSUB_RXD1 (3)
#define INTSUB_ERR0 (2)
#define INTSUB_TXD0 (1)
#define INTSUB_RXD0 (0)
#define BIT_SUB_ADC (0x1<<10)
#define BIT_SUB_TC (0x1<<9)
#define BIT_SUB_ERR2 (0x1<<8)
#define BIT_SUB_TXD2 (0x1<<7)
#define BIT_SUB_RXD2 (0x1<<6)
#define BIT_SUB_ERR1 (0x1<<5)
#define BIT_SUB_TXD1 (0x1<<4)
#define BIT_SUB_RXD1 (0x1<<3)
#define BIT_SUB_ERR0 (0x1<<2)
#define BIT_SUB_TXD0 (0x1<<1)
#define BIT_SUB_RXD0 (0x1<<0)
#define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;}
//Wait until INTPND is changed for the case that the ISR is very short.
#define INTGLOBAL 32
/*****************************/
/* CPU Mode */
/*****************************/
#define USERMODE 0x10
#define FIQMODE 0x11
#define IRQMODE 0x12
#define SVCMODE 0x13
#define ABORTMODE 0x17
#define UNDEFMODE 0x1b
#define MODEMASK 0x1f
#define NOINT 0xc0
struct rt_hw_register
{
rt_uint32_t r0;
rt_uint32_t r1;
rt_uint32_t r2;
rt_uint32_t r3;
rt_uint32_t r4;
rt_uint32_t r5;
rt_uint32_t r6;
rt_uint32_t r7;
rt_uint32_t r8;
rt_uint32_t r9;
rt_uint32_t r10;
rt_uint32_t fp;
rt_uint32_t ip;
rt_uint32_t sp;
rt_uint32_t lr;
rt_uint32_t pc;
rt_uint32_t cpsr;
rt_uint32_t ORIG_r0;
};
#ifdef __cplusplus
}
#endif
/*@}*/
#endif

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rt-thread/libcpu/arm/s3c24x0/stack.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard the first version
*/
#include <rtthread.h>
#include "s3c24x0.h"
/**
* @addtogroup S3C24X0
*/
/*@{*/
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
stack_addr += sizeof(rt_uint32_t);
stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
stk = (rt_uint32_t *)stack_addr;
*(--stk) = (rt_uint32_t)tentry; /* entry point */
*(--stk) = (rt_uint32_t)texit; /* lr */
*(--stk) = 0xdeadbeef; /* r12 */
*(--stk) = 0xdeadbeef; /* r11 */
*(--stk) = 0xdeadbeef; /* r10 */
*(--stk) = 0xdeadbeef; /* r9 */
*(--stk) = 0xdeadbeef; /* r8 */
*(--stk) = 0xdeadbeef; /* r7 */
*(--stk) = 0xdeadbeef; /* r6 */
*(--stk) = 0xdeadbeef; /* r5 */
*(--stk) = 0xdeadbeef; /* r4 */
*(--stk) = 0xdeadbeef; /* r3 */
*(--stk) = 0xdeadbeef; /* r2 */
*(--stk) = 0xdeadbeef; /* r1 */
*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
*(--stk) = SVCMODE; /* cpsr */
*(--stk) = SVCMODE; /* spsr */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/

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rt-thread/libcpu/arm/s3c24x0/start_gcc.S Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
* 2006-10-05 Alsor.Z for s3c2440 initialize
* 2008-01-29 Yi.Qiu for QEMU emulator
*/
#define CONFIG_STACKSIZE 512
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
.equ USERMODE, 0x10
.equ FIQMODE, 0x11
.equ IRQMODE, 0x12
.equ SVCMODE, 0x13
.equ ABORTMODE, 0x17
.equ UNDEFMODE, 0x1b
.equ MODEMASK, 0x1f
.equ NOINT, 0xc0
.equ RAM_BASE, 0x00000000 /*Start address of RAM */
.equ ROM_BASE, 0x30000000 /*Start address of Flash */
.equ MPLLCON, 0x4c000004 /*Mpll control register */
.equ M_MDIV, 0x20
.equ M_PDIV, 0x4
.equ M_SDIV, 0x2
.equ INTMSK, 0x4a000008
.equ INTSUBMSK, 0x4a00001c
.equ WTCON, 0x53000000
.equ LOCKTIME, 0x4c000000
.equ CLKDIVN, 0x4c000014 /*Clock divider control */
.equ GPHCON, 0x56000070 /*Port H control */
.equ GPHUP, 0x56000078 /*Pull-up control H */
.equ BWSCON, 0x48000000 /*Bus width & wait status */
.equ BANKCON0, 0x48000004 /*Boot ROM control */
.equ BANKCON1, 0x48000008 /*BANK1 control */
.equ BANKCON2, 0x4800000c /*BANK2 cControl */
.equ BANKCON3, 0x48000010 /*BANK3 control */
.equ BANKCON4, 0x48000014 /*BANK4 control */
.equ BANKCON5, 0x48000018 /*BANK5 control */
.equ BANKCON6, 0x4800001c /*BANK6 control */
.equ BANKCON7, 0x48000020 /*BANK7 control */
.equ REFRESH, 0x48000024 /*DRAM/SDRAM efresh */
.equ BANKSIZE, 0x48000028 /*Flexible Bank Size */
.equ MRSRB6, 0x4800002c /*Mode egister set for SDRAM*/
.equ MRSRB7, 0x48000030 /*Mode egister set for SDRAM*/
/*
*************************************************************************
*
* Jump vector table
*
*************************************************************************
*/
.section .init, "ax"
.code 32
.globl _start
_start:
b reset
ldr pc, _vector_undef
ldr pc, _vector_swi
ldr pc, _vector_pabt
ldr pc, _vector_dabt
ldr pc, _vector_resv
ldr pc, _vector_irq
ldr pc, _vector_fiq
_vector_undef: .word vector_undef
_vector_swi: .word vector_swi
_vector_pabt: .word vector_pabt
_vector_dabt: .word vector_dabt
_vector_resv: .word vector_resv
_vector_irq: .word vector_irq
_vector_fiq: .word vector_fiq
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
* Startup Code (reset vector)
* relocate armboot to ram
* setup stack
* jump to second stage
*
*************************************************************************
*/
_TEXT_BASE:
.word TEXT_BASE
/*
* rtthread kernel start and end
* which are defined in linker script
*/
.globl _rtthread_start
_rtthread_start:
.word _start
.globl _rtthread_end
_rtthread_end:
.word _end
/*
* rtthread bss start and end which are defined in linker script
*/
.globl _bss_start
_bss_start:
.word __bss_start
.globl _bss_end
_bss_end:
.word __bss_end
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word _irq_stack_start + 1024
.globl FIQ_STACK_START
FIQ_STACK_START:
.word _fiq_stack_start + 1024
.globl UNDEFINED_STACK_START
UNDEFINED_STACK_START:
.word _undefined_stack_start + CONFIG_STACKSIZE
.globl ABORT_STACK_START
ABORT_STACK_START:
.word _abort_stack_start + CONFIG_STACKSIZE
.globl _STACK_START
_STACK_START:
.word _svc_stack_start + 4096
/* ----------------------------------entry------------------------------*/
reset:
/* set the cpu to SVC32 mode */
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r0,r0,#SVCMODE
msr cpsr,r0
/* watch dog disable */
ldr r0,=WTCON
ldr r1,=0x0
str r1,[r0]
/* mask all IRQs by clearing all bits in the INTMRs */
ldr r1, =INTMSK
ldr r0, =0xffffffff
str r0, [r1]
ldr r1, =INTSUBMSK
ldr r0, =0x7fff /*all sub interrupt disable */
str r0, [r1]
/* set interrupt vector */
ldr r0, _load_address
mov r1, #0x0 /* target address */
add r2, r0, #0x20 /* size, 32bytes */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
ble copy_loop
/* setup stack */
bl stack_setup
/* clear .bss */
mov r0,#0 /* get a zero */
ldr r1,=__bss_start /* bss start */
ldr r2,=__bss_end /* bss end */
bss_loop:
cmp r1,r2 /* check if data to clear */
strlo r0,[r1],#4 /* clear 4 bytes */
blo bss_loop /* loop until done */
/* call C++ constructors of global objects */
ldr r0, =__ctors_start__
ldr r1, =__ctors_end__
ctor_loop:
cmp r0, r1
beq ctor_end
ldr r2, [r0], #4
stmfd sp!, {r0-r1}
mov lr, pc
bx r2
ldmfd sp!, {r0-r1}
b ctor_loop
ctor_end:
/* start RT-Thread Kernel */
ldr pc, _rtthread_startup
_rtthread_startup:
.word rtthread_startup
#if defined (__FLASH_BUILD__)
_load_address:
.word ROM_BASE + _TEXT_BASE
#else
_load_address:
.word RAM_BASE + _TEXT_BASE
#endif
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
/* exception handlers */
.align 5
vector_undef:
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} /* Calling r0-r12 */
add r8, sp, #S_PC
stmdb r8, {sp, lr}^ /* Calling SP, LR */
str lr, [r8, #0] /* Save calling PC */
mrs r6, spsr
str r6, [r8, #4] /* Save CPSR */
str r0, [r8, #8] /* Save OLD_R0 */
mov r0, sp
bl rt_hw_trap_udef
.align 5
vector_swi:
bl rt_hw_trap_swi
.align 5
vector_pabt:
bl rt_hw_trap_pabt
.align 5
vector_dabt:
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} /* Calling r0-r12 */
add r8, sp, #S_PC
stmdb r8, {sp, lr}^ /* Calling SP, LR */
str lr, [r8, #0] /* Save calling PC */
mrs r6, spsr
str r6, [r8, #4] /* Save CPSR */
str r0, [r8, #8] /* Save OLD_R0 */
mov r0, sp
bl rt_hw_trap_dabt
.align 5
vector_resv:
bl rt_hw_trap_resv
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
vector_irq:
stmfd sp!, {r0-r12,lr}
bl rt_interrupt_enter
bl rt_hw_trap_irq
bl rt_interrupt_leave
/* if rt_thread_switch_interrupt_flag set, jump to _interrupt_thread_switch and don't return */
ldr r0, =rt_thread_switch_interrupt_flag
ldr r1, [r0]
cmp r1, #1
beq _interrupt_thread_switch
ldmfd sp!, {r0-r12,lr}
subs pc, lr, #4
.align 5
vector_fiq:
stmfd sp!,{r0-r7,lr}
bl rt_hw_trap_fiq
ldmfd sp!,{r0-r7,lr}
subs pc,lr,#4
_interrupt_thread_switch:
mov r1, #0 /* clear rt_thread_switch_interrupt_flag*/
str r1, [r0]
ldmfd sp!, {r0-r12,lr} /* reload saved registers */
stmfd sp!, {r0-r3} /* save r0-r3 */
mov r1, sp
add sp, sp, #16 /* restore sp */
sub r2, lr, #4 /* save old task's pc to r2 */
mrs r3, spsr /* disable interrupt */
orr r0, r3, #NOINT
msr spsr_c, r0
ldr r0, =.+8 /* switch to interrupted task's stack*/
movs pc, r0
stmfd sp!, {r2} /* push old task's pc */
stmfd sp!, {r4-r12,lr} /* push old task's lr,r12-r4 */
mov r4, r1 /* Special optimised code below */
mov r5, r3
ldmfd r4!, {r0-r3}
stmfd sp!, {r0-r3} /* push old task's r3-r0 */
stmfd sp!, {r5} /* push old task's psr */
mrs r4, spsr
stmfd sp!, {r4} /* push old task's spsr */
ldr r4, =rt_interrupt_from_thread
ldr r5, [r4]
str sp, [r5] /* store sp in preempted tasks's TCB*/
ldr r6, =rt_interrupt_to_thread
ldr r6, [r6]
ldr sp, [r6] /* get new task's stack pointer */
ldmfd sp!, {r4} /* pop new task's spsr */
msr SPSR_cxsf, r4
ldmfd sp!, {r4} /* pop new task's psr */
msr CPSR_cxsf, r4
ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */
stack_setup:
mrs r0, cpsr
bic r0, r0, #MODEMASK
orr r1, r0, #UNDEFMODE|NOINT
msr cpsr_cxsf, r1 /* undef mode */
ldr sp, UNDEFINED_STACK_START
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 /* abort mode */
ldr sp, ABORT_STACK_START
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 /* IRQ mode */
ldr sp, IRQ_STACK_START
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 /* FIQ mode */
ldr sp, FIQ_STACK_START
bic r0,r0,#MODEMASK
orr r1,r0,#SVCMODE|NOINT
msr cpsr_cxsf,r1 /* SVC mode */
ldr sp, _STACK_START
/* USER mode is not initialized. */
mov pc,lr /* The LR register may be not valid for the mode changes.*/
/*/*}*/

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2008-04-25 Yi.qiu first version
*/
#include <rtthread.h>
#include "s3c24x0.h"
#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz
#if CONFIG_SYS_CLK_FREQ == 12000000
/* MPLL=2*12*100/6=400MHz */
#define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */
#define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */
#define MPL_SDIV 0 /* s=MPL_SDIV=0 */
/* UPLL=12*64/8=96MHz */
#define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */
#define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */
#define UPL_SDIV 1 /* s=UPL_SDIV=1 */
/* System clock divider FCLK:HCLK:PCLK=1:4:8 */
#define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */
#define HDIVN 0x2 /* HCLK = FCLK / 4 */
#define PDIVN 0x1 /* PCLK = HCLK / 2 */
#endif
rt_uint32_t PCLK;
rt_uint32_t FCLK;
rt_uint32_t HCLK;
rt_uint32_t UCLK;
void rt_hw_get_clock(void)
{
rt_uint32_t val;
rt_uint8_t m, p, s;
val = MPLLCON;
m = (val>>12)&0xff;
p = (val>>4)&0x3f;
s = val&3;
FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100;
val = CLKDIVN;
m = (val>>1)&3;
p = val&1;
switch (m) {
case 0:
HCLK = FCLK;
break;
case 1:
HCLK = FCLK>>1;
break;
case 2:
if(s&2)
HCLK = FCLK>>3;
else
HCLK = FCLK>>2;
break;
case 3:
if(s&1)
HCLK = FCLK/6;
else
HCLK = FCLK/3;
break;
}
if(p)
PCLK = HCLK>>1;
else
PCLK = HCLK;
}
void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
{
MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12);
}
void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
{
UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
}
void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn)
{
CLKDIVN = (hdivn<<1) | pdivn;
}
/**
* @brief System Clock Configuration
*/
void rt_hw_clock_init(void)
{
LOCKTIME = 0xFFFFFFFF;
rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV);
rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV);
rt_hw_set_divider(HDIVN, PDIVN);
}

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
* 2006-05-27 Bernard add skyeye support
* 2007-11-19 Yi.Qiu fix rt_hw_trap_irq function
* 2013-03-29 aozima Modify the interrupt interface implementations.
*/
#include <rtthread.h>
#include <rthw.h>
#include "s3c24x0.h"
/**
* @addtogroup S3C24X0
*/
/*@{*/
extern struct rt_thread *rt_current_thread;
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
extern long list_thread(void);
#endif
/**
* this function will show registers of CPU
*
* @param regs the registers point
*/
void rt_hw_show_register (struct rt_hw_register *regs)
{
rt_kprintf("Execption:\n");
rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
}
/**
* When ARM7TDMI comes across an instruction which it cannot handle,
* it takes the undefined instruction trap.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_udef(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_kprintf("undefined instruction\n");
rt_kprintf("thread - %s stack:\n", rt_current_thread->parent.name);
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
list_thread();
#endif
rt_hw_cpu_shutdown();
}
/**
* The software interrupt instruction (SWI) is used for entering
* Supervisor mode, usually to request a particular supervisor
* function.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_swi(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_kprintf("software interrupt\n");
rt_hw_cpu_shutdown();
}
/**
* An abort indicates that the current memory access cannot be completed,
* which occurs during an instruction prefetch.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_pabt(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_kprintf("prefetch abort\n");
rt_kprintf("thread - %s stack:\n", rt_current_thread->parent.name);
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
list_thread();
#endif
rt_hw_cpu_shutdown();
}
/**
* An abort indicates that the current memory access cannot be completed,
* which occurs during a data access.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_dabt(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_kprintf("data abort\n");
rt_kprintf("thread - %s stack:\n", rt_current_thread->parent.name);
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
list_thread();
#endif
rt_hw_cpu_shutdown();
}
/**
* Normally, system will never reach here
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_resv(struct rt_hw_register *regs)
{
rt_kprintf("not used\n");
rt_hw_show_register(regs);
rt_hw_cpu_shutdown();
}
extern struct rt_irq_desc isr_table[];
void rt_hw_trap_irq(void)
{
unsigned long irq;
rt_isr_handler_t isr_func;
void *param;
irq = INTOFFSET;
if (irq == INTGLOBAL) return;
/* get interrupt service routine */
isr_func = isr_table[irq].handler;
param = isr_table[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
/* clear pending register */
/* note: must be the last, if not, may repeat*/
ClearPending(1 << irq);
#ifdef RT_USING_INTERRUPT_INFO
isr_table[irq].counter++;
#endif /* RT_USING_INTERRUPT_INFO */
}
void rt_hw_trap_fiq(void)
{
rt_kprintf("fast interrupt request\n");
}
/*@}*/