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james
2024-08-05 20:57:09 +08:00
commit 46d9ee7795
3020 changed files with 1725767 additions and 0 deletions
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34
rt-thread/components/drivers/Kconfig Normal file
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menu "Device Drivers"
rsource "core/Kconfig"
rsource "ipc/Kconfig"
rsource "serial/Kconfig"
rsource "can/Kconfig"
rsource "cputime/Kconfig"
rsource "i2c/Kconfig"
rsource "phy/Kconfig"
rsource "misc/Kconfig"
rsource "mtd/Kconfig"
rsource "pm/Kconfig"
rsource "rtc/Kconfig"
rsource "sdio/Kconfig"
rsource "spi/Kconfig"
rsource "watchdog/Kconfig"
rsource "audio/Kconfig"
rsource "sensor/Kconfig"
rsource "touch/Kconfig"
rsource "graphic/Kconfig"
rsource "hwcrypto/Kconfig"
rsource "wlan/Kconfig"
rsource "virtio/Kconfig"
rsource "ofw/Kconfig"
rsource "pic/Kconfig"
rsource "pin/Kconfig"
rsource "pinctrl/Kconfig"
rsource "ktime/Kconfig"
rsource "clk/Kconfig"
rsource "hwtimer/Kconfig"
rsource "usb/Kconfig"
endmenu

14
rt-thread/components/drivers/SConscript Normal file
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# for module compiling
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

17
rt-thread/components/drivers/audio/Kconfig Normal file
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config RT_USING_AUDIO
bool "Using Audio device drivers"
default n
if RT_USING_AUDIO
config RT_AUDIO_REPLAY_MP_BLOCK_SIZE
int "Replay memory pool block size"
default 4096
config RT_AUDIO_REPLAY_MP_BLOCK_COUNT
int "Replay memory pool block count"
default 2
config RT_AUDIO_RECORD_PIPE_SIZE
int "Record pipe size"
default 2048
endif

9
rt-thread/components/drivers/audio/SConscript Normal file
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from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_AUDIO'], CPPPATH = CPPPATH)
Return('group')

612
rt-thread/components/drivers/audio/audio.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-05-09 Urey first version
* 2019-07-09 Zero-Free improve device ops interface and data flows
*/
#include <stdio.h>
#include <string.h>
#include <rthw.h>
#include <rtdevice.h>
#define DBG_TAG "audio"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#ifndef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#endif
enum
{
REPLAY_EVT_NONE = 0x00,
REPLAY_EVT_START = 0x01,
REPLAY_EVT_STOP = 0x02,
};
static rt_err_t _audio_send_replay_frame(struct rt_audio_device *audio)
{
rt_err_t result = RT_EOK;
rt_uint8_t *data;
rt_size_t dst_size, src_size;
rt_uint16_t position, remain_bytes = 0, index = 0;
struct rt_audio_buf_info *buf_info;
RT_ASSERT(audio != RT_NULL);
buf_info = &audio->replay->buf_info;
/* save current pos */
position = audio->replay->pos;
dst_size = buf_info->block_size;
/* check replay queue is empty */
if (rt_data_queue_peek(&audio->replay->queue, (const void **)&data, &src_size) != RT_EOK)
{
/* ack stop event */
if (audio->replay->event & REPLAY_EVT_STOP)
rt_completion_done(&audio->replay->cmp);
/* send zero frames */
rt_memset(&buf_info->buffer[audio->replay->pos], 0, dst_size);
audio->replay->pos += dst_size;
audio->replay->pos %= buf_info->total_size;
}
else
{
rt_memset(&buf_info->buffer[audio->replay->pos], 0, dst_size);
/* copy data from memory pool to hardware device fifo */
while (index < dst_size)
{
result = rt_data_queue_peek(&audio->replay->queue, (const void **)&data, &src_size);
if (result != RT_EOK)
{
LOG_D("under run %d, remain %d", audio->replay->pos, remain_bytes);
audio->replay->pos -= remain_bytes;
audio->replay->pos += dst_size;
audio->replay->pos %= buf_info->total_size;
audio->replay->read_index = 0;
result = -RT_EEMPTY;
break;
}
remain_bytes = MIN((dst_size - index), (src_size - audio->replay->read_index));
rt_memcpy(&buf_info->buffer[audio->replay->pos],
&data[audio->replay->read_index], remain_bytes);
index += remain_bytes;
audio->replay->read_index += remain_bytes;
audio->replay->pos += remain_bytes;
audio->replay->pos %= buf_info->total_size;
if (audio->replay->read_index == src_size)
{
/* free memory */
audio->replay->read_index = 0;
rt_data_queue_pop(&audio->replay->queue, (const void **)&data, &src_size, RT_WAITING_NO);
rt_mp_free(data);
/* notify transmitted complete. */
if (audio->parent.tx_complete != RT_NULL)
audio->parent.tx_complete(&audio->parent, (void *)data);
}
}
}
if (audio->ops->transmit != RT_NULL)
{
if (audio->ops->transmit(audio, &buf_info->buffer[position], RT_NULL, dst_size) != dst_size)
result = -RT_ERROR;
}
return result;
}
static rt_err_t _audio_flush_replay_frame(struct rt_audio_device *audio)
{
rt_err_t result = RT_EOK;
if (audio->replay->write_index)
{
result = rt_data_queue_push(&audio->replay->queue,
(const void **)audio->replay->write_data,
audio->replay->write_index,
RT_WAITING_FOREVER);
audio->replay->write_index = 0;
}
return result;
}
static rt_err_t _aduio_replay_start(struct rt_audio_device *audio)
{
rt_err_t result = RT_EOK;
if (audio->replay->activated != RT_TRUE)
{
/* start playback hardware device */
if (audio->ops->start)
result = audio->ops->start(audio, AUDIO_STREAM_REPLAY);
audio->replay->activated = RT_TRUE;
LOG_D("start audio replay device");
}
return result;
}
static rt_err_t _aduio_replay_stop(struct rt_audio_device *audio)
{
rt_err_t result = RT_EOK;
if (audio->replay->activated == RT_TRUE)
{
/* flush replay remian frames */
_audio_flush_replay_frame(audio);
/* notify irq(or thread) to stop the data transmission */
audio->replay->event |= REPLAY_EVT_STOP;
/* waiting for the remaining data transfer to complete */
rt_completion_init(&audio->replay->cmp);
rt_completion_wait(&audio->replay->cmp, RT_WAITING_FOREVER);
audio->replay->event &= ~REPLAY_EVT_STOP;
/* stop playback hardware device */
if (audio->ops->stop)
result = audio->ops->stop(audio, AUDIO_STREAM_REPLAY);
audio->replay->activated = RT_FALSE;
LOG_D("stop audio replay device");
}
return result;
}
static rt_err_t _audio_record_start(struct rt_audio_device *audio)
{
rt_err_t result = RT_EOK;
if (audio->record->activated != RT_TRUE)
{
/* open audio record pipe */
rt_device_open(RT_DEVICE(&audio->record->pipe), RT_DEVICE_OFLAG_RDONLY);
/* start record hardware device */
if (audio->ops->start)
result = audio->ops->start(audio, AUDIO_STREAM_RECORD);
audio->record->activated = RT_TRUE;
LOG_D("start audio record device");
}
return result;
}
static rt_err_t _audio_record_stop(struct rt_audio_device *audio)
{
rt_err_t result = RT_EOK;
if (audio->record->activated == RT_TRUE)
{
/* stop record hardware device */
if (audio->ops->stop)
result = audio->ops->stop(audio, AUDIO_STREAM_RECORD);
/* close audio record pipe */
rt_device_close(RT_DEVICE(&audio->record->pipe));
audio->record->activated = RT_FALSE;
LOG_D("stop audio record device");
}
return result;
}
static rt_err_t _audio_dev_init(struct rt_device *dev)
{
rt_err_t result = RT_EOK;
struct rt_audio_device *audio;
RT_ASSERT(dev != RT_NULL);
audio = (struct rt_audio_device *) dev;
/* initialize replay & record */
audio->replay = RT_NULL;
audio->record = RT_NULL;
/* initialize replay */
if (dev->flag & RT_DEVICE_FLAG_WRONLY)
{
struct rt_audio_replay *replay = (struct rt_audio_replay *) rt_malloc(sizeof(struct rt_audio_replay));
if (replay == RT_NULL)
return -RT_ENOMEM;
rt_memset(replay, 0, sizeof(struct rt_audio_replay));
/* init memory pool for replay */
replay->mp = rt_mp_create("adu_mp", RT_AUDIO_REPLAY_MP_BLOCK_COUNT, RT_AUDIO_REPLAY_MP_BLOCK_SIZE);
if (replay->mp == RT_NULL)
{
rt_free(replay);
LOG_E("create memory pool for replay failed");
return -RT_ENOMEM;
}
/* init queue for audio replay */
rt_data_queue_init(&replay->queue, CFG_AUDIO_REPLAY_QUEUE_COUNT, 0, RT_NULL);
/* init mutex lock for audio replay */
rt_mutex_init(&replay->lock, "replay", RT_IPC_FLAG_PRIO);
replay->activated = RT_FALSE;
audio->replay = replay;
}
/* initialize record */
if (dev->flag & RT_DEVICE_FLAG_RDONLY)
{
struct rt_audio_record *record = (struct rt_audio_record *) rt_malloc(sizeof(struct rt_audio_record));
rt_uint8_t *buffer;
if (record == RT_NULL)
return -RT_ENOMEM;
rt_memset(record, 0, sizeof(struct rt_audio_record));
/* init pipe for record*/
buffer = rt_malloc(RT_AUDIO_RECORD_PIPE_SIZE);
if (buffer == RT_NULL)
{
rt_free(record);
LOG_E("malloc memory for for record pipe failed");
return -RT_ENOMEM;
}
rt_audio_pipe_init(&record->pipe, "record",
(rt_int32_t)(RT_PIPE_FLAG_FORCE_WR | RT_PIPE_FLAG_BLOCK_RD),
buffer,
RT_AUDIO_RECORD_PIPE_SIZE);
record->activated = RT_FALSE;
audio->record = record;
}
/* initialize hardware configuration */
if (audio->ops->init)
audio->ops->init(audio);
/* get replay buffer information */
if (audio->ops->buffer_info)
audio->ops->buffer_info(audio, &audio->replay->buf_info);
return result;
}
static rt_err_t _audio_dev_open(struct rt_device *dev, rt_uint16_t oflag)
{
struct rt_audio_device *audio;
RT_ASSERT(dev != RT_NULL);
audio = (struct rt_audio_device *) dev;
/* check device flag with the open flag */
if ((oflag & RT_DEVICE_OFLAG_RDONLY) && !(dev->flag & RT_DEVICE_FLAG_RDONLY))
return -RT_EIO;
if ((oflag & RT_DEVICE_OFLAG_WRONLY) && !(dev->flag & RT_DEVICE_FLAG_WRONLY))
return -RT_EIO;
/* get open flags */
dev->open_flag = oflag & 0xff;
/* initialize the Rx/Tx structure according to open flag */
if (oflag & RT_DEVICE_OFLAG_WRONLY)
{
if (audio->replay->activated != RT_TRUE)
{
LOG_D("open audio replay device, oflag = %x\n", oflag);
audio->replay->write_index = 0;
audio->replay->read_index = 0;
audio->replay->pos = 0;
audio->replay->event = REPLAY_EVT_NONE;
}
dev->open_flag |= RT_DEVICE_OFLAG_WRONLY;
}
if (oflag & RT_DEVICE_OFLAG_RDONLY)
{
/* open record pipe */
if (audio->record->activated != RT_TRUE)
{
LOG_D("open audio record device ,oflag = %x\n", oflag);
_audio_record_start(audio);
audio->record->activated = RT_TRUE;
}
dev->open_flag |= RT_DEVICE_OFLAG_RDONLY;
}
return RT_EOK;
}
static rt_err_t _audio_dev_close(struct rt_device *dev)
{
struct rt_audio_device *audio;
RT_ASSERT(dev != RT_NULL);
audio = (struct rt_audio_device *) dev;
if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY)
{
/* stop replay stream */
_aduio_replay_stop(audio);
dev->open_flag &= ~RT_DEVICE_OFLAG_WRONLY;
}
if (dev->open_flag & RT_DEVICE_OFLAG_RDONLY)
{
/* stop record stream */
_audio_record_stop(audio);
dev->open_flag &= ~RT_DEVICE_OFLAG_RDONLY;
}
return RT_EOK;
}
static rt_ssize_t _audio_dev_read(struct rt_device *dev, rt_off_t pos, void *buffer, rt_size_t size)
{
struct rt_audio_device *audio;
RT_ASSERT(dev != RT_NULL);
audio = (struct rt_audio_device *) dev;
if (!(dev->open_flag & RT_DEVICE_OFLAG_RDONLY) || (audio->record == RT_NULL))
return 0;
return rt_device_read(RT_DEVICE(&audio->record->pipe), pos, buffer, size);
}
static rt_ssize_t _audio_dev_write(struct rt_device *dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
struct rt_audio_device *audio;
rt_uint8_t *ptr;
rt_uint16_t block_size, remain_bytes, index = 0;
RT_ASSERT(dev != RT_NULL);
audio = (struct rt_audio_device *) dev;
if (!(dev->open_flag & RT_DEVICE_OFLAG_WRONLY) || (audio->replay == RT_NULL))
return 0;
/* push a new frame to replay data queue */
ptr = (rt_uint8_t *)buffer;
block_size = RT_AUDIO_REPLAY_MP_BLOCK_SIZE;
rt_mutex_take(&audio->replay->lock, RT_WAITING_FOREVER);
while (index < size)
{
/* request buffer from replay memory pool */
if (audio->replay->write_index % block_size == 0)
{
audio->replay->write_data = rt_mp_alloc(audio->replay->mp, RT_WAITING_FOREVER);
rt_memset(audio->replay->write_data, 0, block_size);
}
/* copy data to replay memory pool */
remain_bytes = MIN((block_size - audio->replay->write_index), (size - index));
rt_memcpy(&audio->replay->write_data[audio->replay->write_index], &ptr[index], remain_bytes);
index += remain_bytes;
audio->replay->write_index += remain_bytes;
audio->replay->write_index %= block_size;
if (audio->replay->write_index == 0)
{
rt_data_queue_push(&audio->replay->queue,
audio->replay->write_data,
block_size,
RT_WAITING_FOREVER);
}
}
rt_mutex_release(&audio->replay->lock);
/* check replay state */
if (audio->replay->activated != RT_TRUE)
{
_aduio_replay_start(audio);
audio->replay->activated = RT_TRUE;
}
return index;
}
static rt_err_t _audio_dev_control(struct rt_device *dev, int cmd, void *args)
{
rt_err_t result = RT_EOK;
struct rt_audio_device *audio;
RT_ASSERT(dev != RT_NULL);
audio = (struct rt_audio_device *) dev;
/* dev stat...*/
switch (cmd)
{
case AUDIO_CTL_GETCAPS:
{
struct rt_audio_caps *caps = (struct rt_audio_caps *) args;
LOG_D("AUDIO_CTL_GETCAPS: main_type = %d,sub_type = %d", caps->main_type, caps->sub_type);
if (audio->ops->getcaps != RT_NULL)
{
result = audio->ops->getcaps(audio, caps);
}
break;
}
case AUDIO_CTL_CONFIGURE:
{
struct rt_audio_caps *caps = (struct rt_audio_caps *) args;
LOG_D("AUDIO_CTL_CONFIGURE: main_type = %d,sub_type = %d", caps->main_type, caps->sub_type);
if (audio->ops->configure != RT_NULL)
{
result = audio->ops->configure(audio, caps);
}
break;
}
case AUDIO_CTL_START:
{
int stream = *(int *) args;
LOG_D("AUDIO_CTL_START: stream = %d", stream);
if (stream == AUDIO_STREAM_REPLAY)
{
result = _aduio_replay_start(audio);
}
else
{
result = _audio_record_start(audio);
}
break;
}
case AUDIO_CTL_STOP:
{
int stream = *(int *) args;
LOG_D("AUDIO_CTL_STOP: stream = %d", stream);
if (stream == AUDIO_STREAM_REPLAY)
{
result = _aduio_replay_stop(audio);
}
else
{
result = _audio_record_stop(audio);
}
break;
}
default:
break;
}
return result;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops audio_ops =
{
_audio_dev_init,
_audio_dev_open,
_audio_dev_close,
_audio_dev_read,
_audio_dev_write,
_audio_dev_control
};
#endif
rt_err_t rt_audio_register(struct rt_audio_device *audio, const char *name, rt_uint32_t flag, void *data)
{
rt_err_t result = RT_EOK;
struct rt_device *device;
RT_ASSERT(audio != RT_NULL);
device = &(audio->parent);
device->type = RT_Device_Class_Sound;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
#ifdef RT_USING_DEVICE_OPS
device->ops = &audio_ops;
#else
device->init = _audio_dev_init;
device->open = _audio_dev_open;
device->close = _audio_dev_close;
device->read = _audio_dev_read;
device->write = _audio_dev_write;
device->control = _audio_dev_control;
#endif
device->user_data = data;
/* register a character device */
result = rt_device_register(device, name, flag | RT_DEVICE_FLAG_REMOVABLE);
/* initialize audio device */
if (result == RT_EOK)
result = rt_device_init(device);
return result;
}
int rt_audio_samplerate_to_speed(rt_uint32_t bitValue)
{
int speed = 0;
switch (bitValue)
{
case AUDIO_SAMP_RATE_8K:
speed = 8000;
break;
case AUDIO_SAMP_RATE_11K:
speed = 11052;
break;
case AUDIO_SAMP_RATE_16K:
speed = 16000;
break;
case AUDIO_SAMP_RATE_22K:
speed = 22050;
break;
case AUDIO_SAMP_RATE_32K:
speed = 32000;
break;
case AUDIO_SAMP_RATE_44K:
speed = 44100;
break;
case AUDIO_SAMP_RATE_48K:
speed = 48000;
break;
case AUDIO_SAMP_RATE_96K:
speed = 96000;
break;
case AUDIO_SAMP_RATE_128K:
speed = 128000;
break;
case AUDIO_SAMP_RATE_160K:
speed = 160000;
break;
case AUDIO_SAMP_RATE_172K:
speed = 176400;
break;
case AUDIO_SAMP_RATE_192K:
speed = 192000;
break;
default:
break;
}
return speed;
}
void rt_audio_tx_complete(struct rt_audio_device *audio)
{
/* try to send next frame */
_audio_send_replay_frame(audio);
}
void rt_audio_rx_done(struct rt_audio_device *audio, rt_uint8_t *pbuf, rt_size_t len)
{
/* save data to record pipe */
rt_device_write(RT_DEVICE(&audio->record->pipe), 0, pbuf, len);
/* invoke callback */
if (audio->parent.rx_indicate != RT_NULL)
audio->parent.rx_indicate(&audio->parent, len);
}

296
rt-thread/components/drivers/audio/audio_pipe.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-09-30 Bernard first version.
*/
#include <rthw.h>
#include <rtdevice.h>
#include "audio_pipe.h"
static void _rt_pipe_resume_writer(struct rt_audio_pipe *pipe)
{
if (!rt_list_isempty(&pipe->suspended_write_list))
{
rt_thread_t thread;
RT_ASSERT(pipe->flag & RT_PIPE_FLAG_BLOCK_WR);
/* get suspended thread */
thread = RT_THREAD_LIST_NODE_ENTRY(pipe->suspended_write_list.next);
/* resume the write thread */
rt_thread_resume(thread);
rt_schedule();
}
}
static rt_ssize_t rt_pipe_read(rt_device_t dev,
rt_off_t pos,
void *buffer,
rt_size_t size)
{
rt_base_t level;
rt_thread_t thread;
struct rt_audio_pipe *pipe;
rt_size_t read_nbytes;
pipe = (struct rt_audio_pipe *)dev;
RT_ASSERT(pipe != RT_NULL);
if (!(pipe->flag & RT_PIPE_FLAG_BLOCK_RD))
{
level = rt_hw_interrupt_disable();
read_nbytes = rt_ringbuffer_get(&(pipe->ringbuffer), (rt_uint8_t *)buffer, size);
/* if the ringbuffer is empty, there won't be any writer waiting */
if (read_nbytes)
_rt_pipe_resume_writer(pipe);
rt_hw_interrupt_enable(level);
return read_nbytes;
}
thread = rt_thread_self();
/* current context checking */
RT_DEBUG_NOT_IN_INTERRUPT;
do
{
level = rt_hw_interrupt_disable();
read_nbytes = rt_ringbuffer_get(&(pipe->ringbuffer), (rt_uint8_t *)buffer, size);
if (read_nbytes == 0)
{
rt_thread_suspend(thread);
/* waiting on suspended read list */
rt_list_insert_before(&(pipe->suspended_read_list),
&RT_THREAD_LIST_NODE(thread));
rt_hw_interrupt_enable(level);
rt_schedule();
}
else
{
_rt_pipe_resume_writer(pipe);
rt_hw_interrupt_enable(level);
break;
}
}
while (read_nbytes == 0);
return read_nbytes;
}
static void _rt_pipe_resume_reader(struct rt_audio_pipe *pipe)
{
if (pipe->parent.rx_indicate)
pipe->parent.rx_indicate(&pipe->parent,
rt_ringbuffer_data_len(&pipe->ringbuffer));
if (!rt_list_isempty(&pipe->suspended_read_list))
{
rt_thread_t thread;
RT_ASSERT(pipe->flag & RT_PIPE_FLAG_BLOCK_RD);
/* get suspended thread */
thread = RT_THREAD_LIST_NODE_ENTRY(pipe->suspended_read_list.next);
/* resume the read thread */
rt_thread_resume(thread);
rt_schedule();
}
}
static rt_ssize_t rt_pipe_write(rt_device_t dev,
rt_off_t pos,
const void *buffer,
rt_size_t size)
{
rt_base_t level;
rt_thread_t thread;
struct rt_audio_pipe *pipe;
rt_size_t write_nbytes;
pipe = (struct rt_audio_pipe *)dev;
RT_ASSERT(pipe != RT_NULL);
if ((pipe->flag & RT_PIPE_FLAG_FORCE_WR) ||
!(pipe->flag & RT_PIPE_FLAG_BLOCK_WR))
{
level = rt_hw_interrupt_disable();
if (pipe->flag & RT_PIPE_FLAG_FORCE_WR)
write_nbytes = rt_ringbuffer_put_force(&(pipe->ringbuffer),
(const rt_uint8_t *)buffer, size);
else
write_nbytes = rt_ringbuffer_put(&(pipe->ringbuffer),
(const rt_uint8_t *)buffer, size);
_rt_pipe_resume_reader(pipe);
rt_hw_interrupt_enable(level);
return write_nbytes;
}
thread = rt_thread_self();
/* current context checking */
RT_DEBUG_NOT_IN_INTERRUPT;
do
{
level = rt_hw_interrupt_disable();
write_nbytes = rt_ringbuffer_put(&(pipe->ringbuffer), (const rt_uint8_t *)buffer, size);
if (write_nbytes == 0)
{
/* pipe full, waiting on suspended write list */
rt_thread_suspend(thread);
/* waiting on suspended read list */
rt_list_insert_before(&(pipe->suspended_write_list),
&RT_THREAD_LIST_NODE(thread));
rt_hw_interrupt_enable(level);
rt_schedule();
}
else
{
_rt_pipe_resume_reader(pipe);
rt_hw_interrupt_enable(level);
break;
}
}
while (write_nbytes == 0);
return write_nbytes;
}
static rt_err_t rt_pipe_control(rt_device_t dev, int cmd, void *args)
{
struct rt_audio_pipe *pipe;
pipe = (struct rt_audio_pipe *)dev;
if (cmd == PIPE_CTRL_GET_SPACE && args)
*(rt_size_t *)args = rt_ringbuffer_space_len(&pipe->ringbuffer);
return RT_EOK;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops audio_pipe_ops =
{
RT_NULL,
RT_NULL,
RT_NULL,
rt_pipe_read,
rt_pipe_write,
rt_pipe_control
};
#endif
/**
* This function will initialize a pipe device and put it under control of
* resource management.
*
* @param pipe the pipe device
* @param name the name of pipe device
* @param flag the attribute of the pipe device
* @param buf the buffer of pipe device
* @param size the size of pipe device buffer
*
* @return the operation status, RT_EOK on successful
*/
rt_err_t rt_audio_pipe_init(struct rt_audio_pipe *pipe,
const char *name,
rt_int32_t flag,
rt_uint8_t *buf,
rt_size_t size)
{
RT_ASSERT(pipe);
RT_ASSERT(buf);
/* initialize suspended list */
rt_list_init(&pipe->suspended_read_list);
rt_list_init(&pipe->suspended_write_list);
/* initialize ring buffer */
rt_ringbuffer_init(&pipe->ringbuffer, buf, size);
pipe->flag = flag;
/* create pipe */
pipe->parent.type = RT_Device_Class_Pipe;
#ifdef RT_USING_DEVICE_OPS
pipe->parent.ops = &audio_pipe_ops;
#else
pipe->parent.init = RT_NULL;
pipe->parent.open = RT_NULL;
pipe->parent.close = RT_NULL;
pipe->parent.read = rt_pipe_read;
pipe->parent.write = rt_pipe_write;
pipe->parent.control = rt_pipe_control;
#endif
return rt_device_register(&(pipe->parent), name, RT_DEVICE_FLAG_RDWR);
}
/**
* This function will detach a pipe device from resource management
*
* @param pipe the pipe device
*
* @return the operation status, RT_EOK on successful
*/
rt_err_t rt_audio_pipe_detach(struct rt_audio_pipe *pipe)
{
return rt_device_unregister(&pipe->parent);
}
#ifdef RT_USING_HEAP
rt_err_t rt_audio_pipe_create(const char *name, rt_int32_t flag, rt_size_t size)
{
rt_uint8_t *rb_memptr = RT_NULL;
struct rt_audio_pipe *pipe = RT_NULL;
/* get aligned size */
size = RT_ALIGN(size, RT_ALIGN_SIZE);
pipe = (struct rt_audio_pipe *)rt_calloc(1, sizeof(struct rt_audio_pipe));
if (pipe == RT_NULL)
return -RT_ENOMEM;
/* create ring buffer of pipe */
rb_memptr = (rt_uint8_t *)rt_malloc(size);
if (rb_memptr == RT_NULL)
{
rt_free(pipe);
return -RT_ENOMEM;
}
return rt_audio_pipe_init(pipe, name, flag, rb_memptr, size);
}
void rt_audio_pipe_destroy(struct rt_audio_pipe *pipe)
{
if (pipe == RT_NULL)
return;
/* un-register pipe device */
rt_audio_pipe_detach(pipe);
/* release memory */
rt_free(pipe->ringbuffer.buffer_ptr);
rt_free(pipe);
return;
}
#endif /* RT_USING_HEAP */

75
rt-thread/components/drivers/audio/audio_pipe.h Normal file
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@@ -0,0 +1,75 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __AUDIO_PIPE_H__
#define __AUDIO_PIPE_H__
/**
* Pipe Device
*/
#include <rtdevice.h>
#ifndef RT_PIPE_BUFSZ
#define PIPE_BUFSZ 512
#else
#define PIPE_BUFSZ RT_PIPE_BUFSZ
#endif
/* portal device */
struct rt_audio_portal_device
{
struct rt_device parent;
struct rt_device *write_dev;
struct rt_device *read_dev;
};
enum rt_audio_pipe_flag
{
/* both read and write won't block */
RT_PIPE_FLAG_NONBLOCK_RDWR = 0x00,
/* read would block */
RT_PIPE_FLAG_BLOCK_RD = 0x01,
/* write would block */
RT_PIPE_FLAG_BLOCK_WR = 0x02,
/* write to this pipe will discard some data when the pipe is full.
* When this flag is set, RT_PIPE_FLAG_BLOCK_WR will be ignored since write
* operation will always be success. */
RT_PIPE_FLAG_FORCE_WR = 0x04,
};
struct rt_audio_pipe
{
struct rt_device parent;
/* ring buffer in pipe device */
struct rt_ringbuffer ringbuffer;
rt_int32_t flag;
/* suspended list */
rt_list_t suspended_read_list;
rt_list_t suspended_write_list;
struct rt_audio_portal_device *write_portal;
struct rt_audio_portal_device *read_portal;
};
#define PIPE_CTRL_GET_SPACE 0x14 /**< get the remaining size of a pipe device */
rt_err_t rt_audio_pipe_init(struct rt_audio_pipe *pipe,
const char *name,
rt_int32_t flag,
rt_uint8_t *buf,
rt_size_t size);
rt_err_t rt_audio_pipe_detach(struct rt_audio_pipe *pipe);
#ifdef RT_USING_HEAP
rt_err_t rt_audio_pipe_create(const char *name, rt_int32_t flag, rt_size_t size);
void rt_audio_pipe_destroy(struct rt_audio_pipe *pipe);
#endif /* RT_USING_HEAP */
#endif /* __AUDIO_PIPE_H__ */

12
rt-thread/components/drivers/can/Kconfig Normal file
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@@ -0,0 +1,12 @@
config RT_USING_CAN
bool "Using CAN device drivers"
default n
if RT_USING_CAN
config RT_CAN_USING_HDR
bool "Enable CAN hardware filter"
default n
config RT_CAN_USING_CANFD
bool "Enable CANFD support"
default n
endif

8
rt-thread/components/drivers/can/SConscript Normal file
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@@ -0,0 +1,8 @@
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd + '/../include']
group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_CAN'], CPPPATH = CPPPATH)
Return('group')

974
rt-thread/components/drivers/can/can.c Normal file
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@@ -0,0 +1,974 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2015-05-14 aubrcool@qq.com first version
* 2015-07-06 Bernard code cleanup and remove RT_CAN_USING_LED;
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#define CAN_LOCK(can) rt_mutex_take(&(can->lock), RT_WAITING_FOREVER)
#define CAN_UNLOCK(can) rt_mutex_release(&(can->lock))
static rt_err_t rt_can_init(struct rt_device *dev)
{
rt_err_t result = RT_EOK;
struct rt_can_device *can;
RT_ASSERT(dev != RT_NULL);
can = (struct rt_can_device *)dev;
/* initialize rx/tx */
can->can_rx = RT_NULL;
can->can_tx = RT_NULL;
#ifdef RT_CAN_USING_HDR
can->hdr = RT_NULL;
#endif
/* apply configuration */
if (can->ops->configure)
result = can->ops->configure(can, &can->config);
else
result = -RT_ENOSYS;
return result;
}
/*
* can interrupt routines
*/
rt_inline rt_ssize_t _can_int_rx(struct rt_can_device *can, struct rt_can_msg *data, rt_ssize_t msgs)
{
rt_ssize_t size;
struct rt_can_rx_fifo *rx_fifo;
RT_ASSERT(can != RT_NULL);
size = msgs;
rx_fifo = (struct rt_can_rx_fifo *) can->can_rx;
RT_ASSERT(rx_fifo != RT_NULL);
/* read from software FIFO */
while (msgs / sizeof(struct rt_can_msg) > 0)
{
rt_base_t level;
#ifdef RT_CAN_USING_HDR
rt_int8_t hdr;
#endif /*RT_CAN_USING_HDR*/
struct rt_can_msg_list *listmsg = RT_NULL;
/* disable interrupt */
level = rt_hw_interrupt_disable();
#ifdef RT_CAN_USING_HDR
hdr = data->hdr_index;
if (hdr >= 0 && can->hdr && hdr < can->config.maxhdr && !rt_list_isempty(&can->hdr[hdr].list))
{
listmsg = rt_list_entry(can->hdr[hdr].list.next, struct rt_can_msg_list, hdrlist);
rt_list_remove(&listmsg->list);
rt_list_remove(&listmsg->hdrlist);
if (can->hdr[hdr].msgs)
{
can->hdr[hdr].msgs--;
}
listmsg->owner = RT_NULL;
}
else if (hdr == -1)
#endif /*RT_CAN_USING_HDR*/
{
if (!rt_list_isempty(&rx_fifo->uselist))
{
listmsg = rt_list_entry(rx_fifo->uselist.next, struct rt_can_msg_list, list);
rt_list_remove(&listmsg->list);
#ifdef RT_CAN_USING_HDR
rt_list_remove(&listmsg->hdrlist);
if (listmsg->owner != RT_NULL && listmsg->owner->msgs)
{
listmsg->owner->msgs--;
}
listmsg->owner = RT_NULL;
#endif /*RT_CAN_USING_HDR*/
}
else
{
/* no data, enable interrupt and break out */
rt_hw_interrupt_enable(level);
break;
}
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
if (listmsg != RT_NULL)
{
rt_memcpy(data, &listmsg->data, sizeof(struct rt_can_msg));
level = rt_hw_interrupt_disable();
rt_list_insert_before(&rx_fifo->freelist, &listmsg->list);
rx_fifo->freenumbers++;
RT_ASSERT(rx_fifo->freenumbers <= can->config.msgboxsz);
rt_hw_interrupt_enable(level);
listmsg = RT_NULL;
}
else
{
break;
}
data ++;
msgs -= sizeof(struct rt_can_msg);
}
return (size - msgs);
}
rt_inline int _can_int_tx(struct rt_can_device *can, const struct rt_can_msg *data, int msgs)
{
int size;
struct rt_can_tx_fifo *tx_fifo;
RT_ASSERT(can != RT_NULL);
size = msgs;
tx_fifo = (struct rt_can_tx_fifo *) can->can_tx;
RT_ASSERT(tx_fifo != RT_NULL);
while (msgs)
{
rt_base_t level;
rt_uint32_t no;
rt_uint32_t result;
struct rt_can_sndbxinx_list *tx_tosnd = RT_NULL;
rt_sem_take(&(tx_fifo->sem), RT_WAITING_FOREVER);
level = rt_hw_interrupt_disable();
tx_tosnd = rt_list_entry(tx_fifo->freelist.next, struct rt_can_sndbxinx_list, list);
RT_ASSERT(tx_tosnd != RT_NULL);
rt_list_remove(&tx_tosnd->list);
rt_hw_interrupt_enable(level);
no = ((rt_ubase_t)tx_tosnd - (rt_ubase_t)tx_fifo->buffer) / sizeof(struct rt_can_sndbxinx_list);
tx_tosnd->result = RT_CAN_SND_RESULT_WAIT;
rt_completion_init(&tx_tosnd->completion);
if (can->ops->sendmsg(can, data, no) != RT_EOK)
{
/* send failed. */
level = rt_hw_interrupt_disable();
rt_list_insert_before(&tx_fifo->freelist, &tx_tosnd->list);
rt_hw_interrupt_enable(level);
rt_sem_release(&(tx_fifo->sem));
goto err_ret;
}
can->status.sndchange = 1;
rt_completion_wait(&(tx_tosnd->completion), RT_WAITING_FOREVER);
level = rt_hw_interrupt_disable();
result = tx_tosnd->result;
if (!rt_list_isempty(&tx_tosnd->list))
{
rt_list_remove(&tx_tosnd->list);
}
rt_list_insert_before(&tx_fifo->freelist, &tx_tosnd->list);
rt_hw_interrupt_enable(level);
rt_sem_release(&(tx_fifo->sem));
if (result == RT_CAN_SND_RESULT_OK)
{
level = rt_hw_interrupt_disable();
can->status.sndpkg++;
rt_hw_interrupt_enable(level);
data ++;
msgs -= sizeof(struct rt_can_msg);
if (!msgs) break;
}
else
{
err_ret:
level = rt_hw_interrupt_disable();
can->status.dropedsndpkg++;
rt_hw_interrupt_enable(level);
break;
}
}
return (size - msgs);
}
rt_inline int _can_int_tx_priv(struct rt_can_device *can, const struct rt_can_msg *data, int msgs)
{
int size;
rt_base_t level;
rt_uint32_t no, result;
struct rt_can_tx_fifo *tx_fifo;
RT_ASSERT(can != RT_NULL);
size = msgs;
tx_fifo = (struct rt_can_tx_fifo *) can->can_tx;
RT_ASSERT(tx_fifo != RT_NULL);
while (msgs)
{
no = data->priv;
if (no >= can->config.sndboxnumber)
{
break;
}
level = rt_hw_interrupt_disable();
if ((tx_fifo->buffer[no].result != RT_CAN_SND_RESULT_OK))
{
rt_hw_interrupt_enable(level);
rt_completion_wait(&(tx_fifo->buffer[no].completion), RT_WAITING_FOREVER);
continue;
}
tx_fifo->buffer[no].result = RT_CAN_SND_RESULT_WAIT;
rt_hw_interrupt_enable(level);
if (can->ops->sendmsg(can, data, no) != RT_EOK)
{
continue;
}
can->status.sndchange = 1;
rt_completion_wait(&(tx_fifo->buffer[no].completion), RT_WAITING_FOREVER);
result = tx_fifo->buffer[no].result;
if (result == RT_CAN_SND_RESULT_OK)
{
level = rt_hw_interrupt_disable();
can->status.sndpkg++;
rt_hw_interrupt_enable(level);
data ++;
msgs -= sizeof(struct rt_can_msg);
if (!msgs) break;
}
else
{
level = rt_hw_interrupt_disable();
can->status.dropedsndpkg++;
rt_hw_interrupt_enable(level);
break;
}
}
return (size - msgs);
}
static rt_err_t rt_can_open(struct rt_device *dev, rt_uint16_t oflag)
{
struct rt_can_device *can;
char tmpname[16];
RT_ASSERT(dev != RT_NULL);
can = (struct rt_can_device *)dev;
CAN_LOCK(can);
/* get open flags */
dev->open_flag = oflag & 0xff;
if (can->can_rx == RT_NULL)
{
if (oflag & RT_DEVICE_FLAG_INT_RX)
{
int i = 0;
struct rt_can_rx_fifo *rx_fifo;
rx_fifo = (struct rt_can_rx_fifo *) rt_malloc(sizeof(struct rt_can_rx_fifo) +
can->config.msgboxsz * sizeof(struct rt_can_msg_list));
RT_ASSERT(rx_fifo != RT_NULL);
rx_fifo->buffer = (struct rt_can_msg_list *)(rx_fifo + 1);
rt_memset(rx_fifo->buffer, 0, can->config.msgboxsz * sizeof(struct rt_can_msg_list));
rt_list_init(&rx_fifo->freelist);
rt_list_init(&rx_fifo->uselist);
rx_fifo->freenumbers = can->config.msgboxsz;
for (i = 0; i < can->config.msgboxsz; i++)
{
rt_list_insert_before(&rx_fifo->freelist, &rx_fifo->buffer[i].list);
#ifdef RT_CAN_USING_HDR
rt_list_init(&rx_fifo->buffer[i].hdrlist);
rx_fifo->buffer[i].owner = RT_NULL;
#endif
}
can->can_rx = rx_fifo;
dev->open_flag |= RT_DEVICE_FLAG_INT_RX;
/* open can rx interrupt */
can->ops->control(can, RT_DEVICE_CTRL_SET_INT, (void *)RT_DEVICE_FLAG_INT_RX);
}
}
if (can->can_tx == RT_NULL)
{
if (oflag & RT_DEVICE_FLAG_INT_TX)
{
int i = 0;
struct rt_can_tx_fifo *tx_fifo;
tx_fifo = (struct rt_can_tx_fifo *) rt_malloc(sizeof(struct rt_can_tx_fifo) +
can->config.sndboxnumber * sizeof(struct rt_can_sndbxinx_list));
RT_ASSERT(tx_fifo != RT_NULL);
tx_fifo->buffer = (struct rt_can_sndbxinx_list *)(tx_fifo + 1);
rt_memset(tx_fifo->buffer, 0,
can->config.sndboxnumber * sizeof(struct rt_can_sndbxinx_list));
rt_list_init(&tx_fifo->freelist);
for (i = 0; i < can->config.sndboxnumber; i++)
{
rt_list_insert_before(&tx_fifo->freelist, &tx_fifo->buffer[i].list);
rt_completion_init(&(tx_fifo->buffer[i].completion));
tx_fifo->buffer[i].result = RT_CAN_SND_RESULT_OK;
}
rt_sprintf(tmpname, "%stl", dev->parent.name);
rt_sem_init(&(tx_fifo->sem), tmpname, can->config.sndboxnumber, RT_IPC_FLAG_FIFO);
can->can_tx = tx_fifo;
dev->open_flag |= RT_DEVICE_FLAG_INT_TX;
/* open can tx interrupt */
can->ops->control(can, RT_DEVICE_CTRL_SET_INT, (void *)RT_DEVICE_FLAG_INT_TX);
}
}
can->ops->control(can, RT_DEVICE_CTRL_SET_INT, (void *)RT_DEVICE_CAN_INT_ERR);
#ifdef RT_CAN_USING_HDR
if (can->hdr == RT_NULL)
{
int i = 0;
struct rt_can_hdr *phdr;
phdr = (struct rt_can_hdr *) rt_malloc(can->config.maxhdr * sizeof(struct rt_can_hdr));
RT_ASSERT(phdr != RT_NULL);
rt_memset(phdr, 0, can->config.maxhdr * sizeof(struct rt_can_hdr));
for (i = 0; i < can->config.maxhdr; i++)
{
rt_list_init(&phdr[i].list);
}
can->hdr = phdr;
}
#endif
if (!can->timerinitflag)
{
can->timerinitflag = 1;
rt_timer_start(&can->timer);
}
CAN_UNLOCK(can);
return RT_EOK;
}
static rt_err_t rt_can_close(struct rt_device *dev)
{
struct rt_can_device *can;
RT_ASSERT(dev != RT_NULL);
can = (struct rt_can_device *)dev;
CAN_LOCK(can);
/* this device has more reference count */
if (dev->ref_count > 1)
{
CAN_UNLOCK(can);
return RT_EOK;
}
if (can->timerinitflag)
{
can->timerinitflag = 0;
rt_timer_stop(&can->timer);
}
can->status_indicate.ind = RT_NULL;
can->status_indicate.args = RT_NULL;
#ifdef RT_CAN_USING_HDR
if (can->hdr != RT_NULL)
{
rt_free(can->hdr);
can->hdr = RT_NULL;
}
#endif
if (dev->open_flag & RT_DEVICE_FLAG_INT_RX)
{
struct rt_can_rx_fifo *rx_fifo;
/* clear can rx interrupt */
can->ops->control(can, RT_DEVICE_CTRL_CLR_INT, (void *)RT_DEVICE_FLAG_INT_RX);
rx_fifo = (struct rt_can_rx_fifo *)can->can_rx;
RT_ASSERT(rx_fifo != RT_NULL);
rt_free(rx_fifo);
dev->open_flag &= ~RT_DEVICE_FLAG_INT_RX;
can->can_rx = RT_NULL;
}
if (dev->open_flag & RT_DEVICE_FLAG_INT_TX)
{
struct rt_can_tx_fifo *tx_fifo;
/* clear can tx interrupt */
can->ops->control(can, RT_DEVICE_CTRL_CLR_INT, (void *)RT_DEVICE_FLAG_INT_TX);
tx_fifo = (struct rt_can_tx_fifo *)can->can_tx;
RT_ASSERT(tx_fifo != RT_NULL);
rt_sem_detach(&(tx_fifo->sem));
rt_free(tx_fifo);
dev->open_flag &= ~RT_DEVICE_FLAG_INT_TX;
can->can_tx = RT_NULL;
}
can->ops->control(can, RT_DEVICE_CTRL_CLR_INT, (void *)RT_DEVICE_CAN_INT_ERR);
CAN_UNLOCK(can);
return RT_EOK;
}
static rt_ssize_t rt_can_read(struct rt_device *dev,
rt_off_t pos,
void *buffer,
rt_size_t size)
{
struct rt_can_device *can;
RT_ASSERT(dev != RT_NULL);
if (size == 0) return 0;
can = (struct rt_can_device *)dev;
if ((dev->open_flag & RT_DEVICE_FLAG_INT_RX) && (dev->ref_count > 0))
{
return _can_int_rx(can, buffer, size);
}
return 0;
}
static rt_ssize_t rt_can_write(struct rt_device *dev,
rt_off_t pos,
const void *buffer,
rt_size_t size)
{
struct rt_can_device *can;
RT_ASSERT(dev != RT_NULL);
if (size == 0) return 0;
can = (struct rt_can_device *)dev;
if ((dev->open_flag & RT_DEVICE_FLAG_INT_TX) && (dev->ref_count > 0))
{
if (can->config.privmode)
{
return _can_int_tx_priv(can, buffer, size);
}
else
{
return _can_int_tx(can, buffer, size);
}
}
return 0;
}
static rt_err_t rt_can_control(struct rt_device *dev,
int cmd,
void *args)
{
struct rt_can_device *can;
rt_err_t res;
res = RT_EOK;
RT_ASSERT(dev != RT_NULL);
can = (struct rt_can_device *)dev;
switch (cmd)
{
case RT_DEVICE_CTRL_SUSPEND:
/* suspend device */
dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
break;
case RT_DEVICE_CTRL_RESUME:
/* resume device */
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
break;
case RT_DEVICE_CTRL_CONFIG:
/* configure device */
res = can->ops->configure(can, (struct can_configure *)args);
break;
case RT_CAN_CMD_SET_PRIV:
/* configure device */
if ((rt_uint32_t)(rt_ubase_t)args != can->config.privmode)
{
int i;
rt_base_t level;
struct rt_can_tx_fifo *tx_fifo;
res = can->ops->control(can, cmd, args);
if (res != RT_EOK) return res;
tx_fifo = (struct rt_can_tx_fifo *) can->can_tx;
if (can->config.privmode)
{
for (i = 0; i < can->config.sndboxnumber; i++)
{
level = rt_hw_interrupt_disable();
if(rt_list_isempty(&tx_fifo->buffer[i].list))
{
rt_sem_release(&(tx_fifo->sem));
}
else
{
rt_list_remove(&tx_fifo->buffer[i].list);
}
rt_hw_interrupt_enable(level);
}
}
else
{
for (i = 0; i < can->config.sndboxnumber; i++)
{
level = rt_hw_interrupt_disable();
if (tx_fifo->buffer[i].result == RT_CAN_SND_RESULT_OK)
{
rt_list_insert_before(&tx_fifo->freelist, &tx_fifo->buffer[i].list);
}
rt_hw_interrupt_enable(level);
}
}
}
break;
case RT_CAN_CMD_SET_STATUS_IND:
can->status_indicate.ind = ((rt_can_status_ind_type_t)args)->ind;
can->status_indicate.args = ((rt_can_status_ind_type_t)args)->args;
break;
#ifdef RT_CAN_USING_HDR
case RT_CAN_CMD_SET_FILTER:
res = can->ops->control(can, cmd, args);
if (res != RT_EOK || can->hdr == RT_NULL)
{
return res;
}
struct rt_can_filter_config *pfilter;
struct rt_can_filter_item *pitem;
rt_uint32_t count;
rt_base_t level;
pfilter = (struct rt_can_filter_config *)args;
RT_ASSERT(pfilter);
count = pfilter->count;
pitem = pfilter->items;
if (pfilter->actived)
{
while (count)
{
if (pitem->hdr_bank >= can->config.maxhdr || pitem->hdr_bank < 0)
{
count--;
pitem++;
continue;
}
level = rt_hw_interrupt_disable();
if (!can->hdr[pitem->hdr_bank].connected)
{
rt_hw_interrupt_enable(level);
rt_memcpy(&can->hdr[pitem->hdr_bank].filter, pitem,
sizeof(struct rt_can_filter_item));
level = rt_hw_interrupt_disable();
can->hdr[pitem->hdr_bank].connected = 1;
can->hdr[pitem->hdr_bank].msgs = 0;
rt_list_init(&can->hdr[pitem->hdr_bank].list);
}
rt_hw_interrupt_enable(level);
count--;
pitem++;
}
}
else
{
while (count)
{
if (pitem->hdr_bank >= can->config.maxhdr || pitem->hdr_bank < 0)
{
count--;
pitem++;
continue;
}
level = rt_hw_interrupt_disable();
if (can->hdr[pitem->hdr_bank].connected)
{
can->hdr[pitem->hdr_bank].connected = 0;
can->hdr[pitem->hdr_bank].msgs = 0;
if (!rt_list_isempty(&can->hdr[pitem->hdr_bank].list))
{
rt_list_remove(can->hdr[pitem->hdr_bank].list.next);
}
rt_hw_interrupt_enable(level);
rt_memset(&can->hdr[pitem->hdr_bank].filter, 0,
sizeof(struct rt_can_filter_item));
}
else
{
rt_hw_interrupt_enable(level);
}
count--;
pitem++;
}
}
break;
#endif /*RT_CAN_USING_HDR*/
#ifdef RT_CAN_USING_BUS_HOOK
case RT_CAN_CMD_SET_BUS_HOOK:
can->bus_hook = (rt_can_bus_hook) args;
break;
#endif /*RT_CAN_USING_BUS_HOOK*/
default :
/* control device */
if (can->ops->control != RT_NULL)
{
res = can->ops->control(can, cmd, args);
}
else
{
res = -RT_ENOSYS;
}
break;
}
return res;
}
/*
* can timer
*/
static void cantimeout(void *arg)
{
rt_can_t can;
can = (rt_can_t)arg;
RT_ASSERT(can);
rt_device_control((rt_device_t)can, RT_CAN_CMD_GET_STATUS, (void *)&can->status);
if (can->status_indicate.ind != RT_NULL)
{
can->status_indicate.ind(can, can->status_indicate.args);
}
#ifdef RT_CAN_USING_BUS_HOOK
if(can->bus_hook)
{
can->bus_hook(can);
}
#endif /*RT_CAN_USING_BUS_HOOK*/
if (can->timerinitflag == 1)
{
can->timerinitflag = 0xFF;
}
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops can_device_ops =
{
rt_can_init,
rt_can_open,
rt_can_close,
rt_can_read,
rt_can_write,
rt_can_control
};
#endif
/*
* can register
*/
rt_err_t rt_hw_can_register(struct rt_can_device *can,
const char *name,
const struct rt_can_ops *ops,
void *data)
{
struct rt_device *device;
RT_ASSERT(can != RT_NULL);
device = &(can->parent);
device->type = RT_Device_Class_CAN;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
#ifdef RT_CAN_USING_HDR
can->hdr = RT_NULL;
#endif
can->can_rx = RT_NULL;
can->can_tx = RT_NULL;
rt_mutex_init(&(can->lock), "can", RT_IPC_FLAG_PRIO);
#ifdef RT_CAN_USING_BUS_HOOK
can->bus_hook = RT_NULL;
#endif /*RT_CAN_USING_BUS_HOOK*/
#ifdef RT_USING_DEVICE_OPS
device->ops = &can_device_ops;
#else
device->init = rt_can_init;
device->open = rt_can_open;
device->close = rt_can_close;
device->read = rt_can_read;
device->write = rt_can_write;
device->control = rt_can_control;
#endif
can->ops = ops;
can->status_indicate.ind = RT_NULL;
can->status_indicate.args = RT_NULL;
rt_memset(&can->status, 0, sizeof(can->status));
device->user_data = data;
can->timerinitflag = 0;
rt_timer_init(&can->timer,
name,
cantimeout,
(void *)can,
can->config.ticks,
RT_TIMER_FLAG_PERIODIC);
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR);
}
/* ISR for can interrupt */
void rt_hw_can_isr(struct rt_can_device *can, int event)
{
switch (event & 0xff)
{
case RT_CAN_EVENT_RXOF_IND:
{
rt_base_t level;
level = rt_hw_interrupt_disable();
can->status.dropedrcvpkg++;
rt_hw_interrupt_enable(level);
}
case RT_CAN_EVENT_RX_IND:
{
struct rt_can_msg tmpmsg;
struct rt_can_rx_fifo *rx_fifo;
struct rt_can_msg_list *listmsg = RT_NULL;
#ifdef RT_CAN_USING_HDR
rt_int8_t hdr;
#endif
int ch = -1;
rt_base_t level;
rt_uint32_t no;
rx_fifo = (struct rt_can_rx_fifo *)can->can_rx;
RT_ASSERT(rx_fifo != RT_NULL);
/* interrupt mode receive */
RT_ASSERT(can->parent.open_flag & RT_DEVICE_FLAG_INT_RX);
no = event >> 8;
ch = can->ops->recvmsg(can, &tmpmsg, no);
if (ch == -1) break;
/* disable interrupt */
level = rt_hw_interrupt_disable();
can->status.rcvpkg++;
can->status.rcvchange = 1;
if (!rt_list_isempty(&rx_fifo->freelist))
{
listmsg = rt_list_entry(rx_fifo->freelist.next, struct rt_can_msg_list, list);
rt_list_remove(&listmsg->list);
#ifdef RT_CAN_USING_HDR
rt_list_remove(&listmsg->hdrlist);
if (listmsg->owner != RT_NULL && listmsg->owner->msgs)
{
listmsg->owner->msgs--;
}
listmsg->owner = RT_NULL;
#endif /*RT_CAN_USING_HDR*/
RT_ASSERT(rx_fifo->freenumbers > 0);
rx_fifo->freenumbers--;
}
else if (!rt_list_isempty(&rx_fifo->uselist))
{
listmsg = rt_list_entry(rx_fifo->uselist.next, struct rt_can_msg_list, list);
can->status.dropedrcvpkg++;
rt_list_remove(&listmsg->list);
#ifdef RT_CAN_USING_HDR
rt_list_remove(&listmsg->hdrlist);
if (listmsg->owner != RT_NULL && listmsg->owner->msgs)
{
listmsg->owner->msgs--;
}
listmsg->owner = RT_NULL;
#endif
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
if (listmsg != RT_NULL)
{
rt_memcpy(&listmsg->data, &tmpmsg, sizeof(struct rt_can_msg));
level = rt_hw_interrupt_disable();
rt_list_insert_before(&rx_fifo->uselist, &listmsg->list);
#ifdef RT_CAN_USING_HDR
hdr = tmpmsg.hdr_index;
if (can->hdr != RT_NULL)
{
RT_ASSERT(hdr < can->config.maxhdr && hdr >= 0);
if (can->hdr[hdr].connected)
{
rt_list_insert_before(&can->hdr[hdr].list, &listmsg->hdrlist);
listmsg->owner = &can->hdr[hdr];
can->hdr[hdr].msgs++;
}
}
#endif
rt_hw_interrupt_enable(level);
}
/* invoke callback */
#ifdef RT_CAN_USING_HDR
if (can->hdr != RT_NULL && can->hdr[hdr].connected && can->hdr[hdr].filter.ind)
{
rt_size_t rx_length;
RT_ASSERT(hdr < can->config.maxhdr && hdr >= 0);
level = rt_hw_interrupt_disable();
rx_length = can->hdr[hdr].msgs * sizeof(struct rt_can_msg);
rt_hw_interrupt_enable(level);
if (rx_length)
{
can->hdr[hdr].filter.ind(&can->parent, can->hdr[hdr].filter.args, hdr, rx_length);
}
}
else
#endif
{
if (can->parent.rx_indicate != RT_NULL)
{
rt_size_t rx_length;
level = rt_hw_interrupt_disable();
/* get rx length */
rx_length = rt_list_len(&rx_fifo->uselist)* sizeof(struct rt_can_msg);
rt_hw_interrupt_enable(level);
if (rx_length)
{
can->parent.rx_indicate(&can->parent, rx_length);
}
}
}
break;
}
case RT_CAN_EVENT_TX_DONE:
case RT_CAN_EVENT_TX_FAIL:
{
struct rt_can_tx_fifo *tx_fifo;
rt_uint32_t no;
no = event >> 8;
tx_fifo = (struct rt_can_tx_fifo *) can->can_tx;
RT_ASSERT(tx_fifo != RT_NULL);
if ((event & 0xff) == RT_CAN_EVENT_TX_DONE)
{
tx_fifo->buffer[no].result = RT_CAN_SND_RESULT_OK;
}
else
{
tx_fifo->buffer[no].result = RT_CAN_SND_RESULT_ERR;
}
rt_completion_done(&(tx_fifo->buffer[no].completion));
break;
}
}
}
#ifdef RT_USING_FINSH
#include <finsh.h>
int cmd_canstat(int argc, void **argv)
{
static const char *ErrCode[] =
{
"No Error!",
"Warning !",
"Passive !",
"Bus Off !"
};
if (argc >= 2)
{
struct rt_can_status status;
rt_device_t candev = rt_device_find(argv[1]);
if (!candev)
{
rt_kprintf(" Can't find can device %s\n", argv[1]);
return -1;
}
rt_kprintf(" Found can device: %s...", argv[1]);
rt_device_control(candev, RT_CAN_CMD_GET_STATUS, &status);
rt_kprintf("\n Receive...error..count: %010ld. Send.....error....count: %010ld.",
status.rcverrcnt, status.snderrcnt);
rt_kprintf("\n Bit..pad..error..count: %010ld. Format...error....count: %010ld",
status.bitpaderrcnt, status.formaterrcnt);
rt_kprintf("\n Ack.......error..count: %010ld. Bit......error....count: %010ld.",
status.ackerrcnt, status.biterrcnt);
rt_kprintf("\n CRC.......error..count: %010ld. Error.code.[%010ld]: ",
status.crcerrcnt, status.errcode);
switch (status.errcode)
{
case 0:
rt_kprintf("%s.", ErrCode[0]);
break;
case 1:
rt_kprintf("%s.", ErrCode[1]);
break;
case 2:
case 3:
rt_kprintf("%s.", ErrCode[2]);
break;
case 4:
case 5:
case 6:
case 7:
rt_kprintf("%s.", ErrCode[3]);
break;
}
rt_kprintf("\n Total.receive.packages: %010ld. Dropped.receive.packages: %010ld.",
status.rcvpkg, status.dropedrcvpkg);
rt_kprintf("\n Total..send...packages: %010ld. Dropped...send..packages: %010ld.\n",
status.sndpkg + status.dropedsndpkg, status.dropedsndpkg);
}
else
{
rt_kprintf(" Invalid Call %s\n", argv[0]);
rt_kprintf(" Please using %s cannamex .Here canname is driver name and x is candrive number.\n", argv[0]);
}
return 0;
}
MSH_CMD_EXPORT_ALIAS(cmd_canstat, canstat, stat can device status);
#endif

132
rt-thread/components/drivers/can/readme-zh.txt Normal file
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说明:
本驱动完成了can控制器硬件抽象
一 CAN Driver 注册
Can driver注册需要填充以下几个数据结构：
1、struct can_configure
{
rt_uint32_t baud_rate;
rt_uint32_t msgboxsz;
rt_uint32_t sndboxnumber;
rt_uint32_t mode :8;
rt_uint32_t privmode :8;
rt_uint32_t reserved :16;
#ifdef RT_CAN_USING_LED
const struct rt_can_led* rcvled;
const struct rt_can_led* sndled;
const struct rt_can_led* errled;
#endif /*RT_CAN_USING_LED*/
rt_uint32_t ticks;
#ifdef RT_CAN_USING_HDR
rt_uint32_t maxhdr;
#endif
};
struct can_configure 为can驱动的基本配置信息:
baud_rate :
enum CANBAUD
{
CAN1MBaud=0, // 1 MBit/sec
CAN800kBaud, // 800 kBit/sec
CAN500kBaud, // 500 kBit/sec
CAN250kBaud, // 250 kBit/sec
CAN125kBaud, // 125 kBit/sec
CAN100kBaud, // 100 kBit/sec
CAN50kBaud, // 50 kBit/sec
CAN20kBaud, // 20 kBit/sec
CAN10kBaud // 10 kBit/sec
};
配置Can的波特率。
msgboxsz : Can接收邮箱缓冲数量，本驱动在软件层开辟msgboxsz个接收邮箱。
sndboxnumber : can 发送通道数量，该配置为Can控制器实际的发送通道数量。
mode ：
#define RT_CAN_MODE_NORMAL 0 正常模式
#define RT_CAN_MODE_LISEN 1 只听模式
#define RT_CAN_MODE_LOOPBACK 2 自发自收模式
#define RT_CAN_MODE_LOOPBACKANLISEN 3 自发自收只听模式
配置Can 的工作状态。
privmode :
#define RT_CAN_MODE_PRIV 0x01 处于优先级模式，高优先级的消息优先发送。
#define RT_CAN_MODE_NOPRIV 0x00
配置Can driver的优先级模式。
#ifdef RT_CAN_USING_LED
const struct rt_can_led* rcvled;
const struct rt_can_led* sndled;
const struct rt_can_led* errled;
#endif /*RT_CAN_USING_LED*/
配置can led信息, 当前can驱动的led使用了 pin驱动，
开启RT_CAN_USING_LED时要确保当前系统已实现pin驱动。
rt_uint32_t ticks : 配置Can driver timer周期。
#ifdef RT_CAN_USING_HDR
rt_uint32_t maxhdr;
#endif
如果使用硬件过滤，则开启RT_CAN_USING_HDR, maxhdr 为Can控制器过滤表的数量。
2、struct rt_can_ops
{
rt_err_t (*configure)(struct rt_can_device *can, struct can_configure *cfg);
rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg);
int (*sendmsg)(struct rt_can_device *can, const void* buf, rt_uint32_t boxno);
int (*recvmsg)(struct rt_can_device *can,void* buf, rt_uint32_t boxno);
};
struct rt_can_ops 为要实现的特定的can控制器操作。
rt_err_t (*configure)(struct rt_can_device *can, struct can_configure *cfg);
configure根据配置信息初始化Can控制器工作模式。
rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg);
control 当前接受以下cmd参数：
#define RT_CAN_CMD_SET_FILTER 0x13
#define RT_CAN_CMD_SET_BAUD 0x14
#define RT_CAN_CMD_SET_MODE 0x15
#define RT_CAN_CMD_SET_PRIV 0x16
#define RT_CAN_CMD_GET_STATUS 0x17
#define RT_CAN_CMD_SET_STATUS_IND 0x18
int (*sendmsg)(struct rt_can_device *can, const void* buf, rt_uint32_t boxno);
sendmsg向Can控制器发送数，boxno为发送通道号。
int (*recvmsg)(struct rt_can_device *can,void* buf, rt_uint32_t boxno);
recvmsg从Can控制器接收数据，boxno为接收通道号。
struct rt_can_device
{
struct rt_device parent;
const struct rt_can_ops *ops;
struct can_configure config;
struct rt_can_status status;
rt_uint32_t timerinitflag;
struct rt_timer timer;
struct rt_can_status_ind_type status_indicate;
#ifdef RT_CAN_USING_HDR
struct rt_can_hdr* hdr;
#endif
void *can_rx;
void *can_tx;
};
填充完成后，便可调用rt_hw_can_register完成can驱动的注册。
二、 CAN Driver 的添加：
要添加一个新的Can驱动，至少要完成以下接口。
1、struct rt_can_ops
{
rt_err_t (*configure)(struct rt_can_device *can, struct can_configure *cfg);
rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg);
int (*sendmsg)(struct rt_can_device *can, const void* buf, rt_uint32_t boxno);
int (*recvmsg)(struct rt_can_device *can,void* buf, rt_uint32_t boxno);
};
2、 rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg);
接口的
#define RT_CAN_CMD_SET_FILTER 0x13
#define RT_CAN_CMD_SET_BAUD 0x14
#define RT_CAN_CMD_SET_MODE 0x15
#define RT_CAN_CMD_SET_PRIV 0x16
#define RT_CAN_CMD_GET_STATUS 0x17
#define RT_CAN_CMD_SET_STATUS_IND 0x18
若干命令。
3、can口中断，要完接收，发送结束，以及错误中断。
#define RT_CAN_EVENT_RX_IND 0x01 /* Rx indication */
#define RT_CAN_EVENT_TX_DONE 0x02 /* Tx complete */
#define RT_CAN_EVENT_TX_FAIL 0x03 /* Tx complete */
#define RT_CAN_EVENT_RX_TIMEOUT 0x05 /* Rx timeout */
#define RT_CAN_EVENT_RXOF_IND 0x06 /* Rx overflow */
中断产生后，调用rt_hw_can_isr(struct rt_can_device *can, int event)
进入相应的操作，其中接收发送中断的event，最低8位为上面的事件，16到24位为通信通道号。
一个作为一个例子，参见bsp/stm32f10x/driver下的bxcan.c 。
三、CAN Driver的使用：
一个使用的例子，参数bsp/stm32f10x/applications下的canapp.c
四、当前Can驱动，没有实现轮模式，采用中断模式，bxcan驱动工作在loopback模式下的时候不能读数据。
五、当前Can驱动，在stm32f105上测试，暂无问题。

5
rt-thread/components/drivers/clk/Kconfig Normal file
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@@ -0,0 +1,5 @@
menuconfig RT_USING_CLK
bool "Using Common Clock Framework (CLK)"
depends on RT_USING_DM
select RT_USING_ADT_REF
default y

26
rt-thread/components/drivers/clk/SConscript Normal file
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@@ -0,0 +1,26 @@
from building import *
group = []
objs = []
if not GetDepend(['RT_USING_CLK']):
Return('group')
cwd = GetCurrentDir()
list = os.listdir(cwd)
CPPPATH = [cwd + '/../include']
src = ['clk.c']
if GetDepend(['RT_USING_OFW']):
src += ['clk-fixed-rate.c']
group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
objs = objs + group
Return('objs')

92
rt-thread/components/drivers/clk/clk-fixed-rate.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-11-26 GuEe-GUI first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <drivers/platform.h>
static rt_err_t fixed_clk_ofw_init(struct rt_platform_device *pdev, struct rt_clk_fixed_rate *clk_fixed)
{
rt_err_t err = RT_EOK;
rt_uint32_t rate, accuracy;
struct rt_ofw_node *np = pdev->parent.ofw_node;
const char *clk_name = np->name;
if (!rt_ofw_prop_read_u32(np, "clock-frequency", &rate))
{
rt_ofw_prop_read_u32(np, "clock-accuracy", &accuracy);
rt_ofw_prop_read_string(np, "clock-output-names", &clk_name);
clk_fixed->clk.name = clk_name;
clk_fixed->clk.rate = rate;
clk_fixed->clk.min_rate = rate;
clk_fixed->clk.max_rate = rate;
clk_fixed->fixed_rate = rate;
clk_fixed->fixed_accuracy = accuracy;
rt_ofw_data(np) = &clk_fixed->clk;
}
else
{
err = -RT_EIO;
}
return err;
}
static rt_err_t fixed_clk_probe(struct rt_platform_device *pdev)
{
rt_err_t err = RT_EOK;
struct rt_clk_fixed_rate *clk_fixed = rt_calloc(1, sizeof(*clk_fixed));
if (clk_fixed)
{
err = fixed_clk_ofw_init(pdev, clk_fixed);
}
else
{
err = -RT_ENOMEM;
}
if (!err)
{
err = rt_clk_register(&clk_fixed->clk, RT_NULL);
}
if (err && clk_fixed)
{
rt_free(clk_fixed);
}
return err;
}
static const struct rt_ofw_node_id fixed_clk_ofw_ids[] =
{
{ .compatible = "fixed-clock" },
{ /* sentinel */ }
};
static struct rt_platform_driver fixed_clk_driver =
{
.name = "clk-fixed-rate",
.ids = fixed_clk_ofw_ids,
.probe = fixed_clk_probe,
};
static int fixed_clk_drv_register(void)
{
rt_platform_driver_register(&fixed_clk_driver);
return 0;
}
INIT_SUBSYS_EXPORT(fixed_clk_drv_register);

1078
rt-thread/components/drivers/clk/clk.c Normal file
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File diff suppressed because it is too large Load Diff

11
rt-thread/components/drivers/core/Kconfig Normal file
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@@ -0,0 +1,11 @@
config RT_USING_DM
bool "Enable device driver model with device tree"
default n
help
Enable device driver model with device tree (FDT). It will use more memory
to parse and support device tree feature.
config RT_USING_DEV_BUS
bool "Using Device Bus device drivers"
default y if RT_USING_SMART
default n

21
rt-thread/components/drivers/core/SConscript Normal file
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@@ -0,0 +1,21 @@
from building import *
cwd = GetCurrentDir()
src = ['device.c']
CPPPATH = [cwd + '/../include']
if GetDepend(['RT_USING_DEV_BUS']) or GetDepend(['RT_USING_DM']):
src = src + ['bus.c']
if GetDepend(['RT_USING_DM']):
src = src + ['dm.c', 'driver.c', 'numa.c', 'platform.c', 'power_domain.c']
if GetDepend(['RT_USING_DFS']):
src += ['mnt.c'];
if GetDepend(['RT_USING_OFW']):
src += ['platform_ofw.c']
group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_DEVICE'], CPPPATH = CPPPATH)
Return('group')

520
rt-thread/components/drivers/core/bus.c Normal file
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@@ -0,0 +1,520 @@
/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-13 flybreak the first version
* 2023-04-12 ErikChan support rt_bus
*/
#include <rtthread.h>
#include <string.h>
#include <stdlib.h>
#define DBG_TAG "dev_bus"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#ifdef RT_USING_DEV_BUS
#if defined(RT_USING_POSIX_DEVIO)
#include <unistd.h>
#include <fcntl.h>
#include <poll.h>
#include <sys/ioctl.h>
#include <dfs_file.h>
static int bus_fops_open(struct dfs_file *fd)
{
LOG_D("bus fops open");
return 0;
}
static int bus_fops_close(struct dfs_file *fd)
{
LOG_D("bus fops close");
return 0;
}
static const struct dfs_file_ops bus_fops =
{
bus_fops_open,
bus_fops_close,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
};
#endif
rt_device_t rt_device_bus_create(char *name, int attach_size)
{
rt_err_t result = RT_EOK;
rt_device_t dev = rt_device_create(RT_Device_Class_Bus, 0);
result = rt_device_register(dev, name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE);
if (result < 0)
{
rt_kprintf("dev bus [%s] register failed!, ret=%d\n", name, result);
return RT_NULL;
}
#if defined(RT_USING_POSIX_DEVIO)
dev->fops = &bus_fops;
#endif
LOG_D("bus create");
return dev;
}
rt_err_t rt_device_bus_destroy(rt_device_t dev)
{
rt_device_unregister(dev);
dev->parent.type = RT_Object_Class_Device;
rt_device_destroy(dev);
LOG_D("bus destroy");
return RT_EOK;
}
#endif
#ifdef RT_USING_DM
#include <drivers/core/bus.h>
static struct rt_spinlock bus_lock = {};
static rt_list_t bus_nodes = RT_LIST_OBJECT_INIT(bus_nodes);
static void _dm_bus_lock(struct rt_spinlock *spinlock)
{
rt_hw_spin_lock(&spinlock->lock);
}
static void _dm_bus_unlock(struct rt_spinlock *spinlock)
{
rt_hw_spin_unlock(&spinlock->lock);
}
/**
* @brief This function loop the dev_list of the bus, and call fn in each loop
*
* @param bus the target bus
*
* @param data the data push when call fn
*
* @param fn the function callback in each loop
*
* @return the error code, RT_EOK on added successfully.
*/
rt_err_t rt_bus_for_each_dev(rt_bus_t bus, void *data, int (*fn)(rt_device_t dev, void *))
{
rt_device_t dev;
rt_err_t err = -RT_EEMPTY;
rt_list_t *dev_list;
struct rt_spinlock *dev_lock;
RT_ASSERT(bus != RT_NULL);
dev_list = &bus->dev_list;
dev_lock = &bus->dev_lock;
_dm_bus_lock(dev_lock);
dev = rt_list_entry(dev_list->next, struct rt_device, node);
_dm_bus_unlock(dev_lock);
while (&dev->node != dev_list)
{
if (!fn(dev, data))
{
err = RT_EOK;
break;
}
_dm_bus_lock(dev_lock);
dev = rt_list_entry(dev->node.next, struct rt_device, node);
_dm_bus_unlock(dev_lock);
}
return err;
}
/**
* @brief This function loop the drv_list of the bus, and call fn in each loop
*
* @param bus the target bus
*
* @param data the data push when call fn
*
* @param fn the function callback in each loop
*
* @return the error code, RT_EOK on added successfully.
*/
rt_err_t rt_bus_for_each_drv(rt_bus_t bus, void *data, int (*fn)(rt_driver_t drv, void *))
{
rt_driver_t drv;
rt_err_t err = -RT_EEMPTY;
rt_list_t *drv_list;
struct rt_spinlock *drv_lock;
RT_ASSERT(bus != RT_NULL);
drv_list = &bus->drv_list;
drv_lock = &bus->drv_lock;
_dm_bus_lock(drv_lock);
drv = rt_list_entry(drv_list->next, struct rt_driver, node);
_dm_bus_unlock(drv_lock);
while (&drv->node != drv_list)
{
if (!fn(drv, data))
{
err = RT_EOK;
break;
}
_dm_bus_lock(drv_lock);
drv = rt_list_entry(drv->node.next, struct rt_driver, node);
_dm_bus_unlock(drv_lock);
}
return err;
}
static rt_err_t bus_probe(rt_driver_t drv, rt_device_t dev)
{
rt_bus_t bus = drv->bus;
rt_err_t err = -RT_EEMPTY;
if (!bus)
{
bus = dev->bus;
}
if (!dev->drv && bus->match(drv, dev))
{
dev->drv = drv;
err = bus->probe(dev);
if (err)
{
dev->drv = RT_NULL;
}
}
return err;
}
static int bus_probe_driver(rt_device_t dev, void *drv_ptr)
{
bus_probe(drv_ptr, dev);
/*
* The driver is shared by multiple devices,
* so we always return the '1' to enumerate all devices.
*/
return 1;
}
static int bus_probe_device(rt_driver_t drv, void *dev_ptr)
{
rt_err_t err;
err = bus_probe(drv, dev_ptr);
if (!err)
{
rt_bus_t bus = drv->bus;
_dm_bus_lock(&bus->drv_lock);
++drv->ref_count;
_dm_bus_unlock(&bus->drv_lock);
}
return err;
}
/**
* @brief This function add a driver to the drv_list of a specific bus
*
* @param bus the bus to add
*
* @param drv the driver to be added
*
* @return the error code, RT_EOK on added successfully.
*/
rt_err_t rt_bus_add_driver(rt_bus_t bus, rt_driver_t drv)
{
RT_ASSERT(bus != RT_NULL);
RT_ASSERT(drv != RT_NULL);
drv->bus = bus;
rt_list_init(&drv->node);
_dm_bus_lock(&bus->drv_lock);
rt_list_insert_before(&bus->drv_list, &drv->node);
_dm_bus_unlock(&bus->drv_lock);
rt_bus_for_each_dev(bus, drv, bus_probe_driver);
return RT_EOK;
}
/**
* @brief This function add a device to the dev_list of a specific bus
*
* @param bus the bus to add
*
* @param dev the device to be added
*
* @return the error code, RT_EOK on added successfully.
*/
rt_err_t rt_bus_add_device(rt_bus_t bus, rt_device_t dev)
{
RT_ASSERT(bus != RT_NULL);
RT_ASSERT(dev != RT_NULL);
dev->bus = bus;
rt_list_init(&dev->node);
_dm_bus_lock(&bus->dev_lock);
rt_list_insert_before(&bus->dev_list, &dev->node);
_dm_bus_unlock(&bus->dev_lock);
rt_bus_for_each_drv(bus, dev, bus_probe_device);
return RT_EOK;
}
/**
* @brief This function remove a driver from bus
*
* @param drv the driver to be removed
*
* @return the error code, RT_EOK on added successfully.
*/
rt_err_t rt_bus_remove_driver(rt_driver_t drv)
{
rt_err_t err;
rt_bus_t bus;
RT_ASSERT(drv != RT_NULL);
RT_ASSERT(drv->bus != RT_NULL);
bus = drv->bus;
LOG_D("Bus(%s) remove driver %s", bus->name, drv->parent.name);
_dm_bus_lock(&bus->drv_lock);
if (drv->ref_count)
{
err = -RT_EBUSY;
}
else
{
rt_list_remove(&drv->node);
err = RT_EOK;
}
_dm_bus_unlock(&bus->drv_lock);
return err;
}
/**
* @brief This function remove a device from bus
*
* @param dev the device to be removed
*
* @return the error code, RT_EOK on added successfully.
*/
rt_err_t rt_bus_remove_device(rt_device_t dev)
{
rt_bus_t bus;
rt_driver_t drv;
rt_err_t err = RT_EOK;
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(dev->bus != RT_NULL);
bus = dev->bus;
drv = dev->drv;
LOG_D("Bus(%s) remove device %s", bus->name, dev->parent.name);
_dm_bus_lock(&bus->dev_lock);
rt_list_remove(&dev->node);
_dm_bus_unlock(&bus->dev_lock);
if (dev->bus->remove)
{
err = dev->bus->remove(dev);
}
else if (drv)
{
if (drv->shutdown)
{
err = drv->shutdown(dev);
}
/* device and driver are in the same bus */
_dm_bus_lock(&bus->drv_lock);
--drv->ref_count;
_dm_bus_unlock(&bus->drv_lock);
}
return err;
}
struct bus_shutdown_info
{
rt_bus_t bus;
rt_err_t err;
};
static int device_shutdown(rt_device_t dev, void *info_ptr)
{
rt_bus_t bus;
rt_err_t err = RT_EOK;
struct bus_shutdown_info *info = info_ptr;
bus = info->bus;
if (bus->shutdown)
{
LOG_D("Device(%s) shutdown", dev->parent.name);
err = bus->shutdown(dev);
LOG_D(" Result: %s", rt_strerror(err));
}
else if (dev->drv && dev->drv->shutdown)
{
LOG_D("Device(%s) shutdown", dev->parent.name);
err = dev->drv->shutdown(dev);
LOG_D(" Result: %s", rt_strerror(err));
}
if (err)
{
/* Only get the last one while system not crash */
info->err = err;
}
/* Go on, we want to ask all devices to shutdown */
return 1;
}
/**
* @brief This function call all buses' shutdown
*
* @return the error code, RT_EOK on shutdown successfully.
*/
rt_err_t rt_bus_shutdown(void)
{
rt_bus_t bus = RT_NULL;
struct bus_shutdown_info info =
{
.err = RT_EOK,
};
_dm_bus_lock(&bus_lock);
rt_list_for_each_entry(bus, &bus_nodes, list)
{
info.bus = bus;
rt_bus_for_each_dev(bus, &info, device_shutdown);
}
_dm_bus_unlock(&bus_lock);
return info.err;
}
/**
* @brief This function find a bus by name
* @param bus the name to be finded
*
* @return the bus finded by name.
*/
rt_bus_t rt_bus_find_by_name(const char *name)
{
rt_bus_t bus = RT_NULL;
RT_ASSERT(name != RT_NULL);
_dm_bus_lock(&bus_lock);
rt_list_for_each_entry(bus, &bus_nodes, list)
{
if (!rt_strncmp(bus->name, name, RT_NAME_MAX))
{
break;
}
}
_dm_bus_unlock(&bus_lock);
return bus;
}
/**
* @brief This function transfer dev_list and drv_list to the other bus
*
* @param new_bus the bus to transfer
*
* @param dev the target device
*
* @return the error code, RT_EOK on added successfully.
*/
rt_err_t rt_bus_reload_driver_device(rt_bus_t new_bus, rt_device_t dev)
{
rt_bus_t old_bus;
RT_ASSERT(new_bus != RT_NULL);
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(dev->bus != RT_NULL);
RT_ASSERT(dev->bus != new_bus);
old_bus = dev->bus;
_dm_bus_lock(&old_bus->dev_lock);
rt_list_remove(&dev->node);
_dm_bus_unlock(&old_bus->dev_lock);
return rt_bus_add_device(new_bus, dev);
}
/**
* @brief This function register a bus
* @param bus the bus to be registered
*
* @return the error code, RT_EOK on registeration successfully.
*/
rt_err_t rt_bus_register(rt_bus_t bus)
{
RT_ASSERT(bus != RT_NULL);
rt_list_init(&bus->list);
rt_list_init(&bus->dev_list);
rt_list_init(&bus->drv_list);
rt_spin_lock_init(&bus->dev_lock);
rt_spin_lock_init(&bus->drv_lock);
_dm_bus_lock(&bus_lock);
rt_list_insert_before(&bus_nodes, &bus->list);
_dm_bus_unlock(&bus_lock);
return RT_EOK;
}
#endif

481
rt-thread/components/drivers/core/device.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2007-01-21 Bernard the first version
* 2010-05-04 Bernard add rt_device_init implementation
* 2012-10-20 Bernard add device check in register function,
* provided by Rob <rdent@iinet.net.au>
* 2012-12-25 Bernard return RT_EOK if the device interface not exist.
* 2013-07-09 Grissiom add ref_count support
* 2016-04-02 Bernard fix the open_flag initialization issue.
* 2021-03-19 Meco Man remove rt_device_init_all()
*/
#include <rtthread.h>
#define DBG_TAG "kernel.device"
#ifdef RT_DEBUG_DEVICE
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_WARNING
#endif /* defined (RT_DEBUG_DEVICE) */
#include <rtdbg.h>
#ifdef RT_USING_POSIX_DEVIO
#include <rtdevice.h> /* for wqueue_init */
#endif /* RT_USING_POSIX_DEVIO */
#ifdef RT_USING_DFS_V2
#include <devfs.h>
#endif /* RT_USING_DFS_V2 */
#ifdef RT_USING_DEVICE
#ifdef RT_USING_DEVICE_OPS
#define device_init (dev->ops ? dev->ops->init : RT_NULL)
#define device_open (dev->ops ? dev->ops->open : RT_NULL)
#define device_close (dev->ops ? dev->ops->close : RT_NULL)
#define device_read (dev->ops ? dev->ops->read : RT_NULL)
#define device_write (dev->ops ? dev->ops->write : RT_NULL)
#define device_control (dev->ops ? dev->ops->control : RT_NULL)
#else
#define device_init (dev->init)
#define device_open (dev->open)
#define device_close (dev->close)
#define device_read (dev->read)
#define device_write (dev->write)
#define device_control (dev->control)
#endif /* RT_USING_DEVICE_OPS */
/**
* @brief This function registers a device driver with a specified name.
*
* @param dev is the pointer of device driver structure.
*
* @param name is the device driver's name.
*
* @param flags is the capabilities flag of device.
*
* @return the error code, RT_EOK on initialization successfully.
*/
rt_err_t rt_device_register(rt_device_t dev,
const char *name,
rt_uint16_t flags)
{
if (dev == RT_NULL)
return -RT_ERROR;
if (rt_device_find(name) != RT_NULL)
return -RT_ERROR;
rt_object_init(&(dev->parent), RT_Object_Class_Device, name);
dev->flag = flags;
dev->ref_count = 0;
dev->open_flag = 0;
#ifdef RT_USING_POSIX_DEVIO
dev->fops = RT_NULL;
rt_wqueue_init(&(dev->wait_queue));
#endif /* RT_USING_POSIX_DEVIO */
#ifdef RT_USING_DFS_V2
dfs_devfs_device_add(dev);
#endif /* RT_USING_DFS_V2 */
return RT_EOK;
}
RTM_EXPORT(rt_device_register);
/**
* @brief This function removes a previously registered device driver.
*
* @param dev is the pointer of device driver structure.
*
* @return the error code, RT_EOK on successfully.
*/
rt_err_t rt_device_unregister(rt_device_t dev)
{
/* parameter check */
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(rt_object_get_type(&dev->parent) == RT_Object_Class_Device);
RT_ASSERT(rt_object_is_systemobject(&dev->parent));
rt_object_detach(&(dev->parent));
return RT_EOK;
}
RTM_EXPORT(rt_device_unregister);
/**
* @brief This function finds a device driver by specified name.
*
* @param name is the device driver's name.
*
* @return the registered device driver on successful, or RT_NULL on failure.
*/
rt_device_t rt_device_find(const char *name)
{
return (rt_device_t)rt_object_find(name, RT_Object_Class_Device);
}
RTM_EXPORT(rt_device_find);
#ifdef RT_USING_HEAP
/**
* @brief This function creates a device object with user data size.
*
* @param type is the type of the device object.
*
* @param attach_size is the size of user data.
*
* @return the allocated device object, or RT_NULL when failed.
*/
rt_device_t rt_device_create(int type, int attach_size)
{
int size;
rt_device_t device;
size = RT_ALIGN(sizeof(struct rt_device), RT_ALIGN_SIZE);
attach_size = RT_ALIGN(attach_size, RT_ALIGN_SIZE);
/* use the total size */
size += attach_size;
device = (rt_device_t)rt_malloc(size);
if (device)
{
rt_memset(device, 0x0, sizeof(struct rt_device));
device->type = (enum rt_device_class_type)type;
}
return device;
}
RTM_EXPORT(rt_device_create);
/**
* @brief This function destroy the specific device object.
*
* @param dev is a specific device object.
*/
void rt_device_destroy(rt_device_t dev)
{
/* parameter check */
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(rt_object_get_type(&dev->parent) == RT_Object_Class_Device);
RT_ASSERT(rt_object_is_systemobject(&dev->parent) == RT_FALSE);
rt_object_detach(&(dev->parent));
/* release this device object */
rt_free(dev);
}
RTM_EXPORT(rt_device_destroy);
#endif /* RT_USING_HEAP */
/**
* @brief This function will initialize the specified device.
*
* @param dev is the pointer of device driver structure.
*
* @return the result, RT_EOK on successfully.
*/
rt_err_t rt_device_init(rt_device_t dev)
{
rt_err_t result = RT_EOK;
RT_ASSERT(dev != RT_NULL);
/* get device_init handler */
if (device_init != RT_NULL)
{
if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
{
result = device_init(dev);
if (result != RT_EOK)
{
LOG_E("To initialize device:%s failed. The error code is %d",
dev->parent.name, result);
}
else
{
dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
}
}
}
return result;
}
/**
* @brief This function will open a device.
*
* @param dev is the pointer of device driver structure.
*
* @param oflag is the flags for device open.
*
* @return the result, RT_EOK on successfully.
*/
rt_err_t rt_device_open(rt_device_t dev, rt_uint16_t oflag)
{
rt_err_t result = RT_EOK;
/* parameter check */
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(rt_object_get_type(&dev->parent) == RT_Object_Class_Device);
/* if device is not initialized, initialize it. */
if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
{
if (device_init != RT_NULL)
{
result = device_init(dev);
if (result != RT_EOK)
{
LOG_E("To initialize device:%s failed. The error code is %d",
dev->parent.name, result);
return result;
}
}
dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
}
/* device is a stand alone device and opened */
if ((dev->flag & RT_DEVICE_FLAG_STANDALONE) &&
(dev->open_flag & RT_DEVICE_OFLAG_OPEN))
{
return -RT_EBUSY;
}
/* device is not opened or opened by other oflag, call device_open interface */
if (!(dev->open_flag & RT_DEVICE_OFLAG_OPEN) ||
((dev->open_flag & RT_DEVICE_OFLAG_MASK) != (oflag & RT_DEVICE_OFLAG_MASK)))
{
if (device_open != RT_NULL)
{
result = device_open(dev, oflag);
}
else
{
/* set open flag */
dev->open_flag = (oflag & RT_DEVICE_OFLAG_MASK);
}
}
/* set open flag */
if (result == RT_EOK || result == -RT_ENOSYS)
{
dev->open_flag |= RT_DEVICE_OFLAG_OPEN;
dev->ref_count++;
/* don't let bad things happen silently. If you are bitten by this assert,
* please set the ref_count to a bigger type. */
RT_ASSERT(dev->ref_count != 0);
}
return result;
}
RTM_EXPORT(rt_device_open);
/**
* @brief This function will close a device.
*
* @param dev is the pointer of device driver structure.
*
* @return the result, RT_EOK on successfully.
*/
rt_err_t rt_device_close(rt_device_t dev)
{
rt_err_t result = RT_EOK;
/* parameter check */
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(rt_object_get_type(&dev->parent) == RT_Object_Class_Device);
if (dev->ref_count == 0)
return -RT_ERROR;
dev->ref_count--;
if (dev->ref_count != 0)
return RT_EOK;
/* call device_close interface */
if (device_close != RT_NULL)
{
result = device_close(dev);
}
/* set open flag */
if (result == RT_EOK || result == -RT_ENOSYS)
dev->open_flag = RT_DEVICE_OFLAG_CLOSE;
return result;
}
RTM_EXPORT(rt_device_close);
/**
* @brief This function will read some data from a device.
*
* @param dev is the pointer of device driver structure.
*
* @param pos is the position when reading.
*
* @param buffer is a data buffer to save the read data.
*
* @param size is the size of buffer.
*
* @return the actually read size on successful, otherwise 0 will be returned.
*
* @note the unit of size/pos is a block for block device.
*/
rt_ssize_t rt_device_read(rt_device_t dev,
rt_off_t pos,
void *buffer,
rt_size_t size)
{
/* parameter check */
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(rt_object_get_type(&dev->parent) == RT_Object_Class_Device);
if (dev->ref_count == 0)
{
rt_set_errno(-RT_ERROR);
return 0;
}
/* call device_read interface */
if (device_read != RT_NULL)
{
return device_read(dev, pos, buffer, size);
}
/* set error code */
rt_set_errno(-RT_ENOSYS);
return 0;
}
RTM_EXPORT(rt_device_read);
/**
* @brief This function will write some data to a device.
*
* @param dev is the pointer of device driver structure.
*
* @param pos is the position when writing.
*
* @param buffer is the data buffer to be written to device.
*
* @param size is the size of buffer.
*
* @return the actually written size on successful, otherwise 0 will be returned.
*
* @note the unit of size/pos is a block for block device.
*/
rt_ssize_t rt_device_write(rt_device_t dev,
rt_off_t pos,
const void *buffer,
rt_size_t size)
{
/* parameter check */
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(rt_object_get_type(&dev->parent) == RT_Object_Class_Device);
if (dev->ref_count == 0)
{
rt_set_errno(-RT_ERROR);
return 0;
}
/* call device_write interface */
if (device_write != RT_NULL)
{
return device_write(dev, pos, buffer, size);
}
/* set error code */
rt_set_errno(-RT_ENOSYS);
return 0;
}
RTM_EXPORT(rt_device_write);
/**
* @brief This function will perform a variety of control functions on devices.
*
* @param dev is the pointer of device driver structure.
*
* @param cmd is the command sent to device.
*
* @param arg is the argument of command.
*
* @return the result, -RT_ENOSYS for failed.
*/
rt_err_t rt_device_control(rt_device_t dev, int cmd, void *arg)
{
/* parameter check */
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(rt_object_get_type(&dev->parent) == RT_Object_Class_Device);
/* call device_write interface */
if (device_control != RT_NULL)
{
return device_control(dev, cmd, arg);
}
return -RT_ENOSYS;
}
RTM_EXPORT(rt_device_control);
/**
* @brief This function will set the reception indication callback function. This callback function
* is invoked when this device receives data.
*
* @param dev is the pointer of device driver structure.
*
* @param rx_ind is the indication callback function.
*
* @return RT_EOK
*/
rt_err_t rt_device_set_rx_indicate(rt_device_t dev,
rt_err_t (*rx_ind)(rt_device_t dev,
rt_size_t size))
{
/* parameter check */
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(rt_object_get_type(&dev->parent) == RT_Object_Class_Device);
dev->rx_indicate = rx_ind;
return RT_EOK;
}
RTM_EXPORT(rt_device_set_rx_indicate);
/**
* @brief This function will set a callback function. The callback function
* will be called when device has written data to physical hardware.
*
* @param dev is the pointer of device driver structure.
*
* @param tx_done is the indication callback function.
*
* @return RT_EOK
*/
rt_err_t rt_device_set_tx_complete(rt_device_t dev,
rt_err_t (*tx_done)(rt_device_t dev,
void *buffer))
{
/* parameter check */
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(rt_object_get_type(&dev->parent) == RT_Object_Class_Device);
dev->tx_complete = tx_done;
return RT_EOK;
}
RTM_EXPORT(rt_device_set_tx_complete);
#endif /* RT_USING_DEVICE */

469
rt-thread/components/drivers/core/dm.c Normal file
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@@ -0,0 +1,469 @@
/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-04-20 ErikChan the first version
*/
#include <rtthread.h>
#ifdef RT_USING_OFW
#include <drivers/ofw_io.h>
#include <drivers/ofw_irq.h>
#endif
#include <drivers/core/dm.h>
#ifdef RT_USING_SMP
static int rti_secondary_cpu_start(void)
{
return 0;
}
INIT_EXPORT(rti_secondary_cpu_start, "6.end");
static int rti_secondary_cpu_end(void)
{
return 0;
}
INIT_EXPORT(rti_secondary_cpu_end, "7.end");
void rt_dm_secondary_cpu_init(void)
{
#ifdef RT_DEBUGING_AUTO_INIT
int result;
const struct rt_init_desc *desc;
rt_kprintf("do secondary cpu initialization.\n");
for (desc = &__rt_init_desc_rti_secondary_cpu_start; desc < &__rt_init_desc_rti_secondary_cpu_end; ++desc)
{
rt_kprintf("initialize %s", desc->fn_name);
result = desc->fn();
rt_kprintf(":%d done\n", result);
}
#else
volatile const init_fn_t *fn_ptr;
for (fn_ptr = &__rt_init_rti_secondary_cpu_start; fn_ptr < &__rt_init_rti_secondary_cpu_end; ++fn_ptr)
{
(*fn_ptr)();
}
#endif /* RT_DEBUGING_AUTO_INIT */
}
#endif /* RT_USING_SMP */
struct prefix_track
{
rt_list_t list;
int uid;
const char *prefix;
};
static struct rt_spinlock _prefix_nodes_lock = { 0 };
static rt_list_t _prefix_nodes = RT_LIST_OBJECT_INIT(_prefix_nodes);
int rt_dm_dev_set_name_auto(rt_device_t dev, const char *prefix)
{
int uid = -1;
struct prefix_track *pt = RT_NULL;
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(prefix != RT_NULL);
RT_DEBUG_NOT_IN_INTERRUPT;
rt_spin_lock(&_prefix_nodes_lock);
rt_list_for_each_entry(pt, &_prefix_nodes, list)
{
/* caller always input constants string, check ptr is faster */
if (pt->prefix == prefix || !rt_strcmp(pt->prefix, prefix))
{
uid = ++pt->uid;
break;
}
}
rt_spin_unlock(&_prefix_nodes_lock);
if (uid < 0)
{
pt = rt_malloc(sizeof(*pt));
if (!pt)
{
return -RT_ENOMEM;
}
rt_list_init(&pt->list);
pt->uid = uid = 0;
pt->prefix = prefix;
rt_spin_lock(&_prefix_nodes_lock);
rt_list_insert_before(&_prefix_nodes, &pt->list);
rt_spin_unlock(&_prefix_nodes_lock);
}
return rt_dm_dev_set_name(dev, "%s%u", prefix, uid);
}
int rt_dm_dev_get_name_id(rt_device_t dev)
{
int id = 0, len;
const char *name;
RT_ASSERT(dev != RT_NULL);
name = rt_dm_dev_get_name(dev);
len = rt_strlen(name) - 1;
name += len;
while (len --> 0)
{
if (*name < '0' || *name > '9')
{
while (*(++name))
{
id *= 10;
id += *name - '0';
}
break;
}
--name;
}
return id;
}
int rt_dm_dev_set_name(rt_device_t dev, const char *format, ...)
{
int n;
va_list arg_ptr;
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(format != RT_NULL);
va_start(arg_ptr, format);
n = rt_vsnprintf(dev->parent.name, RT_NAME_MAX, format, arg_ptr);
va_end(arg_ptr);
return n;
}
const char *rt_dm_dev_get_name(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
return dev->parent.name;
}
#ifdef RT_USING_OFW
#define ofw_api_call(name, ...) rt_ofw_##name(__VA_ARGS__)
#define ofw_api_call_ptr(name, ...) ofw_api_call(name, __VA_ARGS__)
#else
#define ofw_api_call(name, ...) (-RT_ENOSYS)
#define ofw_api_call_ptr(name, ...) RT_NULL
#endif
int rt_dm_dev_get_address_count(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (dev->ofw_node)
{
return ofw_api_call(get_address_count, dev->ofw_node);
}
#endif
return -RT_ENOSYS;
}
rt_err_t rt_dm_dev_get_address(rt_device_t dev, int index,
rt_uint64_t *out_address, rt_uint64_t *out_size)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (dev->ofw_node)
{
return ofw_api_call(get_address, dev->ofw_node, index,
out_address, out_size);
}
#endif
return -RT_ENOSYS;
}
rt_err_t rt_dm_dev_get_address_by_name(rt_device_t dev, const char *name,
rt_uint64_t *out_address, rt_uint64_t *out_size)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (dev->ofw_node)
{
return ofw_api_call(get_address_by_name, dev->ofw_node, name,
out_address, out_size);
}
#endif
return -RT_ENOSYS;
}
int rt_dm_dev_get_address_array(rt_device_t dev, int nr, rt_uint64_t *out_regs)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (dev->ofw_node)
{
return ofw_api_call(get_address_array, dev->ofw_node, nr, out_regs);
}
#endif
return -RT_ENOSYS;
}
void *rt_dm_dev_iomap(rt_device_t dev, int index)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (dev->ofw_node)
{
return ofw_api_call_ptr(iomap, dev->ofw_node, index);
}
#endif
return RT_NULL;
}
void *rt_dm_dev_iomap_by_name(rt_device_t dev, const char *name)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (dev->ofw_node)
{
return ofw_api_call_ptr(iomap_by_name, dev->ofw_node, name);
}
#endif
return RT_NULL;
}
int rt_dm_dev_get_irq_count(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
#if defined(RT_USING_OFW) && defined(RT_USING_PIC)
if (dev->ofw_node)
{
return ofw_api_call(get_irq_count, dev->ofw_node);
}
#endif
return -RT_ENOSYS;
}
int rt_dm_dev_get_irq(rt_device_t dev, int index)
{
RT_ASSERT(dev != RT_NULL);
#if defined(RT_USING_OFW) && defined(RT_USING_PIC)
if (dev->ofw_node)
{
return ofw_api_call(get_irq, dev->ofw_node, index);
}
#endif
return -RT_ENOSYS;
}
int rt_dm_dev_get_irq_by_name(rt_device_t dev, const char *name)
{
RT_ASSERT(dev != RT_NULL);
#if defined(RT_USING_OFW) && defined(RT_USING_PIC)
if (dev->ofw_node)
{
return ofw_api_call(get_irq_by_name, dev->ofw_node, name);
}
#endif
return -RT_ENOSYS;
}
void rt_dm_dev_bind_fwdata(rt_device_t dev, void *fw_np, void *data)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (!dev->ofw_node && fw_np)
{
dev->ofw_node = fw_np;
rt_ofw_data(fw_np) = data;
}
if (dev->ofw_node == RT_NULL)
{
rt_kprintf("[%s:%s] line=%d ofw_node is NULL\r\n", __FILE__, __func__, __LINE__);
return;
}
rt_ofw_data(dev->ofw_node) = data;
#endif
}
void rt_dm_dev_unbind_fwdata(rt_device_t dev, void *fw_np)
{
RT_ASSERT(dev!= RT_NULL);
#ifdef RT_USING_OFW
void *dev_fw_np = RT_NULL;
if (!dev->ofw_node && fw_np)
{
dev_fw_np = fw_np;
rt_ofw_data(fw_np) = RT_NULL;
}
if (dev_fw_np == RT_NULL)
{
rt_kprintf("[%s:%s] line=%d dev_fw_np is NULL\r\n", __FILE__, __func__, __LINE__);
return;
}
rt_ofw_data(dev_fw_np) = RT_NULL;
#endif
}
int rt_dm_dev_prop_read_u8_array_index(rt_device_t dev, const char *propname,
int index, int nr, rt_uint8_t *out_values)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_UISNG_OFW
if (dev->ofw_node)
{
return ofw_api_call(prop_read_u8_array_index, dev->ofw_node, propname,
index, nr, out_value);
}
#endif
return -RT_ENOSYS;
}
int rt_dm_dev_prop_read_u16_array_index(rt_device_t dev, const char *propname,
int index, int nr, rt_uint16_t *out_values)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (dev->ofw_node)
{
return ofw_api_call(prop_read_u16_array_index, dev->ofw_node, propname,
index, nr, out_values);
}
#endif
return -RT_ENOSYS;
}
int rt_dm_dev_prop_read_u32_array_index(rt_device_t dev, const char *propname,
int index, int nr, rt_uint32_t *out_values)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (dev->ofw_node)
{
return ofw_api_call(prop_read_u32_array_index, dev->ofw_node, propname,
index, nr, out_values);
}
#endif
return -RT_ENOSYS;
}
int rt_dm_dev_prop_read_u64_array_index(rt_device_t dev, const char *propname,
int index, int nr, rt_uint64_t *out_values)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (dev->ofw_node)
{
return ofw_api_call(prop_read_u64_array_index, dev->ofw_node, propname,
index, nr, out_values);
}
#endif
return -RT_ENOSYS;
}
int rt_dm_dev_prop_read_string_array_index(rt_device_t dev, const char *propname,
int index, int nr, const char **out_strings)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (dev->ofw_node)
{
return ofw_api_call(prop_read_string_array_index, dev->ofw_node, propname,
index, nr, out_strings);
}
#endif
return -RT_ENOSYS;
}
int rt_dm_dev_prop_count_of_size(rt_device_t dev, const char *propname, int size)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (dev->ofw_node)
{
return ofw_api_call(prop_count_of_size, dev->ofw_node, propname, size);
}
#endif
return -RT_ENOSYS;
}
int rt_dm_dev_prop_index_of_string(rt_device_t dev, const char *propname, const char *string)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (dev->ofw_node)
{
return ofw_api_call(prop_index_of_string, dev->ofw_node, propname, string);
}
#endif
return -RT_ENOSYS;
}
rt_bool_t rt_dm_dev_prop_read_bool(rt_device_t dev, const char *propname)
{
RT_ASSERT(dev != RT_NULL);
#ifdef RT_USING_OFW
if (dev->ofw_node)
{
return ofw_api_call(prop_read_bool, dev->ofw_node, propname);
}
#endif
return RT_FALSE;
}

53
rt-thread/components/drivers/core/driver.c Normal file
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@@ -0,0 +1,53 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <rtthread.h>
#include <drivers/core/bus.h>
#if defined(RT_USING_POSIX_DEVIO)
#include <rtdevice.h> /* for wqueue_init */
#endif
/**
* This function attach a driver to bus
*
* @param drv the driver to be attached
*/
rt_err_t rt_driver_register(rt_driver_t drv)
{
rt_err_t ret;
struct rt_bus *bus = RT_NULL;
RT_ASSERT(drv != RT_NULL);
if (drv->bus)
{
bus = drv->bus;
ret = rt_bus_add_driver(bus, drv);
}
else
{
ret = -RT_EINVAL;
}
return ret;
}
RTM_EXPORT(rt_driver_register);
/**
* This function remove driver from system.
*
* @param drv the driver to be removed
*/
rt_err_t rt_driver_unregister(rt_driver_t drv)
{
rt_err_t ret;
ret = rt_bus_remove_driver(drv);
return ret;
}
RTM_EXPORT(rt_driver_unregister);

165
rt-thread/components/drivers/core/mnt.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-02-21 GuEe-GUI first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#define DBG_TAG "rtdm.mnt"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#include <stdlib.h>
#include <dfs_fs.h>
#ifdef RT_USING_FINSH
#include <msh.h>
#endif
#include <ioremap.h>
#include <mm_memblock.h>
#ifdef RT_USING_OFW
#define bootargs_select rt_ofw_bootargs_select
#else
#error Platform have not kernel parameters select interfaces!
#endif
static int rootfs_mnt_init(void)
{
rt_err_t err = -RT_ERROR;
void *fsdata = RT_NULL;
const char *cromfs_type = "crom";
const char *dev = bootargs_select("root=", 0);
const char *fstype = bootargs_select("rootfstype=", 0);
const char *rw = bootargs_select("rw", 0);
if (!dev || !fstype)
{
const char *name = "initrd";
rt_uint64_t initrd_start = 0, initrd_end = 0;
struct rt_mmblk_reg *iter = RT_NULL;
rt_slist_for_each_entry(iter, &(rt_memblock_get_reserved()->reg_list), node)
{
if (rt_strcmp(iter->memreg.name, name) == 0)
{
initrd_start = iter->memreg.start;
initrd_end = iter->memreg.end;
break;
}
}
if (initrd_start && initrd_end)
{
size_t initrd_size = initrd_end - initrd_start;
if ((fsdata = rt_ioremap_cached((void *)initrd_start, initrd_size)))
{
fstype = cromfs_type;
}
}
}
if (fstype != cromfs_type && dev)
{
rt_tick_t timeout = 0;
const char *rootwait, *rootdelay = RT_NULL;
rootwait = bootargs_select("rootwait", 0);
/* Maybe it is undefined or 'rootwaitABC' */
if (!rootwait || *rootwait)
{
rootdelay = bootargs_select("rootdelay=", 0);
if (rootdelay)
{
timeout = rt_tick_from_millisecond(atoi(rootdelay));
}
rootwait = RT_NULL;
}
/*
* Delays in boot flow is a terrible behavior in RTOS, but the RT-Thread
* SDIO framework init the devices in a task that we need to wait for
* SDIO devices to init complete...
*
* WHAT THE F*CK PROBLEMS WILL HAPPENED?
*
* Your main PE, applications, services that depend on the root FS and
* the multi cores setup, init will delay, too...
*
* So, you can try to link this function to `INIT_APP_EXPORT` even later
* and remove the delays if you want to optimize the boot time and mount
* the FS auto.
*/
for (; rootdelay || rootwait; --timeout)
{
if (!rootwait && timeout == 0)
{
LOG_E("Wait for /dev/%s init time out", dev);
/*
* We don't return at once because the device driver may init OK
* when we break from this point, might as well give it another
* try.
*/
break;
}
if (rt_device_find(dev))
{
break;
}
rt_thread_mdelay(1);
}
}
if (fstype)
{
if (!(err = dfs_mount(dev, "/", fstype, rw ? 0 : ~0, fsdata)))
{
LOG_I("Mount root %s%s type=%s %s",
(dev && *dev) ? "on /dev/" : "",
(dev && *dev) ? dev : "\b",
fstype, "done");
}
else
{
LOG_W("Mount root %s%s type=%s %s",
(dev && *dev) ? "on /dev/" : "",
(dev && *dev) ? dev : "\b",
fstype, "fail");
if (fstype == cromfs_type)
{
rt_iounmap(fsdata);
}
}
}
return 0;
}
INIT_ENV_EXPORT(rootfs_mnt_init);
static int fstab_mnt_init(void)
{
mkdir("/mnt", 0755);
#ifdef RT_USING_FINSH
/* Try mount by table */
msh_exec_script("fstab.sh", 16);
#endif
LOG_I("File system initialization done");
return 0;
}
INIT_FS_EXPORT(fstab_mnt_init);

171
rt-thread/components/drivers/core/numa.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-09-24 GuEe-GUI the first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#define DBG_TAG "rtdm.numa"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#include <drivers/pic.h>
struct numa_memory
{
rt_list_t list;
int nid;
rt_uint64_t start;
rt_uint64_t end;
union
{
void *ofw_node;
};
};
static rt_bool_t numa_enabled = RT_FALSE;
static int cpu_numa_map[RT_CPUS_NR] rt_section(".bss.noclean.numa");
static rt_list_t numa_memory_nodes rt_section(".bss.noclean.numa");
int rt_numa_cpu_id(int cpuid)
{
if (!numa_enabled)
{
return -RT_ENOSYS;
}
return cpuid < RT_ARRAY_SIZE(cpu_numa_map) ? cpu_numa_map[cpuid] : -RT_EINVAL;
}
int rt_numa_device_id(struct rt_device *dev)
{
rt_uint32_t nid = (rt_uint32_t)-RT_ENOSYS;
if (!numa_enabled)
{
return nid;
}
return rt_dm_dev_prop_read_u32(dev, "numa-node-id", &nid) ? : (int)nid;
}
rt_err_t rt_numa_memory_affinity(rt_uint64_t phy_addr, rt_bitmap_t *out_affinity)
{
struct numa_memory *nm;
if (!out_affinity)
{
return -RT_EINVAL;
}
if (!numa_enabled)
{
/* Default to CPU#0 */
RT_IRQ_AFFINITY_SET(out_affinity, 0);
return RT_EOK;
}
rt_memset(out_affinity, 0, sizeof(*out_affinity) * RT_BITMAP_LEN(RT_CPUS_NR));
rt_list_for_each_entry(nm, &numa_memory_nodes, list)
{
if (phy_addr >= nm->start && phy_addr < nm->end)
{
for (int i = 0; i < RT_ARRAY_SIZE(cpu_numa_map); ++i)
{
if (cpu_numa_map[i] == nm->nid)
{
RT_IRQ_AFFINITY_SET(out_affinity, i);
}
}
return RT_EOK;
}
}
return -RT_EEMPTY;
}
#ifdef RT_USING_OFW
static int numa_ofw_init(void)
{
int i = 0;
rt_uint32_t nid;
const char *numa_conf;
struct rt_ofw_node *np = RT_NULL;
numa_conf = rt_ofw_bootargs_select("numa=", 0);
if (!numa_conf || rt_strcmp(numa_conf, "on"))
{
return (int)RT_EOK;
}
numa_enabled = RT_TRUE;
for (int i = 0; i < RT_ARRAY_SIZE(cpu_numa_map); ++i)
{
cpu_numa_map[i] = -RT_ENOSYS;
}
rt_list_init(&numa_memory_nodes);
rt_ofw_foreach_cpu_node(np)
{
rt_ofw_prop_read_u32(np, "numa-node-id", (rt_uint32_t *)&cpu_numa_map[i]);
if (++i >= RT_CPUS_NR)
{
break;
}
}
rt_ofw_foreach_node_by_type(np, "memory")
{
if (!rt_ofw_prop_read_u32(np, "numa-node-id", &nid))
{
int mem_nr = rt_ofw_get_address_count(np);
for (i = 0; i < mem_nr; ++i)
{
rt_uint64_t addr, size;
struct numa_memory *nm;
if (rt_ofw_get_address(np, i, &addr, &size))
{
continue;
}
nm = rt_malloc(sizeof(*nm));
if (!nm)
{
LOG_E("No memory to record NUMA[%d] memory[%p, %p] info",
nid, addr, addr + size);
return (int)-RT_ENOMEM;
}
nm->start = addr;
nm->end = addr + size;
nm->ofw_node = np;
rt_list_init(&nm->list);
rt_list_insert_before(&numa_memory_nodes, &nm->list);
}
}
}
return 0;
}
INIT_CORE_EXPORT(numa_ofw_init);
#endif /* RT_USING_OFW */

202
rt-thread/components/drivers/core/platform.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-04-12 ErikChan the first version
* 2023-10-13 zmshahaha distinguish ofw and none-ofw situation
*/
#include <rtthread.h>
#define DBG_TAG "rtdm.pltaform"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#include <drivers/platform.h>
#include <drivers/core/bus.h>
#include <drivers/core/dm.h>
#include <drivers/core/power_domain.h>
static struct rt_bus platform_bus;
/**
* @brief This function create a platform device.
*
* @param name is name of the platform device.
*
* @return a new platform device.
*/
struct rt_platform_device *rt_platform_device_alloc(const char *name)
{
struct rt_platform_device *pdev = rt_calloc(1, sizeof(*pdev));
if (!pdev)
{
return RT_NULL;
}
pdev->parent.bus = &platform_bus;
pdev->name = name;
return pdev;
}
/**
* @brief This function register a rt_driver to platform bus.
*
* @return the error code, RT_EOK on successfully.
*/
rt_err_t rt_platform_driver_register(struct rt_platform_driver *pdrv)
{
RT_ASSERT(pdrv != RT_NULL);
pdrv->parent.bus = &platform_bus;
#if RT_NAME_MAX > 0
rt_strcpy(pdrv->parent.parent.name, pdrv->name);
#else
pdrv->parent.parent.name = pdrv->name;
#endif
return rt_driver_register(&pdrv->parent);
}
/**
* @brief This function register a rt_device to platform bus.
*
* @return the error code, RT_EOK on successfully.
*/
rt_err_t rt_platform_device_register(struct rt_platform_device *pdev)
{
RT_ASSERT(pdev != RT_NULL);
return rt_bus_add_device(&platform_bus, &pdev->parent);
}
static rt_bool_t platform_match(rt_driver_t drv, rt_device_t dev)
{
struct rt_platform_driver *pdrv = rt_container_of(drv, struct rt_platform_driver, parent);
struct rt_platform_device *pdev = rt_container_of(dev, struct rt_platform_device, parent);
#ifdef RT_USING_OFW
struct rt_ofw_node *np = dev->ofw_node;
/* 1、match with ofw node */
if (np)
{
pdev->id = rt_ofw_node_match(np, pdrv->ids);
if (pdev->id)
{
return RT_TRUE;
}
}
#endif
/* 2、match with name */
if (pdev->name && pdrv->name)
{
if (pdev->name == pdrv->name)
{
return RT_TRUE;
}
else
{
return !rt_strcmp(pdrv->name, pdev->name);
}
}
return RT_FALSE;
}
static rt_err_t platform_probe(rt_device_t dev)
{
rt_err_t err;
struct rt_platform_driver *pdrv = rt_container_of(dev->drv, struct rt_platform_driver, parent);
struct rt_platform_device *pdev = rt_container_of(dev, struct rt_platform_device, parent);
#ifdef RT_USING_OFW
struct rt_ofw_node *np = dev->ofw_node;
#endif
err = rt_dm_power_domain_attach(dev, RT_TRUE);
if (err && err != -RT_EEMPTY)
{
LOG_E("Attach power domain error = %s in device %s", pdev->name, rt_strerror(err));
return err;
}
err = pdrv->probe(pdev);
if (!err)
{
#ifdef RT_USING_OFW
if (np)
{
rt_ofw_node_set_flag(np, RT_OFW_F_READLY);
}
#endif
}
else
{
if (err == -RT_ENOMEM)
{
LOG_W("System not memory in driver %s", pdrv->name);
}
rt_dm_power_domain_detach(dev, RT_TRUE);
}
return err;
}
static rt_err_t platform_remove(rt_device_t dev)
{
struct rt_platform_driver *pdrv = rt_container_of(dev->drv, struct rt_platform_driver, parent);
struct rt_platform_device *pdev = rt_container_of(dev, struct rt_platform_device, parent);
if (pdrv && pdrv->remove)
{
pdrv->remove(pdev);
}
rt_dm_power_domain_detach(dev, RT_TRUE);
rt_platform_ofw_free(pdev);
return RT_EOK;
}
static rt_err_t platform_shutdown(rt_device_t dev)
{
struct rt_platform_driver *pdrv = rt_container_of(dev->drv, struct rt_platform_driver, parent);
struct rt_platform_device *pdev = rt_container_of(dev, struct rt_platform_device, parent);
if (pdrv && pdrv->shutdown)
{
pdrv->shutdown(pdev);
}
rt_dm_power_domain_detach(dev, RT_TRUE);
rt_platform_ofw_free(pdev);
return RT_EOK;
}
static struct rt_bus platform_bus =
{
.name = "platform",
.match = platform_match,
.probe = platform_probe,
.remove = platform_remove,
.shutdown = platform_shutdown,
};
static int platform_bus_init(void)
{
rt_bus_register(&platform_bus);
return 0;
}
INIT_CORE_EXPORT(platform_bus_init);

256
rt-thread/components/drivers/core/platform_ofw.c Normal file
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@@ -0,0 +1,256 @@
/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-06-04 GuEe-GUI the first version
*/
#include <rtthread.h>
#define DBG_TAG "drv.platform"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#include <drivers/ofw_io.h>
#include <drivers/ofw_fdt.h>
#include <drivers/platform.h>
#include <drivers/core/dm.h>
#include "../ofw/ofw_internal.h"
static const struct rt_ofw_node_id platform_ofw_ids[] =
{
{ .compatible = "simple-bus", },
#ifdef RT_USING_MFD
{ .compatible = "simple-mfd", },
#endif
#ifdef RT_USING_ISA
{ .compatible = "isa", },
#endif
#ifdef RT_USING_AMBA_BUS
/*
* Maybe ARM has replaced it with compatible: "arm,primecell" and will not
* used anymore in the future.
*/
{ .compatible = "arm,amba-bus", },
#endif
{ /* sentinel */ }
};
static void ofw_device_rename(struct rt_device *dev)
{
rt_uint32_t mask;
rt_uint64_t addr;
const char *dev_name = dev->parent.name;
struct rt_ofw_node *np = dev->ofw_node;
#if RT_NAME_MAX > 0
if (dev_name[0] == '\0')
{
dev_name = RT_NULL;
}
#endif
while (np->parent)
{
if (!rt_ofw_get_address(np, 0, &addr, RT_NULL))
{
const char *node_name = rt_fdt_node_name(np->full_name);
rt_size_t tag_len = strchrnul(node_name, '@') - node_name;
if (!rt_ofw_prop_read_u32(np, "mask", &mask))
{
rt_dm_dev_set_name(dev, dev_name ? "%lx.%x.%.*s:%s" : "%lx.%x.%.*s",
addr, __rt_ffs(mask) - 1, tag_len, node_name, dev_name);
}
else
{
rt_dm_dev_set_name(dev, dev_name ? "%lx.%.*s:%s" : "%lx.%.*s",
addr, tag_len, node_name, dev_name);
}
return;
}
rt_dm_dev_set_name(dev, dev_name ? "%s:%s" : "%s",
rt_fdt_node_name(np->full_name), dev_name);
np = np->parent;
}
}
static struct rt_platform_device *alloc_ofw_platform_device(struct rt_ofw_node *np)
{
struct rt_platform_device *pdev = rt_platform_device_alloc("");
if (pdev)
{
/* inc reference of dt-node */
rt_ofw_node_get(np);
rt_ofw_node_set_flag(np, RT_OFW_F_PLATFORM);
pdev->parent.ofw_node = np;
ofw_device_rename(&pdev->parent);
}
else
{
LOG_E("Alloc device fail for %s", rt_ofw_node_full_name(np));
}
return pdev;
}
static rt_err_t platform_ofw_device_probe_once(struct rt_ofw_node *parent_np)
{
rt_err_t err = RT_EOK;
struct rt_ofw_node *np;
struct rt_platform_device *pdev;
rt_ofw_foreach_available_child_node(parent_np, np)
{
const char *name;
struct rt_ofw_node_id *id;
struct rt_ofw_prop *compat_prop = RT_NULL;
LOG_D("%s found in %s", np->full_name, parent_np->full_name);
/* Is system node or have driver */
if (rt_ofw_node_test_flag(np, RT_OFW_F_SYSTEM) ||
rt_ofw_node_test_flag(np, RT_OFW_F_READLY))
{
continue;
}
compat_prop = rt_ofw_get_prop(np, "compatible", RT_NULL);
name = rt_ofw_node_name(np);
/* Not have name and compatible */
if (!compat_prop && (name == (const char *)"<NULL>" || !rt_strcmp(name, "<NULL>")))
{
continue;
}
id = rt_ofw_prop_match(compat_prop, platform_ofw_ids);
if (id && np->child)
{
/* scan next level */
err = platform_ofw_device_probe_once(np);
if (err)
{
rt_ofw_node_put(np);
LOG_E("%s bus probe fail", np->full_name);
break;
}
}
pdev = alloc_ofw_platform_device(np);
if (!pdev)
{
rt_ofw_node_put(np);
err = -RT_ENOMEM;
break;
}
pdev->dev_id = ofw_alias_node_id(np);
LOG_D("%s register to bus", np->full_name);
rt_platform_device_register(pdev);
}
return err;
}
rt_err_t rt_platform_ofw_device_probe_child(struct rt_ofw_node *np)
{
rt_err_t err;
struct rt_ofw_node *parent = rt_ofw_get_parent(np);
if (parent && rt_strcmp(parent->name, "/") &&
rt_ofw_get_prop(np, "compatible", RT_NULL) &&
!rt_ofw_node_test_flag(np, RT_OFW_F_PLATFORM))
{
struct rt_platform_device *pdev = alloc_ofw_platform_device(np);
if (pdev)
{
err = rt_platform_device_register(pdev);
}
else
{
err = -RT_ENOMEM;
}
}
else
{
err = -RT_EINVAL;
}
rt_ofw_node_put(parent);
return err;
}
static int platform_ofw_device_probe(void)
{
rt_err_t err = RT_EOK;
struct rt_ofw_node *node;
if (ofw_node_root)
{
err = platform_ofw_device_probe_once(ofw_node_root);
rt_ofw_node_put(ofw_node_root);
if ((node = rt_ofw_find_node_by_path("/firmware")))
{
platform_ofw_device_probe_once(node);
rt_ofw_node_put(node);
}
if ((node = rt_ofw_get_child_by_compatible(ofw_node_chosen, "simple-framebuffer")))
{
platform_ofw_device_probe_once(node);
rt_ofw_node_put(node);
}
}
else
{
err = -RT_ENOSYS;
}
return (int)err;
}
INIT_PLATFORM_EXPORT(platform_ofw_device_probe);
rt_err_t rt_platform_ofw_free(struct rt_platform_device *pdev)
{
rt_err_t err = RT_EOK;
if (pdev)
{
struct rt_ofw_node *np = pdev->parent.ofw_node;
if (np)
{
rt_ofw_node_clear_flag(np, RT_OFW_F_PLATFORM);
rt_ofw_node_put(np);
pdev->parent.ofw_node = RT_NULL;
}
}
else
{
err = -RT_EINVAL;
}
return err;
}

477
rt-thread/components/drivers/core/power_domain.c Normal file
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@@ -0,0 +1,477 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-09-24 GuEe-GUI the first version
*/
#include <rtdevice.h>
#define DBG_TAG "rtdm.power_domain"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#include <drivers/ofw.h>
void rt_dm_power_domain_proxy_default_name(struct rt_dm_power_domain_proxy *proxy)
{
#if RT_NAME_MAX > 0
rt_strncpy(proxy->parent.name, RT_POWER_DOMAIN_OBJ_NAME, RT_NAME_MAX);
#else
proxy->parent.name = RT_POWER_DOMAIN_OBJ_NAME;
#endif
}
void rt_dm_power_domain_proxy_ofw_bind(struct rt_dm_power_domain_proxy *proxy,
struct rt_ofw_node *np)
{
if (!proxy || !proxy->ofw_parse || !np)
{
return;
}
rt_dm_power_domain_proxy_default_name(proxy);
rt_ofw_data(np) = proxy;
}
static void dm_power_domain_init(struct rt_dm_power_domain *domain)
{
#if RT_NAME_MAX > 0
rt_strncpy(domain->parent.name, RT_POWER_DOMAIN_OBJ_NAME, RT_NAME_MAX);
#else
domain->parent.name = RT_POWER_DOMAIN_OBJ_NAME;
#endif
domain->parent_domain = RT_NULL;
rt_list_init(&domain->list);
rt_list_init(&domain->child_nodes);
rt_list_init(&domain->unit_nodes);
rt_ref_init(&domain->ref);
rt_spin_lock_init(&domain->lock);
}
static rt_bool_t dm_power_domain_is_free(struct rt_dm_power_domain *domain)
{
return rt_ref_read(&domain->ref) == 1 && !rt_list_isempty(&domain->child_nodes);
}
rt_err_t rt_dm_power_domain_register(struct rt_dm_power_domain *domain)
{
if (!domain)
{
return -RT_EINVAL;
}
dm_power_domain_init(domain);
return RT_EOK;
}
rt_err_t rt_dm_power_domain_unregister(struct rt_dm_power_domain *domain)
{
rt_err_t err = RT_EOK;
if (!domain)
{
return -RT_EINVAL;
}
if (!dm_power_domain_is_free(domain))
{
return -RT_EBUSY;
}
if (domain->parent_domain)
{
err = rt_dm_power_domain_unregister_child(domain->parent_domain, domain);
}
return err;
}
rt_err_t rt_dm_power_domain_register_child(struct rt_dm_power_domain *domain,
struct rt_dm_power_domain *child_domain)
{
if (!domain || !child_domain)
{
return -RT_EINVAL;
}
dm_power_domain_init(child_domain);
child_domain->parent_domain = domain;
return RT_EOK;
}
rt_err_t rt_dm_power_domain_unregister_child(struct rt_dm_power_domain *domain,
struct rt_dm_power_domain *child_domain)
{
rt_err_t err = RT_EOK;
if (!domain || !child_domain)
{
return -RT_EINVAL;
}
rt_hw_spin_lock(&domain->lock.lock);
if (dm_power_domain_is_free(domain))
{
rt_list_remove(&child_domain->list);
}
else
{
err = -RT_EBUSY;
}
rt_hw_spin_unlock(&domain->lock.lock);
return err;
}
rt_err_t rt_dm_power_domain_power_on(struct rt_dm_power_domain *domain)
{
rt_err_t err = RT_EOK;
struct rt_dm_power_domain *child_domain;
if (!domain)
{
return -RT_EINVAL;
}
rt_hw_spin_lock(&domain->lock.lock);
if (rt_ref_read(&domain->ref) == 1)
{
err = domain->power_on(domain);
}
if (!err)
{
struct rt_dm_power_domain *fail_domain = RT_NULL;
rt_list_for_each_entry(child_domain, &domain->child_nodes, list)
{
err = rt_dm_power_domain_power_on(child_domain);
if (err)
{
fail_domain = child_domain;
break;
}
}
if (fail_domain)
{
rt_list_for_each_entry(child_domain, &domain->child_nodes, list)
{
if (child_domain == fail_domain)
{
break;
}
rt_dm_power_domain_power_off(child_domain);
}
}
}
rt_hw_spin_unlock(&domain->lock.lock);
if (!err)
{
rt_ref_get(&domain->ref);
}
return err;
}
static void dm_power_domain_release(struct rt_ref *r)
{
struct rt_dm_power_domain *domain = rt_container_of(r, struct rt_dm_power_domain, ref);
if (domain->dev)
{
LOG_E("%s power domain is release", rt_dm_dev_get_name(domain->dev));
}
RT_ASSERT(0);
}
rt_err_t rt_dm_power_domain_power_off(struct rt_dm_power_domain *domain)
{
rt_err_t err;
struct rt_dm_power_domain *child_domain;
if (!domain)
{
return -RT_EINVAL;
}
rt_ref_put(&domain->ref, dm_power_domain_release);
rt_hw_spin_lock(&domain->lock.lock);
if (rt_ref_read(&domain->ref) == 1)
{
err = domain->power_off(domain);
}
else
{
err = -RT_EBUSY;
}
if (!err)
{
struct rt_dm_power_domain *fail_domain = RT_NULL;
rt_list_for_each_entry(child_domain, &domain->child_nodes, list)
{
err = rt_dm_power_domain_power_off(child_domain);
if (err)
{
fail_domain = child_domain;
break;
}
}
if (fail_domain)
{
rt_list_for_each_entry(child_domain, &domain->child_nodes, list)
{
if (child_domain == fail_domain)
{
break;
}
rt_dm_power_domain_power_on(child_domain);
}
}
}
rt_hw_spin_unlock(&domain->lock.lock);
if (err)
{
rt_ref_get(&domain->ref);
}
return err;
}
#ifdef RT_USING_OFW
static struct rt_dm_power_domain *ofw_find_power_domain(struct rt_device *dev,
int index, struct rt_ofw_cell_args *args)
{
struct rt_object *obj;
struct rt_dm_power_domain_proxy *proxy;
struct rt_dm_power_domain *domain = RT_NULL;
struct rt_ofw_node *np = dev->ofw_node, *power_domain_np;
if (!rt_ofw_parse_phandle_cells(np, "power-domains", "#power-domain-cells",
index, args))
{
power_domain_np = args->data;
if (power_domain_np && (obj = rt_ofw_data(power_domain_np)))
{
if (!rt_strcmp(obj->name, RT_POWER_DOMAIN_OBJ_NAME))
{
proxy = rt_container_of(obj, struct rt_dm_power_domain_proxy, parent);
domain = proxy->ofw_parse(proxy, args);
}
else if (!rt_strcmp(obj->name, RT_POWER_DOMAIN_OBJ_NAME))
{
domain = rt_container_of(obj, struct rt_dm_power_domain, parent);
}
else if ((obj = rt_ofw_parse_object(power_domain_np,
RT_POWER_DOMAIN_PROXY_OBJ_NAME, "#power-domain-cells")))
{
proxy = rt_container_of(obj, struct rt_dm_power_domain_proxy, parent);
domain = proxy->ofw_parse(proxy, args);
}
else if ((obj = rt_ofw_parse_object(power_domain_np,
RT_POWER_DOMAIN_OBJ_NAME, "#power-domain-cells")))
{
domain = rt_container_of(obj, struct rt_dm_power_domain, parent);
}
rt_ofw_node_put(power_domain_np);
}
}
return domain;
}
#else
rt_inline struct rt_dm_power_domain *ofw_find_power_domain(struct rt_device *dev,
int index, struct rt_ofw_cell_args *args)
{
return RT_NULL;
}
#endif /* RT_USING_OFW */
struct rt_dm_power_domain *rt_dm_power_domain_get_by_index(struct rt_device *dev,
int index)
{
struct rt_ofw_cell_args args;
struct rt_dm_power_domain *domain;
if (!dev || index < 0)
{
return RT_NULL;
}
if ((domain = ofw_find_power_domain(dev, index, &args)))
{
goto _end;
}
_end:
return domain;
}
struct rt_dm_power_domain *rt_dm_power_domain_get_by_name(struct rt_device *dev,
const char *name)
{
int index;
if (!dev || !name)
{
return RT_NULL;
}
if ((index = rt_dm_dev_prop_index_of_string(dev, "power-domain-names", name)) < 0)
{
LOG_E("%s find power domain %s not found", rt_dm_dev_get_name(dev));
return RT_NULL;
}
return rt_dm_power_domain_get_by_index(dev, index);
}
rt_err_t rt_dm_power_domain_put(struct rt_dm_power_domain *domain)
{
if (!domain)
{
return -RT_EINVAL;
}
return RT_EOK;
}
rt_err_t rt_dm_power_domain_attach(struct rt_device *dev, rt_bool_t on)
{
int id = -1;
rt_err_t err = RT_EOK;
struct rt_ofw_cell_args args;
struct rt_dm_power_domain *domain;
struct rt_dm_power_domain_unit *unit;
if (!dev)
{
return -RT_EINVAL;
}
/* We only attach the first one, get domains self if there are multiple domains */
if ((domain = ofw_find_power_domain(dev, 0, &args)))
{
id = args.args[0];
}
if (!domain)
{
return -RT_EEMPTY;
}
unit = rt_malloc(sizeof(*unit));
if (!unit)
{
return -RT_ENOMEM;
}
rt_list_init(&unit->list);
unit->id = id;
unit->domain = domain;
dev->power_domain_unit = unit;
rt_hw_spin_lock(&domain->lock.lock);
if (domain->attach_dev)
{
err = domain->attach_dev(domain, dev);
}
if (!err)
{
rt_list_insert_before(&domain->unit_nodes, &unit->list);
}
rt_hw_spin_unlock(&domain->lock.lock);
if (err)
{
dev->power_domain_unit = RT_NULL;
rt_free(unit);
return err;
}
if (on)
{
err = rt_dm_power_domain_power_on(domain);
}
return err;
}
rt_err_t rt_dm_power_domain_detach(struct rt_device *dev, rt_bool_t off)
{
rt_err_t err = RT_EOK;
struct rt_dm_power_domain *domain;
struct rt_dm_power_domain_unit *unit;
if (!dev || !dev->power_domain_unit)
{
return -RT_EINVAL;
}
unit = dev->power_domain_unit;
domain = unit->domain;
rt_hw_spin_lock(&domain->lock.lock);
if (domain->detach_dev)
{
err = domain->detach_dev(domain, dev);
}
if (!err)
{
rt_list_remove(&unit->list);
}
rt_hw_spin_unlock(&domain->lock.lock);
if (err)
{
return err;
}
rt_free(unit);
dev->power_domain_unit = RT_NULL;
if (off)
{
err = rt_dm_power_domain_power_off(domain);
}
return err;
}

34
rt-thread/components/drivers/cputime/Kconfig Normal file
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@@ -0,0 +1,34 @@
config RT_USING_CPUTIME
bool "Enable CPU time for high resolution clock counter"
default n
help
When enable this option, the BSP should provide a rt_clock_cputime_ops
for CPU time by:
const static struct rt_clock_cputime_ops _ops = {...};
clock_cpu_setops(&_ops);
Then user can use high resolution clock counter with:
ts1 = clock_cpu_gettime();
ts2 = clock_cpu_gettime();
/* and get the ms of delta tick with API: */
ms_tick = clock_cpu_millisecond(t2 - t1);
us_tick = clock_cpu_microsecond(t2 - t1);
if RT_USING_CPUTIME
config RT_USING_CPUTIME_CORTEXM
bool "Support Cortex-M CPU"
default y
depends on ARCH_ARM_CORTEX_M0 || ARCH_ARM_CORTEX_M3 || ARCH_ARM_CORTEX_M4 || ARCH_ARM_CORTEX_M7
select PKG_USING_PERF_COUNTER
config RT_USING_CPUTIME_RISCV
bool "Use rdtime instructions for CPU time"
default y
depends on ARCH_RISCV64
help
Some RISCV64 MCU Use rdtime instructions read CPU time.
config CPUTIME_TIMER_FREQ
int "CPUTIME timer freq"
default 0
endif

18
rt-thread/components/drivers/cputime/SConscript Normal file
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@@ -0,0 +1,18 @@
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd + '/../include']
src = Split('''
cputime.c
cputimer.c
''')
if GetDepend('RT_USING_CPUTIME_CORTEXM'):
src += ['cputime_cortexm.c']
if GetDepend('RT_USING_CPUTIME_RISCV'):
src += ['cputime_riscv.c']
group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_CPUTIME'], CPPPATH = CPPPATH)
Return('group')

116
rt-thread/components/drivers/cputime/cputime.c Normal file
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@@ -0,0 +1,116 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-12-23 Bernard first version
*/
#include <rtdevice.h>
#include <rtthread.h>
#include <sys/errno.h>
static const struct rt_clock_cputime_ops *_cputime_ops = RT_NULL;
/**
* The clock_cpu_getres() function shall return the resolution of CPU time, the
* number of nanosecond per tick.
*
* @return the number of nanosecond per tick(x (1000UL * 1000))
*/
uint64_t clock_cpu_getres(void)
{
if (_cputime_ops)
return _cputime_ops->cputime_getres();
rt_set_errno(ENOSYS);
return 0;
}
/**
* The clock_cpu_gettime() function shall return the current value of cpu time tick.
*
* @return the cpu tick
*/
uint64_t clock_cpu_gettime(void)
{
if (_cputime_ops)
return _cputime_ops->cputime_gettime();
rt_set_errno(ENOSYS);
return 0;
}
/**
* The clock_cpu_settimeout() fucntion set timeout time and timeout callback function
* The timeout callback function will be called when the timeout time is reached
*
* @param tick the Timeout tick
* @param timeout the Timeout function
* @param parameter the Parameters of timeout function
*
*/
int clock_cpu_settimeout(uint64_t tick, void (*timeout)(void *param), void *param)
{
if (_cputime_ops)
return _cputime_ops->cputime_settimeout(tick, timeout, param);
rt_set_errno(ENOSYS);
return 0;
}
int clock_cpu_issettimeout(void)
{
if (_cputime_ops)
return _cputime_ops->cputime_settimeout != RT_NULL;
return RT_FALSE;
}
/**
* The clock_cpu_microsecond() fucntion shall return the microsecond according to
* cpu_tick parameter.
*
* @param cpu_tick the cpu tick
*
* @return the microsecond
*/
uint64_t clock_cpu_microsecond(uint64_t cpu_tick)
{
uint64_t unit = clock_cpu_getres();
return (uint64_t)(((cpu_tick * unit) / (1000UL * 1000)) / 1000);
}
/**
* The clock_cpu_microsecond() fucntion shall return the millisecond according to
* cpu_tick parameter.
*
* @param cpu_tick the cpu tick
*
* @return the millisecond
*/
uint64_t clock_cpu_millisecond(uint64_t cpu_tick)
{
uint64_t unit = clock_cpu_getres();
return (uint64_t)(((cpu_tick * unit) / (1000UL * 1000)) / (1000UL * 1000));
}
/**
* The clock_cpu_seops() function shall set the ops of cpu time.
*
* @return always return 0.
*/
int clock_cpu_setops(const struct rt_clock_cputime_ops *ops)
{
_cputime_ops = ops;
if (ops)
{
RT_ASSERT(ops->cputime_getres != RT_NULL);
RT_ASSERT(ops->cputime_gettime != RT_NULL);
}
return 0;
}

69
rt-thread/components/drivers/cputime/cputime_cortexm.c Normal file
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@@ -0,0 +1,69 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-12-23 Bernard first version
* 2022-06-14 Meco Man suuport pref_counter
*/
#include <rthw.h>
#include <rtdevice.h>
#include <rtthread.h>
#include <board.h>
#ifdef PKG_USING_PERF_COUNTER
#include <perf_counter.h>
#endif
/* Use Cycle counter of Data Watchpoint and Trace Register for CPU time */
static uint64_t cortexm_cputime_getres(void)
{
uint64_t ret = 1000UL * 1000 * 1000;
ret = (ret * (1000UL * 1000)) / SystemCoreClock;
return ret;
}
static uint64_t cortexm_cputime_gettime(void)
{
#ifdef PKG_USING_PERF_COUNTER
return get_system_ticks();
#else
return DWT->CYCCNT;
#endif
}
const static struct rt_clock_cputime_ops _cortexm_ops =
{
cortexm_cputime_getres,
cortexm_cputime_gettime
};
int cortexm_cputime_init(void)
{
#ifdef PKG_USING_PERF_COUNTER
clock_cpu_setops(&_cortexm_ops);
#else
/* check support bit */
if ((DWT->CTRL & (1UL << DWT_CTRL_NOCYCCNT_Pos)) == 0)
{
/* enable trace*/
CoreDebug->DEMCR |= (1UL << CoreDebug_DEMCR_TRCENA_Pos);
/* whether cycle counter not enabled */
if ((DWT->CTRL & (1UL << DWT_CTRL_CYCCNTENA_Pos)) == 0)
{
/* enable cycle counter */
DWT->CTRL |= (1UL << DWT_CTRL_CYCCNTENA_Pos);
}
clock_cpu_setops(&_cortexm_ops);
}
#endif /* PKG_USING_PERF_COUNTER */
return 0;
}
INIT_BOARD_EXPORT(cortexm_cputime_init);

37
rt-thread/components/drivers/cputime/cputime_riscv.c Normal file
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#include <rthw.h>
#include <rtdevice.h>
#include <rtthread.h>
#include <board.h>
/* Use Cycle counter of Data Watchpoint and Trace Register for CPU time */
static uint64_t riscv_cputime_getres(void)
{
uint64_t ret = 1000UL * 1000 * 1000;
ret = (ret * (1000UL * 1000)) / CPUTIME_TIMER_FREQ;
return ret;
}
static uint64_t riscv_cputime_gettime(void)
{
uint64_t time_elapsed;
__asm__ __volatile__(
"rdtime %0"
: "=r"(time_elapsed));
return time_elapsed;
}
const static struct rt_clock_cputime_ops _riscv_ops =
{
riscv_cputime_getres,
riscv_cputime_gettime
};
int riscv_cputime_init(void)
{
clock_cpu_setops(&_riscv_ops);
return 0;
}
INIT_BOARD_EXPORT(riscv_cputime_init);

339
rt-thread/components/drivers/cputime/cputimer.c Normal file
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@@ -0,0 +1,339 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-02-13 zhkag first version
* 2023-04-03 xqyjlj fix cputimer in multithreading
*/
#include <rtdevice.h>
#include <rthw.h>
#include <rtthread.h>
static rt_list_t _cputimer_list = RT_LIST_OBJECT_INIT(_cputimer_list);
static struct rt_cputimer *_cputimer_nowtimer = RT_NULL;
static void _cputime_sleep_timeout(void *parameter)
{
struct rt_semaphore *sem;
sem = (struct rt_semaphore *)parameter;
rt_sem_release(sem);
}
static void _cputime_timeout_callback(void *parameter)
{
struct rt_cputimer *timer;
timer = (struct rt_cputimer *)parameter;
rt_base_t level;
level = rt_hw_interrupt_disable();
_cputimer_nowtimer = RT_NULL;
rt_list_remove(&(timer->row));
rt_hw_interrupt_enable(level);
timer->timeout_func(timer->parameter);
if (&_cputimer_list != _cputimer_list.prev)
{
struct rt_cputimer *t;
t = rt_list_entry(_cputimer_list.next, struct rt_cputimer, row);
clock_cpu_settimeout(t->timeout_tick, _cputime_timeout_callback, t);
}
else
{
clock_cpu_settimeout(RT_NULL, RT_NULL, RT_NULL);
}
}
static void _set_next_timeout()
{
struct rt_cputimer *t;
if (&_cputimer_list != _cputimer_list.prev)
{
t = rt_list_entry((&_cputimer_list)->next, struct rt_cputimer, row);
if (_cputimer_nowtimer != RT_NULL)
{
if (t != _cputimer_nowtimer && t->timeout_tick < _cputimer_nowtimer->timeout_tick)
{
_cputimer_nowtimer = t;
clock_cpu_settimeout(t->timeout_tick, _cputime_timeout_callback, t);
}
}
else
{
_cputimer_nowtimer = t;
clock_cpu_settimeout(t->timeout_tick, _cputime_timeout_callback, t);
}
}
else
{
_cputimer_nowtimer = RT_NULL;
clock_cpu_settimeout(RT_NULL, RT_NULL, RT_NULL);
}
}
void rt_cputimer_init(rt_cputimer_t timer,
const char *name,
void (*timeout)(void *parameter),
void *parameter,
rt_uint64_t tick,
rt_uint8_t flag)
{
/* parameter check */
RT_ASSERT(timer != RT_NULL);
RT_ASSERT(timeout != RT_NULL);
RT_ASSERT(clock_cpu_issettimeout() != RT_FALSE);
/* set flag */
timer->parent.flag = flag;
/* set deactivated */
timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED;
timer->timeout_func = timeout;
timer->parameter = parameter;
timer->timeout_tick = tick + clock_cpu_gettime();
timer->init_tick = tick;
rt_list_init(&(timer->row));
rt_sem_init(&(timer->sem), "cputime", 0, RT_IPC_FLAG_PRIO);
}
rt_err_t rt_cputimer_delete(rt_cputimer_t timer)
{
rt_base_t level;
/* parameter check */
RT_ASSERT(timer != RT_NULL);
RT_ASSERT(clock_cpu_issettimeout() != RT_FALSE);
/* disable interrupt */
level = rt_hw_interrupt_disable();
rt_list_remove(&timer->row);
/* stop timer */
timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED;
/* enable interrupt */
rt_hw_interrupt_enable(level);
_set_next_timeout();
return RT_EOK;
}
rt_err_t rt_cputimer_start(rt_cputimer_t timer)
{
rt_list_t *timer_list;
rt_base_t level;
/* parameter check */
RT_ASSERT(timer != RT_NULL);
RT_ASSERT(clock_cpu_issettimeout() != RT_FALSE);
/* stop timer firstly */
level = rt_hw_interrupt_disable();
/* remove timer from list */
rt_list_remove(&timer->row);
/* change status of timer */
timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED;
timer_list = &_cputimer_list;
for (; timer_list != _cputimer_list.prev;
timer_list = timer_list->next)
{
struct rt_cputimer *t;
rt_list_t *p = timer_list->next;
t = rt_list_entry(p, struct rt_cputimer, row);
if ((t->timeout_tick - timer->timeout_tick) == 0)
{
continue;
}
else if ((t->timeout_tick - timer->timeout_tick) < 0x7fffffffffffffff)
{
break;
}
}
rt_list_insert_after(timer_list, &(timer->row));
timer->parent.flag |= RT_TIMER_FLAG_ACTIVATED;
_set_next_timeout();
/* enable interrupt */
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t rt_cputimer_stop(rt_cputimer_t timer)
{
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
/* timer check */
RT_ASSERT(timer != RT_NULL);
RT_ASSERT(clock_cpu_issettimeout() != RT_FALSE);
if (!(timer->parent.flag & RT_TIMER_FLAG_ACTIVATED))
{
rt_hw_interrupt_enable(level);
return -RT_ERROR;
}
rt_list_remove(&timer->row);
/* change status */
timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED;
_set_next_timeout();
/* enable interrupt */
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t rt_cputimer_control(rt_cputimer_t timer, int cmd, void *arg)
{
rt_base_t level;
/* parameter check */
RT_ASSERT(timer != RT_NULL);
RT_ASSERT(clock_cpu_issettimeout() != RT_FALSE);
level = rt_hw_interrupt_disable();
switch (cmd)
{
case RT_TIMER_CTRL_GET_TIME:
*(rt_uint64_t *)arg = timer->init_tick;
break;
case RT_TIMER_CTRL_SET_TIME:
RT_ASSERT((*(rt_uint64_t *)arg) < 0x7fffffffffffffff);
timer->init_tick = *(rt_uint64_t *)arg;
timer->timeout_tick = *(rt_uint64_t *)arg + clock_cpu_gettime();
break;
case RT_TIMER_CTRL_SET_ONESHOT:
timer->parent.flag &= ~RT_TIMER_FLAG_PERIODIC;
break;
case RT_TIMER_CTRL_SET_PERIODIC:
timer->parent.flag |= RT_TIMER_FLAG_PERIODIC;
break;
case RT_TIMER_CTRL_GET_STATE:
if (timer->parent.flag & RT_TIMER_FLAG_ACTIVATED)
{
/*timer is start and run*/
*(rt_uint32_t *)arg = RT_TIMER_FLAG_ACTIVATED;
}
else
{
/*timer is stop*/
*(rt_uint32_t *)arg = RT_TIMER_FLAG_DEACTIVATED;
}
break;
case RT_TIMER_CTRL_GET_REMAIN_TIME:
*(rt_uint64_t *)arg = timer->timeout_tick;
break;
case RT_TIMER_CTRL_GET_FUNC:
arg = (void *)timer->timeout_func;
break;
case RT_TIMER_CTRL_SET_FUNC:
timer->timeout_func = (void (*)(void *))arg;
break;
case RT_TIMER_CTRL_GET_PARM:
*(void **)arg = timer->parameter;
break;
case RT_TIMER_CTRL_SET_PARM:
timer->parameter = arg;
break;
default:
break;
}
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t rt_cputimer_detach(rt_cputimer_t timer)
{
rt_base_t level;
/* parameter check */
RT_ASSERT(timer != RT_NULL);
RT_ASSERT(clock_cpu_issettimeout() != RT_FALSE);
/* disable interrupt */
level = rt_hw_interrupt_disable();
rt_list_remove(&timer->row);
/* stop timer */
timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED;
_set_next_timeout();
/* enable interrupt */
rt_hw_interrupt_enable(level);
rt_sem_detach(&(timer->sem));
return RT_EOK;
}
rt_err_t rt_cputime_sleep(rt_uint64_t tick)
{
rt_base_t level;
struct rt_cputimer cputimer;
if (!clock_cpu_issettimeout())
{
rt_int32_t ms = clock_cpu_millisecond(tick);
return rt_thread_delay(rt_tick_from_millisecond(ms));
}
if (tick == 0)
{
return -RT_EINVAL;
}
rt_cputimer_init(&cputimer, "cputime_sleep", _cputime_sleep_timeout, &(cputimer.sem), tick,
RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_SOFT_TIMER);
/* disable interrupt */
level = rt_hw_interrupt_disable();
rt_cputimer_start(&cputimer); /* reset the timeout of thread timer and start it */
rt_hw_interrupt_enable(level);
rt_sem_take_interruptible(&(cputimer.sem), RT_WAITING_FOREVER);
rt_cputimer_detach(&cputimer);
return RT_EOK;
}
rt_err_t rt_cputime_ndelay(rt_uint64_t ns)
{
uint64_t unit = clock_cpu_getres();
return rt_cputime_sleep(ns * (1000UL * 1000) / unit);
}
rt_err_t rt_cputime_udelay(rt_uint64_t us)
{
return rt_cputime_ndelay(us * 1000);
}
rt_err_t rt_cputime_mdelay(rt_uint64_t ms)
{
return rt_cputime_ndelay(ms * 1000000);
}

3
rt-thread/components/drivers/graphic/Kconfig Normal file
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@@ -0,0 +1,3 @@
config RT_USING_LCD
bool "Using LCD graphic drivers"
default n

165
rt-thread/components/drivers/hwcrypto/Kconfig Normal file
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@@ -0,0 +1,165 @@
menuconfig RT_USING_HWCRYPTO
bool "Using Hardware Crypto drivers"
default n
if RT_USING_HWCRYPTO
config RT_HWCRYPTO_DEFAULT_NAME
string "Hardware crypto device name"
default "hwcryto"
config RT_HWCRYPTO_IV_MAX_SIZE
int "IV max size"
default "16"
config RT_HWCRYPTO_KEYBIT_MAX_SIZE
int "Key max bit length"
default 256
config RT_HWCRYPTO_USING_GCM
bool "Using Hardware GCM"
default n
config RT_HWCRYPTO_USING_AES
bool "Using Hardware AES"
default n
if RT_HWCRYPTO_USING_AES
config RT_HWCRYPTO_USING_AES_ECB
bool "Using Hardware AES ECB mode"
default y
config RT_HWCRYPTO_USING_AES_CBC
bool "Using Hardware AES CBC mode"
default n
config RT_HWCRYPTO_USING_AES_CFB
bool "Using Hardware AES CFB mode"
default n
config RT_HWCRYPTO_USING_AES_CTR
bool "Using Hardware AES CTR mode"
default n
config RT_HWCRYPTO_USING_AES_OFB
bool "Using Hardware AES OFB mode"
default n
endif
config RT_HWCRYPTO_USING_DES
bool "Using Hardware DES"
default n
if RT_HWCRYPTO_USING_DES
config RT_HWCRYPTO_USING_DES_ECB
bool "Using Hardware DES ECB mode"
default y
config RT_HWCRYPTO_USING_DES_CBC
bool "Using Hardware DES CBC mode"
default n
endif
config RT_HWCRYPTO_USING_3DES
bool "Using Hardware 3DES"
default n
if RT_HWCRYPTO_USING_3DES
config RT_HWCRYPTO_USING_3DES_ECB
bool "Using Hardware 3DES ECB mode"
default y
config RT_HWCRYPTO_USING_3DES_CBC
bool "Using Hardware 3DES CBC mode"
default n
endif
config RT_HWCRYPTO_USING_RC4
bool "Using Hardware RC4"
default n
config RT_HWCRYPTO_USING_MD5
bool "Using Hardware MD5"
default n
config RT_HWCRYPTO_USING_SHA1
bool "Using Hardware SHA1"
default n
config RT_HWCRYPTO_USING_SHA2
bool "Using Hardware SHA2"
default n
if RT_HWCRYPTO_USING_SHA2
config RT_HWCRYPTO_USING_SHA2_224
bool "Using Hardware SHA2_224 mode"
default n
config RT_HWCRYPTO_USING_SHA2_256
bool "Using Hardware SHA2_256 mode"
default y
config RT_HWCRYPTO_USING_SHA2_384
bool "Using Hardware SHA2_384 mode"
default n
config RT_HWCRYPTO_USING_SHA2_512
bool "Using Hardware SHA2_512 mode"
default n
endif
config RT_HWCRYPTO_USING_RNG
bool "Using Hardware RNG"
default n
config RT_HWCRYPTO_USING_CRC
bool "Using Hardware CRC"
default n
if RT_HWCRYPTO_USING_CRC
config RT_HWCRYPTO_USING_CRC_07
bool "Using Hardware CRC-8 0x07 polynomial"
default n
config RT_HWCRYPTO_USING_CRC_8005
bool "Using Hardware CRC-16 0x8005 polynomial"
default n
config RT_HWCRYPTO_USING_CRC_1021
bool "Using Hardware CRC-16 0x1021 polynomial"
default n
config RT_HWCRYPTO_USING_CRC_3D65
bool "Using Hardware CRC-16 0x3D65 polynomial"
default n
config RT_HWCRYPTO_USING_CRC_04C11DB7
bool "Using Hardware CRC-32 0x04C11DB7 polynomial"
default n
endif
config RT_HWCRYPTO_USING_BIGNUM
bool "Using Hardware bignum"
default n
if RT_HWCRYPTO_USING_BIGNUM
config RT_HWCRYPTO_USING_BIGNUM_EXPTMOD
bool "Using Hardware bignum expt_mod operation"
default y
config RT_HWCRYPTO_USING_BIGNUM_MULMOD
bool "Using Hardware bignum mul_mod operation"
default y
config RT_HWCRYPTO_USING_BIGNUM_MUL
bool "Using Hardware bignum mul operation"
default n
config RT_HWCRYPTO_USING_BIGNUM_ADD
bool "Using Hardware bignum add operation"
default n
config RT_HWCRYPTO_USING_BIGNUM_SUB
bool "Using Hardware bignum sub operation"
default n
endif
endif

34
rt-thread/components/drivers/hwcrypto/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd, str(Dir('#'))]
src = ['hwcrypto.c']
if (GetDepend(['RT_HWCRYPTO_USING_AES']) or
GetDepend(['RT_HWCRYPTO_USING_DES']) or
GetDepend(['RT_HWCRYPTO_USING_3DES']) or
GetDepend(['RT_HWCRYPTO_USING_RC4'])):
src += ['hw_symmetric.c']
if GetDepend(['RT_HWCRYPTO_USING_GCM']):
src += ['hw_gcm.c']
if (GetDepend(['RT_HWCRYPTO_USING_MD5']) or
GetDepend(['RT_HWCRYPTO_USING_SHA1']) or
GetDepend(['RT_HWCRYPTO_USING_SHA2'])):
src += ['hw_hash.c']
if GetDepend(['RT_HWCRYPTO_USING_RNG']):
src += ['hw_rng.c']
if GetDepend(['RT_HWCRYPTO_USING_CRC']):
src += ['hw_crc.c']
if GetDepend(['RT_HWCRYPTO_USING_BIGNUM']):
src += ['hw_bignum.c']
group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_HWCRYPTO'], CPPPATH = CPPPATH)
Return('group')

318
rt-thread/components/drivers/hwcrypto/hw_bignum.c Normal file
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@@ -0,0 +1,318 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-25 tyx the first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <hw_bignum.h>
static struct rt_hwcrypto_ctx *bignum_default;
rt_inline rt_err_t hwcrypto_bignum_dev_is_init(void)
{
struct rt_hwcrypto_device *dev;
if (bignum_default)
{
return RT_EOK;
}
dev = rt_hwcrypto_dev_default();
if (dev == RT_NULL)
{
return -RT_ERROR;
}
return rt_hwcrypto_bignum_default(dev);
}
/**
* @brief Setting bignum default devices
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_bignum_default(struct rt_hwcrypto_device *device)
{
if (bignum_default)
{
rt_hwcrypto_ctx_destroy(bignum_default);
bignum_default = RT_NULL;
}
if (device == RT_NULL)
{
return RT_EOK;
}
bignum_default = rt_hwcrypto_ctx_create(device, HWCRYPTO_TYPE_BIGNUM, sizeof(struct hwcrypto_bignum));
if (bignum_default == RT_NULL)
{
return -RT_ERROR;
}
return RT_EOK;
}
/**
* @brief Init bignum obj
*
* @param n bignum obj
*/
void rt_hwcrypto_bignum_init(struct hw_bignum_mpi *n)
{
if(n == RT_NULL)
return;
n->sign = 1;
n->total = 0;
n->p = RT_NULL;
}
/**
* @brief free a bignum obj
*
* @param Pointer to bignum obj
*/
void rt_hwcrypto_bignum_free(struct hw_bignum_mpi *n)
{
if (n)
{
rt_memset(n->p, 0xFF, n->total);
rt_free(n->p);
n->sign = 0;
n->total = 0;
n->p = RT_NULL;
}
}
/**
* @brief Get length of bignum as an unsigned binary buffer
*
* @param n bignum obj
*
* @return binary buffer length
*/
int rt_hwcrypto_bignum_get_len(const struct hw_bignum_mpi *n)
{
int tmp_len, total;
if (n == RT_NULL || n->p == RT_NULL)
{
return 0;
}
tmp_len = 0;
total = n->total;
while ((total > 0) && (n->p[total - 1] == 0))
{
tmp_len++;
total--;
}
return n->total - tmp_len;
}
/**
* @brief Export n into unsigned binary data, big endian
*
* @param n bignum obj
* @param buf Buffer for the binary number
* @param len Length of the buffer
*
* @return export bin length
*/
int rt_hwcrypto_bignum_export_bin(struct hw_bignum_mpi *n, rt_uint8_t *buf, int len)
{
int cp_len, i, j;
if (n == RT_NULL || buf == RT_NULL)
{
return 0;
}
rt_memset(buf, 0, len);
cp_len = (int)n->total > len ? len : (int)n->total;
for(i = cp_len, j = 0; i > 0; i--, j++)
{
buf[i - 1] = n->p[j];
}
return cp_len;
}
/**
* @brief Import n from unsigned binary data, big endian
*
* @param n bignum obj
* @param buf Buffer for the binary number
* @param len Length of the buffer
*
* @return import length.
*/
int rt_hwcrypto_bignum_import_bin(struct hw_bignum_mpi *n, rt_uint8_t *buf, int len)
{
int cp_len, i, j;
void *temp_p;
if (n == RT_NULL || buf == RT_NULL)
{
return 0;
}
if ((int)n->total < len)
{
temp_p = rt_malloc(len);
if (temp_p == RT_NULL)
{
return 0;
}
rt_free(n->p);
n->p = temp_p;
n->total = len;
}
n->sign = 1;
rt_memset(n->p, 0, n->total);
cp_len = (int)n->total > len ? len : n->total;
for(i = cp_len, j = 0; i > 0; i--, j++)
{
n->p[j] = buf[i - 1];
}
return cp_len;
}
/**
* @brief x = a + b
*
* @param a bignum obj
* @param b bignum obj
* @param c bignum obj
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_bignum_add(struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b)
{
struct hwcrypto_bignum *bignum_ctx;
if (hwcrypto_bignum_dev_is_init() != RT_EOK)
{
return -RT_ERROR;
}
bignum_ctx = (struct hwcrypto_bignum *)bignum_default;
if (bignum_ctx->ops->add)
{
return bignum_ctx->ops->add(bignum_ctx, x, a, b);
}
return -RT_ERROR;
}
/**
* @brief x = a - b
*
* @param a bignum obj
* @param b bignum obj
* @param c bignum obj
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_bignum_sub(struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b)
{
struct hwcrypto_bignum *bignum_ctx;
if (hwcrypto_bignum_dev_is_init() != RT_EOK)
{
return -RT_ERROR;
}
bignum_ctx = (struct hwcrypto_bignum *)bignum_default;
if (bignum_ctx->ops->sub)
{
return bignum_ctx->ops->sub(bignum_ctx, x, a, b);
}
return -RT_ERROR;
}
/**
* @brief x = a * b
*
* @param a bignum obj
* @param b bignum obj
* @param c bignum obj
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_bignum_mul(struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b)
{
struct hwcrypto_bignum *bignum_ctx;
if (hwcrypto_bignum_dev_is_init() != RT_EOK)
{
return -RT_ERROR;
}
bignum_ctx = (struct hwcrypto_bignum *)bignum_default;
if (bignum_ctx->ops->mul)
{
return bignum_ctx->ops->mul(bignum_ctx, x, a, b);
}
return -RT_ERROR;
}
/**
* @brief x = a * b (mod c)
*
* @param a bignum obj
* @param b bignum obj
* @param c bignum obj
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_bignum_mulmod(struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b,
const struct hw_bignum_mpi *c)
{
struct hwcrypto_bignum *bignum_ctx;
if (hwcrypto_bignum_dev_is_init() != RT_EOK)
{
return -RT_ERROR;
}
bignum_ctx = (struct hwcrypto_bignum *)bignum_default;
if (bignum_ctx->ops->mulmod)
{
return bignum_ctx->ops->mulmod(bignum_ctx, x, a, b, c);
}
return -RT_ERROR;
}
/**
* @brief x = a ^ b (mod c)
*
* @param a bignum obj
* @param b bignum obj
* @param c bignum obj
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_bignum_exptmod(struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b,
const struct hw_bignum_mpi *c)
{
struct hwcrypto_bignum *bignum_ctx;
if (hwcrypto_bignum_dev_is_init() != RT_EOK)
{
return -RT_ERROR;
}
bignum_ctx = (struct hwcrypto_bignum *)bignum_default;
if (bignum_ctx->ops->exptmod)
{
return bignum_ctx->ops->exptmod(bignum_ctx, x, a, b, c);
}
return -RT_ERROR;
}

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-25 tyx the first version
*/
#ifndef __HW_BIGNUM_H__
#define __HW_BIGNUM_H__
#include <hwcrypto.h>
#ifdef __cplusplus
extern "C" {
#endif
struct hwcrypto_bignum;
/* bignum obj */
struct hw_bignum_mpi
{
int sign; /**< integer sign. -1 or 1 */
rt_size_t total; /**< total of limbs */
rt_uint8_t *p; /**< pointer to limbs */
};
struct hwcrypto_bignum_ops
{
rt_err_t (*add)(struct hwcrypto_bignum *bignum_ctx,
struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b); /**< x = a + b */
rt_err_t (*sub)(struct hwcrypto_bignum *bignum_ctx,
struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b); /**< x = a - b */
rt_err_t (*mul)(struct hwcrypto_bignum *bignum_ctx,
struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b); /**< x = a * b */
rt_err_t (*mulmod)(struct hwcrypto_bignum *bignum_ctx,
struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b,
const struct hw_bignum_mpi *c); /**< x = a * b (mod c) */
rt_err_t (*exptmod)(struct hwcrypto_bignum *bignum_ctx,
struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b,
const struct hw_bignum_mpi *c); /**< x = a ^ b (mod c) */
};
/**
* @brief bignum context. Hardware driver usage
*/
struct hwcrypto_bignum
{
struct rt_hwcrypto_ctx parent; /**< Inheritance from hardware crypto context */
const struct hwcrypto_bignum_ops *ops; /**< !! Hardware initializes this value when creating context !! */
};
/**
* @brief Setting bignum default devices
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_bignum_default(struct rt_hwcrypto_device *device);
/**
* @brief Init bignum obj
*/
void rt_hwcrypto_bignum_init(struct hw_bignum_mpi *n);
/**
* @brief free a bignum obj
*
* @param Pointer to bignum obj
*/
void rt_hwcrypto_bignum_free(struct hw_bignum_mpi *n);
/**
* @brief Get length of bignum as an unsigned binary buffer
*
* @param n bignum obj
*
* @return binary buffer Length
*/
int rt_hwcrypto_bignum_get_len(const struct hw_bignum_mpi *n);
/**
* @brief Export n into unsigned binary data, big endian
*
* @param n bignum obj
* @param buf Buffer for the binary number
* @param len Length of the buffer
*
* @return export bin length
*/
int rt_hwcrypto_bignum_export_bin(struct hw_bignum_mpi *n, rt_uint8_t *buf, int len);
/**
* @brief Import n from unsigned binary data, big endian
*
* @param n bignum obj
* @param buf Buffer for the binary number
* @param len Length of the buffer
*
* @return import length.
*/
int rt_hwcrypto_bignum_import_bin(struct hw_bignum_mpi *n, rt_uint8_t *buf, int len);
/**
* @brief x = a + b
*
* @param a bignum obj
* @param b bignum obj
* @param c bignum obj
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_bignum_add(struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b);
/**
* @brief x = a - b
*
* @param a bignum obj
* @param b bignum obj
* @param c bignum obj
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_bignum_sub(struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b);
/**
* @brief x = a * b
*
* @param a bignum obj
* @param b bignum obj
* @param c bignum obj
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_bignum_mul(struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b);
/**
* @brief x = a * b (mod c)
*
* @param a bignum obj
* @param b bignum obj
* @param c bignum obj
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_bignum_mulmod(struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b,
const struct hw_bignum_mpi *c);
/**
* @brief x = a ^ b (mod c)
*
* @param a bignum obj
* @param b bignum obj
* @param c bignum obj
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_bignum_exptmod(struct hw_bignum_mpi *x,
const struct hw_bignum_mpi *a,
const struct hw_bignum_mpi *b,
const struct hw_bignum_mpi *c);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-25 tyx the first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <hw_crc.h>
/**
* @brief Creating CRC Context
*
* @param device Hardware crypto device
* @param mode Setting default mode or custom mode
*
* @return CRC context
*/
struct rt_hwcrypto_ctx *rt_hwcrypto_crc_create(struct rt_hwcrypto_device *device,
hwcrypto_crc_mode mode)
{
struct hwcrypto_crc *crc_ctx;
crc_ctx = (struct hwcrypto_crc *)rt_hwcrypto_ctx_create(device, HWCRYPTO_TYPE_CRC, sizeof(struct hwcrypto_crc));
if (crc_ctx == RT_NULL)
{
return RT_NULL;
}
switch (mode)
{
case HWCRYPTO_CRC_CRC8:
{
struct hwcrypto_crc_cfg temp = HWCRYPTO_CRC8_CFG;
crc_ctx->crc_cfg = temp;
break;
}
case HWCRYPTO_CRC_CRC16:
{
struct hwcrypto_crc_cfg temp = HWCRYPTO_CRC16_CFG;
crc_ctx->crc_cfg = temp;
break;
}
case HWCRYPTO_CRC_CRC32:
{
struct hwcrypto_crc_cfg temp = HWCRYPTO_CRC32_CFG;
crc_ctx->crc_cfg = temp;
break;
}
case HWCRYPTO_CRC_CCITT:
{
struct hwcrypto_crc_cfg temp = HWCRYPTO_CRC_CCITT_CFG;
crc_ctx->crc_cfg = temp;
break;
}
case HWCRYPTO_CRC_DNP:
{
struct hwcrypto_crc_cfg temp = HWCRYPTO_CRC_DNP_CFG;
crc_ctx->crc_cfg = temp;
break;
}
default:
break;
}
return &crc_ctx->parent;
}
/**
* @brief Destroy CRC Context
*
* @param ctx CRC context
*/
void rt_hwcrypto_crc_destroy(struct rt_hwcrypto_ctx *ctx)
{
rt_hwcrypto_ctx_destroy(ctx);
}
/**
* @brief Processing a packet of data
*
* @param ctx CRC context
* @param input Data buffer to be Processed
* @param length Data Buffer length
*
* @return CRC value
*/
rt_uint32_t rt_hwcrypto_crc_update(struct rt_hwcrypto_ctx *ctx,
const rt_uint8_t *input,
rt_size_t length)
{
struct hwcrypto_crc *crc_ctx = (struct hwcrypto_crc *)ctx;
if (ctx && crc_ctx->ops->update)
{
return crc_ctx->ops->update(crc_ctx, input, length);
}
return 0;
}
/**
* @brief CRC context configuration
*
* @param ctx CRC context
* @param cfg CRC config
*/
void rt_hwcrypto_crc_cfg(struct rt_hwcrypto_ctx *ctx,
struct hwcrypto_crc_cfg *cfg)
{
if (cfg)
{
((struct hwcrypto_crc *)ctx)->crc_cfg = *cfg;
}
}

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-25 tyx the first version
*/
#ifndef __HW_CRC_H__
#define __HW_CRC_H__
#include <hwcrypto.h>
#define CRC_FLAG_REFIN (0x1 << 0)
#define CRC_FLAG_REFOUT (0x1 << 1)
#define HWCRYPTO_CRC8_CFG \
{ \
.last_val = 0x00, \
.poly = 0x07, \
.width = 8, \
.xorout = 0x00, \
.flags = 0, \
}
#define HWCRYPTO_CRC16_CFG \
{ \
.last_val = 0x0000, \
.poly = 0x8005, \
.width = 16, \
.xorout = 0x0000, \
.flags = 0, \
}
#define HWCRYPTO_CRC32_CFG \
{ \
.last_val = 0x00000000, \
.poly = 0x04C11DB7, \
.width = 32, \
.xorout = 0x00000000, \
.flags = 0, \
}
#define HWCRYPTO_CRC_CCITT_CFG \
{ \
.last_val = 0x0000, \
.poly = 0x1021, \
.width = 16, \
.xorout = 0x0000, \
.flags = CRC_FLAG_REFIN | CRC_FLAG_REFOUT, \
}
#define HWCRYPTO_CRC_DNP_CFG \
{ \
.last_val = 0x0000, \
.poly = 0x3D65, \
.width = 16, \
.xorout = 0xffff, \
.flags = CRC_FLAG_REFIN | CRC_FLAG_REFOUT, \
}
#ifdef __cplusplus
extern "C" {
#endif
struct hwcrypto_crc;
typedef enum
{
HWCRYPTO_CRC_CUSTOM, /**< Custom CRC mode */
HWCRYPTO_CRC_CRC8, /**< poly : 0x07 */
HWCRYPTO_CRC_CRC16, /**< poly : 0x8005 */
HWCRYPTO_CRC_CRC32, /**< poly : 0x04C11DB7 */
HWCRYPTO_CRC_CCITT, /**< poly : 0x1021 */
HWCRYPTO_CRC_DNP, /**< poly : 0x3D65 */
} hwcrypto_crc_mode;
struct hwcrypto_crc_cfg
{
rt_uint32_t last_val; /**< Last CRC value cache */
rt_uint32_t poly; /**< CRC polynomial */
rt_uint16_t width; /**< CRC value width */
rt_uint32_t xorout; /**< Result XOR Value */
rt_uint16_t flags; /**< Input or output data reverse. CRC_FLAG_REFIN or CRC_FLAG_REFOUT */
};
struct hwcrypto_crc_ops
{
rt_uint32_t (*update)(struct hwcrypto_crc *ctx,
const rt_uint8_t *in, rt_size_t length); /**< Perform a CRC calculation. return CRC value */
};
/**
* @brief CRC context. Hardware driver usage
*/
struct hwcrypto_crc
{
struct rt_hwcrypto_ctx parent; /**< Inherited from the standard device */
struct hwcrypto_crc_cfg crc_cfg; /**< CRC configure */
const struct hwcrypto_crc_ops *ops; /**< !! Hardware initializes this value when creating context !! */
};
/**
* @brief Creating CRC Context
*
* @param device Hardware crypto device
* @param mode Setting default mode or custom mode
*
* @return CRC context
*/
struct rt_hwcrypto_ctx *rt_hwcrypto_crc_create(struct rt_hwcrypto_device *device,
hwcrypto_crc_mode mode);
/**
* @brief Destroy CRC Context
*
* @param ctx CRC context
*/
void rt_hwcrypto_crc_destroy(struct rt_hwcrypto_ctx *ctx);
/**
* @brief Processing a packet of data
*
* @param ctx CRC context
* @param input Data buffer to be Processed
* @param length Data Buffer length
*
* @return CRC value
*/
rt_uint32_t rt_hwcrypto_crc_update(struct rt_hwcrypto_ctx *ctx,
const rt_uint8_t *input, rt_size_t length);
/**
* @brief CRC context configuration
*
* @param ctx CRC context
* @param cfg CRC config
*/
void rt_hwcrypto_crc_cfg(struct rt_hwcrypto_ctx *ctx,
struct hwcrypto_crc_cfg *cfg);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-05-14 tyx the first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <hw_gcm.h>
/**
* @brief Creating GCM Context
*
* @param device Hardware crypto device
* @param type Type of symmetric crypto context
*
* @return GCM context
*/
struct rt_hwcrypto_ctx *rt_hwcrypto_gcm_create(struct rt_hwcrypto_device *device,
hwcrypto_type crypt_type)
{
struct rt_hwcrypto_ctx *ctx;
ctx = rt_hwcrypto_ctx_create(device, HWCRYPTO_TYPE_GCM, sizeof(struct hwcrypto_gcm));
if (ctx)
{
((struct hwcrypto_gcm *)ctx)->crypt_type = crypt_type;
}
return ctx;
}
/**
* @brief Destroy GCM Context
*
* @param ctx GCM context
*/
void rt_hwcrypto_gcm_destroy(struct rt_hwcrypto_ctx *ctx)
{
rt_hwcrypto_ctx_destroy(ctx);
}
/**
* @brief This function starts a GCM encryption or decryption operation
*
* @param ctx GCM context
* @param add The buffer holding the additional data
* @param add_len The length of the additional data
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_gcm_start(struct rt_hwcrypto_ctx *ctx, const rt_uint8_t *add,
rt_size_t add_len)
{
struct hwcrypto_gcm *gcm_ctx = (struct hwcrypto_gcm *)ctx;
if (gcm_ctx && gcm_ctx->ops->start)
{
return gcm_ctx->ops->start(gcm_ctx, add, add_len);
}
return -RT_EINVAL;
}
/**
* @brief This function finishes the GCM operation and generates the authentication tag
*
* @param ctx GCM context
* @param tag The buffer for holding the tag
* @param tag_len The length of the tag to generate
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_gcm_finish(struct rt_hwcrypto_ctx *ctx, const rt_uint8_t *tag,
rt_size_t tag_len)
{
struct hwcrypto_gcm *gcm_ctx = (struct hwcrypto_gcm *)ctx;
if (gcm_ctx && gcm_ctx->ops->finish)
{
return gcm_ctx->ops->finish(gcm_ctx, tag, tag_len);
}
return -RT_EINVAL;
}
/**
* @brief This function performs a symmetric encryption or decryption operation
*
* @param ctx GCM context
* @param mode Operation mode. HWCRYPTO_MODE_ENCRYPT or HWCRYPTO_MODE_DECRYPT
* @param length The length of the input data in Bytes. This must be a multiple of the block size
* @param in The buffer holding the input data
* @param out The buffer holding the output data
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_gcm_crypt(struct rt_hwcrypto_ctx *ctx, hwcrypto_mode mode,
rt_size_t length, const rt_uint8_t *in, rt_uint8_t *out)
{
return rt_hwcrypto_symmetric_crypt(ctx, mode, length, in, out);
}
/**
* @brief Set Symmetric Encryption and Decryption Key
*
* @param ctx GCM context
* @param key The crypto key
* @param bitlen The crypto key bit length
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_gcm_setkey(struct rt_hwcrypto_ctx *ctx,
const rt_uint8_t *key, rt_uint32_t bitlen)
{
return rt_hwcrypto_symmetric_setkey(ctx, key, bitlen);
}
/**
* @brief Get Symmetric Encryption and Decryption Key
*
* @param ctx GCM context
* @param key The crypto key buffer
* @param bitlen The crypto key bit length
*
* @return Key length of copy
*/
rt_err_t rt_hwcrypto_gcm_getkey(struct rt_hwcrypto_ctx *ctx,
rt_uint8_t *key, rt_uint32_t bitlen)
{
return rt_hwcrypto_symmetric_getkey(ctx, key, bitlen);
}
/**
* @brief Set Symmetric Encryption and Decryption initialization vector
*
* @param ctx GCM context
* @param iv The crypto initialization vector
* @param len The crypto initialization vector length
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_gcm_setiv(struct rt_hwcrypto_ctx *ctx,
const rt_uint8_t *iv, rt_size_t len)
{
return rt_hwcrypto_symmetric_setiv(ctx, iv, len);
}
/**
* @brief Get Symmetric Encryption and Decryption initialization vector
*
* @param ctx GCM context
* @param iv The crypto initialization vector buffer
* @param len The crypto initialization vector buffer length
*
* @return IV length of copy
*/
rt_err_t rt_hwcrypto_gcm_getiv(struct rt_hwcrypto_ctx *ctx,
rt_uint8_t *iv, rt_size_t len)
{
return rt_hwcrypto_symmetric_getiv(ctx, iv, len);
}
/**
* @brief Set offset in initialization vector
*
* @param ctx GCM context
* @param iv_off The offset in IV
*/
void rt_hwcrypto_gcm_set_ivoff(struct rt_hwcrypto_ctx *ctx, rt_int32_t iv_off)
{
rt_hwcrypto_symmetric_set_ivoff(ctx, iv_off);
}
/**
* @brief Get offset in initialization vector
*
* @param ctx GCM context
* @param iv_off It must point to a valid memory
*/
void rt_hwcrypto_gcm_get_ivoff(struct rt_hwcrypto_ctx *ctx, rt_int32_t *iv_off)
{
rt_hwcrypto_symmetric_get_ivoff(ctx, iv_off);
}
/**
* @brief This function copy GCM context
*
* @param des The destination GCM context
* @param src The GCM context to be copy
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_gcm_cpy(struct rt_hwcrypto_ctx *des,
const struct rt_hwcrypto_ctx *src)
{
struct hwcrypto_gcm *gcm_des = (struct hwcrypto_gcm *)des;
struct hwcrypto_gcm *gcm_src = (struct hwcrypto_gcm *)src;
if (des != RT_NULL && src != RT_NULL)
{
gcm_des->crypt_type = gcm_src->crypt_type;
/* symmetric crypto context copy */
return rt_hwcrypto_symmetric_cpy(des, src);
}
return -RT_EINVAL;
}
/**
* @brief Reset GCM context
*
* @param ctx GCM context
*/
void rt_hwcrypto_gcm_reset(struct rt_hwcrypto_ctx *ctx)
{
rt_hwcrypto_symmetric_reset(ctx);
}

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-05-14 tyx the first version
*/
#ifndef __HW_GCM_H__
#define __HW_GCM_H__
#include "hw_symmetric.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hwcrypto_gcm;
struct hwcrypto_gcm_ops
{
rt_err_t (*start)(struct hwcrypto_gcm *gcm_ctx,
const unsigned char *add, rt_size_t add_len); /**< Set additional data. start GCM operation */
rt_err_t (*finish)(struct hwcrypto_gcm *gcm_ctx,
const unsigned char *tag, rt_size_t tag_len); /**< finish GCM operation. get tag */
};
/**
* @brief GCM context. Hardware driver usage
*/
struct hwcrypto_gcm
{
struct hwcrypto_symmetric parent; /**< Inheritance from hardware symmetric crypto context */
hwcrypto_type crypt_type; /**< symmetric crypto type. eg: AES/DES */
const struct hwcrypto_gcm_ops *ops; /**< !! Hardware initializes this value when creating context !! */
};
/**
* @brief Creating GCM Context
*
* @param device Hardware crypto device
* @param type Type of symmetric crypto context
*
* @return GCM context
*/
struct rt_hwcrypto_ctx *rt_hwcrypto_gcm_create(struct rt_hwcrypto_device *device,
hwcrypto_type crypt_type);
/**
* @brief Destroy GCM Context
*
* @param ctx GCM context
*/
void rt_hwcrypto_gcm_destroy(struct rt_hwcrypto_ctx *ctx);
/**
* @brief This function starts a GCM encryption or decryption operation
*
* @param ctx GCM context
* @param add The buffer holding the additional data
* @param add_len The length of the additional data
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_gcm_start(struct rt_hwcrypto_ctx *ctx, const rt_uint8_t *add,
rt_size_t add_len);
/**
* @brief This function finishes the GCM operation and generates the authentication tag
*
* @param ctx GCM context
* @param tag The buffer for holding the tag
* @param tag_len The length of the tag to generate
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_gcm_finish(struct rt_hwcrypto_ctx *ctx, const rt_uint8_t *tag,
rt_size_t tag_len);
/**
* @brief This function performs a symmetric encryption or decryption operation
*
* @param ctx GCM context
* @param mode Operation mode. HWCRYPTO_MODE_ENCRYPT or HWCRYPTO_MODE_DECRYPT
* @param length The length of the input data in Bytes. This must be a multiple of the block size
* @param in The buffer holding the input data
* @param out The buffer holding the output data
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_gcm_crypt(struct rt_hwcrypto_ctx *ctx, hwcrypto_mode mode,
rt_size_t length, const rt_uint8_t *in, rt_uint8_t *out);
/**
* @brief Set Symmetric Encryption and Decryption Key
*
* @param ctx GCM context
* @param key The crypto key
* @param bitlen The crypto key bit length
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_gcm_setkey(struct rt_hwcrypto_ctx *ctx,
const rt_uint8_t *key, rt_uint32_t bitlen);
/**
* @brief Get Symmetric Encryption and Decryption Key
*
* @param ctx GCM context
* @param key The crypto key buffer
* @param bitlen The crypto key bit length
*
* @return Key length of copy
*/
rt_err_t rt_hwcrypto_gcm_getkey(struct rt_hwcrypto_ctx *ctx,
rt_uint8_t *key, rt_uint32_t bitlen);
/**
* @brief Set Symmetric Encryption and Decryption initialization vector
*
* @param ctx GCM context
* @param iv The crypto initialization vector
* @param len The crypto initialization vector length
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_gcm_setiv(struct rt_hwcrypto_ctx *ctx,
const rt_uint8_t *iv, rt_size_t len);
/**
* @brief Get Symmetric Encryption and Decryption initialization vector
*
* @param ctx GCM context
* @param iv The crypto initialization vector buffer
* @param len The crypto initialization vector buffer length
*
* @return IV length of copy
*/
rt_err_t rt_hwcrypto_gcm_getiv(struct rt_hwcrypto_ctx *ctx,
rt_uint8_t *iv, rt_size_t len);
/**
* @brief Set offset in initialization vector
*
* @param ctx GCM context
* @param iv_off The offset in IV
*/
void rt_hwcrypto_gcm_set_ivoff(struct rt_hwcrypto_ctx *ctx, rt_int32_t iv_off);
/**
* @brief Get offset in initialization vector
*
* @param ctx GCM context
* @param iv_off It must point to a valid memory
*/
void rt_hwcrypto_gcm_get_ivoff(struct rt_hwcrypto_ctx *ctx, rt_int32_t *iv_off);
/**
* @brief This function copy GCM context
*
* @param des The destination GCM context
* @param src The GCM context to be copy
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_gcm_cpy(struct rt_hwcrypto_ctx *des,
const struct rt_hwcrypto_ctx *src);
/**
* @brief Reset GCM context
*
* @param ctx GCM context
*/
void rt_hwcrypto_gcm_reset(struct rt_hwcrypto_ctx *ctx);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-23 tyx the first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <hw_hash.h>
/**
* @brief Creating hash Context
*
* @param device Hardware crypto device
* @param type Type of hash context
*
* @return Hash context
*/
struct rt_hwcrypto_ctx *rt_hwcrypto_hash_create(struct rt_hwcrypto_device *device, hwcrypto_type type)
{
struct rt_hwcrypto_ctx *ctx;
ctx = rt_hwcrypto_ctx_create(device, type, sizeof(struct hwcrypto_hash));
return ctx;
}
/**
* @brief Destroy hash Context
*
* @param ctx Hash context
*/
void rt_hwcrypto_hash_destroy(struct rt_hwcrypto_ctx *ctx)
{
rt_hwcrypto_ctx_destroy(ctx);
}
/**
* @brief Get the final hash value
*
* @param ctx Hash context
* @param output Hash value buffer
* @param length Hash value buffer length
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_hash_finish(struct rt_hwcrypto_ctx *ctx, rt_uint8_t *output, rt_size_t length)
{
if (ctx && ((struct hwcrypto_hash *)ctx)->ops->finish)
{
return ((struct hwcrypto_hash *)ctx)->ops->finish((struct hwcrypto_hash *)ctx, output, length);
}
return -RT_ERROR;
}
/**
* @brief Processing a packet of data
*
* @param ctx Hash context
* @param input Data buffer to be Processed
* @param length Data Buffer length
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_hash_update(struct rt_hwcrypto_ctx *ctx, const rt_uint8_t *input, rt_size_t length)
{
if (ctx && ((struct hwcrypto_hash *)ctx)->ops->update)
{
return ((struct hwcrypto_hash *)ctx)->ops->update((struct hwcrypto_hash *)ctx, input, length);
}
return -RT_ERROR;
}
/**
* @brief This function copy hash context
*
* @param des The destination hash context
* @param src The hash context to be copy
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_hash_cpy(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
{
return rt_hwcrypto_ctx_cpy(des, src);
}
/**
* @brief Reset hash context
*
* @param ctx Hash context
*/
void rt_hwcrypto_hash_reset(struct rt_hwcrypto_ctx *ctx)
{
rt_hwcrypto_ctx_reset(ctx);
}
/**
* @brief Setting hash context type
*
* @param ctx Hash context
* @param type Types of settings
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_hash_set_type(struct rt_hwcrypto_ctx *ctx, hwcrypto_type type)
{
return rt_hwcrypto_set_type(ctx, type);
}

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-23 tyx the first version
*/
#ifndef __HW_HASH_H__
#define __HW_HASH_H__
#include <hwcrypto.h>
#ifdef __cplusplus
extern "C" {
#endif
struct hwcrypto_hash;
struct hwcrypto_hash_ops
{
rt_err_t (*update)(struct hwcrypto_hash *hash_ctx,
const rt_uint8_t *in, rt_size_t length); /**< Processing a packet of data */
rt_err_t (*finish)(struct hwcrypto_hash *hash_ctx,
rt_uint8_t *out, rt_size_t length); /**< Get the final hash value */
};
/**
* @brief hash context. Hardware driver usage
*/
struct hwcrypto_hash
{
struct rt_hwcrypto_ctx parent; /**< Inheritance from hardware crypto context */
const struct hwcrypto_hash_ops *ops; /**< !! Hardware initializes this value when creating context !! */
};
/**
* @brief Creating hash Context
*
* @param device Hardware crypto device
* @param type Type of hash context
*
* @return Hash context
*/
struct rt_hwcrypto_ctx *rt_hwcrypto_hash_create(struct rt_hwcrypto_device *device,
hwcrypto_type type);
/**
* @brief Destroy hash Context
*
* @param ctx Hash context
*/
void rt_hwcrypto_hash_destroy(struct rt_hwcrypto_ctx *ctx);
/**
* @brief Get the final hash value
*
* @param ctx Hash context
* @param output Hash value buffer
* @param length Hash value buffer length
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_hash_finish(struct rt_hwcrypto_ctx *ctx, rt_uint8_t *output, rt_size_t length);
/**
* @brief Processing a packet of data
*
* @param ctx Hash context
* @param input Data buffer to be Processed
* @param length Data Buffer length
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_hash_update(struct rt_hwcrypto_ctx *ctx, const rt_uint8_t *input, rt_size_t length);
/**
* @brief This function copy hash context
*
* @param des The destination hash context
* @param src The hash context to be copy
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_hash_cpy(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src);
/**
* @brief Reset hash context
*
* @param ctx Hash context
*/
void rt_hwcrypto_hash_reset(struct rt_hwcrypto_ctx *ctx);
/**
* @brief Setting hash context type
*
* @param ctx Hash context
* @param type Types of settings
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_hash_set_type(struct rt_hwcrypto_ctx *ctx, hwcrypto_type type);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-25 tyx the first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <hw_rng.h>
/* Used to save default RNG Context */
static struct rt_hwcrypto_ctx *ctx_default;
/**
* @brief Creating RNG Context
*
* @param device Hardware crypto device
*
* @return RNG context
*/
struct rt_hwcrypto_ctx *rt_hwcrypto_rng_create(struct rt_hwcrypto_device *device)
{
struct rt_hwcrypto_ctx *ctx;
ctx = rt_hwcrypto_ctx_create(device, HWCRYPTO_TYPE_RNG, sizeof(struct hwcrypto_rng));
return ctx;
}
/**
* @brief Destroy RNG Context
*
* @param ctx RNG context
*/
void rt_hwcrypto_rng_destroy(struct rt_hwcrypto_ctx *ctx)
{
/* Destroy the defaule RNG Context ? */
if (ctx == ctx_default)
{
ctx_default = RT_NULL;
}
rt_hwcrypto_ctx_destroy(ctx);
}
/**
* @brief Setting RNG default devices
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_rng_default(struct rt_hwcrypto_device *device)
{
struct rt_hwcrypto_ctx *tmp_ctx;
/* if device is null, destroy default RNG Context */
if (device == RT_NULL)
{
if (ctx_default)
{
rt_hwcrypto_rng_destroy(ctx_default);
ctx_default = RT_NULL;
}
return RT_EOK;
}
/* Try create RNG Context */
tmp_ctx = rt_hwcrypto_rng_create(device);
if (tmp_ctx == RT_NULL)
{
return -RT_ERROR;
}
/* create RNG Context success, update default RNG Context */
rt_hwcrypto_rng_destroy(ctx_default);
ctx_default = tmp_ctx;
return RT_EOK;
}
/**
* @brief Getting Random Numbers from RNG Context
*
* @param ctx RNG context
*
* @return Random number
*/
rt_uint32_t rt_hwcrypto_rng_update_ctx(struct rt_hwcrypto_ctx *ctx)
{
if (ctx)
{
return ((struct hwcrypto_rng *)ctx)->ops->update((struct hwcrypto_rng *)ctx);
}
return 0;
}
/**
* @brief Return a random number
*
* @return Random number
*/
rt_uint32_t rt_hwcrypto_rng_update(void)
{
/* Default device does not exist ? */
if (ctx_default == RT_NULL)
{
/* try create Context from default device */
rt_hwcrypto_rng_default(rt_hwcrypto_dev_default());
}
return rt_hwcrypto_rng_update_ctx(ctx_default);
}

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-25 tyx the first version
*/
#ifndef __HW_RNG_H__
#define __HW_RNG_H__
#include <hwcrypto.h>
#ifdef __cplusplus
extern "C" {
#endif
struct hwcrypto_rng;
struct hwcrypto_rng_ops
{
rt_uint32_t (*update)(struct hwcrypto_rng *ctx); /**< Return a random number */
};
/**
* @brief random context. Hardware driver usage
*/
struct hwcrypto_rng
{
struct rt_hwcrypto_ctx parent; /**< Inheritance from hardware crypto context */
const struct hwcrypto_rng_ops *ops; /**< !! Hardware initializes this value when creating context !! */
};
/**
* @brief Creating RNG Context
*
* @param device Hardware crypto device
*
* @return RNG context
*/
struct rt_hwcrypto_ctx *rt_hwcrypto_rng_create(struct rt_hwcrypto_device *device);
/**
* @brief Destroy RNG Context
*
* @param ctx RNG context
*/
void rt_hwcrypto_rng_destroy(struct rt_hwcrypto_ctx *ctx);
/**
* @brief Setting RNG default devices
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_rng_default(struct rt_hwcrypto_device *device);
/**
* @brief Getting Random Numbers from RNG Context
*
* @param ctx RNG context
*
* @return Random number
*/
rt_uint32_t rt_hwcrypto_rng_update_ctx(struct rt_hwcrypto_ctx *ctx);
/**
* @brief Return a random number
*
* @return Random number
*/
rt_uint32_t rt_hwcrypto_rng_update(void);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-25 tyx the first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <hw_symmetric.h>
/**
* @brief Creating Symmetric Encryption and Decryption Context
*
* @param device Hardware crypto device
* @param type Type of symmetric crypto context
*
* @return Symmetric crypto context
*/
struct rt_hwcrypto_ctx *rt_hwcrypto_symmetric_create(struct rt_hwcrypto_device *device, hwcrypto_type type)
{
struct rt_hwcrypto_ctx *ctx;
ctx = rt_hwcrypto_ctx_create(device, type, sizeof(struct hwcrypto_symmetric));
return ctx;
}
/**
* @brief Destroy Symmetric Encryption and Decryption Context
*
* @param ctx Symmetric crypto context
*/
void rt_hwcrypto_symmetric_destroy(struct rt_hwcrypto_ctx *ctx)
{
rt_hwcrypto_ctx_destroy(ctx);
}
/**
* @brief This function performs a symmetric encryption or decryption operation
*
* @param ctx Symmetric crypto context
* @param mode Operation mode. HWCRYPTO_MODE_ENCRYPT or HWCRYPTO_MODE_DECRYPT
* @param length The length of the input data in Bytes. This must be a multiple of the block size
* @param in The buffer holding the input data
* @param out The buffer holding the output data
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_symmetric_crypt(struct rt_hwcrypto_ctx *ctx, hwcrypto_mode mode, rt_size_t length, const rt_uint8_t *in, rt_uint8_t *out)
{
struct hwcrypto_symmetric *symmetric_ctx;
struct hwcrypto_symmetric_info symmetric_info;
rt_err_t err;
if (ctx == RT_NULL)
{
return -RT_EINVAL;
}
symmetric_ctx = (struct hwcrypto_symmetric *)ctx;
if (symmetric_ctx->ops->crypt == RT_NULL)
{
return -RT_ERROR;
}
if (mode != HWCRYPTO_MODE_ENCRYPT && mode != HWCRYPTO_MODE_DECRYPT)
{
return -RT_EINVAL;
}
/* Input information packaging */
symmetric_info.mode = mode;
symmetric_info.in = in;
symmetric_info.out = out;
symmetric_info.length = length;
/* Calling Hardware Encryption and Decryption Function */
err = symmetric_ctx->ops->crypt(symmetric_ctx, &symmetric_info);
/* clean up flags */
symmetric_ctx->flags &= ~(SYMMTRIC_MODIFY_KEY | SYMMTRIC_MODIFY_IV | SYMMTRIC_MODIFY_IVOFF);
return err;
}
/**
* @brief Set Symmetric Encryption and Decryption Key
*
* @param ctx Symmetric crypto context
* @param key The crypto key
* @param bitlen The crypto key bit length
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_symmetric_setkey(struct rt_hwcrypto_ctx *ctx, const rt_uint8_t *key, rt_uint32_t bitlen)
{
struct hwcrypto_symmetric *symmetric_ctx;
if (ctx && bitlen <= RT_HWCRYPTO_KEYBIT_MAX_SIZE)
{
symmetric_ctx = (struct hwcrypto_symmetric *)ctx;
rt_memcpy(symmetric_ctx->key, key, bitlen >> 3);
/* Record key length */
symmetric_ctx->key_bitlen = bitlen;
/* Key change flag set up */
symmetric_ctx->flags |= SYMMTRIC_MODIFY_KEY;
return RT_EOK;
}
return -RT_EINVAL;
}
/**
* @brief Get Symmetric Encryption and Decryption Key
*
* @param ctx Symmetric crypto context
* @param key The crypto key buffer
* @param bitlen The crypto key bit length
*
* @return Key length of copy
*/
int rt_hwcrypto_symmetric_getkey(struct rt_hwcrypto_ctx *ctx, rt_uint8_t *key, rt_uint32_t bitlen)
{
struct hwcrypto_symmetric *symmetric_ctx = (struct hwcrypto_symmetric *)ctx;
if (ctx && bitlen >= symmetric_ctx->key_bitlen)
{
rt_memcpy(key, symmetric_ctx->key, symmetric_ctx->key_bitlen >> 3);
return symmetric_ctx->key_bitlen;
}
return 0;
}
/**
* @brief Set Symmetric Encryption and Decryption initialization vector
*
* @param ctx Symmetric crypto context
* @param iv The crypto initialization vector
* @param len The crypto initialization vector length
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_symmetric_setiv(struct rt_hwcrypto_ctx *ctx, const rt_uint8_t *iv, rt_size_t len)
{
struct hwcrypto_symmetric *symmetric_ctx;
if (ctx && len <= RT_HWCRYPTO_IV_MAX_SIZE)
{
symmetric_ctx = (struct hwcrypto_symmetric *)ctx;
rt_memcpy(symmetric_ctx->iv, iv, len);
symmetric_ctx->iv_len = len;
/* IV change flag set up */
symmetric_ctx->flags |= SYMMTRIC_MODIFY_IV;
return RT_EOK;
}
return -RT_EINVAL;
}
/**
* @brief Get Symmetric Encryption and Decryption initialization vector
*
* @param ctx Symmetric crypto context
* @param iv The crypto initialization vector buffer
* @param len The crypto initialization vector buffer length
*
* @return IV length of copy
*/
int rt_hwcrypto_symmetric_getiv(struct rt_hwcrypto_ctx *ctx, rt_uint8_t *iv, rt_size_t len)
{
struct hwcrypto_symmetric *symmetric_ctx = (struct hwcrypto_symmetric *)ctx;;
if (ctx && len >= symmetric_ctx->iv_len)
{
rt_memcpy(iv, symmetric_ctx->iv, symmetric_ctx->iv_len);
return symmetric_ctx->iv_len;
}
return 0;
}
/**
* @brief Set offset in initialization vector
*
* @param ctx Symmetric crypto context
* @param iv_off The offset in IV
*/
void rt_hwcrypto_symmetric_set_ivoff(struct rt_hwcrypto_ctx *ctx, rt_int32_t iv_off)
{
if (ctx)
{
((struct hwcrypto_symmetric *)ctx)->iv_off = iv_off;
/* iv_off change flag set up */
((struct hwcrypto_symmetric *)ctx)->flags |= SYMMTRIC_MODIFY_IVOFF;
}
}
/**
* @brief Get offset in initialization vector
*
* @param ctx Symmetric crypto context
* @param iv_off It must point to a valid memory
*/
void rt_hwcrypto_symmetric_get_ivoff(struct rt_hwcrypto_ctx *ctx, rt_int32_t *iv_off)
{
if (ctx && iv_off)
{
*iv_off = ((struct hwcrypto_symmetric *)ctx)->iv_off;
}
}
/**
* @brief This function copy symmetric crypto context
*
* @param des The destination symmetric crypto context
* @param src The symmetric crypto context to be copy
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_symmetric_cpy(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
{
struct hwcrypto_symmetric *symmetric_des = (struct hwcrypto_symmetric *)des;
struct hwcrypto_symmetric *symmetric_src = (struct hwcrypto_symmetric *)src;
if (des != RT_NULL && src != RT_NULL)
{
/* Copy Symmetric Encryption and Decryption Context Information */
symmetric_des->flags = symmetric_src->flags ;
symmetric_des->iv_len = symmetric_src->iv_len ;
symmetric_des->iv_off = symmetric_src->iv_off ;
symmetric_des->key_bitlen = symmetric_src->key_bitlen;
rt_memcpy(symmetric_des->iv, symmetric_src->iv, symmetric_src->iv_len);
rt_memcpy(symmetric_des->key, symmetric_src->key, symmetric_src->key_bitlen >> 3);
/* Hardware context copy */
return rt_hwcrypto_ctx_cpy(des, src);
}
return -RT_EINVAL;
}
/**
* @brief Reset symmetric crypto context
*
* @param ctx Symmetric crypto context
*/
void rt_hwcrypto_symmetric_reset(struct rt_hwcrypto_ctx *ctx)
{
struct hwcrypto_symmetric *symmetric_ctx = (struct hwcrypto_symmetric *)ctx;
if (ctx != RT_NULL)
{
/* Copy Symmetric Encryption and Decryption Context Information */
symmetric_ctx->flags = 0x00;
symmetric_ctx->iv_len = 0x00;
symmetric_ctx->iv_off = 0x00;
symmetric_ctx->key_bitlen = 0x00;
rt_memset(symmetric_ctx->iv, 0, RT_HWCRYPTO_IV_MAX_SIZE);
rt_memset(symmetric_ctx->key, 0, RT_HWCRYPTO_KEYBIT_MAX_SIZE >> 3);
/* Hardware context reset */
rt_hwcrypto_ctx_reset(ctx);
}
}
/**
* @brief Setting symmetric crypto context type
*
* @param ctx Symmetric crypto context
* @param type Types of settings
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_symmetric_set_type(struct rt_hwcrypto_ctx *ctx, hwcrypto_type type)
{
return rt_hwcrypto_set_type(ctx, type);
}

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-25 tyx the first version
*/
#ifndef __HW_SYMMETRIC_H__
#define __HW_SYMMETRIC_H__
#include <hwcrypto.h>
#ifndef RT_HWCRYPTO_IV_MAX_SIZE
#define RT_HWCRYPTO_IV_MAX_SIZE (16)
#endif
#ifndef RT_HWCRYPTO_KEYBIT_MAX_SIZE
#define RT_HWCRYPTO_KEYBIT_MAX_SIZE (256)
#endif
#define SYMMTRIC_MODIFY_KEY (0x1 << 0)
#define SYMMTRIC_MODIFY_IV (0x1 << 1)
#define SYMMTRIC_MODIFY_IVOFF (0x1 << 2)
#ifdef __cplusplus
extern "C" {
#endif
struct hwcrypto_symmetric;
struct hwcrypto_symmetric_info;
struct hwcrypto_symmetric_ops
{
rt_err_t (*crypt)(struct hwcrypto_symmetric *symmetric_ctx,
struct hwcrypto_symmetric_info *symmetric_info); /**< Hardware Symmetric Encryption and Decryption Callback */
};
/**
* @brief Hardware driver usage, including input and output information
*/
struct hwcrypto_symmetric_info
{
hwcrypto_mode mode; /**< crypto mode. HWCRYPTO_MODE_ENCRYPT or HWCRYPTO_MODE_DECRYPT */
const rt_uint8_t *in; /**< Input data */
rt_uint8_t *out; /**< Output data will be written */
rt_size_t length; /**< The length of the input data in Bytes. It's a multiple of block size. */
};
/**
* @brief Symmetric crypto context. Hardware driver usage
*/
struct hwcrypto_symmetric
{
struct rt_hwcrypto_ctx parent; /**< Inheritance from hardware crypto context */
rt_uint16_t flags; /**< key or iv or ivoff has been changed. The flag will be set up */
rt_uint16_t iv_len; /**< initialization vector effective length */
rt_uint16_t iv_off; /**< The offset in IV */
rt_uint16_t key_bitlen; /**< The crypto key bit length */
rt_uint8_t iv[RT_HWCRYPTO_IV_MAX_SIZE]; /**< The initialization vector */
rt_uint8_t key[RT_HWCRYPTO_KEYBIT_MAX_SIZE >> 3]; /**< The crypto key */
const struct hwcrypto_symmetric_ops *ops; /**< !! Hardware initializes this value when creating context !! */
};
/**
* @brief Creating Symmetric Encryption and Decryption Context
*
* @param device Hardware crypto device
* @param type Type of symmetric crypto context
*
* @return Symmetric crypto context
*/
struct rt_hwcrypto_ctx *rt_hwcrypto_symmetric_create(struct rt_hwcrypto_device *device,
hwcrypto_type type);
/**
* @brief Destroy Symmetric Encryption and Decryption Context
*
* @param ctx Symmetric crypto context
*/
void rt_hwcrypto_symmetric_destroy(struct rt_hwcrypto_ctx *ctx);
/**
* @brief This function performs a symmetric encryption or decryption operation
*
* @param ctx Symmetric crypto context
* @param mode Operation mode. HWCRYPTO_MODE_ENCRYPT or HWCRYPTO_MODE_DECRYPT
* @param length The length of the input data in Bytes. This must be a multiple of the block size
* @param in The buffer holding the input data
* @param out The buffer holding the output data
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_symmetric_crypt(struct rt_hwcrypto_ctx *ctx, hwcrypto_mode mode,
rt_size_t length, const rt_uint8_t *in, rt_uint8_t *out);
/**
* @brief Set Symmetric Encryption and Decryption Key
*
* @param ctx Symmetric crypto context
* @param key The crypto key
* @param bitlen The crypto key bit length
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_symmetric_setkey(struct rt_hwcrypto_ctx *ctx, const rt_uint8_t *key, rt_uint32_t bitlen);
/**
* @brief Get Symmetric Encryption and Decryption Key
*
* @param ctx Symmetric crypto context
* @param key The crypto key buffer
* @param bitlen The crypto key bit length
*
* @return Key length of copy
*/
int rt_hwcrypto_symmetric_getkey(struct rt_hwcrypto_ctx *ctx, rt_uint8_t *key, rt_uint32_t bitlen);
/**
* @brief Set Symmetric Encryption and Decryption initialization vector
*
* @param ctx Symmetric crypto context
* @param iv The crypto initialization vector
* @param len The crypto initialization vector length
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_symmetric_setiv(struct rt_hwcrypto_ctx *ctx, const rt_uint8_t *iv, rt_size_t len);
/**
* @brief Get Symmetric Encryption and Decryption initialization vector
*
* @param ctx Symmetric crypto context
* @param iv The crypto initialization vector buffer
* @param len The crypto initialization vector buffer length
*
* @return IV length of copy
*/
int rt_hwcrypto_symmetric_getiv(struct rt_hwcrypto_ctx *ctx, rt_uint8_t *iv, rt_size_t len);
/**
* @brief Set offset in initialization vector
*
* @param ctx Symmetric crypto context
* @param iv_off The offset in IV
*/
void rt_hwcrypto_symmetric_set_ivoff(struct rt_hwcrypto_ctx *ctx, rt_int32_t iv_off);
/**
* @brief Get offset in initialization vector
*
* @param ctx Symmetric crypto context
* @param iv_off It must point to a valid memory
*/
void rt_hwcrypto_symmetric_get_ivoff(struct rt_hwcrypto_ctx *ctx, rt_int32_t *iv_off);
/**
* @brief This function copy symmetric crypto context
*
* @param des The destination symmetric crypto context
* @param src The symmetric crypto context to be copy
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_symmetric_cpy(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src);
/**
* @brief Reset symmetric crypto context
*
* @param ctx Symmetric crypto context
*/
void rt_hwcrypto_symmetric_reset(struct rt_hwcrypto_ctx *ctx);
/**
* @brief Setting symmetric crypto context type
*
* @param ctx Symmetric crypto context
* @param type Types of settings
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_symmetric_set_type(struct rt_hwcrypto_ctx *ctx, hwcrypto_type type);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-23 tyx the first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <hwcrypto.h>
/**
* @brief Setting context type (Direct calls are not recommended)
*
* @param ctx Crypto context
* @param type Types of settings
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_set_type(struct rt_hwcrypto_ctx *ctx, hwcrypto_type type)
{
if (ctx)
{
/* Is it the same category? */
if ((ctx->type & HWCRYPTO_MAIN_TYPE_MASK) == (type & HWCRYPTO_MAIN_TYPE_MASK))
{
ctx->type = type;
return RT_EOK;
}
/* Context is empty type */
else if (ctx->type == HWCRYPTO_TYPE_NULL)
{
ctx->type = type;
return RT_EOK;
}
else
{
return -RT_ERROR;
}
}
return -RT_EINVAL;
}
/**
* @brief Reset context type (Direct calls are not recommended)
*
* @param ctx Crypto context
*
*/
void rt_hwcrypto_ctx_reset(struct rt_hwcrypto_ctx *ctx)
{
if (ctx && ctx->device->ops->reset)
{
ctx->device->ops->reset(ctx);
}
}
/**
* @brief Init crypto context
*
* @param ctx The context to initialize
* @param device Hardware crypto device
* @param type Type of context
* @param obj_size Size of context object
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_ctx_init(struct rt_hwcrypto_ctx *ctx, struct rt_hwcrypto_device *device, hwcrypto_type type)
{
rt_err_t err;
/* Setting context type */
rt_hwcrypto_set_type(ctx, type);
ctx->device = device;
/* Create hardware context */
err = ctx->device->ops->create(ctx);
if (err != RT_EOK)
{
return err;
}
return RT_EOK;
}
/**
* @brief Create crypto context
*
* @param device Hardware crypto device
* @param type Type of context
* @param obj_size Size of context object
*
* @return Crypto context
*/
struct rt_hwcrypto_ctx *rt_hwcrypto_ctx_create(struct rt_hwcrypto_device *device, hwcrypto_type type, rt_uint32_t obj_size)
{
struct rt_hwcrypto_ctx *ctx;
rt_err_t err;
/* Parameter checking */
if (device == RT_NULL || obj_size < sizeof(struct rt_hwcrypto_ctx))
{
return RT_NULL;
}
ctx = rt_malloc(obj_size);
if (ctx == RT_NULL)
{
return ctx;
}
rt_memset(ctx, 0, obj_size);
/* Init context */
err = rt_hwcrypto_ctx_init(ctx, device, type);
if (err != RT_EOK)
{
rt_free(ctx);
ctx = RT_NULL;
}
return ctx;
}
/**
* @brief Destroy crypto context
*
* @param device Crypto context
*/
void rt_hwcrypto_ctx_destroy(struct rt_hwcrypto_ctx *ctx)
{
if (ctx == RT_NULL)
{
return;
}
/* Destroy hardware context */
if (ctx->device->ops->destroy)
{
ctx->device->ops->destroy(ctx);
}
/* Free the resources */
rt_free(ctx);
}
/**
* @brief Copy crypto context
*
* @param des The destination context
* @param src The context to be copy
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_ctx_cpy(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
{
if (des == RT_NULL || src == RT_NULL)
{
return -RT_EINVAL;
}
/* The equipment is different or of different types and cannot be copied */
if (des->device != src->device ||
(des->type & HWCRYPTO_MAIN_TYPE_MASK) != (src->type & HWCRYPTO_MAIN_TYPE_MASK))
{
return -RT_EINVAL;
}
des->type = src->type;
/* Calling Hardware Context Copy Function */
return src->device->ops->copy(des, src);
}
/**
* @brief Get the default hardware crypto device
*
* @return Hardware crypto device
*
*/
struct rt_hwcrypto_device *rt_hwcrypto_dev_default(void)
{
static struct rt_hwcrypto_device *hwcrypto_dev;
/* If there is a default device, return the device */
if (hwcrypto_dev)
{
return hwcrypto_dev;
}
/* Find by default device name */
hwcrypto_dev = (struct rt_hwcrypto_device *)rt_device_find(RT_HWCRYPTO_DEFAULT_NAME);
return hwcrypto_dev;
}
/**
* @brief Get the unique ID of the device
*
* @param device Device object
*
* @return Device unique ID
*/
rt_uint64_t rt_hwcrypto_id(struct rt_hwcrypto_device *device)
{
if (device)
{
return device->id;
}
return 0;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops hwcrypto_ops =
{
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL
};
#endif
/**
* @brief Register hardware crypto device
*
* @param device Hardware crypto device
* @param name Name of device
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_register(struct rt_hwcrypto_device *device, const char *name)
{
rt_err_t err;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(name != RT_NULL);
RT_ASSERT(device->ops != RT_NULL);
RT_ASSERT(device->ops->create != RT_NULL);
RT_ASSERT(device->ops->destroy != RT_NULL);
RT_ASSERT(device->ops->copy != RT_NULL);
RT_ASSERT(device->ops->reset != RT_NULL);
rt_memset(&device->parent, 0, sizeof(struct rt_device));
#ifdef RT_USING_DEVICE_OPS
device->parent.ops = &hwcrypto_ops;
#else
device->parent.init = RT_NULL;
device->parent.open = RT_NULL;
device->parent.close = RT_NULL;
device->parent.read = RT_NULL;
device->parent.write = RT_NULL;
device->parent.control = RT_NULL;
#endif
device->parent.user_data = RT_NULL;
device->parent.type = RT_Device_Class_Security;
/* Register device */
err = rt_device_register(&device->parent, name, RT_DEVICE_FLAG_RDWR);
return err;
}

193
rt-thread/components/drivers/hwcrypto/hwcrypto.h Normal file
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@@ -0,0 +1,193 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-23 tyx the first version
*/
#ifndef __HWCRYPTO_H__
#define __HWCRYPTO_H__
#include <rtthread.h>
#ifndef RT_HWCRYPTO_DEFAULT_NAME
#define RT_HWCRYPTO_DEFAULT_NAME ("hwcryto")
#endif
#define HWCRYPTO_MAIN_TYPE_MASK (0xffffUL << 16)
#define HWCRYPTO_SUB_TYPE_MASK (0xffUL << 8)
#ifdef __cplusplus
extern "C" {
#endif
typedef enum
{
HWCRYPTO_TYPE_NULL = 0x00000000,
/* Main Type */
/* symmetric Type */
HWCRYPTO_TYPE_HEAD = __LINE__,
HWCRYPTO_TYPE_AES = ((__LINE__ - HWCRYPTO_TYPE_HEAD) & 0xffff) << 16, /**< AES */
HWCRYPTO_TYPE_DES = ((__LINE__ - HWCRYPTO_TYPE_HEAD) & 0xffff) << 16, /**< DES */
HWCRYPTO_TYPE_3DES = ((__LINE__ - HWCRYPTO_TYPE_HEAD) & 0xffff) << 16, /**< 3DES */
HWCRYPTO_TYPE_RC4 = ((__LINE__ - HWCRYPTO_TYPE_HEAD) & 0xffff) << 16, /**< RC4 */
HWCRYPTO_TYPE_GCM = ((__LINE__ - HWCRYPTO_TYPE_HEAD) & 0xffff) << 16, /**< GCM */
/* HASH Type */
HWCRYPTO_TYPE_MD5 = ((__LINE__ - HWCRYPTO_TYPE_HEAD) & 0xffff) << 16, /**< MD5 */
HWCRYPTO_TYPE_SHA1 = ((__LINE__ - HWCRYPTO_TYPE_HEAD) & 0xffff) << 16, /**< SHA1 */
HWCRYPTO_TYPE_SHA2 = ((__LINE__ - HWCRYPTO_TYPE_HEAD) & 0xffff) << 16, /**< SHA2 */
/* Other Type */
HWCRYPTO_TYPE_RNG = ((__LINE__ - HWCRYPTO_TYPE_HEAD) & 0xffff) << 16, /**< RNG */
HWCRYPTO_TYPE_CRC = ((__LINE__ - HWCRYPTO_TYPE_HEAD) & 0xffff) << 16, /**< CRC */
HWCRYPTO_TYPE_BIGNUM = ((__LINE__ - HWCRYPTO_TYPE_HEAD) & 0xffff) << 16, /**< BIGNUM */
/* AES Subtype */
HWCRYPTO_TYPE_AES_ECB = HWCRYPTO_TYPE_AES | (0x01 << 8),
HWCRYPTO_TYPE_AES_CBC = HWCRYPTO_TYPE_AES | (0x02 << 8),
HWCRYPTO_TYPE_AES_CFB = HWCRYPTO_TYPE_AES | (0x03 << 8),
HWCRYPTO_TYPE_AES_CTR = HWCRYPTO_TYPE_AES | (0x04 << 8),
HWCRYPTO_TYPE_AES_OFB = HWCRYPTO_TYPE_AES | (0x05 << 8),
/* DES Subtype */
HWCRYPTO_TYPE_DES_ECB = HWCRYPTO_TYPE_DES | (0x01 << 8),
HWCRYPTO_TYPE_DES_CBC = HWCRYPTO_TYPE_DES | (0x02 << 8),
/* 3DES Subtype */
HWCRYPTO_TYPE_3DES_ECB = HWCRYPTO_TYPE_3DES | (0x01 << 8),
HWCRYPTO_TYPE_3DES_CBC = HWCRYPTO_TYPE_3DES | (0x02 << 8),
/* SHA2 Subtype */
HWCRYPTO_TYPE_SHA224 = HWCRYPTO_TYPE_SHA2 | (0x01 << 8),
HWCRYPTO_TYPE_SHA256 = HWCRYPTO_TYPE_SHA2 | (0x02 << 8),
HWCRYPTO_TYPE_SHA384 = HWCRYPTO_TYPE_SHA2 | (0x03 << 8),
HWCRYPTO_TYPE_SHA512 = HWCRYPTO_TYPE_SHA2 | (0x04 << 8),
} hwcrypto_type;
typedef enum
{
HWCRYPTO_MODE_ENCRYPT = 0x1, /**< Encryption operations */
HWCRYPTO_MODE_DECRYPT = 0x2, /**< Decryption operations */
HWCRYPTO_MODE_UNKNOWN = 0x7fffffff, /**< Unknown */
} hwcrypto_mode;
struct rt_hwcrypto_ctx;
struct rt_hwcrypto_ops
{
rt_err_t (*create)(struct rt_hwcrypto_ctx *ctx); /**< Creating hardware context */
void (*destroy)(struct rt_hwcrypto_ctx *ctx); /**< Delete hardware context */
rt_err_t (*copy)(struct rt_hwcrypto_ctx *des,
const struct rt_hwcrypto_ctx *src); /**< Cpoy hardware context */
void (*reset)(struct rt_hwcrypto_ctx *ctx); /**< Reset hardware context */
};
struct rt_hwcrypto_device
{
struct rt_device parent; /**< Inherited from the standard device */
const struct rt_hwcrypto_ops *ops; /**< Hardware crypto ops */
rt_uint64_t id; /**< Unique id */
void *user_data; /**< Device user data */
};
struct rt_hwcrypto_ctx
{
struct rt_hwcrypto_device *device; /**< Binding device */
hwcrypto_type type; /**< Encryption and decryption types */
void *contex; /**< Hardware context */
};
/**
* @brief Setting context type (Direct calls are not recommended)
*
* @param ctx Crypto context
* @param type Types of settings
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_set_type(struct rt_hwcrypto_ctx *ctx, hwcrypto_type type);
/**
* @brief Reset context type (Direct calls are not recommended)
*
* @param ctx Crypto context
*/
void rt_hwcrypto_ctx_reset(struct rt_hwcrypto_ctx *ctx);
/**
* @brief Init crypto context (Direct calls are not recommended)
*
* @param ctx The context to initialize
* @param device Hardware crypto device
* @param type Type of context
* @param obj_size Size of context object
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_ctx_init(struct rt_hwcrypto_ctx *ctx,
struct rt_hwcrypto_device *device, hwcrypto_type type);
/**
* @brief Create crypto context (Direct calls are not recommended)
*
* @param device Hardware crypto device
* @param type Type of context
* @param obj_size Size of context object
*
* @return Crypto context
*/
struct rt_hwcrypto_ctx *rt_hwcrypto_ctx_create(struct rt_hwcrypto_device *device,
hwcrypto_type type, rt_uint32_t obj_size);
/**
* @brief Destroy crypto context (Direct calls are not recommended)
*
* @param device Crypto context
*/
void rt_hwcrypto_ctx_destroy(struct rt_hwcrypto_ctx *ctx);
/**
* @brief Copy crypto context (Direct calls are not recommended)
*
* @param des The destination context
* @param src The context to be copy
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_ctx_cpy(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src);
/**
* @brief Register hardware crypto device
*
* @param device Hardware crypto device
* @param name Name of device
*
* @return RT_EOK on success.
*/
rt_err_t rt_hwcrypto_register(struct rt_hwcrypto_device *device, const char *name);
/**
* @brief Get the default hardware crypto device
*
* @return Hardware crypto device
*
*/
struct rt_hwcrypto_device *rt_hwcrypto_dev_default(void);
/**
* @brief Get the unique ID of the device
*
* @param device Device object
*
* @return Device unique ID
*/
rt_uint64_t rt_hwcrypto_id(struct rt_hwcrypto_device *device);
#ifdef __cplusplus
}
#endif
#endif

10
rt-thread/components/drivers/hwtimer/Kconfig Normal file
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@@ -0,0 +1,10 @@
menuconfig RT_USING_HWTIMER
bool "Using Hardware Timer device drivers"
default n
config RT_HWTIMER_ARM_ARCH
bool "ARM ARCH Timer"
depends on RT_USING_DM
depends on RT_USING_HWTIMER
depends on ARCH_ARM_CORTEX_A || ARCH_ARMV8
default n

18
rt-thread/components/drivers/hwtimer/SConscript Normal file
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@@ -0,0 +1,18 @@
from building import *
group = []
if not GetDepend(['RT_USING_HWTIMER']):
Return('group')
cwd = GetCurrentDir()
CPPPATH = [cwd + '/../include']
src = ['hwtimer.c']
if GetDepend(['RT_HWTIMER_ARM_ARCH']):
src += ['hwtimer-arm_arch.c']
group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

383
rt-thread/components/drivers/hwtimer/hwtimer-arm_arch.c Normal file
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@@ -0,0 +1,383 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-12-20 GuEe-GUI first version
* 2022-08-24 GuEe-GUI Add OFW support
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
/* support registers access and timer registers in libcpu */
#include <cpu.h>
#include <cpuport.h>
typedef void (*timer_ctrl_handle)(rt_bool_t enable);
typedef rt_uint64_t (*timer_value_handle)(rt_uint64_t val);
static volatile rt_uint64_t timer_step;
static int arm_arch_timer_irq = -1;
static timer_ctrl_handle arm_arch_timer_ctrl_handle = RT_NULL;
static timer_value_handle arm_arch_timer_value_handle = RT_NULL;
/* CTL */
static void mon_ptimer_ctrl(rt_bool_t enable)
{
rt_hw_sysreg_write(CNTPS_CTL, !!enable);
}
static void hyp_s_ptimer_ctrl(rt_bool_t enable)
{
#if ARCH_ARMV8_EXTENSIONS > 1
rt_hw_sysreg_write(CNTHPS_CTL, !!enable);
#endif
}
static void hyp_ns_ptimer_ctrl(rt_bool_t enable)
{
rt_hw_sysreg_write(CNTHP_CTL, !!enable);
}
static void hyp_s_vtimer_ctrl(rt_bool_t enable)
{
#if ARCH_ARMV8_EXTENSIONS > 1
rt_hw_sysreg_write(CNTHVS_CTL, !!enable);
#endif
}
static void hyp_ns_vtimer_ctrl(rt_bool_t enable)
{
#if ARCH_ARMV8_EXTENSIONS > 1
rt_hw_sysreg_write(CNTHV_CTL, !!enable);
#endif
}
static void os_ptimer_ctrl(rt_bool_t enable)
{
rt_hw_sysreg_write(CNTP_CTL, !!enable);
}
static void os_vtimer_ctrl(rt_bool_t enable)
{
rt_hw_sysreg_write(CNTV_CTL, !!enable);
}
/* TVAL */
static rt_uint64_t mon_ptimer_value(rt_uint64_t val)
{
if (val)
{
rt_hw_sysreg_write(CNTPS_TVAL, val);
}
else
{
rt_hw_sysreg_read(CNTPS_TVAL, val);
}
return val;
}
static rt_uint64_t hyp_s_ptimer_value(rt_uint64_t val)
{
#if ARCH_ARMV8_EXTENSIONS > 1
if (val)
{
rt_hw_sysreg_write(CNTHPS_TVAL, val);
}
else
{
rt_hw_sysreg_read(CNTHPS_TVAL, val);
}
return val;
#else
return 0;
#endif
}
static rt_uint64_t hyp_ns_ptimer_value(rt_uint64_t val)
{
if (val)
{
rt_hw_sysreg_write(CNTHP_TVAL, val);
}
else
{
rt_hw_sysreg_read(CNTHP_TVAL, val);
}
return val;
}
static rt_uint64_t hyp_s_vtimer_value(rt_uint64_t val)
{
#if ARCH_ARMV8_EXTENSIONS > 1
if (val)
{
rt_hw_sysreg_write(CNTHVS_TVAL, val);
}
else
{
rt_hw_sysreg_read(CNTHVS_TVAL, val);
}
return val;
#else
return 0;
#endif
}
static rt_uint64_t hyp_ns_vtimer_value(rt_uint64_t val)
{
#if ARCH_ARMV8_EXTENSIONS > 1
if (val)
{
rt_hw_sysreg_write(CNTHV_TVAL, val);
}
else
{
rt_hw_sysreg_read(CNTHV_TVAL, val);
}
return val;
#else
return 0;
#endif
}
static rt_uint64_t os_ptimer_value(rt_uint64_t val)
{
if (val)
{
rt_hw_sysreg_write(CNTP_TVAL, val);
}
else
{
rt_hw_sysreg_read(CNTP_TVAL, val);
}
return val;
}
static rt_uint64_t os_vtimer_value(rt_uint64_t val)
{
if (val)
{
rt_hw_sysreg_write(CNTV_TVAL, val);
}
else
{
rt_hw_sysreg_read(CNTV_TVAL, val);
}
return val;
}
static timer_ctrl_handle ctrl_handle[] =
{
mon_ptimer_ctrl,
hyp_s_ptimer_ctrl,
hyp_ns_ptimer_ctrl,
hyp_s_vtimer_ctrl,
hyp_ns_vtimer_ctrl,
os_ptimer_ctrl,
os_vtimer_ctrl,
};
static timer_value_handle value_handle[] =
{
mon_ptimer_value,
hyp_s_ptimer_value,
hyp_ns_ptimer_value,
hyp_s_vtimer_value,
hyp_ns_vtimer_value,
os_ptimer_value,
os_vtimer_value,
};
static rt_err_t arm_arch_timer_local_enable(void)
{
rt_err_t ret = RT_EOK;
if (arm_arch_timer_irq >= 0)
{
arm_arch_timer_ctrl_handle(RT_FALSE);
arm_arch_timer_value_handle(timer_step);
rt_hw_interrupt_umask(arm_arch_timer_irq);
arm_arch_timer_ctrl_handle(RT_TRUE);
}
else
{
ret = -RT_ENOSYS;
}
return ret;
}
rt_used
static rt_err_t arm_arch_timer_local_disable(void)
{
rt_err_t ret = RT_EOK;
if (arm_arch_timer_ctrl_handle)
{
arm_arch_timer_ctrl_handle(RT_FALSE);
rt_hw_interrupt_mask(arm_arch_timer_irq);
}
else
{
ret = -RT_ENOSYS;
}
return ret;
}
rt_used
static rt_err_t arm_arch_timer_set_frequency(rt_uint64_t frq)
{
rt_err_t ret = RT_EOK;
#ifdef ARCH_SUPPORT_TEE
rt_hw_isb();
rt_hw_sysreg_write(CNTFRQ, frq);
rt_hw_dsb();
#else
ret = -RT_ENOSYS;
#endif
return ret;
}
rt_used
static rt_uint64_t arm_arch_timer_get_frequency(void)
{
rt_uint64_t frq;
rt_hw_isb();
rt_hw_sysreg_read(CNTFRQ, frq);
rt_hw_isb();
return frq;
}
rt_used
static rt_err_t arm_arch_timer_set_value(rt_uint64_t val)
{
rt_err_t ret = RT_EOK;
if (arm_arch_timer_value_handle)
{
val = arm_arch_timer_value_handle(val);
}
else
{
ret = -RT_ENOSYS;
}
return ret;
}
rt_used
static rt_uint64_t arm_arch_timer_get_value(void)
{
rt_uint64_t val = 0;
if (arm_arch_timer_value_handle)
{
val = arm_arch_timer_value_handle(0);
}
return val;
}
static void arm_arch_timer_isr(int vector, void *param)
{
arm_arch_timer_set_value(timer_step);
rt_tick_increase();
}
static int arm_arch_timer_post_init(void)
{
arm_arch_timer_local_enable();
return 0;
}
INIT_SECONDARY_CPU_EXPORT(arm_arch_timer_post_init);
static rt_err_t arm_arch_timer_probe(struct rt_platform_device *pdev)
{
int mode_idx, irq_idx;
const char *irq_name[] =
{
"phys", /* Secure Phys IRQ */
"virt", /* Non-secure Phys IRQ */
"hyp-phys", /* Virt IRQ */
"hyp-virt", /* Hyp IRQ */
};
#if defined(ARCH_SUPPORT_TEE)
mode_idx = 0;
irq_idx = 0;
#elif defined(ARCH_SUPPORT_HYP)
mode_idx = 2;
irq_idx = 3;
#else
mode_idx = 5;
irq_idx = 1;
#endif
arm_arch_timer_irq = rt_dm_dev_get_irq_by_name(&pdev->parent, irq_name[irq_idx]);
if (arm_arch_timer_irq < 0)
{
arm_arch_timer_irq = rt_dm_dev_get_irq(&pdev->parent, irq_idx);
}
if (arm_arch_timer_irq < 0)
{
return -RT_EEMPTY;
}
arm_arch_timer_ctrl_handle = ctrl_handle[mode_idx];
arm_arch_timer_value_handle = value_handle[mode_idx];
rt_hw_interrupt_install(arm_arch_timer_irq, arm_arch_timer_isr, RT_NULL, "tick-arm-timer");
timer_step = arm_arch_timer_get_frequency() / RT_TICK_PER_SECOND;
arm_arch_timer_local_enable();
return RT_EOK;
}
static const struct rt_ofw_node_id arm_arch_timer_ofw_ids[] =
{
{ .compatible = "arm,armv7-timer", },
{ .compatible = "arm,armv8-timer", },
{ /* sentinel */ }
};
static struct rt_platform_driver arm_arch_timer_driver =
{
.name = "arm-arch-timer",
.ids = arm_arch_timer_ofw_ids,
.probe = arm_arch_timer_probe,
};
static int arm_arch_timer_drv_register(void)
{
rt_platform_driver_register(&arm_arch_timer_driver);
return 0;
}
INIT_SUBSYS_EXPORT(arm_arch_timer_drv_register);

410
rt-thread/components/drivers/hwtimer/hwtimer.c Normal file
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@@ -0,0 +1,410 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2015-08-31 heyuanjie87 first version
*/
#include <rtdevice.h>
#include <rthw.h>
#define DBG_TAG "hwtimer"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#ifdef RT_USING_DM
void (*rt_device_hwtimer_us_delay)(rt_uint32_t us) = RT_NULL;
void rt_hw_us_delay(rt_uint32_t us)
{
if (rt_device_hwtimer_us_delay)
{
rt_device_hwtimer_us_delay(us);
}
else
{
LOG_E("Implemented at least in the libcpu");
RT_ASSERT(0);
}
}
#endif /* RT_USING_DM */
rt_inline rt_uint32_t timeout_calc(rt_hwtimer_t *timer, rt_hwtimerval_t *tv)
{
float overflow;
float timeout;
rt_uint32_t counter;
int i, index = 0;
float tv_sec;
float devi_min = 1;
float devi;
/* changed to second */
overflow = timer->info->maxcnt/(float)timer->freq;
tv_sec = tv->sec + tv->usec/(float)1000000;
if (tv_sec < (1/(float)timer->freq))
{
/* little timeout */
i = 0;
timeout = 1/(float)timer->freq;
}
else
{
for (i = 1; i > 0; i ++)
{
timeout = tv_sec/i;
if (timeout <= overflow)
{
counter = (rt_uint32_t)(timeout * timer->freq);
devi = tv_sec - (counter / (float)timer->freq) * i;
/* Minimum calculation error */
if (devi > devi_min)
{
i = index;
timeout = tv_sec/i;
break;
}
else if (devi == 0)
{
break;
}
else if (devi < devi_min)
{
devi_min = devi;
index = i;
}
}
}
}
timer->cycles = i;
timer->reload = i;
timer->period_sec = timeout;
counter = (rt_uint32_t)(timeout * timer->freq);
return counter;
}
static rt_err_t rt_hwtimer_init(struct rt_device *dev)
{
rt_err_t result = RT_EOK;
rt_hwtimer_t *timer;
timer = (rt_hwtimer_t *)dev;
/* try to change to 1MHz */
if ((1000000 <= timer->info->maxfreq) && (1000000 >= timer->info->minfreq))
{
timer->freq = 1000000;
}
else
{
timer->freq = timer->info->minfreq;
}
timer->mode = HWTIMER_MODE_ONESHOT;
timer->cycles = 0;
timer->overflow = 0;
if (timer->ops->init)
{
timer->ops->init(timer, 1);
}
else
{
result = -RT_ENOSYS;
}
return result;
}
static rt_err_t rt_hwtimer_open(struct rt_device *dev, rt_uint16_t oflag)
{
rt_err_t result = RT_EOK;
rt_hwtimer_t *timer;
timer = (rt_hwtimer_t *)dev;
if (timer->ops->control != RT_NULL)
{
timer->ops->control(timer, HWTIMER_CTRL_FREQ_SET, &timer->freq);
}
else
{
result = -RT_ENOSYS;
}
return result;
}
static rt_err_t rt_hwtimer_close(struct rt_device *dev)
{
rt_err_t result = RT_EOK;
rt_hwtimer_t *timer;
timer = (rt_hwtimer_t*)dev;
if (timer->ops->init != RT_NULL)
{
timer->ops->init(timer, 0);
}
else
{
result = -RT_ENOSYS;
}
dev->flag &= ~RT_DEVICE_FLAG_ACTIVATED;
dev->rx_indicate = RT_NULL;
return result;
}
static rt_ssize_t rt_hwtimer_read(struct rt_device *dev, rt_off_t pos, void *buffer, rt_size_t size)
{
rt_hwtimer_t *timer;
rt_hwtimerval_t tv;
rt_uint32_t cnt;
rt_base_t level;
rt_int32_t overflow;
float t;
timer = (rt_hwtimer_t *)dev;
if (timer->ops->count_get == RT_NULL)
return 0;
level = rt_hw_interrupt_disable();
cnt = timer->ops->count_get(timer);
overflow = timer->overflow;
rt_hw_interrupt_enable(level);
if (timer->info->cntmode == HWTIMER_CNTMODE_DW)
{
cnt = (rt_uint32_t)(timer->freq * timer->period_sec) - cnt;
}
if (timer->mode == HWTIMER_MODE_ONESHOT)
{
overflow = 0;
}
t = overflow * timer->period_sec + cnt/(float)timer->freq;
tv.sec = (rt_int32_t)t;
tv.usec = (rt_int32_t)((t - tv.sec) * 1000000);
size = size > sizeof(tv)? sizeof(tv) : size;
rt_memcpy(buffer, &tv, size);
return size;
}
static rt_ssize_t rt_hwtimer_write(struct rt_device *dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
rt_base_t level;
rt_uint32_t t;
rt_hwtimer_mode_t opm = HWTIMER_MODE_PERIOD;
rt_hwtimer_t *timer;
timer = (rt_hwtimer_t *)dev;
if ((timer->ops->start == RT_NULL) || (timer->ops->stop == RT_NULL))
return 0;
if (size != sizeof(rt_hwtimerval_t))
return 0;
timer->ops->stop(timer);
level = rt_hw_interrupt_disable();
timer->overflow = 0;
rt_hw_interrupt_enable(level);
t = timeout_calc(timer, (rt_hwtimerval_t*)buffer);
if ((timer->cycles <= 1) && (timer->mode == HWTIMER_MODE_ONESHOT))
{
opm = HWTIMER_MODE_ONESHOT;
}
if (timer->ops->start(timer, t, opm) != RT_EOK)
size = 0;
return size;
}
static rt_err_t rt_hwtimer_control(struct rt_device *dev, int cmd, void *args)
{
rt_base_t level;
rt_err_t result = RT_EOK;
rt_hwtimer_t *timer;
timer = (rt_hwtimer_t *)dev;
switch (cmd)
{
case HWTIMER_CTRL_STOP:
{
if (timer->ops->stop != RT_NULL)
{
timer->ops->stop(timer);
}
else
{
result = -RT_ENOSYS;
}
}
break;
case HWTIMER_CTRL_FREQ_SET:
{
rt_int32_t *f;
if (args == RT_NULL)
{
result = -RT_EEMPTY;
break;
}
f = (rt_int32_t*)args;
if ((*f > timer->info->maxfreq) || (*f < timer->info->minfreq))
{
LOG_W("frequency setting out of range! It will maintain at %d Hz", timer->freq);
result = -RT_EINVAL;
break;
}
if (timer->ops->control != RT_NULL)
{
result = timer->ops->control(timer, cmd, args);
if (result == RT_EOK)
{
level = rt_hw_interrupt_disable();
timer->freq = *f;
rt_hw_interrupt_enable(level);
}
}
else
{
result = -RT_ENOSYS;
}
}
break;
case HWTIMER_CTRL_INFO_GET:
{
if (args == RT_NULL)
{
result = -RT_EEMPTY;
break;
}
*((struct rt_hwtimer_info*)args) = *timer->info;
}
break;
case HWTIMER_CTRL_MODE_SET:
{
rt_hwtimer_mode_t *m;
if (args == RT_NULL)
{
result = -RT_EEMPTY;
break;
}
m = (rt_hwtimer_mode_t*)args;
if ((*m != HWTIMER_MODE_ONESHOT) && (*m != HWTIMER_MODE_PERIOD))
{
result = -RT_ERROR;
break;
}
level = rt_hw_interrupt_disable();
timer->mode = *m;
rt_hw_interrupt_enable(level);
}
break;
default:
{
result = -RT_ENOSYS;
}
break;
}
return result;
}
void rt_device_hwtimer_isr(rt_hwtimer_t *timer)
{
rt_base_t level;
RT_ASSERT(timer != RT_NULL);
level = rt_hw_interrupt_disable();
timer->overflow ++;
if (timer->cycles != 0)
{
timer->cycles --;
}
if (timer->cycles == 0)
{
timer->cycles = timer->reload;
rt_hw_interrupt_enable(level);
if (timer->mode == HWTIMER_MODE_ONESHOT)
{
if (timer->ops->stop != RT_NULL)
{
timer->ops->stop(timer);
}
}
if (timer->parent.rx_indicate != RT_NULL)
{
timer->parent.rx_indicate(&timer->parent, sizeof(struct rt_hwtimerval));
}
}
else
{
rt_hw_interrupt_enable(level);
}
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops hwtimer_ops =
{
rt_hwtimer_init,
rt_hwtimer_open,
rt_hwtimer_close,
rt_hwtimer_read,
rt_hwtimer_write,
rt_hwtimer_control
};
#endif
rt_err_t rt_device_hwtimer_register(rt_hwtimer_t *timer, const char *name, void *user_data)
{
struct rt_device *device;
RT_ASSERT(timer != RT_NULL);
RT_ASSERT(timer->ops != RT_NULL);
RT_ASSERT(timer->info != RT_NULL);
device = &(timer->parent);
device->type = RT_Device_Class_Timer;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
#ifdef RT_USING_DEVICE_OPS
device->ops = &hwtimer_ops;
#else
device->init = rt_hwtimer_init;
device->open = rt_hwtimer_open;
device->close = rt_hwtimer_close;
device->read = rt_hwtimer_read;
device->write = rt_hwtimer_write;
device->control = rt_hwtimer_control;
#endif
device->user_data = user_data;
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
}

219
rt-thread/components/drivers/i2c/Kconfig Normal file
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@@ -0,0 +1,219 @@
config RT_USING_I2C
bool "Using I2C device drivers"
default n
if RT_USING_I2C
config RT_I2C_DEBUG
bool "Use I2C debug message"
default n
config RT_USING_I2C_BITOPS
bool "Use GPIO to simulate I2C"
default y
if RT_USING_I2C_BITOPS
config RT_I2C_BITOPS_DEBUG
bool "Use simulate I2C debug message"
default n
endif
config RT_USING_SOFT_I2C
bool "Use GPIO to soft simulate I2C"
default n
select RT_USING_PIN
select RT_USING_I2C_BITOPS
if RT_USING_SOFT_I2C
config RT_USING_SOFT_I2C1
bool "Enable I2C1 Bus (software simulation)"
default y
if RT_USING_SOFT_I2C1
config RT_SOFT_I2C1_SCL_PIN
int "SCL pin number"
range 0 32767
default 1
config RT_SOFT_I2C1_SDA_PIN
int "SDA pin number"
range 0 32767
default 2
config RT_SOFT_I2C1_BUS_NAME
string "Bus name"
default "i2c1"
config RT_SOFT_I2C1_TIMING_DELAY
int "Timing delay (us)"
range 0 32767
default 10
config RT_SOFT_I2C1_TIMING_TIMEOUT
int "Timing timeout (tick)"
range 0 32767
default 10
endif
config RT_USING_SOFT_I2C2
bool "Enable I2C2 Bus (software simulation)"
default n
if RT_USING_SOFT_I2C2
config RT_SOFT_I2C2_SCL_PIN
int "SCL pin number"
range 0 32767
default 3
config RT_SOFT_I2C2_SDA_PIN
int "SDA pin number"
range 0 32767
default 4
config RT_SOFT_I2C2_BUS_NAME
string "Bus name"
default "i2c2"
config RT_SOFT_I2C2_TIMING_DELAY
int "Timing delay (us)"
range 0 32767
default 10
config RT_SOFT_I2C2_TIMING_TIMEOUT
int "Timing timeout (tick)"
range 0 32767
default 10
endif
config RT_USING_SOFT_I2C3
bool "Enable I2C3 Bus (software simulation)"
default n
if RT_USING_SOFT_I2C3
config RT_SOFT_I2C3_SCL_PIN
int "SCL pin number"
range 0 32767
default 5
config RT_SOFT_I2C3_SDA_PIN
int "SDA pin number"
range 0 32767
default 6
config RT_SOFT_I2C3_BUS_NAME
string "Bus name"
default "i2c3"
config RT_SOFT_I2C3_TIMING_DELAY
int "Timing delay (us)"
range 0 32767
default 10
config RT_SOFT_I2C3_TIMING_TIMEOUT
int "Timing timeout (tick)"
range 0 32767
default 10
endif
config RT_USING_SOFT_I2C4
bool "Enable I2C4 Bus (software simulation)"
default n
if RT_USING_SOFT_I2C4
config RT_SOFT_I2C4_SCL_PIN
int "SCL pin number"
range 0 32767
default 7
config RT_SOFT_I2C4_SDA_PIN
int "SDA pin number"
range 0 32767
default 8
config RT_SOFT_I2C4_BUS_NAME
string "Bus name"
default "i2c4"
config RT_SOFT_I2C4_TIMING_DELAY
int "Timing delay (us)"
range 0 32767
default 10
config RT_SOFT_I2C4_TIMING_TIMEOUT
int "Timing timeout (tick)"
range 0 32767
default 10
endif
config RT_USING_SOFT_I2C5
bool "Enable I2C5 Bus (software simulation)"
default n
if RT_USING_SOFT_I2C5
config RT_SOFT_I2C5_SCL_PIN
int "SCL pin number"
range 0 32767
default 9
config RT_SOFT_I2C5_SDA_PIN
int "SDA pin number"
range 0 32767
default 10
config RT_SOFT_I2C5_BUS_NAME
string "Bus name"
default "i2c5"
config RT_SOFT_I2C5_TIMING_DELAY
int "Timing delay (us)"
range 0 32767
default 10
config RT_SOFT_I2C5_TIMING_TIMEOUT
int "Timing timeout (tick)"
range 0 32767
default 10
endif
config RT_USING_SOFT_I2C6
bool "Enable I2C6 Bus (software simulation)"
default n
if RT_USING_SOFT_I2C6
config RT_SOFT_I2C6_SCL_PIN
int "SCL pin number"
range 0 32767
default 11
config RT_SOFT_I2C6_SDA_PIN
int "SDA pin number"
range 0 32767
default 12
config RT_SOFT_I2C6_BUS_NAME
string "Bus name"
default "i2c6"
config RT_SOFT_I2C6_TIMING_DELAY
int "Timing delay (us)"
range 0 32767
default 10
config RT_SOFT_I2C6_TIMING_TIMEOUT
int "Timing timeout (tick)"
range 0 32767
default 10
endif
config RT_USING_SOFT_I2C7
bool "Enable I2C7 Bus (software simulation)"
default n
if RT_USING_SOFT_I2C7
config RT_SOFT_I2C7_SCL_PIN
int "SCL pin number"
range 0 32767
default 13
config RT_SOFT_I2C7_SDA_PIN
int "SDA pin number"
range 0 32767
default 14
config RT_SOFT_I2C7_BUS_NAME
string "Bus name"
default "i2c7"
config RT_SOFT_I2C7_TIMING_DELAY
int "Timing delay (us)"
range 0 32767
default 10
config RT_SOFT_I2C7_TIMING_TIMEOUT
int "Timing timeout (tick)"
range 0 32767
default 10
endif
config RT_USING_SOFT_I2C8
bool "Enable I2C8 Bus (software simulation)"
default n
if RT_USING_SOFT_I2C8
config RT_SOFT_I2C8_SCL_PIN
int "SCL pin number"
range 0 32767
default 15
config RT_SOFT_I2C8_SDA_PIN
int "SDA pin number"
range 0 32767
default 16
config RT_SOFT_I2C8_BUS_NAME
string "Bus name"
default "i2c8"
config RT_SOFT_I2C8_TIMING_DELAY
int "Timing delay (us)"
range 0 32767
default 10
config RT_SOFT_I2C8_TIMING_TIMEOUT
int "Timing timeout (tick)"
range 0 32767
default 10
endif
endif
endif

22
rt-thread/components/drivers/i2c/SConscript Normal file
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@@ -0,0 +1,22 @@
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
src = Split("""
i2c_core.c
i2c_dev.c
""")
if GetDepend('RT_USING_I2C_BITOPS'):
src = src + ['i2c-bit-ops.c']
if GetDepend('RT_USING_SOFT_I2C'):
src = src + ['soft_i2c.c']
if GetDepend(['RT_USING_DM']):
src += ['i2c_bus.c', 'i2c_dm.c']
# The set of source files associated with this SConscript file.
path = [cwd + '/../include']
group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_I2C'], CPPPATH = path)
Return('group')

464
rt-thread/components/drivers/i2c/i2c-bit-ops.c Normal file
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@@ -0,0 +1,464 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-04-25 weety first version
*/
#include <rtdevice.h>
#define DBG_TAG "I2C"
#ifdef RT_I2C_BITOPS_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif
#include <rtdbg.h>
#define SET_SDA(ops, val) ops->set_sda(ops->data, val)
#define SET_SCL(ops, val) ops->set_scl(ops->data, val)
#define GET_SDA(ops) ops->get_sda(ops->data)
#define GET_SCL(ops) ops->get_scl(ops->data)
rt_inline void i2c_delay(struct rt_i2c_bit_ops *ops)
{
ops->udelay((ops->delay_us + 1) >> 1);
}
rt_inline void i2c_delay2(struct rt_i2c_bit_ops *ops)
{
ops->udelay(ops->delay_us);
}
#define SDA_L(ops) SET_SDA(ops, 0)
#define SDA_H(ops) SET_SDA(ops, 1)
#define SCL_L(ops) SET_SCL(ops, 0)
/**
* release scl line, and wait scl line to high.
*/
static rt_err_t SCL_H(struct rt_i2c_bit_ops *ops)
{
rt_tick_t start;
SET_SCL(ops, 1);
if (!ops->get_scl)
goto done;
start = rt_tick_get();
while (!GET_SCL(ops))
{
if ((rt_tick_get() - start) > ops->timeout)
return -RT_ETIMEOUT;
i2c_delay(ops);
}
#ifdef RT_I2C_BITOPS_DEBUG
if (rt_tick_get() != start)
{
LOG_D("wait %ld tick for SCL line to go high",
rt_tick_get() - start);
}
#endif
done:
i2c_delay(ops);
return RT_EOK;
}
static void i2c_start(struct rt_i2c_bit_ops *ops)
{
#ifdef RT_I2C_BITOPS_DEBUG
if (ops->get_scl && !GET_SCL(ops))
{
LOG_E("I2C bus error, SCL line low");
}
if (ops->get_sda && !GET_SDA(ops))
{
LOG_E("I2C bus error, SDA line low");
}
#endif
SDA_L(ops);
i2c_delay(ops);
SCL_L(ops);
}
static void i2c_restart(struct rt_i2c_bit_ops *ops)
{
SDA_H(ops);
SCL_H(ops);
i2c_delay(ops);
SDA_L(ops);
i2c_delay(ops);
SCL_L(ops);
}
static void i2c_stop(struct rt_i2c_bit_ops *ops)
{
SDA_L(ops);
i2c_delay(ops);
SCL_H(ops);
i2c_delay(ops);
SDA_H(ops);
i2c_delay2(ops);
}
rt_inline rt_bool_t i2c_waitack(struct rt_i2c_bit_ops *ops)
{
rt_bool_t ack;
SDA_H(ops);
i2c_delay(ops);
if (SCL_H(ops) < 0)
{
LOG_W("wait ack timeout");
return -RT_ETIMEOUT;
}
ack = !GET_SDA(ops); /* ACK : SDA pin is pulled low */
LOG_D("%s", ack ? "ACK" : "NACK");
SCL_L(ops);
return ack;
}
static rt_int32_t i2c_writeb(struct rt_i2c_bus_device *bus, rt_uint8_t data)
{
rt_int32_t i;
rt_uint8_t bit;
struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
for (i = 7; i >= 0; i--)
{
SCL_L(ops);
bit = (data >> i) & 1;
SET_SDA(ops, bit);
i2c_delay(ops);
if (SCL_H(ops) < 0)
{
LOG_D("i2c_writeb: 0x%02x, "
"wait scl pin high timeout at bit %d",
data, i);
return -RT_ETIMEOUT;
}
}
SCL_L(ops);
i2c_delay(ops);
return i2c_waitack(ops);
}
static rt_int32_t i2c_readb(struct rt_i2c_bus_device *bus)
{
rt_uint8_t i;
rt_uint8_t data = 0;
struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
SDA_H(ops);
i2c_delay(ops);
for (i = 0; i < 8; i++)
{
data <<= 1;
if (SCL_H(ops) < 0)
{
LOG_D("i2c_readb: wait scl pin high "
"timeout at bit %d", 7 - i);
return -RT_ETIMEOUT;
}
if (GET_SDA(ops))
data |= 1;
SCL_L(ops);
i2c_delay2(ops);
}
return data;
}
static rt_ssize_t i2c_send_bytes(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg *msg)
{
rt_int32_t ret;
rt_size_t bytes = 0;
const rt_uint8_t *ptr = msg->buf;
rt_int32_t count = msg->len;
rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
while (count > 0)
{
ret = i2c_writeb(bus, *ptr);
if ((ret > 0) || (ignore_nack && (ret == 0)))
{
count --;
ptr ++;
bytes ++;
}
else if (ret == 0)
{
LOG_D("send bytes: NACK.");
return 0;
}
else
{
LOG_E("send bytes: error %d", ret);
return ret;
}
}
return bytes;
}
static rt_err_t i2c_send_ack_or_nack(struct rt_i2c_bus_device *bus, int ack)
{
struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
if (ack)
SET_SDA(ops, 0);
i2c_delay(ops);
if (SCL_H(ops) < 0)
{
LOG_E("ACK or NACK timeout.");
return -RT_ETIMEOUT;
}
SCL_L(ops);
return RT_EOK;
}
static rt_ssize_t i2c_recv_bytes(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg *msg)
{
rt_int32_t val;
rt_int32_t bytes = 0; /* actual bytes */
rt_uint8_t *ptr = msg->buf;
rt_int32_t count = msg->len;
const rt_uint32_t flags = msg->flags;
while (count > 0)
{
val = i2c_readb(bus);
if (val >= 0)
{
*ptr = val;
bytes ++;
}
else
{
break;
}
ptr ++;
count --;
LOG_D("recieve bytes: 0x%02x, %s",
val, (flags & RT_I2C_NO_READ_ACK) ?
"(No ACK/NACK)" : (count ? "ACK" : "NACK"));
if (!(flags & RT_I2C_NO_READ_ACK))
{
val = i2c_send_ack_or_nack(bus, count);
if (val < 0)
return val;
}
}
return bytes;
}
static rt_int32_t i2c_send_address(struct rt_i2c_bus_device *bus,
rt_uint8_t addr,
rt_int32_t retries)
{
struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
rt_int32_t i;
rt_err_t ret = 0;
for (i = 0; i <= retries; i++)
{
ret = i2c_writeb(bus, addr);
if (ret == 1 || i == retries)
break;
LOG_D("send stop condition");
i2c_stop(ops);
i2c_delay2(ops);
LOG_D("send start condition");
i2c_start(ops);
}
return ret;
}
static rt_err_t i2c_bit_send_address(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg *msg)
{
rt_uint16_t flags = msg->flags;
rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
rt_uint8_t addr1, addr2;
rt_int32_t retries;
rt_err_t ret;
retries = ignore_nack ? 0 : bus->retries;
if (flags & RT_I2C_ADDR_10BIT)
{
addr1 = 0xf0 | ((msg->addr >> 7) & 0x06);
addr2 = msg->addr & 0xff;
LOG_D("addr1: %d, addr2: %d", addr1, addr2);
ret = i2c_send_address(bus, addr1, retries);
if ((ret != 1) && !ignore_nack)
{
LOG_W("NACK: sending first addr");
return -RT_EIO;
}
ret = i2c_writeb(bus, addr2);
if ((ret != 1) && !ignore_nack)
{
LOG_W("NACK: sending second addr");
return -RT_EIO;
}
if (flags & RT_I2C_RD)
{
LOG_D("send repeated start condition");
i2c_restart(ops);
addr1 |= 0x01;
ret = i2c_send_address(bus, addr1, retries);
if ((ret != 1) && !ignore_nack)
{
LOG_E("NACK: sending repeated addr");
return -RT_EIO;
}
}
}
else
{
/* 7-bit addr */
addr1 = msg->addr << 1;
if (flags & RT_I2C_RD)
addr1 |= 1;
ret = i2c_send_address(bus, addr1, retries);
if ((ret != 1) && !ignore_nack)
return -RT_EIO;
}
return RT_EOK;
}
static rt_ssize_t i2c_bit_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num)
{
struct rt_i2c_msg *msg;
struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
rt_int32_t ret;
rt_uint32_t i;
rt_uint16_t ignore_nack;
if((ops->i2c_pin_init_flag == RT_FALSE) && (ops->pin_init != RT_NULL))
{
ops->pin_init();
ops->i2c_pin_init_flag = RT_TRUE;
}
if (num == 0) return 0;
for (i = 0; i < num; i++)
{
msg = &msgs[i];
ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
if (!(msg->flags & RT_I2C_NO_START))
{
if (i)
{
i2c_restart(ops);
}
else
{
LOG_D("send start condition");
i2c_start(ops);
}
ret = i2c_bit_send_address(bus, msg);
if ((ret != RT_EOK) && !ignore_nack)
{
LOG_D("receive NACK from device addr 0x%02x msg %d",
msgs[i].addr, i);
goto out;
}
}
if (msg->flags & RT_I2C_RD)
{
ret = i2c_recv_bytes(bus, msg);
if (ret >= 1)
{
LOG_D("read %d byte%s", ret, ret == 1 ? "" : "s");
}
if (ret < msg->len)
{
if (ret >= 0)
ret = -RT_EIO;
goto out;
}
}
else
{
ret = i2c_send_bytes(bus, msg);
if (ret >= 1)
{
LOG_D("write %d byte%s", ret, ret == 1 ? "" : "s");
}
if (ret < msg->len)
{
if (ret >= 0)
ret = -RT_ERROR;
goto out;
}
}
}
ret = i;
out:
if (!(msg->flags & RT_I2C_NO_STOP))
{
LOG_D("send stop condition");
i2c_stop(ops);
}
return ret;
}
static const struct rt_i2c_bus_device_ops i2c_bit_bus_ops =
{
i2c_bit_xfer,
RT_NULL,
RT_NULL
};
rt_err_t rt_i2c_bit_add_bus(struct rt_i2c_bus_device *bus,
const char *bus_name)
{
bus->ops = &i2c_bit_bus_ops;
return rt_i2c_bus_device_register(bus, bus_name);
}

182
rt-thread/components/drivers/i2c/i2c_bus.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-12-06 GuEe-GUI first version
*/
#include <rtdevice.h>
#define DBG_TAG "i2c.bus"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
static struct rt_bus i2c_bus;
void i2c_bus_scan_clients(struct rt_i2c_bus_device *bus)
{
#ifdef RT_USING_OFW
if (bus->parent.ofw_node)
{
struct rt_ofw_node *np = bus->parent.ofw_node, *child_np, *i2c_client_np;
rt_ofw_foreach_available_child_node(np, child_np)
{
rt_uint32_t client_addr;
struct rt_i2c_client *client;
if (rt_ofw_prop_read_bool(child_np, "compatible"))
{
i2c_client_np = child_np;
}
else
{
/* Maybe in i2c-mux */
i2c_client_np = rt_ofw_get_next_child(child_np, RT_NULL);
if (!rt_ofw_prop_read_bool(i2c_client_np, "compatible"))
{
continue;
}
}
client = rt_calloc(1, sizeof(*client));
if (!client)
{
rt_ofw_node_put(i2c_client_np);
LOG_E("Not memory to create i2c client: %s",
rt_ofw_node_full_name(i2c_client_np));
return;
}
rt_ofw_prop_read_u32(i2c_client_np, "reg", &client_addr);
client->parent.ofw_node = i2c_client_np;
client->name = rt_ofw_node_name(i2c_client_np);
client->bus = bus;
client->client_addr = client_addr;
rt_i2c_device_register(client);
if (i2c_client_np != child_np)
{
rt_ofw_node_put(i2c_client_np);
}
}
}
#endif /* RT_USING_OFW */
}
rt_err_t rt_i2c_driver_register(struct rt_i2c_driver *driver)
{
RT_ASSERT(driver != RT_NULL);
driver->parent.bus = &i2c_bus;
return rt_driver_register(&driver->parent);
}
rt_err_t rt_i2c_device_register(struct rt_i2c_client *client)
{
RT_ASSERT(client != RT_NULL);
return rt_bus_add_device(&i2c_bus, &client->parent);
}
static rt_bool_t i2c_match(rt_driver_t drv, rt_device_t dev)
{
const struct rt_i2c_device_id *id;
struct rt_i2c_driver *driver = rt_container_of(drv, struct rt_i2c_driver, parent);
struct rt_i2c_client *client = rt_container_of(dev, struct rt_i2c_client, parent);
if ((id = driver->ids))
{
for (; id->name[0]; ++id)
{
if (!rt_strcmp(id->name, client->name))
{
client->id = id;
client->ofw_id = RT_NULL;
return RT_TRUE;
}
}
}
#ifdef RT_USING_OFW
client->ofw_id = rt_ofw_node_match(client->parent.ofw_node, driver->ofw_ids);
if (client->ofw_id)
{
client->id = RT_NULL;
return RT_TRUE;
}
#endif
return RT_FALSE;
}
static rt_err_t i2c_probe(rt_device_t dev)
{
rt_err_t err;
struct rt_i2c_driver *driver = rt_container_of(dev->drv, struct rt_i2c_driver, parent);
struct rt_i2c_client *client = rt_container_of(dev, struct rt_i2c_client, parent);
if (!client->bus)
{
return -RT_EINVAL;
}
err = driver->probe(client);
return err;
}
static rt_err_t i2c_remove(rt_device_t dev)
{
struct rt_i2c_driver *driver = rt_container_of(dev->drv, struct rt_i2c_driver, parent);
struct rt_i2c_client *client = rt_container_of(dev, struct rt_i2c_client, parent);
if (driver && driver->remove)
{
driver->remove(client);
}
return RT_EOK;
}
static rt_err_t i2c_shutdown(rt_device_t dev)
{
struct rt_i2c_driver *driver = rt_container_of(dev->drv, struct rt_i2c_driver, parent);
struct rt_i2c_client *client = rt_container_of(dev, struct rt_i2c_client, parent);
if (driver && driver->shutdown)
{
driver->shutdown(client);
}
return RT_EOK;
}
static struct rt_bus i2c_bus =
{
.name = "i2c",
.match = i2c_match,
.probe = i2c_probe,
.remove = i2c_remove,
.shutdown = i2c_shutdown,
};
static int i2c_bus_init(void)
{
rt_bus_register(&i2c_bus);
return 0;
}
INIT_CORE_EXPORT(i2c_bus_init);

153
rt-thread/components/drivers/i2c/i2c_core.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-04-25 weety first version
* 2021-04-20 RiceChen added support for bus control api
*/
#include <rtdevice.h>
#define DBG_TAG "I2C"
#ifdef RT_I2C_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif
#include <rtdbg.h>
rt_err_t rt_i2c_bus_device_register(struct rt_i2c_bus_device *bus,
const char *bus_name)
{
rt_err_t res = RT_EOK;
rt_mutex_init(&bus->lock, "i2c_bus_lock", RT_IPC_FLAG_PRIO);
if (bus->timeout == 0) bus->timeout = RT_TICK_PER_SECOND;
res = rt_i2c_bus_device_device_init(bus, bus_name);
LOG_I("I2C bus [%s] registered", bus_name);
#ifdef RT_USING_DM
if (!res)
{
i2c_bus_scan_clients(bus);
}
#endif
return res;
}
struct rt_i2c_bus_device *rt_i2c_bus_device_find(const char *bus_name)
{
struct rt_i2c_bus_device *bus;
rt_device_t dev = rt_device_find(bus_name);
if (dev == RT_NULL || dev->type != RT_Device_Class_I2CBUS)
{
LOG_E("I2C bus %s not exist", bus_name);
return RT_NULL;
}
bus = (struct rt_i2c_bus_device *)dev->user_data;
return bus;
}
rt_ssize_t rt_i2c_transfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num)
{
rt_ssize_t ret;
rt_err_t err;
if (bus->ops->master_xfer)
{
#ifdef RT_I2C_DEBUG
for (ret = 0; ret < num; ret++)
{
LOG_D("msgs[%d] %c, addr=0x%02x, len=%d", ret,
(msgs[ret].flags & RT_I2C_RD) ? 'R' : 'W',
msgs[ret].addr, msgs[ret].len);
}
#endif
err = rt_mutex_take(&bus->lock, RT_WAITING_FOREVER);
if (err != RT_EOK)
{
return (rt_ssize_t)err;
}
ret = bus->ops->master_xfer(bus, msgs, num);
err = rt_mutex_release(&bus->lock);
if (err != RT_EOK)
{
return (rt_ssize_t)err;
}
return ret;
}
else
{
LOG_E("I2C bus operation not supported");
return -RT_EINVAL;
}
}
rt_err_t rt_i2c_control(struct rt_i2c_bus_device *bus,
int cmd,
void *args)
{
rt_err_t ret;
if(bus->ops->i2c_bus_control)
{
ret = bus->ops->i2c_bus_control(bus, cmd, args);
return ret;
}
else
{
LOG_E("I2C bus operation not supported");
return -RT_EINVAL;
}
}
rt_ssize_t rt_i2c_master_send(struct rt_i2c_bus_device *bus,
rt_uint16_t addr,
rt_uint16_t flags,
const rt_uint8_t *buf,
rt_uint32_t count)
{
rt_ssize_t ret;
struct rt_i2c_msg msg;
msg.addr = addr;
msg.flags = flags;
msg.len = count;
msg.buf = (rt_uint8_t *)buf;
ret = rt_i2c_transfer(bus, &msg, 1);
return (ret == 1) ? count : ret;
}
rt_ssize_t rt_i2c_master_recv(struct rt_i2c_bus_device *bus,
rt_uint16_t addr,
rt_uint16_t flags,
rt_uint8_t *buf,
rt_uint32_t count)
{
rt_ssize_t ret;
struct rt_i2c_msg msg;
RT_ASSERT(bus != RT_NULL);
msg.addr = addr;
msg.flags = flags | RT_I2C_RD;
msg.len = count;
msg.buf = buf;
ret = rt_i2c_transfer(bus, &msg, 1);
return (ret == 1) ? count : ret;
}

137
rt-thread/components/drivers/i2c/i2c_dev.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-04-25 weety first version
* 2014-08-03 bernard fix some compiling warning
* 2021-04-20 RiceChen added support for bus clock control
*/
#include <rtdevice.h>
#define DBG_TAG "I2C"
#ifdef RT_I2C_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif
#include <rtdbg.h>
static rt_ssize_t i2c_bus_device_read(rt_device_t dev,
rt_off_t pos,
void *buffer,
rt_size_t count)
{
rt_uint16_t addr;
rt_uint16_t flags;
struct rt_i2c_bus_device *bus = (struct rt_i2c_bus_device *)dev->user_data;
RT_ASSERT(bus != RT_NULL);
RT_ASSERT(buffer != RT_NULL);
LOG_D("I2C bus dev [%s] reading %u bytes.", dev->parent.name, count);
addr = pos & 0xffff;
flags = (pos >> 16) & 0xffff;
return rt_i2c_master_recv(bus, addr, flags, (rt_uint8_t *)buffer, count);
}
static rt_ssize_t i2c_bus_device_write(rt_device_t dev,
rt_off_t pos,
const void *buffer,
rt_size_t count)
{
rt_uint16_t addr;
rt_uint16_t flags;
struct rt_i2c_bus_device *bus = (struct rt_i2c_bus_device *)dev->user_data;
RT_ASSERT(bus != RT_NULL);
RT_ASSERT(buffer != RT_NULL);
LOG_D("I2C bus dev [%s] writing %u bytes.", dev->parent.name, count);
addr = pos & 0xffff;
flags = (pos >> 16) & 0xffff;
return rt_i2c_master_send(bus, addr, flags, (const rt_uint8_t *)buffer, count);
}
static rt_err_t i2c_bus_device_control(rt_device_t dev,
int cmd,
void *args)
{
rt_err_t ret;
struct rt_i2c_priv_data *priv_data;
struct rt_i2c_bus_device *bus = (struct rt_i2c_bus_device *)dev->user_data;
RT_ASSERT(bus != RT_NULL);
switch (cmd)
{
/* set 10-bit addr mode */
case RT_I2C_DEV_CTRL_10BIT:
bus->flags |= RT_I2C_ADDR_10BIT;
break;
case RT_I2C_DEV_CTRL_TIMEOUT:
bus->timeout = *(rt_uint32_t *)args;
break;
case RT_I2C_DEV_CTRL_RW:
priv_data = (struct rt_i2c_priv_data *)args;
ret = rt_i2c_transfer(bus, priv_data->msgs, priv_data->number);
if (ret < 0)
{
return -RT_EIO;
}
break;
default:
return rt_i2c_control(bus, cmd, args);
}
return RT_EOK;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops i2c_ops =
{
RT_NULL,
RT_NULL,
RT_NULL,
i2c_bus_device_read,
i2c_bus_device_write,
i2c_bus_device_control
};
#endif
rt_err_t rt_i2c_bus_device_device_init(struct rt_i2c_bus_device *bus,
const char *name)
{
struct rt_device *device;
RT_ASSERT(bus != RT_NULL);
device = &bus->parent;
device->user_data = bus;
/* set device type */
device->type = RT_Device_Class_I2CBUS;
/* initialize device interface */
#ifdef RT_USING_DEVICE_OPS
device->ops = &i2c_ops;
#else
device->init = RT_NULL;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = i2c_bus_device_read;
device->write = i2c_bus_device_write;
device->control = i2c_bus_device_control;
#endif
/* register to device manager */
rt_device_register(device, name, RT_DEVICE_FLAG_RDWR);
return RT_EOK;
}

50
rt-thread/components/drivers/i2c/i2c_dm.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-12-06 GuEe-GUI first version
*/
#include <rtdevice.h>
#define DBG_TAG "i2c.dm"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#ifdef RT_USING_OFW
static void i2c_parse_timing(struct rt_ofw_node *dev_np, const char *propname,
rt_uint32_t *out_value, rt_uint32_t def_value, rt_bool_t use_defaults)
{
if (rt_ofw_prop_read_u32(dev_np, propname, out_value) && use_defaults)
{
*out_value = def_value;
}
}
rt_err_t i2c_timings_ofw_parse(struct rt_ofw_node *dev_np, struct i2c_timings *timings,
rt_bool_t use_defaults)
{
rt_ubase_t def;
rt_bool_t udef = use_defaults;
struct i2c_timings *t = timings;
i2c_parse_timing(dev_np, "clock-frequency", &t->bus_freq_hz, I2C_MAX_STANDARD_MODE_FREQ, udef);
def = t->bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ ? 1000 : t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ ? 300 : 120;
i2c_parse_timing(dev_np, "i2c-scl-rising-time-ns", &t->scl_rise_ns, def, udef);
def = t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ ? 300 : 120;
i2c_parse_timing(dev_np, "i2c-scl-falling-time-ns", &t->scl_fall_ns, def, udef);
i2c_parse_timing(dev_np, "i2c-scl-internal-delay-ns", &t->scl_int_delay_ns, 0, udef);
i2c_parse_timing(dev_np, "i2c-sda-falling-time-ns", &t->sda_fall_ns, t->scl_fall_ns, udef);
i2c_parse_timing(dev_np, "i2c-sda-hold-time-ns", &t->sda_hold_ns, 0, udef);
i2c_parse_timing(dev_np, "i2c-digital-filter-width-ns", &t->digital_filter_width_ns, 0, udef);
i2c_parse_timing(dev_np, "i2c-analog-filter-cutoff-frequency", &t->analog_filter_cutoff_freq_hz, 0, udef);
return RT_EOK;
}
#endif /* RT_USING_OFW */

264
rt-thread/components/drivers/i2c/soft_i2c.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-07-30 sp-cai first version
*/
#include <rtdevice.h>
#ifdef RT_USING_SOFT_I2C
#if !defined(RT_USING_SOFT_I2C1) && !defined(RT_USING_SOFT_I2C2) &&\
!defined(RT_USING_SOFT_I2C3) && !defined(RT_USING_SOFT_I2C4) &&\
!defined(RT_USING_SOFT_I2C5) && !defined(RT_USING_SOFT_I2C6) &&\
!defined(RT_USING_SOFT_I2C7) && !defined(RT_USING_SOFT_I2C8)
#error "Please define at least one RT_USING_SOFT_I2Cx"
/*
This driver can be disabled at:
menuconfig -> RT-Thread Components -> Device Drivers -> Using I2C device drivers
*/
#endif
#define DBG_ENABLE
#define DBG_TAG "I2C_S"
#ifdef RT_I2C_BITOPS_DEBUG
#define DBG_LEVEL DBG_LOG
#endif
#include <rtdbg.h>
/* i2c config class */
struct soft_i2c_config
{
rt_base_t scl_pin;
rt_base_t sda_pin;
const char *bus_name;
rt_uint16_t timing_delay; /* scl and sda line delay */
rt_uint16_t timing_timeout; /* in tick */
};
/* i2c dirver class */
struct rt_soft_i2c
{
struct rt_i2c_bus_device i2c_bus;
struct rt_i2c_bit_ops ops;
};
struct soft_i2c_config i2c_cfg[] =
{
#ifdef RT_USING_SOFT_I2C1
{
.scl_pin = RT_SOFT_I2C1_SCL_PIN,
.sda_pin = RT_SOFT_I2C1_SDA_PIN,
.bus_name = RT_SOFT_I2C1_BUS_NAME,
.timing_delay = RT_SOFT_I2C1_TIMING_DELAY,
.timing_timeout = RT_SOFT_I2C1_TIMING_TIMEOUT,
},
#endif //RT_USING_SOFT_I2C1
#ifdef RT_USING_SOFT_I2C2
{
.scl_pin = RT_SOFT_I2C2_SCL_PIN,
.sda_pin = RT_SOFT_I2C2_SDA_PIN,
.bus_name = RT_SOFT_I2C2_BUS_NAME,
.timing_delay = RT_SOFT_I2C2_TIMING_DELAY,
.timing_timeout = RT_SOFT_I2C2_TIMING_TIMEOUT,
},
#endif //RT_USING_SOFT_I2C2
#ifdef RT_USING_SOFT_I2C3
{
.scl_pin = RT_SOFT_I2C3_SCL_PIN,
.sda_pin = RT_SOFT_I2C3_SDA_PIN,
.bus_name = RT_SOFT_I2C3_BUS_NAME,
.timing_delay = RT_SOFT_I2C3_TIMING_DELAY,
.timing_timeout = RT_SOFT_I2C3_TIMING_TIMEOUT,
},
#endif //RT_USING_SOFT_I2C3
#ifdef RT_USING_SOFT_I2C4
{
.scl_pin = RT_SOFT_I2C4_SCL_PIN,
.sda_pin = RT_SOFT_I2C4_SDA_PIN,
.bus_name = RT_SOFT_I2C4_BUS_NAME,
.timing_delay = RT_SOFT_I2C4_TIMING_DELAY,
.timing_timeout = RT_SOFT_I2C4_TIMING_TIMEOUT,
},
#endif //RT_USING_SOFT_I2C4
#ifdef RT_USING_SOFT_I2C5
{
.scl_pin = RT_SOFT_I2C5_SCL_PIN,
.sda_pin = RT_SOFT_I2C5_SDA_PIN,
.bus_name = RT_SOFT_I2C5_BUS_NAME,
.timing_delay = RT_SOFT_I2C5_TIMING_DELAY,
.timing_timeout = RT_SOFT_I2C5_TIMING_TIMEOUT,
},
#endif //RT_USING_SOFT_I2C5
#ifdef RT_USING_SOFT_I2C6
{
.scl_pin = RT_SOFT_I2C6_SCL_PIN,
.sda_pin = RT_SOFT_I2C6_SDA_PIN,
.bus_name = RT_SOFT_I2C6_BUS_NAME,
.timing_delay = RT_SOFT_I2C6_TIMING_DELAY,
.timing_timeout = RT_SOFT_I2C6_TIMING_TIMEOUT,
},
#endif //RT_USING_SOFT_I2C6
#ifdef RT_USING_SOFT_I2C7
{
.scl_pin = RT_SOFT_I2C7_SCL_PIN,
.sda_pin = RT_SOFT_I2C7_SDA_PIN,
.bus_name = RT_SOFT_I2C7_BUS_NAME,
.timing_delay = RT_SOFT_I2C7_TIMING_DELAY,
.timing_timeout = RT_SOFT_I2C7_TIMING_TIMEOUT,
},
#endif //RT_USING_SOFT_I2C7
#ifdef RT_USING_SOFT_I2C8
{
.scl_pin = RT_SOFT_I2C8_SCL_PIN,
.sda_pin = RT_SOFT_I2C8_SDA_PIN,
.bus_name = RT_SOFT_I2C8_BUS_NAME,
.timing_delay = RT_SOFT_I2C8_TIMING_DELAY,
.timing_timeout = RT_SOFT_I2C8_TIMING_TIMEOUT,
},
#endif //RT_USING_SOFT_I2C8
};
static struct rt_soft_i2c i2c_bus_obj[sizeof(i2c_cfg) / sizeof(i2c_cfg[0])] =
{ 0 };
/**
* This function initializes the i2c pin.
* @param i2c config class.
*/
static void pin_init(const struct soft_i2c_config *cfg)
{
rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT_OD);
rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT_OD);
rt_pin_write(cfg->scl_pin, PIN_HIGH);
rt_pin_write(cfg->sda_pin, PIN_HIGH);
}
/**
* This function sets the sda pin.
* @param i2c config class.
* @param The sda pin state.
*/
static void set_sda(void *cfg, rt_int32_t value)
{
rt_pin_write(((const struct soft_i2c_config*)cfg)->sda_pin, value);
}
/**
* This function sets the scl pin.
* @param i2c config class.
* @param The sda pin state.
*/
static void set_scl(void *cfg, rt_int32_t value)
{
rt_pin_write(((const struct soft_i2c_config*)cfg)->scl_pin, value);
}
/**
* This function gets the sda pin state.
* @param i2c config class.
*/
static rt_int32_t get_sda(void *cfg)
{
return rt_pin_read(((const struct soft_i2c_config*)cfg)->sda_pin);
}
/**
* This function gets the scl pin state.
* @param i2c config class.
*/
static rt_int32_t get_scl(void *cfg)
{
return rt_pin_read(((const struct soft_i2c_config*)cfg)->scl_pin);
}
static const struct rt_i2c_bit_ops soft_i2c_ops =
{
.set_sda = set_sda,
.set_scl = set_scl,
.get_sda = get_sda,
.get_scl = get_scl,
.udelay = rt_hw_us_delay,
};
/**
* if i2c is locked, this function will unlock it
*
* @param i2c config class.
*
* @return RT_EOK indicates successful unlock.
*/
static rt_err_t i2c_bus_unlock(const struct soft_i2c_config *cfg)
{
rt_ubase_t i = 0;
if(PIN_LOW == rt_pin_read(cfg->sda_pin))
{
while(i++ < 9)
{
rt_pin_write(cfg->scl_pin, PIN_HIGH);
rt_hw_us_delay(cfg->timing_delay);
rt_pin_write(cfg->scl_pin, PIN_LOW);
rt_hw_us_delay(cfg->timing_delay);
}
}
if(PIN_LOW == rt_pin_read(cfg->sda_pin))
{
return -RT_ERROR;
}
return RT_EOK;
}
/* I2C initialization function */
int rt_soft_i2c_init(void)
{
int err = RT_EOK;
struct rt_soft_i2c *obj;
int i;
for(i = 0; i < sizeof(i2c_bus_obj) / sizeof(i2c_bus_obj[0]); i++)
{
struct soft_i2c_config *cfg = &i2c_cfg[i];
pin_init(cfg);
obj = &i2c_bus_obj[i];
obj->ops = soft_i2c_ops;
obj->ops.data = cfg;
obj->i2c_bus.priv = &obj->ops;
obj->ops.delay_us = cfg->timing_delay;
obj->ops.timeout = cfg->timing_timeout;
if(rt_i2c_bit_add_bus(&obj->i2c_bus, cfg->bus_name) == RT_EOK)
{
i2c_bus_unlock(cfg);
LOG_D("Software simulation %s init done"
", SCL pin: 0x%02X, SDA pin: 0x%02X"
, cfg->bus_name
, cfg->scl_pin
, cfg->sda_pin
);
}
else
{
err++;
LOG_E("Software simulation %s init fail"
", SCL pin: 0x%02X, SDA pin: 0x%02X"
, cfg->bus_name
, cfg->scl_pin
, cfg->sda_pin
);
}
}
return err;
}
INIT_PREV_EXPORT(rt_soft_i2c_init);
#endif // RT_USING_SOFT_I2C

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rt-thread/components/drivers/include/drivers/adc.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-07 aozima the first version
* 2018-11-16 Ernest Chen add finsh command and update adc function
* 2022-05-11 Stanley Lwin add finsh voltage conversion command
*/
#ifndef __ADC_H__
#define __ADC_H__
#include <rtthread.h>
#define RT_ADC_INTERN_CH_TEMPER (-1)
#define RT_ADC_INTERN_CH_VREF (-2)
#define RT_ADC_INTERN_CH_VBAT (-3)
struct rt_adc_device;
struct rt_adc_ops
{
rt_err_t (*enabled)(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled);
rt_err_t (*convert)(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value);
rt_uint8_t (*get_resolution)(struct rt_adc_device *device);
rt_int16_t (*get_vref) (struct rt_adc_device *device);
};
struct rt_adc_device
{
struct rt_device parent;
const struct rt_adc_ops *ops;
};
typedef struct rt_adc_device *rt_adc_device_t;
typedef enum
{
RT_ADC_CMD_ENABLE = RT_DEVICE_CTRL_BASE(ADC) + 1,
RT_ADC_CMD_DISABLE = RT_DEVICE_CTRL_BASE(ADC) + 2,
RT_ADC_CMD_GET_RESOLUTION = RT_DEVICE_CTRL_BASE(ADC) + 3, /* get the resolution in bits */
RT_ADC_CMD_GET_VREF = RT_DEVICE_CTRL_BASE(ADC) + 4, /* get reference voltage */
} rt_adc_cmd_t;
rt_err_t rt_hw_adc_register(rt_adc_device_t adc,const char *name, const struct rt_adc_ops *ops, const void *user_data);
rt_uint32_t rt_adc_read(rt_adc_device_t dev, rt_int8_t channel);
rt_err_t rt_adc_enable(rt_adc_device_t dev, rt_int8_t channel);
rt_err_t rt_adc_disable(rt_adc_device_t dev, rt_int8_t channel);
rt_int16_t rt_adc_voltage(rt_adc_device_t dev, rt_int8_t channel);
#endif /* __ADC_H__ */

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rt-thread/components/drivers/include/drivers/alarm.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-10-27 heyuanjie87 first version.
* 2013-05-17 aozima initial alarm event & mutex in system init.
* 2020-10-15 zhangsz add alarm flags hour minute second.
*/
#ifndef __ALARM_H__
#define __ALARM_H__
#include <sys/time.h>
#include <rtdef.h>
#define RT_ALARM_TM_NOW -1 /* set the alarm tm_day,tm_mon,tm_sec,etc.
to now.we also call it "don't care" value */
/* alarm flags */
#define RT_ALARM_ONESHOT 0x000 /* only alarm once */
#define RT_ALARM_DAILY 0x100 /* alarm everyday */
#define RT_ALARM_WEEKLY 0x200 /* alarm weekly at Monday or Friday etc. */
#define RT_ALARM_MONTHLY 0x400 /* alarm monthly at someday */
#define RT_ALARM_YAERLY 0x800 /* alarm yearly at a certain date */
#define RT_ALARM_HOUR 0x1000 /* alarm each hour at a certain min:second */
#define RT_ALARM_MINUTE 0x2000 /* alarm each minute at a certain second */
#define RT_ALARM_SECOND 0x4000 /* alarm each second */
#define RT_ALARM_STATE_INITED 0x02
#define RT_ALARM_STATE_START 0x01
#define RT_ALARM_STATE_STOP 0x00
/* alarm control cmd */
#define RT_ALARM_CTRL_MODIFY 1 /* modify alarm time or alarm flag */
typedef struct rt_alarm *rt_alarm_t;
typedef void (*rt_alarm_callback_t)(rt_alarm_t alarm, time_t timestamp);
struct rt_alarm
{
rt_list_t list;
rt_uint32_t flag;
rt_alarm_callback_t callback;
struct tm wktime;
void *user_data;
};
struct rt_alarm_setup
{
rt_uint32_t flag; /* alarm flag */
struct tm wktime; /* when will the alarm wake up user */
};
struct rt_alarm_container
{
rt_list_t head;
struct rt_mutex mutex;
struct rt_event event;
struct rt_alarm *current;
};
rt_alarm_t rt_alarm_create(rt_alarm_callback_t callback,
struct rt_alarm_setup *setup);
rt_err_t rt_alarm_control(rt_alarm_t alarm, int cmd, void *arg);
void rt_alarm_update(rt_device_t dev, rt_uint32_t event);
rt_err_t rt_alarm_delete(rt_alarm_t alarm);
rt_err_t rt_alarm_start(rt_alarm_t alarm);
rt_err_t rt_alarm_stop(rt_alarm_t alarm);
int rt_alarm_system_init(void);
#endif /* __ALARM_H__ */

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rt-thread/components/drivers/include/drivers/audio.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-05-09 Urey first version
* 2019-07-09 Zero-Free improve device ops interface and data flows
*
*/
#ifndef __AUDIO_H__
#define __AUDIO_H__
#include "audio_pipe.h"
/* AUDIO command */
#define _AUDIO_CTL(a) (RT_DEVICE_CTRL_BASE(Sound) + a)
#define AUDIO_CTL_GETCAPS _AUDIO_CTL(1)
#define AUDIO_CTL_CONFIGURE _AUDIO_CTL(2)
#define AUDIO_CTL_START _AUDIO_CTL(3)
#define AUDIO_CTL_STOP _AUDIO_CTL(4)
#define AUDIO_CTL_GETBUFFERINFO _AUDIO_CTL(5)
/* Audio Device Types */
#define AUDIO_TYPE_QUERY 0x00
#define AUDIO_TYPE_INPUT 0x01
#define AUDIO_TYPE_OUTPUT 0x02
#define AUDIO_TYPE_MIXER 0x04
/* Supported Sampling Rates */
#define AUDIO_SAMP_RATE_8K 0x0001
#define AUDIO_SAMP_RATE_11K 0x0002
#define AUDIO_SAMP_RATE_16K 0x0004
#define AUDIO_SAMP_RATE_22K 0x0008
#define AUDIO_SAMP_RATE_32K 0x0010
#define AUDIO_SAMP_RATE_44K 0x0020
#define AUDIO_SAMP_RATE_48K 0x0040
#define AUDIO_SAMP_RATE_96K 0x0080
#define AUDIO_SAMP_RATE_128K 0x0100
#define AUDIO_SAMP_RATE_160K 0x0200
#define AUDIO_SAMP_RATE_172K 0x0400
#define AUDIO_SAMP_RATE_192K 0x0800
/* Supported Bit Rates */
#define AUDIO_BIT_RATE_22K 0x01
#define AUDIO_BIT_RATE_44K 0x02
#define AUDIO_BIT_RATE_48K 0x04
#define AUDIO_BIT_RATE_96K 0x08
#define AUDIO_BIT_RATE_128K 0x10
#define AUDIO_BIT_RATE_160K 0x20
#define AUDIO_BIT_RATE_172K 0x40
#define AUDIO_BIT_RATE_192K 0x80
/* Support Dsp(input/output) Units controls */
#define AUDIO_DSP_PARAM 0 /* get/set all params */
#define AUDIO_DSP_SAMPLERATE 1 /* samplerate */
#define AUDIO_DSP_CHANNELS 2 /* channels */
#define AUDIO_DSP_SAMPLEBITS 3 /* sample bits width */
/* Supported Mixer Units controls */
#define AUDIO_MIXER_QUERY 0x0000
#define AUDIO_MIXER_MUTE 0x0001
#define AUDIO_MIXER_VOLUME 0x0002
#define AUDIO_MIXER_BASS 0x0004
#define AUDIO_MIXER_MID 0x0008
#define AUDIO_MIXER_TREBLE 0x0010
#define AUDIO_MIXER_EQUALIZER 0x0020
#define AUDIO_MIXER_LINE 0x0040
#define AUDIO_MIXER_DIGITAL 0x0080
#define AUDIO_MIXER_MIC 0x0100
#define AUDIO_MIXER_VITURAL 0x0200
#define AUDIO_MIXER_EXTEND 0x8000 /* extend mixer command */
#define AUDIO_VOLUME_MAX (100)
#define AUDIO_VOLUME_MIN (0)
#define CFG_AUDIO_REPLAY_QUEUE_COUNT 4
enum
{
AUDIO_STREAM_REPLAY = 0,
AUDIO_STREAM_RECORD,
AUDIO_STREAM_LAST = AUDIO_STREAM_RECORD,
};
/* the preferred number and size of audio pipeline buffer for the audio device */
struct rt_audio_buf_info
{
rt_uint8_t *buffer;
rt_uint16_t block_size;
rt_uint16_t block_count;
rt_uint32_t total_size;
};
struct rt_audio_device;
struct rt_audio_caps;
struct rt_audio_configure;
struct rt_audio_ops
{
rt_err_t (*getcaps)(struct rt_audio_device *audio, struct rt_audio_caps *caps);
rt_err_t (*configure)(struct rt_audio_device *audio, struct rt_audio_caps *caps);
rt_err_t (*init)(struct rt_audio_device *audio);
rt_err_t (*start)(struct rt_audio_device *audio, int stream);
rt_err_t (*stop)(struct rt_audio_device *audio, int stream);
rt_ssize_t (*transmit)(struct rt_audio_device *audio, const void *writeBuf, void *readBuf, rt_size_t size);
/* get page size of codec or private buffer's info */
void (*buffer_info)(struct rt_audio_device *audio, struct rt_audio_buf_info *info);
};
struct rt_audio_configure
{
rt_uint32_t samplerate;
rt_uint16_t channels;
rt_uint16_t samplebits;
};
struct rt_audio_caps
{
int main_type;
int sub_type;
union
{
rt_uint32_t mask;
int value;
struct rt_audio_configure config;
} udata;
};
struct rt_audio_replay
{
struct rt_mempool *mp;
struct rt_data_queue queue;
struct rt_mutex lock;
struct rt_completion cmp;
struct rt_audio_buf_info buf_info;
rt_uint8_t *write_data;
rt_uint16_t write_index;
rt_uint16_t read_index;
rt_uint32_t pos;
rt_uint8_t event;
rt_bool_t activated;
};
struct rt_audio_record
{
struct rt_audio_pipe pipe;
rt_bool_t activated;
};
struct rt_audio_device
{
struct rt_device parent;
struct rt_audio_ops *ops;
struct rt_audio_replay *replay;
struct rt_audio_record *record;
};
rt_err_t rt_audio_register(struct rt_audio_device *audio, const char *name, rt_uint32_t flag, void *data);
void rt_audio_tx_complete(struct rt_audio_device *audio);
void rt_audio_rx_done(struct rt_audio_device *audio, rt_uint8_t *pbuf, rt_size_t len);
/* Device Control Commands */
#define CODEC_CMD_RESET 0
#define CODEC_CMD_SET_VOLUME 1
#define CODEC_CMD_GET_VOLUME 2
#define CODEC_CMD_SAMPLERATE 3
#define CODEC_CMD_EQ 4
#define CODEC_CMD_3D 5
#define CODEC_VOLUME_MAX (63)
#endif /* __AUDIO_H__ */

58
rt-thread/components/drivers/include/drivers/byteorder.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-02-25 GuEe-GUI the first version
*/
#ifndef __BYTEORDER__
#define __BYTEORDER__
#ifdef __CHECKER__
#define __bitwise __attribute__((bitwise))
#else
#define __bitwise
#endif
typedef rt_uint16_t __bitwise rt_le16_t;
typedef rt_uint32_t __bitwise rt_le32_t;
typedef rt_uint64_t __bitwise rt_le64_t;
typedef rt_uint16_t __bitwise rt_be16_t;
typedef rt_uint32_t __bitwise rt_be32_t;
typedef rt_uint64_t __bitwise rt_be64_t;
/* gcc defines __BIG_ENDIAN__ on big endian targets */
#if defined(__BIG_ENDIAN__) || defined(ARCH_CPU_BIG_ENDIAN)
#define rt_cpu_to_be16(x) (x)
#define rt_cpu_to_be32(x) (x)
#define rt_cpu_to_be64(x) (x)
#define rt_be16_to_cpu(x) (x)
#define rt_be32_to_cpu(x) (x)
#define rt_be64_to_cpu(x) (x)
#define rt_le16_to_cpu(x) __builtin_bswap16(x)
#define rt_le32_to_cpu(x) __builtin_bswap32(x)
#define rt_le64_to_cpu(x) __builtin_bswap64(x)
#define rt_cpu_to_le16(x) __builtin_bswap16(x)
#define rt_cpu_to_le32(x) __builtin_bswap32(x)
#define rt_cpu_to_le64(x) __builtin_bswap64(x)
#else
#define rt_cpu_to_be16(x) __builtin_bswap16(x)
#define rt_cpu_to_be32(x) __builtin_bswap32(x)
#define rt_cpu_to_be64(x) __builtin_bswap64(x)
#define rt_be16_to_cpu(x) __builtin_bswap16(x)
#define rt_be32_to_cpu(x) __builtin_bswap32(x)
#define rt_be64_to_cpu(x) __builtin_bswap64(x)
#define rt_le16_to_cpu(x) (x)
#define rt_le32_to_cpu(x) (x)
#define rt_le64_to_cpu(x) (x)
#define rt_cpu_to_le16(x) (x)
#define rt_cpu_to_le32(x) (x)
#define rt_cpu_to_le64(x) (x)
#endif /* __BIG_ENDIAN__ || ARCH_CPU_BIG_ENDIAN */
#undef __bitwise
#endif /* __BYTEORDER__ */

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rt-thread/components/drivers/include/drivers/can.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2015-05-14 aubrcool@qq.com first version
* 2015-07-06 Bernard remove RT_CAN_USING_LED.
* 2022-05-08 hpmicro add CANFD support, fixed typos
*/
#ifndef CAN_H_
#define CAN_H_
#include <rtthread.h>
#ifndef RT_CANMSG_BOX_SZ
#define RT_CANMSG_BOX_SZ 16
#endif
#ifndef RT_CANSND_BOX_NUM
#define RT_CANSND_BOX_NUM 1
#endif
enum CAN_DLC
{
CAN_MSG_0BYTE = 0,
CAN_MSG_1BYTE,
CAN_MSG_2BYTES,
CAN_MSG_3BYTES,
CAN_MSG_4BYTES,
CAN_MSG_5BYTES,
CAN_MSG_6BYTES,
CAN_MSG_7BYTES,
CAN_MSG_8BYTES,
CAN_MSG_12BYTES,
CAN_MSG_16BYTES,
CAN_MSG_20BYTES,
CAN_MSG_24BYTES,
CAN_MSG_32BYTES,
CAN_MSG_48BYTES,
CAN_MSG_64BYTES,
};
enum CANBAUD
{
CAN1MBaud = 1000UL * 1000,/* 1 MBit/sec */
CAN800kBaud = 1000UL * 800, /* 800 kBit/sec */
CAN500kBaud = 1000UL * 500, /* 500 kBit/sec */
CAN250kBaud = 1000UL * 250, /* 250 kBit/sec */
CAN125kBaud = 1000UL * 125, /* 125 kBit/sec */
CAN100kBaud = 1000UL * 100, /* 100 kBit/sec */
CAN50kBaud = 1000UL * 50, /* 50 kBit/sec */
CAN20kBaud = 1000UL * 20, /* 20 kBit/sec */
CAN10kBaud = 1000UL * 10 /* 10 kBit/sec */
};
#define RT_CAN_MODE_NORMAL 0
#define RT_CAN_MODE_LISTEN 1
#define RT_CAN_MODE_LOOPBACK 2
#define RT_CAN_MODE_LOOPBACKANLISTEN 3
#define RT_CAN_MODE_PRIV 0x01
#define RT_CAN_MODE_NOPRIV 0x00
/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
* @{
*/
#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */
#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */
struct rt_can_filter_item
{
rt_uint32_t id : 29;
rt_uint32_t ide : 1;
rt_uint32_t rtr : 1;
rt_uint32_t mode : 1;
rt_uint32_t mask;
rt_int32_t hdr_bank;/*Should be defined as:rx.FilterBank,which should be changed to rt_int32_t hdr_bank*/
rt_uint32_t rxfifo;/*Add a configuration item that CAN_RX_FIFO0/CAN_RX_FIFO1*/
#ifdef RT_CAN_USING_HDR
rt_err_t (*ind)(rt_device_t dev, void *args , rt_int32_t hdr, rt_size_t size);
void *args;
#endif /*RT_CAN_USING_HDR*/
};
#ifdef RT_CAN_USING_HDR
#define RT_CAN_FILTER_ITEM_INIT(id,ide,rtr,mode,mask,ind,args) \
{(id), (ide), (rtr), (mode),(mask), -1, CAN_RX_FIFO0,(ind), (args)}/*0:CAN_RX_FIFO0*/
#define RT_CAN_FILTER_STD_INIT(id,ind,args) \
RT_CAN_FILTER_ITEM_INIT(id,0,0,0,0xFFFFFFFF,ind,args)
#define RT_CAN_FILTER_EXT_INIT(id,ind,args) \
RT_CAN_FILTER_ITEM_INIT(id,1,0,0,0xFFFFFFFF,ind,args)
#define RT_CAN_STD_RMT_FILTER_INIT(id,ind,args) \
RT_CAN_FILTER_ITEM_INIT(id,0,1,0,0xFFFFFFFF,ind,args)
#define RT_CAN_EXT_RMT_FILTER_INIT(id,ind,args) \
RT_CAN_FILTER_ITEM_INIT(id,1,1,0,0xFFFFFFFF,ind,args)
#define RT_CAN_STD_RMT_DATA_FILTER_INIT(id,ind,args) \
RT_CAN_FILTER_ITEM_INIT(id,0,0,1,0xFFFFFFFF,ind,args)
#define RT_CAN_EXT_RMT_DATA_FILTER_INIT(id,ind,args) \
RT_CAN_FILTER_ITEM_INIT(id,1,0,1,0xFFFFFFFF,ind,args)
#else
#define RT_CAN_FILTER_ITEM_INIT(id,ide,rtr,mode,mask) \
{(id), (ide), (rtr), (mode), (mask), -1, CAN_RX_FIFO0 }/*0:CAN_RX_FIFO0*/
#define RT_CAN_FILTER_STD_INIT(id) \
RT_CAN_FILTER_ITEM_INIT(id,0,0,0,0xFFFFFFFF)
#define RT_CAN_FILTER_EXT_INIT(id) \
RT_CAN_FILTER_ITEM_INIT(id,1,0,0,0xFFFFFFFF)
#define RT_CAN_STD_RMT_FILTER_INIT(id) \
RT_CAN_FILTER_ITEM_INIT(id,0,1,0,0xFFFFFFFF)
#define RT_CAN_EXT_RMT_FILTER_INIT(id) \
RT_CAN_FILTER_ITEM_INIT(id,1,1,0,0xFFFFFFFF)
#define RT_CAN_STD_RMT_DATA_FILTER_INIT(id) \
RT_CAN_FILTER_ITEM_INIT(id,0,0,1,0xFFFFFFFF)
#define RT_CAN_EXT_RMT_DATA_FILTER_INIT(id) \
RT_CAN_FILTER_ITEM_INIT(id,1,0,1,0xFFFFFFFF)
#endif
struct rt_can_filter_config
{
rt_uint32_t count;
rt_uint32_t actived;
struct rt_can_filter_item *items;
};
struct rt_can_bit_timing
{
rt_uint16_t prescaler; /* Pre-scaler */
rt_uint16_t num_seg1; /* Bit Timing Segment 1, in terms of Tq */
rt_uint16_t num_seg2; /* Bit Timing Segment 2, in terms of Tq */
rt_uint8_t num_sjw; /* Synchronization Jump Width, in terms of Tq */
rt_uint8_t num_sspoff; /* Secondary Sample Point Offset, in terms of Tq */
};
/**
* CAN bit timing configuration list
* NOTE:
* items[0] always for CAN2.0/CANFD Arbitration Phase
* items[1] always for CANFD (if it exists)
*/
struct rt_can_bit_timing_config
{
rt_uint32_t count;
struct rt_can_bit_timing *items;
};
struct can_configure
{
rt_uint32_t baud_rate;
rt_uint32_t msgboxsz;
rt_uint32_t sndboxnumber;
rt_uint32_t mode : 8;
rt_uint32_t privmode : 8;
rt_uint32_t reserved : 16;
rt_uint32_t ticks;
#ifdef RT_CAN_USING_HDR
rt_uint32_t maxhdr;
#endif
#ifdef RT_CAN_USING_CANFD
rt_uint32_t baud_rate_fd; /* CANFD data bit rate*/
rt_uint32_t use_bit_timing: 8; /* Use the bit timing for CAN timing configuration */
rt_uint32_t enable_canfd : 8; /* Enable CAN-FD mode */
rt_uint32_t reserved1 : 16;
/* The below fields take effect only if use_bit_timing is non-zero */
struct rt_can_bit_timing can_timing; /* CAN bit-timing /CANFD bit-timing for arbitration phase */
struct rt_can_bit_timing canfd_timing; /* CANFD bit-timing for datat phase */
#endif
};
#define CANDEFAULTCONFIG \
{\
CAN1MBaud,\
RT_CANMSG_BOX_SZ,\
RT_CANSND_BOX_NUM,\
RT_CAN_MODE_NORMAL,\
};
struct rt_can_ops;
#define RT_CAN_CMD_SET_FILTER 0x13
#define RT_CAN_CMD_SET_BAUD 0x14
#define RT_CAN_CMD_SET_MODE 0x15
#define RT_CAN_CMD_SET_PRIV 0x16
#define RT_CAN_CMD_GET_STATUS 0x17
#define RT_CAN_CMD_SET_STATUS_IND 0x18
#define RT_CAN_CMD_SET_BUS_HOOK 0x19
#define RT_CAN_CMD_SET_CANFD 0x1A
#define RT_CAN_CMD_SET_BAUD_FD 0x1B
#define RT_CAN_CMD_SET_BITTIMING 0x1C
#define RT_DEVICE_CAN_INT_ERR 0x1000
enum RT_CAN_STATUS_MODE
{
NORMAL = 0,
ERRWARNING = 1,
ERRPASSIVE = 2,
BUSOFF = 4,
};
enum RT_CAN_BUS_ERR
{
RT_CAN_BUS_NO_ERR = 0,
RT_CAN_BUS_BIT_PAD_ERR = 1,
RT_CAN_BUS_FORMAT_ERR = 2,
RT_CAN_BUS_ACK_ERR = 3,
RT_CAN_BUS_IMPLICIT_BIT_ERR = 4,
RT_CAN_BUS_EXPLICIT_BIT_ERR = 5,
RT_CAN_BUS_CRC_ERR = 6,
};
struct rt_can_status
{
rt_uint32_t rcverrcnt;
rt_uint32_t snderrcnt;
rt_uint32_t errcode;
rt_uint32_t rcvpkg;
rt_uint32_t dropedrcvpkg;
rt_uint32_t sndpkg;
rt_uint32_t dropedsndpkg;
rt_uint32_t bitpaderrcnt;
rt_uint32_t formaterrcnt;
rt_uint32_t ackerrcnt;
rt_uint32_t biterrcnt;
rt_uint32_t crcerrcnt;
rt_uint32_t rcvchange;
rt_uint32_t sndchange;
rt_uint32_t lasterrtype;
};
#ifdef RT_CAN_USING_HDR
struct rt_can_hdr
{
rt_uint32_t connected;
rt_uint32_t msgs;
struct rt_can_filter_item filter;
struct rt_list_node list;
};
#endif
struct rt_can_device;
typedef rt_err_t (*rt_canstatus_ind)(struct rt_can_device *, void *);
typedef struct rt_can_status_ind_type
{
rt_canstatus_ind ind;
void *args;
} *rt_can_status_ind_type_t;
typedef void (*rt_can_bus_hook)(struct rt_can_device *);
struct rt_can_device
{
struct rt_device parent;
const struct rt_can_ops *ops;
struct can_configure config;
struct rt_can_status status;
rt_uint32_t timerinitflag;
struct rt_timer timer;
struct rt_can_status_ind_type status_indicate;
#ifdef RT_CAN_USING_HDR
struct rt_can_hdr *hdr;
#endif
#ifdef RT_CAN_USING_BUS_HOOK
rt_can_bus_hook bus_hook;
#endif /*RT_CAN_USING_BUS_HOOK*/
struct rt_mutex lock;
void *can_rx;
void *can_tx;
};
typedef struct rt_can_device *rt_can_t;
#define RT_CAN_STDID 0
#define RT_CAN_EXTID 1
#define RT_CAN_DTR 0
#define RT_CAN_RTR 1
typedef struct rt_can_status *rt_can_status_t;
struct rt_can_msg
{
rt_uint32_t id : 29;
rt_uint32_t ide : 1;
rt_uint32_t rtr : 1;
rt_uint32_t rsv : 1;
rt_uint32_t len : 8;
rt_uint32_t priv : 8;
rt_int32_t hdr_index : 8;/*Should be defined as:rx.FilterMatchIndex,which should be changed to rt_int32_t hdr_index : 8*/
#ifdef RT_CAN_USING_CANFD
rt_uint32_t fd_frame : 1;
rt_uint32_t brs : 1;
rt_uint32_t rxfifo : 2;/*Redefined to return :CAN RX FIFO0/CAN RX FIFO1*/
rt_uint32_t reserved : 4;
#else
rt_uint32_t rxfifo : 2;/*Redefined to return :CAN RX FIFO0/CAN RX FIFO1*/
rt_uint32_t reserved : 6;
#endif
#ifdef RT_CAN_USING_CANFD
rt_uint8_t data[64];
#else
rt_uint8_t data[8];
#endif
};
typedef struct rt_can_msg *rt_can_msg_t;
struct rt_can_msg_list
{
struct rt_list_node list;
#ifdef RT_CAN_USING_HDR
struct rt_list_node hdrlist;
struct rt_can_hdr *owner;
#endif
struct rt_can_msg data;
};
struct rt_can_rx_fifo
{
/* software fifo */
struct rt_can_msg_list *buffer;
rt_uint32_t freenumbers;
struct rt_list_node freelist;
struct rt_list_node uselist;
};
#define RT_CAN_SND_RESULT_OK 0
#define RT_CAN_SND_RESULT_ERR 1
#define RT_CAN_SND_RESULT_WAIT 2
#define RT_CAN_EVENT_RX_IND 0x01 /* Rx indication */
#define RT_CAN_EVENT_TX_DONE 0x02 /* Tx complete */
#define RT_CAN_EVENT_TX_FAIL 0x03 /* Tx fail */
#define RT_CAN_EVENT_RX_TIMEOUT 0x05 /* Rx timeout */
#define RT_CAN_EVENT_RXOF_IND 0x06 /* Rx overflow */
struct rt_can_sndbxinx_list
{
struct rt_list_node list;
struct rt_completion completion;
rt_uint32_t result;
};
struct rt_can_tx_fifo
{
struct rt_can_sndbxinx_list *buffer;
struct rt_semaphore sem;
struct rt_list_node freelist;
};
struct rt_can_ops
{
rt_err_t (*configure)(struct rt_can_device *can, struct can_configure *cfg);
rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg);
rt_ssize_t (*sendmsg)(struct rt_can_device *can, const void *buf, rt_uint32_t boxno);
rt_ssize_t (*recvmsg)(struct rt_can_device *can, void *buf, rt_uint32_t boxno);
};
rt_err_t rt_hw_can_register(struct rt_can_device *can,
const char *name,
const struct rt_can_ops *ops,
void *data);
void rt_hw_can_isr(struct rt_can_device *can, int event);
#endif /*_CAN_H*/

42
rt-thread/components/drivers/include/drivers/classes/block.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-10-11 zmshahaha move from <rtdef.h>
*/
#ifndef __BLOCK_H__
#define __BLOCK_H__
#include <rtdef.h>
/* block device commands*/
#define RT_DEVICE_CTRL_BLK_GETGEOME (RT_DEVICE_CTRL_BASE(Block) + 1) /**< get geometry information */
#define RT_DEVICE_CTRL_BLK_SYNC (RT_DEVICE_CTRL_BASE(Block) + 2) /**< flush data to block device */
#define RT_DEVICE_CTRL_BLK_ERASE (RT_DEVICE_CTRL_BASE(Block) + 3) /**< erase block on block device */
#define RT_DEVICE_CTRL_BLK_AUTOREFRESH (RT_DEVICE_CTRL_BASE(Block) + 4) /**< block device : enter/exit auto refresh mode */
#define RT_DEVICE_CTRL_BLK_PARTITION (RT_DEVICE_CTRL_BASE(Block) + 5) /**< get block device partition */
/**
* block device geometry structure
*/
struct rt_device_blk_geometry
{
rt_uint64_t sector_count; /**< count of sectors */
rt_uint32_t bytes_per_sector; /**< number of bytes per sector */
rt_uint32_t block_size; /**< number of bytes to erase one block */
};
/**
* sector arrange struct on block device
*/
struct rt_device_blk_sectors
{
rt_uint64_t sector_begin; /**< begin sector */
rt_uint64_t sector_end; /**< end sector */
};
#endif /* __BLOCK_H__ */

19
rt-thread/components/drivers/include/drivers/classes/char.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-10-11 zmshahaha move from <rtdef.h>
*/
#ifndef __CHAR_H__
#define __CHAR_H__
#include <rtdef.h>
/* char device commands*/
#define RT_DEVICE_CTRL_CHAR_STREAM (RT_DEVICE_CTRL_BASE(Char) + 1) /**< stream mode on char device */
#endif /* __CHAR_H__ */

104
rt-thread/components/drivers/include/drivers/classes/graphic.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-10-11 zmshahaha move from <rtdef.h>
*/
#ifndef __GRAPHIC_H__
#define __GRAPHIC_H__
#include <rtdef.h>
/**
* cursor control command
*/
#define RT_DEVICE_CTRL_CURSOR_SET_POSITION 0x10
#define RT_DEVICE_CTRL_CURSOR_SET_TYPE 0x11
/**
* graphic device control command
*/
#define RTGRAPHIC_CTRL_RECT_UPDATE (RT_DEVICE_CTRL_BASE(Graphic) + 0)
#define RTGRAPHIC_CTRL_POWERON (RT_DEVICE_CTRL_BASE(Graphic) + 1)
#define RTGRAPHIC_CTRL_POWEROFF (RT_DEVICE_CTRL_BASE(Graphic) + 2)
#define RTGRAPHIC_CTRL_GET_INFO (RT_DEVICE_CTRL_BASE(Graphic) + 3)
#define RTGRAPHIC_CTRL_SET_MODE (RT_DEVICE_CTRL_BASE(Graphic) + 4)
#define RTGRAPHIC_CTRL_GET_EXT (RT_DEVICE_CTRL_BASE(Graphic) + 5)
#define RTGRAPHIC_CTRL_SET_BRIGHTNESS (RT_DEVICE_CTRL_BASE(Graphic) + 6)
#define RTGRAPHIC_CTRL_GET_BRIGHTNESS (RT_DEVICE_CTRL_BASE(Graphic) + 7)
#define RTGRAPHIC_CTRL_GET_MODE (RT_DEVICE_CTRL_BASE(Graphic) + 8)
#define RTGRAPHIC_CTRL_GET_STATUS (RT_DEVICE_CTRL_BASE(Graphic) + 9)
#define RTGRAPHIC_CTRL_PAN_DISPLAY (RT_DEVICE_CTRL_BASE(Graphic) + 10)
#define RTGRAPHIC_CTRL_WAIT_VSYNC (RT_DEVICE_CTRL_BASE(Graphic) + 11)
/* graphic device */
enum
{
RTGRAPHIC_PIXEL_FORMAT_MONO = 0,
RTGRAPHIC_PIXEL_FORMAT_GRAY4,
RTGRAPHIC_PIXEL_FORMAT_GRAY16,
RTGRAPHIC_PIXEL_FORMAT_RGB332,
RTGRAPHIC_PIXEL_FORMAT_RGB444,
RTGRAPHIC_PIXEL_FORMAT_RGB565,
RTGRAPHIC_PIXEL_FORMAT_RGB565P,
RTGRAPHIC_PIXEL_FORMAT_BGR565 = RTGRAPHIC_PIXEL_FORMAT_RGB565P,
RTGRAPHIC_PIXEL_FORMAT_RGB666,
RTGRAPHIC_PIXEL_FORMAT_RGB888,
RTGRAPHIC_PIXEL_FORMAT_BGR888,
RTGRAPHIC_PIXEL_FORMAT_ARGB888,
RTGRAPHIC_PIXEL_FORMAT_ABGR888,
RTGRAPHIC_PIXEL_FORMAT_RESERVED,
};
/**
* build a pixel position according to (x, y) coordinates.
*/
#define RTGRAPHIC_PIXEL_POSITION(x, y) ((x << 16) | y)
/**
* graphic device information structure
*/
struct rt_device_graphic_info
{
rt_uint8_t pixel_format; /**< graphic format */
rt_uint8_t bits_per_pixel; /**< bits per pixel */
rt_uint16_t pitch; /**< bytes per line */
rt_uint16_t width; /**< width of graphic device */
rt_uint16_t height; /**< height of graphic device */
rt_uint8_t *framebuffer; /**< frame buffer */
rt_uint32_t smem_len; /**< allocated frame buffer size */
};
/**
* rectangle information structure
*/
struct rt_device_rect_info
{
rt_uint16_t x; /**< x coordinate */
rt_uint16_t y; /**< y coordinate */
rt_uint16_t width; /**< width */
rt_uint16_t height; /**< height */
};
/**
* graphic operations
*/
struct rt_device_graphic_ops
{
void (*set_pixel) (const char *pixel, int x, int y);
void (*get_pixel) (char *pixel, int x, int y);
void (*draw_hline)(const char *pixel, int x1, int x2, int y);
void (*draw_vline)(const char *pixel, int x, int y1, int y2);
void (*blit_line) (const char *pixel, int x, int y, rt_size_t size);
};
#define rt_graphix_ops(device) ((struct rt_device_graphic_ops *)(device->user_data))
#endif /* __GRAPHIC_H__ */

19
rt-thread/components/drivers/include/drivers/classes/mtd.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-10-11 zmshahaha move from <rtdef.h>
*/
#ifndef __MTD_H__
#define __MTD_H__
#include <rtdef.h>
/* mtd interface device*/
#define RT_DEVICE_CTRL_MTD_FORMAT (RT_DEVICE_CTRL_BASE(MTD) + 1) /**< format a MTD device */
#endif /* __MTD_H__ */

19
rt-thread/components/drivers/include/drivers/classes/net.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-10-11 zmshahaha move from <rtdef.h>
*/
#ifndef __NET_H__
#define __NET_H__
#include <rtdef.h>
/* net interface device*/
#define RT_DEVICE_CTRL_NETIF_GETMAC (RT_DEVICE_CTRL_BASE(NetIf) + 1) /**< get mac address */
#endif /* __NET_H__ */

189
rt-thread/components/drivers/include/drivers/clk.h Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-11-26 GuEe-GUI first version
*/
#ifndef __CLK_H__
#define __CLK_H__
#include <rthw.h>
#include <ref.h>
#include <drivers/ofw.h>
struct rt_clk_ops;
struct rt_reset_control_node;
struct rt_clk_node
{
/*
* Defined as the array like this if if the CLK have multi out clocks:
*
* struct XYZ_single_clk
* {
* struct rt_clk_node parent;
* ...
* };
*
* struct XYZ_multi_clk
* {
* struct rt_clk_node parent[N];
* ...
* };
* We assume the 'N' is the max value of element in 'clock-indices' if OFW.
*/
rt_list_t list;
rt_list_t children_nodes;
const char *name;
const struct rt_clk_ops *ops;
struct rt_clk_node *parent;
struct rt_ref ref;
rt_ubase_t rate;
rt_ubase_t min_rate;
rt_ubase_t max_rate;
rt_size_t notifier_count;
void *priv;
struct rt_clk *clk;
rt_size_t multi_clk;
};
struct rt_clk_fixed_rate
{
struct rt_clk_node clk;
rt_ubase_t fixed_rate;
rt_ubase_t fixed_accuracy;
};
struct rt_clk
{
struct rt_clk_node *clk_np;
const char *dev_id;
const char *con_id;
rt_ubase_t rate;
void *fw_node;
void *priv;
};
struct rt_clk_array
{
rt_size_t count;
struct rt_clk *clks[];
};
struct rt_clk_ops
{
rt_err_t (*init)(struct rt_clk *, void *fw_data);
rt_err_t (*finit)(struct rt_clk *);
/* API */
rt_err_t (*prepare)(struct rt_clk *);
void (*unprepare)(struct rt_clk *);
rt_bool_t (*is_prepared)(struct rt_clk *);
rt_err_t (*enable)(struct rt_clk *);
void (*disable)(struct rt_clk *);
rt_bool_t (*is_enabled)(struct rt_clk *);
rt_err_t (*set_rate)(struct rt_clk *, rt_ubase_t rate, rt_ubase_t parent_rate);
rt_err_t (*set_parent)(struct rt_clk *, struct rt_clk *parent);
rt_err_t (*set_phase)(struct rt_clk *, int degrees);
rt_base_t (*get_phase)(struct rt_clk *);
rt_base_t (*round_rate)(struct rt_clk *, rt_ubase_t drate, rt_ubase_t *prate);
};
struct rt_clk_notifier;
#define RT_CLK_MSG_PRE_RATE_CHANGE RT_BIT(0)
#define RT_CLK_MSG_POST_RATE_CHANGE RT_BIT(1)
#define RT_CLK_MSG_ABORT_RATE_CHANGE RT_BIT(2)
typedef rt_err_t (*rt_clk_notifier_callback)(struct rt_clk_notifier *notifier,
rt_ubase_t msg, rt_ubase_t old_rate, rt_ubase_t new_rate);
struct rt_clk_notifier
{
rt_list_t list;
struct rt_clk *clk;
rt_clk_notifier_callback callback;
void *priv;
};
rt_err_t rt_clk_register(struct rt_clk_node *clk_np, struct rt_clk_node *parent_np);
rt_err_t rt_clk_unregister(struct rt_clk_node *clk_np);
rt_err_t rt_clk_notifier_register(struct rt_clk *clk, struct rt_clk_notifier *notifier);
rt_err_t rt_clk_notifier_unregister(struct rt_clk *clk, struct rt_clk_notifier *notifier);
rt_err_t rt_clk_set_parent(struct rt_clk *clk, struct rt_clk *clk_parent);
rt_err_t rt_clk_prepare(struct rt_clk *clk);
rt_err_t rt_clk_unprepare(struct rt_clk *clk);
rt_err_t rt_clk_enable(struct rt_clk *clk);
void rt_clk_disable(struct rt_clk *clk);
rt_err_t rt_clk_prepare_enable(struct rt_clk *clk);
void rt_clk_disable_unprepare(struct rt_clk *clk);
rt_err_t rt_clk_array_prepare(struct rt_clk_array *clk_arr);
rt_err_t rt_clk_array_unprepare(struct rt_clk_array *clk_arr);
rt_err_t rt_clk_array_enable(struct rt_clk_array *clk_arr);
void rt_clk_array_disable(struct rt_clk_array *clk_arr);
rt_err_t rt_clk_array_prepare_enable(struct rt_clk_array *clk_arr);
void rt_clk_array_disable_unprepare(struct rt_clk_array *clk_arr);
rt_err_t rt_clk_set_rate_range(struct rt_clk *clk, rt_ubase_t min, rt_ubase_t max);
rt_err_t rt_clk_set_min_rate(struct rt_clk *clk, rt_ubase_t rate);
rt_err_t rt_clk_set_max_rate(struct rt_clk *clk, rt_ubase_t rate);
rt_err_t rt_clk_set_rate(struct rt_clk *clk, rt_ubase_t rate);
rt_ubase_t rt_clk_get_rate(struct rt_clk *clk);
rt_err_t rt_clk_set_phase(struct rt_clk *clk, int degrees);
rt_base_t rt_clk_get_phase(struct rt_clk *clk);
rt_base_t rt_clk_round_rate(struct rt_clk *clk, rt_ubase_t rate);
struct rt_clk *rt_clk_get_parent(struct rt_clk *clk);
struct rt_clk_array *rt_clk_get_array(struct rt_device *dev);
struct rt_clk *rt_clk_get_by_index(struct rt_device *dev, int index);
struct rt_clk *rt_clk_get_by_name(struct rt_device *dev, const char *name);
void rt_clk_array_put(struct rt_clk_array *clk_arr);
void rt_clk_put(struct rt_clk *clk);
#ifdef RT_USING_OFW
struct rt_clk_array *rt_ofw_get_clk_array(struct rt_ofw_node *np);
struct rt_clk *rt_ofw_get_clk(struct rt_ofw_node *np, int index);
struct rt_clk *rt_ofw_get_clk_by_name(struct rt_ofw_node *np, const char *name);
rt_ssize_t rt_ofw_count_of_clk(struct rt_ofw_node *clk_ofw_np);
#else
rt_inline struct rt_clk *rt_ofw_get_clk(struct rt_ofw_node *np, int index)
{
return RT_NULL;
}
rt_inline struct rt_clk *rt_ofw_get_clk_by_name(struct rt_ofw_node *np, const char *name)
{
return RT_NULL;
}
rt_inline rt_ssize_t rt_ofw_count_of_clk(struct rt_ofw_node *clk_ofw_np)
{
return 0;
}
#endif /* RT_USING_OFW */
#endif /* __CLK_H__ */

54
rt-thread/components/drivers/include/drivers/core/bus.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-04-12 ErikChan the first version
*/
#ifndef __CORE_BUS_H__
#define __CORE_BUS_H__
#include <rthw.h>
#include <rtdef.h>
#include <drivers/core/driver.h>
typedef struct rt_bus *rt_bus_t;
struct rt_bus
{
struct rt_object parent; /**< inherit from rt_object */
const char *name;
rt_list_t list;
rt_list_t dev_list;
rt_list_t drv_list;
struct rt_spinlock dev_lock;
struct rt_spinlock drv_lock;
rt_bool_t (*match)(rt_driver_t drv, rt_device_t dev);
rt_err_t (*probe)(rt_device_t dev);
rt_err_t (*remove)(rt_device_t dev);
rt_err_t (*shutdown)(rt_device_t dev);
};
rt_err_t rt_bus_for_each_dev(rt_bus_t bus, void *data, int (*fn)(rt_device_t dev, void *));
rt_err_t rt_bus_for_each_drv(rt_bus_t bus, void *data, int (*fn)(rt_driver_t drv, void *));
rt_err_t rt_bus_add_driver(rt_bus_t bus, rt_driver_t drv);
rt_err_t rt_bus_add_device(rt_bus_t bus, rt_device_t dev);
rt_err_t rt_bus_remove_driver(rt_driver_t drv);
rt_err_t rt_bus_remove_device(rt_device_t dev);
rt_err_t rt_bus_shutdown(void);
rt_bus_t rt_bus_find_by_name(const char *name);
rt_err_t rt_bus_reload_driver_device(rt_bus_t new_bus, rt_device_t dev);
rt_err_t rt_bus_register(rt_bus_t bus);
#endif /* __BUS_H__ */

165
rt-thread/components/drivers/include/drivers/core/dm.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-04-20 ErikChan the first version
*/
#ifndef __CORE_DM_H__
#define __CORE_DM_H__
#include <rthw.h>
#include <rtdef.h>
#include <ioremap.h>
#include <drivers/misc.h>
#include <drivers/byteorder.h>
#ifndef RT_CPUS_NR
#define RT_CPUS_NR 1
#endif
#ifndef RT_USING_SMP
extern int rt_hw_cpu_id(void);
#endif
void rt_dm_secondary_cpu_init(void);
int rt_dm_dev_set_name_auto(rt_device_t dev, const char *prefix);
int rt_dm_dev_get_name_id(rt_device_t dev);
int rt_dm_dev_set_name(rt_device_t dev, const char *format, ...);
const char *rt_dm_dev_get_name(rt_device_t dev);
int rt_dm_dev_get_address_count(rt_device_t dev);
rt_err_t rt_dm_dev_get_address(rt_device_t dev, int index,
rt_uint64_t *out_address, rt_uint64_t *out_size);
rt_err_t rt_dm_dev_get_address_by_name(rt_device_t dev, const char *name,
rt_uint64_t *out_address, rt_uint64_t *out_size);
int rt_dm_dev_get_address_array(rt_device_t dev, int nr, rt_uint64_t *out_regs);
void *rt_dm_dev_iomap(rt_device_t dev, int index);
void *rt_dm_dev_iomap_by_name(rt_device_t dev, const char *name);
int rt_dm_dev_get_irq_count(rt_device_t dev);
int rt_dm_dev_get_irq(rt_device_t dev, int index);
int rt_dm_dev_get_irq_by_name(rt_device_t dev, const char *name);
void rt_dm_dev_bind_fwdata(rt_device_t dev, void *fw_np, void *data);
void rt_dm_dev_unbind_fwdata(rt_device_t dev, void *fw_np);
int rt_dm_dev_prop_read_u8_array_index(rt_device_t dev, const char *propname,
int index, int nr, rt_uint8_t *out_values);
int rt_dm_dev_prop_read_u16_array_index(rt_device_t dev, const char *propname,
int index, int nr, rt_uint16_t *out_values);
int rt_dm_dev_prop_read_u32_array_index(rt_device_t dev, const char *propname,
int index, int nr, rt_uint32_t *out_values);
int rt_dm_dev_prop_read_u64_array_index(rt_device_t dev, const char *propname,
int index, int nr, rt_uint64_t *out_values);
int rt_dm_dev_prop_read_string_array_index(rt_device_t dev, const char *propname,
int index, int nr, const char **out_strings);
int rt_dm_dev_prop_count_of_size(rt_device_t dev, const char *propname, int size);
int rt_dm_dev_prop_index_of_string(rt_device_t dev, const char *propname, const char *string);
rt_bool_t rt_dm_dev_prop_read_bool(rt_device_t dev, const char *propname);
rt_inline rt_err_t rt_dm_dev_prop_read_u8_index(rt_device_t dev, const char *propname,
int index, rt_uint8_t *out_value)
{
int nr = rt_dm_dev_prop_read_u8_array_index(dev, propname, index, 1, out_value);
return nr > 0 ? RT_EOK : (rt_err_t)nr;
}
rt_inline rt_err_t rt_dm_dev_prop_read_u16_index(rt_device_t dev, const char *propname,
int index, rt_uint16_t *out_value)
{
int nr = rt_dm_dev_prop_read_u16_array_index(dev, propname, index, 1, out_value);
return nr > 0 ? RT_EOK : (rt_err_t)nr;
}
rt_inline rt_err_t rt_dm_dev_prop_read_u32_index(rt_device_t dev, const char *propname,
int index, rt_uint32_t *out_value)
{
int nr = rt_dm_dev_prop_read_u32_array_index(dev, propname, index, 1, out_value);
return nr > 0 ? RT_EOK : (rt_err_t)nr;
}
rt_inline rt_err_t rt_dm_dev_prop_read_u64_index(rt_device_t dev, const char *propname,
int index, rt_uint64_t *out_value)
{
int nr = rt_dm_dev_prop_read_u64_array_index(dev, propname, index, 1, out_value);
return nr > 0 ? RT_EOK : (rt_err_t)nr;
}
rt_inline rt_err_t rt_dm_dev_prop_read_string_index(rt_device_t dev, const char *propname,
int index, const char **out_string)
{
int nr = rt_dm_dev_prop_read_string_array_index(dev, propname, index, 1, out_string);
return nr > 0 ? RT_EOK : (rt_err_t)nr;
}
rt_inline rt_err_t rt_dm_dev_prop_read_u8(rt_device_t dev, const char *propname,
rt_uint8_t *out_value)
{
return rt_dm_dev_prop_read_u8_index(dev, propname, 0, out_value);
}
rt_inline rt_err_t rt_dm_dev_prop_read_u16(rt_device_t dev, const char *propname,
rt_uint16_t *out_value)
{
return rt_dm_dev_prop_read_u16_index(dev, propname, 0, out_value);
}
rt_inline rt_err_t rt_dm_dev_prop_read_u32(rt_device_t dev, const char *propname,
rt_uint32_t *out_value)
{
return rt_dm_dev_prop_read_u32_index(dev, propname, 0, out_value);
}
rt_inline rt_err_t rt_dm_dev_prop_read_s32(rt_device_t dev, const char *propname,
rt_int32_t *out_value)
{
return rt_dm_dev_prop_read_u32_index(dev, propname, 0, (rt_uint32_t *)out_value);
}
rt_inline rt_err_t rt_dm_dev_prop_read_u64(rt_device_t dev, const char *propname,
rt_uint64_t *out_value)
{
return rt_dm_dev_prop_read_u64_index(dev, propname, 0, out_value);
}
rt_inline rt_err_t rt_dm_dev_prop_read_string(rt_device_t dev, const char *propname,
const char **out_string)
{
return rt_dm_dev_prop_read_string_index(dev, propname, 0, out_string);
}
rt_inline int rt_dm_dev_prop_count_of_u8(rt_device_t dev, const char *propname)
{
return rt_dm_dev_prop_count_of_size(dev, propname, sizeof(rt_uint8_t));
}
rt_inline int rt_dm_dev_prop_count_of_u16(rt_device_t dev, const char *propname)
{
return rt_dm_dev_prop_count_of_size(dev, propname, sizeof(rt_uint16_t));
}
rt_inline int rt_dm_dev_prop_count_of_u32(rt_device_t dev, const char *propname)
{
return rt_dm_dev_prop_count_of_size(dev, propname, sizeof(rt_uint32_t));
}
rt_inline int rt_dm_dev_prop_count_of_u64(rt_device_t dev, const char *propname)
{
return rt_dm_dev_prop_count_of_size(dev, propname, sizeof(rt_uint64_t));
}
#endif /* __RT_DM_H__ */

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rt-thread/components/drivers/include/drivers/core/driver.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-04-12 ErikChan the first version
*/
#ifndef __CORE_DRIVER_H__
#define __CORE_DRIVER_H__
#include <rtdef.h>
struct rt_driver
{
struct rt_object parent;
struct rt_bus *bus;
rt_list_t node;
rt_uint32_t ref_count;
#ifdef RT_USING_DEVICE_OPS
const struct rt_device_ops *dev_ops;
#else
/* common device interface */
rt_err_t (*init) (rt_device_t dev);
rt_err_t (*open) (rt_device_t dev, rt_uint16_t oflag);
rt_err_t (*close) (rt_device_t dev);
rt_ssize_t (*read) (rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size);
rt_ssize_t (*write) (rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size);
rt_err_t (*control)(rt_device_t dev, int cmd, void *args);
#endif
const struct filesystem_ops *fops;
int (*probe)(struct rt_device *dev);
int (*remove)(struct rt_device *dev);
int (*shutdown)(struct rt_device *dev);
};
rt_err_t rt_driver_register(rt_driver_t drv);
rt_err_t rt_driver_unregister(rt_driver_t drv);
#define RT_DRIVER_EXPORT(driver, bus_name, mode) \
static int ___##driver##_register(void) \
{ \
rt_##bus_name##_driver_register(&driver); \
return 0; \
} \
INIT_DEVICE_EXPORT(___##driver##_register); \
#endif /* __DRIVER_H__ */

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rt-thread/components/drivers/include/drivers/core/numa.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-09-24 GuEe-GUI the first version
*/
#ifndef __RT_DM_NUMA_H__
#define __RT_DM_NUMA_H__
#include <rthw.h>
#include <rtthread.h>
#include <bitmap.h>
/* NUMA: Non-Uniform Memory Access */
int rt_numa_cpu_id(int cpuid);
int rt_numa_device_id(struct rt_device *dev);
rt_err_t rt_numa_memory_affinity(rt_uint64_t phy_addr, rt_bitmap_t *out_affinity);
#endif /* __RT_DM_NUMA_H__ */

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-11-21 GuEe-GUI first version
*/
#ifndef __RT_DM_POWER_DOMAIN_H__
#define __RT_DM_POWER_DOMAIN_H__
#include <rthw.h>
#include <rtthread.h>
#include <ref.h>
#define RT_POWER_DOMAIN_OBJ_NAME "PMD"
#define RT_POWER_DOMAIN_PROXY_OBJ_NAME "PMP"
struct rt_ofw_node;
struct rt_ofw_cell_args;
struct rt_dm_power_domain_unit
{
rt_list_t list;
int id;
struct rt_dm_power_domain *domain;
};
struct rt_dm_power_domain_proxy
{
struct rt_object parent;
struct rt_dm_power_domain *(*ofw_parse)(struct rt_dm_power_domain_proxy *proxy,
struct rt_ofw_cell_args *args);
};
struct rt_dm_power_domain
{
struct rt_object parent;
struct rt_device *dev;
struct rt_dm_power_domain *parent_domain;
rt_list_t list;
rt_list_t child_nodes;
rt_list_t unit_nodes;
struct rt_ref ref;
struct rt_spinlock lock;
rt_err_t (*power_on)(struct rt_dm_power_domain *domain);
rt_err_t (*power_off)(struct rt_dm_power_domain *domain);
rt_err_t (*attach_dev)(struct rt_dm_power_domain *domain, struct rt_device *dev);
rt_err_t (*detach_dev)(struct rt_dm_power_domain *domain, struct rt_device *dev);
void *pirv;
};
void rt_dm_power_domain_proxy_default_name(struct rt_dm_power_domain_proxy *proxy);
void rt_dm_power_domain_proxy_ofw_bind(struct rt_dm_power_domain_proxy *proxy,
struct rt_ofw_node *np);
rt_err_t rt_dm_power_domain_register(struct rt_dm_power_domain *domain);
rt_err_t rt_dm_power_domain_unregister(struct rt_dm_power_domain *domain);
rt_err_t rt_dm_power_domain_register_child(struct rt_dm_power_domain *domain,
struct rt_dm_power_domain *child_domain);
rt_err_t rt_dm_power_domain_unregister_child(struct rt_dm_power_domain *domain,
struct rt_dm_power_domain *child_domain);
rt_err_t rt_dm_power_domain_power_on(struct rt_dm_power_domain *domain);
rt_err_t rt_dm_power_domain_power_off(struct rt_dm_power_domain *domain);
struct rt_dm_power_domain *rt_dm_power_domain_get_by_index(struct rt_device *dev, int index);
struct rt_dm_power_domain *rt_dm_power_domain_get_by_name(struct rt_device *dev, const char *name);
rt_err_t rt_dm_power_domain_put(struct rt_dm_power_domain *domain);
rt_err_t rt_dm_power_domain_attach(struct rt_device *dev, rt_bool_t on);
rt_err_t rt_dm_power_domain_detach(struct rt_device *dev, rt_bool_t off);
#endif /* __RT_DM_POWER_DOMAIN_H__ */

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rt-thread/components/drivers/include/drivers/cputime.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-12-23 Bernard first version
*/
#ifndef CPUTIME_H__
#define CPUTIME_H__
#include <stdint.h>
#include "cputimer.h"
struct rt_clock_cputime_ops
{
uint64_t (*cputime_getres)(void);
uint64_t (*cputime_gettime)(void);
int (*cputime_settimeout)(uint64_t tick, void (*timeout)(void *param), void *param);
};
uint64_t clock_cpu_getres(void);
uint64_t clock_cpu_gettime(void);
int clock_cpu_settimeout(uint64_t tick, void (*timeout)(void *param), void *param);
int clock_cpu_issettimeout(void);
uint64_t clock_cpu_microsecond(uint64_t cpu_tick);
uint64_t clock_cpu_millisecond(uint64_t cpu_tick);
int clock_cpu_setops(const struct rt_clock_cputime_ops *ops);
#endif

48
rt-thread/components/drivers/include/drivers/cputimer.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-02-13 zhkag first version
*/
#ifndef CPUTIMER_H__
#define CPUTIMER_H__
#include <rtthread.h>
struct rt_cputimer
{
struct rt_object parent; /**< inherit from rt_object */
rt_list_t row;
void (*timeout_func)(void *parameter);
void *parameter;
rt_uint64_t init_tick;
rt_uint64_t timeout_tick;
struct rt_semaphore sem;
};
typedef struct rt_cputimer *rt_cputimer_t;
rt_err_t rt_cputimer_detach(rt_cputimer_t timer);
#ifdef RT_USING_HEAP
void rt_cputimer_init(rt_cputimer_t timer,
const char *name,
void (*timeout)(void *parameter),
void *parameter,
rt_uint64_t tick,
rt_uint8_t flag);
rt_err_t rt_cputimer_delete(rt_cputimer_t timer);
#endif
rt_err_t rt_cputimer_start(rt_cputimer_t timer);
rt_err_t rt_cputimer_stop(rt_cputimer_t timer);
rt_err_t rt_cputimer_control(rt_cputimer_t timer, int cmd, void *arg);
rt_err_t rt_cputime_sleep(rt_uint64_t tick);
rt_err_t rt_cputime_ndelay(rt_uint64_t ns);
rt_err_t rt_cputime_udelay(rt_uint64_t us);
rt_err_t rt_cputime_mdelay(rt_uint64_t ms);
#endif

23
rt-thread/components/drivers/include/drivers/crypto.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-05-17 tyx the first version
*/
#ifndef __CRYPTO_H__
#define __CRYPTO_H__
#include <rtthread.h>
#include <hwcrypto.h>
#include <hw_symmetric.h>
#include <hw_rng.h>
#include <hw_hash.h>
#include <hw_crc.h>
#include <hw_gcm.h>
#include <hw_bignum.h>
#endif

44
rt-thread/components/drivers/include/drivers/dac.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-19 thread-liu the first version
*/
#ifndef __DAC_H__
#define __DAC_H__
#include <rtthread.h>
struct rt_dac_device;
struct rt_dac_ops
{
rt_err_t (*disabled)(struct rt_dac_device *device, rt_uint32_t channel);
rt_err_t (*enabled)(struct rt_dac_device *device, rt_uint32_t channel);
rt_err_t (*convert)(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value);
rt_uint8_t (*get_resolution)(struct rt_dac_device *device);
};
struct rt_dac_device
{
struct rt_device parent;
const struct rt_dac_ops *ops;
};
typedef struct rt_dac_device *rt_dac_device_t;
typedef enum
{
RT_DAC_CMD_ENABLE = RT_DEVICE_CTRL_BASE(DAC) + 0,
RT_DAC_CMD_DISABLE = RT_DEVICE_CTRL_BASE(DAC) + 1,
RT_DAC_CMD_GET_RESOLUTION = RT_DEVICE_CTRL_BASE(DAC) + 2,
} rt_dac_cmd_t;
rt_err_t rt_hw_dac_register(rt_dac_device_t dac,const char *name, const struct rt_dac_ops *ops, const void *user_data);
rt_err_t rt_dac_write(rt_dac_device_t dev, rt_uint32_t channel, rt_uint32_t value);
rt_err_t rt_dac_enable(rt_dac_device_t dev, rt_uint32_t channel);
rt_err_t rt_dac_disable(rt_dac_device_t dev, rt_uint32_t channel);
#endif /* __dac_H__ */

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rt-thread/components/drivers/include/drivers/gpt.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-05-05 linzhenxing first version
*/
#ifndef __GPT_H
#define __GPT_H
#include <rtthread.h>
#include <stdint.h>
typedef struct
{
uint8_t b[16]; /* GUID 16 bytes*/
} guid_t;
#define MSDOS_MBR_SIGNATURE 0xaa55
#define EFI_PMBR_OSTYPE_EFI 0xEF
#define EFI_PMBR_OSTYPE_EFI_GPT 0xEE
#define GPT_MBR_PROTECTIVE 1
#define GPT_MBR_HYBRID 2
#define GPT_HEADER_SIGNATURE 0x5452415020494645ULL
#define GPT_HEADER_REVISION_V1 0x00010000
#define GPT_PRIMARY_PARTITION_TABLE_LBA 1
typedef guid_t gpt_guid_t __attribute__ ((aligned (4)));
#define EFI_GUID(a, b, c, d...) (gpt_guid_t){ { \
(a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
(b) & 0xff, ((b) >> 8) & 0xff, \
(c) & 0xff, ((c) >> 8) & 0xff, d } }
#define NULL_GUID \
EFI_GUID(0x00000000, 0x0000, 0x0000,\
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
#define PARTITION_SYSTEM_GUID \
EFI_GUID( 0xC12A7328, 0xF81F, 0x11d2, \
0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B)
#define LEGACY_MBR_PARTITION_GUID \
EFI_GUID( 0x024DEE41, 0x33E7, 0x11d3, \
0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F)
#define PARTITION_MSFT_RESERVED_GUID \
EFI_GUID( 0xE3C9E316, 0x0B5C, 0x4DB8, \
0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE)
#define PARTITION_BASIC_DATA_GUID \
EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \
0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7)
#define PARTITION_LINUX_RAID_GUID \
EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \
0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e)
#define PARTITION_LINUX_SWAP_GUID \
EFI_GUID( 0x0657fd6d, 0xa4ab, 0x43c4, \
0x84, 0xe5, 0x09, 0x33, 0xc8, 0x4b, 0x4f, 0x4f)
#define PARTITION_LINUX_LVM_GUID \
EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
#pragma pack(push, 1)
typedef struct _gpt_header
{
uint64_t signature;
uint32_t revision;
uint32_t header_size;
uint32_t header_crc32;
uint32_t reserved1;
uint64_t start_lba; /*GPT head start sector*/
uint64_t alternate_lba; /*GPT head alternate sector*/
uint64_t first_usable_lba;
uint64_t last_usable_lba;
gpt_guid_t disk_guid;
uint64_t partition_entry_lba;
uint32_t num_partition_entries;
uint32_t sizeof_partition_entry;
uint32_t partition_entry_array_crc32;
/* The rest of the logical block is reserved by UEFI and must be zero.
* EFI standard handles this by:
*
* uint8_t reserved2[ BlockSize - 92 ];
*/
} gpt_header;
typedef struct _gpt_entry_attributes
{
uint64_t required_to_function:1;
uint64_t reserved:47;
uint64_t type_guid_specific:16;
} gpt_entry_attributes;
typedef struct _gpt_entry
{
gpt_guid_t partition_type_guid;
gpt_guid_t unique_partition_guid;
uint64_t starting_lba;
uint64_t ending_lba;
gpt_entry_attributes attributes;
uint16_t partition_name[72/sizeof(uint16_t)];
} gpt_entry;
typedef struct _gpt_mbr_record
{
uint8_t boot_indicator; /* unused by EFI, set to 0x80 for bootable */
uint8_t start_head; /* unused by EFI, pt start in CHS */
uint8_t start_sector; /* unused by EFI, pt start in CHS */
uint8_t start_track;
uint8_t os_type; /* EFI and legacy non-EFI OS types */
uint8_t end_head; /* unused by EFI, pt end in CHS */
uint8_t end_sector; /* unused by EFI, pt end in CHS */
uint8_t end_track; /* unused by EFI, pt end in CHS */
uint32_t starting_lba; /* used by EFI - start addr of the on disk pt */
uint32_t size_in_lba; /* used by EFI - size of pt in LBA */
} gpt_mbr_record;
typedef struct _legacy_mbr
{
uint8_t boot_code[440];
uint32_t unique_mbr_signature;
uint16_t unknown;
gpt_mbr_record partition_record[4];
uint16_t signature;
} legacy_mbr;
#pragma pack(pop)
int check_gpt(struct rt_mmcsd_card *card);
int gpt_get_partition_param(struct rt_mmcsd_card *card, struct dfs_partition *part, uint32_t pindex);
void gpt_free(void);
#endif /*__GPT_H*/

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rt-thread/components/drivers/include/drivers/hwtimer.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __HWTIMER_H__
#define __HWTIMER_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Timer Control Command */
typedef enum
{
HWTIMER_CTRL_FREQ_SET = RT_DEVICE_CTRL_BASE(Timer) + 0x01, /* set the count frequency */
HWTIMER_CTRL_STOP = RT_DEVICE_CTRL_BASE(Timer) + 0x02, /* stop timer */
HWTIMER_CTRL_INFO_GET = RT_DEVICE_CTRL_BASE(Timer) + 0x03, /* get a timer feature information */
HWTIMER_CTRL_MODE_SET = RT_DEVICE_CTRL_BASE(Timer) + 0x04 /* Setting the timing mode(oneshot/period) */
} rt_hwtimer_ctrl_t;
/* Timing Mode */
typedef enum
{
HWTIMER_MODE_ONESHOT = 0x01,
HWTIMER_MODE_PERIOD
} rt_hwtimer_mode_t;
/* Time Value */
typedef struct rt_hwtimerval
{
rt_int32_t sec; /* second */
rt_int32_t usec; /* microsecond */
} rt_hwtimerval_t;
#define HWTIMER_CNTMODE_UP 0x01 /* increment count mode */
#define HWTIMER_CNTMODE_DW 0x02 /* decreasing count mode */
struct rt_hwtimer_device;
struct rt_hwtimer_ops
{
void (*init)(struct rt_hwtimer_device *timer, rt_uint32_t state);
rt_err_t (*start)(struct rt_hwtimer_device *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode);
void (*stop)(struct rt_hwtimer_device *timer);
rt_uint32_t (*count_get)(struct rt_hwtimer_device *timer);
rt_err_t (*control)(struct rt_hwtimer_device *timer, rt_uint32_t cmd, void *args);
};
/* Timer Feature Information */
struct rt_hwtimer_info
{
rt_int32_t maxfreq; /* the maximum count frequency timer support */
rt_int32_t minfreq; /* the minimum count frequency timer support */
rt_uint32_t maxcnt; /* counter maximum value */
rt_uint8_t cntmode; /* count mode (inc/dec) */
};
typedef struct rt_hwtimer_device
{
struct rt_device parent;
const struct rt_hwtimer_ops *ops;
const struct rt_hwtimer_info *info;
rt_int32_t freq; /* counting frequency set by the user */
rt_int32_t overflow; /* timer overflows */
float period_sec;
rt_int32_t cycles; /* how many times will generate a timeout event after overflow */
rt_int32_t reload; /* reload cycles(using in period mode) */
rt_hwtimer_mode_t mode; /* timing mode(oneshot/period) */
} rt_hwtimer_t;
rt_err_t rt_device_hwtimer_register(rt_hwtimer_t *timer, const char *name, void *user_data);
void rt_device_hwtimer_isr(rt_hwtimer_t *timer);
#ifdef RT_USING_DM
extern void (*rt_device_hwtimer_us_delay)(rt_uint32_t us);
#endif
#ifdef __cplusplus
}
#endif
#endif

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rt-thread/components/drivers/include/drivers/i2c-bit-ops.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-04-25 weety first version
*/
#ifndef __I2C_BIT_OPS_H__
#define __I2C_BIT_OPS_H__
#ifdef __cplusplus
extern "C" {
#endif
struct rt_i2c_bit_ops
{
void *data; /* private data for lowlevel routines */
void (*set_sda)(void *data, rt_int32_t state);
void (*set_scl)(void *data, rt_int32_t state);
rt_int32_t (*get_sda)(void *data);
rt_int32_t (*get_scl)(void *data);
void (*udelay)(rt_uint32_t us);
rt_uint32_t delay_us; /* scl and sda line delay */
rt_uint32_t timeout; /* in tick */
void (*pin_init)(void);
rt_bool_t i2c_pin_init_flag;
};
rt_err_t rt_i2c_bit_add_bus(struct rt_i2c_bus_device *bus,
const char *bus_name);
#ifdef __cplusplus
}
#endif
#endif

136
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-04-25 weety first version
* 2021-04-20 RiceChen added support for bus control api
*/
#ifndef __I2C_H__
#define __I2C_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#define RT_I2C_WR 0x0000
#define RT_I2C_RD (1u << 0)
#define RT_I2C_ADDR_10BIT (1u << 2) /* this is a ten bit chip address */
#define RT_I2C_NO_START (1u << 4)
#define RT_I2C_IGNORE_NACK (1u << 5)
#define RT_I2C_NO_READ_ACK (1u << 6) /* when I2C reading, we do not ACK */
#define RT_I2C_NO_STOP (1u << 7)
struct rt_i2c_msg
{
rt_uint16_t addr;
rt_uint16_t flags;
rt_uint16_t len;
rt_uint8_t *buf;
};
struct rt_i2c_bus_device;
struct rt_i2c_bus_device_ops
{
rt_ssize_t (*master_xfer)(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num);
rt_ssize_t (*slave_xfer)(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num);
rt_err_t (*i2c_bus_control)(struct rt_i2c_bus_device *bus,
int cmd,
void *args);
};
/*for i2c bus driver*/
struct rt_i2c_bus_device
{
struct rt_device parent;
const struct rt_i2c_bus_device_ops *ops;
rt_uint16_t flags;
struct rt_mutex lock;
rt_uint32_t timeout;
rt_uint32_t retries;
void *priv;
};
struct rt_i2c_client
{
#ifdef RT_USING_DM
struct rt_device parent;
const char *name;
const struct rt_i2c_device_id *id;
const struct rt_ofw_node_id *ofw_id;
#endif
struct rt_i2c_bus_device *bus;
rt_uint16_t client_addr;
};
#ifdef RT_USING_DM
struct rt_i2c_device_id
{
char name[20];
void *data;
};
struct rt_i2c_driver
{
struct rt_driver parent;
const struct rt_i2c_device_id *ids;
const struct rt_ofw_node_id *ofw_ids;
rt_err_t (*probe)(struct rt_i2c_client *client);
rt_err_t (*remove)(struct rt_i2c_client *client);
rt_err_t (*shutdown)(struct rt_i2c_client *client);
};
rt_err_t rt_i2c_driver_register(struct rt_i2c_driver *driver);
rt_err_t rt_i2c_device_register(struct rt_i2c_client *client);
#define RT_I2C_DRIVER_EXPORT(driver) RT_DRIVER_EXPORT(driver, i2c, BUILIN)
#endif /* RT_USING_DM */
rt_err_t rt_i2c_bus_device_register(struct rt_i2c_bus_device *bus,
const char *bus_name);
struct rt_i2c_bus_device *rt_i2c_bus_device_find(const char *bus_name);
rt_ssize_t rt_i2c_transfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num);
rt_err_t rt_i2c_control(struct rt_i2c_bus_device *bus,
int cmd,
void *args);
rt_ssize_t rt_i2c_master_send(struct rt_i2c_bus_device *bus,
rt_uint16_t addr,
rt_uint16_t flags,
const rt_uint8_t *buf,
rt_uint32_t count);
rt_ssize_t rt_i2c_master_recv(struct rt_i2c_bus_device *bus,
rt_uint16_t addr,
rt_uint16_t flags,
rt_uint8_t *buf,
rt_uint32_t count);
rt_inline rt_err_t rt_i2c_bus_lock(struct rt_i2c_bus_device *bus, rt_tick_t timeout)
{
return rt_mutex_take(&bus->lock, timeout);
}
rt_inline rt_err_t rt_i2c_bus_unlock(struct rt_i2c_bus_device *bus)
{
return rt_mutex_release(&bus->lock);
}
#ifdef __cplusplus
}
#endif
#endif

44
rt-thread/components/drivers/include/drivers/i2c_dev.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-04-25 weety first version
* 2021-04-20 RiceChen added bus clock command
*/
#ifndef __I2C_DEV_H__
#define __I2C_DEV_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#define RT_I2C_DEV_CTRL_10BIT (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x01)
#define RT_I2C_DEV_CTRL_ADDR (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x02)
#define RT_I2C_DEV_CTRL_TIMEOUT (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x03)
#define RT_I2C_DEV_CTRL_RW (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x04)
#define RT_I2C_DEV_CTRL_CLK (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x05)
#define RT_I2C_DEV_CTRL_UNLOCK (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x06)
#define RT_I2C_DEV_CTRL_GET_STATE (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x07)
#define RT_I2C_DEV_CTRL_GET_MODE (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x08)
#define RT_I2C_DEV_CTRL_GET_ERROR (RT_DEVICE_CTRL_BASE(I2CBUS) + 0x09)
struct rt_i2c_priv_data
{
struct rt_i2c_msg *msgs;
rt_size_t number;
};
rt_err_t rt_i2c_bus_device_device_init(struct rt_i2c_bus_device *bus,
const char *name);
#ifdef __cplusplus
}
#endif
#endif

51
rt-thread/components/drivers/include/drivers/i2c_dm.h Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-11-26 GuEe-GUI first version
*/
#ifndef __I2C_DM_H__
#define __I2C_DM_H__
#include <rthw.h>
#include <rtthread.h>
#include <drivers/core/bus.h>
/* I2C Frequency Modes */
#define I2C_MAX_STANDARD_MODE_FREQ 100000
#define I2C_MAX_FAST_MODE_FREQ 400000
#define I2C_MAX_FAST_MODE_PLUS_FREQ 1000000
#define I2C_MAX_TURBO_MODE_FREQ 1400000
#define I2C_MAX_HIGH_SPEED_MODE_FREQ 3400000
#define I2C_MAX_ULTRA_FAST_MODE_FREQ 5000000
struct i2c_timings
{
rt_uint32_t bus_freq_hz; /* the bus frequency in Hz */
rt_uint32_t scl_rise_ns; /* time SCL signal takes to rise in ns; t(r) in the I2C specification */
rt_uint32_t scl_fall_ns; /* time SCL signal takes to fall in ns; t(f) in the I2C specification */
rt_uint32_t scl_int_delay_ns; /* time IP core additionally needs to setup SCL in ns */
rt_uint32_t sda_fall_ns; /* time SDA signal takes to fall in ns; t(f) in the I2C specification */
rt_uint32_t sda_hold_ns; /* time IP core additionally needs to hold SDA in ns */
rt_uint32_t digital_filter_width_ns; /* width in ns of spikes on i2c lines that the IP core digital filter can filter out */
rt_uint32_t analog_filter_cutoff_freq_hz; /* threshold frequency for the low pass IP core analog filter */
};
#ifdef RT_USING_OFW
rt_err_t i2c_timings_ofw_parse(struct rt_ofw_node *dev_np, struct i2c_timings *timings,
rt_bool_t use_defaults);
#else
rt_inline rt_err_t i2c_timings_ofw_parse(struct rt_ofw_node *dev_np, struct i2c_timings *timings,
rt_bool_t use_defaults)
{
return RT_EOK;
}
#endif /* RT_USING_OFW */
void i2c_bus_scan_clients(struct rt_i2c_bus_device *bus);
#endif /* __I2C_DM_H__ */

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rt-thread/components/drivers/include/drivers/lcd.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-03-05 bernard first version.
*/
#ifndef RT_LCD_H__
#define RT_LCD_H__
/* ioctls
0x46 is 'F' */
#define FBIOGET_VSCREENINFO 0x4600
#define FBIOPUT_VSCREENINFO 0x4601
#define FBIOGET_FSCREENINFO 0x4602
#define FBIOGET_PIXELINFO 0x4603
#define FBIOGETCMAP 0x4604
#define FBIOPUTCMAP 0x4605
#define FBIOPAN_DISPLAY 0x4606
#define FBIO_CURSOR 0x4608
/* #define FBIOGET_MONITORSPEC 0x460C */
/* #define FBIOPUT_MONITORSPEC 0x460D */
/* #define FBIOSWITCH_MONIBIT 0x460E */
#define FBIOGET_CON2FBMAP 0x460F
#define FBIOPUT_CON2FBMAP 0x4610
#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */
#define FBIOGET_VBLANK 0x4612
#define FBIO_ALLOC 0x4613
#define FBIO_FREE 0x4614
#define FBIOGET_GLYPH 0x4615
#define FBIOGET_HWCINFO 0x4616
#define FBIOPUT_MODEINFO 0x4617
#define FBIOGET_DISPINFO 0x4618
#define FBIO_WAITFORVSYNC 0x4620
struct fb_bitfield
{
uint32_t offset; /* beginning of bitfield */
uint32_t length; /* length of bitfield */
uint32_t msb_right; /* != 0 : Most significant bit is */
/* right */
};
struct fb_var_screeninfo
{
uint32_t xres; /* visible resolution */
uint32_t yres;
uint32_t xres_virtual; /* virtual resolution */
uint32_t yres_virtual;
uint32_t xoffset; /* offset from virtual to visible */
uint32_t yoffset; /* resolution */
uint32_t bits_per_pixel; /* guess what */
uint32_t grayscale; /* 0 = color, 1 = grayscale, */
/* >1 = FOURCC */
struct fb_bitfield red; /* bitfield in fb mem if true color, */
struct fb_bitfield green; /* else only length is significant */
struct fb_bitfield blue;
struct fb_bitfield transp; /* transparency */
uint32_t nonstd; /* != 0 Non standard pixel format */
uint32_t activate; /* see FB_ACTIVATE_* */
uint32_t height; /* height of picture in mm */
uint32_t width; /* width of picture in mm */
uint32_t accel_flags; /* (OBSOLETE) see fb_info.flags */
/* Timing: All values in pixclocks, except pixclock (of course) */
uint32_t pixclock; /* pixel clock in ps (pico seconds) */
uint32_t left_margin; /* time from sync to picture */
uint32_t right_margin; /* time from picture to sync */
uint32_t upper_margin; /* time from sync to picture */
uint32_t lower_margin;
uint32_t hsync_len; /* length of horizontal sync */
uint32_t vsync_len; /* length of vertical sync */
uint32_t sync; /* see FB_SYNC_* */
uint32_t vmode; /* see FB_VMODE_* */
uint32_t rotate; /* angle we rotate counter clockwise */
uint32_t colorspace; /* colorspace for FOURCC-based modes */
uint32_t reserved[4]; /* Reserved for future compatibility */
};
struct fb_fix_screeninfo
{
char id[16]; /* identification string eg "TT Builtin" */
unsigned long smem_start; /* Start of frame buffer mem */
/* (physical address) */
uint32_t smem_len; /* Length of frame buffer mem */
uint32_t type; /* see FB_TYPE_* */
uint32_t type_aux; /* Interleave for interleaved Planes */
uint32_t visual; /* see FB_VISUAL_* */
uint16_t xpanstep; /* zero if no hardware panning */
uint16_t ypanstep; /* zero if no hardware panning */
uint16_t ywrapstep; /* zero if no hardware ywrap */
uint32_t line_length; /* length of a line in bytes */
unsigned long mmio_start; /* Start of Memory Mapped I/O */
/* (physical address) */
uint32_t mmio_len; /* Length of Memory Mapped I/O */
uint32_t accel; /* Indicate to driver which */
/* specific chip/card we have */
uint16_t capabilities; /* see FB_CAP_* */
uint16_t reserved[2]; /* Reserved for future compatibility */
};
#endif

38
rt-thread/components/drivers/include/drivers/lptimer.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-11 zhangsz the first version
*/
#ifndef __LPTIMER_H__
#define __LPTIMER_H__
#include <rtthread.h>
struct rt_lptimer
{
struct rt_timer timer;
rt_list_t list;
};
typedef struct rt_lptimer *rt_lptimer_t;
void rt_lptimer_init(rt_lptimer_t timer,
const char *name,
void (*timeout)(void *parameter),
void *parameter,
rt_tick_t time,
rt_uint8_t flag);
rt_err_t rt_lptimer_detach(rt_lptimer_t timer);
rt_err_t rt_lptimer_start(rt_lptimer_t timer);
rt_err_t rt_lptimer_stop(rt_lptimer_t timer);
rt_err_t rt_lptimer_control(rt_lptimer_t timer, int cmd, void *arg);
rt_tick_t rt_lptimer_next_timeout_tick(void);
#endif

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rt-thread/components/drivers/include/drivers/misc.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-02-25 GuEe-GUI the first version
*/
#ifndef __MISC_H__
#define __MISC_H__
#include <rtdef.h>
#ifdef ARCH_CPU_64BIT
#define RT_BITS_PER_LONG 64
#else
#define RT_BITS_PER_LONG 32
#endif
#define RT_BITS_PER_LONG_LONG 64
#define RT_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define RT_DIV_ROUND_CLOSEST(x, divisor) \
({ \
typeof(x) __x = x; \
typeof(divisor) __d = divisor; \
(((typeof(x))-1) > 0 || \
((typeof(divisor))-1) > 0 || \
(((__x) > 0) == ((__d) > 0))) ? \
(((__x) + ((__d) / 2)) / (__d)) : \
(((__x) - ((__d) / 2)) / (__d)); \
})
#define RT_BIT(n) (1UL << (n))
#define RT_BIT_ULL(n) (1ULL << (n))
#define RT_BIT_MASK(nr) (1UL << ((nr) % RT_BITS_PER_LONG))
#define RT_BIT_WORD(nr) ((nr) / RT_BITS_PER_LONG)
#define RT_BITS_PER_BYTE 8
#define RT_BITS_PER_TYPE(type) (sizeof(type) * RT_BITS_PER_BYTE)
#define RT_BITS_TO_BYTES(nr) RT_DIV_ROUND_UP(nr, RT_BITS_PER_TYPE(char))
#define RT_BITS_TO_LONGS(nr) RT_DIV_ROUND_UP(nr, RT_BITS_PER_TYPE(long))
#define RT_GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (RT_BITS_PER_LONG - 1 - (h))))
#define RT_GENMASK_ULL(h, l) (((~0ULL) << (l)) & (~0ULL >> (RT_BITS_PER_LONG_LONG - 1 - (h))))
#define RT_ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0]))
#define rt_min(x, y) \
({ \
typeof(x) _x = (x); \
typeof(y) _y = (y); \
(void) (&_x == &_y); \
_x < _y ? _x : _y; \
})
#define rt_max(x, y) \
({ \
typeof(x) _x = (x); \
typeof(y) _y = (y); \
(void) (&_x == &_y); \
_x > _y ? _x : _y; \
})
#define rt_min_t(type, x, y) \
({ \
type _x = (x); \
type _y = (y); \
_x < _y ? _x: _y; \
})
#define rt_clamp(val, lo, hi) rt_min((typeof(val))rt_max(val, lo), hi)
#define rt_do_div(n, base) \
({ \
rt_uint32_t _base = (base), _rem; \
_rem = ((rt_uint64_t)(n)) % _base; \
(n) = ((rt_uint64_t)(n)) / _base; \
if (_rem > _base / 2) \
++(n); \
_rem; \
})
#endif /* __MISC_H__ */

195
rt-thread/components/drivers/include/drivers/mmc.h Normal file
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/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2015-06-15 hichard first version
* 2024-05-25 HPMicro add strobe support
*/
#ifndef __MMC_H__
#define __MMC_H__
#include <rtthread.h>
#include <drivers/mmcsd_host.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* EXT_CSD fields
*/
#define EXT_CSD_FLUSH_CACHE 32 /* W */
#define EXT_CSD_CACHE_CTRL 33 /* R/W */
#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
#define EXT_CSD_HPI_MGMT 161 /* R/W */
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
#define EXT_CSD_BKOPS_EN 163 /* R/W */
#define EXT_CSD_BKOPS_START 164 /* W */
#define EXT_CSD_SANITIZE_START 165 /* W */
#define EXT_CSD_WR_REL_PARAM 166 /* RO */
#define EXT_CSD_RPMB_MULT 168 /* RO */
#define EXT_CSD_BOOT_WP 173 /* R/W */
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
#define EXT_CSD_PART_CONFIG 179 /* R/W */
#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
#define EXT_CSD_HS_TIMING 185 /* R/W */
#define EXT_CSD_POWER_CLASS 187 /* R/W */
#define EXT_CSD_REV 192 /* RO */
#define EXT_CSD_STRUCTURE 194 /* RO */
#define EXT_CSD_CARD_TYPE 196 /* RO */
#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
#define EXT_CSD_PWR_CL_52_195 200 /* RO */
#define EXT_CSD_PWR_CL_26_195 201 /* RO */
#define EXT_CSD_PWR_CL_52_360 202 /* RO */
#define EXT_CSD_PWR_CL_26_360 203 /* RO */
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
#define EXT_CSD_BOOT_MULT 226 /* RO */
#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
#define EXT_CSD_TRIM_MULT 232 /* RO */
#define EXT_CSD_PWR_CL_200_195 236 /* RO */
#define EXT_CSD_PWR_CL_200_360 237 /* RO */
#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
#define EXT_CSD_BKOPS_STATUS 246 /* RO */
#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
#define EXT_CSD_HPI_FEATURES 503 /* RO */
/*
* EXT_CSD field definitions
*/
#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3)
#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
#define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
#define EXT_CSD_CMD_SET_NORMAL (1<<0)
#define EXT_CSD_CMD_SET_SECURE (1<<1)
#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \
EXT_CSD_CARD_TYPE_HS_52)
#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
/* DDR mode @1.8V or 3V I/O */
#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
/* DDR mode @1.2V I/O */
#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
| EXT_CSD_CARD_TYPE_DDR_1_2V)
#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
/* SDR mode @1.2V I/O */
#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
EXT_CSD_CARD_TYPE_HS200_1_2V)
#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
EXT_CSD_CARD_TYPE_HS400_1_2V)
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
#define EXT_CSD_DDR_BUS_WIDTH_8_EH_DS 0x86/* Card is in 8 bit DDR mode with Enhanced Data Strobe */
#define EXT_CSD_TIMING_BC 0 /* Backwards compatibility */
#define EXT_CSD_TIMING_HS 1 /* High speed */
#define EXT_CSD_TIMING_HS200 2 /* HS200 */
#define EXT_CSD_TIMING_HS400 3 /* HS400 */
#define EXT_CSD_SEC_ER_EN BIT(0)
#define EXT_CSD_SEC_BD_BLK_EN BIT(2)
#define EXT_CSD_SEC_GB_CL_EN BIT(4)
#define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
#define EXT_CSD_RST_N_EN_MASK 0x3
#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
#define EXT_CSD_NO_POWER_NOTIFICATION 0
#define EXT_CSD_POWER_ON 1
#define EXT_CSD_POWER_OFF_SHORT 2
#define EXT_CSD_POWER_OFF_LONG 3
#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
#define EXT_CSD_PWR_CL_8BIT_SHIFT 4
#define EXT_CSD_PWR_CL_4BIT_SHIFT 0
#define EXT_CSD_PACKED_EVENT_EN BIT(3)
/*
* EXCEPTION_EVENT_STATUS field
*/
#define EXT_CSD_URGENT_BKOPS BIT(0)
#define EXT_CSD_DYNCAP_NEEDED BIT(1)
#define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2)
#define EXT_CSD_PACKED_FAILURE BIT(3)
#define EXT_CSD_PACKED_GENERIC_ERROR BIT(0)
#define EXT_CSD_PACKED_INDEXED_ERROR BIT(1)
/*
* BKOPS status level
*/
#define EXT_CSD_BKOPS_LEVEL_2 0x2
/*
* MMC_SWITCH access modes
*/
#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
/*
* extern function
*/
rt_err_t mmc_send_op_cond(struct rt_mmcsd_host *host, rt_uint32_t ocr, rt_uint32_t *rocr);
rt_int32_t init_mmc(struct rt_mmcsd_host *host, rt_uint32_t ocr);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-07-25 weety first version
* 2024-05-24 HPMicro add HS400 support
* 2024-05-26 HPMicro add UHS-I support for SD card
*/
#ifndef __MMCSD_CARD_H__
#define __MMCSD_CARD_H__
#include <drivers/mmcsd_host.h>
#ifdef __cplusplus
extern "C" {
#endif
#define SD_SCR_BUS_WIDTH_1 (1 << 0)
#define SD_SCR_BUS_WIDTH_4 (1 << 2)
struct rt_mmcsd_cid {
rt_uint8_t mid; /* ManufacturerID */
rt_uint8_t prv; /* Product Revision */
rt_uint16_t oid; /* OEM/Application ID */
rt_uint32_t psn; /* Product Serial Number */
rt_uint8_t pnm[5]; /* Product Name */
rt_uint8_t reserved1;/* reserved */
rt_uint16_t mdt; /* Manufacturing Date */
rt_uint8_t crc; /* CID CRC */
rt_uint8_t reserved2;/* not used, always 1 */
};
struct rt_mmcsd_csd {
rt_uint8_t csd_structure; /* CSD register version */
rt_uint8_t taac;
rt_uint8_t nsac;
rt_uint8_t tran_speed; /* max data transfer rate */
rt_uint16_t card_cmd_class; /* card command classes */
rt_uint8_t rd_blk_len; /* max read data block length */
rt_uint8_t rd_blk_part;
rt_uint8_t wr_blk_misalign;
rt_uint8_t rd_blk_misalign;
rt_uint8_t dsr_imp; /* DSR implemented */
rt_uint8_t c_size_mult; /* CSD 1.0 , device size multiplier */
rt_uint32_t c_size; /* device size */
rt_uint8_t r2w_factor;
rt_uint8_t wr_blk_len; /* max wtire data block length */
rt_uint8_t wr_blk_partial;
rt_uint8_t csd_crc;
};
struct rt_sd_scr {
rt_uint8_t sd_version;
rt_uint8_t sd_bus_widths;
};
struct rt_sdio_cccr {
rt_uint8_t sdio_version;
rt_uint8_t sd_version;
rt_uint8_t direct_cmd:1, /* Card Supports Direct Commands during data transfer
only SD mode, not used for SPI mode */
multi_block:1, /* Card Supports Multi-Block */
read_wait:1, /* Card Supports Read Wait
only SD mode, not used for SPI mode */
suspend_resume:1, /* Card supports Suspend/Resume
only SD mode, not used for SPI mode */
s4mi:1, /* generate interrupts during a 4-bit
multi-block data transfer */
e4mi:1, /* Enable the multi-block IRQ during
4-bit transfer for the SDIO card */
low_speed:1, /* Card is a Low-Speed card */
low_speed_4:1; /* 4-bit support for Low-Speed cards */
rt_uint8_t bus_width:1, /* Support SDIO bus width, 1:4bit, 0:1bit */
cd_disable:1, /* Connect[0]/Disconnect[1] the 10K-90K ohm pull-up
resistor on CD/DAT[3] (pin 1) of the card */
power_ctrl:1, /* Support Master Power Control */
high_speed:1; /* Support High-Speed */
};
/*
* SD Status
*/
union rt_sd_status {
rt_uint32_t status_words[16];
struct {
rt_uint32_t reserved[12];
rt_uint64_t : 8;
rt_uint64_t uhs_au_size: 4;
rt_uint64_t uhs_speed_grade: 4;
rt_uint64_t erase_offset: 2;
rt_uint64_t erase_timeout: 6;
rt_uint64_t erase_size: 16;
rt_uint64_t : 4;
rt_uint64_t au_size: 4;
rt_uint64_t performance_move: 8;
rt_uint64_t speed_class: 8;
rt_uint32_t size_of_protected_area;
rt_uint32_t sd_card_type: 16;
rt_uint32_t : 6;
rt_uint32_t : 7;
rt_uint32_t secured_mode: 1;
rt_uint32_t data_bus_width: 2;
};
};
/*
* SD Speed Class
*/
#define SD_SPEED_CLASS_0 0
#define SD_SPEED_CLASS_2 1
#define SD_SPEED_CLASS_4 2
#define SD_SPEED_CLASS_6 3
#define SD_SPEED_CLASS_10 4
/*
* UHS Speed Grade
*/
#define UHS_SPEED_GRADE_0 0
#define UHS_SPEED_GRADE_1 1
#define UHS_SPEED_GRADE_3 3
struct rt_sdio_cis {
rt_uint16_t manufacturer;
rt_uint16_t product;
rt_uint16_t func0_blk_size;
rt_uint32_t max_tran_speed;
};
/*
* SDIO function CIS tuple (unknown to the core)
*/
struct rt_sdio_function_tuple {
struct rt_sdio_function_tuple *next;
rt_uint8_t code;
rt_uint8_t size;
rt_uint8_t *data;
};
struct rt_sdio_function;
typedef void (rt_sdio_irq_handler_t)(struct rt_sdio_function *);
/*
* SDIO function devices
*/
struct rt_sdio_function {
struct rt_mmcsd_card *card; /* the card this device belongs to */
rt_sdio_irq_handler_t *irq_handler; /* IRQ callback */
rt_uint8_t num; /* function number */
rt_uint8_t func_code; /* Standard SDIO Function interface code */
rt_uint16_t manufacturer; /* manufacturer id */
rt_uint16_t product; /* product id */
rt_uint32_t max_blk_size; /* maximum block size */
rt_uint32_t cur_blk_size; /* current block size */
rt_uint32_t enable_timeout_val; /* max enable timeout in msec */
struct rt_sdio_function_tuple *tuples;
void *priv;
};
#define SDIO_MAX_FUNCTIONS 7
struct rt_mmc_ext_csd
{
rt_uint32_t cache_size;
rt_uint32_t enhanced_data_strobe;
};
struct rt_mmcsd_card {
struct rt_mmcsd_host *host;
rt_uint32_t rca; /* card addr */
rt_uint32_t resp_cid[4]; /* card CID register */
rt_uint32_t resp_csd[4]; /* card CSD register */
rt_uint32_t resp_scr[2]; /* card SCR register */
rt_uint16_t tacc_clks; /* data access time by ns */
rt_uint32_t tacc_ns; /* data access time by clk cycles */
rt_uint32_t max_data_rate; /* max data transfer rate */
rt_uint32_t card_capacity; /* card capacity, unit:KB */
rt_uint32_t card_blksize; /* card block size */
rt_uint32_t card_sec_cnt; /* card sector count*/
rt_uint32_t erase_size; /* erase size in sectors */
rt_uint16_t card_type;
#define CARD_TYPE_MMC 0 /* MMC card */
#define CARD_TYPE_SD 1 /* SD card */
#define CARD_TYPE_SDIO 2 /* SDIO card */
#define CARD_TYPE_SDIO_COMBO 3 /* SD combo (IO+mem) card */
rt_uint16_t flags;
#define CARD_FLAG_HIGHSPEED (1 << 0) /* SDIO bus speed 50MHz */
#define CARD_FLAG_SDHC (1 << 1) /* SDHC card */
#define CARD_FLAG_SDXC (1 << 2) /* SDXC card */
#define CARD_FLAG_HIGHSPEED_DDR (1 << 3) /* HIGH SPEED DDR */
#define CARD_FLAG_HS200 (1 << 4) /* BUS SPEED 200MHz */
#define CARD_FLAG_HS400 (1 << 5) /* BUS SPEED 400MHz */
#define CARD_FLAG_SDR50 (1 << 6) /* BUS SPEED 100MHz */
#define CARD_FLAG_SDR104 (1 << 7) /* BUS SPEED 200MHz */
#define CARD_FLAG_DDR50 (1 << 8) /* DDR50, works on 1.8V only */
struct rt_sd_scr scr;
struct rt_mmcsd_csd csd;
rt_uint32_t hs_max_data_rate; /* max data transfer rate in high speed mode */
rt_uint8_t sdio_function_num; /* total number of SDIO functions */
struct rt_sdio_cccr cccr; /* common card info */
struct rt_sdio_cis cis; /* common tuple info */
struct rt_sdio_function *sdio_function[SDIO_MAX_FUNCTIONS + 1]; /* SDIO functions (devices) */
rt_list_t blk_devices; /* for block device list */
struct rt_mmc_ext_csd ext_csd;
};
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-07-25 weety first version
* 2024-05-26 HPMicro add VOLTAGE_SWITCH definition
*/
#ifndef __CMD_H__
#define __CMD_H__
#ifdef __cplusplus
extern "C" {
#endif
/* class 1 */
#define GO_IDLE_STATE 0 /* bc */
#define SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
#define ALL_SEND_CID 2 /* bcr R2 */
#define SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
#define SET_DSR 4 /* bc [31:16] RCA */
#define SWITCH 6 /* ac [31:0] See below R1b */
#define SELECT_CARD 7 /* ac [31:16] RCA R1 */
#define SEND_EXT_CSD 8 /* adtc R1 */
#define SEND_CSD 9 /* ac [31:16] RCA R2 */
#define SEND_CID 10 /* ac [31:16] RCA R2 */
#define VOLTAGE_SWITCH 11 /* ac [31:0] R1 */
#define STOP_TRANSMISSION 12 /* ac R1b */
#define SEND_STATUS 13 /* ac [31:16] RCA R1 */
#define GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
#define SPI_READ_OCR 58 /* spi spi_R3 */
#define SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
/* class 2 */
#define SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
#define READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
#define READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
#define SEND_TUNING_BLOCK 19 /* adtc R1 */
#define SEND_TUNING_BLOCK_HS200 21 /* adtc R1*/
/* class 3 */
#define WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
/* class 4 */
#define SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
#define WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
#define WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
#define PROGRAM_CID 26 /* adtc R1 */
#define PROGRAM_CSD 27 /* adtc R1 */
/* class 6 */
#define SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
#define CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
#define SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
/* class 5 */
#define ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
#define ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
#define ERASE 38 /* ac R1b */
/* class 9 */
#define FAST_IO 39 /* ac <Complex> R4 */
#define GO_IRQ_STATE 40 /* bcr R5 */
/* class 7 */
#define LOCK_UNLOCK 42 /* adtc R1b */
/* class 8 */
#define APP_CMD 55 /* ac [31:16] RCA R1 */
#define GEN_CMD 56 /* adtc [0] RD/WR R1 */
/* SD commands type argument response */
/* class 0 */
/* This is basically the same command as for MMC with some quirks. */
#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */
/* class 10 */
#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
/* Application commands */
#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */
#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
#define SD_APP_SEND_SCR 51 /* adtc R1 */
#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */
#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */
#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00 */
/* SDIO commands type argument response */
#define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */
#define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */
#define SD_IO_RW_EXTENDED 53 /* adtc [31:0] See below R5 */
/* CMD52 arguments */
#define SDIO_ARG_CMD52_READ (0<<31)
#define SDIO_ARG_CMD52_WRITE (1u<<31)
#define SDIO_ARG_CMD52_FUNC_SHIFT 28
#define SDIO_ARG_CMD52_FUNC_MASK 0x7
#define SDIO_ARG_CMD52_RAW_FLAG (1u<<27)
#define SDIO_ARG_CMD52_REG_SHIFT 9
#define SDIO_ARG_CMD52_REG_MASK 0x1ffff
#define SDIO_ARG_CMD52_DATA_SHIFT 0
#define SDIO_ARG_CMD52_DATA_MASK 0xff
#define SDIO_R5_DATA(resp) ((resp)[0] & 0xff)
/* CMD53 arguments */
#define SDIO_ARG_CMD53_READ (0<<31)
#define SDIO_ARG_CMD53_WRITE (1u<<31)
#define SDIO_ARG_CMD53_FUNC_SHIFT 28
#define SDIO_ARG_CMD53_FUNC_MASK 0x7
#define SDIO_ARG_CMD53_BLOCK_MODE (1u<<27)
#define SDIO_ARG_CMD53_INCREMENT (1u<<26)
#define SDIO_ARG_CMD53_REG_SHIFT 9
#define SDIO_ARG_CMD53_REG_MASK 0x1ffff
#define SDIO_ARG_CMD53_LENGTH_SHIFT 0
#define SDIO_ARG_CMD53_LENGTH_MASK 0x1ff
#define SDIO_ARG_CMD53_LENGTH_MAX 511
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-07-25 weety first version
*/
#ifndef __CORE_H__
#define __CORE_H__
#include <rtthread.h>
#include <drivers/mmcsd_host.h>
#include <drivers/mmcsd_card.h>
#include <drivers/mmcsd_cmd.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef RT_MMCSD_DBG
#define mmcsd_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__)
#else
#define mmcsd_dbg(fmt, ...)
#endif
struct rt_mmcsd_data
{
rt_uint32_t blksize;
rt_uint32_t blks;
rt_uint32_t *buf;
rt_int32_t err;
rt_uint32_t flags;
#define DATA_DIR_WRITE (1 << 0)
#define DATA_DIR_READ (1 << 1)
#define DATA_STREAM (1 << 2)
unsigned int bytes_xfered;
struct rt_mmcsd_cmd *stop; /* stop command */
struct rt_mmcsd_req *mrq; /* associated request */
rt_uint32_t timeout_ns;
rt_uint32_t timeout_clks;
void *sg; /* scatter list */
rt_uint16_t sg_len; /* size of scatter list */
rt_int16_t sg_count; /* mapped sg entries */
rt_ubase_t host_cookie; /* host driver private data */
};
struct rt_mmcsd_cmd
{
rt_uint32_t cmd_code;
rt_uint32_t arg;
rt_uint32_t resp[4];
rt_uint32_t flags;
/*rsponse types
*bits:0~3
*/
#define RESP_MASK (0xF)
#define RESP_NONE (0)
#define RESP_R1 (1 << 0)
#define RESP_R1B (2 << 0)
#define RESP_R2 (3 << 0)
#define RESP_R3 (4 << 0)
#define RESP_R4 (5 << 0)
#define RESP_R6 (6 << 0)
#define RESP_R7 (7 << 0)
#define RESP_R5 (8 << 0) /*SDIO command response type*/
/*command types
*bits:4~5
*/
#define CMD_MASK (3 << 4) /* command type */
#define CMD_AC (0 << 4)
#define CMD_ADTC (1 << 4)
#define CMD_BC (2 << 4)
#define CMD_BCR (3 << 4)
#define resp_type(cmd) ((cmd)->flags & RESP_MASK)
/*spi rsponse types
*bits:6~8
*/
#define RESP_SPI_MASK (0x7 << 6)
#define RESP_SPI_R1 (1 << 6)
#define RESP_SPI_R1B (2 << 6)
#define RESP_SPI_R2 (3 << 6)
#define RESP_SPI_R3 (4 << 6)
#define RESP_SPI_R4 (5 << 6)
#define RESP_SPI_R5 (6 << 6)
#define RESP_SPI_R7 (7 << 6)
#define spi_resp_type(cmd) ((cmd)->flags & RESP_SPI_MASK)
/*
* These are the command types.
*/
#define cmd_type(cmd) ((cmd)->flags & CMD_MASK)
rt_int32_t retries; /* max number of retries */
rt_int32_t err;
unsigned int busy_timeout; /* busy detect timeout in ms */
struct rt_mmcsd_data *data;
struct rt_mmcsd_req *mrq; /* associated request */
};
struct rt_mmcsd_req
{
struct rt_mmcsd_data *data;
struct rt_mmcsd_cmd *cmd;
struct rt_mmcsd_cmd *stop;
struct rt_mmcsd_cmd *sbc; /* SET_BLOCK_COUNT for multiblock */
/* Allow other commands during this ongoing data transfer or busy wait */
int cap_cmd_during_tfr;
};
/*the following is response bit*/
#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
#define R1_ERASE_PARAM (1 << 27) /* ex, c */
#define R1_WP_VIOLATION (1 << 26) /* erx, c */
#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
#define R1_CC_ERROR (1 << 20) /* erx, c */
#define R1_ERROR (1 << 19) /* erx, c */
#define R1_UNDERRUN (1 << 18) /* ex, c */
#define R1_OVERRUN (1 << 17) /* ex, c */
#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
#define R1_ERASE_RESET (1 << 13) /* sr, c */
#define R1_STATUS(x) (x & 0xFFFFE000)
#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
#define R1_APP_CMD (1 << 5) /* sr, c */
#define R1_SPI_IDLE (1 << 0)
#define R1_SPI_ERASE_RESET (1 << 1)
#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
#define R1_SPI_COM_CRC (1 << 3)
#define R1_SPI_ERASE_SEQ (1 << 4)
#define R1_SPI_ADDRESS (1 << 5)
#define R1_SPI_PARAMETER (1 << 6)
/* R1 bit 7 is always zero */
#define R2_SPI_CARD_LOCKED (1 << 8)
#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
#define R2_SPI_ERROR (1 << 10)
#define R2_SPI_CC_ERROR (1 << 11)
#define R2_SPI_CARD_ECC_ERROR (1 << 12)
#define R2_SPI_WP_VIOLATION (1 << 13)
#define R2_SPI_ERASE_PARAM (1 << 14)
#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
#define CARD_BUSY 0x80000000 /* Card Power up status bit */
/* R5 response bits */
#define R5_COM_CRC_ERROR (1 << 15)
#define R5_ILLEGAL_COMMAND (1 << 14)
#define R5_ERROR (1 << 11)
#define R5_FUNCTION_NUMBER (1 << 9)
#define R5_OUT_OF_RANGE (1 << 8)
#define R5_STATUS(x) (x & 0xCB00)
#define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12)
/**
* fls - find last (most-significant) bit set
* @x: the word to search
*
* This is defined the same way as ffs.
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
rt_inline rt_uint32_t __rt_fls(rt_uint32_t val)
{
rt_uint32_t bit = 32;
if (!val)
return 0;
if (!(val & 0xffff0000u))
{
val <<= 16;
bit -= 16;
}
if (!(val & 0xff000000u))
{
val <<= 8;
bit -= 8;
}
if (!(val & 0xf0000000u))
{
val <<= 4;
bit -= 4;
}
if (!(val & 0xc0000000u))
{
val <<= 2;
bit -= 2;
}
if (!(val & 0x80000000u))
{
bit -= 1;
}
return bit;
}
#define MMCSD_HOST_PLUGED 0
#define MMCSD_HOST_UNPLUGED 1
rt_int32_t mmcsd_excute_tuning(struct rt_mmcsd_card *card);
int mmcsd_wait_cd_changed(rt_int32_t timeout);
void mmcsd_host_lock(struct rt_mmcsd_host *host);
void mmcsd_host_unlock(struct rt_mmcsd_host *host);
void mmcsd_req_complete(struct rt_mmcsd_host *host);
void mmcsd_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req);
rt_int32_t mmcsd_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd, int retries);
rt_int32_t mmcsd_go_idle(struct rt_mmcsd_host *host);
rt_int32_t mmcsd_spi_read_ocr(struct rt_mmcsd_host *host, rt_int32_t high_capacity, rt_uint32_t *ocr);
rt_int32_t mmcsd_all_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid);
rt_int32_t mmcsd_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid);
rt_int32_t mmcsd_get_csd(struct rt_mmcsd_card *card, rt_uint32_t *csd);
rt_int32_t mmcsd_select_card(struct rt_mmcsd_card *card);
rt_int32_t mmcsd_deselect_cards(struct rt_mmcsd_card *host);
rt_int32_t mmcsd_spi_use_crc(struct rt_mmcsd_host *host, rt_int32_t use_crc);
void mmcsd_set_chip_select(struct rt_mmcsd_host *host, rt_int32_t mode);
void mmcsd_set_clock(struct rt_mmcsd_host *host, rt_uint32_t clk);
void mmcsd_set_bus_mode(struct rt_mmcsd_host *host, rt_uint32_t mode);
void mmcsd_set_bus_width(struct rt_mmcsd_host *host, rt_uint32_t width);
void mmcsd_set_timing(struct rt_mmcsd_host *host, rt_uint32_t timing);
void mmcsd_set_data_timeout(struct rt_mmcsd_data *data, const struct rt_mmcsd_card *card);
rt_uint32_t mmcsd_select_voltage(struct rt_mmcsd_host *host, rt_uint32_t ocr);
void mmcsd_change(struct rt_mmcsd_host *host);
void mmcsd_detect(void *param);
void mmcsd_host_init(struct rt_mmcsd_host *host);
struct rt_mmcsd_host *mmcsd_alloc_host(void);
void mmcsd_free_host(struct rt_mmcsd_host *host);
int rt_mmcsd_core_init(void);
int rt_mmcsd_blk_init(void);
rt_int32_t read_lba(struct rt_mmcsd_card *card, size_t lba, uint8_t *buffer, size_t count);
rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card);
void rt_mmcsd_blk_remove(struct rt_mmcsd_card *card);
#ifdef __cplusplus
}
#endif
#endif

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rt-thread/components/drivers/include/drivers/mmcsd_host.h Normal file
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/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-07-25 weety first version
* 2024-05-25 HPMicro add HS400 support
* 2024-05-26 HPMicro add UHS-I support
*/
#ifndef __HOST_H__
#define __HOST_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
struct rt_mmcsd_io_cfg
{
rt_uint32_t clock; /* clock rate */
rt_uint16_t vdd;
/* vdd stores the bit number of the selected voltage range from below. */
rt_uint8_t bus_mode; /* command output mode */
#define MMCSD_BUSMODE_OPENDRAIN 1
#define MMCSD_BUSMODE_PUSHPULL 2
rt_uint8_t chip_select; /* SPI chip select */
#define MMCSD_CS_IGNORE 0
#define MMCSD_CS_HIGH 1
#define MMCSD_CS_LOW 2
rt_uint8_t power_mode; /* power supply mode */
#define MMCSD_POWER_OFF 0
#define MMCSD_POWER_UP 1
#define MMCSD_POWER_ON 2
rt_uint8_t bus_width; /* data bus width */
#define MMCSD_BUS_WIDTH_1 0
#define MMCSD_BUS_WIDTH_4 2
#define MMCSD_BUS_WIDTH_8 3
unsigned char timing; /* timing specification used */
#define MMCSD_TIMING_LEGACY 0
#define MMCSD_TIMING_MMC_HS 1
#define MMCSD_TIMING_SD_HS 2
#define MMCSD_TIMING_UHS_SDR12 3
#define MMCSD_TIMING_UHS_SDR25 4
#define MMCSD_TIMING_UHS_SDR50 5
#define MMCSD_TIMING_UHS_SDR104 6
#define MMCSD_TIMING_UHS_DDR50 7
#define MMCSD_TIMING_MMC_DDR52 8
#define MMCSD_TIMING_MMC_HS200 9
#define MMCSD_TIMING_MMC_HS400 10
#define MMCSD_TIMING_MMC_HS400_ENH_DS 11
unsigned char drv_type; /* driver type (A, B, C, D) */
#define MMCSD_SET_DRIVER_TYPE_B 0
#define MMCSD_SET_DRIVER_TYPE_A 1
#define MMCSD_SET_DRIVER_TYPE_C 2
#define MMCSD_SET_DRIVER_TYPE_D 3
unsigned char signal_voltage;
#define MMCSD_SIGNAL_VOLTAGE_330 0
#define MMCSD_SIGNAL_VOLTAGE_180 1
#define MMCSD_SIGNAL_VOLTAGE_120 2
};
struct rt_mmcsd_host;
struct rt_mmcsd_req;
struct rt_mmcsd_host_ops
{
void (*request)(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req);
void (*set_iocfg)(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg);
rt_int32_t (*get_card_status)(struct rt_mmcsd_host *host);
void (*enable_sdio_irq)(struct rt_mmcsd_host *host, rt_int32_t en);
rt_int32_t (*execute_tuning)(struct rt_mmcsd_host *host, rt_int32_t opcode);
rt_int32_t (*switch_uhs_voltage)(struct rt_mmcsd_host *host);
};
struct rt_mmcsd_host
{
char name[RT_NAME_MAX];
struct rt_mmcsd_card *card;
const struct rt_mmcsd_host_ops *ops;
rt_uint32_t freq_min;
rt_uint32_t freq_max;
struct rt_mmcsd_io_cfg io_cfg;
rt_uint32_t valid_ocr; /* current valid OCR */
#define VDD_165_195 (1 << 7) /* VDD voltage 1.65 - 1.95 */
#define VDD_20_21 (1 << 8) /* VDD voltage 2.0 ~ 2.1 */
#define VDD_21_22 (1 << 9) /* VDD voltage 2.1 ~ 2.2 */
#define VDD_22_23 (1 << 10) /* VDD voltage 2.2 ~ 2.3 */
#define VDD_23_24 (1 << 11) /* VDD voltage 2.3 ~ 2.4 */
#define VDD_24_25 (1 << 12) /* VDD voltage 2.4 ~ 2.5 */
#define VDD_25_26 (1 << 13) /* VDD voltage 2.5 ~ 2.6 */
#define VDD_26_27 (1 << 14) /* VDD voltage 2.6 ~ 2.7 */
#define VDD_27_28 (1 << 15) /* VDD voltage 2.7 ~ 2.8 */
#define VDD_28_29 (1 << 16) /* VDD voltage 2.8 ~ 2.9 */
#define VDD_29_30 (1 << 17) /* VDD voltage 2.9 ~ 3.0 */
#define VDD_30_31 (1 << 18) /* VDD voltage 3.0 ~ 3.1 */
#define VDD_31_32 (1 << 19) /* VDD voltage 3.1 ~ 3.2 */
#define VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */
#define VDD_33_34 (1 << 21) /* VDD voltage 3.3 ~ 3.4 */
#define VDD_34_35 (1 << 22) /* VDD voltage 3.4 ~ 3.5 */
#define VDD_35_36 (1 << 23) /* VDD voltage 3.5 ~ 3.6 */
#define OCR_S18R (1 << 24) /* Switch to 1V8 Request */
rt_uint32_t flags; /* define device capabilities */
#define MMCSD_BUSWIDTH_4 (1 << 0)
#define MMCSD_BUSWIDTH_8 (1 << 1)
#define MMCSD_MUTBLKWRITE (1 << 2)
#define MMCSD_HOST_IS_SPI (1 << 3)
#define controller_is_spi(host) (host->flags & MMCSD_HOST_IS_SPI)
#define MMCSD_SUP_SDIO_IRQ (1 << 4) /* support signal pending SDIO IRQs */
#define MMCSD_SUP_HIGHSPEED (1 << 5) /* support high speed SDR */
#define MMCSD_SUP_DDR_3V3 (1 << 6)
#define MMCSD_SUP_DDR_1V8 (1 << 7)
#define MMCSD_SUP_DDR_1V2 (1 << 8)
#define MMCSD_SUP_HIGHSPEED_DDR (MMCSD_SUP_DDR_3V3 | MMCSD_SUP_DDR_1V8 | MMCSD_SUP_DDR_1V2)/* HIGH SPEED DDR */
#define MMCSD_SUP_HS200_1V8 (1 << 9)
#define MMCSD_SUP_HS200_1V2 (1 << 10)
#define MMCSD_SUP_HS200 (MMCSD_SUP_HS200_1V2 | MMCSD_SUP_HS200_1V8) /* hs200 sdr */
#define MMCSD_SUP_NONREMOVABLE (1 << 11)
#define MMCSD_SUP_HS400_1V8 (1 << 12)
#define MMCSD_SUP_HS400_1V2 (1 << 13)
#define MMCSD_SUP_HS400 (MMCSD_SUP_HS400_1V2 | MMCSD_SUP_HS400_1V8) /* hs400 ddr */
#define MMCSD_SUP_ENH_DS (1 << 14)
#define MMCSD_SUP_SDR50 (1 << 15)
#define MMCSD_SUP_SDR104 (1 << 16)
#define MMCSD_SUP_DDR50 (1 << 17)
rt_uint32_t max_seg_size; /* maximum size of one dma segment */
rt_uint32_t max_dma_segs; /* maximum number of dma segments in one request */
rt_uint32_t max_blk_size; /* maximum block size */
rt_uint32_t max_blk_count; /* maximum block count */
rt_uint32_t id; /* Assigned host id */
rt_uint32_t spi_use_crc;
struct rt_mutex bus_lock;
struct rt_semaphore sem_ack;
rt_uint32_t sdio_irq_num;
struct rt_semaphore *sdio_irq_sem;
struct rt_thread *sdio_irq_thread;
void *private_data;
};
#ifdef __cplusplus
}
#endif
#endif

93
rt-thread/components/drivers/include/drivers/mtd_nand.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-12-05 Bernard the first version
* 2011-04-02 prife add mark_badblock and check_block
*/
/*
* COPYRIGHT (C) 2012, Shanghai Real Thread
*/
#ifndef __MTD_NAND_H__
#define __MTD_NAND_H__
#include <rtthread.h>
struct rt_mtd_nand_driver_ops;
#define RT_MTD_NAND_DEVICE(device) ((struct rt_mtd_nand_device*)(device))
#define RT_MTD_EOK 0 /* NO error */
#define RT_MTD_EECC 101 /* ECC error */
#define RT_MTD_EBUSY 102 /* hardware busy */
#define RT_MTD_EIO 103 /* generic IO issue */
#define RT_MTD_ENOMEM 104 /* out of memory */
#define RT_MTD_ESRC 105 /* source issue */
#define RT_MTD_EECC_CORRECT 106 /* ECC error but correct */
struct rt_mtd_nand_device
{
struct rt_device parent;
rt_uint16_t page_size; /* The Page size in the flash */
rt_uint16_t oob_size; /* Out of bank size */
rt_uint16_t oob_free; /* the free area in oob that flash driver not use */
rt_uint16_t plane_num; /* the number of plane in the NAND Flash */
rt_uint32_t pages_per_block; /* The number of page a block */
rt_uint16_t block_total;
/* Only be touched by driver */
rt_uint32_t block_start; /* The start of available block*/
rt_uint32_t block_end; /* The end of available block */
/* operations interface */
const struct rt_mtd_nand_driver_ops *ops;
void *priv;
};
typedef struct rt_mtd_nand_device* rt_mtd_nand_t;
struct rt_mtd_nand_driver_ops
{
rt_err_t (*read_id)(struct rt_mtd_nand_device *device);
rt_err_t (*read_page)(struct rt_mtd_nand_device *device,
rt_off_t page,
rt_uint8_t *data, rt_uint32_t data_len,
rt_uint8_t *spare, rt_uint32_t spare_len);
rt_err_t (*write_page)(struct rt_mtd_nand_device *device,
rt_off_t page,
const rt_uint8_t *data, rt_uint32_t data_len,
const rt_uint8_t *spare, rt_uint32_t spare_len);
rt_err_t (*move_page)(struct rt_mtd_nand_device *device, rt_off_t src_page, rt_off_t dst_page);
rt_err_t (*erase_block)(struct rt_mtd_nand_device *device, rt_uint32_t block);
rt_err_t (*check_block)(struct rt_mtd_nand_device *device, rt_uint32_t block);
rt_err_t (*mark_badblock)(struct rt_mtd_nand_device *device, rt_uint32_t block);
};
rt_err_t rt_mtd_nand_register_device(const char *name, struct rt_mtd_nand_device *device);
rt_uint32_t rt_mtd_nand_read_id(struct rt_mtd_nand_device *device);
rt_err_t rt_mtd_nand_read(
struct rt_mtd_nand_device *device,
rt_off_t page,
rt_uint8_t *data, rt_uint32_t data_len,
rt_uint8_t *spare, rt_uint32_t spare_len);
rt_err_t rt_mtd_nand_write(
struct rt_mtd_nand_device *device,
rt_off_t page,
const rt_uint8_t *data, rt_uint32_t data_len,
const rt_uint8_t *spare, rt_uint32_t spare_len);
rt_err_t rt_mtd_nand_move_page(struct rt_mtd_nand_device *device,
rt_off_t src_page, rt_off_t dst_page);
rt_err_t rt_mtd_nand_erase_block(struct rt_mtd_nand_device *device, rt_uint32_t block);
rt_err_t rt_mtd_nand_check_block(struct rt_mtd_nand_device *device, rt_uint32_t block);
rt_err_t rt_mtd_nand_mark_badblock(struct rt_mtd_nand_device *device, rt_uint32_t block);
#endif /* MTD_NAND_H_ */

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rt-thread/components/drivers/include/drivers/mtd_nor.h Normal file
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/*
* COPYRIGHT (C) 2011-2023, Real-Thread Information Technology Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-5-30 Bernard the first version
*/
#ifndef __MTD_NOR_H__
#define __MTD_NOR_H__
#include <rtthread.h>
struct rt_mtd_nor_driver_ops;
#define RT_MTD_NOR_DEVICE(device) ((struct rt_mtd_nor_device*)(device))
struct rt_mtd_nor_device
{
struct rt_device parent;
rt_uint32_t block_size; /* The Block size in the flash */
rt_uint32_t block_start; /* The start of available block*/
rt_uint32_t block_end; /* The end of available block */
/* operations interface */
const struct rt_mtd_nor_driver_ops* ops;
};
struct rt_mtd_nor_driver_ops
{
rt_err_t (*read_id) (struct rt_mtd_nor_device* device);
rt_ssize_t (*read) (struct rt_mtd_nor_device* device, rt_off_t offset, rt_uint8_t* data, rt_size_t length);
rt_ssize_t (*write) (struct rt_mtd_nor_device* device, rt_off_t offset, const rt_uint8_t* data, rt_size_t length);
rt_err_t (*erase_block)(struct rt_mtd_nor_device* device, rt_off_t offset, rt_size_t length);
};
rt_err_t rt_mtd_nor_register_device(const char* name, struct rt_mtd_nor_device* device);
rt_uint32_t rt_mtd_nor_read_id(struct rt_mtd_nor_device* device);
rt_ssize_t rt_mtd_nor_read(struct rt_mtd_nor_device* device,
rt_off_t offset, rt_uint8_t* data, rt_size_t length);
rt_ssize_t rt_mtd_nor_write(struct rt_mtd_nor_device* device,
rt_off_t offset, const rt_uint8_t* data, rt_size_t length);
rt_err_t rt_mtd_nor_erase_block(struct rt_mtd_nor_device* device,
rt_off_t offset, rt_size_t length);
#endif

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rt-thread/components/drivers/include/drivers/ofw.h Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-08-25 GuEe-GUI first version
*/
#ifndef __OFW_H__
#define __OFW_H__
#include <rtthread.h>
#include <ref.h>
#include <bitmap.h>
#include <libfdt/libfdt.h>
typedef rt_uint32_t rt_phandle;
struct rt_ofw_prop
{
const char *name;
int length;
void *value;
struct rt_ofw_prop *next;
};
struct rt_ofw_node
{
const char *name;
/* full_name is 'path/tag' or 'path/tag@reg' */
const char *full_name;
/* phandles range from 1 to 2^32-2 (0xfffffffe) */
rt_phandle phandle;
struct rt_ofw_prop *props;
struct rt_ofw_node *parent;
struct rt_ofw_node *child;
struct rt_ofw_node *sibling;
struct rt_ref ref;
#define RT_OFW_F_SYSTEM 0 /* node is system node */
#define RT_OFW_F_READLY 1 /* node has driver */
#define RT_OFW_F_PLATFORM 2 /* node is platform device */
#define RT_OFW_F_OVERLAY 3 /* node is from overlay */
rt_bitmap_t flags;
/* RT-Thread object prototype */
void *rt_data;
};
#define RT_OFW_MAX_CELL_ARGS 16
struct rt_ofw_cell_args
{
void *data;
int args_count;
rt_uint32_t args[RT_OFW_MAX_CELL_ARGS];
};
struct rt_ofw_node_id
{
/* The name string should consist name property (deprecated) */
char name[32];
/*
* The type string should consist device_type property, such as pci, memory
* serial. Because it's deprecated in <devicetree-basics>, we can use other
* name (like "ttyS" or "ttyAMA" ...) to config with /chosen.
*/
char type[32];
/*
* The compatible string should consist only of lowercase letters, digits
* and dashes, and should start with a letter. A single comma is typically
* only used following a vendor prefix. Underscores should not be used.
*/
char compatible[128];
const void *data;
};
struct rt_ofw_stub
{
const struct rt_ofw_node_id *ids;
rt_err_t (*handler)(struct rt_ofw_node *np, const struct rt_ofw_node_id *id);
};
#define RT_OFW_SYMBOL(_class, _level) \
rt_section(".rt_ofw_data." #_class "." #_level)
#define RT_OFW_SYMBOL_TYPE_RANGE(_class, _type, _start, _end) \
static const rt_used RT_OFW_SYMBOL(_class, 0) _type _start; \
static const rt_used RT_OFW_SYMBOL(_class, end) _type _end; \
#define RT_OFW_STUB_EXPORT(_name, _ids, _class, _handler, ...) \
static const struct rt_ofw_stub __rt_ofw_##_name \
rt_used RT_OFW_SYMBOL(_class, __VA_ARGS__ _) = \
{ \
.ids = _ids, \
.handler = _handler, \
}
#define RT_OFW_STUB_RANGE_EXPORT(_class, _start, _end) \
RT_OFW_SYMBOL_TYPE_RANGE(_class, struct rt_ofw_stub, _start = {}, _end = {})
#define rt_ofw_data(np) ((struct rt_ofw_node *)np)->rt_data
rt_inline rt_bool_t rt_ofw_node_test_flag(const struct rt_ofw_node *np, int flag)
{
return rt_bitmap_test_bit((rt_bitmap_t *)&np->flags, flag);
}
rt_inline void rt_ofw_node_set_flag(struct rt_ofw_node *np, int flag)
{
rt_bitmap_set_bit(&np->flags, flag);
}
rt_inline rt_bool_t rt_ofw_node_test_and_set_flag(struct rt_ofw_node *np, int flag)
{
rt_bool_t res = rt_ofw_node_test_flag(np, flag);
rt_ofw_node_set_flag(np, flag);
return res;
}
rt_inline void rt_ofw_node_clear_flag(struct rt_ofw_node *np, int flag)
{
rt_bitmap_clear_bit(&np->flags, flag);
}
rt_err_t rt_ofw_node_destroy(struct rt_ofw_node *np);
struct rt_ofw_node *rt_ofw_node_get(struct rt_ofw_node *np);
void rt_ofw_node_put(struct rt_ofw_node *np);
rt_bool_t rt_ofw_node_tag_equ(const struct rt_ofw_node *np, const char *tag);
rt_bool_t rt_ofw_node_tag_prefix(const struct rt_ofw_node *np, const char *prefix);
rt_inline const char *rt_ofw_node_name(const struct rt_ofw_node *np)
{
return np ? np->name : "<no-node>";
}
rt_inline const char *rt_ofw_node_full_name(const struct rt_ofw_node *np)
{
return np ? np->full_name : "<no-node>";
}
rt_bool_t rt_ofw_machine_is_compatible(const char *compatible);
rt_bool_t rt_ofw_node_is_available(const struct rt_ofw_node *np);
rt_bool_t rt_ofw_node_is_compatible(const struct rt_ofw_node *np, const char *compatible);
struct rt_ofw_node_id *rt_ofw_prop_match(struct rt_ofw_prop *prop, const struct rt_ofw_node_id *ids);
struct rt_ofw_node_id *rt_ofw_node_match(struct rt_ofw_node *np, const struct rt_ofw_node_id *ids);
struct rt_ofw_node *rt_ofw_find_node_by_tag(struct rt_ofw_node *from, const char *tag);
struct rt_ofw_node *rt_ofw_find_node_by_prop_r(struct rt_ofw_node *from, const char *propname,
const struct rt_ofw_prop **out_prop);
rt_inline struct rt_ofw_node *rt_ofw_find_node_by_prop(struct rt_ofw_node *from, const char *propname)
{
return rt_ofw_find_node_by_prop_r(from, propname, RT_NULL);
}
struct rt_ofw_node *rt_ofw_find_node_by_name(struct rt_ofw_node *from, const char *name);
struct rt_ofw_node *rt_ofw_find_node_by_type(struct rt_ofw_node *from, const char *type);
struct rt_ofw_node *rt_ofw_find_node_by_compatible(struct rt_ofw_node *from, const char *compatible);
struct rt_ofw_node *rt_ofw_find_node_by_ids_r(struct rt_ofw_node *from, const struct rt_ofw_node_id *ids,
const struct rt_ofw_node_id **out_id);
struct rt_ofw_node *rt_ofw_find_node_by_path(const char *path);
struct rt_ofw_node *rt_ofw_find_node_by_phandle(rt_phandle phandle);
rt_inline struct rt_ofw_node *rt_ofw_find_node_by_ids(struct rt_ofw_node *from, const struct rt_ofw_node_id *ids)
{
return rt_ofw_find_node_by_ids_r(from, ids, RT_NULL);
}
struct rt_ofw_node *rt_ofw_get_parent(const struct rt_ofw_node *np);
struct rt_ofw_node *rt_ofw_get_child_by_tag(const struct rt_ofw_node *parent, const char *tag);
struct rt_ofw_node *rt_ofw_get_child_by_compatible(const struct rt_ofw_node *parent, const char *compatible);
int rt_ofw_get_child_count(const struct rt_ofw_node *np);
int rt_ofw_get_available_child_count(const struct rt_ofw_node *np);
struct rt_ofw_node *rt_ofw_get_next_node(struct rt_ofw_node *prev);
struct rt_ofw_node *rt_ofw_get_next_parent(struct rt_ofw_node *prev);
struct rt_ofw_node *rt_ofw_get_next_child(const struct rt_ofw_node *parent, struct rt_ofw_node *prev);
struct rt_ofw_node *rt_ofw_get_next_available_child(const struct rt_ofw_node *parent, struct rt_ofw_node *prev);
struct rt_ofw_node *rt_ofw_get_cpu_node(int cpu, int *thread, rt_bool_t (*match_cpu_hwid)(int cpu, rt_uint64_t hwid));
struct rt_ofw_node *rt_ofw_get_next_cpu_node(struct rt_ofw_node *prev);
struct rt_ofw_node *rt_ofw_get_cpu_state_node(struct rt_ofw_node *cpu_np, int index);
rt_uint64_t rt_ofw_get_cpu_id(struct rt_ofw_node *cpu_np);
rt_uint64_t rt_ofw_get_cpu_hwid(struct rt_ofw_node *cpu_np, unsigned int thread);
struct rt_ofw_node *rt_ofw_get_alias_node(const char *tag, int id);
int rt_ofw_get_alias_id(struct rt_ofw_node *np, const char *tag);
int rt_ofw_get_alias_last_id(const char *tag);
rt_err_t rt_ofw_map_id(struct rt_ofw_node *np, rt_uint32_t id, const char *map_name, const char *map_mask_name,
struct rt_ofw_node **ref_np, rt_uint32_t *out_id);
struct rt_ofw_node *rt_ofw_append_child(struct rt_ofw_node *parent, const char *full_name);
rt_err_t rt_ofw_append_prop(struct rt_ofw_node *np, const char *name, int length, void *value);
struct rt_ofw_node *rt_ofw_parse_phandle(const struct rt_ofw_node *np, const char *phandle_name, int index);
rt_err_t rt_ofw_parse_phandle_cells(const struct rt_ofw_node *np, const char *list_name, const char *cells_name,
int index, struct rt_ofw_cell_args *out_args);
int rt_ofw_count_phandle_cells(const struct rt_ofw_node *np, const char *list_name, const char *cells_name);
const char *rt_ofw_get_prop_fuzzy_name(const struct rt_ofw_node *np, const char *name);
struct rt_ofw_prop *rt_ofw_get_prop(const struct rt_ofw_node *np, const char *name, rt_ssize_t *out_length);
rt_inline const void *rt_ofw_prop_read_raw(const struct rt_ofw_node *np, const char *name, rt_ssize_t *out_length)
{
struct rt_ofw_prop *prop = rt_ofw_get_prop(np, name, out_length);
return prop ? prop->value : RT_NULL;
}
int rt_ofw_prop_read_u8_array_index(const struct rt_ofw_node *np, const char *propname,
int index, int nr, rt_uint8_t *out_values);
int rt_ofw_prop_read_u16_array_index(const struct rt_ofw_node *np, const char *propname,
int index, int nr, rt_uint16_t *out_values);
int rt_ofw_prop_read_u32_array_index(const struct rt_ofw_node *np, const char *propname,
int index, int nr, rt_uint32_t *out_values);
int rt_ofw_prop_read_u64_array_index(const struct rt_ofw_node *np, const char *propname,
int index, int nr, rt_uint64_t *out_values);
int rt_ofw_prop_read_string_array_index(const struct rt_ofw_node *np, const char *propname,
int index, int nr, const char **out_strings);
int rt_ofw_prop_count_of_size(const struct rt_ofw_node *np, const char *propname, int size);
int rt_ofw_prop_index_of_string(const struct rt_ofw_node *np, const char *propname, const char *string);
const fdt32_t *rt_ofw_prop_next_u32(struct rt_ofw_prop *prop, const fdt32_t *cur, rt_uint32_t *out_value);
const char *rt_ofw_prop_next_string(struct rt_ofw_prop *prop, const char *cur);
rt_inline rt_err_t rt_ofw_prop_read_u8_index(const struct rt_ofw_node *np, const char *propname,
int index, rt_uint8_t *out_value)
{
int nr = rt_ofw_prop_read_u8_array_index(np, propname, index, 1, out_value);
return nr > 0 ? RT_EOK : (rt_err_t)nr;
}
rt_inline rt_err_t rt_ofw_prop_read_u16_index(const struct rt_ofw_node *np, const char *propname,
int index, rt_uint16_t *out_value)
{
int nr = rt_ofw_prop_read_u16_array_index(np, propname, index, 1, out_value);
return nr > 0 ? RT_EOK : (rt_err_t)nr;
}
rt_inline rt_err_t rt_ofw_prop_read_u32_index(const struct rt_ofw_node *np, const char *propname,
int index, rt_uint32_t *out_value)
{
int nr = rt_ofw_prop_read_u32_array_index(np, propname, index, 1, out_value);
return nr > 0 ? RT_EOK : (rt_err_t)nr;
}
rt_inline rt_err_t rt_ofw_prop_read_u64_index(const struct rt_ofw_node *np, const char *propname,
int index, rt_uint64_t *out_value)
{
int nr = rt_ofw_prop_read_u64_array_index(np, propname, index, 1, out_value);
return nr > 0 ? RT_EOK : (rt_err_t)nr;
}
rt_inline rt_err_t rt_ofw_prop_read_string_index(const struct rt_ofw_node *np, const char *propname,
int index, const char **out_string)
{
int nr = rt_ofw_prop_read_string_array_index(np, propname, index, 1, out_string);
return nr > 0 ? RT_EOK : (rt_err_t)nr;
}
rt_inline rt_err_t rt_ofw_prop_read_u8(const struct rt_ofw_node *np, const char *propname,
rt_uint8_t *out_value)
{
return rt_ofw_prop_read_u8_index(np, propname, 0, out_value);
}
rt_inline rt_err_t rt_ofw_prop_read_u16(const struct rt_ofw_node *np, const char *propname,
rt_uint16_t *out_value)
{
return rt_ofw_prop_read_u16_index(np, propname, 0, out_value);
}
rt_inline rt_err_t rt_ofw_prop_read_u32(const struct rt_ofw_node *np, const char *propname,
rt_uint32_t *out_value)
{
return rt_ofw_prop_read_u32_index(np, propname, 0, out_value);
}
rt_inline rt_err_t rt_ofw_prop_read_s32(const struct rt_ofw_node *np, const char *propname,
rt_int32_t *out_value)
{
return rt_ofw_prop_read_u32_index(np, propname, 0, (rt_uint32_t *)out_value);
}
rt_inline rt_err_t rt_ofw_prop_read_u64(const struct rt_ofw_node *np, const char *propname,
rt_uint64_t *out_value)
{
return rt_ofw_prop_read_u64_index(np, propname, 0, out_value);
}
rt_inline rt_err_t rt_ofw_prop_read_string(const struct rt_ofw_node *np, const char *propname,
const char **out_string)
{
return rt_ofw_prop_read_string_index(np, propname, 0, out_string);
}
rt_inline rt_bool_t rt_ofw_prop_read_bool(const struct rt_ofw_node *np, const char *propname)
{
return rt_ofw_get_prop(np, propname, RT_NULL) ? RT_TRUE : RT_FALSE;
}
rt_inline int rt_ofw_prop_count_of_u8(const struct rt_ofw_node *np, const char *propname)
{
return rt_ofw_prop_count_of_size(np, propname, sizeof(rt_uint8_t));
}
rt_inline int rt_ofw_prop_count_of_u16(const struct rt_ofw_node *np, const char *propname)
{
return rt_ofw_prop_count_of_size(np, propname, sizeof(rt_uint16_t));
}
rt_inline int rt_ofw_prop_count_of_u32(const struct rt_ofw_node *np, const char *propname)
{
return rt_ofw_prop_count_of_size(np, propname, sizeof(rt_uint32_t));
}
rt_inline int rt_ofw_prop_count_of_u64(const struct rt_ofw_node *np, const char *propname)
{
return rt_ofw_prop_count_of_size(np, propname, sizeof(rt_uint64_t));
}
rt_inline const char *rt_ofw_node_type(const struct rt_ofw_node *np)
{
return rt_ofw_prop_read_raw(np, "device_type", RT_NULL);
}
rt_inline rt_bool_t rt_ofw_node_is_type(const struct rt_ofw_node *np, const char *type)
{
const char *get_type = rt_ofw_node_type(np);
return np && get_type && type && !rt_strcmp(get_type, type);
}
#define rt_ofw_foreach_node_by_tag(np, name) \
for (np = rt_ofw_find_node_by_tag(RT_NULL, name); np; \
np = rt_ofw_find_node_by_tag(np, name))
#define rt_ofw_foreach_node_by_prop(np, prop_name) \
for (np = rt_ofw_find_node_by_prop(RT_NULL, prop_name); \
np; np = rt_ofw_find_node_by_prop(np, prop_name))
#define rt_ofw_foreach_node_by_prop_r(np, prop_name, prop) \
for (np = rt_ofw_find_node_by_prop_r(RT_NULL, prop_name, prop); \
np; np = rt_ofw_find_node_by_prop_r(np, prop_name, prop))
#define rt_ofw_foreach_node_by_name(np, name) \
for (np = rt_ofw_find_node_by_name(RT_NULL, name); np; \
np = rt_ofw_find_node_by_name(np, name))
#define rt_ofw_foreach_node_by_type(np, type) \
for (np = rt_ofw_find_node_by_type(RT_NULL, type); np; \
np = rt_ofw_find_node_by_type(np, type))
#define rt_ofw_foreach_node_by_compatible(np, type, compatible) \
for (np = rt_ofw_find_node_by_compatible(RT_NULL, type, compatible); np; \
np = rt_ofw_find_node_by_compatible(np, type, compatible))
#define rt_ofw_foreach_node_by_ids_r(np, id, ids) \
for (np = rt_ofw_find_node_by_ids_r(RT_NULL, ids, id); \
np; np = rt_ofw_find_node_by_ids_r(np, ids, id))
#define rt_ofw_foreach_node_by_ids(np, ids) \
for (np = rt_ofw_find_node_by_ids(RT_NULL, ids); np; \
np = rt_ofw_find_node_by_ids(np, ids))
#define rt_ofw_foreach_nodes(from, np) \
for (np = rt_ofw_get_next_node(from); \
np; np = rt_ofw_get_next_node(np))
#define rt_ofw_foreach_allnodes(np) \
rt_ofw_foreach_nodes(RT_NULL, np)
#define rt_ofw_foreach_parent_node(np) \
for (np = rt_ofw_get_next_parent(rt_ofw_node_get(np)); \
np; np = rt_ofw_get_next_parent(np))
#define rt_ofw_foreach_child_node(parent, child) \
for (child = rt_ofw_get_next_child(parent, RT_NULL); \
child; child = rt_ofw_get_next_child(parent, child))
#define rt_ofw_foreach_available_child_node(parent, child) \
for (child = rt_ofw_get_next_available_child(parent, RT_NULL); child; \
child = rt_ofw_get_next_available_child(parent, child))
#define rt_ofw_foreach_cpu_node(cpu_np) \
for (cpu_np = rt_ofw_get_next_cpu_node(RT_NULL); \
cpu_np; cpu_np = rt_ofw_get_next_cpu_node(cpu_np))
#define rt_ofw_foreach_prop(np, prop) \
for (prop = np->props; prop; prop = prop->next)
#define rt_ofw_foreach_prop_u32(np, propname, prop, p, u) \
for (prop = rt_ofw_get_prop(np, propname, RT_NULL), \
p = rt_ofw_prop_next_u32(prop, RT_NULL, &u); p; \
p = rt_ofw_prop_next_u32(prop, p, &u))
#define rt_ofw_foreach_prop_string(np, propname, prop, s) \
for (prop = rt_ofw_get_prop(np, propname, RT_NULL), \
s = rt_ofw_prop_next_string(prop, RT_NULL); s; \
s = rt_ofw_prop_next_string(prop, s))
#define rt_ofw_foreach_stub(stub, stub_start, stub_end) \
for (stub = stub_start; stub <= stub_end; ++stub)
struct rt_ofw_stub *rt_ofw_stub_probe_range(struct rt_ofw_node *np,
const struct rt_ofw_stub *stub_start, const struct rt_ofw_stub *stub_end);
struct rt_object *rt_ofw_parse_object(struct rt_ofw_node *np, const char *obj_name, const char *cells_name);
rt_err_t rt_ofw_console_setup(void);
const char *rt_ofw_bootargs_select(const char *key, int index);
#ifdef RT_USING_CONSOLE
void rt_ofw_node_dump_dts(struct rt_ofw_node *np, rt_bool_t sibling_too);
#endif
#endif /* __OFW_H__ */

77
rt-thread/components/drivers/include/drivers/ofw_fdt.h Normal file
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@@ -0,0 +1,77 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-08-25 GuEe-GUI first version
*/
#ifndef __OFW_FDT_H__
#define __OFW_FDT_H__
#include <mm_page.h>
#include <drivers/ofw.h>
struct rt_fdt_earlycon
{
union { rt_ubase_t mmio, port; };
union { rt_ubase_t size, width; };
void *fdt;
char options[32];
long nodeoffset;
void *data;
void (*console_putc)(void *data, char c);
#define FDT_EARLYCON_KICK_UPDATE 0
#define FDT_EARLYCON_KICK_COMPLETED 1
void (*console_kick)(struct rt_fdt_earlycon *earlycon, int why);
long msg_idx;
char msg[RT_FDT_EARLYCON_MSG_SIZE * 1024];
};
struct rt_fdt_earlycon_id
{
char *name;
char *type;
char *compatible;
rt_err_t (*setup)(struct rt_fdt_earlycon *earlycon, const char *options);
};
#define RT_FDT_EARLYCON_EXPORT(_name, _type, _compatible, _setup) \
static const struct rt_fdt_earlycon_id __rt_fdt_##_name##_earlycon \
rt_used RT_OFW_SYMBOL(earlycon, _) = \
{ \
.name = #_name, \
.type = _type, \
.compatible = _compatible, \
.setup = _setup, \
}
const char *rt_fdt_node_name(const char *full_name);
rt_uint64_t rt_fdt_read_number(const fdt32_t *cell, int size);
rt_uint64_t rt_fdt_next_cell(const fdt32_t **cellptr, int size);
rt_uint64_t rt_fdt_translate_address(void *fdt, int nodeoffset, rt_uint64_t address);
rt_bool_t rt_fdt_device_is_available(void *fdt, int nodeoffset);
rt_err_t rt_fdt_commit_memregion_early(rt_region_t *region, rt_bool_t is_reserved);
rt_err_t rt_fdt_commit_memregion_request(rt_region_t **out_region, rt_size_t *out_nr, rt_bool_t is_reserved);
rt_err_t rt_fdt_prefetch(void *fdt);
rt_err_t rt_fdt_scan_root(void);
rt_err_t rt_fdt_scan_memory(void);
rt_err_t rt_fdt_scan_initrd(rt_uint64_t *ranges);
rt_err_t rt_fdt_model_dump(void);
rt_err_t rt_fdt_boot_dump(void);
void rt_fdt_earlycon_output(const char *str);
void rt_fdt_earlycon_kick(int why);
rt_err_t rt_fdt_scan_chosen_stdout(void);
rt_err_t rt_fdt_unflatten(void);
struct rt_ofw_node *rt_fdt_unflatten_single(void *fdt);
#endif /* __OFW_FDT_H__ */

33
rt-thread/components/drivers/include/drivers/ofw_io.h Normal file
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@@ -0,0 +1,33 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-08-25 GuEe-GUI first version
*/
#ifndef __OFW_IO_H__
#define __OFW_IO_H__
#include <ioremap.h>
#include <drivers/ofw.h>
int rt_ofw_bus_addr_cells(struct rt_ofw_node *np);
int rt_ofw_bus_size_cells(struct rt_ofw_node *np);
int rt_ofw_io_addr_cells(struct rt_ofw_node *np);
int rt_ofw_io_size_cells(struct rt_ofw_node *np);
int rt_ofw_get_address_count(struct rt_ofw_node *np);
rt_err_t rt_ofw_get_address(struct rt_ofw_node *np, int index, rt_uint64_t *out_address, rt_uint64_t *out_size);
rt_err_t rt_ofw_get_address_by_name(struct rt_ofw_node *np, const char *name,
rt_uint64_t *out_address, rt_uint64_t *out_size);
int rt_ofw_get_address_array(struct rt_ofw_node *np, int nr, rt_uint64_t *out_regs);
rt_uint64_t rt_ofw_translate_address(struct rt_ofw_node *np, const char *range_type, rt_uint64_t address);
void *rt_ofw_iomap(struct rt_ofw_node *np, int index);
void *rt_ofw_iomap_by_name(struct rt_ofw_node *np, const char *name);
#endif /* __OFW_IO_H__ */

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