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This commit is contained in:
47
libraries/HAL_Drivers/drivers/config/g0/adc_config.h
Normal file
47
libraries/HAL_Drivers/drivers/config/g0/adc_config.h
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@@ -0,0 +1,47 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
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||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
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||||
* 2018-01-05 zylx first version
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||||
* 2019-01-08 SummerGift clean up the code
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||||
*/
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#ifndef __ADC_CONFIG_H__
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#define __ADC_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_ADC1
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#ifndef ADC1_CONFIG
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#define ADC1_CONFIG \
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{ \
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.Instance = ADC1, \
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.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1, \
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.Init.Resolution = ADC_RESOLUTION_12B, \
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.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
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.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.LowPowerAutoPowerOff = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.DiscontinuousConvMode = ENABLE, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.DMAContinuousRequests = ENABLE, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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}
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#endif /* ADC1_CONFIG */
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#endif /* BSP_USING_ADC1 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ADC_CONFIG_H__ */
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125
libraries/HAL_Drivers/drivers/config/g0/dma_config.h
Normal file
125
libraries/HAL_Drivers/drivers/config/g0/dma_config.h
Normal file
@@ -0,0 +1,125 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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||||
*
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||||
* Change Logs:
|
||||
* Date Author Notes
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||||
* 2018-01-05 zylx first version
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* 2019-01-08 SummerGift clean up the code
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(STM32G030xx) || defined(STM32G031xx) || defined(STM32G041xx)
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#define DMA_Channelx_IRQn DMA1_Ch4_5_DMAMUX1_OVR_IRQn
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#define DMA_Channelx_IRQHandler DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler
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#elif defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
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#define DMA_Channelx_IRQn DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQn
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#define DMA_Channelx_IRQHandler DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler
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#else
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#define DMA_Channelx_IRQn DMA1_Ch4_7_DMAMUX1_OVR_IRQn
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#define DMA_Channelx_IRQHandler DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
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#endif
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/* DMA1 channel2 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
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#define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX
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#define SPI1_RX_DMA_IRQ DMA1_Channel2_3_IRQn
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#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Channel2
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#define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX
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#define SPI2_RX_DMA_IRQ DMA1_Channel2_3_IRQn
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#endif
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/* DMA1 channle3 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI1_TX_DMA_INSTANCE DMA1_Channel3
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#define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX
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#define SPI1_TX_DMA_IRQ DMA1_Channel2_3_IRQn
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#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_TX_DMA_INSTANCE DMA1_Channel3
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#define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX
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#define SPI2_TX_DMA_IRQ DMA1_Channel2_3_IRQn
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#endif
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/* DMA1 channle4 */
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#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
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#define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART1_RX_DMA_INSTANCE DMA1_Channel4
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#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX
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#define UART1_RX_DMA_IRQ DMA_Channelx_IRQn
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#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Channel4
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#define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX
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#define SPI2_RX_DMA_IRQ DMA_Channelx_IRQn
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#endif
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/* DMA1 channle5 */
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#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
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#define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
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#define UART1_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART1_TX_DMA_INSTANCE DMA1_Channel5
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#define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX
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#define UART1_TX_DMA_IRQ DMA_Channelx_IRQn
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#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_TX_DMA_INSTANCE DMA1_Channel5
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#define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX
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#define SPI2_TX_DMA_IRQ DMA_Channelx_IRQn
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#endif
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#if !(defined(STM32G030xx) || defined(STM32G031xx) || defined(STM32G041xx))
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/* DMA1 channle6 */
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#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
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#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART2_RX_DMA_INSTANCE DMA1_Channel6
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#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
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#define UART2_RX_DMA_IRQ DMA_Channelx_IRQn
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#endif
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/* DMA1 channle7 */
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#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
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#define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
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#define UART2_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART2_TX_DMA_INSTANCE DMA1_Channel7
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#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX
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#define UART2_TX_DMA_IRQ DMA_Channelx_IRQn
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#endif
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#endif
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/* DMA1 channle1 */
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#if defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
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#define LPUART1_DMA_RX_IRQHandler DMA1_Channel1_IRQHandler
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#define LPUART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define LPUART1_RX_DMA_INSTANCE DMA1_Channel1
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#define LPUART1_RX_DMA_REQUEST DMA_REQUEST_LPUART1_RX
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#define LPUART1_RX_DMA_IRQ DMA1_Channel1_IRQn
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DMA_CONFIG_H__ */
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197
libraries/HAL_Drivers/drivers/config/g0/pwm_config.h
Normal file
197
libraries/HAL_Drivers/drivers/config/g0/pwm_config.h
Normal file
@@ -0,0 +1,197 @@
|
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-01-05 zylx first version
|
||||
* 2019-01-08 SummerGift clean up the code
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* 2023-04-08 Wangyuqiang complete PWM defination
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*/
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#ifndef __PWM_CONFIG_H__
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#define __PWM_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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||||
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#ifdef BSP_USING_PWM1
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#define PWM1_CONFIG \
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{ \
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.tim_handle.Instance = TIM1, \
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.name = "pwm1", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM1 */
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#ifdef BSP_USING_PWM2
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#define PWM2_CONFIG \
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{ \
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.tim_handle.Instance = TIM2, \
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.name = "pwm2", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM2 */
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#ifdef BSP_USING_PWM3
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#define PWM3_CONFIG \
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{ \
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.tim_handle.Instance = TIM3, \
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.name = "pwm3", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM3 */
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#ifdef BSP_USING_PWM4
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#define PWM4_CONFIG \
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{ \
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.tim_handle.Instance = TIM4, \
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.name = "pwm4", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM4 */
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#ifdef BSP_USING_PWM5
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#define PWM5_CONFIG \
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{ \
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.tim_handle.Instance = TIM5, \
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.name = "pwm5", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM5 */
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#ifdef BSP_USING_PWM6
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#define PWM6_CONFIG \
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{ \
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.tim_handle.Instance = TIM6, \
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.name = "pwm6", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM6 */
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#ifdef BSP_USING_PWM7
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#define PWM7_CONFIG \
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{ \
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.tim_handle.Instance = TIM7, \
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.name = "pwm7", \
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.channel = RT_NULL \
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||||
}
|
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#endif /* BSP_USING_PWM7 */
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||||
|
||||
#ifdef BSP_USING_PWM8
|
||||
#define PWM8_CONFIG \
|
||||
{ \
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||||
.tim_handle.Instance = TIM8, \
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.name = "pwm8", \
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.channel = RT_NULL \
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||||
}
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||||
#endif /* BSP_USING_PWM8 */
|
||||
|
||||
#ifdef BSP_USING_PWM9
|
||||
#define PWM9_CONFIG \
|
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{ \
|
||||
.tim_handle.Instance = TIM9, \
|
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.name = "pwm9", \
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.channel = RT_NULL \
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||||
}
|
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#endif /* BSP_USING_PWM9 */
|
||||
|
||||
#ifdef BSP_USING_PWM10
|
||||
#define PWM10_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM10, \
|
||||
.name = "pwm10", \
|
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.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM10 */
|
||||
|
||||
#ifdef BSP_USING_PWM11
|
||||
#define PWM11_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM11, \
|
||||
.name = "pwm11", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM11 */
|
||||
|
||||
#ifdef BSP_USING_PWM12
|
||||
#define PWM12_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM12, \
|
||||
.name = "pwm12", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM12 */
|
||||
|
||||
#ifdef BSP_USING_PWM13
|
||||
#define PWM13_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM13, \
|
||||
.name = "pwm13", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM13 */
|
||||
|
||||
#ifdef BSP_USING_PWM14
|
||||
#define PWM14_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM14, \
|
||||
.name = "pwm14", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM14 */
|
||||
|
||||
#ifdef BSP_USING_PWM15
|
||||
#define PWM15_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM15, \
|
||||
.name = "pwm15", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM15 */
|
||||
|
||||
#ifdef BSP_USING_PWM16
|
||||
#define PWM16_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM16, \
|
||||
.name = "pwm16", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM16 */
|
||||
|
||||
#ifdef BSP_USING_PWM17
|
||||
#define PWM17_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM17, \
|
||||
.name = "pwm17", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM17 */
|
||||
|
||||
#ifdef BSP_USING_PWM18
|
||||
#define PWM18_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM18, \
|
||||
.name = "pwm18", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM18 */
|
||||
|
||||
#ifdef BSP_USING_PWM19
|
||||
#define PWM19_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM19, \
|
||||
.name = "pwm19", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM19 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PWM_CONFIG_H__ */
|
||||
107
libraries/HAL_Drivers/drivers/config/g0/spi_config.h
Normal file
107
libraries/HAL_Drivers/drivers/config/g0/spi_config.h
Normal file
@@ -0,0 +1,107 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-01-05 zylx first version
|
||||
* 2019-01-08 SummerGift clean up the code
|
||||
*/
|
||||
|
||||
#ifndef __SPI_CONFIG_H__
|
||||
#define __SPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI1
|
||||
#ifndef SPI1_BUS_CONFIG
|
||||
#define SPI1_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1, \
|
||||
.bus_name = "spi1", \
|
||||
.irq_type = SPI1_IRQn, \
|
||||
}
|
||||
#endif /* SPI1_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
|
||||
#ifdef BSP_SPI1_TX_USING_DMA
|
||||
#ifndef SPI1_TX_DMA_CONFIG
|
||||
#define SPI1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI1_TX_DMA_RCC, \
|
||||
.Instance = SPI1_TX_DMA_INSTANCE, \
|
||||
.request = SPI1_TX_DMA_REQUEST, \
|
||||
.dma_irq = SPI1_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI1_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI1_RX_USING_DMA
|
||||
#ifndef SPI1_RX_DMA_CONFIG
|
||||
#define SPI1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI1_RX_DMA_RCC, \
|
||||
.Instance = SPI1_RX_DMA_INSTANCE, \
|
||||
.request = SPI1_RX_DMA_REQUEST, \
|
||||
.dma_irq = SPI1_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI2
|
||||
#ifndef SPI2_BUS_CONFIG
|
||||
#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||
#define SPI2_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI2, \
|
||||
.bus_name = "spi2", \
|
||||
.irq_type = SPI2_3_IRQn, \
|
||||
}
|
||||
#else
|
||||
#define SPI2_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI2, \
|
||||
.bus_name = "spi2", \
|
||||
.irq_type = SPI2_IRQn, \
|
||||
}
|
||||
#endif /* defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx) */
|
||||
#endif /* SPI2_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI2 */
|
||||
|
||||
#ifdef BSP_SPI2_TX_USING_DMA
|
||||
#ifndef SPI2_TX_DMA_CONFIG
|
||||
#define SPI2_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI2_TX_DMA_RCC, \
|
||||
.Instance = SPI2_TX_DMA_INSTANCE, \
|
||||
.request = SPI2_TX_DMA_REQUEST, \
|
||||
.dma_irq = SPI2_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI2_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI2_RX_USING_DMA
|
||||
#ifndef SPI2_RX_DMA_CONFIG
|
||||
#define SPI2_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI2_RX_DMA_RCC, \
|
||||
.Instance = SPI2_RX_DMA_INSTANCE, \
|
||||
.request = SPI2_RX_DMA_REQUEST, \
|
||||
.dma_irq = SPI2_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI2_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_RX_USING_DMA */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SPI_CONFIG_H__ */
|
||||
|
||||
|
||||
|
||||
66
libraries/HAL_Drivers/drivers/config/g0/tim_config.h
Normal file
66
libraries/HAL_Drivers/drivers/config/g0/tim_config.h
Normal file
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-01-05 zylx first version
|
||||
* 2019-01-08 SummerGift clean up the code
|
||||
*/
|
||||
|
||||
#ifndef __TIM_CONFIG_H__
|
||||
#define __TIM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef TIM_DEV_INFO_CONFIG
|
||||
#define TIM_DEV_INFO_CONFIG \
|
||||
{ \
|
||||
.maxfreq = 1000000, \
|
||||
.minfreq = 2000, \
|
||||
.maxcnt = 0xFFFF, \
|
||||
.cntmode = HWTIMER_CNTMODE_UP, \
|
||||
}
|
||||
#endif /* TIM_DEV_INFO_CONFIG */
|
||||
|
||||
#ifdef BSP_USING_TIM2
|
||||
#ifndef TIM2_CONFIG
|
||||
#define TIM2_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM2, \
|
||||
.tim_irqn = TIM2_IRQn, \
|
||||
.name = "timer2", \
|
||||
}
|
||||
#endif /* TIM2_CONFIG */
|
||||
#endif /* BSP_USING_TIM2 */
|
||||
|
||||
#ifdef BSP_USING_TIM3
|
||||
#ifndef TIM3_CONFIG
|
||||
#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||
#define TIM3_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM3, \
|
||||
.tim_irqn = TIM3_TIM4_IRQn, \
|
||||
.name = "timer3", \
|
||||
}
|
||||
#else
|
||||
#define TIM3_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM3, \
|
||||
.tim_irqn = TIM3_IRQn, \
|
||||
.name = "timer3", \
|
||||
}
|
||||
#endif /* defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx) */
|
||||
#endif /* TIM3_CONFIG */
|
||||
#endif /* BSP_USING_TIM3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __TIM_CONFIG_H__ */
|
||||
276
libraries/HAL_Drivers/drivers/config/g0/uart_config.h
Normal file
276
libraries/HAL_Drivers/drivers/config/g0/uart_config.h
Normal file
@@ -0,0 +1,276 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-30 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __UART_CONFIG_H__
|
||||
#define __UART_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_LPUART1)
|
||||
#ifndef LPUART1_CONFIG
|
||||
#if defined(STM32G071xx) || defined(STM32G081xx)
|
||||
#define LPUART1_CONFIG \
|
||||
{ \
|
||||
.name = "lpuart1", \
|
||||
.Instance = LPUART1, \
|
||||
.irq_type = USART3_4_LPUART1_IRQn, \
|
||||
}
|
||||
#elif defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||
#define LPUART1_CONFIG \
|
||||
{ \
|
||||
.name = "lpuart1", \
|
||||
.Instance = LPUART1, \
|
||||
.irq_type = USART3_4_5_6_LPUART1_IRQn, \
|
||||
}
|
||||
#endif /* defined(STM32G071xx) || defined(STM32G081xx) */
|
||||
#endif /* LPUART1_CONFIG */
|
||||
#if defined(BSP_LPUART1_RX_USING_DMA)
|
||||
#ifndef LPUART1_DMA_CONFIG
|
||||
#define LPUART1_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = LPUART1_RX_DMA_INSTANCE, \
|
||||
.request = LPUART1_RX_DMA_REQUEST, \
|
||||
.dma_rcc = LPUART1_RX_DMA_RCC, \
|
||||
.dma_irq = LPUART1_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* LPUART1_DMA_CONFIG */
|
||||
#endif /* BSP_LPUART1_RX_USING_DMA */
|
||||
#endif /* BSP_USING_LPUART1 */
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#ifndef UART1_CONFIG
|
||||
#define UART1_CONFIG \
|
||||
{ \
|
||||
.name = "uart1", \
|
||||
.Instance = USART1, \
|
||||
.irq_type = USART1_IRQn, \
|
||||
}
|
||||
#endif /* UART1_CONFIG */
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_UART1_RX_USING_DMA)
|
||||
#ifndef UART1_DMA_RX_CONFIG
|
||||
#define UART1_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART1_RX_DMA_INSTANCE, \
|
||||
.request = UART1_RX_DMA_REQUEST, \
|
||||
.dma_rcc = UART1_RX_DMA_RCC, \
|
||||
.dma_irq = UART1_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART1_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART1_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART1_TX_USING_DMA)
|
||||
#ifndef UART1_DMA_TX_CONFIG
|
||||
#define UART1_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART1_TX_DMA_INSTANCE, \
|
||||
.request = UART1_TX_DMA_REQUEST, \
|
||||
.dma_rcc = UART1_TX_DMA_RCC, \
|
||||
.dma_irq = UART1_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART1_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART1_TX_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#ifndef UART2_CONFIG
|
||||
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||
#define UART2_CONFIG \
|
||||
{ \
|
||||
.name = "uart2", \
|
||||
.Instance = USART2, \
|
||||
.irq_type = USART2_LPUART2_IRQn , \
|
||||
}
|
||||
#else
|
||||
#define UART2_CONFIG \
|
||||
{ \
|
||||
.name = "uart2", \
|
||||
.Instance = USART2, \
|
||||
.irq_type = USART2_IRQn, \
|
||||
}
|
||||
#endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */
|
||||
#endif /* UART2_CONFIG */
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_UART2_RX_USING_DMA)
|
||||
#ifndef UART2_DMA_RX_CONFIG
|
||||
#define UART2_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART2_RX_DMA_INSTANCE, \
|
||||
.request = UART2_RX_DMA_REQUEST, \
|
||||
.dma_rcc = UART2_RX_DMA_RCC, \
|
||||
.dma_irq = UART2_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART2_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART2_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART2_TX_USING_DMA)
|
||||
#ifndef UART2_DMA_TX_CONFIG
|
||||
#define UART2_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART2_TX_DMA_INSTANCE, \
|
||||
.request = UART2_TX_DMA_REQUEST, \
|
||||
.dma_rcc = UART2_TX_DMA_RCC, \
|
||||
.dma_irq = UART2_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART2_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART2_TX_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#ifndef UART3_CONFIG
|
||||
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.Instance = USART3, \
|
||||
.irq_type = USART3_4_5_6_LPUART1_IRQn, \
|
||||
}
|
||||
#elif defined(STM32G070xx)
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.Instance = USART3, \
|
||||
.irq_type = USART3_4_IRQn, \
|
||||
}
|
||||
#elif defined(STM32G071xx) || defined(STM32G081xx)
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.Instance = USART3, \
|
||||
.irq_type = USART3_4_LPUART1_IRQn, \
|
||||
}
|
||||
#elif defined(STM32G0B0xx)
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.Instance = USART3, \
|
||||
.irq_type = USART3_4_5_6_IRQn, \
|
||||
}
|
||||
#else
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.Instance = USART3, \
|
||||
.irq_type = USART3_IRQn, \
|
||||
}
|
||||
#endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */
|
||||
#endif /* UART3_CONFIG */
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined(BSP_UART3_RX_USING_DMA)
|
||||
#ifndef UART3_DMA_RX_CONFIG
|
||||
#define UART3_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART3_RX_DMA_INSTANCE, \
|
||||
.request = UART3_RX_DMA_REQUEST, \
|
||||
.dma_rcc = UART3_RX_DMA_RCC, \
|
||||
.dma_irq = UART3_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART3_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART3_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_UART4)
|
||||
#ifndef UART4_CONFIG
|
||||
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||
#define UART4_CONFIG \
|
||||
{ \
|
||||
.name = "uart4", \
|
||||
.Instance = USART4, \
|
||||
.irq_type = USART3_4_5_6_LPUART1_IRQn, \
|
||||
}
|
||||
#elif defined(STM32G070xx)
|
||||
#define UART4_CONFIG \
|
||||
{ \
|
||||
.name = "uart4", \
|
||||
.Instance = USART4, \
|
||||
.irq_type = USART3_4_IRQn, \
|
||||
}
|
||||
#elif defined(STM32G071xx) || defined(STM32G081xx)
|
||||
#define UART4_CONFIG \
|
||||
{ \
|
||||
.name = "uart4", \
|
||||
.Instance = USART4, \
|
||||
.irq_type = USART3_4_LPUART1_IRQn, \
|
||||
}
|
||||
#elif defined(STM32G0B0xx)
|
||||
#define UART4_CONFIG \
|
||||
{ \
|
||||
.name = "uart4", \
|
||||
.Instance = USART4, \
|
||||
.irq_type = USART3_4_5_6_IRQn, \
|
||||
}
|
||||
#else
|
||||
#define UART4_CONFIG \
|
||||
{ \
|
||||
.name = "uart4", \
|
||||
.Instance = USART4, \
|
||||
.irq_type = USART4_IRQn, \
|
||||
}
|
||||
#endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */
|
||||
#endif /* UART4_CONFIG */
|
||||
#endif /* BSP_USING_UART4 */
|
||||
|
||||
#if defined(BSP_UART4_RX_USING_DMA)
|
||||
#ifndef UART4_DMA_RX_CONFIG
|
||||
#define UART4_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART4_RX_DMA_INSTANCE, \
|
||||
.request = UART4_RX_DMA_REQUEST, \
|
||||
.dma_rcc = UART4_RX_DMA_RCC, \
|
||||
.dma_irq = UART4_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART4_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART4_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_UART5)
|
||||
#ifndef UART5_CONFIG
|
||||
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||
#define UART5_CONFIG \
|
||||
{ \
|
||||
.name = "uart5", \
|
||||
.Instance = UART5, \
|
||||
.irq_type = USART3_4_5_6_LPUART1_IRQn, \
|
||||
}
|
||||
#elif defined(STM32G0B0xx)
|
||||
#define UART5_CONFIG \
|
||||
{ \
|
||||
.name = "uart5", \
|
||||
.Instance = UART5, \
|
||||
.irq_type = USART3_4_5_6_IRQn, \
|
||||
}
|
||||
#else
|
||||
#define UART5_CONFIG \
|
||||
{ \
|
||||
.name = "uart5", \
|
||||
.Instance = UART5, \
|
||||
.irq_type = UART5_IRQn, \
|
||||
}
|
||||
#endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */
|
||||
#endif /* UART5_CONFIG */
|
||||
#endif /* BSP_USING_UART5 */
|
||||
|
||||
#if defined(BSP_UART5_RX_USING_DMA)
|
||||
#ifndef UART5_DMA_RX_CONFIG
|
||||
#define UART5_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = DMA_NOT_AVAILABLE, \
|
||||
}
|
||||
#endif /* UART5_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART5_RX_USING_DMA */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __UART_CONFIG_H__ */
|
||||
Reference in New Issue
Block a user