first
This commit is contained in:
87
libraries/HAL_Drivers/drivers/config/f7/adc_config.h
Normal file
87
libraries/HAL_Drivers/drivers/config/f7/adc_config.h
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@@ -0,0 +1,87 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-06 zylx first version
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*/
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#ifndef __ADC_CONFIG_H__
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#define __ADC_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_ADC1
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#ifndef ADC1_CONFIG
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#define ADC1_CONFIG \
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{ \
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.Instance = ADC1, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_12B, \
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.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
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.Init.ScanConvMode = DISABLE, \
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.Init.EOCSelection = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 0, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.DMAContinuousRequests = DISABLE, \
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}
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#endif /* ADC1_CONFIG */
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#endif /* BSP_USING_ADC1 */
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#ifdef BSP_USING_ADC2
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#ifndef ADC2_CONFIG
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#define ADC2_CONFIG \
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{ \
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.Instance = ADC2, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_12B, \
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.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
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.Init.ScanConvMode = DISABLE, \
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.Init.EOCSelection = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 0, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.DMAContinuousRequests = DISABLE, \
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}
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#endif /* ADC2_CONFIG */
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#endif /* BSP_USING_ADC2 */
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#ifdef BSP_USING_ADC3
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#ifndef ADC3_CONFIG
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#define ADC3_CONFIG \
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{ \
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.Instance = ADC3, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_12B, \
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.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
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.Init.ScanConvMode = DISABLE, \
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.Init.EOCSelection = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 0, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.DMAContinuousRequests = DISABLE, \
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}
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#endif /* ADC3_CONFIG */
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#endif /* BSP_USING_ADC3 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ADC_CONFIG_H__ */
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229
libraries/HAL_Drivers/drivers/config/f7/dma_config.h
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229
libraries/HAL_Drivers/drivers/config/f7/dma_config.h
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@@ -0,0 +1,229 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-01-02 zylx first version
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* 2019-01-08 SummerGift clean up the code
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DMA1 stream0 */
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
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#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_RX_DMA_INSTANCE DMA1_Stream0
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#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn
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#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
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#define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
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#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART5_RX_DMA_INSTANCE DMA1_Stream0
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#define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn
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#endif
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/* DMA1 stream1 */
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#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
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#define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler
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#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART3_RX_DMA_INSTANCE DMA1_Stream1
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#define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn
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#endif
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/* DMA1 stream2 */
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
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#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_RX_DMA_INSTANCE DMA1_Stream2
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#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
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#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
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#define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
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#define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART4_RX_DMA_INSTANCE DMA1_Stream2
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#define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn
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#endif
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/* DMA1 stream3 */
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#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
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#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
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#endif
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/* DMA1 stream4 */
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#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
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#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
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#endif
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/* DMA1 stream5 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_TX_DMA_INSTANCE DMA1_Stream5
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#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
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#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler
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#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART2_RX_DMA_INSTANCE DMA1_Stream5
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#define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn
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#endif
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/* DMA1 stream6 */
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/* DMA1 stream7 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
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#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
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#endif
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/* DMA2 stream0 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
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#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
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#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
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#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
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#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
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#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI4_RX_DMA_INSTANCE DMA2_Stream0
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#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn
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#endif
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/* DMA2 stream1 */
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#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
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#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
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#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI4_TX_DMA_INSTANCE DMA2_Stream1
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#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4
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#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn
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#endif
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/* DMA2 stream2 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
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#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
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#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
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#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
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#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define UART1_RX_DMA_INSTANCE DMA2_Stream2
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#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn
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#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
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#define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler
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#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define QSPI_DMA_INSTANCE DMA2_Stream2
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#define QSPI_DMA_CHANNEL DMA_CHANNEL_11
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#define QSPI_DMA_IRQ DMA2_Stream2_IRQn
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#endif
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/* DMA2 stream3 */
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#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
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#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
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#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
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#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2
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#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
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#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_TX_DMA_INSTANCE DMA2_Stream3
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#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
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#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn
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#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
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#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
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#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI4_RX_DMA_INSTANCE DMA2_Stream3
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#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5
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#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn
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#endif
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/* DMA2 stream4 */
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#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
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#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
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#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
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#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2
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#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
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#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
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#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
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#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI4_TX_DMA_INSTANCE DMA2_Stream4
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#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5
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#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn
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#endif
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/* DMA2 stream5 */
|
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
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#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
|
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#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
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#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
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#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
|
||||
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
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#define UART1_RX_DMA_INSTANCE DMA2_Stream5
|
||||
#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
|
||||
#define UART1_RX_DMA_IRQ DMA2_Stream5_IRQn
|
||||
#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
|
||||
#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
|
||||
#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
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#define SPI5_RX_DMA_INSTANCE DMA2_Stream5
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#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7
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#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn
|
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#endif
|
||||
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||||
/* DMA2 stream6 */
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#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
|
||||
#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
|
||||
#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
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#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7
|
||||
#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA2 stream7 */
|
||||
#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
|
||||
#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
|
||||
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define QSPI_DMA_INSTANCE DMA2_Stream7
|
||||
#define QSPI_DMA_CHANNEL DMA_CHANNEL_3
|
||||
#define QSPI_DMA_IRQ DMA2_Stream7_IRQn
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DMA_CONFIG_H__ */
|
||||
196
libraries/HAL_Drivers/drivers/config/f7/pwm_config.h
Normal file
196
libraries/HAL_Drivers/drivers/config/f7/pwm_config.h
Normal file
@@ -0,0 +1,196 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-13 zylx first version
|
||||
* 2023-04-08 Wangyuqiang complete PWM defination
|
||||
*/
|
||||
|
||||
#ifndef __PWM_CONFIG_H__
|
||||
#define __PWM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM1
|
||||
#define PWM1_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM1, \
|
||||
.name = "pwm1", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM1 */
|
||||
|
||||
#ifdef BSP_USING_PWM2
|
||||
#define PWM2_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM2, \
|
||||
.name = "pwm2", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM2 */
|
||||
|
||||
#ifdef BSP_USING_PWM3
|
||||
#define PWM3_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM3, \
|
||||
.name = "pwm3", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM3 */
|
||||
|
||||
#ifdef BSP_USING_PWM4
|
||||
#define PWM4_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM4, \
|
||||
.name = "pwm4", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM4 */
|
||||
|
||||
#ifdef BSP_USING_PWM5
|
||||
#define PWM5_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM5, \
|
||||
.name = "pwm5", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM5 */
|
||||
|
||||
#ifdef BSP_USING_PWM6
|
||||
#define PWM6_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM6, \
|
||||
.name = "pwm6", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM6 */
|
||||
|
||||
#ifdef BSP_USING_PWM7
|
||||
#define PWM7_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM7, \
|
||||
.name = "pwm7", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM7 */
|
||||
|
||||
#ifdef BSP_USING_PWM8
|
||||
#define PWM8_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM8, \
|
||||
.name = "pwm8", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM8 */
|
||||
|
||||
#ifdef BSP_USING_PWM9
|
||||
#define PWM9_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM9, \
|
||||
.name = "pwm9", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM9 */
|
||||
|
||||
#ifdef BSP_USING_PWM10
|
||||
#define PWM10_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM10, \
|
||||
.name = "pwm10", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM10 */
|
||||
|
||||
#ifdef BSP_USING_PWM11
|
||||
#define PWM11_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM11, \
|
||||
.name = "pwm11", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM11 */
|
||||
|
||||
#ifdef BSP_USING_PWM12
|
||||
#define PWM12_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM12, \
|
||||
.name = "pwm12", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM12 */
|
||||
|
||||
#ifdef BSP_USING_PWM13
|
||||
#define PWM13_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM13, \
|
||||
.name = "pwm13", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM13 */
|
||||
|
||||
#ifdef BSP_USING_PWM14
|
||||
#define PWM14_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM14, \
|
||||
.name = "pwm14", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM14 */
|
||||
|
||||
#ifdef BSP_USING_PWM15
|
||||
#define PWM15_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM15, \
|
||||
.name = "pwm15", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM15 */
|
||||
|
||||
#ifdef BSP_USING_PWM16
|
||||
#define PWM16_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM16, \
|
||||
.name = "pwm16", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM16 */
|
||||
|
||||
#ifdef BSP_USING_PWM17
|
||||
#define PWM17_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM17, \
|
||||
.name = "pwm17", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM17 */
|
||||
|
||||
#ifdef BSP_USING_PWM18
|
||||
#define PWM18_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM18, \
|
||||
.name = "pwm18", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM18 */
|
||||
|
||||
#ifdef BSP_USING_PWM19
|
||||
#define PWM19_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM19, \
|
||||
.name = "pwm19", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM19 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PWM_CONFIG_H__ */
|
||||
56
libraries/HAL_Drivers/drivers/config/f7/qspi_config.h
Normal file
56
libraries/HAL_Drivers/drivers/config/f7/qspi_config.h
Normal file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-22 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __QSPI_CONFIG_H__
|
||||
#define __QSPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_QSPI
|
||||
#ifndef QSPI_BUS_CONFIG
|
||||
#define QSPI_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = QUADSPI, \
|
||||
.Init.FifoThreshold = 4, \
|
||||
.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
|
||||
.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE, \
|
||||
}
|
||||
#endif /* QSPI_BUS_CONFIG */
|
||||
#endif /* BSP_USING_QSPI */
|
||||
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
#ifndef QSPI_DMA_CONFIG
|
||||
#define QSPI_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = QSPI_DMA_INSTANCE, \
|
||||
.Init.Channel = QSPI_DMA_CHANNEL, \
|
||||
.Init.Direction = DMA_PERIPH_TO_MEMORY, \
|
||||
.Init.PeriphInc = DMA_PINC_DISABLE, \
|
||||
.Init.MemInc = DMA_MINC_ENABLE, \
|
||||
.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \
|
||||
.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \
|
||||
.Init.Mode = DMA_NORMAL, \
|
||||
.Init.Priority = DMA_PRIORITY_LOW \
|
||||
}
|
||||
#endif /* QSPI_DMA_CONFIG */
|
||||
#endif /* BSP_QSPI_USING_DMA */
|
||||
|
||||
#define QSPI_IRQn QUADSPI_IRQn
|
||||
#define QSPI_IRQHandler QUADSPI_IRQHandler
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __QSPI_CONFIG_H__ */
|
||||
44
libraries/HAL_Drivers/drivers/config/f7/sdio_config.h
Normal file
44
libraries/HAL_Drivers/drivers/config/f7/sdio_config.h
Normal file
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-13 BalanceTWK first version
|
||||
*/
|
||||
|
||||
#ifndef __SDIO_CONFIG_H__
|
||||
#define __SDIO_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SDIO
|
||||
#define SDIO_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SDMMC1, \
|
||||
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
|
||||
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
|
||||
.dma_rx.Instance = DMA2_Stream3, \
|
||||
.dma_rx.channel = DMA_CHANNEL_4, \
|
||||
.dma_rx.dma_irq = DMA2_Stream3_IRQn, \
|
||||
.dma_tx.Instance = DMA2_Stream6, \
|
||||
.dma_tx.channel = DMA_CHANNEL_4, \
|
||||
.dma_tx.dma_irq = DMA2_Stream6_IRQn, \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SDIO_CONFIG_H__ */
|
||||
|
||||
|
||||
|
||||
199
libraries/HAL_Drivers/drivers/config/f7/spi_config.h
Normal file
199
libraries/HAL_Drivers/drivers/config/f7/spi_config.h
Normal file
@@ -0,0 +1,199 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-06 SummerGift first version
|
||||
*/
|
||||
|
||||
#ifndef __SPI_CONFIG_H__
|
||||
#define __SPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI1
|
||||
#ifndef SPI1_BUS_CONFIG
|
||||
#define SPI1_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1, \
|
||||
.bus_name = "spi1", \
|
||||
.irq_type = SPI1_IRQn, \
|
||||
}
|
||||
#endif /* SPI1_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
|
||||
#ifdef BSP_SPI1_TX_USING_DMA
|
||||
#ifndef SPI1_TX_DMA_CONFIG
|
||||
#define SPI1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI1_TX_DMA_RCC, \
|
||||
.Instance = SPI1_TX_DMA_INSTANCE, \
|
||||
.channel = SPI1_TX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI1_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI1_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI1_RX_USING_DMA
|
||||
#ifndef SPI1_RX_DMA_CONFIG
|
||||
#define SPI1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI1_RX_DMA_RCC, \
|
||||
.Instance = SPI1_RX_DMA_INSTANCE, \
|
||||
.channel = SPI1_RX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI1_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI2
|
||||
#ifndef SPI2_BUS_CONFIG
|
||||
#define SPI2_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI2, \
|
||||
.bus_name = "spi2", \
|
||||
.irq_type = SPI2_IRQn, \
|
||||
}
|
||||
#endif /* SPI2_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI2 */
|
||||
|
||||
#ifdef BSP_SPI2_TX_USING_DMA
|
||||
#ifndef SPI2_TX_DMA_CONFIG
|
||||
#define SPI2_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI2_TX_DMA_RCC, \
|
||||
.Instance = SPI2_TX_DMA_INSTANCE, \
|
||||
.channel = SPI2_TX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI2_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI2_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI2_RX_USING_DMA
|
||||
#ifndef SPI2_RX_DMA_CONFIG
|
||||
#define SPI2_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI2_RX_DMA_RCC, \
|
||||
.Instance = SPI2_RX_DMA_INSTANCE, \
|
||||
.channel = SPI2_RX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI2_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI2_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI3
|
||||
#ifndef SPI3_BUS_CONFIG
|
||||
#define SPI3_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI3, \
|
||||
.bus_name = "spi3", \
|
||||
.irq_type = SPI3_IRQn, \
|
||||
}
|
||||
#endif /* SPI3_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI3 */
|
||||
|
||||
#ifdef BSP_SPI3_TX_USING_DMA
|
||||
#ifndef SPI3_TX_DMA_CONFIG
|
||||
#define SPI3_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI3_TX_DMA_RCC, \
|
||||
.Instance = SPI3_TX_DMA_INSTANCE, \
|
||||
.channel = SPI3_TX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI3_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI3_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI3_RX_USING_DMA
|
||||
#ifndef SPI3_RX_DMA_CONFIG
|
||||
#define SPI3_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI3_RX_DMA_RCC, \
|
||||
.Instance = SPI3_RX_DMA_INSTANCE, \
|
||||
.channel = SPI3_RX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI3_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI3_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI4
|
||||
#ifndef SPI4_BUS_CONFIG
|
||||
#define SPI4_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI4, \
|
||||
.bus_name = "spi4", \
|
||||
.irq_type = SPI4_IRQn, \
|
||||
}
|
||||
#endif /* SPI4_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI4 */
|
||||
|
||||
#ifdef BSP_SPI4_TX_USING_DMA
|
||||
#ifndef SPI4_TX_DMA_CONFIG
|
||||
#define SPI4_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI4_TX_DMA_RCC, \
|
||||
.Instance = SPI4_TX_DMA_INSTANCE, \
|
||||
.channel = SPI4_TX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI4_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI4_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI4_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI4_RX_USING_DMA
|
||||
#ifndef SPI4_RX_DMA_CONFIG
|
||||
#define SPI4_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI4_RX_DMA_RCC, \
|
||||
.Instance = SPI4_RX_DMA_INSTANCE, \
|
||||
.channel = SPI4_RX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI4_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI4_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI4_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI5
|
||||
#ifndef SPI5_BUS_CONFIG
|
||||
#define SPI5_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI5, \
|
||||
.bus_name = "spi5", \
|
||||
.irq_type = SPI5_IRQn, \
|
||||
}
|
||||
#endif /* SPI5_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI5 */
|
||||
|
||||
#ifdef BSP_SPI5_TX_USING_DMA
|
||||
#ifndef SPI5_TX_DMA_CONFIG
|
||||
#define SPI5_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI5_TX_DMA_RCC, \
|
||||
.Instance = SPI5_TX_DMA_INSTANCE, \
|
||||
.channel = SPI5_TX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI5_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI5_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI5_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI5_RX_USING_DMA
|
||||
#ifndef SPI5_RX_DMA_CONFIG
|
||||
#define SPI5_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI5_RX_DMA_RCC, \
|
||||
.Instance = SPI5_RX_DMA_INSTANCE, \
|
||||
.channel = SPI5_RX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI5_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI5_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI5_RX_USING_DMA */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SPI_CONFIG_H__ */
|
||||
67
libraries/HAL_Drivers/drivers/config/f7/tim_config.h
Normal file
67
libraries/HAL_Drivers/drivers/config/f7/tim_config.h
Normal file
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-11 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __TIM_CONFIG_H__
|
||||
#define __TIM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef TIM_DEV_INFO_CONFIG
|
||||
#define TIM_DEV_INFO_CONFIG \
|
||||
{ \
|
||||
.maxfreq = 1000000, \
|
||||
.minfreq = 3000, \
|
||||
.maxcnt = 0xFFFF, \
|
||||
.cntmode = HWTIMER_CNTMODE_UP, \
|
||||
}
|
||||
#endif /* TIM_DEV_INFO_CONFIG */
|
||||
|
||||
#ifdef BSP_USING_TIM11
|
||||
#ifndef TIM11_CONFIG
|
||||
#define TIM11_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM11, \
|
||||
.tim_irqn = TIM1_TRG_COM_TIM11_IRQn, \
|
||||
.name = "timer11", \
|
||||
}
|
||||
#endif /* TIM11_CONFIG */
|
||||
#endif /* BSP_USING_TIM11 */
|
||||
|
||||
#ifdef BSP_USING_TIM13
|
||||
#ifndef TIM13_CONFIG
|
||||
#define TIM13_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM13, \
|
||||
.tim_irqn = TIM8_UP_TIM13_IRQn, \
|
||||
.name = "timer13", \
|
||||
}
|
||||
#endif /* TIM13_CONFIG */
|
||||
#endif /* BSP_USING_TIM13 */
|
||||
|
||||
#ifdef BSP_USING_TIM14
|
||||
#ifndef TIM14_CONFIG
|
||||
#define TIM14_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM14, \
|
||||
.tim_irqn = TIM8_TRG_COM_TIM14_IRQn, \
|
||||
.name = "timer14", \
|
||||
}
|
||||
#endif /* TIM14_CONFIG */
|
||||
#endif /* BSP_USING_TIM14 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __TIM_CONFIG_H__ */
|
||||
163
libraries/HAL_Drivers/drivers/config/f7/uart_config.h
Normal file
163
libraries/HAL_Drivers/drivers/config/f7/uart_config.h
Normal file
@@ -0,0 +1,163 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-30 SummerGift first version
|
||||
* 2019-01-05 zylx modify dma support
|
||||
*/
|
||||
|
||||
#ifndef __UART_CONFIG_H__
|
||||
#define __UART_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#ifndef UART1_CONFIG
|
||||
#define UART1_CONFIG \
|
||||
{ \
|
||||
.name = "uart1", \
|
||||
.Instance = USART1, \
|
||||
.irq_type = USART1_IRQn, \
|
||||
}
|
||||
#endif /* UART1_CONFIG */
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_UART1_RX_USING_DMA)
|
||||
#ifndef UART1_DMA_RX_CONFIG
|
||||
#define UART1_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART1_RX_DMA_INSTANCE, \
|
||||
.channel = UART1_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART1_RX_DMA_RCC, \
|
||||
.dma_irq = UART1_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART1_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART1_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#ifndef UART2_CONFIG
|
||||
#define UART2_CONFIG \
|
||||
{ \
|
||||
.name = "uart2", \
|
||||
.Instance = USART2, \
|
||||
.irq_type = USART2_IRQn, \
|
||||
}
|
||||
#endif /* UART2_CONFIG */
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_UART2_RX_USING_DMA)
|
||||
#ifndef UART2_DMA_RX_CONFIG
|
||||
#define UART2_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART2_RX_DMA_INSTANCE, \
|
||||
.channel = UART2_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART2_RX_DMA_RCC, \
|
||||
.dma_irq = UART2_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART2_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART2_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#ifndef UART3_CONFIG
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.Instance = USART3, \
|
||||
.irq_type = USART3_IRQn, \
|
||||
}
|
||||
#endif /* UART3_CONFIG */
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined(BSP_UART3_RX_USING_DMA)
|
||||
#ifndef UART3_DMA_RX_CONFIG
|
||||
#define UART3_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART3_RX_DMA_INSTANCE, \
|
||||
.channel = UART3_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART3_RX_DMA_RCC, \
|
||||
.dma_irq = UART3_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART3_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART3_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_UART4)
|
||||
#ifndef UART4_CONFIG
|
||||
#define UART4_CONFIG \
|
||||
{ \
|
||||
.name = "uart4", \
|
||||
.Instance = UART4, \
|
||||
.irq_type = UART4_IRQn, \
|
||||
}
|
||||
#endif /* UART4_CONFIG */
|
||||
#endif /* BSP_USING_UART4 */
|
||||
|
||||
#if defined(BSP_UART4_RX_USING_DMA)
|
||||
#ifndef UART4_DMA_RX_CONFIG
|
||||
#define UART4_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART4_RX_DMA_INSTANCE, \
|
||||
.channel = UART4_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART4_RX_DMA_RCC, \
|
||||
.dma_irq = UART4_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART4_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART4_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_UART5)
|
||||
#ifndef UART5_CONFIG
|
||||
#define UART5_CONFIG \
|
||||
{ \
|
||||
.name = "uart5", \
|
||||
.Instance = UART5, \
|
||||
.irq_type = UART5_IRQn, \
|
||||
}
|
||||
#endif /* UART5_CONFIG */
|
||||
#endif /* BSP_USING_UART5 */
|
||||
|
||||
#if defined(BSP_UART5_RX_USING_DMA)
|
||||
#ifndef UART5_DMA_RX_CONFIG
|
||||
#define UART5_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART5_RX_DMA_INSTANCE, \
|
||||
.channel = UART5_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART5_RX_DMA_RCC, \
|
||||
.dma_irq = UART5_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART5_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART5_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_UART6)
|
||||
#ifndef UART6_CONFIG
|
||||
#define UART6_CONFIG \
|
||||
{ \
|
||||
.name = "uart6", \
|
||||
.Instance = USART6, \
|
||||
.irq_type = USART6_IRQn, \
|
||||
}
|
||||
#endif /* UART6_CONFIG */
|
||||
#endif /* BSP_USING_UART6 */
|
||||
|
||||
#if defined(BSP_UART6_RX_USING_DMA)
|
||||
#ifndef UART6_DMA_RX_CONFIG
|
||||
#define UART6_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART6_RX_DMA_INSTANCE, \
|
||||
.channel = UART6_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART6_RX_DMA_RCC, \
|
||||
.dma_irq = UART6_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART6_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART6_RX_USING_DMA */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user