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james
2024-08-05 20:57:09 +08:00
commit 46d9ee7795
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316
board/ports/audio/drv_es8388.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2019-07-31 Zero-Free first implementation
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "drv_es8388.h"
/* ES8388 address */
#define ES8388_ADDR 0x10 /*0x11:CE=1;0x10:CE=0*/
struct es8388_device
{
struct rt_i2c_bus_device *i2c;
rt_uint16_t pin;
};
static struct es8388_device es_dev = {0};
static rt_uint16_t reg_read(rt_uint8_t addr)
{
struct rt_i2c_msg msg[2] = {0};
rt_uint8_t val = 0xff;
RT_ASSERT(es_dev.i2c != RT_NULL);
msg[0].addr = ES8388_ADDR;
msg[0].flags = RT_I2C_WR;
msg[0].len = 1;
msg[0].buf = &addr;
msg[1].addr = ES8388_ADDR;
msg[1].flags = RT_I2C_RD;
msg[1].len = 1;
msg[1].buf = &val;
if (rt_i2c_transfer(es_dev.i2c, msg, 2) != 2)
{
rt_kprintf("I2C read data failed, reg = 0x%02x. \n", addr);
return 0xff;
}
return val;
}
static void reg_write(rt_uint8_t addr, rt_uint8_t val)
{
struct rt_i2c_msg msgs[1] = {0};
rt_uint8_t buff[2] = {0};
RT_ASSERT(es_dev.i2c != RT_NULL);
buff[0] = addr;
buff[1] = val;
msgs[0].addr = ES8388_ADDR;
msgs[0].flags = RT_I2C_WR;
msgs[0].buf = buff;
msgs[0].len = 2;
if (rt_i2c_transfer(es_dev.i2c, msgs, 1) != 1)
{
rt_kprintf("I2C write data failed, reg = 0x%2x. \n", addr);
return;
}
}
static int es8388_set_adc_dac_volume(int mode, int volume, int dot)
{
int res = 0;
if (volume < -96 || volume > 0)
{
if (volume < -96)
volume = -96;
else
volume = 0;
}
dot = (dot >= 5 ? 1 : 0);
volume = (-volume << 1) + dot;
if (mode == ES_MODE_ADC || mode == ES_MODE_DAC_ADC)
{
reg_write(ES8388_ADCCONTROL8, volume);
reg_write(ES8388_ADCCONTROL9, volume); //ADC Right Volume=0db
}
if (mode == ES_MODE_DAC || mode == ES_MODE_DAC_ADC)
{
reg_write(ES8388_DACCONTROL5, volume);
reg_write(ES8388_DACCONTROL4, volume);
}
return res;
}
void es8388_set_voice_mute(rt_bool_t enable)
{
rt_uint8_t reg = 0;
reg = reg_read(ES8388_DACCONTROL3);
reg = reg & 0xFB;
reg_write(ES8388_DACCONTROL3, reg | (((int)enable) << 2));
}
rt_err_t es8388_init(const char *i2c_name, rt_uint16_t pin)
{
es_dev.i2c = rt_i2c_bus_device_find(i2c_name);
if (es_dev.i2c == RT_NULL)
{
rt_kprintf("%s bus not found\n", i2c_name);
return -RT_ERROR;
}
es_dev.pin = pin;
reg_write(ES8388_DACCONTROL3, 0x04); // 0x04 mute/0x00 unmute&ramp;DAC unmute and disabled digital volume control soft ramp
/* Chip Control and Power Management */
reg_write(ES8388_CONTROL2, 0x50);
reg_write(ES8388_CHIPPOWER, 0x00); //normal all and power up all
reg_write(ES8388_MASTERMODE, 0x00); //TODO:CODEC IN I2S SLAVE MODE
/* dac */
reg_write(ES8388_DACPOWER, 0xC0); //disable DAC and disable Lout/Rout/1/2
reg_write(ES8388_CONTROL1, 0x12); //Enfr=0,Play&Record Mode,(0x17-both of mic&paly)
// reg_write(ES8388_CONTROL2, 0); //LPVrefBuf=0,Pdn_ana=0
reg_write(ES8388_DACCONTROL1, 0x18);//1a 0x18:16bit iis , 0x00:24
reg_write(ES8388_DACCONTROL2, 0x02); //DACFsMode,SINGLE SPEED; DACFsRatio,256
reg_write(ES8388_DACCONTROL16, 0x00); // 0x00 audio on LIN1&RIN1, 0x09 LIN2&RIN2
reg_write(ES8388_DACCONTROL17, 0x9C); // only left DAC to left mixer enable 0db
reg_write(ES8388_DACCONTROL20, 0x9C); // only right DAC to right mixer enable 0db
reg_write(ES8388_DACCONTROL21, 0x80); //set internal ADC and DAC use the same LRCK clock, ADC LRCK as internal LRCK
reg_write(ES8388_DACCONTROL23, 0x00); //vroi=0
es8388_set_adc_dac_volume(ES_MODE_DAC, 0, 0); // 0db
reg_write(ES8388_DACPOWER, 0x3c); //0x3c Enable DAC and Enable Lout/Rout/1/2
/* adc */
reg_write(ES8388_ADCPOWER, 0xFF);
reg_write(ES8388_ADCCONTROL1, 0xbb); // MIC Left and Right channel PGA gain
reg_write(ES8388_ADCCONTROL2, 0x00); //0x00 LINSEL & RINSEL, LIN1/RIN1 as ADC Input; DSSEL,use one DS Reg11; DSR, LINPUT1-RINPUT1
reg_write(ES8388_ADCCONTROL3, 0x02);
reg_write(ES8388_ADCCONTROL4, 0x0d); // Left/Right data, Left/Right justified mode, Bits length, I2S format
reg_write(ES8388_ADCCONTROL5, 0x02); //ADCFsMode,singel SPEED,RATIO=256
//ALC for Microphone
es8388_set_adc_dac_volume(ES_MODE_ADC, 0, 0); // 0db
reg_write(ES8388_ADCPOWER, 0x09); //Power on ADC, Enable LIN&RIN, Power off MICBIAS, set int1lp to low power mode
/* enable es8388 PA */
es8388_pa_power(RT_TRUE);
reg_write(ES8388_DACCONTROL24, 0x1E); // LOUT1VOL balanced noise: 0x18
reg_write(ES8388_DACCONTROL25, 0x1E); // ROUT1VOL balanced noise: 0x18
return RT_EOK;
}
rt_err_t es8388_start(enum es8388_mode mode)
{
int res = 0;
rt_uint8_t prev_data = 0, data = 0;
prev_data = reg_read(ES8388_DACCONTROL21);
if (mode == ES_MODE_LINE)
{
reg_write(ES8388_DACCONTROL16, 0x09); // 0x00 audio on LIN1&RIN1, 0x09 LIN2&RIN2 by pass enable
reg_write(ES8388_DACCONTROL17, 0x50); // left DAC to left mixer enable and LIN signal to left mixer enable 0db : bupass enable
reg_write(ES8388_DACCONTROL20, 0x50); // right DAC to right mixer enable and LIN signal to right mixer enable 0db : bupass enable
reg_write(ES8388_DACCONTROL21, 0xC0); //enable adc
}
else
{
reg_write(ES8388_DACCONTROL21, 0x80); //enable dac
}
data = reg_read(ES8388_DACCONTROL21);
if (prev_data != data)
{
reg_write(ES8388_CHIPPOWER, 0xF0); //start state machine
// reg_write(ES8388_ADDR, ES8388_CONTROL1, 0x16);
// reg_write(ES8388_ADDR, ES8388_CONTROL2, 0x50);
reg_write(ES8388_CHIPPOWER, 0x00); //start state machine
}
if (mode == ES_MODE_ADC || mode == ES_MODE_DAC_ADC || mode == ES_MODE_LINE)
{
reg_write(ES8388_ADCPOWER, 0x00); //power up adc and line in
}
if (mode == ES_MODE_DAC || mode == ES_MODE_DAC_ADC || mode == ES_MODE_LINE)
{
reg_write(ES8388_DACPOWER, 0x3c); //power up dac and line out
es8388_set_voice_mute(RT_FALSE);
}
return res;
}
rt_err_t es8388_stop(enum es8388_mode mode)
{
int res = 0;
if (mode == ES_MODE_LINE)
{
reg_write(ES8388_DACCONTROL21, 0x80); //enable dac
reg_write(ES8388_DACCONTROL16, 0x00); // 0x00 audio on LIN1&RIN1, 0x09 LIN2&RIN2
reg_write(ES8388_DACCONTROL17, 0x90); // only left DAC to left mixer enable 0db
reg_write(ES8388_DACCONTROL20, 0x90); // only right DAC to right mixer enable 0db
return res;
}
if (mode == ES_MODE_DAC || mode == ES_MODE_DAC_ADC)
{
reg_write(ES8388_DACPOWER, 0x00);
es8388_set_voice_mute(RT_TRUE); //res |= Es8388SetAdcDacVolume(ES_MODULE_DAC, -96, 5); // 0db
// reg_write(ES8388_ADDR, ES8388_DACPOWER, 0xC0); //power down dac and line out
}
if (mode == ES_MODE_ADC || mode == ES_MODE_DAC_ADC)
{
// Es8388SetAdcDacVolume(ES_MODULE_ADC, -96, 5); // 0db
reg_write(ES8388_ADCPOWER, 0xFF); //power down adc and line in
}
if (mode == ES_MODE_DAC_ADC)
{
reg_write(ES8388_DACCONTROL21, 0x9C); //disable mclk
// reg_write(ES8388_CONTROL1, 0x00);
// reg_write(ES8388_CONTROL2, 0x58);
// reg_write(ES8388_CHIPPOWER, 0xF3); //stop state machine
}
return RT_EOK;
}
rt_err_t es8388_fmt_set(enum es8388_mode mode, enum es8388_format fmt)
{
rt_uint8_t reg = 0;
if (mode == ES_MODE_ADC || mode == ES_MODE_DAC_ADC)
{
reg = reg_read(ES8388_ADCCONTROL4);
reg = reg & 0xfc;
reg_write(ES8388_ADCCONTROL4, reg | fmt);
}
if (mode == ES_MODE_DAC || mode == ES_MODE_DAC_ADC)
{
reg = reg_read(ES8388_DACCONTROL1);
reg = reg & 0xf9;
reg_write(ES8388_DACCONTROL1, reg | (fmt << 1));
}
return RT_EOK;
}
void es8388_volume_set(rt_uint8_t volume)
{
uint32_t real_vol = 0;
volume = 100 - volume;
if (volume > 100)
volume = 100;
real_vol = 192 * volume / 100;
reg_write(ES8388_DACCONTROL4, (rt_uint8_t)real_vol); // DAC L
reg_write(ES8388_DACCONTROL5, (rt_uint8_t)real_vol); // DAC R
}
rt_uint8_t es8388_volume_get(void)
{
rt_uint8_t volume;
volume = reg_read(ES8388_DACCONTROL24);
if (volume == 0xff)
{
volume = 0;
}
else
{
volume *= 3;
if (volume == 99)
volume = 100;
}
return volume;
}
void es8388_pa_power(rt_bool_t enable)
{
rt_pin_mode(es_dev.pin, PIN_MODE_OUTPUT);
if (enable)
{
rt_pin_write(es_dev.pin, PIN_HIGH);
}
else
{
rt_pin_write(es_dev.pin, PIN_LOW);
}
}
void estest()
{
// reg_write(ES8388_DACCONTROL24, volume);
reg_write(ES8388_ADCCONTROL1, 0x88); /* R9,左右通道PGA增益设置 */
reg_write(ES8388_ADCCONTROL2, 0x10); // 使用板载麦克风
// reg_write(ES8388_ADCCONTROL2,0x50); // 使用耳机麦克风
// reg_write(ES8388_ADCCONTROL3, 0xC0);
reg_write(ES8388_ADCCONTROL8, 0x00); // LADCVOL
reg_write(ES8388_ADCCONTROL9, 0x00); // RADCVOL
reg_write(ES8388_DACCONTROL16, 0x1B); // LMIXSEL RMIXSEL
reg_write(ES8388_DACCONTROL17, 0x40); // LI2LOVOL
reg_write(ES8388_DACCONTROL24, 0x21); // LOUT1VOL
reg_write(ES8388_DACCONTROL25, 0x21); // ROUT1VOL
reg_write(ES8388_DACCONTROL24, 33); // LOUT1VOL balanced noise: 0x18
reg_write(ES8388_DACCONTROL25, 33); // ROUT1VOL balanced noise: 0x18
}
MSH_CMD_EXPORT(estest, test mic loop)

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board/ports/audio/drv_es8388.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2019-07-31 Zero-Free first implementation
*/
#ifndef __DRV_ES8388_H__
#define __DRV_ES8388_H__
/* ES8388 register space */
#define ES8388_CONTROL1 0x00
#define ES8388_CONTROL2 0x01
#define ES8388_CHIPPOWER 0x02
#define ES8388_ADCPOWER 0x03
#define ES8388_DACPOWER 0x04
#define ES8388_CHIPLOPOW1 0x05
#define ES8388_CHIPLOPOW2 0x06
#define ES8388_ANAVOLMANAG 0x07
#define ES8388_MASTERMODE 0x08
#define ES8388_ADCCONTROL1 0x09
#define ES8388_ADCCONTROL2 0x0a
#define ES8388_ADCCONTROL3 0x0b
#define ES8388_ADCCONTROL4 0x0c
#define ES8388_ADCCONTROL5 0x0d
#define ES8388_ADCCONTROL6 0x0e
#define ES8388_ADCCONTROL7 0x0f
#define ES8388_ADCCONTROL8 0x10
#define ES8388_ADCCONTROL9 0x11
#define ES8388_ADCCONTROL10 0x12
#define ES8388_ADCCONTROL11 0x13
#define ES8388_ADCCONTROL12 0x14
#define ES8388_ADCCONTROL13 0x15
#define ES8388_ADCCONTROL14 0x16
#define ES8388_DACCONTROL1 0x17
#define ES8388_DACCONTROL2 0x18
#define ES8388_DACCONTROL3 0x19
#define ES8388_DACCONTROL4 0x1a
#define ES8388_DACCONTROL5 0x1b
#define ES8388_DACCONTROL6 0x1c
#define ES8388_DACCONTROL7 0x1d
#define ES8388_DACCONTROL8 0x1e
#define ES8388_DACCONTROL9 0x1f
#define ES8388_DACCONTROL10 0x20
#define ES8388_DACCONTROL11 0x21
#define ES8388_DACCONTROL12 0x22
#define ES8388_DACCONTROL13 0x23
#define ES8388_DACCONTROL14 0x24
#define ES8388_DACCONTROL15 0x25
#define ES8388_DACCONTROL16 0x26
#define ES8388_DACCONTROL17 0x27
#define ES8388_DACCONTROL18 0x28
#define ES8388_DACCONTROL19 0x29
#define ES8388_DACCONTROL20 0x2a
#define ES8388_DACCONTROL21 0x2b
#define ES8388_DACCONTROL22 0x2c
#define ES8388_DACCONTROL23 0x2d
#define ES8388_DACCONTROL24 0x2e
#define ES8388_DACCONTROL25 0x2f
#define ES8388_DACCONTROL26 0x30
#define ES8388_DACCONTROL27 0x31
#define ES8388_DACCONTROL28 0x32
#define ES8388_DACCONTROL29 0x33
#define ES8388_DACCONTROL30 0x34
enum es8388_mode
{
ES_MODE_NONE = 0x00,
ES_MODE_DAC = 0x01,
ES_MODE_ADC = 0x02,
ES_MODE_DAC_ADC = 0x03,
ES_MODE_LINE = 0x04,
ES_MODE_MAX = 0x06,
};
enum es8388_format
{
ES_FMT_NORMAL = 0,
ES_FMT_LEFT = 1,
ES_FMT_RIGHT = 2,
ES_FMT_DSP = 3,
};
rt_err_t es8388_init(const char *i2c_name, rt_uint16_t pin);
rt_err_t es8388_start(enum es8388_mode mode);
rt_err_t es8388_stop(enum es8388_mode mode);
rt_err_t es8388_fmt_set(enum es8388_mode mode, enum es8388_format fmt);
void es8388_volume_set(rt_uint8_t volume);
rt_uint8_t es8388_volume_get(void);
void es8388_pa_power(rt_bool_t enable);
#endif

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board/ports/audio/drv_mic.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2019-07-31 Zero-Free first implementation
*/
#include <board.h>
#include "drv_es8388.h"
#define DBG_TAG "drv.mic"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#define RX_FIFO_SIZE (1024)
struct mic_device
{
struct rt_audio_device audio;
struct rt_audio_configure record_config;
rt_uint8_t *rx_fifo;
rt_uint8_t volume;
};
static struct mic_device mic_dev = {0};
static rt_uint16_t zero_frame[2] = {0};
static I2S_HandleTypeDef I2S3_Handler = {0};
static DMA_HandleTypeDef I2S3_RXDMA_Handler = {0};
static void I2S3_Init(void)
{
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_I2S;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
HAL_I2S_DeInit(&I2S3_Handler);
I2S3_Handler.Instance = I2S3ext;
I2S3_Handler.Init.Mode = I2S_MODE_SLAVE_RX;
I2S3_Handler.Init.Standard = I2S_STANDARD_PHILIPS;
I2S3_Handler.Init.DataFormat = I2S_DATAFORMAT_16B;
I2S3_Handler.Init.MCLKOutput = I2S_MCLKOUTPUT_ENABLE;
I2S3_Handler.Init.AudioFreq = I2S_AUDIOFREQ_DEFAULT;
I2S3_Handler.Init.CPOL = I2S_CPOL_LOW;
I2S3_Handler.Init.ClockSource = I2S_CLOCK_PLL;
I2S3_Handler.Init.FullDuplexMode = I2S_FULLDUPLEXMODE_ENABLE;
if (HAL_I2S_Init(&I2S3_Handler) != HAL_OK)
{
Error_Handler();
}
SET_BIT(I2S3_Handler.Instance->CR2, SPI_CR2_RXDMAEN);
__HAL_I2S_ENABLE(&I2S3_Handler);
/* Configure DMA used for I2S3 */
__HAL_RCC_DMA1_CLK_ENABLE();
I2S3_RXDMA_Handler.Instance = DMA1_Stream2;
I2S3_RXDMA_Handler.Init.Channel = DMA_CHANNEL_2;
I2S3_RXDMA_Handler.Init.Direction = DMA_PERIPH_TO_MEMORY;
I2S3_RXDMA_Handler.Init.PeriphInc = DMA_PINC_DISABLE;
I2S3_RXDMA_Handler.Init.MemInc = DMA_MINC_ENABLE;
I2S3_RXDMA_Handler.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
I2S3_RXDMA_Handler.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
I2S3_RXDMA_Handler.Init.Mode = DMA_CIRCULAR;
I2S3_RXDMA_Handler.Init.Priority = DMA_PRIORITY_MEDIUM;
I2S3_RXDMA_Handler.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
__HAL_LINKDMA(&I2S3_Handler,hdmarx,I2S3_RXDMA_Handler);
HAL_DMA_DeInit(&I2S3_RXDMA_Handler);
HAL_DMA_Init(&I2S3_RXDMA_Handler);
__HAL_DMA_DISABLE(&I2S3_RXDMA_Handler);
__HAL_DMA_ENABLE_IT(&I2S3_RXDMA_Handler, DMA_IT_TC); /* 开启传输完成中断 */
__HAL_DMA_CLEAR_FLAG(&I2S3_RXDMA_Handler, DMA_FLAG_TCIF2_6);
HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
}
void DMA1_Stream2_IRQHandler(void)
{
rt_audio_rx_done(&mic_dev.audio, &mic_dev.rx_fifo[0], RX_FIFO_SIZE);
HAL_DMA_IRQHandler(&I2S3_RXDMA_Handler);
}
static rt_err_t mic_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps)
{
rt_err_t result = RT_EOK;
struct mic_device *mic_dev;
RT_ASSERT(audio != RT_NULL);
mic_dev = (struct mic_device *)audio->parent.user_data;
switch (caps->main_type)
{
case AUDIO_TYPE_QUERY: /* qurey the types of hw_codec device */
{
switch (caps->sub_type)
{
case AUDIO_TYPE_QUERY:
caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_MIXER;
break;
default:
result = -RT_ERROR;
break;
}
break;
}
case AUDIO_TYPE_INPUT: /* Provide capabilities of INPUT unit */
{
switch (caps->sub_type)
{
case AUDIO_DSP_PARAM:
caps->udata.config.samplerate = mic_dev->record_config.samplerate;
caps->udata.config.channels = mic_dev->record_config.channels;
caps->udata.config.samplebits = mic_dev->record_config.samplebits;
break;
case AUDIO_DSP_SAMPLERATE:
caps->udata.config.samplerate = mic_dev->record_config.samplerate;
break;
case AUDIO_DSP_CHANNELS:
caps->udata.config.channels = mic_dev->record_config.channels;
break;
case AUDIO_DSP_SAMPLEBITS:
caps->udata.config.samplebits = mic_dev->record_config.samplebits;
break;
default:
result = -RT_ERROR;
break;
}
break;
}
case AUDIO_TYPE_MIXER: /* report the Mixer Units */
{
switch (caps->sub_type)
{
case AUDIO_MIXER_QUERY:
caps->udata.mask = AUDIO_MIXER_VOLUME | AUDIO_MIXER_LINE;
break;
case AUDIO_MIXER_VOLUME:
caps->udata.value = mic_dev->volume;
break;
case AUDIO_MIXER_LINE:
break;
default:
result = -RT_ERROR;
break;
}
break;
}
default:
result = -RT_ERROR;
break;
}
return result;
}
static rt_err_t mic_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
{
rt_err_t result = RT_EOK;
struct mic_device *mic_dev;
RT_ASSERT(audio != RT_NULL);
mic_dev = (struct mic_device *)audio->parent.user_data;
switch (caps->main_type)
{
case AUDIO_TYPE_MIXER:
{
switch (caps->sub_type)
{
case AUDIO_MIXER_VOLUME:
{
rt_uint32_t volume = caps->udata.value;
mic_dev->volume = volume;
LOG_D("set volume %d", volume);
break;
}
default:
result = -RT_ERROR;
break;
}
break;
}
case AUDIO_TYPE_INPUT:
{
switch (caps->sub_type)
{
case AUDIO_DSP_PARAM:
{
// SAIA_Frequency_Set(caps->udata.config.samplerate);
HAL_I2S_DMAStop(&I2S3_Handler);
// SAIB_Channels_Set(caps->udata.config.channels);
HAL_I2S_Transmit(&I2S3_Handler, (uint16_t *)&zero_frame[0], 2, 0);
HAL_I2S_Receive_DMA(&I2S3_Handler, (uint16_t *)mic_dev->rx_fifo, RX_FIFO_SIZE / 2);
/* save configs */
mic_dev->record_config.samplerate = caps->udata.config.samplerate;
mic_dev->record_config.channels = caps->udata.config.channels;
mic_dev->record_config.samplebits = caps->udata.config.samplebits;
LOG_D("set samplerate %d", mic_dev->record_config.samplerate);
LOG_D("set channels %d", mic_dev->record_config.channels);
break;
}
case AUDIO_DSP_SAMPLERATE:
{
mic_dev->record_config.samplerate = caps->udata.config.samplerate;
LOG_D("set channels %d", mic_dev->record_config.channels);
break;
}
case AUDIO_DSP_CHANNELS:
{
mic_dev->record_config.channels = caps->udata.config.channels;
LOG_D("set channels %d", mic_dev->record_config.channels);
break;
}
default:
break;
}
break;
}
default:
break;
}
return result;
}
static rt_err_t mic_init(struct rt_audio_device *audio)
{
struct mic_device *mic_dev;
RT_ASSERT(audio != RT_NULL);
mic_dev = (struct mic_device *)audio->parent.user_data;
es8388_init("i2c2", RT_NULL);
I2S3_Init();
LOG_I("ES8388 init success.");
/* set default params */
// SAIB_Channels_Set(mic_dev->record_config.channels);
return RT_EOK;
}
static rt_err_t sound_init(struct rt_audio_device *audio)
{
rt_err_t result = RT_EOK;
struct sound_device *snd_dev;
RT_ASSERT(audio != RT_NULL);
snd_dev = (struct sound_device *)audio->parent.user_data;
I2S3_Init();
es8388_init("i2c2", RT_NULL);
/* set default params */
// I2S_Frequency_Set(snd_dev->replay_config.samplerate);
// SAIA_Channels_Set(snd_dev->replay_config.channels);
return result;
}
static rt_err_t mic_start(struct rt_audio_device *audio, int stream)
{
struct mic_device *mic_dev;
RT_ASSERT(audio != RT_NULL);
mic_dev = (struct mic_device *)audio->parent.user_data;
if (stream == AUDIO_STREAM_RECORD)
{
es8388_start(ES_MODE_ADC);
HAL_I2S_Transmit(&I2S3_Handler, (uint16_t *)&zero_frame[0], 2, 0);
// HAL_I2S_Receive_DMA(&I2S3_Handler, (uint16_t *)mic_dev->rx_fifo, RX_FIFO_SIZE / 2);
while(1)
{
HAL_I2S_Receive(&I2S3_Handler, (uint16_t *)mic_dev->rx_fifo, RX_FIFO_SIZE / 2,10);
for(int i=0;i<RX_FIFO_SIZE;i++)
{
rt_kprintf("%x",mic_dev->rx_fifo[i]);
}
}
}
return RT_EOK;
}
static rt_err_t mic_stop(struct rt_audio_device *audio, int stream)
{
if (stream == AUDIO_STREAM_RECORD)
{
HAL_I2S_DMAStop(&I2S3_Handler);
es8388_stop(ES_MODE_ADC);
LOG_D("mic stop.");
}
return RT_EOK;
}
static struct rt_audio_ops mic_ops =
{
.getcaps = mic_getcaps,
.configure = mic_configure,
.init = mic_init,
.start = mic_start,
.stop = mic_stop,
.transmit = RT_NULL,
.buffer_info = RT_NULL,
};
int rt_hw_mic_init(void)
{
rt_uint8_t *rx_fifo;
if (mic_dev.rx_fifo)
return RT_EOK;
rx_fifo = rt_malloc(RX_FIFO_SIZE);
if (rx_fifo == RT_NULL)
return -RT_ENOMEM;
rt_memset(rx_fifo, 0, RX_FIFO_SIZE);
mic_dev.rx_fifo = rx_fifo;
/* init default configuration */
{
mic_dev.record_config.samplerate = 44100;
mic_dev.record_config.channels = 2;
mic_dev.record_config.samplebits = 16;
mic_dev.volume = 55;
}
/* register sound device */
mic_dev.audio.ops = &mic_ops;
rt_audio_register(&mic_dev.audio, "mic0", RT_DEVICE_FLAG_RDONLY, &mic_dev);
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_mic_init);

514
board/ports/audio/drv_sound.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2019-07-31 Zero-Free first implementation
*/
#include <board.h>
#include "drv_sound.h"
#include "drv_es8388.h"
#define DBG_TAG "drv.sound"
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
#define TX_FIFO_SIZE (2048)
struct sound_device
{
struct rt_audio_device audio;
struct rt_audio_configure replay_config;
rt_uint8_t *tx_fifo;
rt_uint8_t volume;
};
static struct sound_device snd_dev = {0};
static I2S_HandleTypeDef I2S3_Handler = {0};
static DMA_HandleTypeDef I2S3_TXDMA_Handler = {0};
/**
* 采样率计算公式:Fs=I2SxCLK/[256*(2*I2SDIV+ODD)]
* I2SxCLK=(HSE/pllm)*PLLI2SN/PLLI2SR
* 一般HSE=8Mhz
* pllm:在Sys_Clock_Set设置的时候确定，一般是8
* PLLI2SN:一般是192~432
* PLLI2SR:2~7
* I2SDIV:2~255
* ODD:0/1
* I2S分频系数表@pllm=8,HSE=8Mhz,即vco输入频率为1Mhz
* 表格式:采样率/10,PLLI2SN,PLLI2SR,I2SDIV,ODD
*/
const uint16_t I2S_PSC_TBL[][5]=
{
{ 800, 256, 5, 12, 1 }, /* 8Khz采样率 */
{ 1102, 429, 4, 19, 0 }, /* 11.025Khz采样率 */
{ 1600, 213, 2, 13, 0 }, /* 16Khz采样率 */
{ 2205, 429, 4, 9, 1 }, /* 22.05Khz采样率 */
{ 3200, 213, 2, 6, 1 }, /* 32Khz采样率 */
{ 4410, 271, 2, 6, 0 }, /* 44.1Khz采样率 */
{ 4800, 258, 3, 3, 1 }, /* 48Khz采样率 */
{ 8820, 316, 2, 3, 1 }, /* 88.2Khz采样率 */
{ 9600, 344, 2, 3, 1 }, /* 96Khz采样率 */
{ 17640, 361, 2, 2, 0 }, /* 176.4Khz采样率 */
{ 19200, 393, 2, 2, 0 }, /* 192Khz采样率 */
};
static void I2S3_Init(void)
{
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_I2S;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
HAL_I2S_DeInit(&I2S3_Handler);
I2S3_Handler.Instance = SPI3;
I2S3_Handler.Init.Mode = I2S_MODE_MASTER_TX;
I2S3_Handler.Init.Standard = I2S_STANDARD_PHILIPS;
I2S3_Handler.Init.DataFormat = I2S_DATAFORMAT_16B;
I2S3_Handler.Init.MCLKOutput = I2S_MCLKOUTPUT_ENABLE;
I2S3_Handler.Init.AudioFreq = I2S_AUDIOFREQ_44K;
I2S3_Handler.Init.CPOL = I2S_CPOL_LOW;
I2S3_Handler.Init.ClockSource = I2S_CLOCK_PLL;
I2S3_Handler.Init.FullDuplexMode = I2S_FULLDUPLEXMODE_ENABLE;
if (HAL_I2S_Init(&I2S3_Handler) != HAL_OK)
{
Error_Handler();
}
SET_BIT(I2S3_Handler.Instance->CR2, SPI_CR2_TXDMAEN);
__HAL_I2S_ENABLE(&I2S3_Handler);
/* Configure DMA used for I2S3 */
__HAL_RCC_DMA1_CLK_ENABLE();
I2S3_TXDMA_Handler.Instance = DMA1_Stream7;
I2S3_TXDMA_Handler.Init.Channel = DMA_CHANNEL_0;
I2S3_TXDMA_Handler.Init.Direction = DMA_MEMORY_TO_PERIPH;
I2S3_TXDMA_Handler.Init.PeriphInc = DMA_PINC_DISABLE;
I2S3_TXDMA_Handler.Init.MemInc = DMA_MINC_ENABLE;
I2S3_TXDMA_Handler.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
I2S3_TXDMA_Handler.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
I2S3_TXDMA_Handler.Init.Mode = DMA_CIRCULAR;
I2S3_TXDMA_Handler.Init.Priority = DMA_PRIORITY_HIGH;
I2S3_TXDMA_Handler.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
__HAL_LINKDMA(&I2S3_Handler,hdmatx,I2S3_TXDMA_Handler);
HAL_DMA_DeInit(&I2S3_TXDMA_Handler);
HAL_DMA_Init(&I2S3_TXDMA_Handler);
// __HAL_DMA_ENABLE(&I2S3_TXDMA_Handler);
__HAL_DMA_DISABLE(&I2S3_TXDMA_Handler);
__HAL_DMA_ENABLE_IT(&I2S3_TXDMA_Handler, DMA_IT_TC); /* 开启传输完成中断 */
__HAL_DMA_CLEAR_FLAG(&I2S3_TXDMA_Handler, DMA_FLAG_TCIF0_4);
HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);
}
void DMA1_Stream7_IRQHandler(void)
{
rt_audio_tx_complete(&snd_dev.audio);
HAL_DMA_IRQHandler(&I2S3_TXDMA_Handler);
}
//void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
//{
// if (hsai == &SAI1A_Handler)
// {
// rt_audio_tx_complete(&snd_dev.audio);
// }
//}
//void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
//{
// if (hsai == &SAI1A_Handler)
// {
// rt_audio_tx_complete(&snd_dev.audio);
// }
//}
void I2S_Frequency_Set(uint32_t samplerate)
{
// uint8_t i = 0;
// uint32_t tempreg = 0;
// RCC_PeriphCLKInitTypeDef rcc_i2s_clkinit_struct;
// for (i = 0; i < (sizeof(I2S_PSC_TBL) / 10); i++) /* 看看改采样率是否可以支持 */
// {
// if ((samplerate / 10) == I2S_PSC_TBL[i][0])
// {
// break;
// }
// }
// if (i == (sizeof(I2S_PSC_TBL) / 10))
// {
// LOG_E("samplerate not supported.");
// // return 1; /* 找不到 */
// }
// rcc_i2s_clkinit_struct.PeriphClockSelection = RCC_PERIPHCLK_I2S; /* 外设时钟源选择 */
// rcc_i2s_clkinit_struct.PLLI2S.PLLI2SN = (uint32_t)I2S_PSC_TBL[i][1]; /* 设置PLLI2SN */
// rcc_i2s_clkinit_struct.PLLI2S.PLLI2SR = (uint32_t)I2S_PSC_TBL[i][2]; /* 设置PLLI2SR */
// HAL_RCCEx_PeriphCLKConfig(&rcc_i2s_clkinit_struct); /* 设置时钟 */
// RCC->CR |= 1 << 26; /* 开启I2S时钟 */
// while((RCC->CR & 1 << 27) == 0); /* 等待I2S时钟开启成功. */
// tempreg = I2S_PSC_TBL[i][3] << 0; /* 设置I2SDIV */
// tempreg |= I2S_PSC_TBL[i][4] << 8; /* 设置ODD位 */
// tempreg |= 1 << 9; /* 使能MCKOE位,输出MCK */
// I2S3_Handler.Instance->I2SPR = tempreg; /* 设置I2SPR寄存器 */
// return 0;
// RCC_PeriphCLKInitTypeDef PeriphClkInit;
// HAL_RCCEx_GetPeriphCLKConfig(&PeriphClkInit);
// if ((frequency == SAI_AUDIO_FREQUENCY_11K) || (frequency == SAI_AUDIO_FREQUENCY_22K) || (frequency == SAI_AUDIO_FREQUENCY_44K))
// {
// /* Configure and enable PLLSAI1 clock to generate 45.714286MHz */
// PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI1;
// PeriphClkInit.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLLSAI2;
// PeriphClkInit.PLLSAI2.PLLSAI2Source = RCC_PLLSOURCE_HSE;
// PeriphClkInit.PLLSAI2.PLLSAI2M = 1;
// PeriphClkInit.PLLSAI2.PLLSAI2N = 40;
// PeriphClkInit.PLLSAI2.PLLSAI2ClockOut = RCC_PLLSAI2_SAI2CLK;
// HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
// }
// else
// {
// /* Configure and enable PLLSAI1 clock to generate 49.142857MHz */
// PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI1;
// PeriphClkInit.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLLSAI2;
// PeriphClkInit.PLLSAI2.PLLSAI2Source = RCC_PLLSOURCE_HSE;
// PeriphClkInit.PLLSAI2.PLLSAI2M = 1;
// PeriphClkInit.PLLSAI2.PLLSAI2N = 43;
// PeriphClkInit.PLLSAI2.PLLSAI2P = RCC_PLLP_DIV7;
// PeriphClkInit.PLLSAI2.PLLSAI2ClockOut = RCC_PLLSAI2_SAI2CLK;
// HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
// }
// /* Disable SAI peripheral to allow access to SAI internal registers */
// __HAL_SAI_DISABLE(&SAI1A_Handler);
// /* Update the SAI audio frequency configuration */
// SAI1A_Handler.Init.AudioFrequency = frequency;
// HAL_SAI_Init(&SAI1A_Handler);
// /* Enable SAI peripheral to generate MCLK */
// __HAL_SAI_ENABLE(&SAI1A_Handler);
}
void SAIA_Channels_Set(uint8_t channels)
{
// if (channels == 1)
// {
// SAI1A_Handler.Init.MonoStereoMode = SAI_MONOMODE;
// }
// else
// {
// SAI1A_Handler.Init.MonoStereoMode = SAI_STEREOMODE;
// }
// __HAL_SAI_DISABLE(&SAI1A_Handler);
// HAL_SAI_Init(&SAI1A_Handler);
// __HAL_SAI_ENABLE(&SAI1A_Handler);
}
/**
* RT-Thread Audio Device Driver Interface
*/
static rt_err_t sound_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps)
{
rt_err_t result = RT_EOK;
struct sound_device *snd_dev;
RT_ASSERT(audio != RT_NULL);
snd_dev = (struct sound_device *)audio->parent.user_data;
switch (caps->main_type)
{
case AUDIO_TYPE_QUERY: /* qurey the types of hw_codec device */
{
switch (caps->sub_type)
{
case AUDIO_TYPE_QUERY:
caps->udata.mask = AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER;
break;
default:
result = -RT_ERROR;
break;
}
break;
}
case AUDIO_TYPE_OUTPUT: /* Provide capabilities of OUTPUT unit */
{
switch (caps->sub_type)
{
case AUDIO_DSP_PARAM:
caps->udata.config.samplerate = snd_dev->replay_config.samplerate;
caps->udata.config.channels = snd_dev->replay_config.channels;
caps->udata.config.samplebits = snd_dev->replay_config.samplebits;
break;
case AUDIO_DSP_SAMPLERATE:
caps->udata.config.samplerate = snd_dev->replay_config.samplerate;
break;
case AUDIO_DSP_CHANNELS:
caps->udata.config.channels = snd_dev->replay_config.channels;
break;
case AUDIO_DSP_SAMPLEBITS:
caps->udata.config.samplebits = snd_dev->replay_config.samplebits;
break;
default:
result = -RT_ERROR;
break;
}
break;
}
case AUDIO_TYPE_MIXER: /* report the Mixer Units */
{
switch (caps->sub_type)
{
case AUDIO_MIXER_QUERY:
caps->udata.mask = AUDIO_MIXER_VOLUME;
break;
case AUDIO_MIXER_VOLUME:
caps->udata.value = es8388_volume_get();
break;
default:
result = -RT_ERROR;
break;
}
break;
}
default:
result = -RT_ERROR;
break;
}
return result;
}
static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
{
rt_err_t result = RT_EOK;
struct sound_device *snd_dev;
RT_ASSERT(audio != RT_NULL);
snd_dev = (struct sound_device *)audio->parent.user_data;
switch (caps->main_type)
{
case AUDIO_TYPE_MIXER:
{
switch (caps->sub_type)
{
case AUDIO_MIXER_VOLUME:
{
rt_uint8_t volume = caps->udata.value;
es8388_volume_set(volume);
snd_dev->volume = volume;
LOG_D("set volume %d", volume);
break;
}
default:
result = -RT_ERROR;
break;
}
break;
}
case AUDIO_TYPE_OUTPUT:
{
switch (caps->sub_type)
{
case AUDIO_DSP_PARAM:
{
/* set samplerate */
I2S_Frequency_Set(caps->udata.config.samplerate);
/* set channels */
SAIA_Channels_Set(caps->udata.config.channels);
/* save configs */
snd_dev->replay_config.samplerate = caps->udata.config.samplerate;
snd_dev->replay_config.channels = caps->udata.config.channels;
snd_dev->replay_config.samplebits = caps->udata.config.samplebits;
LOG_D("set samplerate %d", snd_dev->replay_config.samplerate);
break;
}
case AUDIO_DSP_SAMPLERATE:
{
I2S_Frequency_Set(caps->udata.config.samplerate);
snd_dev->replay_config.samplerate = caps->udata.config.samplerate;
LOG_D("set samplerate %d", snd_dev->replay_config.samplerate);
break;
}
case AUDIO_DSP_CHANNELS:
{
SAIA_Channels_Set(caps->udata.config.channels);
snd_dev->replay_config.channels = caps->udata.config.channels;
LOG_D("set channels %d", snd_dev->replay_config.channels);
break;
}
case AUDIO_DSP_SAMPLEBITS:
{
/* not support */
snd_dev->replay_config.samplebits = caps->udata.config.samplebits;
break;
}
default:
result = -RT_ERROR;
break;
}
break;
}
default:
break;
}
return result;
}
static rt_err_t sound_init(struct rt_audio_device *audio)
{
rt_err_t result = RT_EOK;
struct sound_device *snd_dev;
RT_ASSERT(audio != RT_NULL);
snd_dev = (struct sound_device *)audio->parent.user_data;
es8388_init("i2c2", RT_NULL);
I2S3_Init();
LOG_I("ES8388 init success.");
/* set default params */
I2S_Frequency_Set(snd_dev->replay_config.samplerate);
SAIA_Channels_Set(snd_dev->replay_config.channels);
return result;
}
static rt_err_t sound_start(struct rt_audio_device *audio, int stream)
{
struct sound_device *snd_dev;
RT_ASSERT(audio != RT_NULL);
snd_dev = (struct sound_device *)audio->parent.user_data;
if (stream == AUDIO_STREAM_REPLAY)
{
LOG_D("sound start.");
es8388_start(ES_MODE_DAC);
HAL_I2S_Transmit_DMA(&I2S3_Handler, (uint16_t*)snd_dev->tx_fifo, TX_FIFO_SIZE / 2);
}
return RT_EOK;
}
static rt_err_t sound_stop(struct rt_audio_device *audio, int stream)
{
RT_ASSERT(audio != RT_NULL);
if (stream == AUDIO_STREAM_REPLAY)
{
HAL_I2S_DMAStop(&I2S3_Handler);
es8388_stop(ES_MODE_DAC);
LOG_D("sound stop.");
}
return RT_EOK;
}
static void sound_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info)
{
struct sound_device *snd_dev;
RT_ASSERT(audio != RT_NULL);
snd_dev = (struct sound_device *)audio->parent.user_data;
/**
* TX_FIFO
* +----------------+----------------+
* | block1 | block2 |
* +----------------+----------------+
* \ block_size /
*/
info->buffer = snd_dev->tx_fifo;
info->total_size = TX_FIFO_SIZE;
info->block_size = TX_FIFO_SIZE / 2;
info->block_count = 2;
}
static struct rt_audio_ops snd_ops =
{
.getcaps = sound_getcaps,
.configure = sound_configure,
.init = sound_init,
.start = sound_start,
.stop = sound_stop,
.transmit = RT_NULL,
.buffer_info = sound_buffer_info,
};
int rt_hw_sound_init(void)
{
rt_uint8_t *tx_fifo;
if (snd_dev.tx_fifo)
return RT_EOK;
tx_fifo = rt_malloc(TX_FIFO_SIZE);
if (tx_fifo == RT_NULL)
return -RT_ENOMEM;
rt_memset(tx_fifo, 0, TX_FIFO_SIZE);
snd_dev.tx_fifo = tx_fifo;
/* init default configuration */
{
snd_dev.replay_config.samplerate = 44100;
snd_dev.replay_config.channels = 2;
snd_dev.replay_config.samplebits = 16;
snd_dev.volume = 55;
}
/* register sound device */
snd_dev.audio.ops = &snd_ops;
rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev);
return RT_EOK;
}
// INIT_DEVICE_EXPORT(rt_hw_sound_init);

16
board/ports/audio/drv_sound.h Normal file
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@@ -0,0 +1,16 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2019-07-31 Zero-Free first implementation
*/
#ifndef __DRV_SOUND_H__
#define __DRV_SOUND_H__
int rt_hw_sound_init(void);
int rt_hw_mic_init(void);
#endif