729 lines
25 KiB
C
729 lines
25 KiB
C
/*
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* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_flexio_uart.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*<! @brief uart transfer state. */
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enum _flexio_uart_transfer_states
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{
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kFLEXIO_UART_TxIdle, /* TX idle. */
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kFLEXIO_UART_TxBusy, /* TX busy. */
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kFLEXIO_UART_RxIdle, /* RX idle. */
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kFLEXIO_UART_RxBusy /* RX busy. */
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};
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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extern const clock_ip_name_t s_flexioClocks[];
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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extern FLEXIO_Type *const s_flexioBases[];
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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extern uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
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/*!
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* @brief Get the length of received data in RX ring buffer.
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*
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* @param handle FLEXIO UART handle pointer.
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* @return Length of received data in RX ring buffer.
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*/
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static size_t FLEXIO_UART_TransferGetRxRingBufferLength(flexio_uart_handle_t *handle);
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/*!
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* @brief Check whether the RX ring buffer is full.
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*
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* @param handle FLEXIO UART handle pointer.
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* @retval true RX ring buffer is full.
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* @retval false RX ring buffer is not full.
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*/
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static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle);
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/*******************************************************************************
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* Codes
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******************************************************************************/
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uint32_t FLEXIO_UART_GetInstance(FLEXIO_UART_Type *base)
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{
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return FLEXIO_GetInstance(base->flexioBase);
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}
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static size_t FLEXIO_UART_TransferGetRxRingBufferLength(flexio_uart_handle_t *handle)
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{
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size_t size;
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if (handle->rxRingBufferTail > handle->rxRingBufferHead)
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{
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size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
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}
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else
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{
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size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
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}
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return size;
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}
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static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle)
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{
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bool full;
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if (FLEXIO_UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
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{
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full = true;
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}
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else
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{
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full = false;
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}
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return full;
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}
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status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz)
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{
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assert(base && userConfig);
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flexio_shifter_config_t shifterConfig;
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flexio_timer_config_t timerConfig;
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uint32_t ctrlReg = 0;
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uint16_t timerDiv = 0;
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uint16_t timerCmp = 0;
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status_t result = kStatus_Success;
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/* Clear the shifterConfig & timerConfig struct. */
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memset(&shifterConfig, 0, sizeof(shifterConfig));
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memset(&timerConfig, 0, sizeof(timerConfig));
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate flexio clock. */
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CLOCK_EnableClock(s_flexioClocks[FLEXIO_UART_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Configure FLEXIO UART */
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ctrlReg = base->flexioBase->CTRL;
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ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
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ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) |
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FLEXIO_CTRL_FLEXEN(userConfig->enableUart));
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if (!userConfig->enableInDoze)
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{
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ctrlReg |= FLEXIO_CTRL_DOZEN_MASK;
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}
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base->flexioBase->CTRL = ctrlReg;
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/* Do hardware configuration. */
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/* 1. Configure the shifter 0 for tx. */
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shifterConfig.timerSelect = base->timerIndex[0];
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
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shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
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shifterConfig.pinSelect = base->TxPinIndex;
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shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
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FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
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/*2. Configure the timer 0 for tx. */
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
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timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
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timerConfig.pinSelect = base->TxPinIndex;
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timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
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timerConfig.timerReset = kFLEXIO_TimerResetNever;
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timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
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timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
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timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
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timerDiv = srcClock_Hz / userConfig->baudRate_Bps;
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timerDiv = timerDiv / 2 - 1;
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if (timerDiv > 0xFFU)
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{
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result = kStatus_InvalidArgument;
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}
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timerCmp = ((uint32_t)(userConfig->bitCountPerChar * 2 - 1)) << 8U;
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timerCmp |= timerDiv;
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timerConfig.timerCompare = timerCmp;
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FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
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/* 3. Configure the shifter 1 for rx. */
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shifterConfig.timerSelect = base->timerIndex[1];
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
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shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
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shifterConfig.pinSelect = base->RxPinIndex;
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shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
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FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
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/* 4. Configure the timer 1 for rx. */
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal;
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timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
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timerConfig.pinSelect = base->RxPinIndex;
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timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
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timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
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timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge;
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timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge;
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timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
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timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
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timerConfig.timerCompare = timerCmp;
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FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
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return result;
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}
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void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)
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{
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base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
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base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0;
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base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0;
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base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0;
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base->flexioBase->TIMCFG[base->timerIndex[0]] = 0;
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base->flexioBase->TIMCMP[base->timerIndex[0]] = 0;
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base->flexioBase->TIMCTL[base->timerIndex[0]] = 0;
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base->flexioBase->TIMCFG[base->timerIndex[1]] = 0;
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base->flexioBase->TIMCMP[base->timerIndex[1]] = 0;
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base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
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/* Clear the shifter flag. */
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base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]);
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base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]);
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/* Clear the timer flag. */
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base->flexioBase->TIMSTAT = (1U << base->timerIndex[0]);
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base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]);
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}
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void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)
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{
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assert(userConfig);
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userConfig->enableUart = true;
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userConfig->enableInDoze = false;
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userConfig->enableInDebug = true;
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userConfig->enableFastAccess = false;
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/* Default baud rate 115200. */
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userConfig->baudRate_Bps = 115200U;
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/* Default bit count at 8. */
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userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar;
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}
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void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
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{
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if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable)
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{
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FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]);
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}
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if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable)
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{
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FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]);
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}
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}
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void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
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{
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if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable)
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{
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FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]);
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}
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if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable)
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{
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FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]);
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}
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}
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uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)
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{
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uint32_t status = 0;
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status =
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((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]);
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status |=
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(((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1]))
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<< 1U);
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status |=
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(((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1]))
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<< 2U);
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return status;
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}
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void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)
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{
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if (mask & kFLEXIO_UART_TxDataRegEmptyFlag)
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{
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FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]);
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}
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if (mask & kFLEXIO_UART_RxDataRegFullFlag)
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{
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FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]);
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}
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if (mask & kFLEXIO_UART_RxOverRunFlag)
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{
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FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
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}
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}
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void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize)
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{
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assert(txData);
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assert(txSize);
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while (txSize--)
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{
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/* Wait until data transfer complete. */
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while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))
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{
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}
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base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *txData++;
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}
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}
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void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize)
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{
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assert(rxData);
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assert(rxSize);
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while (rxSize--)
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{
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/* Wait until data transfer complete. */
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while (!(FLEXIO_UART_GetStatusFlags(base) & kFLEXIO_UART_RxDataRegFullFlag))
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{
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}
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*rxData++ = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]];
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}
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}
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status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base,
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flexio_uart_handle_t *handle,
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flexio_uart_transfer_callback_t callback,
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void *userData)
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{
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assert(handle);
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IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
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/* Zero the handle. */
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memset(handle, 0, sizeof(*handle));
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/* Set the TX/RX state. */
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handle->rxState = kFLEXIO_UART_RxIdle;
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handle->txState = kFLEXIO_UART_TxIdle;
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/* Set the callback and user data. */
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handle->callback = callback;
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handle->userData = userData;
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/* Enable interrupt in NVIC. */
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EnableIRQ(flexio_irqs[FLEXIO_UART_GetInstance(base)]);
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/* Save the context in global variables to support the double weak mechanism. */
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return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ);
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}
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void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base,
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flexio_uart_handle_t *handle,
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uint8_t *ringBuffer,
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size_t ringBufferSize)
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{
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assert(handle);
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/* Setup the ringbuffer address */
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if (ringBuffer)
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{
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handle->rxRingBuffer = ringBuffer;
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handle->rxRingBufferSize = ringBufferSize;
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handle->rxRingBufferHead = 0U;
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handle->rxRingBufferTail = 0U;
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/* Enable the interrupt to accept the data when user need the ring buffer. */
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FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
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}
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}
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void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
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{
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assert(handle);
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if (handle->rxState == kFLEXIO_UART_RxIdle)
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{
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FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
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}
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handle->rxRingBuffer = NULL;
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handle->rxRingBufferSize = 0U;
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handle->rxRingBufferHead = 0U;
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handle->rxRingBufferTail = 0U;
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}
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status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base,
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flexio_uart_handle_t *handle,
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flexio_uart_transfer_t *xfer)
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{
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status_t status;
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/* Return error if xfer invalid. */
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if ((0U == xfer->dataSize) || (NULL == xfer->data))
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{
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return kStatus_InvalidArgument;
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}
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/* Return error if current TX busy. */
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if (kFLEXIO_UART_TxBusy == handle->txState)
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{
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status = kStatus_FLEXIO_UART_TxBusy;
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}
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else
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{
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handle->txData = xfer->data;
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handle->txDataSize = xfer->dataSize;
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handle->txDataSizeAll = xfer->dataSize;
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handle->txState = kFLEXIO_UART_TxBusy;
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/* Enable transmiter interrupt. */
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FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable);
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status = kStatus_Success;
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}
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return status;
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}
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void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
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{
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/* Disable the transmitter and disable the interrupt. */
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FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable);
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handle->txDataSize = 0;
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handle->txState = kFLEXIO_UART_TxIdle;
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}
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status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
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{
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assert(handle);
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assert(count);
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if (kFLEXIO_UART_TxIdle == handle->txState)
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{
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return kStatus_NoTransferInProgress;
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}
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|
|
*count = handle->txDataSizeAll - handle->txDataSize;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
|
|
flexio_uart_handle_t *handle,
|
|
flexio_uart_transfer_t *xfer,
|
|
size_t *receivedBytes)
|
|
{
|
|
uint32_t i;
|
|
status_t status;
|
|
/* How many bytes to copy from ring buffer to user memory. */
|
|
size_t bytesToCopy = 0U;
|
|
/* How many bytes to receive. */
|
|
size_t bytesToReceive;
|
|
/* How many bytes currently have received. */
|
|
size_t bytesCurrentReceived;
|
|
|
|
/* Return error if xfer invalid. */
|
|
if ((0U == xfer->dataSize) || (NULL == xfer->data))
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* How to get data:
|
|
1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
|
|
to uart handle, enable interrupt to store received data to xfer->data. When
|
|
all data received, trigger callback.
|
|
2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
|
|
If there are enough data in ring buffer, copy them to xfer->data and return.
|
|
If there are not enough data in ring buffer, copy all of them to xfer->data,
|
|
save the xfer->data remained empty space to uart handle, receive data
|
|
to this empty space and trigger callback when finished. */
|
|
|
|
if (kFLEXIO_UART_RxBusy == handle->rxState)
|
|
{
|
|
status = kStatus_FLEXIO_UART_RxBusy;
|
|
}
|
|
else
|
|
{
|
|
bytesToReceive = xfer->dataSize;
|
|
bytesCurrentReceived = 0U;
|
|
|
|
/* If RX ring buffer is used. */
|
|
if (handle->rxRingBuffer)
|
|
{
|
|
/* Disable FLEXIO_UART RX IRQ, protect ring buffer. */
|
|
FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
|
|
|
|
/* How many bytes in RX ring buffer currently. */
|
|
bytesToCopy = FLEXIO_UART_TransferGetRxRingBufferLength(handle);
|
|
|
|
if (bytesToCopy)
|
|
{
|
|
bytesToCopy = MIN(bytesToReceive, bytesToCopy);
|
|
|
|
bytesToReceive -= bytesToCopy;
|
|
|
|
/* Copy data from ring buffer to user memory. */
|
|
for (i = 0U; i < bytesToCopy; i++)
|
|
{
|
|
xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
|
|
|
|
/* Wrap to 0. Not use modulo (%) because it might be large and slow. */
|
|
if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
|
|
{
|
|
handle->rxRingBufferTail = 0U;
|
|
}
|
|
else
|
|
{
|
|
handle->rxRingBufferTail++;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* If ring buffer does not have enough data, still need to read more data. */
|
|
if (bytesToReceive)
|
|
{
|
|
/* No data in ring buffer, save the request to UART handle. */
|
|
handle->rxData = xfer->data + bytesCurrentReceived;
|
|
handle->rxDataSize = bytesToReceive;
|
|
handle->rxDataSizeAll = bytesToReceive;
|
|
handle->rxState = kFLEXIO_UART_RxBusy;
|
|
}
|
|
|
|
/* Enable FLEXIO_UART RX IRQ if previously enabled. */
|
|
FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
|
|
}
|
|
/* Ring buffer not used. */
|
|
else
|
|
{
|
|
handle->rxData = xfer->data + bytesCurrentReceived;
|
|
handle->rxDataSize = bytesToReceive;
|
|
handle->rxDataSizeAll = bytesToReceive;
|
|
handle->rxState = kFLEXIO_UART_RxBusy;
|
|
|
|
/* Enable RX interrupt. */
|
|
FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
|
|
}
|
|
|
|
/* Return the how many bytes have read. */
|
|
if (receivedBytes)
|
|
{
|
|
*receivedBytes = bytesCurrentReceived;
|
|
}
|
|
|
|
status = kStatus_Success;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
|
|
{
|
|
/* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
|
|
if (!handle->rxRingBuffer)
|
|
{
|
|
/* Disable RX interrupt. */
|
|
FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
|
|
}
|
|
|
|
handle->rxDataSize = 0U;
|
|
handle->rxState = kFLEXIO_UART_RxIdle;
|
|
}
|
|
|
|
status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
|
|
{
|
|
assert(handle);
|
|
assert(count);
|
|
|
|
if (kFLEXIO_UART_RxIdle == handle->rxState)
|
|
{
|
|
return kStatus_NoTransferInProgress;
|
|
}
|
|
|
|
*count = handle->rxDataSizeAll - handle->rxDataSize;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)
|
|
{
|
|
uint8_t count = 1;
|
|
FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType;
|
|
flexio_uart_handle_t *handle = (flexio_uart_handle_t *)uartHandle;
|
|
|
|
/* Read the status back. */
|
|
uint8_t status = FLEXIO_UART_GetStatusFlags(base);
|
|
|
|
/* If RX overrun. */
|
|
if (kFLEXIO_UART_RxOverRunFlag & status)
|
|
{
|
|
/* Clear Overrun flag. */
|
|
FLEXIO_UART_ClearStatusFlags(base, kFLEXIO_UART_RxOverRunFlag);
|
|
|
|
/* Trigger callback. */
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_FLEXIO_UART_RxHardwareOverrun, handle->userData);
|
|
}
|
|
}
|
|
|
|
/* Receive data register full */
|
|
if ((kFLEXIO_UART_RxDataRegFullFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[1])))
|
|
{
|
|
/* If handle->rxDataSize is not 0, first save data to handle->rxData. */
|
|
if (handle->rxDataSize)
|
|
{
|
|
/* Using non block API to read the data from the registers. */
|
|
FLEXIO_UART_ReadByte(base, handle->rxData);
|
|
handle->rxDataSize--;
|
|
handle->rxData++;
|
|
count--;
|
|
|
|
/* If all the data required for upper layer is ready, trigger callback. */
|
|
if (!handle->rxDataSize)
|
|
{
|
|
handle->rxState = kFLEXIO_UART_RxIdle;
|
|
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (handle->rxRingBuffer)
|
|
{
|
|
if (count)
|
|
{
|
|
/* If RX ring buffer is full, trigger callback to notify over run. */
|
|
if (FLEXIO_UART_TransferIsRxRingBufferFull(handle))
|
|
{
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_FLEXIO_UART_RxRingBufferOverrun, handle->userData);
|
|
}
|
|
}
|
|
|
|
/* If ring buffer is still full after callback function, the oldest data is overrided. */
|
|
if (FLEXIO_UART_TransferIsRxRingBufferFull(handle))
|
|
{
|
|
/* Increase handle->rxRingBufferTail to make room for new data. */
|
|
if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
|
|
{
|
|
handle->rxRingBufferTail = 0U;
|
|
}
|
|
else
|
|
{
|
|
handle->rxRingBufferTail++;
|
|
}
|
|
}
|
|
|
|
/* Read data. */
|
|
handle->rxRingBuffer[handle->rxRingBufferHead] = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]];
|
|
|
|
/* Increase handle->rxRingBufferHead. */
|
|
if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
|
|
{
|
|
handle->rxRingBufferHead = 0U;
|
|
}
|
|
else
|
|
{
|
|
handle->rxRingBufferHead++;
|
|
}
|
|
}
|
|
}
|
|
/* If no receive requst pending, stop RX interrupt. */
|
|
else if (!handle->rxDataSize)
|
|
{
|
|
FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
|
|
}
|
|
else
|
|
{
|
|
}
|
|
}
|
|
|
|
/* Send data register empty and the interrupt is enabled. */
|
|
if ((kFLEXIO_UART_TxDataRegEmptyFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[0])))
|
|
{
|
|
if (handle->txDataSize)
|
|
{
|
|
/* Using non block API to write the data to the registers. */
|
|
FLEXIO_UART_WriteByte(base, handle->txData);
|
|
handle->txData++;
|
|
handle->txDataSize--;
|
|
count--;
|
|
|
|
/* If all the data are written to data register, TX finished. */
|
|
if (!handle->txDataSize)
|
|
{
|
|
handle->txState = kFLEXIO_UART_TxIdle;
|
|
|
|
/* Disable TX register empty interrupt. */
|
|
FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable);
|
|
|
|
/* Trigger callback. */
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_FLEXIO_UART_TxIdle, handle->userData);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|