298 lines
10 KiB
C
298 lines
10 KiB
C
/*
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* Copyright (c) 2017, NXP Semiconductors, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_elcdif.h"
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get instance number for ELCDIF module.
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*
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* @param base ELCDIF peripheral base address
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*/
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static uint32_t ELCDIF_GetInstance(LCDIF_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to ELCDIF bases for each instance. */
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static LCDIF_Type *const s_elcdifBases[] = LCDIF_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to eLCDIF apb_clk for each instance. */
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static const clock_ip_name_t s_elcdifApbClocks[] = LCDIF_CLOCKS;
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#if defined(LCDIF_PERIPH_CLOCKS)
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/*! @brief Pointers to eLCDIF pix_clk for each instance. */
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static const clock_ip_name_t s_elcdifPixClocks[] = LCDIF_PERIPH_CLOCKS;
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#endif
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*! @brief The control register value to select different pixel format. */
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elcdif_pixel_format_reg_t s_pixelFormatReg[] = {
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/* kELCDIF_PixelFormatRAW8 */
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{/* Register CTRL. */
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LCDIF_CTRL_WORD_LENGTH(1U),
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/* Register CTRL1. */
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LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)},
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/* kELCDIF_PixelFormatRGB565 */
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{/* Register CTRL. */
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LCDIF_CTRL_WORD_LENGTH(0U),
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/* Register CTRL1. */
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LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)},
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/* kELCDIF_PixelFormatRGB666 */
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{/* Register CTRL. */
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LCDIF_CTRL_WORD_LENGTH(3U) | LCDIF_CTRL_DATA_FORMAT_24_BIT(1U),
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/* Register CTRL1. */
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LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)},
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/* kELCDIF_PixelFormatXRGB8888 */
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{/* Register CTRL. 24-bit. */
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LCDIF_CTRL_WORD_LENGTH(3U),
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/* Register CTRL1. */
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LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)},
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/* kELCDIF_PixelFormatRGB888 */
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{/* Register CTRL. 24-bit. */
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LCDIF_CTRL_WORD_LENGTH(3U),
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/* Register CTRL1. */
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LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)},
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};
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/*******************************************************************************
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* Codes
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******************************************************************************/
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static uint32_t ELCDIF_GetInstance(LCDIF_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_elcdifBases); instance++)
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{
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if (s_elcdifBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_elcdifBases));
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return instance;
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}
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void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config)
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{
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assert(config);
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assert(config->pixelFormat < ARRAY_SIZE(s_pixelFormatReg));
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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uint32_t instance = ELCDIF_GetInstance(base);
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/* Enable the clock. */
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CLOCK_EnableClock(s_elcdifApbClocks[instance]);
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#if defined(LCDIF_PERIPH_CLOCKS)
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CLOCK_EnableClock(s_elcdifPixClocks[instance]);
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#endif
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Reset. */
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ELCDIF_Reset(base);
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base->CTRL = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl | (uint32_t)(config->dataBus) |
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LCDIF_CTRL_DOTCLK_MODE_MASK | /* RGB mode. */
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LCDIF_CTRL_BYPASS_COUNT_MASK | /* Keep RUN bit set. */
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LCDIF_CTRL_MASTER_MASK;
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base->CTRL1 = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl1;
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base->TRANSFER_COUNT = ((uint32_t)config->panelHeight << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT) |
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((uint32_t)config->panelWidth << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT);
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base->VDCTRL0 = LCDIF_VDCTRL0_ENABLE_PRESENT_MASK | /* Data enable signal. */
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LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK | /* VSYNC period in the unit of display clock. */
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LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK | /* VSYNC pulse width in the unit of display clock. */
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(uint32_t)config->polarityFlags | (uint32_t)config->vsw;
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base->VDCTRL1 = config->vsw + config->panelHeight + config->vfp + config->vbp;
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base->VDCTRL2 = ((uint32_t)config->hsw << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT) |
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((uint32_t)(config->hfp + config->hbp + config->panelWidth + config->hsw))
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<< LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT;
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base->VDCTRL3 = (((uint32_t)config->hbp + config->hsw) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT) |
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(((uint32_t)config->vbp + config->vsw) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT);
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base->VDCTRL4 = LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK |
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((uint32_t)config->panelWidth << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT);
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base->CUR_BUF = config->bufferAddr;
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base->NEXT_BUF = config->bufferAddr;
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}
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void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
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{
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assert(config);
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config->panelWidth = 480U;
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config->panelHeight = 272U;
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config->hsw = 41;
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config->hfp = 4;
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config->hbp = 8;
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config->vsw = 10;
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config->vfp = 4;
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config->vbp = 2;
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config->polarityFlags = kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveLow |
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kELCDIF_DriveDataOnFallingClkEdge;
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config->bufferAddr = 0U;
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config->pixelFormat = kELCDIF_PixelFormatRGB888;
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config->dataBus = kELCDIF_DataBus24Bit;
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}
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void ELCDIF_Deinit(LCDIF_Type *base)
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{
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ELCDIF_Reset(base);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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uint32_t instance = ELCDIF_GetInstance(base);
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/* Disable the clock. */
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#if defined(LCDIF_PERIPH_CLOCKS)
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CLOCK_DisableClock(s_elcdifPixClocks[instance]);
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#endif
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CLOCK_DisableClock(s_elcdifApbClocks[instance]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void ELCDIF_RgbModeStop(LCDIF_Type *base)
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{
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base->CTRL_CLR = LCDIF_CTRL_DOTCLK_MODE_MASK;
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/* Wait for data transfer finished. */
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while (base->CTRL & LCDIF_CTRL_DOTCLK_MODE_MASK)
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{
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}
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}
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void ELCDIF_Reset(LCDIF_Type *base)
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{
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volatile uint32_t i = 0x100;
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/* Disable the clock gate. */
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base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK;
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/* Confirm the clock gate is disabled. */
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while (base->CTRL & LCDIF_CTRL_CLKGATE_MASK)
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{
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}
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/* Reset the block. */
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base->CTRL_SET = LCDIF_CTRL_SFTRST_MASK;
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/* Confirm the reset bit is set. */
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while (!(base->CTRL & LCDIF_CTRL_SFTRST_MASK))
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{
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}
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/* Delay for the reset. */
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while (i--)
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{
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}
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/* Bring the module out of reset. */
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base->CTRL_CLR = LCDIF_CTRL_SFTRST_MASK;
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/* Disable the clock gate. */
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base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK;
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}
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#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
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void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config)
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{
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assert(config);
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base->AS_CTRL = (base->AS_CTRL & ~LCDIF_AS_CTRL_FORMAT_MASK) | LCDIF_AS_CTRL_FORMAT(config->pixelFormat);
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base->AS_BUF = config->bufferAddr;
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base->AS_NEXT_BUF = config->bufferAddr;
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}
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void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config)
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{
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assert(config);
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uint32_t reg;
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reg = base->AS_CTRL;
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reg &= ~(LCDIF_AS_CTRL_ALPHA_INVERT_MASK | LCDIF_AS_CTRL_ROP_MASK | LCDIF_AS_CTRL_ALPHA_MASK |
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LCDIF_AS_CTRL_ALPHA_CTRL_MASK);
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reg |= (LCDIF_AS_CTRL_ROP(config->ropMode) | LCDIF_AS_CTRL_ALPHA(config->alpha) |
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LCDIF_AS_CTRL_ALPHA_CTRL(config->alphaMode));
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if (config->invertAlpha)
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{
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reg |= LCDIF_AS_CTRL_ALPHA_INVERT_MASK;
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}
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base->AS_CTRL = reg;
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}
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#endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */
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#if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT)
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status_t ELCDIF_UpdateLut(
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LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count)
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{
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volatile uint32_t *regLutAddr;
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volatile uint32_t *regLutData;
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uint32_t i;
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/* Only has 256 entries. */
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if (startIndex + count > ELCDIF_LUT_ENTRY_NUM)
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{
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return kStatus_InvalidArgument;
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}
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if (kELCDIF_Lut0 == lut)
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{
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regLutAddr = &(base->LUT0_ADDR);
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regLutData = &(base->LUT0_DATA);
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}
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else
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{
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regLutAddr = &(base->LUT1_ADDR);
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regLutData = &(base->LUT1_DATA);
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}
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*regLutAddr = startIndex;
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for (i = 0; i < count; i++)
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{
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*regLutData = lutData[i];
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for (volatile uint32_t j = 0; j < 0x80; j++)
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{
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}
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}
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return kStatus_Success;
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}
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#endif /* FSL_FEATURE_LCDIF_HAS_LUT */
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