259 lines
12 KiB
C
259 lines
12 KiB
C
/*
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* @brief GPDMA Registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __GPDMA_001_H_
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#define __GPDMA_001_H_
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#include "sys_config.h"
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup IP_GPDMA_001 IP: GPDMA register block and driver
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* @ingroup IP_Drivers
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* General Purpose DMA
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* @{
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*/
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/**
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* @brief GPDMA Channel register block structure
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*/
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typedef struct {
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__IO uint32_t SRCADDR; /*!< DMA Channel Source Address Register */
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__IO uint32_t DESTADDR; /*!< DMA Channel Destination Address Register */
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__IO uint32_t LLI; /*!< DMA Channel Linked List Item Register */
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__IO uint32_t CONTROL; /*!< DMA Channel Control Register */
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__IO uint32_t CONFIG; /*!< DMA Channel Configuration Register */
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__I uint32_t RESERVED1[3];
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} IP_GPDMA_001_CH_Type;
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#define GPDMA_CHANNELS 8
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/**
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* @brief GPDMA register block
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*/
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typedef struct { /*!< GPDMA Structure */
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__I uint32_t INTSTAT; /*!< DMA Interrupt Status Register */
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__I uint32_t INTTCSTAT; /*!< DMA Interrupt Terminal Count Request Status Register */
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__O uint32_t INTTCCLEAR; /*!< DMA Interrupt Terminal Count Request Clear Register */
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__I uint32_t INTERRSTAT; /*!< DMA Interrupt Error Status Register */
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__O uint32_t INTERRCLR; /*!< DMA Interrupt Error Clear Register */
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__I uint32_t RAWINTTCSTAT; /*!< DMA Raw Interrupt Terminal Count Status Register */
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__I uint32_t RAWINTERRSTAT; /*!< DMA Raw Error Interrupt Status Register */
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__I uint32_t ENBLDCHNS; /*!< DMA Enabled Channel Register */
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__IO uint32_t SOFTBREQ; /*!< DMA Software Burst Request Register */
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__IO uint32_t SOFTSREQ; /*!< DMA Software Single Request Register */
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__IO uint32_t SOFTLBREQ; /*!< DMA Software Last Burst Request Register */
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__IO uint32_t SOFTLSREQ; /*!< DMA Software Last Single Request Register */
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__IO uint32_t CONFIG; /*!< DMA Configuration Register */
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__IO uint32_t SYNC; /*!< DMA Synchronization Register */
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__I uint32_t RESERVED0[50];
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IP_GPDMA_001_CH_Type CH[GPDMA_CHANNELS];
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} IP_GPDMA_001_Type;
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/**
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* @brief Macro defines for DMA channel control registers
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*/
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#define GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0)) /**< Transfer size*/
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#define GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12)) /**< Source burst size*/
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#define GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15)) /**< Destination burst size*/
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#define GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18)) /**< Source transfer width*/
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#define GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21)) /**< Destination transfer width*/
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#define GPDMA_DMACCxControl_SI ((1UL << 26)) /**< Source increment*/
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#define GPDMA_DMACCxControl_DI ((1UL << 27)) /**< Destination increment*/
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#if defined(CHIP_LPC43XX) || defined(CHIP_LPC18XX)
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#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL << 24)) /**< Source AHB master select in 18xx43xx*/
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#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL << 25)) /**< Destination AHB master select in 18xx43xx*/
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#else
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#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 0
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#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 0
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#endif
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#define GPDMA_DMACCxControl_Prot1 ((1UL << 28)) /**< Indicates that the access is in user mode or privileged mode*/
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#define GPDMA_DMACCxControl_Prot2 ((1UL << 29)) /**< Indicates that the access is bufferable or not bufferable*/
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#define GPDMA_DMACCxControl_Prot3 ((1UL << 30)) /**< Indicates that the access is cacheable or not cacheable*/
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#define GPDMA_DMACCxControl_I ((1UL << 31)) /**< Terminal count interrupt enable bit */
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/**
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* @brief Macro defines for DMA Configuration register
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*/
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#define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/
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#define GPDMA_DMACConfig_M ((0x02)) /**< AHB Master endianness configuration*/
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#define GPDMA_DMACConfig_BITMASK ((0x03))
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/**
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* @brief Macro defines for DMA Channel Configuration registers
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*/
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#define GPDMA_DMACCxConfig_E ((1UL << 0)) /**< DMA control enable*/
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#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1)) /**< Source peripheral*/
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#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6)) /**< Destination peripheral*/
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#define GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11)) /**< This value indicates the type of transfer*/
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#define GPDMA_DMACCxConfig_IE ((1UL << 14)) /**< Interrupt error mask*/
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#define GPDMA_DMACCxConfig_ITC ((1UL << 15)) /**< Terminal count interrupt mask*/
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#define GPDMA_DMACCxConfig_L ((1UL << 16)) /**< Lock*/
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#define GPDMA_DMACCxConfig_A ((1UL << 17)) /**< Active*/
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#define GPDMA_DMACCxConfig_H ((1UL << 18)) /**< Halt*/
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/**
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* @brief GPDMA Interrupt Clear Status
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*/
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typedef enum {
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GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
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GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
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} GPDMA_StateClear_Type;
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/**
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* @brief GPDMA Type of Interrupt Status
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*/
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typedef enum {
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GPDMA_STAT_INT, /**< GPDMA Interrupt Status */
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GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */
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GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */
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GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */
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GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */
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GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */
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} GPDMA_Status_Type;
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/**
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* @brief GPDMA Type of DMA controller
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*/
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typedef enum {
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GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA = ((0UL)), /**< Memory to memory - DMA control */
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GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA = ((1UL)), /**< Memory to peripheral - DMA control */
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GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA = ((2UL)), /**< Peripheral to memory - DMA control */
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GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA = ((3UL)), /**< Source peripheral to destination peripheral - DMA control */
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GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL = ((4UL)), /**< Source peripheral to destination peripheral - destination peripheral control */
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GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL = ((5UL)), /**< Memory to peripheral - peripheral control */
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GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL = ((6UL)), /**< Peripheral to memory - peripheral control */
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GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL = ((7UL)) /**< Source peripheral to destination peripheral - source peripheral control */
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} FlowControlType;
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/**
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* @brief GPDMA structure using for DMA configuration
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*/
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typedef struct {
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uint32_t ChannelNum; /**< DMA channel number, should be in
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* range from 0 to 7.
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* Note: DMA channel 0 has the highest priority
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* and DMA channel 7 the lowest priority.
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*/
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uint32_t TransferSize; /**< Length/Size of transfer */
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uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
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uint32_t SrcAddr; /**< Physical Source Address, used in case TransferType is chosen as
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* GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
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uint32_t DstAddr; /**< Physical Destination Address, used in case TransferType is chosen as
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* GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
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uint32_t TransferType; /**< Transfer Type, should be one of the following:
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* - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
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* - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
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* - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
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* - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
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*/
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} GPDMA_Channel_CFG_Type;
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/**
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* @brief Initialize the GPDMA
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* @param pGPDMA : The Base Address of GPDMA on the chip
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* @return Nothing
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*/
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void IP_GPDMA_Init(IP_GPDMA_001_Type *pGPDMA);
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/**
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* @brief Set up the DPDMA according to the specification configuration details
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* @param pGPDMA : The Base Address of GPDMA on the chip
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* @param GPDMAChannelConfig : Configuration struct
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* @param GPDMA_LUTPerBurstSrcConn : Peripheral Source burst size
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* @param GPDMA_LUTPerBurstDstConn : Peripheral Destination burst size
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* @param GPDMA_LUTPerWidSrcConn : Peripheral Source transfer width
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* @param GPDMA_LUTPerWidDstConn : Peripheral Destination transfer width
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* @param GPDMA_LUTPerAddrSrcConn : Peripheral Source Address
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* @param GPDMA_LUTPerAddrDstConn : Peripheral Destination Address
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* @param SrcPeripheral : Peripheral Source ID
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* @param DstPeripheral : Peripheral Destination ID
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* @return SUCCESS or ERROR on setup failure
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*/
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Status IP_GPDMA_Setup(IP_GPDMA_001_Type *pGPDMA,
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GPDMA_Channel_CFG_Type *GPDMAChannelConfig,
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uint32_t GPDMA_LUTPerBurstSrcConn,
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uint32_t GPDMA_LUTPerBurstDstConn,
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uint32_t GPDMA_LUTPerWidSrcConn,
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uint32_t GPDMA_LUTPerWidDstConn,
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uint32_t GPDMA_LUTPerAddrSrcConn,
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uint32_t GPDMA_LUTPerAddrDstConn,
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uint8_t SrcPeripheral,
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uint8_t DstPeripheral);
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/**
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* @brief Read the status from different registers according to the type
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* @param pGPDMA : The Base Address of GPDMA on the chip
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* @param type : Status mode, should be:
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* - GPDMA_STAT_INT : GPDMA Interrupt Status
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* - GPDMA_STAT_INTTC : GPDMA Interrupt Terminal Count Request Status
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* - GPDMA_STAT_INTERR : GPDMA Interrupt Error Status
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* - GPDMA_STAT_RAWINTTC : GPDMA Raw Interrupt Terminal Count Status
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* - GPDMA_STAT_RAWINTERR : GPDMA Raw Error Interrupt Status
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* - GPDMA_STAT_ENABLED_CH : GPDMA Enabled Channel Status
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* @param channel : The GPDMA channel : 0 - 7
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* @return SET is interrupt is pending or RESET if not pending
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*/
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IntStatus IP_GPDMA_IntGetStatus(IP_GPDMA_001_Type *pGPDMA, GPDMA_Status_Type type, uint8_t channel);
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/**
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* @brief Clear the Interrupt Flag from different registers according to the type
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* @param pGPDMA : The Base Address of GPDMA on the chip
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* @param type : Flag mode, should be:
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* - GPDMA_STATCLR_INTTC : GPDMA Interrupt Terminal Count Request
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* - GPDMA_STATCLR_INTERR : GPDMA Interrupt Error
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* @param channel : The GPDMA channel : 0 - 7
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* @return Nothing
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*/
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void IP_GPDMA_ClearIntPending(IP_GPDMA_001_Type *pGPDMA, GPDMA_StateClear_Type type, uint8_t channel);
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/**
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* @brief Enable or Disable the GPDMA Channel
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* @param pGPDMA : The Base Address of GPDMA on the chip
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* @param channelNum : The GPDMA channel : 0 - 7
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* @param NewState : ENABLE to enable GPDMA or DISABLE to disable GPDMA
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* @return Nothing
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*/
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void IP_GPDMA_ChannelCmd(IP_GPDMA_001_Type *pGPDMA, uint8_t channelNum, FunctionalState NewState);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __GPDMA_001_H_ */
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