ea6d73f140
1. Upgrade Cortex driver library (CMSIS -> CMSIS & Device): version 2.3.2 -> 3.0.1 & 3.0.0 - Remove "bsp/efm32/Libraries/CMSIS/Lib/ARM", "bsp/efm32/Libraries/CMSIS/Lib/G++" and "bsp/efm32/Libraries/CMSIS/SVD" to save space 2. Upgrade EFM32 driver libraries (efm32lib -> emlib): version 2.3.2 -> 3.0.0 - Remove "bsp/efm32/Libraries/Device/EnergyMicro/EFM32LG" and "bsp/efm32/Libraries/Device/EnergyMicro/EFM32TG" to save space 3. Upgrade EFM32GG_DK3750 development kit driver library: version 1.2.2 -> 2.0.1 4. Upgrade EFM32_Gxxx_DK development kit driver library: version 1.7.3 -> 2.0.1 5. Add energy management unit driver and test code 6. Modify linker script and related code to compatible with new version of libraries 7. Change EFM32 branch version number to 1.0 8. Add photo frame demo application git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2122 bbd45198-f89e-11dd-88c7-29a3b14d5316
110 lines
8.5 KiB
C
110 lines
8.5 KiB
C
/**************************************************************************//**
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* @file
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* @brief efm32g_rmu Register and Bit Field definitions
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* @author Energy Micro AS
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* @version 3.0.0
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
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******************************************************************************
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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*****************************************************************************/
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/**************************************************************************//**
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* @defgroup EFM32G_RMU
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* @{
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* @brief EFM32G_RMU Register Declaration
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*****************************************************************************/
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typedef struct
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{
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__IO uint32_t CTRL; /**< Control Register */
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__I uint32_t RSTCAUSE; /**< Reset Cause Register */
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__O uint32_t CMD; /**< Command Register */
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} RMU_TypeDef; /** @} */
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/**************************************************************************//**
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* @defgroup EFM32G_RMU_BitFields
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* @{
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*****************************************************************************/
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/* Bit fields for RMU CTRL */
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#define _RMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for RMU_CTRL */
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#define _RMU_CTRL_MASK 0x00000001UL /**< Mask for RMU_CTRL */
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#define RMU_CTRL_LOCKUPRDIS (0x1UL << 0) /**< Lockup Reset Disable */
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#define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 /**< Shift value for RMU_LOCKUPRDIS */
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#define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL /**< Bit mask for RMU_LOCKUPRDIS */
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#define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */
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#define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */
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/* Bit fields for RMU RSTCAUSE */
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#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */
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#define _RMU_RSTCAUSE_MASK 0x0000007FUL /**< Mask for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */
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#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */
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#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */
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#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1) /**< Brown Out Detector Unregulated Domain Reset */
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#define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 /**< Shift value for RMU_BODUNREGRST */
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#define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL /**< Bit mask for RMU_BODUNREGRST */
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#define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODREGRST (0x1UL << 2) /**< Brown Out Detector Regulated Domain Reset */
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#define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 /**< Shift value for RMU_BODREGRST */
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#define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL /**< Bit mask for RMU_BODREGRST */
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#define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_EXTRST (0x1UL << 3) /**< External Pin Reset */
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#define _RMU_RSTCAUSE_EXTRST_SHIFT 3 /**< Shift value for RMU_EXTRST */
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#define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL /**< Bit mask for RMU_EXTRST */
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#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_WDOGRST (0x1UL << 4) /**< Watchdog Reset */
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#define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 /**< Shift value for RMU_WDOGRST */
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#define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL /**< Bit mask for RMU_WDOGRST */
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#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5) /**< LOCKUP Reset */
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#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 /**< Shift value for RMU_LOCKUPRST */
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#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL /**< Bit mask for RMU_LOCKUPRST */
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#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6) /**< System Request Reset */
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#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 /**< Shift value for RMU_SYSREQRST */
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#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL /**< Bit mask for RMU_SYSREQRST */
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#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
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#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
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/* Bit fields for RMU CMD */
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#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */
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#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */
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#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */
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#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */
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#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */
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#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */
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#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
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/** @} End of group EFM32G_RMU */
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