ea6d73f140
1. Upgrade Cortex driver library (CMSIS -> CMSIS & Device): version 2.3.2 -> 3.0.1 & 3.0.0 - Remove "bsp/efm32/Libraries/CMSIS/Lib/ARM", "bsp/efm32/Libraries/CMSIS/Lib/G++" and "bsp/efm32/Libraries/CMSIS/SVD" to save space 2. Upgrade EFM32 driver libraries (efm32lib -> emlib): version 2.3.2 -> 3.0.0 - Remove "bsp/efm32/Libraries/Device/EnergyMicro/EFM32LG" and "bsp/efm32/Libraries/Device/EnergyMicro/EFM32TG" to save space 3. Upgrade EFM32GG_DK3750 development kit driver library: version 1.2.2 -> 2.0.1 4. Upgrade EFM32_Gxxx_DK development kit driver library: version 1.7.3 -> 2.0.1 5. Add energy management unit driver and test code 6. Modify linker script and related code to compatible with new version of libraries 7. Change EFM32 branch version number to 1.0 8. Add photo frame demo application git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2122 bbd45198-f89e-11dd-88c7-29a3b14d5316
117 lines
8.6 KiB
C
117 lines
8.6 KiB
C
/**************************************************************************//**
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* @file
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* @brief efm32g_emu Register and Bit Field definitions
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* @author Energy Micro AS
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* @version 3.0.0
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
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******************************************************************************
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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*****************************************************************************/
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/**************************************************************************//**
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* @defgroup EFM32G_EMU
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* @{
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* @brief EFM32G_EMU Register Declaration
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*****************************************************************************/
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typedef struct
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{
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__IO uint32_t CTRL; /**< Control Register */
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__IO uint32_t MEMCTRL; /**< Memory Control Register */
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__IO uint32_t LOCK; /**< Configuration Lock Register */
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uint32_t RESERVED0[6]; /**< Reserved for future use **/
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__IO uint32_t AUXCTRL; /**< Auxiliary Control Register */
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} EMU_TypeDef; /** @} */
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/**************************************************************************//**
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* @defgroup EFM32G_EMU_BitFields
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* @{
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*****************************************************************************/
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/* Bit fields for EMU CTRL */
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#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
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#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
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#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
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#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
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#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
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#define _EMU_CTRL_EMVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
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#define _EMU_CTRL_EMVREG_REDUCED 0x00000000UL /**< Mode REDUCED for EMU_CTRL */
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#define _EMU_CTRL_EMVREG_FULL 0x00000001UL /**< Mode FULL for EMU_CTRL */
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#define EMU_CTRL_EMVREG_DEFAULT (_EMU_CTRL_EMVREG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */
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#define EMU_CTRL_EMVREG_REDUCED (_EMU_CTRL_EMVREG_REDUCED << 0) /**< Shifted mode REDUCED for EMU_CTRL */
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#define EMU_CTRL_EMVREG_FULL (_EMU_CTRL_EMVREG_FULL << 0) /**< Shifted mode FULL for EMU_CTRL */
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#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */
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#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */
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#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */
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#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
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#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
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#define _EMU_CTRL_EM4CTRL_SHIFT 2 /**< Shift value for EMU_EM4CTRL */
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#define _EMU_CTRL_EM4CTRL_MASK 0xCUL /**< Bit mask for EMU_EM4CTRL */
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#define _EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
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#define EMU_CTRL_EM4CTRL_DEFAULT (_EMU_CTRL_EM4CTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */
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/* Bit fields for EMU MEMCTRL */
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#define _EMU_MEMCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_MEMCTRL */
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#define _EMU_MEMCTRL_MASK 0x00000007UL /**< Mask for EMU_MEMCTRL */
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#define _EMU_MEMCTRL_POWERDOWN_SHIFT 0 /**< Shift value for EMU_POWERDOWN */
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#define _EMU_MEMCTRL_POWERDOWN_MASK 0x7UL /**< Bit mask for EMU_POWERDOWN */
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#define _EMU_MEMCTRL_POWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_MEMCTRL */
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#define _EMU_MEMCTRL_POWERDOWN_BLK3 0x00000004UL /**< Mode BLK3 for EMU_MEMCTRL */
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#define _EMU_MEMCTRL_POWERDOWN_BLK23 0x00000006UL /**< Mode BLK23 for EMU_MEMCTRL */
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#define _EMU_MEMCTRL_POWERDOWN_BLK123 0x00000007UL /**< Mode BLK123 for EMU_MEMCTRL */
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#define EMU_MEMCTRL_POWERDOWN_DEFAULT (_EMU_MEMCTRL_POWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_MEMCTRL */
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#define EMU_MEMCTRL_POWERDOWN_BLK3 (_EMU_MEMCTRL_POWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_MEMCTRL */
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#define EMU_MEMCTRL_POWERDOWN_BLK23 (_EMU_MEMCTRL_POWERDOWN_BLK23 << 0) /**< Shifted mode BLK23 for EMU_MEMCTRL */
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#define EMU_MEMCTRL_POWERDOWN_BLK123 (_EMU_MEMCTRL_POWERDOWN_BLK123 << 0) /**< Shifted mode BLK123 for EMU_MEMCTRL */
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/* Bit fields for EMU LOCK */
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#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */
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#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */
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#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
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#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
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#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
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#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
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#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
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#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
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#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
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#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
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#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
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#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
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#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
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#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
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/* Bit fields for EMU AUXCTRL */
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#define _EMU_AUXCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_AUXCTRL */
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#define _EMU_AUXCTRL_MASK 0x00000001UL /**< Mask for EMU_AUXCTRL */
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#define EMU_AUXCTRL_HRCCLR (0x1UL << 0) /**< Hard Reset Cause Clear */
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#define _EMU_AUXCTRL_HRCCLR_SHIFT 0 /**< Shift value for EMU_HRCCLR */
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#define _EMU_AUXCTRL_HRCCLR_MASK 0x1UL /**< Bit mask for EMU_HRCCLR */
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#define _EMU_AUXCTRL_HRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_AUXCTRL */
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#define EMU_AUXCTRL_HRCCLR_DEFAULT (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_AUXCTRL */
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/** @} End of group EFM32G_EMU */
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