f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
53 lines
1.3 KiB
C
53 lines
1.3 KiB
C
/** @file reg_tcram.h
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* @brief TCRAM Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* .
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* which are relevant for the System driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_TCRAM_H__
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#define __REG_TCRAM_H__
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#include "sys_common.h"
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/* Tcram Register Frame Definition */
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/** @struct tcramBase
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* @brief TCRAM Wrapper Register Frame Definition
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*
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* This type is used to access the TCRAM Wrapper Registers.
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*/
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/** @typedef tcramBASE_t
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* @brief TCRAM Wrapper Register Frame Type Definition
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*
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* This type is used to access the TCRAM Wrapper Registers.
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*/
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typedef volatile struct tcramBase
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{
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uint32 RAMCTRL; /* 0x0000 */
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uint32 RAMTHRESHOLD; /* 0x0004 */
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uint32 RAMOCCUR; /* 0x0008 */
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uint32 RAMINTCTRL; /* 0x000C */
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uint32 RAMERRSTATUS; /* 0x0010 */
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uint32 RAMSERRADDR; /* 0x0014 */
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uint32 rsvd1; /* 0x0018 */
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uint32 RAMUERRADDR; /* 0x001C */
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uint32 rsvd2[4U]; /* 0x0020 */
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uint32 RAMTEST; /* 0x0030 */
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uint32 rsvd3; /* 0x0034 */
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uint32 RAMADDRDECVECT; /* 0x0038 */
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uint32 RAMPERADDR; /* 0x003C */
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} tcramBASE_t;
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#define tcram1REG ((tcramBASE_t *)(0xFFFFF800U))
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#define tcram2REG ((tcramBASE_t *)(0xFFFFF900U))
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#endif
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