f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
179 lines
7.7 KiB
C
179 lines
7.7 KiB
C
/** @file reg_can.h
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* @brief CAN Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the CAN driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_CAN_H__
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#define __REG_CAN_H__
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#include "sys_common.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Can Register Frame Definition */
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/** @struct canBase
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* @brief CAN Register Frame Definition
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*
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* This type is used to access the CAN Registers.
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*/
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/** @typedef canBASE_t
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* @brief CAN Register Frame Type Definition
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*
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* This type is used to access the CAN Registers.
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*/
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typedef volatile struct canBase
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{
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uint32 CTL; /**< 0x0000: Control Register */
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uint32 ES; /**< 0x0004: Error and Status Register */
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uint32 EERC; /**< 0x0008: Error Counter Register */
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uint32 BTR; /**< 0x000C: Bit Timing Register */
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uint32 INT; /**< 0x0010: Interrupt Register */
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uint32 TEST; /**< 0x0014: Test Register */
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uint32 rsvd1; /**< 0x0018: Reserved */
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uint32 PERR; /**< 0x001C: Parity/SECDED Error Code Register */
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uint32 REL; /**< 0x0020: Core Release Register */
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uint32 ECCDIAG; /**< 0x0024: ECC Diagnostic Register */
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uint32 ECCDIADSTAT; /**< 0x0028: ECC Diagnostic Status Register */
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uint32 rsvd2[21]; /**< 0x002C: Reserved */
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uint32 ABOTR; /**< 0x0080: Auto Bus On Time Register */
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uint32 TXRQX; /**< 0x0084: Transmission Request X Register */
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uint32 TXRQx[4U]; /**< 0x0088-0x0094: Transmission Request Registers */
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uint32 NWDATX; /**< 0x0098: New Data X Register */
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uint32 NWDATx[4U]; /**< 0x009C-0x00A8: New Data Registers */
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uint32 INTPNDX; /**< 0x00AC: Interrupt Pending X Register */
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uint32 INTPNDx[4U]; /**< 0x00B0-0x00BC: Interrupt Pending Registers */
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uint32 MSGVALX; /**< 0x00C0: Message Valid X Register */
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uint32 MSGVALx[4U]; /**< 0x00C4-0x00D0: Message Valid Registers */
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uint32 rsvd3; /**< 0x00D4: Reserved */
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uint32 INTMUXx[4U]; /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */
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uint32 rsvd4[6]; /**< 0x00E8: Reserved */
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#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
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uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */
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uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */
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uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */
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uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */
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#else
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uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */
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uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */
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uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */
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uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */
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#endif
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uint32 IF1MSK; /**< 0x0104: IF1 Mask Register */
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uint32 IF1ARB; /**< 0x0108: IF1 Arbitration Register */
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uint32 IF1MCTL; /**< 0x010C: IF1 Message Control Register */
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uint8 IF1DATx[8U]; /**< 0x0110-0x0114: IF1 Data A and B Registers */
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uint32 rsvd5[2]; /**< 0x0118: Reserved */
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#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
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uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg No */
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uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */
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uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */
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uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */
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#else
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uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */
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uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */
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uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */
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uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg Number */
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#endif
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uint32 IF2MSK; /**< 0x0124: IF2 Mask Register */
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uint32 IF2ARB; /**< 0x0128: IF2 Arbitration Register */
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uint32 IF2MCTL; /**< 0x012C: IF2 Message Control Register */
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uint8 IF2DATx[8U]; /**< 0x0130-0x0134: IF2 Data A and B Registers */
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uint32 rsvd6[2]; /**< 0x0138: Reserved */
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uint32 IF3OBS; /**< 0x0140: IF3 Observation Register */
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uint32 IF3MSK; /**< 0x0144: IF3 Mask Register */
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uint32 IF3ARB; /**< 0x0148: IF3 Arbitration Register */
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uint32 IF3MCTL; /**< 0x014C: IF3 Message Control Register */
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uint8 IF3DATx[8U]; /**< 0x0150-0x0154: IF3 Data A and B Registers */
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uint32 rsvd7[2]; /**< 0x0158: Reserved */
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uint32 IF3UEy[4U]; /**< 0x0160-0x016C: IF3 Update Enable Registers */
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uint32 rsvd8[28]; /**< 0x0170: Reserved */
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uint32 TIOC; /**< 0x01E0: TX IO Control Register */
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uint32 RIOC; /**< 0x01E4: RX IO Control Register */
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} canBASE_t;
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/** @def canREG1
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* @brief CAN1 Register Frame Pointer
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*
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* This pointer is used by the CAN driver to access the CAN1 registers.
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*/
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#define canREG1 ((canBASE_t *)0xFFF7DC00U)
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/** @def canREG2
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* @brief CAN2 Register Frame Pointer
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*
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* This pointer is used by the CAN driver to access the CAN2 registers.
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*/
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#define canREG2 ((canBASE_t *)0xFFF7DE00U)
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/** @def canREG3
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* @brief CAN3 Register Frame Pointer
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*
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* This pointer is used by the CAN driver to access the CAN3 registers.
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*/
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#define canREG3 ((canBASE_t *)0xFFF7E000U)
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/** @def canRAM1
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* @brief CAN1 Mailbox RAM Pointer
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*
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* This pointer is used by the CAN driver to access the CAN1 RAM.
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*/
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#define canRAM1 (*(volatile uint32 *)0xFF1E0000U)
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/** @def canRAM2
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* @brief CAN2 Mailbox RAM Pointer
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*
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* This pointer is used by the CAN driver to access the CAN2 RAM.
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*/
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#define canRAM2 (*(volatile uint32 *)0xFF1C0000U)
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/** @def canRAM3
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* @brief CAN3 Mailbox RAM Pointer
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*
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* This pointer is used by the CAN driver to access the CAN3 RAM.
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*/
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#define canRAM3 (*(volatile uint32 *)0xFF1A0000U)
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/** @def canPARRAM1
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* @brief CAN1 Mailbox Parity RAM Pointer
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*
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* This pointer is used by the CAN driver to access the CAN1 Parity RAM
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* for testing RAM parity error detect logic.
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*/
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#define canPARRAM1 (*(volatile uint32 *)(0xFF1E0000U + 0x10U))
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/** @def canPARRAM2
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* @brief CAN2 Mailbox Parity RAM Pointer
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*
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* This pointer is used by the CAN driver to access the CAN2 Parity RAM
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* for testing RAM parity error detect logic.
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*/
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#define canPARRAM2 (*(volatile uint32 *)(0xFF1C0000U + 0x10U))
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/** @def canPARRAM3
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* @brief CAN3 Mailbox Parity RAM Pointer
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*
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* This pointer is used by the CAN driver to access the CAN3 Parity RAM
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* for testing RAM parity error detect logic.
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*/
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#define canPARRAM3 (*(volatile uint32 *)(0xFF1A0000U + 0x10U))
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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