674 lines
13 KiB
C
674 lines
13 KiB
C
/*
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* File : mmu.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2015-04-15 ArdaFu Add code for IAR
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*/
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#include "mmu.h"
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#ifdef __CC_ARM
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void mmu_setttbase(rt_uint32_t i)
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{
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register rt_uint32_t value;
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/* Invalidates all TLBs.Domain access is selected as
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* client by configuring domain access register,
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* in that case access controlled by permission value
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* set by page table entry
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*/
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value = 0;
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__asm
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{
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mcr p15, 0, value, c8, c7, 0
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}
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value = 0x55555555;
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__asm
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{
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mcr p15, 0, value, c3, c0, 0
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mcr p15, 0, i, c2, c0, 0
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}
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}
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void mmu_set_domain(rt_uint32_t i)
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{
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__asm
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{
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mcr p15,0, i, c3, c0, 0
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}
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}
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void mmu_enable()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x01
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x01
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_enable_icache()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x1000
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_enable_dcache()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x04
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable_icache()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x1000
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable_dcache()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x04
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_enable_alignfault()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x02
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable_alignfault()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x02
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_clean_invalidated_cache_index(int index)
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{
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__asm
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{
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mcr p15, 0, index, c7, c14, 2
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}
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}
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void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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while(ptr < buffer + size)
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{
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__asm
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{
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MCR p15, 0, ptr, c7, c14, 1
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}
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ptr += CACHE_LINE_SIZE;
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}
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}
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void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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while (ptr < buffer + size)
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{
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__asm
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{
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MCR p15, 0, ptr, c7, c10, 1
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}
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ptr += CACHE_LINE_SIZE;
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}
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}
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void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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while (ptr < buffer + size)
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{
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__asm
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{
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MCR p15, 0, ptr, c7, c6, 1
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}
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ptr += CACHE_LINE_SIZE;
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}
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}
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void mmu_invalidate_tlb()
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{
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register rt_uint32_t value;
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value = 0;
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__asm
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{
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mcr p15, 0, value, c8, c7, 0
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}
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}
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void mmu_invalidate_icache()
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{
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register rt_uint32_t value;
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value = 0;
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__asm
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{
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mcr p15, 0, value, c7, c5, 0
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}
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}
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void mmu_invalidate_dcache_all()
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{
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register rt_uint32_t value;
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value = 0;
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__asm
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{
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mcr p15, 0, value, c7, c6, 0
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}
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}
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#elif defined(__GNUC__)
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void mmu_setttbase(register rt_uint32_t i)
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{
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register rt_uint32_t value;
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/* Invalidates all TLBs.Domain access is selected as
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* client by configuring domain access register,
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* in that case access controlled by permission value
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* set by page table entry
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*/
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value = 0;
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asm ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
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value = 0x55555555;
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asm ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
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asm ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
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}
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void mmu_set_domain(register rt_uint32_t i)
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{
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asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
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}
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void mmu_enable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= 0x1;
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~0x1;
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 12);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 2);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 12);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 2);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 1);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 1);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_clean_invalidated_cache_index(int index)
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{
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asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
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}
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void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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while(ptr < buffer + size)
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{
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asm ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
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ptr += CACHE_LINE_SIZE;
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}
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}
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void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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while (ptr < buffer + size)
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{
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asm ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
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ptr += CACHE_LINE_SIZE;
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}
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}
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void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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while (ptr < buffer + size)
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{
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asm ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
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ptr += CACHE_LINE_SIZE;
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}
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}
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void mmu_invalidate_tlb()
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{
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asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
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}
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void mmu_invalidate_icache()
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{
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asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
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}
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void mmu_invalidate_dcache_all()
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{
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asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
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}
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#elif defined(__ICCARM__)
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void mmu_setttbase(register rt_uint32_t i)
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{
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register rt_uint32_t value;
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/* Invalidates all TLBs.Domain access is selected as
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* client by configuring domain access register,
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* in that case access controlled by permission value
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* set by page table entry
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*/
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value = 0;
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asm ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
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value = 0x55555555;
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asm ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
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asm ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
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}
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void mmu_set_domain(register rt_uint32_t i)
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{
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asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
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}
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void mmu_enable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= 0x1;
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~0x1;
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 12);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 2);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 12);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 2);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 1);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 1);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_clean_invalidated_cache_index(int index)
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{
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asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
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}
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void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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while(ptr < buffer + size)
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{
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asm ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
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ptr += CACHE_LINE_SIZE;
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}
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}
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void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
|
|
{
|
|
unsigned int ptr;
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|
|
|
ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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|
|
|
while (ptr < buffer + size)
|
|
{
|
|
asm ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
|
|
ptr += CACHE_LINE_SIZE;
|
|
}
|
|
}
|
|
|
|
void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
|
|
{
|
|
unsigned int ptr;
|
|
|
|
ptr = buffer & ~(CACHE_LINE_SIZE - 1);
|
|
|
|
while (ptr < buffer + size)
|
|
{
|
|
asm ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
|
|
ptr += CACHE_LINE_SIZE;
|
|
}
|
|
}
|
|
|
|
void mmu_invalidate_tlb()
|
|
{
|
|
asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
|
|
}
|
|
|
|
void mmu_invalidate_icache()
|
|
{
|
|
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
|
|
}
|
|
|
|
void mmu_invalidate_dcache_all()
|
|
{
|
|
asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
|
|
}
|
|
#endif
|
|
|
|
/* level1 page table */
|
|
#if defined(__ICCARM__)
|
|
#pragma data_alignment=(16*1024)
|
|
static volatile unsigned int _page_table[4*1024];;
|
|
#else
|
|
static volatile unsigned int _page_table[4*1024] \
|
|
__attribute__((aligned(16*1024)));
|
|
#endif
|
|
void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
|
|
rt_uint32_t paddrStart, rt_uint32_t attr)
|
|
{
|
|
volatile rt_uint32_t *pTT;
|
|
volatile int nSec;
|
|
int i = 0;
|
|
pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
|
|
nSec=(vaddrEnd>>20)-(vaddrStart>>20);
|
|
for(i=0; i<=nSec; i++)
|
|
{
|
|
*pTT = attr |(((paddrStart>>20)+i)<<20);
|
|
pTT++;
|
|
}
|
|
}
|
|
|
|
void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
|
|
{
|
|
/* disable I/D cache */
|
|
mmu_disable_dcache();
|
|
mmu_disable_icache();
|
|
mmu_disable();
|
|
mmu_invalidate_tlb();
|
|
|
|
/* set page table */
|
|
for (; size > 0; size--)
|
|
{
|
|
mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end,
|
|
mdesc->paddr_start, mdesc->attr);
|
|
mdesc++;
|
|
}
|
|
|
|
/* set MMU table address */
|
|
mmu_setttbase((rt_uint32_t)_page_table);
|
|
|
|
/* enables MMU */
|
|
mmu_enable();
|
|
|
|
/* enable Instruction Cache */
|
|
mmu_enable_icache();
|
|
|
|
/* enable Data Cache */
|
|
mmu_enable_dcache();
|
|
|
|
mmu_invalidate_icache();
|
|
mmu_invalidate_dcache_all();
|
|
}
|