f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
653 lines
18 KiB
C
653 lines
18 KiB
C
/** @file sys_startup.c
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* @brief Startup Source File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Include Files
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* - Type Definitions
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* - External Functions
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* - VIM RAM Setup
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* - Startup Routine
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* .
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* which are relevant for the Startup.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Include Files */
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#include "sys_common.h"
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#include "system.h"
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#include "sys_vim.h"
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#include "sys_core.h"
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#include "sys_selftest.h"
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#include "esm.h"
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#include "mibspi.h"
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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/* Type Definitions */
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typedef void (*handler_fptr)(const uint8 * in, uint8 * out);
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/* USER CODE BEGIN (2) */
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/* USER CODE END */
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/* External Functions */
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/*SAFETYMCUSW 94 S MR:11.1 <REVIEWED> "Startup code(handler pointers)" */
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/*SAFETYMCUSW 122 S MR:20.11 <REVIEWED> "Startup code(exit and abort need to be present)" */
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/*SAFETYMCUSW 296 S MR:8.6 <REVIEWED> "Startup code(library functions at block scope)" */
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/*SAFETYMCUSW 298 S MR: <REVIEWED> "Startup code(handler pointers)" */
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/*SAFETYMCUSW 299 S MR: <REVIEWED> "Startup code(typedef for handler pointers in library )" */
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/*SAFETYMCUSW 326 S MR:8.2 <REVIEWED> "Startup code(Declaration for main in library)" */
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/*SAFETYMCUSW 60 D MR:8.8 <REVIEWED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
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/*SAFETYMCUSW 94 S MR:11.1 <REVIEWED> "Startup code(handler pointers)" */
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/*SAFETYMCUSW 354 S MR:1.4 <REVIEWED> " Startup code(Extern declaration present in the library)" */
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/*SAFETYMCUSW 218 S MR:20.2 <REVIEWED> "Functions from library" */
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#pragma WEAK(__TI_Handler_Table_Base)
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#pragma WEAK(__TI_Handler_Table_Limit)
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#pragma WEAK(__TI_CINIT_Base)
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#pragma WEAK(__TI_CINIT_Limit)
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extern uint32 __TI_Handler_Table_Base;
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extern uint32 __TI_Handler_Table_Limit;
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extern uint32 __TI_CINIT_Base;
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extern uint32 __TI_CINIT_Limit;
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extern uint32 __TI_PINIT_Base;
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extern uint32 __TI_PINIT_Limit;
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extern uint32 * __binit__;
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extern void main(void);
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extern void exit(void);
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extern void muxInit(void);
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/* USER CODE BEGIN (3) */
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/* USER CODE END */
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/* Startup Routine */
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/* USER CODE BEGIN (4) */
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/* USER CODE END */
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#pragma CODE_STATE(_c_int00, 32)
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#pragma INTERRUPT(_c_int00, RESET)
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void _c_int00(void)
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{
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/* USER CODE BEGIN (5) */
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/* USER CODE END */
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/* Initialize Core Registers to avoid CCM Error */
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_coreInitRegisters_();
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/* USER CODE BEGIN (6) */
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/* USER CODE END */
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/* Initialize Stack Pointers */
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_coreInitStackPointer_();
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/* USER CODE BEGIN (7) */
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/* USER CODE END */
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/* Work Around for Errata DEVICE#140: ( Only on Rev A silicon)
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*
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* Errata Description:
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* The Core Compare Module(CCM-R4) may cause nERROR to be asserted after a cold power-on
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* Workaround:
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* Clear ESM Group2 Channel 2 error in ESMSR2 and Compare error in CCMSR register */
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if (DEVICE_ID_REV == 0x802AAD05U)
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{
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_esmCcmErrorsClear_();
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}
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/* USER CODE BEGIN (8) */
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/* USER CODE END */
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/* Enable CPU Event Export */
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/* This allows the CPU to signal any single-bit or double-bit errors detected
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* by its ECC logic for accesses to program flash or data RAM.
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*/
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_coreEnableEventBusExport_();
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/* USER CODE BEGIN (11) */
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/* USER CODE END */
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/* Reset handler: the following instructions read from the system exception status register
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* to identify the cause of the CPU reset.
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*/
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/* check for power-on reset condition */
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if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
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{
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/* USER CODE BEGIN (12) */
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/* USER CODE END */
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/* clear all reset status flags */
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SYS_EXCEPTION = 0xFFFFU;
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/* USER CODE BEGIN (13) */
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/* USER CODE END */
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_errata_CORTEXR4_66_();
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/* USER CODE BEGIN (14) */
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/* USER CODE END */
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_errata_CORTEXR4_57_();
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/* USER CODE BEGIN (15) */
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/* USER CODE END */
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/* continue with normal start-up sequence */
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}
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else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
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{
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/* Reset caused due to oscillator failure.
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Add user code here to handle oscillator failure */
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/* USER CODE BEGIN (16) */
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/* USER CODE END */
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}
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else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
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{
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/* Reset caused due
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* 1) windowed watchdog violation - Add user code here to handle watchdog violation.
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* 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
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*/
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/* Check the WatchDog Status register */
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if(WATCHDOG_STATUS != 0U)
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{
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/* Add user code here to handle watchdog violation. */
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/* USER CODE BEGIN (17) */
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/* USER CODE END */
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/* Clear the Watchdog reset flag in Exception Status register */
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SYS_EXCEPTION = WATCHDOG_RESET;
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/* USER CODE BEGIN (18) */
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/* USER CODE END */
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}
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else
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{
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/* Clear the ICEPICK reset flag in Exception Status register */
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SYS_EXCEPTION = ICEPICK_RESET;
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/* USER CODE BEGIN (19) */
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/* USER CODE END */
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}
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}
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else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
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{
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/* Reset caused due to CPU reset.
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CPU reset can be caused by CPU self-test completion, or
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by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
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/* USER CODE BEGIN (20) */
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/* USER CODE END */
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/* clear all reset status flags */
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SYS_EXCEPTION = CPU_RESET;
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/* USER CODE BEGIN (21) */
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/* USER CODE END */
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}
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else if ((SYS_EXCEPTION & SW_RESET) != 0U)
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{
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/* Reset caused due to software reset.
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Add user code to handle software reset. */
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/* USER CODE BEGIN (22) */
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/* USER CODE END */
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}
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else
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{
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/* Reset caused by nRST being driven low externally.
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Add user code to handle external reset. */
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/* USER CODE BEGIN (23) */
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/* USER CODE END */
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}
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/* Check if there were ESM group3 errors during power-up.
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* These could occur during eFuse auto-load or during reads from flash OTP
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* during power-up. Device operation is not reliable and not recommended
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* in this case.
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* An ESM group3 error only drives the nERROR pin low. An external circuit
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* that monitors the nERROR pin must take the appropriate action to ensure that
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* the system is placed in a safe state, as determined by the application.
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*/
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if ((esmREG->ESTATUS1[2]) != 0U)
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{
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/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
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/* USER CODE BEGIN (24) */
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/* USER CODE END */
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for(;;)
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{
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}/* Wait */
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/* USER CODE BEGIN (25) */
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/* USER CODE END */
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}
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/* USER CODE BEGIN (26) */
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/* USER CODE END */
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/* Initialize System - Clock, Flash settings with Efuse self check */
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systemInit();
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/* USER CODE BEGIN (29) */
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/* USER CODE END */
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/* Run a diagnostic check on the memory self-test controller.
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* This function chooses a RAM test algorithm and runs it on an on-chip ROM.
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* The memory self-test is expected to fail. The function ensures that the PBIST controller
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* is capable of detecting and indicating a memory self-test failure.
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*/
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pbistSelfCheck();
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/* USER CODE BEGIN (31) */
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/* USER CODE END */
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/* Run PBIST on CPU RAM.
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* The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
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* The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
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* device datasheet.
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*/
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pbistRun(0x08300020U, /* ESRAM Single Port PBIST */
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(uint32)PBIST_March13N_SP);
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/* USER CODE BEGIN (32) */
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/* USER CODE END */
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/* Wait for PBIST for CPU RAM to be completed */
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while((!pbistIsTestCompleted()) == TRUE)
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{
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}/* Wait */
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/* USER CODE BEGIN (33) */
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/* USER CODE END */
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/* Check if CPU RAM passed the self-test */
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if( pbistIsTestPassed() != TRUE)
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{
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/* CPU RAM failed the self-test.
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* Need custom handler to check the memory failure
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* and to take the appropriate next step.
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*/
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if(pbistPortTestStatus((uint32)PBIST_PORT0) != TRUE)
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{
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memoryPort0TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U), (uint32)pbistREG->FSRA0, (uint32)pbistREG->FSRDL0);
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}
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else if(pbistPortTestStatus((uint32)PBIST_PORT1) != TRUE)
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{
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memoryPort1TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U),(uint32)pbistREG->FSRA1, (uint32)pbistREG->FSRDL1);
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}
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else
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{
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/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
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/* USER CODE BEGIN (34) */
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/* USER CODE END */
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for(;;)
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{
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}/* Wait */
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/* USER CODE BEGIN (35) */
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/* USER CODE END */
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}
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}
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/* USER CODE BEGIN (36) */
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/* USER CODE END */
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/* Disable PBIST clocks and disable memory self-test mode */
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pbistStop();
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/* USER CODE BEGIN (37) */
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/* USER CODE END */
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/* Initialize CPU RAM.
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* This function uses the system module's hardware for auto-initialization of memories and their
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* associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
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* Hence the value 0x1 passed to the function.
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* This function will initialize the entire CPU RAM and the corresponding ECC locations.
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*/
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memoryInit(0x1U);
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/* USER CODE BEGIN (38) */
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/* USER CODE END */
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/* Enable ECC checking for TCRAM accesses.
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* This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
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*/
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_coreEnableRamEcc_();
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/* USER CODE BEGIN (39) */
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/* USER CODE END */
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/* Start PBIST on all dual-port memories */
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/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories.
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PBIST test perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
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*/
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pbistRun( 0x00000000U
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| 0x00000000U
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| 0x00000800U
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| 0x00000200U
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| 0x00000040U
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| 0x00000080U
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| 0x00000100U
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| 0x00000004U
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| 0x00000008U
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| 0x00000010U
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| 0x00000400U
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| 0x00020000U
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| 0x00001000U
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| 0x00040000U
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| 0x00002000U
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| 0x00080000U
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| 0x00004000U
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| 0x00000000U
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| 0x00000000U
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,(uint32) PBIST_March13N_DP);
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/* USER CODE BEGIN (40) */
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/* USER CODE END */
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/* Test the CPU ECC mechanism for RAM accesses.
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* The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
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* by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
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* in the ECC causes a data abort exception. The data abort handler is written to look for
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* deliberately caused exception and to return the code execution to the instruction
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* following the one that caused the abort.
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*/
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checkB0RAMECC();
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tcram1REG->RAMCTRL &= ~(0x00000100U); /* disable writes to ECC RAM */
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tcram2REG->RAMCTRL &= ~(0x00000100U);
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checkB1RAMECC();
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tcram1REG->RAMCTRL &= ~(0x00000100U); /* disable writes to ECC RAM */
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tcram2REG->RAMCTRL &= ~(0x00000100U);
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/* USER CODE BEGIN (41) */
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/* USER CODE END */
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/* USER CODE BEGIN (43) */
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/* USER CODE END */
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/* Wait for PBIST for CPU RAM to be completed */
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while((!pbistIsTestCompleted()) == TRUE)
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{
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}/* Wait */
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/* USER CODE BEGIN (44) */
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/* USER CODE END */
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/* Check if CPU RAM passed the self-test */
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if( pbistIsTestPassed() != TRUE)
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{
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/* USER CODE BEGIN (45) */
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/* USER CODE END */
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/* CPU RAM failed the self-test.
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* Need custom handler to check the memory failure
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* and to take the appropriate next step.
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*/
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if(pbistPortTestStatus((uint32)PBIST_PORT0) != TRUE)
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{
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memoryPort0TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U),(uint32)pbistREG->FSRA0, (uint32)pbistREG->FSRDL0);
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}
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else if(pbistPortTestStatus((uint32)PBIST_PORT1) != TRUE)
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{
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memoryPort1TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U), (uint32)pbistREG->FSRA1, (uint32)pbistREG->FSRDL1);
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}
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else
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{
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/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
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/* USER CODE BEGIN (46) */
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/* USER CODE END */
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for(;;)
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{
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}/* Wait */
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/* USER CODE BEGIN (47) */
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/* USER CODE END */
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}
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}
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/* USER CODE BEGIN (48) */
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/* USER CODE END */
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/* Disable PBIST clocks and disable memory self-test mode */
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pbistStop();
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/* USER CODE BEGIN (56) */
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/* USER CODE END */
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/* Release the MibSPI1 modules from local reset.
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* This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
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*/
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mibspiREG1->GCR0 = 0x1U;
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/* Release the MibSPI3 modules from local reset.
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* This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
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*/
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mibspiREG3->GCR0 = 0x1U;
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/* Release the MibSPI5 modules from local reset.
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* This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
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*/
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mibspiREG5->GCR0 = 0x1U;
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/* USER CODE BEGIN (57) */
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/* USER CODE END */
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/* Initialize all on-chip SRAMs except for MibSPIx RAMs
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* The MibSPIx modules have their own auto-initialization mechanism which is triggered
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* as soon as the modules are brought out of local reset.
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*/
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/* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
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*/
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/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers.
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Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
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*/
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memoryInit( (1U << 1U)
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| (1U << 2U)
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| (1U << 5U)
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| (1U << 6U)
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| (1U << 10U)
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| (1U << 8U)
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| (1U << 14U)
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| (1U << 3U)
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| (1U << 4U)
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| (1U << 15U)
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| (1U << 16U)
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| (0U << 13U) );
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/* Test the parity protection mechanism for peripheral RAMs
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NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity.
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Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
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*/
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/* USER CODE BEGIN (58) */
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/* USER CODE END */
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het1ParityCheck();
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/* USER CODE BEGIN (59) */
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/* USER CODE END */
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htu1ParityCheck();
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/* USER CODE BEGIN (60) */
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/* USER CODE END */
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het2ParityCheck();
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/* USER CODE BEGIN (61) */
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/* USER CODE END */
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htu2ParityCheck();
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/* USER CODE BEGIN (62) */
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/* USER CODE END */
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adc1ParityCheck();
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/* USER CODE BEGIN (63) */
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/* USER CODE END */
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adc2ParityCheck();
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/* USER CODE BEGIN (64) */
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/* USER CODE END */
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can1ParityCheck();
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/* USER CODE BEGIN (65) */
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/* USER CODE END */
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can2ParityCheck();
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/* USER CODE BEGIN (66) */
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/* USER CODE END */
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can3ParityCheck();
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/* USER CODE BEGIN (67) */
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/* USER CODE END */
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vimParityCheck();
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|
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/* USER CODE BEGIN (68) */
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/* USER CODE END */
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|
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dmaParityCheck();
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|
|
|
|
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/* USER CODE BEGIN (69) */
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|
/* USER CODE END */
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while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
|
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{
|
|
}/* Wait */
|
|
/* wait for MibSPI1 RAM to complete initialization */
|
|
while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U)
|
|
{
|
|
}/* Wait */
|
|
/* wait for MibSPI3 RAM to complete initialization */
|
|
while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U)
|
|
{
|
|
}/* Wait */
|
|
/* wait for MibSPI5 RAM to complete initialization */
|
|
|
|
/* USER CODE BEGIN (70) */
|
|
/* USER CODE END */
|
|
|
|
mibspi1ParityCheck();
|
|
|
|
/* USER CODE BEGIN (71) */
|
|
/* USER CODE END */
|
|
|
|
mibspi3ParityCheck();
|
|
|
|
/* USER CODE BEGIN (72) */
|
|
/* USER CODE END */
|
|
|
|
mibspi5ParityCheck();
|
|
|
|
|
|
/* USER CODE BEGIN (73) */
|
|
/* USER CODE END */
|
|
|
|
|
|
/* USER CODE BEGIN (74) */
|
|
/* USER CODE END */
|
|
|
|
/* Initialize VIM table */
|
|
vimInit();
|
|
|
|
/* USER CODE BEGIN (75) */
|
|
/* USER CODE END */
|
|
|
|
/* Configure system response to error conditions signaled to the ESM group1 */
|
|
/* This function can be configured from the ESM tab of HALCoGen */
|
|
esmInit();
|
|
|
|
/* initialize copy table */
|
|
if ((uint32 *)&__binit__ != (uint32 *)0xFFFFFFFFU)
|
|
{
|
|
extern void copy_in(void * binit);
|
|
copy_in((void *)&__binit__);
|
|
}
|
|
|
|
/* initialize the C global variables */
|
|
if (&__TI_Handler_Table_Base < &__TI_Handler_Table_Limit)
|
|
{
|
|
uint8 **tablePtr = (uint8 **)&__TI_CINIT_Base;
|
|
uint8 **tableLimit = (uint8 **)&__TI_CINIT_Limit;
|
|
|
|
while (tablePtr < tableLimit)
|
|
{
|
|
uint8 * loadAdr = *tablePtr++;
|
|
uint8 * runAdr = *tablePtr++;
|
|
uint8 idx = *loadAdr++;
|
|
handler_fptr handler = (handler_fptr)(&__TI_Handler_Table_Base)[idx];
|
|
|
|
(*handler)((const uint8 *)loadAdr, runAdr);
|
|
}
|
|
}
|
|
|
|
/* initialize constructors */
|
|
if (__TI_PINIT_Base < __TI_PINIT_Limit)
|
|
{
|
|
void (**p0)(void) = (void *)__TI_PINIT_Base;
|
|
|
|
while ((uint32)p0 < __TI_PINIT_Limit)
|
|
{
|
|
void (*p)(void) = *p0++;
|
|
p();
|
|
}
|
|
}
|
|
|
|
/* USER CODE BEGIN (76) */
|
|
/* USER CODE END */
|
|
|
|
/* call the application */
|
|
main();
|
|
|
|
/* USER CODE BEGIN (77) */
|
|
/* USER CODE END */
|
|
|
|
exit();
|
|
/* USER CODE BEGIN (78) */
|
|
/* USER CODE END */
|
|
}
|
|
|
|
/* USER CODE BEGIN (79) */
|
|
/* USER CODE END */
|