f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
102 lines
1.8 KiB
C
102 lines
1.8 KiB
C
/** @file emif.h
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* @brief emif Driver Definition File
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* @date 23.May.2013
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* @version 03.05.01
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*
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef _EMIF_H_
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#define _EMIF_H_
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#include "reg_emif.h"
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/** @enum emif_pins
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* @brief Alias for emif pins
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*
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*/
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enum emif_pins
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{
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emif_wait_pin0 = 0U,
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emif_wait_pin1 = 1U
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};
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/** @enum emif_size
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* @brief Alias for emif page size
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*
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*/
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enum emif_size
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{
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elements_256 = 0U,
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elements_512 = 1U,
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elements_1024 = 2U,
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elements_2048 = 3U
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};
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/** @enum emif_port
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* @brief Alias for emif port
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*
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*/
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enum emif_port
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{
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emif_8_bit_port = 0U,
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emif_16_bit_port = 1U
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};
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/** @enum emif_pagesize
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* @brief Alias for emif pagesize
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*
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*/
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enum emif_pagesize
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{
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emif_4_words = 0U,
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emif_8_words = 1U
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};
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/** @enum emif_wait_polarity
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* @brief Alias for emif wait polarity
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*
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*/
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enum emif_wait_polarity
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{
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emif_pin_low = 0U,
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emif_pin_high = 1U
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};
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#define PTR (uint32 *)(0x80000000U)
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/**
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* @defgroup EMIF EMIF
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* @brief Error Signaling Module.
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*
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* This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories utilizing a 16-bit
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* data bus. The purpose of this EMIF is to provide a means for the CPU to connect to a variety of external
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* devices including:
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* - Single data rate (SDR) SDRAM
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* - Asynchronous devices including NOR Flash and SRAM
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* The most common use for the EMIF is to interface with both a flash device and an SDRAM device
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* simultaneously. contains an example of operating the EMIF in this configuration.
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*
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* Related Files
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* - reg_emif.h
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* - emif.h
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* - emif.c
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* @addtogroup EMIF
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* @{
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*/
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/* EMIF Interface Functions */
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void emif_SDRAMInit(void);
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void emif_ASYNC1Init(void);
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void emif_ASYNC2Init(void);
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void emif_ASYNC3Init(void);
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/**@}*/
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#endif /*EMIF_H_*/
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