287 lines
8.0 KiB
ArmAsm
287 lines
8.0 KiB
ArmAsm
/*
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* File : start.S
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://openlab.rt-thread.com/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2008-12-11 XuXinming first version
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* 2011-03-17 Bernard update to 0.4.x
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*/
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#define WDMOD (0xE0000000 + 0x00)
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#define VICIntEnClr (0xFFFFF000 + 0x014)
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#define VICVectAddr (0xFFFFF000 + 0xF00)
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#define VICIntSelect (0xFFFFF000 + 0x00C)
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#define PLLCFG (0xE01FC000 + 0x084)
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#define PLLCON (0xE01FC000 + 0x080)
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#define PLLFEED (0xE01FC000 + 0x08C)
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#define PLLSTAT (0xE01FC000 + 0x088)
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#define CCLKCFG (0xE01FC000 + 0x104)
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#define MEMMAP (0xE01FC000 + 0x040)
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#define SCS (0xE01FC000 + 0x1A0)
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#define CLKSRCSEL (0xE01FC000 + 0x10C)
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#define MAMCR (0xE01FC000 + 0x000)
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#define MAMTIM (0xE01FC000 + 0x004)
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/* stack memory */
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.section .bss.noinit
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.equ IRQ_STACK_SIZE, 0x00000200
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.equ FIQ_STACK_SIZE, 0x00000100
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.equ UDF_STACK_SIZE, 0x00000004
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.equ ABT_STACK_SIZE, 0x00000004
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.equ SVC_STACK_SIZE, 0x00000200
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.space IRQ_STACK_SIZE
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IRQ_STACK:
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.space FIQ_STACK_SIZE
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FIQ_STACK:
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.space UDF_STACK_SIZE
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UDF_STACK:
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.space ABT_STACK_SIZE
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ABT_STACK:
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.space SVC_STACK_SIZE
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SVC_STACK:
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.section .init, "ax"
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.code 32
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.globl _start
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_start:
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b reset
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ldr pc, _vector_undef
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ldr pc, _vector_swi
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ldr pc, _vector_pabt
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ldr pc, _vector_dabt
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ldr pc, _vector_resv
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ldr pc, _vector_irq
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ldr pc, _vector_fiq
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_vector_undef: .word vector_undef
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_vector_swi: .word vector_swi
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_vector_pabt: .word vector_pabt
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_vector_dabt: .word vector_dabt
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_vector_resv: .word vector_resv
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_vector_irq: .word vector_irq
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_vector_fiq: .word vector_fiq
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.balignl 16,0xdeadbeef
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/*
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* rtthread kernel start and end
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* which are defined in linker script
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*/
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.globl _rtthread_start
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_rtthread_start:
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.word _start
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.globl _rtthread_end
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_rtthread_end:
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.word _end
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/*
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* rtthread bss start and end which are defined in linker script
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*/
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.globl _bss_start
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_bss_start:
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.word __bss_start
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.globl _bss_end
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_bss_end:
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.word __bss_end
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.text
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.code 32
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/* the system entry */
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reset:
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/* enter svc mode */
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msr cpsr_c, #SVCMODE|NOINT
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/*watch dog disable */
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ldr r0,=WDMOD
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ldr r1,=0x0
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str r1,[r0]
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/* all interrupt disable */
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ldr r0,=VICIntEnClr
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ldr r1,=0xffffffff
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str r1,[r0]
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ldr r1, =VICVectAddr
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ldr r0, =0x00
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str r0, [r1]
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ldr r1, =VICIntSelect
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ldr r0, =0x00
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str r0, [r1]
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/* setup stack */
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bl stack_setup
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/* copy .data to SRAM */
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ldr r1, =_sidata /* .data start in image */
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ldr r2, =_edata /* .data end in image */
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ldr r3, =_sdata /* sram data start */
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data_loop:
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ldr r0, [r1, #0]
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str r0, [r3]
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add r1, r1, #4
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add r3, r3, #4
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cmp r3, r2 /* check if data to clear */
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blo data_loop /* loop until done */
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/* clear .bss */
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start /* bss start */
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ldr r2,=__bss_end /* bss end */
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bss_loop:
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cmp r1,r2 /* check if data to clear */
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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/* call C++ constructors of global objects */
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r1}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r1}
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b ctor_loop
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ctor_end:
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/* start RT-Thread Kernel */
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ldr pc, _rtthread_startup
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_rtthread_startup:
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.word rtthread_startup
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.equ USERMODE, 0x10
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.equ FIQMODE, 0x11
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.equ IRQMODE, 0x12
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.equ SVCMODE, 0x13
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.equ ABORTMODE, 0x17
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.equ UNDEFMODE, 0x1b
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.equ MODEMASK, 0x1f
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.equ NOINT, 0xc0
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/* exception handlers */
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vector_undef: bl rt_hw_trap_udef
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vector_swi: bl rt_hw_trap_swi
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vector_pabt: bl rt_hw_trap_pabt
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vector_dabt: bl rt_hw_trap_dabt
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vector_resv: bl rt_hw_trap_resv
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.globl rt_interrupt_enter
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.globl rt_interrupt_leave
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.globl rt_thread_switch_interrput_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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vector_irq:
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stmfd sp!, {r0-r12,lr}
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bl rt_interrupt_enter
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bl rt_hw_trap_irq
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bl rt_interrupt_leave
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/* if rt_thread_switch_interrput_flag set,
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* jump to _interrupt_thread_switch and don't return
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*/
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ldr r0, =rt_thread_switch_interrput_flag
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ldr r1, [r0]
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cmp r1, #1
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beq _interrupt_thread_switch
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ldmfd sp!, {r0-r12,lr}
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subs pc, lr, #4
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.align 5
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vector_fiq:
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stmfd sp!,{r0-r7,lr}
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bl rt_hw_trap_fiq
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ldmfd sp!,{r0-r7,lr}
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subs pc,lr,#4
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_interrupt_thread_switch:
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mov r1, #0 /* clear rt_thread_switch_interrput_flag */
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str r1, [r0]
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ldmfd sp!, {r0-r12,lr} /* reload saved registers */
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stmfd sp!, {r0-r3} /* save r0-r3 */
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mov r1, sp
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add sp, sp, #16 /* restore sp */
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sub r2, lr, #4 /* save old task's pc to r2 */
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mrs r3, spsr /* disable interrupt */
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orr r0, r3, #NOINT
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msr spsr_c, r0
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ldr r0, =.+8 /* switch to interrupted task's stack */
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movs pc, r0
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stmfd sp!, {r2} /* push old task's pc */
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stmfd sp!, {r4-r12,lr} /* push old task's lr,r12-r4 */
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mov r4, r1 /* Special optimised code below */
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mov r5, r3
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ldmfd r4!, {r0-r3}
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stmfd sp!, {r0-r3} /* push old task's r3-r0 */
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stmfd sp!, {r5} /* push old task's psr */
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mrs r4, spsr
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stmfd sp!, {r4} /* push old task's spsr */
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ldr r4, =rt_interrupt_from_thread
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ldr r5, [r4]
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str sp, [r5] /* store sp in preempted tasks's TCB */
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ldr r6, =rt_interrupt_to_thread
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ldr r6, [r6]
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ldr sp, [r6] /* get new task's stack pointer */
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ldmfd sp!, {r4} /* pop new task's spsr */
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msr SPSR_cxsf, r4
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ldmfd sp!, {r4} /* pop new task's psr */
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msr CPSR_cxsf, r4
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ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */
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stack_setup:
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mrs r0, cpsr
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bic r0, r0, #MODEMASK
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orr r1, r0, #UNDEFMODE|NOINT
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msr cpsr_cxsf, r1 /* undef mode */
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ldr sp, =UDF_STACK
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orr r1,r0,#ABORTMODE|NOINT
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msr cpsr_cxsf,r1 /* abort mode */
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ldr sp, =ABT_STACK
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orr r1,r0,#IRQMODE|NOINT
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msr cpsr_cxsf,r1 /* IRQ mode */
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ldr sp, =IRQ_STACK
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orr r1,r0,#FIQMODE|NOINT
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msr cpsr_cxsf,r1 /* FIQ mode */
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ldr sp, =FIQ_STACK
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bic r0,r0,#MODEMASK
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orr r1,r0,#SVCMODE|NOINT
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msr cpsr_cxsf,r1 /* SVC mode */
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ldr sp, =SVC_STACK
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/* USER mode is not initialized. */
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mov pc,lr /* The LR register may be not valid for the mode changes.*/
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