460 lines
16 KiB
C
460 lines
16 KiB
C
/*!
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*******************************************************************************
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**
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** \file gh_wdt.h
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**
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** \brief Watch Dog Timer.
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**
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** Copyright: 2012 - 2013 (C) GoKe Microelectronics ShangHai Branch
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**
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** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS
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** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
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** OMMISSIONS.
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**
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** \note Do not modify this file as it is generated automatically.
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**
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******************************************************************************/
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#ifndef _GH_WDT_H
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#define _GH_WDT_H
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#ifdef __LINUX__
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#include "reg4linux.h"
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#else
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#define FIO_ADDRESS(block,address) (address)
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#define FIO_MOFFSET(block,moffset) (moffset)
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#endif
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#ifndef __LINUX__
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#include "gtypes.h" /* global type definitions */
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#include "gh_lib_cfg.h" /* configuration */
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#endif
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#define GH_WDT_ENABLE_DEBUG_PRINT 0
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#ifdef __LINUX__
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#define GH_WDT_DEBUG_PRINT_FUNCTION printk
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#else
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#define GH_WDT_DEBUG_PRINT_FUNCTION printf
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#endif
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#ifndef __LINUX__
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#if GH_WDT_ENABLE_DEBUG_PRINT
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#include <stdio.h>
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#endif
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#endif
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/* check configuration */
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#ifndef GH_INLINE_LEVEL
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#error "GH_INLINE_LEVEL is not defined!"
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#endif
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#if GH_INLINE_LEVEL > 2
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#error "GH_INLINE_LEVEL must be set 0, 1 or 2!"
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#endif
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#ifndef GH_INLINE
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#error "GH_INLINE is not defined!"
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#endif
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/* disable inlining for debugging */
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#ifdef DEBUG
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#undef GH_INLINE_LEVEL
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#define GH_INLINE_LEVEL 0
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#endif
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/*----------------------------------------------------------------------------*/
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/* registers */
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/*----------------------------------------------------------------------------*/
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#define REG_WDT_CTRLR FIO_ADDRESS(WDT,0xA0006000) /* read/write */
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#define REG_WDT_TIMEOUTR FIO_ADDRESS(WDT,0xA0006004) /* read */
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#define REG_WDT_CLRR FIO_ADDRESS(WDT,0xA0006008) /* write */
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#define REG_WDT_CNTSTSR FIO_ADDRESS(WDT,0xA000600C) /* read */
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#define REG_WDT_RELOADR FIO_ADDRESS(WDT,0xA0006010) /* read/write */
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#define REG_WDT_RESTARTR FIO_ADDRESS(WDT,0xA0006014) /* write */
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#define REG_WDT_RSTWDR FIO_ADDRESS(WDT,0xA0006018) /* read/write */
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/*----------------------------------------------------------------------------*/
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/* bit group structures */
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/*----------------------------------------------------------------------------*/
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typedef union { /* WDT_CtrlR */
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U32 all;
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struct {
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U32 enable : 1;
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U32 intenable : 1;
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U32 resetenable : 1;
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U32 : 29;
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} bitc;
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} GH_WDT_CTRLR_S;
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typedef union { /* WDT_TimeoutR */
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U32 all;
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struct {
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U32 timeout : 1;
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U32 : 31;
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} bitc;
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} GH_WDT_TIMEOUTR_S;
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typedef union { /* WDT_ClrR */
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U32 all;
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struct {
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U32 clr : 1;
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U32 : 31;
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} bitc;
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} GH_WDT_CLRR_S;
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typedef union { /* WDT_RstWdR */
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U32 all;
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struct {
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U32 rstwd : 8;
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U32 : 24;
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} bitc;
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} GH_WDT_RSTWDR_S;
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/*----------------------------------------------------------------------------*/
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/* mirror variables */
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/*----------------------------------------------------------------------------*/
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extern GH_WDT_CLRR_S m_wdt_clrr;
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extern U32 m_wdt_restartr;
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* register WDT_CtrlR (read/write) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Writes the register 'WDT_CtrlR'. */
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void GH_WDT_set_CtrlR(U32 data);
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/*! \brief Reads the register 'WDT_CtrlR'. */
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U32 GH_WDT_get_CtrlR(void);
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/*! \brief Writes the bit group 'Enable' of register 'WDT_CtrlR'. */
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void GH_WDT_set_CtrlR_Enable(U8 data);
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/*! \brief Reads the bit group 'Enable' of register 'WDT_CtrlR'. */
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U8 GH_WDT_get_CtrlR_Enable(void);
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/*! \brief Writes the bit group 'IntEnable' of register 'WDT_CtrlR'. */
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void GH_WDT_set_CtrlR_IntEnable(U8 data);
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/*! \brief Reads the bit group 'IntEnable' of register 'WDT_CtrlR'. */
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U8 GH_WDT_get_CtrlR_IntEnable(void);
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/*! \brief Writes the bit group 'ResetEnable' of register 'WDT_CtrlR'. */
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void GH_WDT_set_CtrlR_ResetEnable(U8 data);
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/*! \brief Reads the bit group 'ResetEnable' of register 'WDT_CtrlR'. */
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U8 GH_WDT_get_CtrlR_ResetEnable(void);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE void GH_WDT_set_CtrlR(U32 data)
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{
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*(volatile U32 *)REG_WDT_CTRLR = data;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_WDT_set_CtrlR] <-- 0x%08x\n",
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REG_WDT_CTRLR,data,data);
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#endif
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}
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GH_INLINE U32 GH_WDT_get_CtrlR(void)
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{
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U32 value = (*(volatile U32 *)REG_WDT_CTRLR);
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_WDT_get_CtrlR] --> 0x%08x\n",
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REG_WDT_CTRLR,value);
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#endif
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return value;
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}
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GH_INLINE void GH_WDT_set_CtrlR_Enable(U8 data)
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{
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GH_WDT_CTRLR_S d;
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d.all = *(volatile U32 *)REG_WDT_CTRLR;
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d.bitc.enable = data;
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*(volatile U32 *)REG_WDT_CTRLR = d.all;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_WDT_set_CtrlR_Enable] <-- 0x%08x\n",
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REG_WDT_CTRLR,d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_WDT_get_CtrlR_Enable(void)
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{
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GH_WDT_CTRLR_S tmp_value;
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U32 value = (*(volatile U32 *)REG_WDT_CTRLR);
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tmp_value.all = value;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_WDT_get_CtrlR_Enable] --> 0x%08x\n",
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REG_WDT_CTRLR,value);
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#endif
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return tmp_value.bitc.enable;
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}
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GH_INLINE void GH_WDT_set_CtrlR_IntEnable(U8 data)
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{
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GH_WDT_CTRLR_S d;
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d.all = *(volatile U32 *)REG_WDT_CTRLR;
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d.bitc.intenable = data;
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*(volatile U32 *)REG_WDT_CTRLR = d.all;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_WDT_set_CtrlR_IntEnable] <-- 0x%08x\n",
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REG_WDT_CTRLR,d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_WDT_get_CtrlR_IntEnable(void)
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{
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GH_WDT_CTRLR_S tmp_value;
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U32 value = (*(volatile U32 *)REG_WDT_CTRLR);
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tmp_value.all = value;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_WDT_get_CtrlR_IntEnable] --> 0x%08x\n",
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REG_WDT_CTRLR,value);
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#endif
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return tmp_value.bitc.intenable;
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}
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GH_INLINE void GH_WDT_set_CtrlR_ResetEnable(U8 data)
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{
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GH_WDT_CTRLR_S d;
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d.all = *(volatile U32 *)REG_WDT_CTRLR;
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d.bitc.resetenable = data;
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*(volatile U32 *)REG_WDT_CTRLR = d.all;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_WDT_set_CtrlR_ResetEnable] <-- 0x%08x\n",
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REG_WDT_CTRLR,d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_WDT_get_CtrlR_ResetEnable(void)
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{
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GH_WDT_CTRLR_S tmp_value;
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U32 value = (*(volatile U32 *)REG_WDT_CTRLR);
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tmp_value.all = value;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_WDT_get_CtrlR_ResetEnable] --> 0x%08x\n",
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REG_WDT_CTRLR,value);
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#endif
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return tmp_value.bitc.resetenable;
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}
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#endif /* GH_INLINE_LEVEL == 0 */
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/*----------------------------------------------------------------------------*/
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/* register WDT_TimeoutR (read) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Reads the register 'WDT_TimeoutR'. */
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U32 GH_WDT_get_TimeoutR(void);
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/*! \brief Reads the bit group 'Timeout' of register 'WDT_TimeoutR'. */
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U8 GH_WDT_get_TimeoutR_Timeout(void);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE U32 GH_WDT_get_TimeoutR(void)
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{
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U32 value = (*(volatile U32 *)REG_WDT_TIMEOUTR);
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_WDT_get_TimeoutR] --> 0x%08x\n",
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REG_WDT_TIMEOUTR,value);
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#endif
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return value;
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}
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GH_INLINE U8 GH_WDT_get_TimeoutR_Timeout(void)
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{
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GH_WDT_TIMEOUTR_S tmp_value;
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U32 value = (*(volatile U32 *)REG_WDT_TIMEOUTR);
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tmp_value.all = value;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_WDT_get_TimeoutR_Timeout] --> 0x%08x\n",
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REG_WDT_TIMEOUTR,value);
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#endif
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return tmp_value.bitc.timeout;
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}
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#endif /* GH_INLINE_LEVEL == 0 */
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/*----------------------------------------------------------------------------*/
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/* register WDT_ClrR (write) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL < 2
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/*! \brief Writes the register 'WDT_ClrR'. */
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void GH_WDT_set_ClrR(U32 data);
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/*! \brief Reads the mirror variable of the register 'WDT_ClrR'. */
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U32 GH_WDT_getm_ClrR(void);
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/*! \brief Writes the bit group 'Clr' of register 'WDT_ClrR'. */
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void GH_WDT_set_ClrR_Clr(U8 data);
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/*! \brief Reads the bit group 'Clr' from the mirror variable of register 'WDT_ClrR'. */
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U8 GH_WDT_getm_ClrR_Clr(void);
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#else /* GH_INLINE_LEVEL < 2 */
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GH_INLINE void GH_WDT_set_ClrR(U32 data)
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{
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m_wdt_clrr.all = data;
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*(volatile U32 *)REG_WDT_CLRR = data;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_WDT_set_ClrR] <-- 0x%08x\n",
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REG_WDT_CLRR,data,data);
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#endif
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}
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GH_INLINE U32 GH_WDT_getm_ClrR(void)
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{
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "[GH_WDT_getm_ClrR] --> 0x%08x\n",
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m_wdt_clrr.all);
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#endif
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return m_wdt_clrr.all;
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}
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GH_INLINE void GH_WDT_set_ClrR_Clr(U8 data)
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{
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m_wdt_clrr.bitc.clr = data;
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*(volatile U32 *)REG_WDT_CLRR = m_wdt_clrr.all;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_WDT_set_ClrR_Clr] <-- 0x%08x\n",
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REG_WDT_CLRR,m_wdt_clrr.all,m_wdt_clrr.all);
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#endif
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}
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GH_INLINE U8 GH_WDT_getm_ClrR_Clr(void)
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{
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "[GH_WDT_getm_ClrR_Clr] --> 0x%08x\n",
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m_wdt_clrr.bitc.clr);
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#endif
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return m_wdt_clrr.bitc.clr;
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}
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#endif /* GH_INLINE_LEVEL < 2 */
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/*----------------------------------------------------------------------------*/
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/* register WDT_CntStsR (read) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Reads the register 'WDT_CntStsR'. */
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U32 GH_WDT_get_CntStsR(void);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE U32 GH_WDT_get_CntStsR(void)
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{
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U32 value = (*(volatile U32 *)REG_WDT_CNTSTSR);
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_WDT_get_CntStsR] --> 0x%08x\n",
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REG_WDT_CNTSTSR,value);
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#endif
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return value;
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}
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#endif /* GH_INLINE_LEVEL == 0 */
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/*----------------------------------------------------------------------------*/
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/* register WDT_ReloadR (read/write) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Writes the register 'WDT_ReloadR'. */
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void GH_WDT_set_ReloadR(U32 data);
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/*! \brief Reads the register 'WDT_ReloadR'. */
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U32 GH_WDT_get_ReloadR(void);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE void GH_WDT_set_ReloadR(U32 data)
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{
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*(volatile U32 *)REG_WDT_RELOADR = data;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_WDT_set_ReloadR] <-- 0x%08x\n",
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REG_WDT_RELOADR,data,data);
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#endif
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}
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GH_INLINE U32 GH_WDT_get_ReloadR(void)
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{
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U32 value = (*(volatile U32 *)REG_WDT_RELOADR);
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_WDT_get_ReloadR] --> 0x%08x\n",
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REG_WDT_RELOADR,value);
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#endif
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return value;
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}
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#endif /* GH_INLINE_LEVEL == 0 */
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/*----------------------------------------------------------------------------*/
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/* register WDT_RestartR (write) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL < 2
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/*! \brief Writes the register 'WDT_RestartR'. */
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void GH_WDT_set_RestartR(U32 data);
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/*! \brief Reads the mirror variable of the register 'WDT_RestartR'. */
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U32 GH_WDT_getm_RestartR(void);
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#else /* GH_INLINE_LEVEL < 2 */
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GH_INLINE void GH_WDT_set_RestartR(U32 data)
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{
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m_wdt_restartr = data;
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*(volatile U32 *)REG_WDT_RESTARTR = data;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_WDT_set_RestartR] <-- 0x%08x\n",
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REG_WDT_RESTARTR,data,data);
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#endif
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}
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GH_INLINE U32 GH_WDT_getm_RestartR(void)
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{
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "[GH_WDT_getm_RestartR] --> 0x%08x\n",
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m_wdt_restartr);
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#endif
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return m_wdt_restartr;
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}
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#endif /* GH_INLINE_LEVEL < 2 */
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/*----------------------------------------------------------------------------*/
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/* register WDT_RstWdR (read/write) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Writes the register 'WDT_RstWdR'. */
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void GH_WDT_set_RstWdR(U32 data);
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/*! \brief Reads the register 'WDT_RstWdR'. */
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U32 GH_WDT_get_RstWdR(void);
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/*! \brief Writes the bit group 'RstWd' of register 'WDT_RstWdR'. */
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void GH_WDT_set_RstWdR_RstWd(U8 data);
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/*! \brief Reads the bit group 'RstWd' of register 'WDT_RstWdR'. */
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U8 GH_WDT_get_RstWdR_RstWd(void);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE void GH_WDT_set_RstWdR(U32 data)
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{
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*(volatile U32 *)REG_WDT_RSTWDR = data;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_WDT_set_RstWdR] <-- 0x%08x\n",
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REG_WDT_RSTWDR,data,data);
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#endif
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}
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GH_INLINE U32 GH_WDT_get_RstWdR(void)
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{
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U32 value = (*(volatile U32 *)REG_WDT_RSTWDR);
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_WDT_get_RstWdR] --> 0x%08x\n",
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REG_WDT_RSTWDR,value);
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#endif
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return value;
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}
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GH_INLINE void GH_WDT_set_RstWdR_RstWd(U8 data)
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{
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GH_WDT_RSTWDR_S d;
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d.all = *(volatile U32 *)REG_WDT_RSTWDR;
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d.bitc.rstwd = data;
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*(volatile U32 *)REG_WDT_RSTWDR = d.all;
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#if GH_WDT_ENABLE_DEBUG_PRINT
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GH_WDT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_WDT_set_RstWdR_RstWd] <-- 0x%08x\n",
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REG_WDT_RSTWDR,d.all,d.all);
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#endif
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}
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|
GH_INLINE U8 GH_WDT_get_RstWdR_RstWd(void)
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|
{
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|
GH_WDT_RSTWDR_S tmp_value;
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|
U32 value = (*(volatile U32 *)REG_WDT_RSTWDR);
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|
|
|
tmp_value.all = value;
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|
#if GH_WDT_ENABLE_DEBUG_PRINT
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|
GH_WDT_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_WDT_get_RstWdR_RstWd] --> 0x%08x\n",
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|
REG_WDT_RSTWDR,value);
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|
#endif
|
|
return tmp_value.bitc.rstwd;
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|
}
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* init function */
|
|
/*----------------------------------------------------------------------------*/
|
|
/*! \brief Initialises the registers and mirror variables. */
|
|
void GH_WDT_init(void);
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _GH_WDT_H */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* end of file */
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|
/*----------------------------------------------------------------------------*/
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|
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