1137 lines
27 KiB
C
1137 lines
27 KiB
C
/******************************************************************//**
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* @file drv_usart.c
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* @brief USART driver of RT-Thread RTOS for EFM32
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* COPYRIGHT (C) 2011, RT-Thread Development Team
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* @author onelife
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* @version 0.4 beta
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**********************************************************************
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* @section License
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* The license and distribution terms for this file may be found in the file LICENSE in this
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* distribution or at http://www.rt-thread.org/license/LICENSE
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**********************************************************************
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* @section Change Logs
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* Date Author Notes
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* 2010-12-22 onelife Initial creation for EFM32
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* 2011-01-17 onelife Merge with serial.c
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* 2011-05-06 onelife Add sync mode (SPI) support
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*
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* @section Change Logs of serial.c
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* 2009-02-05 Bernard first version
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* 2009-10-25 Bernard fix rt_serial_read bug when there is no data in the buffer.
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* 2010-03-29 Bernard cleanup code.
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*********************************************************************/
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/******************************************************************//**
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* @addtogroup efm32
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* @{
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*********************************************************************/
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/* Includes -------------------------------------------------------------------*/
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#include "board.h"
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#include "hdl_interrupt.h"
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#include "drv_usart.h"
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/* Private typedef -------------------------------------------------------------*/
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union efm32_usart_init_t
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{
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USART_InitAsync_TypeDef async;
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USART_InitSync_TypeDef sync;
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};
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/* Private define --------------------------------------------------------------*/
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/* Private macro --------------------------------------------------------------*/
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#ifdef RT_USART_DEBUG
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#define usart_debug(format,args...) rt_kprintf(format, ##args)
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#else
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#define usart_debug(format,args...)
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#endif
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/* Private variables ------------------------------------------------------------*/
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#ifdef RT_USING_USART0
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#if (RT_USING_USART0 > 3)
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#error "The location number range of usart is 0~3"
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#endif
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struct rt_device usart0_device;
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#endif
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#ifdef RT_USING_USART1
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#if (RT_USING_USART1 > 3)
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#error "The location number range of usart is 0~3"
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#endif
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struct rt_device usart1_device;
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#endif
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#ifdef RT_USING_USART2
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#if (RT_USING_USART2 > 3)
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#error "The location number range of usart is 0~3"
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#endif
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struct rt_device usart2_device;
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#endif
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/* Private function prototypes ---------------------------------------------------*/
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/* Private functions ------------------------------------------------------------*/
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/******************************************************************//**
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* @brief
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* Initialize USART device
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*
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* @details
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*
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* @note
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*
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* @param[in] dev
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* Pointer to device descriptor
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*
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* @return
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* Error code
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*********************************************************************/
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static rt_err_t rt_usart_init (rt_device_t dev)
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{
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struct efm32_usart_device_t *usart;
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usart = (struct efm32_usart_device_t *)(dev->user_data);
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if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
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{
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if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
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{
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struct efm32_usart_dma_mode_t *dma_tx;
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dma_tx = (struct efm32_usart_dma_mode_t *)(usart->tx_mode);
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usart->state |= USART_STATE_RX_BUSY;
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}
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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struct efm32_usart_int_mode_t *int_rx;
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int_rx = (struct efm32_usart_int_mode_t *)(usart->rx_mode);
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int_rx->data_ptr = RT_NULL;
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}
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/* Enable USART */
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USART_Enable(usart->usart_device, usartEnable);
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dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
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}
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return RT_EOK;
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}
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/******************************************************************//**
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* @brief
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* Open USART device
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*
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* @details
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*
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* @note
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*
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* @param[in] dev
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* Pointer to device descriptor
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*
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* @param[in] oflag
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* Device open flag
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*
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* @return
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* Error code
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*********************************************************************/
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static rt_err_t rt_usart_open(rt_device_t dev, rt_uint16_t oflag)
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{
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RT_ASSERT(dev != RT_NULL);
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struct efm32_usart_device_t *usart;
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usart = (struct efm32_usart_device_t *)(dev->user_data);
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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IRQn_Type rxIrq;
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//if (usart->state & USART_STATE_CONSOLE)
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{ /* Allocate new RX buffer */
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struct efm32_usart_int_mode_t *int_mode;
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int_mode = (struct efm32_usart_int_mode_t *)(usart->rx_mode);
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if ((int_mode->data_ptr = rt_malloc(USART_RX_BUFFER_SIZE)) == RT_NULL)
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{
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usart_debug("USART: no memory for RX buffer\n");
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return -RT_ENOMEM;
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}
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rt_memset(int_mode->data_ptr, 0, USART_RX_BUFFER_SIZE);
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int_mode->data_size = USART_RX_BUFFER_SIZE;
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int_mode->read_index = 0;
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int_mode->save_index = 0;
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}
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/* Enable TX/RX interrupt */
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switch (usart->unit)
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{
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case 0:
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rxIrq = USART0_RX_IRQn;
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break;
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case 1:
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rxIrq = USART1_RX_IRQn;
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break;
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case 2:
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rxIrq = USART2_RX_IRQn;
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break;
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}
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/* Enable RX interrupts */
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usart->usart_device->IEN = USART_IEN_RXDATAV;
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/* Enable IRQ */
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if (oflag != RT_DEVICE_OFLAG_WRONLY)
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{
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NVIC_ClearPendingIRQ(rxIrq);
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NVIC_SetPriority(rxIrq, EFM32_IRQ_PRI_DEFAULT);
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NVIC_EnableIRQ(rxIrq);
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}
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}
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usart->usart_device->IFC = _USART_IFC_MASK;
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if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (oflag != RT_DEVICE_OFLAG_RDONLY))
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{
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/* DMA IRQ is enabled by DMA_Init() */
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NVIC_SetPriority(DMA_IRQn, EFM32_IRQ_PRI_DEFAULT);
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}
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usart_debug("USART%d: Open with flag %x\n", usart->unit, oflag);
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return RT_EOK;
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}
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/******************************************************************//**
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* @brief
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* Close USART device
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*
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* @details
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*
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* @note
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*
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* @param[in] dev
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* Pointer to device descriptor
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*
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* @return
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* Error code
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*********************************************************************/
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static rt_err_t rt_usart_close(rt_device_t dev)
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{
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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struct efm32_usart_int_mode_t *int_rx;
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int_rx = (struct efm32_usart_int_mode_t *)\
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(((struct efm32_usart_device_t *)(dev->user_data))->rx_mode);
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rt_free(int_rx->data_ptr);
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int_rx->data_ptr = RT_NULL;
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}
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return RT_EOK;
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}
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/******************************************************************//**
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* @brief
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* Read from USART device
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*
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* @details
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*
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* @note
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*
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* @param[in] dev
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* Pointer to device descriptor
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*
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* @param[in] pos
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* Offset
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*
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* @param[in] buffer
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* Poniter to the buffer
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*
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* @param[in] size
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* Buffer size in byte
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*
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* @return
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* Error code
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*********************************************************************/
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static rt_size_t rt_usart_read (
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rt_device_t dev,
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rt_off_t pos,
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void *buffer,
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rt_size_t size)
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{
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rt_uint8_t *ptr;
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rt_err_t err_code;
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rt_size_t read_len;
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err_code = RT_EOK;
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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ptr = buffer;
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/* interrupt mode Rx */
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while (size)
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{
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rt_base_t level;
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struct efm32_usart_int_mode_t *int_rx;
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int_rx = (struct efm32_usart_int_mode_t *)\
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(((struct efm32_usart_device_t *)(dev->user_data))->rx_mode);
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/* disable interrupt */
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level = rt_hw_interrupt_disable();
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if (int_rx->read_index != int_rx->save_index)
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{
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/* read a character */
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*ptr++ = int_rx->data_ptr[int_rx->read_index];
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size--;
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/* move to next position */
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int_rx->read_index ++;
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if (int_rx->read_index >= USART_RX_BUFFER_SIZE)
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{
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int_rx->read_index = 0;
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}
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}
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else
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{
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/* set error code */
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err_code = -RT_EEMPTY;
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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break;
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}
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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}
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read_len = (rt_uint32_t)ptr - (rt_uint32_t)buffer;
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}
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else
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{
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RT_ASSERT(buffer != RT_NULL);
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struct efm32_usart_device_t *usart;
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USART_TypeDef *usart_device;
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usart = (struct efm32_usart_device_t *)(dev->user_data);
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usart_device = ((struct efm32_usart_device_t *)(dev->user_data))->usart_device;
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if (usart->state & USART_STATE_SYNC)
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{
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/* SPI read */
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rt_uint8_t inst_len = *((rt_uint8_t *)buffer);
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rt_uint8_t *inst_ptr = (rt_uint8_t *)(buffer + 1);
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rt_uint8_t *rx_buf = *((rt_uint8_t **)(buffer + inst_len + 1));
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ptr = rx_buf;
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/* write instruction */
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while (inst_len)
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{
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while (!(usart->usart_device->STATUS & USART_STATUS_TXBL));
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usart->usart_device->TXDATA = (rt_uint32_t)*inst_ptr;
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++inst_ptr; --inst_len;
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}
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/* Flushing RX */
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usart_device->CMD = USART_CMD_CLEARRX;
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/* dummy write */
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while (!(usart_device->STATUS & USART_STATUS_TXBL));
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usart_device->TXDATA = (rt_uint32_t)0x00;
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/* dummy read */
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while (!(usart_device->STATUS & USART_STATUS_RXDATAV));
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*((rt_uint32_t *)0x00) = usart_device->RXDATA;
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while ((rt_uint32_t)ptr - (rt_uint32_t)rx_buf < size)
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{
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/* dummy write */
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while (!(usart_device->STATUS & USART_STATUS_TXBL));
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usart_device->TXDATA = (rt_uint32_t)0x00;
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/* read a byte of data */
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while (!(usart_device->STATUS & USART_STATUS_RXDATAV));
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*ptr = usart_device->RXDATA & 0xff;
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ptr ++;
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}
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}
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else
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{
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ptr = buffer;
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/* polling mode */
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while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
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{
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while (usart_device->STATUS & USART_STATUS_RXDATAV)
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{
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*ptr = usart_device->RXDATA & 0xff;
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ptr ++;
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}
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}
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}
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read_len = size;
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}
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/* set error code */
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rt_set_errno(err_code);
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return read_len;
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}
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/******************************************************************//**
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* @brief
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* Write to USART device
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*
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* @details
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*
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* @note
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*
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* @param[in] dev
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* Pointer to device descriptor
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*
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* @param[in] pos
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* Offset
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*
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* @param[in] buffer
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* Poniter to the buffer
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*
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* @param[in] size
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* Buffer size in byte
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*
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* @return
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* Number of written bytes
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*********************************************************************/
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static rt_size_t rt_usart_write (
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rt_device_t dev,
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rt_off_t pos,
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const void* buffer,
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rt_size_t size)
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{
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rt_err_t err_code;
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rt_size_t write_size;
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struct efm32_usart_device_t* usart;
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err_code = RT_EOK;
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write_size = 0;
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usart = (struct efm32_usart_device_t*)(dev->user_data);
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if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (size > 1))
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{ /* DMA mode Tx */
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struct efm32_usart_dma_mode_t *dma_tx;
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if (dev->flag & RT_DEVICE_FLAG_STREAM)
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{
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*((rt_uint8_t *)buffer + size++) = '\r';
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*((rt_uint8_t *)buffer + size) = 0x0;
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}
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dma_tx = (struct efm32_usart_dma_mode_t *)(usart->tx_mode);
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dma_tx->data_ptr = (rt_uint32_t *)buffer;
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dma_tx->data_size = size;
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usart->state |= USART_STATE_TX_BUSY;
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DMA_ActivateBasic(
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dma_tx->dma_channel,
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true,
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false,
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(void *)&(usart->usart_device->TXDATA),
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buffer,
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size - 1);
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/* Wait, otherwise the TX buffer is overwrite */
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if (usart->state & USART_STATE_CONSOLE)
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{
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while(usart->state & USART_STATE_TX_BUSY);
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}
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else
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{
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while(usart->state & USART_STATE_TX_BUSY)
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{
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rt_thread_sleep(USART_WAIT_TIME_TX);
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}
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}
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write_size = size;
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}
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else
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{ /* polling mode */
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rt_uint8_t *ptr = (rt_uint8_t *)buffer;
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if (dev->flag & RT_DEVICE_FLAG_STREAM)
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{
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/* stream mode */
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while (size)
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{
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if (*ptr == '\n')
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{
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while (!(usart->usart_device->STATUS & USART_STATUS_TXBL));
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usart->usart_device->TXDATA = '\r';
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}
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while (!(usart->usart_device->STATUS & USART_STATUS_TXBL));
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usart->usart_device->TXDATA = (rt_uint32_t)*ptr;
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++ptr; --size;
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}
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}
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else
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{
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/* write data directly */
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while (size)
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{
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while (!(usart->usart_device->STATUS & USART_STATUS_TXBL));
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usart->usart_device->TXDATA = (rt_uint32_t)*ptr;
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++ptr; --size;
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}
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}
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write_size = (rt_size_t)ptr - (rt_size_t)buffer;
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}
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/* set error code */
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rt_set_errno(err_code);
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return write_size;
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}
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|
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/******************************************************************//**
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* @brief
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* Configure USART device
|
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*
|
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* @details
|
|
*
|
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* @note
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|
*
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* @param[in] dev
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* Pointer to device descriptor
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*
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* @param[in] cmd
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* IIC control command
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*
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* @param[in] args
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* Arguments
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*
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* @return
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* Error code
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*********************************************************************/
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static rt_err_t rt_usart_control (
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rt_device_t dev,
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rt_uint8_t cmd,
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void *args)
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{
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RT_ASSERT(dev != RT_NULL);
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struct efm32_usart_device_t *usart;
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usart = (struct efm32_usart_device_t *)(dev->user_data);
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switch (cmd)
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{
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case RT_DEVICE_CTRL_SUSPEND:
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/* Suspend device */
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dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
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USART_Enable(usart->usart_device, usartDisable);
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break;
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case RT_DEVICE_CTRL_RESUME:
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/* Resume device */
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dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
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USART_Enable(usart->usart_device, usartEnable);
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break;
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|
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case RT_DEVICE_CTRL_USART_RBUFFER:
|
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/* Set RX buffer */
|
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{
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struct efm32_usart_int_mode_t *int_rx;
|
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rt_uint8_t size;
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|
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int_rx = (struct efm32_usart_int_mode_t *)(usart->rx_mode);
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size = (rt_uint8_t)((rt_uint32_t)args & 0xFFUL);
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|
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/* Free previous RX buffer */
|
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if (int_rx->data_ptr != RT_NULL)
|
|
{
|
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if (size == 0)
|
|
{ /* Free RX buffer */
|
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rt_free(int_rx->data_ptr);
|
|
int_rx->data_ptr = RT_NULL;
|
|
}
|
|
else if (size != int_rx->data_size)
|
|
{
|
|
/* Re-allocate RX buffer */
|
|
if ((int_rx->data_ptr = rt_realloc(int_rx->data_ptr, size)) \
|
|
== RT_NULL)
|
|
{
|
|
usart_debug("USART: no memory for RX buffer\n");
|
|
return -RT_ENOMEM;
|
|
}
|
|
// TODO: Is the following line necessary?
|
|
//rt_memset(int_rx->data_ptr, 0, size);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Allocate new RX buffer */
|
|
if ((int_rx->data_ptr = rt_malloc(size)) == RT_NULL)
|
|
{
|
|
usart_debug("USART: no memory for RX buffer\n");
|
|
return -RT_ENOMEM;
|
|
}
|
|
}
|
|
int_rx->data_size = size;
|
|
int_rx->read_index = 0;
|
|
int_rx->save_index = 0;
|
|
}
|
|
break;
|
|
|
|
}
|
|
|
|
return RT_EOK;
|
|
}
|
|
|
|
/******************************************************************//**
|
|
* @brief
|
|
* USART RX data valid interrupt handler
|
|
*
|
|
* @details
|
|
*
|
|
* @note
|
|
*
|
|
* @param[in] dev
|
|
* Pointer to device descriptor
|
|
*********************************************************************/
|
|
void rt_hw_usart_rx_isr(rt_device_t dev)
|
|
{
|
|
struct efm32_usart_device_t *usart;
|
|
struct efm32_usart_int_mode_t *int_rx;
|
|
|
|
/* interrupt mode receive */
|
|
RT_ASSERT(dev->flag & RT_DEVICE_FLAG_INT_RX);
|
|
|
|
usart = (struct efm32_usart_device_t *)(dev->user_data);
|
|
int_rx = (struct efm32_usart_int_mode_t *)(usart->rx_mode);
|
|
|
|
RT_ASSERT(int_rx->data_ptr != RT_NULL);
|
|
|
|
/* Set status */
|
|
usart->state |= USART_STATE_RX_BUSY;
|
|
|
|
/* save on rx buffer */
|
|
while (usart->usart_device->STATUS & USART_STATUS_RXDATAV)
|
|
{
|
|
rt_base_t level;
|
|
|
|
/* disable interrupt */
|
|
level = rt_hw_interrupt_disable();
|
|
|
|
/* save character */
|
|
int_rx->data_ptr[int_rx->save_index] = \
|
|
(rt_uint8_t)(usart->usart_device->RXDATA & 0xFFUL);
|
|
int_rx->save_index ++;
|
|
if (int_rx->save_index >= USART_RX_BUFFER_SIZE)
|
|
int_rx->save_index = 0;
|
|
|
|
/* if the next position is read index, discard this 'read char' */
|
|
if (int_rx->save_index == int_rx->read_index)
|
|
{
|
|
int_rx->read_index ++;
|
|
if (int_rx->read_index >= USART_RX_BUFFER_SIZE)
|
|
{
|
|
int_rx->read_index = 0;
|
|
}
|
|
}
|
|
|
|
/* enable interrupt */
|
|
rt_hw_interrupt_enable(level);
|
|
}
|
|
|
|
/* invoke callback */
|
|
if (dev->rx_indicate != RT_NULL)
|
|
{
|
|
rt_size_t rx_length;
|
|
|
|
/* get rx length */
|
|
rx_length = int_rx->read_index > int_rx->save_index ?
|
|
USART_RX_BUFFER_SIZE - int_rx->read_index + int_rx->save_index : \
|
|
int_rx->save_index - int_rx->read_index;
|
|
|
|
dev->rx_indicate(dev, rx_length);
|
|
}
|
|
}
|
|
|
|
/******************************************************************//**
|
|
* @brief
|
|
* DMA for USART TX interrupt handler
|
|
*
|
|
* @details
|
|
*
|
|
* @note
|
|
*
|
|
* @param[in] dev
|
|
* Pointer to device descriptor
|
|
*********************************************************************/
|
|
void rt_hw_usart_dma_tx_isr(rt_device_t dev)
|
|
{
|
|
/* DMA mode receive */
|
|
struct efm32_usart_device_t *usart;
|
|
struct efm32_usart_dma_mode_t *dma_tx;
|
|
|
|
RT_ASSERT(dev->flag & RT_DEVICE_FLAG_DMA_TX);
|
|
|
|
usart = (struct efm32_usart_device_t *)(dev->user_data);
|
|
dma_tx = (struct efm32_usart_dma_mode_t *)(usart->tx_mode);
|
|
|
|
/* invoke call to notify tx complete */
|
|
if (dev->tx_complete != RT_NULL)
|
|
{
|
|
dev->tx_complete(dev, dma_tx->data_ptr);
|
|
}
|
|
|
|
/* Set status */
|
|
usart->state &= ~(rt_uint32_t)USART_STATE_TX_BUSY;
|
|
}
|
|
|
|
/******************************************************************//**
|
|
* @brief
|
|
* Register USART device
|
|
*
|
|
* @details
|
|
*
|
|
* @note
|
|
*
|
|
* @param[in] device
|
|
* Pointer to device descriptor
|
|
*
|
|
* @param[in] name
|
|
* Device name
|
|
*
|
|
* @param[in] flag
|
|
* Configuration flags
|
|
*
|
|
* @param[in] usart
|
|
* Pointer to USART device descriptor
|
|
*
|
|
* @return
|
|
* Error code
|
|
*********************************************************************/
|
|
rt_err_t rt_hw_usart_register(
|
|
rt_device_t device,
|
|
const char *name,
|
|
rt_uint32_t flag,
|
|
struct efm32_usart_device_t *usart)
|
|
{
|
|
RT_ASSERT(device != RT_NULL);
|
|
|
|
if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
|
|
(flag & RT_DEVICE_FLAG_INT_TX))
|
|
{
|
|
RT_ASSERT(0);
|
|
}
|
|
|
|
device->type = RT_Device_Class_Char;
|
|
device->rx_indicate = RT_NULL;
|
|
device->tx_complete = RT_NULL;
|
|
device->init = rt_usart_init;
|
|
device->open = rt_usart_open;
|
|
device->close = rt_usart_close;
|
|
device->read = rt_usart_read;
|
|
device->write = rt_usart_write;
|
|
device->control = rt_usart_control;
|
|
device->user_data = usart;
|
|
|
|
/* register a character device */
|
|
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
|
|
}
|
|
|
|
/******************************************************************//**
|
|
* @brief
|
|
* Initialize the specified USART unit
|
|
*
|
|
* @details
|
|
*
|
|
* @note
|
|
*
|
|
* @param[in] device
|
|
* Pointer to device descriptor
|
|
*
|
|
* @param[in] unitNumber
|
|
* Unit number
|
|
*
|
|
* @param[in] location
|
|
* Pin location number
|
|
*
|
|
* @param[in] flag
|
|
* Configuration flag
|
|
*
|
|
* @param[in] dmaChannel
|
|
* DMA channel number for TX
|
|
*
|
|
* @param[in] console
|
|
* Indicate if using as console
|
|
*
|
|
* @return
|
|
* Pointer to USART device
|
|
*********************************************************************/
|
|
static struct efm32_usart_device_t *rt_hw_usart_unit_init(
|
|
rt_device_t device,
|
|
rt_uint8_t unitNumber,
|
|
rt_uint8_t location,
|
|
rt_uint32_t flag,
|
|
rt_uint32_t dmaChannel,
|
|
rt_uint8_t config)
|
|
{
|
|
struct efm32_usart_device_t *usart;
|
|
struct efm32_usart_dma_mode_t *dma_mode;
|
|
CMU_Clock_TypeDef usartClock;
|
|
rt_uint32_t txDmaSelect;
|
|
union efm32_usart_init_t init;
|
|
efm32_irq_hook_init_t hook;
|
|
|
|
/* Allocate device */
|
|
usart = rt_malloc(sizeof(struct efm32_usart_device_t));
|
|
if (usart == RT_NULL)
|
|
{
|
|
usart_debug("USART: no memory for device\n");
|
|
return usart;
|
|
}
|
|
usart->unit = unitNumber;
|
|
usart->state = config;
|
|
usart->tx_mode = RT_NULL;
|
|
usart->rx_mode = RT_NULL;
|
|
|
|
/* Allocate TX */
|
|
dma_mode = RT_NULL;
|
|
if (flag & RT_DEVICE_FLAG_DMA_TX)
|
|
{
|
|
usart->tx_mode = dma_mode = rt_malloc(sizeof(struct efm32_usart_dma_mode_t));
|
|
if (dma_mode == RT_NULL)
|
|
{
|
|
usart_debug("USART: no memory for DMA TX\n");
|
|
rt_free(usart->rx_mode);
|
|
rt_free(usart);
|
|
usart = RT_NULL;
|
|
return usart;
|
|
}
|
|
dma_mode->dma_channel = dmaChannel;
|
|
}
|
|
|
|
/* Allocate RX */
|
|
if (flag & RT_DEVICE_FLAG_INT_RX)
|
|
{
|
|
usart->rx_mode = rt_malloc(sizeof(struct efm32_usart_int_mode_t));
|
|
if (usart->rx_mode == RT_NULL)
|
|
{
|
|
usart_debug("USART: no memory for interrupt RX\n");
|
|
rt_free(usart->tx_mode);
|
|
rt_free(usart);
|
|
usart = RT_NULL;
|
|
return usart;
|
|
}
|
|
}
|
|
|
|
/* Initialization */
|
|
switch (unitNumber)
|
|
{
|
|
case 0:
|
|
usart->usart_device = USART0;
|
|
usartClock = (CMU_Clock_TypeDef)cmuClock_USART0;
|
|
txDmaSelect = DMAREQ_USART0_TXBL;
|
|
break;
|
|
|
|
case 1:
|
|
usart->usart_device = USART1;
|
|
usartClock = (CMU_Clock_TypeDef)cmuClock_USART1;
|
|
txDmaSelect = DMAREQ_USART1_TXBL;
|
|
break;
|
|
|
|
case 2:
|
|
usart->usart_device = USART2;
|
|
usartClock = (CMU_Clock_TypeDef)cmuClock_USART2;
|
|
txDmaSelect = DMAREQ_USART2_TXBL;
|
|
break;
|
|
}
|
|
|
|
/* Enable USART clock */
|
|
CMU_ClockEnable(usartClock, true);
|
|
|
|
/* Reset */
|
|
USART_Reset(usart->usart_device);
|
|
|
|
/* Config GPIO */
|
|
GPIO_PinModeSet(
|
|
(GPIO_Port_TypeDef)AF_PORT(AF_USART_TX(unitNumber), location),
|
|
AF_PIN(AF_USART_TX(unitNumber), location),
|
|
gpioModePushPull,
|
|
0);
|
|
GPIO_PinModeSet(
|
|
(GPIO_Port_TypeDef)AF_PORT(AF_USART_RX(unitNumber), location),
|
|
AF_PIN(AF_USART_RX(unitNumber), location),
|
|
gpioModeInputPull,
|
|
1);
|
|
if (config & USART_STATE_SYNC)
|
|
{
|
|
GPIO_PinModeSet(
|
|
(GPIO_Port_TypeDef)AF_PORT(AF_USART_CLK(unitNumber), location),
|
|
AF_PIN(AF_USART_CLK(unitNumber), location),
|
|
gpioModePushPull,
|
|
0);
|
|
}
|
|
if (config & USART_STATE_AUTOCS)
|
|
{
|
|
GPIO_PinModeSet(
|
|
(GPIO_Port_TypeDef)AF_PORT(AF_USART_CS(unitNumber), location),
|
|
AF_PIN(AF_USART_CS(unitNumber), location),
|
|
gpioModePushPull,
|
|
1);
|
|
}
|
|
|
|
/* Config interrupt and NVIC */
|
|
if (flag & RT_DEVICE_FLAG_INT_RX)
|
|
{
|
|
hook.type = efm32_irq_type_usart;
|
|
hook.unit = unitNumber * 2 + 1;
|
|
hook.cbFunc = rt_hw_usart_rx_isr;
|
|
hook.userPtr = device;
|
|
efm32_irq_hook_register(&hook);
|
|
}
|
|
|
|
/* Config DMA */
|
|
if (flag & RT_DEVICE_FLAG_DMA_TX)
|
|
{
|
|
DMA_CB_TypeDef *callback;
|
|
DMA_CfgChannel_TypeDef chnlCfg;
|
|
DMA_CfgDescr_TypeDef descrCfg;
|
|
|
|
hook.type = efm32_irq_type_dma;
|
|
hook.unit = dmaChannel;
|
|
hook.cbFunc = rt_hw_usart_dma_tx_isr;
|
|
hook.userPtr = device;
|
|
efm32_irq_hook_register(&hook);
|
|
|
|
callback = (DMA_CB_TypeDef *)rt_malloc(sizeof(DMA_CB_TypeDef));
|
|
callback->cbFunc = DMA_IRQHandler_All;
|
|
callback->userPtr = RT_NULL;
|
|
callback->primary = 0;
|
|
|
|
/* Setting up DMA channel */
|
|
chnlCfg.highPri = false; /* Can't use with peripherals */
|
|
chnlCfg.enableInt = true; /* Interrupt for callback function */
|
|
chnlCfg.select = txDmaSelect;
|
|
chnlCfg.cb = callback;
|
|
DMA_CfgChannel(dmaChannel, &chnlCfg);
|
|
|
|
/* Setting up DMA channel descriptor */
|
|
descrCfg.dstInc = dmaDataIncNone;
|
|
descrCfg.srcInc = dmaDataInc1;
|
|
descrCfg.size = dmaDataSize1;
|
|
descrCfg.arbRate = dmaArbitrate1;
|
|
descrCfg.hprot = 0;
|
|
DMA_CfgDescr(dmaChannel, true, &descrCfg);
|
|
}
|
|
|
|
/* Enable RX and TX pins and set location */
|
|
usart->usart_device->ROUTE = USART_ROUTE_RXPEN | USART_ROUTE_TXPEN | \
|
|
(location << _USART_ROUTE_LOCATION_SHIFT);
|
|
if (config & USART_STATE_SYNC)
|
|
{
|
|
usart->usart_device->ROUTE |= USART_ROUTE_CLKPEN;
|
|
}
|
|
if (config & USART_STATE_AUTOCS)
|
|
{
|
|
usart->usart_device->ROUTE |= USART_ROUTE_CSPEN;
|
|
if (config & USART_STATE_MASTER)
|
|
{
|
|
usart->usart_device->CTRL |= USART_CTRL_AUTOCS;
|
|
}
|
|
}
|
|
|
|
/* Init specified USART unit */
|
|
if (config & USART_STATE_SYNC)
|
|
{
|
|
init.sync.enable = usartEnable;
|
|
init.sync.refFreq = 0;
|
|
init.sync.baudrate = SPI_BAUDRATE;
|
|
init.sync.databits = usartDatabits8;
|
|
if (config & USART_STATE_MASTER)
|
|
{
|
|
init.sync.master = true;
|
|
}
|
|
else
|
|
{
|
|
init.sync.master = false;
|
|
}
|
|
init.sync.msbf = true;
|
|
init.sync.clockMode = usartClockMode0; /* Clock idle low, sample on rising edge. */
|
|
USART_InitSync(usart->usart_device, &init.sync);
|
|
}
|
|
else
|
|
{
|
|
init.async.enable = usartEnable;
|
|
init.async.refFreq = 0;
|
|
init.async.baudrate = UART_BAUDRATE;
|
|
init.async.oversampling = USART_CTRL_OVS_X4;
|
|
init.async.databits = USART_FRAME_DATABITS_EIGHT;
|
|
init.async.parity = USART_FRAME_PARITY_NONE;
|
|
init.async.stopbits = USART_FRAME_STOPBITS_ONE;
|
|
USART_InitAsync(usart->usart_device, &init.async);
|
|
}
|
|
|
|
/* Clear RX/TX buffers */
|
|
usart->usart_device->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX;
|
|
|
|
return usart;
|
|
}
|
|
|
|
/******************************************************************//**
|
|
* @brief
|
|
* Initialize all USART module related hardware and register USART device to kernel
|
|
*
|
|
* @details
|
|
*
|
|
* @note
|
|
*********************************************************************/
|
|
void rt_hw_usart_init(void)
|
|
{
|
|
struct efm32_usart_device_t *usart;
|
|
rt_uint32_t flag;
|
|
rt_uint8_t config;
|
|
|
|
/* Register usart0 */
|
|
#ifdef RT_USING_USART0
|
|
config = 0x00;
|
|
flag = RT_DEVICE_FLAG_RDWR;
|
|
|
|
#ifdef RT_USART0_SYNC_MODE
|
|
config |= USART_STATE_SYNC;
|
|
#if (RT_USART0_SYNC_MODE != 0x0UL)
|
|
config |= USART_STATE_MASTER;
|
|
#else
|
|
flag |= RT_DEVICE_FLAG_INT_RX;
|
|
#endif
|
|
#else
|
|
flag |= RT_DEVICE_FLAG_INT_RX;
|
|
#endif
|
|
|
|
#if (SPI_AUTOCS_ENABLE & (1 << 0))
|
|
config |= USART_STATE_AUTOCS;
|
|
#endif
|
|
|
|
#if (RT_CONSOLE_DEVICE == 0x0UL)
|
|
config |= USART_STATE_CONSOLE;
|
|
flag |= RT_DEVICE_FLAG_STREAM;
|
|
#endif
|
|
|
|
#ifdef RT_USART0_USING_DMA
|
|
RT_ASSERT(RT_USART0_USING_DMA < DMA_CHAN_COUNT);
|
|
flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
#else
|
|
#define RT_USART0_USING_DMA EFM32_NO_DATA
|
|
#endif
|
|
|
|
usart = rt_hw_usart_unit_init(
|
|
&usart0_device,
|
|
0,
|
|
RT_USING_USART0,
|
|
flag,
|
|
RT_USART0_USING_DMA,
|
|
config);
|
|
|
|
rt_hw_usart_register(&usart0_device, RT_USART0_NAME, flag, usart);
|
|
#endif
|
|
|
|
/* Register usart1 */
|
|
#ifdef RT_USING_USART1
|
|
config = 0x00;
|
|
flag = RT_DEVICE_FLAG_RDWR;
|
|
|
|
#ifdef RT_USART1_SYNC_MODE
|
|
config |= USART_STATE_SYNC;
|
|
#if (RT_USART1_SYNC_MODE != 0x0UL)
|
|
config |= USART_STATE_MASTER;
|
|
#else
|
|
flag |= RT_DEVICE_FLAG_INT_RX;
|
|
#endif
|
|
#else
|
|
flag |= RT_DEVICE_FLAG_INT_RX;
|
|
#endif
|
|
|
|
#if (SPI_AUTOCS_ENABLE & (1 << 1))
|
|
config |= USART_STATE_AUTOCS;
|
|
#endif
|
|
|
|
#if (RT_CONSOLE_DEVICE == 0x1UL)
|
|
config |= USART_STATE_CONSOLE;
|
|
flag |= RT_DEVICE_FLAG_STREAM;
|
|
#endif
|
|
|
|
#ifdef RT_USART1_USING_DMA
|
|
RT_ASSERT(RT_USART1_USING_DMA < DMA_CHAN_COUNT);
|
|
flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
#else
|
|
|
|
#define RT_USART1_USING_DMA EFM32_NO_DATA
|
|
#endif
|
|
|
|
usart = rt_hw_usart_unit_init(
|
|
&usart1_device,
|
|
1,
|
|
RT_USING_USART1,
|
|
flag,
|
|
RT_USART1_USING_DMA,
|
|
config);
|
|
|
|
rt_hw_usart_register(&usart1_device, RT_USART1_NAME, flag, usart);
|
|
#endif
|
|
|
|
/* Register usart2 */
|
|
#ifdef RT_USING_USART2
|
|
config = 0x00;
|
|
flag = RT_DEVICE_FLAG_RDWR;
|
|
|
|
#ifdef RT_USART2_SYNC_MODE
|
|
config |= USART_STATE_SYNC;
|
|
#if (RT_USART2_SYNC_MODE != 0x0UL)
|
|
config |= USART_STATE_MASTER;
|
|
#else
|
|
flag |= RT_DEVICE_FLAG_INT_RX;
|
|
#endif
|
|
#else
|
|
flag |= RT_DEVICE_FLAG_INT_RX;
|
|
#endif
|
|
|
|
#if (SPI_AUTOCS_ENABLE & (1 << 2))
|
|
config |= USART_STATE_AUTOCS;
|
|
#endif
|
|
|
|
#if (RT_CONSOLE_DEVICE == 0x2UL)
|
|
config |= USART_STATE_CONSOLE;
|
|
flag |= RT_DEVICE_FLAG_STREAM;
|
|
#endif
|
|
|
|
#ifdef RT_USART2_USING_DMA
|
|
RT_ASSERT(RT_USART2_USING_DMA < DMA_CHAN_COUNT);
|
|
flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
|
#else
|
|
|
|
#define RT_USART2_USING_DMA EFM32_NO_DATA
|
|
#endif
|
|
|
|
usart = rt_hw_usart_unit_init(
|
|
&usart2_device,
|
|
2,
|
|
RT_USING_USART2,
|
|
flag,
|
|
RT_USART2_USING_DMA,
|
|
config);
|
|
|
|
rt_hw_usart_register(&usart2_device, RT_USART2_NAME, flag, usart);
|
|
#endif
|
|
}
|
|
|
|
/******************************************************************//**
|
|
* @}
|
|
*********************************************************************/
|