451 lines
17 KiB
C
451 lines
17 KiB
C
/**************************************************************************//**
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* @file system_LPC11xx.c
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
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* for the NXP LPC11xx Device Series
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* @version V1.00
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* @date 17. November 2009
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*
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* @note
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* Copyright (C) 2009 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#include <stdint.h>
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#include "LPC11xx.h"
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*--------------------- Clock Configuration ----------------------------------
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//
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// <e> Clock Configuration
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// <e1> System Clock Setup
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// <e2> System Oscillator Enable
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// <o3.1> Select System Oscillator Frequency Range
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// <0=> 1 - 20 MHz
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// <1=> 15 - 25 MHz
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// </e2>
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// <e4> Watchdog Oscillator Enable
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// <o5.0..4> Select Divider for Fclkana
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// <0=> 2 <1=> 4 <2=> 6 <3=> 8
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// <4=> 10 <5=> 12 <6=> 14 <7=> 16
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// <8=> 18 <9=> 20 <10=> 22 <11=> 24
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// <12=> 26 <13=> 28 <14=> 30 <15=> 32
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// <16=> 34 <17=> 36 <18=> 38 <19=> 40
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// <20=> 42 <21=> 44 <22=> 46 <23=> 48
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// <24=> 50 <25=> 52 <26=> 54 <27=> 56
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// <28=> 58 <29=> 60 <30=> 62 <31=> 64
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// <o5.5..8> Select Watchdog Oscillator Analog Frequency (Fclkana)
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// <0=> Disabled
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// <1=> 0.5 MHz
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// <2=> 0.8 MHz
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// <3=> 1.1 MHz
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// <4=> 1.4 MHz
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// <5=> 1.6 MHz
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// <6=> 1.8 MHz
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// <7=> 2.0 MHz
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// <8=> 2.2 MHz
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// <9=> 2.4 MHz
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// <10=> 2.6 MHz
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// <11=> 2.7 MHz
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// <12=> 2.9 MHz
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// <13=> 3.1 MHz
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// <14=> 3.2 MHz
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// <15=> 3.4 MHz
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// </e4>
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// <o6> Select Input Clock for sys_pllclkin (Register: SYSPLLCLKSEL)
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// <0=> IRC Oscillator
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// <1=> System Oscillator
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// <2=> WDT Oscillator
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// <3=> Invalid
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// <e7> Use System PLL
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// <i> F_pll = M * F_in
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// <i> F_in must be in the range of 10 MHz to 25 MHz
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// <o8.0..4> M: PLL Multiplier Selection
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// <1-32><#-1>
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// <o8.5..6> P: PLL Divider Selection
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// <0=> 2
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// <1=> 4
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// <2=> 8
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// <3=> 16
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// <o8.7> DIRECT: Direct CCO Clock Output Enable
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// <o8.8> BYPASS: PLL Bypass Enable
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// </e7>
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// <o9> Select Input Clock for Main clock (Register: MAINCLKSEL)
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// <0=> IRC Oscillator
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// <1=> Input Clock to System PLL
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// <2=> WDT Oscillator
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// <3=> System PLL Clock Out
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// </e1>
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// <o10.0..7> System AHB Divider <0-255>
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// <i> 0 = is disabled
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// <o11.0> SYS Clock Enable
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// <o11.1> ROM Clock Enable
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// <o11.2> RAM Clock Enable
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// <o11.3> FLASHREG Flash Register Interface Clock Enable
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// <o11.4> FLASHARRAY Flash Array Access Clock Enable
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// <o11.5> I2C Clock Enable
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// <o11.6> GPIO Clock Enable
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// <o11.7> CT16B0 Clock Enable
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// <o11.8> CT16B1 Clock Enable
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// <o11.9> CT32B0 Clock Enable
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// <o11.10> CT32B1 Clock Enable
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// <o11.11> SSP0 Clock Enable
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// <o11.12> UART Clock Enable
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// <o11.13> ADC Clock Enable
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// <o11.15> WDT Clock Enable
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// <o11.16> IOCON Clock Enable
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// <o11.18> SSP1 Clock Enable
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//
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// <o12.0..7> SSP0 Clock Divider <0-255>
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// <i> 0 = is disabled
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// <o13.0..7> UART Clock Divider <0-255>
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// <i> 0 = is disabled
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// <o14.0..7> SSP1 Clock Divider <0-255>
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// <i> 0 = is disabled
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// </e>
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*/
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#define CLOCK_SETUP 1
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#define SYSCLK_SETUP 1
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#define SYSOSC_SETUP 1
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#define SYSOSCCTRL_Val 0x00000000
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#define WDTOSC_SETUP 0
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#define WDTOSCCTRL_Val 0x000000A0
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#define SYSPLLCLKSEL_Val 0x00000001
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#define SYSPLL_SETUP 1
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#define SYSPLLCTRL_Val 0x00000023
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#define MAINCLKSEL_Val 0x00000003
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#define SYSAHBCLKDIV_Val 0x00000001
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#define AHBCLKCTRL_Val 0x0001005F
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#define SSP0CLKDIV_Val 0x00000001
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#define UARTCLKDIV_Val 0x00000001
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#define SSP1CLKDIV_Val 0x00000001
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/*--------------------- Memory Mapping Configuration -------------------------
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//
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// <e> Memory Mapping
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// <o1.0..1> System Memory Remap (Register: SYSMEMREMAP)
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// <0=> Bootloader mapped to address 0
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// <1=> RAM mapped to address 0
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// <2=> Flash mapped to address 0
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// <3=> Flash mapped to address 0
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// </e>
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*/
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#define MEMMAP_SETUP 0
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#define SYSMEMREMAP_Val 0x00000001
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/*
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//-------- <<< end of configuration section >>> ------------------------------
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*/
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/*----------------------------------------------------------------------------
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Check the register settings
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*----------------------------------------------------------------------------*/
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#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
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#define CHECK_RSVD(val, mask) (val & mask)
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/* Clock Configuration -------------------------------------------------------*/
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#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
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#error "SYSOSCCTRL: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
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#error "WDTOSCCTRL: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
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#error "SYSPLLCLKSEL: Value out of range!"
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#endif
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#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
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#error "SYSPLLCTRL: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
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#error "MAINCLKSEL: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
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#error "SYSAHBCLKDIV: Value out of range!"
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#endif
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#if (CHECK_RSVD((AHBCLKCTRL_Val), ~0x0001FFFF))
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#error "AHBCLKCTRL: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RANGE((SSP0CLKDIV_Val), 0, 255))
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#error "SSP0CLKDIV: Value out of range!"
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#endif
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#if (CHECK_RANGE((UARTCLKDIV_Val), 0, 255))
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#error "UARTCLKDIV: Value out of range!"
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#endif
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#if (CHECK_RANGE((SSP1CLKDIV_Val), 0, 255))
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#error "SSP1CLKDIV: Value out of range!"
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#endif
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#if (CHECK_RSVD((SYSMEMREMAP_Val), ~0x00000003))
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#error "SYSMEMREMAP: Invalid values of reserved bits!"
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#endif
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/*----------------------------------------------------------------------------
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DEFINES
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*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------
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Define clocks
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*----------------------------------------------------------------------------*/
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#define __XTAL (12000000UL) /* Oscillator frequency */
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#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
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#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
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#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
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#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
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#if (CLOCK_SETUP) /* Clock Setup */
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#if (SYSCLK_SETUP) /* System Clock Setup */
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#if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/
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#if (__FREQSEL == 0)
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#define __WDT_OSC_CLK ( 400000 / __DIVSEL)
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#elif (__FREQSEL == 1)
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#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
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#elif (__FREQSEL == 2)
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#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
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#elif (__FREQSEL == 3)
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#define __WDT_OSC_CLK (1100000 / __DIVSEL)
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#elif (__FREQSEL == 4)
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#define __WDT_OSC_CLK (1400000 / __DIVSEL)
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#elif (__FREQSEL == 5)
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#define __WDT_OSC_CLK (1600000 / __DIVSEL)
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#elif (__FREQSEL == 6)
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#define __WDT_OSC_CLK (1800000 / __DIVSEL)
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#elif (__FREQSEL == 7)
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#define __WDT_OSC_CLK (2000000 / __DIVSEL)
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#elif (__FREQSEL == 8)
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#define __WDT_OSC_CLK (2200000 / __DIVSEL)
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#elif (__FREQSEL == 9)
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#define __WDT_OSC_CLK (2400000 / __DIVSEL)
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#elif (__FREQSEL == 10)
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#define __WDT_OSC_CLK (2600000 / __DIVSEL)
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#elif (__FREQSEL == 11)
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#define __WDT_OSC_CLK (2700000 / __DIVSEL)
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#elif (__FREQSEL == 12)
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#define __WDT_OSC_CLK (2900000 / __DIVSEL)
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#elif (__FREQSEL == 13)
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#define __WDT_OSC_CLK (3100000 / __DIVSEL)
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#elif (__FREQSEL == 14)
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#define __WDT_OSC_CLK (3200000 / __DIVSEL)
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#else
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#define __WDT_OSC_CLK (3400000 / __DIVSEL)
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#endif
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#else
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#define __WDT_OSC_CLK (1600000 / 2)
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#endif // WDTOSC_SETUP
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/* sys_pllclkin calculation */
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#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
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#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
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#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
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#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
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#elif ((SYSPLLCLKSEL_Val & 0x03) == 2)
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#define __SYS_PLLCLKIN (__WDT_OSC_CLK)
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#else
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#define __SYS_PLLCLKIN (0)
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#endif
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#if (SYSPLL_SETUP) /* System PLL Setup */
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#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
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#else
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#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * (1))
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#endif // SYSPLL_SETUP
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/* main clock calculation */
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#if ((MAINCLKSEL_Val & 0x03) == 0)
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#define __MAIN_CLOCK (__IRC_OSC_CLK)
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#elif ((MAINCLKSEL_Val & 0x03) == 1)
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#define __MAIN_CLOCK (__SYS_PLLCLKIN)
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#elif ((MAINCLKSEL_Val & 0x03) == 2)
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#define __MAIN_CLOCK (__WDT_OSC_CLK)
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#elif ((MAINCLKSEL_Val & 0x03) == 3)
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#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
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#else
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#define __MAIN_CLOCK (0)
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#endif
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#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
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#else // SYSCLK_SETUP
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#if (SYSAHBCLKDIV_Val == 0)
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#define __SYSTEM_CLOCK (0)
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#else
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#define __SYSTEM_CLOCK (__XTAL / SYSAHBCLKDIV_Val)
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#endif
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#endif // SYSCLK_SETUP
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#else
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#define __SYSTEM_CLOCK (__XTAL)
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#endif // CLOCK_SETUP
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/*----------------------------------------------------------------------------
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Clock Variable definitions
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*----------------------------------------------------------------------------*/
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uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
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/*----------------------------------------------------------------------------
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Clock functions
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*----------------------------------------------------------------------------*/
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void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
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{
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uint32_t wdt_osc = 0;
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/* Determine clock frequency according to clock register values */
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switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
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case 0: wdt_osc = 400000; break;
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case 1: wdt_osc = 500000; break;
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case 2: wdt_osc = 800000; break;
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case 3: wdt_osc = 1100000; break;
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case 4: wdt_osc = 1400000; break;
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case 5: wdt_osc = 1600000; break;
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case 6: wdt_osc = 1800000; break;
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case 7: wdt_osc = 2000000; break;
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case 8: wdt_osc = 2200000; break;
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case 9: wdt_osc = 2400000; break;
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case 10: wdt_osc = 2600000; break;
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case 11: wdt_osc = 2700000; break;
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case 12: wdt_osc = 2900000; break;
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case 13: wdt_osc = 3100000; break;
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case 14: wdt_osc = 3200000; break;
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case 15: wdt_osc = 3400000; break;
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}
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wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
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switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
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case 0: /* Internal RC oscillator */
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SystemCoreClock = __IRC_OSC_CLK;
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break;
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case 1: /* Input Clock to System PLL */
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switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
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case 0: /* Internal RC oscillator */
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SystemCoreClock = __IRC_OSC_CLK;
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break;
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case 1: /* System oscillator */
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SystemCoreClock = __SYS_OSC_CLK;
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break;
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case 2: /* WDT Oscillator */
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SystemCoreClock = wdt_osc;
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break;
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case 3: /* Reserved */
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SystemCoreClock = 0;
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break;
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}
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break;
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case 2: /* WDT Oscillator */
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SystemCoreClock = wdt_osc;
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break;
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case 3: /* System PLL Clock Out */
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switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
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case 0: /* Internal RC oscillator */
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if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
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SystemCoreClock = __IRC_OSC_CLK;
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} else {
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SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
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}
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break;
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case 1: /* System oscillator */
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if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
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SystemCoreClock = __SYS_OSC_CLK;
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} else {
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SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
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}
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break;
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case 2: /* WDT Oscillator */
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if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
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SystemCoreClock = wdt_osc;
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} else {
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SystemCoreClock = wdt_osc * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
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}
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break;
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case 3: /* Reserved */
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SystemCoreClock = 0;
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break;
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}
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break;
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}
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SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
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}
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System.
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*/
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void SystemInit (void)
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{
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#if (CLOCK_SETUP) /* Clock Setup */
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#if (SYSCLK_SETUP) /* System Clock Setup */
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#if (SYSOSC_SETUP) /* System Oscillator Setup */
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uint32_t i;
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LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
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LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
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for (i = 0; i < 200; i++) __NOP();
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LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
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LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
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LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
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LPC_SYSCON->SYSPLLCLKUEN = 0x01;
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while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
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#if (SYSPLL_SETUP) /* System PLL Setup */
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LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
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LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
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while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
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#endif
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#endif
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#if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/
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LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
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LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
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#endif
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LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
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LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
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LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
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LPC_SYSCON->MAINCLKUEN = 0x01;
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while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
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#endif
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LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
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LPC_SYSCON->SYSAHBCLKCTRL = AHBCLKCTRL_Val;
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LPC_SYSCON->SSP0CLKDIV = SSP0CLKDIV_Val;
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LPC_SYSCON->UARTCLKDIV = UARTCLKDIV_Val;
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LPC_SYSCON->SSP1CLKDIV = SSP1CLKDIV_Val;
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#endif
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#if (MEMMAP_SETUP || MEMMAP_INIT) /* Memory Mapping Setup */
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LPC_SYSCON->SYSMEMREMAP = SYSMEMREMAP_Val;
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#endif
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}
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