412 lines
10 KiB
C
412 lines
10 KiB
C
/*
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* File : dev_gpio.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2015, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2017-10-20 ZYH the first version
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* 2017-11-35 ZYH update to 3.0.0
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*/
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#include <board.h>
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#include <drv_spi.h>
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#ifdef RT_USING_SPI
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#define SPIRXEVENT 0x01
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#define SPITXEVENT 0x02
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#define SPITIMEOUT 2
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#define SPICRCEN 0
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struct stm32_hw_spi_cs
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{
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rt_uint32_t pin;
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};
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struct stm32_spi
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{
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SPI_TypeDef *Instance;
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struct rt_spi_configuration *cfg;
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};
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static rt_err_t stm32_spi_init(SPI_TypeDef *spix, struct rt_spi_configuration *cfg)
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{
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SPI_HandleTypeDef hspi;
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hspi.Instance = spix;
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if (cfg->mode & RT_SPI_SLAVE)
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{
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hspi.Init.Mode = SPI_MODE_SLAVE;
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}
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else
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{
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hspi.Init.Mode = SPI_MODE_MASTER;
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}
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if (cfg->mode & RT_SPI_3WIRE)
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{
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hspi.Init.Direction = SPI_DIRECTION_1LINE;
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}
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else
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{
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hspi.Init.Direction = SPI_DIRECTION_2LINES;
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}
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if (cfg->data_width == 8)
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{
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hspi.Init.DataSize = SPI_DATASIZE_8BIT;
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}
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else if (cfg->data_width == 16)
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{
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hspi.Init.DataSize = SPI_DATASIZE_16BIT;
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}
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else
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{
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return RT_EIO;
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}
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if (cfg->mode & RT_SPI_CPHA)
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{
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hspi.Init.CLKPhase = SPI_PHASE_2EDGE;
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}
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else
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{
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hspi.Init.CLKPhase = SPI_PHASE_1EDGE;
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}
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if (cfg->mode & RT_SPI_CPOL)
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{
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hspi.Init.CLKPolarity = SPI_POLARITY_HIGH;
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}
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else
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{
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hspi.Init.CLKPolarity = SPI_POLARITY_LOW;
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}
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if (cfg->mode & RT_SPI_NO_CS)
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{
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hspi.Init.NSS = SPI_NSS_SOFT;
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}
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else
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{
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hspi.Init.NSS = SPI_NSS_SOFT;
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// hspi.Init.NSS = SPI_NSS_HARD_OUTPUT;
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}
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if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 2)
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{
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hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
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}
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else if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 4)
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{
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hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
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}
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else if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 8)
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{
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hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
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}
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else if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 16)
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{
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hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
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}
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else if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 32)
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{
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hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
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}
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else if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 64)
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{
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hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
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}
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else if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 128)
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{
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hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;
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}
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else
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{
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/* min prescaler 256 */
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hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
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}
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if (cfg->mode & RT_SPI_MSB)
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{
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hspi.Init.FirstBit = SPI_FIRSTBIT_MSB;
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}
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else
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{
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hspi.Init.FirstBit = SPI_FIRSTBIT_LSB;
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}
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hspi.Init.TIMode = SPI_TIMODE_DISABLE;
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hspi.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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hspi.Init.CRCPolynomial = 7;
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hspi.State = HAL_SPI_STATE_RESET;
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if (HAL_SPI_Init(&hspi) != HAL_OK)
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{
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return RT_EIO;
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}
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__HAL_SPI_ENABLE(&hspi);
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return RT_EOK;
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}
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#define SPISTEP(datalen) (((datalen) == 8) ? 1 : 2)
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#define SPISEND_1(reg, ptr, datalen) \
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do \
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{ \
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if (datalen == 8) \
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{ \
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(reg) = *(rt_uint8_t *)(ptr); \
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} \
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else \
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{ \
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(reg) = *(rt_uint16_t *)(ptr); \
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} \
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} while (0)
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#define SPIRECV_1(reg, ptr, datalen) \
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do \
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{ \
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if (datalen == 8) \
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{ \
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*(rt_uint8_t *)(ptr) = (reg); \
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} \
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else \
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{ \
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*(rt_uint16_t *)(ptr) = reg; \
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} \
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} while (0)
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static rt_err_t spitxrx1b(struct stm32_spi *hspi, void *rcvb, const void *sndb)
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{
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rt_uint32_t padrcv = 0;
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rt_uint32_t padsnd = 0xFF;
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if (!rcvb && !sndb)
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{
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return RT_ERROR;
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}
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if (!rcvb)
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{
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rcvb = &padrcv;
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}
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if (!sndb)
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{
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sndb = &padsnd;
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}
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while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) == RESET)
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;
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SPISEND_1(hspi->Instance->DR, sndb, hspi->cfg->data_width);
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while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) == RESET)
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;
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SPIRECV_1(hspi->Instance->DR, rcvb, hspi->cfg->data_width);
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return RT_EOK;
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}
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static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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rt_err_t res;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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RT_ASSERT(device->bus->parent.user_data != RT_NULL);
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struct stm32_spi *hspi = (struct stm32_spi *)device->bus->parent.user_data;
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struct stm32_hw_spi_cs *cs = device->parent.user_data;
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if (message->cs_take)
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{
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rt_pin_write(cs->pin, 0);
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}
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const rt_uint8_t *sndb = message->send_buf;
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rt_uint8_t *rcvb = message->recv_buf;
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rt_int32_t length = message->length;
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while (length)
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{
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res = spitxrx1b(hspi, rcvb, sndb);
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if (rcvb)
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{
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rcvb += SPISTEP(hspi->cfg->data_width);
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}
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if (sndb)
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{
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sndb += SPISTEP(hspi->cfg->data_width);
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}
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if (res != RT_EOK)
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{
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break;
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}
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length--;
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}
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/* Wait until Busy flag is reset before disabling SPI */
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while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) == SET)
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;
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if (message->cs_release)
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{
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rt_pin_write(cs->pin, 1);
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}
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return message->length - length;
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}
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rt_err_t spi_configure(struct rt_spi_device *device,
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struct rt_spi_configuration *configuration)
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{
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struct stm32_spi *hspi = (struct stm32_spi *)device->bus->parent.user_data;
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hspi->cfg = configuration;
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return stm32_spi_init(hspi->Instance, configuration);
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}
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const struct rt_spi_ops stm_spi_ops =
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{
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.configure = spi_configure,
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.xfer = spixfer,
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};
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struct rt_spi_bus _spi_bus1, _spi_bus2;
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struct stm32_spi _spi1, _spi2;
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int stm32_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
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{
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struct rt_spi_bus *spi_bus;
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struct stm32_spi *spi;
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if (SPIx == SPI1)
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{
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spi_bus = &_spi_bus1;
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spi = &_spi1;
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}
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else if (SPIx == SPI2)
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{
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spi_bus = &_spi_bus2;
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spi = &_spi2;
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}
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else
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{
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return -1;
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}
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spi->Instance = SPIx;
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spi_bus->parent.user_data = spi;
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return rt_spi_bus_register(spi_bus, name, &stm_spi_ops);
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}
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rt_err_t stm32_spi_bus_attach_device(rt_uint32_t pin, const char *bus_name, const char *device_name)
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{
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struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
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RT_ASSERT(spi_device != RT_NULL);
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struct stm32_hw_spi_cs *cs_pin = (struct stm32_hw_spi_cs *)rt_malloc(sizeof(struct stm32_hw_spi_cs));
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RT_ASSERT(cs_pin != RT_NULL);
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cs_pin->pin = pin;
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rt_pin_mode(pin, PIN_MODE_OUTPUT);
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rt_pin_write(pin, 1);
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return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
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}
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int stm32_hw_spi_init(void)
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{
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int result = 0;
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#ifdef RT_USING_SPI1
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result = stm32_spi_register_bus(SPI1, "spi1");
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#endif
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#ifdef RT_USING_SPI2
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result = stm32_spi_register_bus(SPI2, "spi2");
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#endif
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return result;
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}
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INIT_BOARD_EXPORT(stm32_hw_spi_init);
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void HAL_SPI_MspInit(SPI_HandleTypeDef *spiHandle)
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{
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GPIO_InitTypeDef GPIO_InitStruct;
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if (spiHandle->Instance == SPI1)
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{
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/* SPI1 clock enable */
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__HAL_RCC_SPI1_CLK_ENABLE();
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__HAL_RCC_GPIOA_CLK_ENABLE();
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/**SPI1 GPIO Configuration
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PA5 ------> SPI1_SCK
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PA6 ------> SPI1_MISO
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PA7 ------> SPI1_MOSI
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*/
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GPIO_InitStruct.Pin = GPIO_PIN_5 | GPIO_PIN_7;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = GPIO_PIN_6;
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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}
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else if (spiHandle->Instance == SPI2)
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{
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/* SPI2 clock enable */
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__HAL_RCC_SPI2_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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/**SPI2 GPIO Configuration
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PB13 ------> SPI2_SCK
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PB14 ------> SPI2_MISO
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PB15 ------> SPI2_MOSI
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*/
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GPIO_InitStruct.Pin = GPIO_PIN_13 | GPIO_PIN_15;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = GPIO_PIN_14;
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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}
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}
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void HAL_SPI_MspDeInit(SPI_HandleTypeDef *spiHandle)
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{
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if (spiHandle->Instance == SPI1)
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{
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/* Peripheral clock disable */
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__HAL_RCC_SPI1_CLK_DISABLE();
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/**SPI1 GPIO Configuration
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PA5 ------> SPI1_SCK
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PA6 ------> SPI1_MISO
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PA7 ------> SPI1_MOSI
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*/
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HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7);
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}
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else if (spiHandle->Instance == SPI2)
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{
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/* Peripheral clock disable */
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__HAL_RCC_SPI2_CLK_DISABLE();
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/**SPI2 GPIO Configuration
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PB13 ------> SPI2_SCK
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PB14 ------> SPI2_MISO
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PB15 ------> SPI2_MOSI
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*/
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HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
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}
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}
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#endif /*RT_USING_SPI*/
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