306 lines
8.6 KiB
C
306 lines
8.6 KiB
C
/*
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* File : edma.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2010-11-13 weety first version
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*/
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/*
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* This EDMA3 programming framework exposes two basic kinds of resource:
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*
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* Channel Triggers transfers, usually from a hardware event but
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* also manually or by "chaining" from DMA completions.
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* Each channel is coupled to a Parameter RAM (PaRAM) slot.
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*
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* Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
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* "set"), source and destination addresses, a link to a
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* next PaRAM slot (if any), options for the transfer, and
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* instructions for updating those addresses. There are
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* more than twice as many slots as event channels.
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*
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* Each PaRAM set describes a sequence of transfers, either for one large
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* buffer or for several discontiguous smaller buffers. An EDMA transfer
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* is driven only from a channel, which performs the transfers specified
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* in its PaRAM slot until there are no more transfers. When that last
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* transfer completes, the "link" field may be used to reload the channel's
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* PaRAM slot with a new transfer descriptor.
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*
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* The EDMA Channel Controller (CC) maps requests from channels into physical
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* Transfer Controller (TC) requests when the channel triggers (by hardware
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* or software events, or by chaining). The two physical DMA channels provided
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* by the TCs are thus shared by many logical channels.
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*
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* DaVinci hardware also has a "QDMA" mechanism which is not currently
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* supported through this interface. (DSP firmware uses it though.)
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*/
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#ifndef EDMA_H_
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#define EDMA_H_
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#include <rtthread.h>
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#include <dm36x.h>
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#ifdef RT_EDMA_DEBUG
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#define edma_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__)
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#else
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#define edma_dbg(fmt, ...)
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#endif
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/* PaRAM slots are laid out like this */
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struct edmacc_param {
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unsigned int opt;
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unsigned int src;
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unsigned int a_b_cnt;
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unsigned int dst;
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unsigned int src_dst_bidx;
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unsigned int link_bcntrld;
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unsigned int src_dst_cidx;
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unsigned int ccnt;
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};
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#define CCINT0_INTERRUPT 16
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#define CCERRINT_INTERRUPT 17
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#define TCERRINT0_INTERRUPT 18
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#define TCERRINT1_INTERRUPT 19
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/* fields in edmacc_param.opt */
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#define SAM BIT(0)
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#define DAM BIT(1)
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#define SYNCDIM BIT(2)
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#define STATIC BIT(3)
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#define EDMA_FWID (0x07 << 8)
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#define TCCMODE BIT(11)
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#define EDMA_TCC(t) ((t) << 12)
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#define TCINTEN BIT(20)
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#define ITCINTEN BIT(21)
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#define TCCHEN BIT(22)
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#define ITCCHEN BIT(23)
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#define TRWORD (0x7<<2)
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#define PAENTRY (0x1ff<<5)
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/* DM365 specific EDMA3 Events Information */
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enum dm365_edma_ch {
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DM365_DMA_TIMER3_TINT6,
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DM365_DMA_TIMER3_TINT7,
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DM365_DMA_MCBSP_TX = 2,
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DM365_DMA_VCIF_TX = 2,
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DM365_DMA_MCBSP_RX = 3,
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DM365_DMA_VCIF_RX = 3,
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DM365_DMA_VPSS_EVT1,
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DM365_DMA_VPSS_EVT2,
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DM365_DMA_VPSS_EVT3,
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DM365_DMA_VPSS_EVT4,
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DM365_DMA_TIMER2_TINT4,
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DM365_DMA_TIMER2_TINT5,
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DM365_DMA_SPI2XEVT,
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DM365_DMA_SPI2REVT,
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DM365_DMA_IMCOP_IMX0INT = 12,
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DM365_DMA_KALEIDO_ARMINT = 12,
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DM365_DMA_IMCOP_SEQINT,
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DM365_DMA_SPI1XEVT,
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DM365_DMA_SPI1REVT,
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DM365_DMA_SPI0XEVT,
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DM365_DMA_SPI0REVT,
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DM365_DMA_URXEVT0 = 18,
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DM365_DMA_SPI3XEVT = 18,
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DM365_DMA_UTXEVT0 = 19,
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DM365_DMA_SPI3REVT = 19,
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DM365_DMA_URXEVT1,
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DM365_DMA_UTXEVT1,
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DM365_DMA_TIMER4_TINT8,
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DM365_DMA_TIMER4_TINT9,
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DM365_DMA_RTOINT,
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DM365_DMA_GPIONT9,
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DM365_DMA_MMC0RXEVT = 26,
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DM365_DMA_MEMSTK_MSEVT = 26,
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DM365_DMA_MMC0TXEVT,
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DM365_DMA_I2C_ICREVT,
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DM365_DMA_I2C_ICXEVT,
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DM365_DMA_MMC1RXEVT,
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DM365_DMA_MMC1TXEVT,
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DM365_DMA_GPIOINT0,
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DM365_DMA_GPIOINT1,
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DM365_DMA_GPIOINT2,
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DM365_DMA_GPIOINT3,
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DM365_DMA_GPIOINT4,
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DM365_DMA_GPIOINT5,
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DM365_DMA_GPIOINT6,
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DM365_DMA_GPIOINT7,
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DM365_DMA_GPIOINT10 = 40,
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DM365_DMA_EMAC_RXTHREESH = 40,
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DM365_DMA_GPIOINT11 = 41,
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DM365_DMA_EMAC_RXPULSE = 41,
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DM365_DMA_GPIOINT12 = 42,
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DM365_DMA_EMAC_TXPULSE = 42,
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DM365_DMA_GPIOINT13 = 43,
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DM365_DMA_EMAC_MISCPULSE = 43,
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DM365_DMA_GPIOINT14 = 44,
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DM365_DMA_SPI4XEVT = 44,
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DM365_DMA_GPIOINT15 = 45,
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DM365_DMA_SPI4REVT = 45,
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DM365_DMA_ADC_ADINT,
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DM365_DMA_GPIOINT8,
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DM365_DMA_TIMER0_TINT0,
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DM365_DMA_TIMER0_TINT1,
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DM365_DMA_TIMER1_TINT2,
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DM365_DMA_TIMER1_TINT3,
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DM365_DMA_PWM0,
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DM365_DMA_PWM1 = 53,
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DM365_DMA_IMCOP_IMX1INT = 53,
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DM365_DMA_PWM2 = 54,
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DM365_DMA_IMCOP_NSFINT = 54,
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DM365_DMA_PWM3 = 55,
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DM365_DMA_KALEIDO6_CP_UNDEF = 55,
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DM365_DMA_IMCOP_VLCDINT = 56,
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DM365_DMA_KALEIDO5_CP_ECDCMP = 56,
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DM365_DMA_IMCOP_BIMINT = 57,
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DM365_DMA_KALEIDO8_CP_ME = 57,
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DM365_DMA_IMCOP_DCTINT = 58,
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DM365_DMA_KALEIDO1_CP_CALC = 58,
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DM365_DMA_IMCOP_QIQINT = 59,
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DM365_DMA_KALEIDO7_CP_IPE = 59,
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DM365_DMA_IMCOP_BPSINT = 60,
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DM365_DMA_KALEIDO2_CP_BS = 60,
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DM365_DMA_IMCOP_VLCDERRINT = 61,
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DM365_DMA_KALEIDO0_CP_LPF = 61,
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DM365_DMA_IMCOP_RCNTINT = 62,
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DM365_DMA_KALEIDO3_CP_MC = 62,
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DM365_DMA_IMCOP_COPCINT = 63,
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DM365_DMA_KALEIDO4_CP_ECDEND = 63,
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};
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/* end DM365 specific info */
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/*ch_status paramater of callback function possible values*/
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#define DMA_COMPLETE 1
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#define DMA_CC_ERROR 2
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#define DMA_TC1_ERROR 3
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#define DMA_TC2_ERROR 4
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enum address_mode {
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INCR = 0,
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FIFO = 1
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};
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enum fifo_width {
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W8BIT = 0,
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W16BIT = 1,
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W32BIT = 2,
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W64BIT = 3,
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W128BIT = 4,
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W256BIT = 5
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};
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enum dma_event_q {
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EVENTQ_0 = 0,
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EVENTQ_1 = 1,
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EVENTQ_2 = 2,
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EVENTQ_3 = 3,
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EVENTQ_DEFAULT = -1
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};
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enum sync_dimension {
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ASYNC = 0,
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ABSYNC = 1
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};
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#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
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#define EDMA_CTLR(i) ((i) >> 16)
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#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
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#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
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#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
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#define EDMA_CONT_PARAMS_ANY 1001
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#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
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#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
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#define EDMA_MAX_CC 2
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/* alloc/free DMA channels and their dedicated parameter RAM slots */
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int edma_alloc_channel(int channel,
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void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data),
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void *data, enum dma_event_q);
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void edma_free_channel(unsigned channel);
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/* alloc/free parameter RAM slots */
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int edma_alloc_slot(unsigned ctlr, int slot);
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void edma_free_slot(unsigned slot);
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/* alloc/free a set of contiguous parameter RAM slots */
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int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
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int edma_free_cont_slots(unsigned slot, int count);
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/* calls that operate on part of a parameter RAM slot */
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void edma_set_src(unsigned slot, rt_uint32_t src_port,
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enum address_mode mode, enum fifo_width);
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void edma_set_dest(unsigned slot, rt_uint32_t dest_port,
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enum address_mode mode, enum fifo_width);
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void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst);
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void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx);
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void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_cidx);
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void edma_set_transfer_params(unsigned slot, rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt,
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rt_uint16_t bcnt_rld, enum sync_dimension sync_mode);
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void edma_link(unsigned from, unsigned to);
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void edma_unlink(unsigned from);
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/* calls that operate on an entire parameter RAM slot */
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void edma_write_slot(unsigned slot, const struct edmacc_param *params);
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void edma_read_slot(unsigned slot, struct edmacc_param *params);
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/* channel control operations */
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int edma_start(unsigned channel);
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void edma_stop(unsigned channel);
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void edma_clean_channel(unsigned channel);
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void edma_clear_event(unsigned channel);
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void edma_pause(unsigned channel);
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void edma_resume(unsigned channel);
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struct edma_rsv_info {
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const rt_int16_t (*rsv_chans)[2];
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const rt_int16_t (*rsv_slots)[2];
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};
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/* platform_data for EDMA driver */
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struct edma_soc_info {
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/* how many dma resources of each type */
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unsigned n_channel;
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unsigned n_region;
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unsigned n_slot;
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unsigned n_tc;
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unsigned n_cc;
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enum dma_event_q default_queue;
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/* Resource reservation for other cores */
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struct edma_rsv_info *rsv;
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const rt_int8_t (*queue_tc_mapping)[2];
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const rt_int8_t (*queue_priority_mapping)[2];
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};
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int edma_init(struct edma_soc_info **info);
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#endif
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