680 lines
25 KiB
C
680 lines
25 KiB
C
/************************************************************************/
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/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
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/* */
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/* The following software deliverable is intended for and must only be */
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/* used for reference and in an evaluation laboratory environment. */
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/* It is provided on an as-is basis without charge and is subject to */
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/* alterations. */
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/* It is the user's obligation to fully test the software in its */
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/* environment and to ensure proper functionality, qualification and */
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/* compliance with component specifications. */
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/* */
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/* In the event the software deliverable includes the use of open */
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/* source components, the provisions of the governing open source */
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/* license agreement shall apply with respect to such software */
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/* deliverable. */
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/* FSEU does not warrant that the deliverables do not infringe any */
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/* third party intellectual property right (IPR). In the event that */
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/* the deliverables infringe a third party IPR it is the sole */
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/* responsibility of the customer to obtain necessary licenses to */
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/* continue the usage of the deliverable. */
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/* */
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/* To the maximum extent permitted by applicable law FSEU disclaims all */
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/* warranties, whether express or implied, in particular, but not */
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/* limited to, warranties of merchantability and fitness for a */
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/* particular purpose for which the deliverable is not designated. */
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/* */
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/* To the maximum extent permitted by applicable law, FSEU's liability */
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/* is restricted to intentional misconduct and gross negligence. */
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/* FSEU is not liable for consequential damages. */
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/* */
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/* (V1.5) */
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/************************************************************************/
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/** \file system_mb9bf50x.h
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**
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** Headerfile for FM3 system parameters
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**
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** User clock definitions can be done for the following clock settings:
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** - CLOCK_SETUP : Execute the clock settings form the settings below in
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** SystemInit()
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** - __CLKMO : External clock frequency for main oscillion
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** - __CLKSO : External clock frequency for sub oscillion
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** - SCM_CTL : System Clock Mode Control Register
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** - BSC_PSR : Base Clock Prescaler Register
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** - APBC0_PSR : APB0 Prescaler Register
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** - APBC1_PSR : APB1 Prescaler Register
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** - APBC2_PSR : APB2 Prescaler Register
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** - SWC_PSR : Software Watchdog Clock Prescaler Register
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** - TTC_PSR : Trace Clock Prescaler Register
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** - CSW_TMR : Clock Stabilization Wait Time Register
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** - PSW_TMR : PLL Clock Stabilization Wait Time Setup Register
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** - PLL_CTL1 : PLL Control Register 1
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** - PLL_CTL2 : PLL Control Register 2
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**
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** The register settings are check for correct values of reserved bits.
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** Otherwise a preprocessor error is output and stops the build process.
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** Furthermore the 'master clock' is retrieved from the register settings
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** and the system clock (HCLK) is calculated from the Base Clock Prescaler
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** Register (BSC_PSR). This value is used for the global CMSIS variable
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** #SystemCoreClock. Also the absolute external, PLL and HCL freqeuncy is
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** is checked. Note that not all possible wrong setting are checked! The
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** user has to take care to fulfill the settings stated in the according
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** device's data sheet!
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**
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** User definition for Hardware Watchdog:
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** - HWWD_DISABLE : Disables Hardware Watchdog in SystemInit()
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**
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** User definition for CR Trimming:
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** - CR_TRIM_SETUP : Enables CR trimming in SystemInit()
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**
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** History:
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** 2011-05-16 V1.0 MWi original version
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** 2011-12-20 V1.1 EH corresponded to C++
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*****************************************************************************/
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#ifndef _SYSTEM_MB9BF50X_H_
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#define _SYSTEM_MB9BF50X_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/******************************************************************************/
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/* Include files */
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/******************************************************************************/
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#include <stdint.h>
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/******************************************************************************/
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/* Global pre-processor symbols/macros ('define') */
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/******************************************************************************/
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/******************************************************************************/
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/* */
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/* START OF USER SETTINGS HERE */
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/* =========================== */
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/* */
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/* All lines with '<<<' can be set by user. */
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/* */
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/******************************************************************************/
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/**
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******************************************************************************
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** \brief Clock Setup Enable
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** <i>(USER SETTING)</i>
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**
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** - 0 = No clock setup done by system_mb9xfxxx.c
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** - 1 = Clock setup done by system_mb9xfxxx.c
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******************************************************************************/
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#define CLOCK_SETUP 1 // <<< Define clock setup here
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/**
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******************************************************************************
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** \brief External Main Clock Frequency (in Hz, [value]UL)
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** <i>(USER SETTING)</i>
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******************************************************************************/
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#define __CLKMO ( 4000000UL) // <<< External 4MHz Crystal
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/**
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******************************************************************************
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** \brief External Sub Clock Frequency (in Hz, [value]UL)
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** <i>(USER SETTING)</i>
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******************************************************************************/
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#define __CLKSO ( 32768UL) // <<< External 32KHz Crystal
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/**
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******************************************************************************
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** \brief System Clock Mode Control Register value definition
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** <i>(USER SETTING)</i>
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**
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** SCM_CTL
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**
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** Bit#7-5 : RCS[2:0]
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** - 0 = Internal high-speed CR oscillation (default)
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** - 1 = Main oscillation clock
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** - 2 = PLL oscillation clock
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** - 3 = (not allowed)
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** - 4 = Internal low-speed CR oscillation
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** - 5 = Sub clock oscillation
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** - 6 = (not allowed)
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** - 7 = (not allowed)
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**
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** Bit#4 : PLLE
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** - 0 = Disable PLL (default)
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** - 1 = Enable PLL
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**
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** Bit#3 : SOSCE
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** - 0 = Disable sub oscillation (default)
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** - 1 = Enable sub oscillation
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**
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** Bit#2 : (reserved)
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**
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** Bit#1 : MOSCE
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** - 0 = Disable main oscillation (default)
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** - 1 = Enable main oscillation
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**
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** Bit#0 : (reserved)
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******************************************************************************/
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#define SCM_CTL_Val 0x00000052 // <<< Define SCM_CTL here
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/**
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******************************************************************************
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** \brief Base Clock Prescaler Register value definition
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** <i>(USER SETTING)</i>
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**
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** BSC_PSR
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**
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** Bit#7-3 : (reserved)
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**
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** Bit#2-0 : BSR[2:0]
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** - 0 = HCLK = Master Clock
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** - 1 = HCLK = Master Clock / 2
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** - 2 = HCLK = Master Clock / 3
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** - 3 = HCLK = Master Clock / 4
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** - 4 = HCLK = Master Clock / 6
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** - 5 = HCLK = Master Clock / 8
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** - 6 = HCLK = Master Clock / 16
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** - 7 = (reserved)
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******************************************************************************/
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#define BSC_PSR_Val 0x00000000 // <<< Define BSC_PSR here
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/**
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******************************************************************************
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** \brief APB0 Prescaler Register value definition
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** <i>(USER SETTING)</i>
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**
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** APBC0_PSR
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**
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** Bit#7-2 : (reserved)
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**
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** Bit#1-0 : BSR[2:0]
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** - 0 = PCLK0 = HCLK
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** - 1 = PCLK0 = HCLK / 2
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** - 2 = PCLK0 = HCLK / 4
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** - 3 = PCLK0 = HCLK / 8
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******************************************************************************/
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#define APBC0_PSR_Val 0x00000001 // <<< Define APBC0_PSR here
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/**
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******************************************************************************
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** \brief APB1 Prescaler Register value definition
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** <i>(USER SETTING)</i>
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**
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** APBC1_PSR
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**
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** Bit#7 : APBC1EN
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** - 0 = Disable PCLK1 output
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** - 1 = Enables PCLK1 (default)
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**
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** Bit#6-5 : (reserved)
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**
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** Bit#4 : APBC1RST
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** - 0 = APB1 bus reset, inactive (default)
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** - 1 = APB1 bus reset, active
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**
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** Bit#3-2 : (reserved)
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**
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** Bit#1-0 : APBC1[2:0]
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** - 0 = PCLK1 = HCLK
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** - 1 = PCLK1 = HCLK / 2
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** - 2 = PCLK1 = HCLK / 4
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** - 3 = PCLK1 = HCLK / 8
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******************************************************************************/
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#define APBC1_PSR_Val 0x00000081 // <<< Define APBC1_PSR here
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/**
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******************************************************************************
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** \brief APB2 Prescaler Register value definition
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** <i>(USER SETTING)</i>
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**
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** APBC2_PSR
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**
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** Bit#7 : APBC2EN
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** - 0 = Disable PCLK2 output
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** - 1 = Enables PCLK2 (default)
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**
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** Bit#6-5 : (reserved)
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**
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** Bit#4 : APBC2RST
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** - 0 = APB2 bus reset, inactive (default)
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** - 1 = APB2 bus reset, active
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**
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** Bit#3-2 : (reserved)
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**
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** Bit#1-0 : APBC2[1:0]
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** - 0 = PCLK2 = HCLK
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** - 1 = PCLK2 = HCLK / 2
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** - 2 = PCLK2 = HCLK / 4
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** - 3 = PCLK2 = HCLK / 8
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******************************************************************************/
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#define APBC2_PSR_Val 0x00000081 // <<< Define APBC2_PSR here
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/**
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******************************************************************************
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** \brief Software Watchdog Clock Prescaler Register value definition
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** <i>(USER SETTING)</i>
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**
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** SWC_PSR
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**
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** Bit#7 : TESTB
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** - 0 = (not allowed)
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** - 1 = (always write "1" to this bit)
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**
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** Bit#6-2 : (reserved)
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**
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** Bit#1-0 : SWDS[2:0]
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** - 0 = SWDGOGCLK = PCLK0
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** - 1 = SWDGOGCLK = PCLK0 / 2
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** - 2 = SWDGOGCLK = PCLK0 / 4
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** - 3 = SWDGOGCLK = PCLK0 / 8
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******************************************************************************/
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#define SWC_PSR_Val 0x00000003 // <<< Define SWC_PSR here
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/**
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******************************************************************************
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** \brief Trace Clock Prescaler Register value definition
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** <i>(USER SETTING)</i>
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**
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** TTC_PSR
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**
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** Bit#7-1 : (reserved)
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**
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** Bit#0 : TTC
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** - 0 = TPIUCLK = HCLK
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** - 1 = TPIUCLK = HCLK / 2
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******************************************************************************/
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#define TTC_PSR_Val 0x00000000 // <<< Define TTC_PSR here
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/**
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******************************************************************************
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** \brief Clock Stabilization Wait Time Register value definition
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** <i>(USER SETTING)</i>
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**
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** CSW_TMR
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**
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** Bit#7 : (reserved)
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**
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** Bit#6-4 : SOWT[2:0]
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** - 0 = ~10.3 ms (default)
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** - 1 = ~20.5 ms
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** - 2 = ~41 ms
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** - 3 = ~82 ms
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** - 4 = ~164 ms
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** - 5 = ~327 ms
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** - 6 = ~655 ms
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** - 7 = ~1.31 s
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**
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** Bit#3-0 : MOWT[3:0]
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** - 0 = ~500 ns (default)
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** - 1 = ~8 us
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** - 2 = ~16 us
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** - 3 = ~32 us
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** - 4 = ~64 us
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** - 5 = ~128 us
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** - 6 = ~256 us
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** - 7 = ~512 us
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** - 8 = ~1.0 ms
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** - 9 = ~2.0 ms
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** - 10 = ~4.0 ms
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** - 11 = ~8.0 ms
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** - 12 = ~33.0 ms
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** - 13 = ~131 ms
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** - 14 = ~524 ms
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** - 15 = ~2.0 s
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******************************************************************************/
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#define CSW_TMR_Val 0x0000005C // <<< Define CSW_TMR here
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/**
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******************************************************************************
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** \brief PLL Clock Stabilization Wait Time Setup Register value definition
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** <i>(USER SETTING)</i>
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**
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** PSW_TMR
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**
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** Bit#7-5 : (reserved)
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**
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** Bit#4 : PINC
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** - 0 = Selects CLKMO (main oscillation) (default)
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** - 1 = (setting diabled)
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**
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** Bit#3 : (reserved)
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**
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** Bit#2-0 : POWT[2:0]
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** - 0 = ~128 us (default)
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** - 1 = ~256 us
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** - 2 = ~512 us
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** - 3 = ~1.02 ms
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** - 4 = ~2.05 ms
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** - 5 = ~4.10 ms
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** - 6 = ~8.20 ms
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** - 7 = ~16.40 ms
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******************************************************************************/
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#define PSW_TMR_Val 0x00000000 // <<< Define PSW_TMR here
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/**
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******************************************************************************
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** \brief PLL Control Register 1 value definition
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** <i>(USER SETTING)</i>
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**
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** PLL_CTL1
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**
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** Bit#7-4 : PLLK[3:0]
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** - 0 = Division(PLLK) = 1/1 (default)
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** - 1 = Division(PLLK) = 1/2
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** - 2 = Division(PLLK) = 1/3
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** - . . .
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** - 15 = Division(PLLK) = 1/16
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**
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** Bit#3-0 : PLLM[3:0]
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** - 0 = Division(PLLM) = 1/1 (default)
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** - 1 = Division(PLLM) = 1/2
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** - 2 = Division(PLLM) = 1/3
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** - . . .
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** - 15 = Division(PLLM) = 1/16
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******************************************************************************/
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#define PLL_CTL1_Val 0x00000000 // <<< Define PLL_CTL1 here
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/**
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******************************************************************************
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** \brief PLL Control Register 2 value definition
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** <i>(USER SETTING)</i>
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**
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** PLL_CTL2
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**
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** Bit#7-6 : (reserved)
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**
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** Bit#5-0 : PLLN[5:0]
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** - 0 = Division(PLLN) = 1/1 (default)
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** - 1 = Division(PLLN) = 1/2
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** - 2 = Division(PLLN) = 1/3
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** - . . .
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** - 63 = Division(PLLN) = 1/64
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******************************************************************************/
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#define PLL_CTL2_Val 0x00000013 // <<< Define PLL_CTL2 here
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/**
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******************************************************************************
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** \brief Hardware Watchdog disable definition
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** <i>(USER SETTING)</i>
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**
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** - 0 = Hardware Watchdog enable
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** - 1 = Hardware Watchdog disable
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******************************************************************************/
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#define HWWD_DISABLE 1 // <<< Define HW Watach dog enable here
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/**
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******************************************************************************
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** \brief Trimming CR
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** <i>(USER SETTING)</i>
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**
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** - 0 = CR is not trimmed at startup
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** - 1 = CR is trimmed at startup
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******************************************************************************/
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#define CR_TRIM_SETUP 1 // <<< Define CR trimming at startup enable here
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/******************************************************************************/
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/* */
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/* END OF USER SETTINGS HERE */
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/* ========================= */
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/* */
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/******************************************************************************/
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/******************************************************************************/
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/* Device dependent System Clock absolute maximum ranges */
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/******************************************************************************/
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/**
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******************************************************************************
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** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]UL)
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** <i>(USER SETTING)</i>
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******************************************************************************/
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#define __CLKHC ( 4000000UL) /* Internal 4MHz CR Oscillator */
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/**
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******************************************************************************
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** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]UL)
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** <i>(USER SETTING)</i>
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******************************************************************************/
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#define __CLKLC ( 100000UL) /* Internal 100KHz CR Oscillator */
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/**
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******************************************************************************
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** \brief Any case minimum Main Clock frequency (in Hz, [value]UL)
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** <i>(DEVICE DEPENDENT SETTING)</i>
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******************************************************************************/
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#define __CLKMOMIN ( 4000000UL)
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/**
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******************************************************************************
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** \brief Maximum Main Clock frequency using external clock
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** <i>(DEVICE DEPENDENT SETTING)</i>
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******************************************************************************/
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#define __CLKMOMAX ( 48000000UL)
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/**
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******************************************************************************
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** \brief Any case minimum Sub Clock frequency
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** <i>(DEVICE DEPENDENT SETTING)</i>
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******************************************************************************/
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#define __CLKSOMIN ( 32000UL)
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/**
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******************************************************************************
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** \brief Maximum Sub Clock frequency using external clock
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** <i>(DEVICE DEPENDENT SETTING)</i>
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******************************************************************************/
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#define __CLKSOMAX ( 100000UL)
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/**
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******************************************************************************
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** \brief Absolute minimum PLL input frequency
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** <i>(DEVICE DEPENDENT SETTING)</i>
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******************************************************************************/
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#define __PLLCLKINMIN ( 4000000UL)
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/**
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******************************************************************************
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** \brief Absolute maximum PLL input frequency
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** <i>(DEVICE DEPENDENT SETTING)</i>
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******************************************************************************/
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#define __PLLCLKINMAX ( 30000000UL)
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/**
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******************************************************************************
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** \brief Absolute minimum PLL oscillation frequency
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** <i>(DEVICE DEPENDENT SETTING)</i>
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******************************************************************************/
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#define __PLLCLKMIN ( 60000000UL)
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/**
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******************************************************************************
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** \brief Absolute maximum PLL oscillation frequency
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** <i>(DEVICE DEPENDENT SETTING)</i>
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******************************************************************************/
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#define __PLLCLKMAX (120000000UL)
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/**
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******************************************************************************
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** \brief Absolute maximum System Clock frequency (HCLK)
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** <i>(DEVICE DEPENDENT SETTING)</i>
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******************************************************************************/
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#define __HCLKMAX ( 80000000UL)
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/**
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******************************************************************************
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** \brief Preprocessor macro for checking range (clock settings)
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******************************************************************************/
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#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
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/**
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******************************************************************************
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** \brief Preprocessor macro for checking bits with mask (clock settings)
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******************************************************************************/
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#define CHECK_RSVD(val, mask) (val & mask)
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/******************************************************************************/
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/* Check register settings */
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/******************************************************************************/
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#if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FA))
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#error "SCM_CTL: Invalid values of reserved bits!"
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#endif
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#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10)
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#error "SCM_CTL: CLKPLL is selected but PLL is not enabled!"
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#endif
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#if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007F))
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#error "CSW_TMR: Invalid values of reserved bits!"
|
|
#endif
|
|
|
|
#if ((SCM_CTL_Val & 0x10)) /* if PLL is used */
|
|
#if (CHECK_RSVD((PSW_TMR_val), ~0x00000007))
|
|
#error "PSW_TMR: Invalid values of reserved bits!"
|
|
#endif
|
|
|
|
#if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF))
|
|
#error "PLL_CTL1: Invalid values of reserved bits!"
|
|
#endif
|
|
|
|
#if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003F))
|
|
#error "PLL_CTL2: Invalid values of reserved bits!"
|
|
#endif
|
|
#endif
|
|
|
|
#if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007))
|
|
#error "BSC_PSR: Invalid values of reserved bits!"
|
|
#endif
|
|
|
|
#if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003))
|
|
#error "APBC0_PSR: Invalid values of reserved bits!"
|
|
#endif
|
|
|
|
#if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000083))
|
|
#error "APBC1_PSR: Invalid values of reserved bits!"
|
|
#endif
|
|
|
|
#if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000083))
|
|
#error "APBC2_PSR: Invalid values of reserved bits!"
|
|
#endif
|
|
|
|
#if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003))
|
|
#error "SWC_PSR: Invalid values of reserved bits!"
|
|
#endif
|
|
|
|
#if (CHECK_RSVD((TTC_PSR_Val), ~0x00000001))
|
|
#error "TTC_PSR: Invalid values of reserved bits!"
|
|
#endif
|
|
|
|
/******************************************************************************/
|
|
/* Define clocks with checking settings */
|
|
/******************************************************************************/
|
|
|
|
/**
|
|
******************************************************************************
|
|
** \brief Calculate PLL K factor from settings
|
|
******************************************************************************/
|
|
#define __PLLK (((PLL_CTL1_Val >> 4) & 0x0F) + 1)
|
|
|
|
/**
|
|
******************************************************************************
|
|
** \brief Calculate PLL N factor from settings
|
|
******************************************************************************/
|
|
#define __PLLN (((PLL_CTL2_Val ) & 0x1F) + 1)
|
|
|
|
/**
|
|
******************************************************************************
|
|
** \brief Calculate PLL M factor from settings
|
|
******************************************************************************/
|
|
#define __PLLM (((PLL_CTL1_Val ) & 0x0F) + 1)
|
|
|
|
/**
|
|
******************************************************************************
|
|
** \brief Calculate PLL output frequency from settings
|
|
******************************************************************************/
|
|
#define __PLLCLK ((__CLKMO * __PLLN) / __PLLK)
|
|
|
|
/******************************************************************************/
|
|
/* Determine core clock frequency according to settings */
|
|
/******************************************************************************/
|
|
|
|
/**
|
|
******************************************************************************
|
|
** \brief Define Master Clock from settings
|
|
******************************************************************************/
|
|
#if (((SCM_CTL_Val >> 5) & 0x07) == 0)
|
|
#define __MASTERCLK (__CLKHC)
|
|
#elif (((SCM_CTL_Val >> 5) & 0x07) == 1)
|
|
#define __MASTERCLK (__CLKMO)
|
|
#elif (((SCM_CTL_Val >> 5) & 0x07) == 2)
|
|
#define __MASTERCLK (__PLLCLK)
|
|
#elif (((SCM_CTL_Val >> 5) & 0x07) == 4)
|
|
#define __MASTERCLK (__CLKLC)
|
|
#elif (((SCM_CTL_Val >> 5) & 0x07) == 5)
|
|
#define __MASTERCLK (__CLKSO)
|
|
#else
|
|
#define __MASTERCLK (0UL)
|
|
#endif
|
|
|
|
/**
|
|
******************************************************************************
|
|
** \brief Define System Clock Frequency (Core Clock) from settings
|
|
******************************************************************************/
|
|
#if ((BSC_PSR_Val & 0x07) == 0)
|
|
#define __HCLK (__MASTERCLK / 1)
|
|
#elif ((BSC_PSR_Val & 0x07) == 1)
|
|
#define __HCLK (__MASTERCLK / 2)
|
|
#elif ((BSC_PSR_Val & 0x07) == 2)
|
|
#define __HCLK (__MASTERCLK / 3)
|
|
#elif ((BSC_PSR_Val & 0x07) == 3)
|
|
#define __HCLK (__MASTERCLK / 4)
|
|
#elif ((BSC_PSR_Val & 0x07) == 4)
|
|
#define __HCLK (__MASTERCLK / 6)
|
|
#elif ((BSC_PSR_Val & 0x07) == 5)
|
|
#define __HCLK (__MASTERCLK / 8)
|
|
#elif ((BSC_PSR_Val & 0x07) == 6)
|
|
#define __HCLK (__MASTERCLK /16)
|
|
#else
|
|
#define __HCLK (0UL)
|
|
#endif
|
|
|
|
/******************************************************************************/
|
|
/* HCLK range check */
|
|
/******************************************************************************/
|
|
#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX) != 0)
|
|
#error "Main Oscillator Clock (CLKMO) out of range!"
|
|
#endif
|
|
|
|
#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX) != 0)
|
|
#error "Sub Oscillator Clock (CLKMO) out of range!"
|
|
#endif
|
|
|
|
#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX) != 0)
|
|
#error "PLL input frequency out of range!"
|
|
#endif
|
|
|
|
#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX) != 0)
|
|
#error "PLL oscillation frequency out of range!"
|
|
#endif
|
|
|
|
#if (CHECK_RANGE(__HCLK, 0, __HCLKMAX) != 0)
|
|
#error "System Clock (HCLK) out of range!"
|
|
#endif
|
|
|
|
/******************************************************************************/
|
|
/* Global function prototypes ('extern', definition in C source) */
|
|
/******************************************************************************/
|
|
|
|
extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
|
|
|
|
extern void SystemInit (void); // Initialize the system
|
|
|
|
extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __SYSTEM_MB9BF50X_H */
|