352 lines
14 KiB
C
352 lines
14 KiB
C
/**
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******************************************************************************
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* @file stm32f0xx_dma.h
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* @author MCD Application Team
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* @version V1.0.0
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* @date 23-March-2012
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* @brief This file contains all the functions prototypes for the DMA firmware
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* library.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F0XX_DMA_H
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#define __STM32F0XX_DMA_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f0xx.h"
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/** @addtogroup STM32F0xx_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup DMA
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief DMA Init structures definition
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*/
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typedef struct
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{
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uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
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uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
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uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
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This parameter can be a value of @ref DMA_data_transfer_direction */
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uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
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The data unit is equal to the configuration set in DMA_PeripheralDataSize
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or DMA_MemoryDataSize members depending in the transfer direction */
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uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
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This parameter can be a value of @ref DMA_peripheral_incremented_mode */
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uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
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This parameter can be a value of @ref DMA_memory_incremented_mode */
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uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
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This parameter can be a value of @ref DMA_peripheral_data_size */
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uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
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This parameter can be a value of @ref DMA_memory_data_size */
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uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
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This parameter can be a value of @ref DMA_circular_normal_mode
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@note: The circular buffer mode cannot be used if the memory-to-memory
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data transfer is configured on the selected Channel */
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uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
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This parameter can be a value of @ref DMA_priority_level */
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uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
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This parameter can be a value of @ref DMA_memory_to_memory */
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}DMA_InitTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup DMA_Exported_Constants
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* @{
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*/
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#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
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((PERIPH) == DMA1_Channel2) || \
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((PERIPH) == DMA1_Channel3) || \
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((PERIPH) == DMA1_Channel4) || \
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((PERIPH) == DMA1_Channel5))
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/** @defgroup DMA_data_transfer_direction
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* @{
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*/
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#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
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#define DMA_DIR_PeripheralDST DMA_CCR_DIR
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#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
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((DIR) == DMA_DIR_PeripheralDST))
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/**
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* @}
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*/
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/** @defgroup DMA_peripheral_incremented_mode
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* @{
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*/
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#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
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#define DMA_PeripheralInc_Enable DMA_CCR_PINC
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#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
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((STATE) == DMA_PeripheralInc_Enable))
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/**
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* @}
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*/
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/** @defgroup DMA_memory_incremented_mode
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* @{
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*/
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#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
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#define DMA_MemoryInc_Enable DMA_CCR_MINC
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#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
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((STATE) == DMA_MemoryInc_Enable))
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/**
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* @}
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*/
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/** @defgroup DMA_peripheral_data_size
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* @{
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*/
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#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
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#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
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#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
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#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
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((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
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((SIZE) == DMA_PeripheralDataSize_Word))
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/**
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* @}
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*/
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/** @defgroup DMA_memory_data_size
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* @{
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*/
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#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
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#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
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#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
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#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
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((SIZE) == DMA_MemoryDataSize_HalfWord) || \
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((SIZE) == DMA_MemoryDataSize_Word))
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/**
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* @}
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*/
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/** @defgroup DMA_circular_normal_mode
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* @{
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*/
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#define DMA_Mode_Normal ((uint32_t)0x00000000)
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#define DMA_Mode_Circular DMA_CCR_CIRC
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#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
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/**
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* @}
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*/
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/** @defgroup DMA_priority_level
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* @{
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*/
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#define DMA_Priority_VeryHigh DMA_CCR_PL
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#define DMA_Priority_High DMA_CCR_PL_1
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#define DMA_Priority_Medium DMA_CCR_PL_0
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#define DMA_Priority_Low ((uint32_t)0x00000000)
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#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
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((PRIORITY) == DMA_Priority_High) || \
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((PRIORITY) == DMA_Priority_Medium) || \
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((PRIORITY) == DMA_Priority_Low))
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/**
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* @}
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*/
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/** @defgroup DMA_memory_to_memory
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* @{
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*/
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#define DMA_M2M_Disable ((uint32_t)0x00000000)
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#define DMA_M2M_Enable DMA_CCR_MEM2MEM
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#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
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/**
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* @}
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*/
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/** @defgroup DMA_interrupts_definition
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* @{
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*/
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#define DMA_IT_TC DMA_CCR_TCIE
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#define DMA_IT_HT DMA_CCR_HTIE
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#define DMA_IT_TE DMA_CCR_TEIE
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#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
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#define DMA1_IT_GL1 DMA_ISR_GIF1
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#define DMA1_IT_TC1 DMA_ISR_TCIF1
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#define DMA1_IT_HT1 DMA_ISR_HTIF1
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#define DMA1_IT_TE1 DMA_ISR_TEIF1
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#define DMA1_IT_GL2 DMA_ISR_GIF2
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#define DMA1_IT_TC2 DMA_ISR_TCIF2
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#define DMA1_IT_HT2 DMA_ISR_HTIF2
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#define DMA1_IT_TE2 DMA_ISR_TEIF2
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#define DMA1_IT_GL3 DMA_ISR_GIF3
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#define DMA1_IT_TC3 DMA_ISR_TCIF3
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#define DMA1_IT_HT3 DMA_ISR_HTIF3
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#define DMA1_IT_TE3 DMA_ISR_TEIF3
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#define DMA1_IT_GL4 DMA_ISR_GIF4
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#define DMA1_IT_TC4 DMA_ISR_TCIF4
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#define DMA1_IT_HT4 DMA_ISR_HTIF4
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#define DMA1_IT_TE4 DMA_ISR_TEIF4
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#define DMA1_IT_GL5 DMA_ISR_GIF5
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#define DMA1_IT_TC5 DMA_ISR_TCIF5
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#define DMA1_IT_HT5 DMA_ISR_HTIF5
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#define DMA1_IT_TE5 DMA_ISR_TEIF5
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#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xFFF00000) == 0x00) && ((IT) != 0x00))
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#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
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((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
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((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
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((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
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((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
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((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
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((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
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((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
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((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
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((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5))
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/**
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* @}
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*/
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/** @defgroup DMA_flags_definition
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* @{
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*/
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#define DMA1_FLAG_GL1 DMA_ISR_GIF1
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#define DMA1_FLAG_TC1 DMA_ISR_TCIF1
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#define DMA1_FLAG_HT1 DMA_ISR_HTIF1
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#define DMA1_FLAG_TE1 DMA_ISR_TEIF1
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#define DMA1_FLAG_GL2 DMA_ISR_GIF2
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#define DMA1_FLAG_TC2 DMA_ISR_TCIF2
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#define DMA1_FLAG_HT2 DMA_ISR_HTIF2
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#define DMA1_FLAG_TE2 DMA_ISR_TEIF2
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#define DMA1_FLAG_GL3 DMA_ISR_GIF3
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#define DMA1_FLAG_TC3 DMA_ISR_TCIF3
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#define DMA1_FLAG_HT3 DMA_ISR_HTIF3
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#define DMA1_FLAG_TE3 DMA_ISR_TEIF3
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#define DMA1_FLAG_GL4 DMA_ISR_GIF4
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#define DMA1_FLAG_TC4 DMA_ISR_TCIF4
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#define DMA1_FLAG_HT4 DMA_ISR_HTIF4
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#define DMA1_FLAG_TE4 DMA_ISR_TEIF4
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#define DMA1_FLAG_GL5 DMA_ISR_GIF5
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#define DMA1_FLAG_TC5 DMA_ISR_TCIF5
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#define DMA1_FLAG_HT5 DMA_ISR_HTIF5
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#define DMA1_FLAG_TE5 DMA_ISR_TEIF5
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#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xFFF00000) == 0x00) && ((FLAG) != 0x00))
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#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
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((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
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((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
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((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
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((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
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((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
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((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
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((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
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((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
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((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5))
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/**
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* @}
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*/
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/** @defgroup DMA_Buffer_Size
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* @{
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*/
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#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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/* Function used to set the DMA configuration to the default reset state ******/
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void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
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/* Initialization and Configuration functions *********************************/
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void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
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void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
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void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
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/* Data Counter functions******************************************************/
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void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
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uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
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/* Interrupts and flags management functions **********************************/
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void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
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FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
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void DMA_ClearFlag(uint32_t DMA_FLAG);
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ITStatus DMA_GetITStatus(uint32_t DMA_IT);
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void DMA_ClearITPendingBit(uint32_t DMA_IT);
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#ifdef __cplusplus
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}
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#endif
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#endif /*__STM32F0XX_DMA_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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