311 lines
16 KiB
C
311 lines
16 KiB
C
//*****************************************************************************
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//
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// hw_des.h - Macros used when accessing the DES hardware.
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//
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// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_DES_H__
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#define __HW_DES_H__
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//*****************************************************************************
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//
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// The following are defines for the DES register offsets.
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//
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//*****************************************************************************
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#define DES_O_KEY3_L 0x00000000 // DES Key 3 LSW for 192-Bit Key
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#define DES_O_KEY3_H 0x00000004 // DES Key 3 MSW for 192-Bit Key
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#define DES_O_KEY2_L 0x00000008 // DES Key 2 LSW for 128-Bit Key
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#define DES_O_KEY2_H 0x0000000C // DES Key 2 MSW for 128-Bit Key
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#define DES_O_KEY1_L 0x00000010 // DES Key 1 LSW for 64-Bit Key
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#define DES_O_KEY1_H 0x00000014 // DES Key 1 MSW for 64-Bit Key
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#define DES_O_IV_L 0x00000018 // DES Initialization Vector
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#define DES_O_IV_H 0x0000001C // DES Initialization Vector
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#define DES_O_CTRL 0x00000020 // DES Control
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#define DES_O_LENGTH 0x00000024 // DES Cryptographic Data Length
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#define DES_O_DATA_L 0x00000028 // DES LSW Data RW
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#define DES_O_DATA_H 0x0000002C // DES MSW Data RW
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#define DES_O_REVISION 0x00000030 // DES Revision Number
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#define DES_O_SYSCONFIG 0x00000034 // DES System Configuration
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#define DES_O_SYSSTATUS 0x00000038 // DES System Status
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#define DES_O_IRQSTATUS 0x0000003C // DES Interrupt Status
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#define DES_O_IRQENABLE 0x00000040 // DES Interrupt Enable
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#define DES_O_DIRTYBITS 0x00000044 // DES Dirty Bits
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#define DES_O_DMAIM 0xFFFF8030 // DES DMA Interrupt Mask
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#define DES_O_DMARIS 0xFFFF8034 // DES DMA Raw Interrupt Status
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#define DES_O_DMAMIS 0xFFFF8038 // DES DMA Masked Interrupt Status
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#define DES_O_DMAIC 0xFFFF803C // DES DMA Interrupt Clear
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_KEY3_L register.
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//
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//*****************************************************************************
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#define DES_KEY3_L_KEY_M 0xFFFFFFFF // Key Data
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#define DES_KEY3_L_KEY_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_KEY3_H register.
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//
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//*****************************************************************************
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#define DES_KEY3_H_KEY_M 0xFFFFFFFF // Key Data
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#define DES_KEY3_H_KEY_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_KEY2_L register.
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//
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//*****************************************************************************
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#define DES_KEY2_L_KEY_M 0xFFFFFFFF // Key Data
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#define DES_KEY2_L_KEY_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_KEY2_H register.
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//
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//*****************************************************************************
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#define DES_KEY2_H_KEY_M 0xFFFFFFFF // Key Data
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#define DES_KEY2_H_KEY_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_KEY1_L register.
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//
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//*****************************************************************************
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#define DES_KEY1_L_KEY_M 0xFFFFFFFF // Key Data
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#define DES_KEY1_L_KEY_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_KEY1_H register.
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//
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//*****************************************************************************
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#define DES_KEY1_H_KEY_M 0xFFFFFFFF // Key Data
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#define DES_KEY1_H_KEY_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_IV_L register.
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//
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//*****************************************************************************
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#define DES_IV_L_M 0xFFFFFFFF // Initialization vector for CBC,
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// CFB modes (LSW)
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#define DES_IV_L_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_IV_H register.
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//
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//*****************************************************************************
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#define DES_IV_H_M 0xFFFFFFFF // Initialization vector for CBC,
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// CFB modes (MSW)
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#define DES_IV_H_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_CTRL register.
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//
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//*****************************************************************************
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#define DES_CTRL_CONTEXT 0x80000000 // If 1, this read-only status bit
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// indicates that the context data
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// registers can be overwritten and
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// the host is permitted to write
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// the next context
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#define DES_CTRL_MODE_M 0x00000030 // Select CBC, ECB or CFB mode0x0:
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// ECB mode0x1: CBC mode0x2: CFB
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// mode0x3: reserved
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#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES
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// encryption/decryption
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#define DES_CTRL_DIRECTION 0x00000004 // Select encryption/decryption
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// 0x0: decryption is selected0x1:
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// Encryption is selected
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#define DES_CTRL_INPUT_READY 0x00000002 // When 1, ready to encrypt/decrypt
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// data
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#define DES_CTRL_OUTPUT_READY 0x00000001 // When 1, Data decrypted/encrypted
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// ready
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#define DES_CTRL_MODE_S 4
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_LENGTH register.
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//
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//*****************************************************************************
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#define DES_LENGTH_M 0xFFFFFFFF // Cryptographic data length in
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// bytes for all modes
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#define DES_LENGTH_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_DATA_L register.
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//
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//*****************************************************************************
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#define DES_DATA_L_M 0xFFFFFFFF // Data for encryption/decryption,
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// LSW
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#define DES_DATA_L_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_DATA_H register.
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//
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//*****************************************************************************
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#define DES_DATA_H_M 0xFFFFFFFF // Data for encryption/decryption,
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// MSW
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#define DES_DATA_H_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_REVISION register.
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//
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//*****************************************************************************
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#define DES_REVISION_M 0xFFFFFFFF // Revision number
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#define DES_REVISION_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_SYSCONFIG
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// register.
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//
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//*****************************************************************************
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#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
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0x00000080 // DMA Request Context In Enable
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#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
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0x00000040 // DMA Request Data Out Enable
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#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
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0x00000020 // DMA Request Data In Enable
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#define DES_SYSCONFIG_SIDLE_M 0x0000000C // Sidle mode
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#define DES_SYSCONFIG_SIDLE_FORCE \
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0x00000000 // Force-idle mode
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#define DES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_SYSSTATUS
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// register.
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//
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//*****************************************************************************
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#define DES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_IRQSTATUS
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// register.
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//
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//*****************************************************************************
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#define DES_IRQSTATUS_DATA_OUT 0x00000004 // This bit indicates data output
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// interrupt is active and triggers
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// the interrupt output
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#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input
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// interrupt is active and triggers
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// the interrupt output
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#define DES_IRQSTATUS_CONTEX_IN 0x00000001 // This bit indicates context
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// interrupt is active and triggers
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// the interrupt output
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_IRQENABLE
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// register.
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//
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//*****************************************************************************
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#define DES_IRQENABLE_M_DATA_OUT \
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0x00000004 // If this bit is set to 1 the data
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// output interrupt is enabled
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#define DES_IRQENABLE_M_DATA_IN 0x00000002 // If this bit is set to 1 the data
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// input interrupt is enabled
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#define DES_IRQENABLE_M_CONTEX_IN \
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0x00000001 // If this bit is set to 1 the
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// context interrupt is enabled
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_DIRTYBITS
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// register.
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//
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//*****************************************************************************
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#define DES_DIRTYBITS_S_DIRTY 0x00000002 // This bit is set to 1 by the
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// module if any of the DES_*
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// registers is written
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#define DES_DIRTYBITS_S_ACCESS 0x00000001 // This bit is set to 1 by the
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// module if any of the DES_*
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// registers is read
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_DMAIM register.
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//
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//*****************************************************************************
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#define DES_DMAIM_DOUT 0x00000004 // Data Out DMA Done Interrupt Mask
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#define DES_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask
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#define DES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt
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// Mask
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_DMARIS register.
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//
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//*****************************************************************************
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#define DES_DMARIS_DOUT 0x00000004 // Data Out DMA Done Raw Interrupt
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// Status
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#define DES_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt
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// Status
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#define DES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw
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// Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_DMAMIS register.
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//
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//*****************************************************************************
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#define DES_DMAMIS_DOUT 0x00000004 // Data Out DMA Done Masked
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// Interrupt Status
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#define DES_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked
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// Interrupt Status
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#define DES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw
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// Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DES_O_DMAIC register.
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//
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//*****************************************************************************
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#define DES_DMAIC_DOUT 0x00000004 // Data Out DMA Done Interrupt
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// Clear
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#define DES_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear
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#define DES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw
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// Interrupt Status
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#endif // __HW_DES_H__
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