359 lines
9.7 KiB
C
359 lines
9.7 KiB
C
/*
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* File : mipscfg.c
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* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2010-05-27 swkyer first version
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*/
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#include <rtthread.h>
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#include "../common/mipsregs.h"
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#include "../common/mipscfg.h"
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mips32_core_cfg_t g_mips_core =
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{
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16, /* icache_line_size */
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256, /* icache_lines_per_way */
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4, /* icache_ways */
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16, /* dcache_line_size */
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256, /* dcache_lines_per_way */
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4, /* dcache_ways */
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16, /* max_tlb_entries */
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};
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static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
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{
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rt_uint16_t rets = 1;
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while (n--)
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rets *= b;
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return rets;
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}
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/**
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* read core attribute
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*/
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void mips32_cfg_init(void)
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{
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rt_uint16_t val;
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rt_uint32_t cp0_config1;
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cp0_config1 = read_c0_config();
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if (cp0_config1 & 0x80000000)
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{
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cp0_config1 = read_c0_config1();
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val = (cp0_config1 & (7<<22))>>22;
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g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
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val = (cp0_config1 & (7<<19))>>19;
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g_mips_core.icache_line_size = 2 * m_pow(2, val);
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val = (cp0_config1 & (7<<16))>>16;
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g_mips_core.icache_ways = val + 1;
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val = (cp0_config1 & (7<<13))>>13;
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g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
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val = (cp0_config1 & (7<<10))>>10;
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g_mips_core.dcache_line_size = 2 * m_pow(2, val);
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val = (cp0_config1 & (7<<7))>>7;
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g_mips_core.dcache_ways = val + 1;
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val = (cp0_config1 & (0x3F<<25))>>25;
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g_mips_core.max_tlb_entries = val + 1;
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}
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}
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#ifdef RT_USING_FINSH
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#include <finsh.h>
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static void CP0_status_analyze(unsigned long value)
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{
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if(value & (1<<26))
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rt_kprintf(" FR");
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if(value & (1<<23))
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rt_kprintf(" PX");
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if(value & (1<<22))
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rt_kprintf(" BEV");
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if(value & (1<<20))
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rt_kprintf(" SR");
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if(value & (1<<19))
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rt_kprintf(" NMI");
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if(value & (1<<20))
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rt_kprintf(" SR");
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if(value & (0xFF<<8))
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rt_kprintf(" IM:0x%02X", (value >> 8) & 0xFF);
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if(value & (1<<7))
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rt_kprintf(" KX");
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if(value & (1<<6))
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rt_kprintf(" SX");
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if(value & (1<<5))
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rt_kprintf(" UX");
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if(value & (0x03<<3))
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rt_kprintf(" KSU:0x%02X", (value >> 3) & 0x03);
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if(value & (1<<2))
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rt_kprintf(" ERL");
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if(value & (1<<1))
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rt_kprintf(" EXL");
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if(value & (1<<0))
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rt_kprintf(" IE");
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}
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static void CP0_config0_analyze(unsigned long value)
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{
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/* [31] M */
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if(value & (1UL<<31))
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rt_kprintf(" M");
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/* [15] BE */
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if(value & (1<<15))
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rt_kprintf(" big-endian");
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else
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rt_kprintf(" little-endian");
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/* [14:13] AT */
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{
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int AT = (value >> 13) & 0x03;
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if(AT == 0)
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{
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rt_kprintf(" MIPS32");
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}
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else if(AT == 1)
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{
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rt_kprintf(" MIPS64/A32");
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}
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else if(AT == 2)
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{
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rt_kprintf(" MIPS64/A64");
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}
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else
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{
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rt_kprintf(" unkown");
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}
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}
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/* [12:10] AR */
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{
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int AR = (value >> 10) & 0x07;
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if(AR == 0)
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{
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rt_kprintf(" R1");
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}
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else if(AR == 1)
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{
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rt_kprintf(" R2");
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}
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else
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{
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rt_kprintf(" reserve");
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}
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}
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/* [3] VI */
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if(value & (1UL<<31))
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rt_kprintf(" VI");
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/* [2:0] K0 */
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{
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int K0 = value & 0x07;
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if(K0 == 2)
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{
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rt_kprintf(" uncached");
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}
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else if(K0 == 3)
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{
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rt_kprintf(" cacheable");
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}
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else
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{
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rt_kprintf(" K0:reserve");
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}
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}
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}
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static void CP0_config1_analyze(unsigned long value)
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{
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/* [31] M */
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if(value & (1UL<<31))
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rt_kprintf(" M");
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/* [30:25] MMU size */
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{
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int MMU_size = (value >> 25) & 0x3F;
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rt_kprintf(" TLB:%d", MMU_size + 1);
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}
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/* [24:22] IS, [21:19] IL, [18:16] IA */
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{
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int IS = (value >> 22) & 0x07;
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int IL = (value >> 19) & 0x07;
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int IA = (value >> 16) & 0x07;
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IA = IA + 1;
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IS = 64 << IS;
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IL = 2 << IL;
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rt_kprintf(" Icache-%dKB:%dway*%dset*%dbyte",
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(IA*IS*IL) >> 10, IA, IS, IL);
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}
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/* [15:13] DS, [12:10] DL, [9:7] DA */
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{
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int DS = (value >> 13) & 0x07;
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int DL = (value >> 10) & 0x07;
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int DA = (value >> 7) & 0x07;
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DA = DA + 1;
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DS = 64 << DS;
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DL = 2 << DL;
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rt_kprintf(" Dcache-%dKB:%dway*%dset*%dbyte",
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(DA*DS*DL) >> 10, DA, DS, DL);
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}
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/* [6] C2 */
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if(value & (1UL<<6))
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rt_kprintf(" CP2");
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/* [5] MD */
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if(value & (1UL<<5))
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rt_kprintf(" MDMX-ASE");
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/* [4] PC */
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if(value & (1UL<<4))
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rt_kprintf(" performa-count");
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/* [3] WR */
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if(value & (1UL<<3))
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rt_kprintf(" Watch");
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/* [2] CA */
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if(value & (1UL<<2))
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rt_kprintf(" MIPS16e");
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/* [1] EP */
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if(value & (1UL<<1))
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rt_kprintf(" EJTAG");
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/* [0] FP */
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if(value & (1UL<<0))
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rt_kprintf(" FPU");
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}
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static void CP0_config2_analyze(unsigned long value)
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{
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/* [31] M */
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if(value & (1UL<<31))
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rt_kprintf(" M");
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}
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static void CP0_config3_analyze(unsigned long value)
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{
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/* [31] M */
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if(value & (1UL<<31))
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rt_kprintf(" M");
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}
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static void list_mips(void)
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{
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unsigned long value;
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unsigned long num = 0;
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rt_kprintf("MIPS coprocessor register:\r\n");
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rt_kprintf("( 0,0) INDEX : 0x%08X\r\n", read_c0_index());
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rt_kprintf("( 1,0) RANDOM : 0x%08X\r\n", read_c0_random());
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rt_kprintf("( 2,0) ENTRYLO0 : 0x%08X\r\n", read_c0_entrylo0());
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rt_kprintf("( 3,0) ENTRYLO1 : 0x%08X\r\n", read_c0_entrylo1());
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rt_kprintf("( 4,0) CONTEXT : 0x%08X\r\n", read_c0_context());
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rt_kprintf("( 5,0) PAGEMASK : 0x%08X\r\n", read_c0_pagemask());
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rt_kprintf("( 6,0) WIRED : 0x%08X\r\n", read_c0_wired());
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rt_kprintf("( 7,0) INFO : 0x%08X\r\n", read_c0_info());
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rt_kprintf("( 8,0) BADVADDR : 0x%08X\r\n", read_c0_badvaddr());
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rt_kprintf("( 9,0) COUNT : 0x%08X\r\n", read_c0_count());
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rt_kprintf("(10,0) ENTRYHI : 0x%08X\r\n", read_c0_entryhi());
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rt_kprintf("(11,0) COMPARE : 0x%08X\r\n", read_c0_compare());
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value = read_c0_status();
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rt_kprintf("(12,0) STATUS : 0x%08X", value);
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CP0_status_analyze(value);
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rt_kprintf("\r\n");
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/*
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rt_kprintf("(12,1) INTCTL : 0x%08X\r\n", __read_32bit_c0_register(12, 1));
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rt_kprintf("(12,2) SRSCTL : 0x%08X\r\n", __read_32bit_c0_register(12, 2));
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*/
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rt_kprintf("(13,0) CAUSE : 0x%08X\r\n", read_c0_cause());
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rt_kprintf("(14,0) EPC : 0x%08X\r\n", read_c0_epc());
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rt_kprintf("(15,0) PRID : 0x%08X\r\n", read_c0_prid());
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rt_kprintf("(15,1) EBASE : 0x%08X\r\n", read_c0_ebase());
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value = read_c0_config();
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rt_kprintf("(16,0) CONFIG : 0x%08X", value);
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CP0_config0_analyze(value);
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rt_kprintf("\r\n");
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if(value & (1UL << 31))
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{
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value = read_c0_config1();
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rt_kprintf("(16,1) CONFIG1 : 0x%08X", value);
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CP0_config1_analyze(value);
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rt_kprintf("\r\n");
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if(value & (1UL << 31))
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{
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value = read_c0_config2();
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rt_kprintf("(16,2) CONFIG2 : 0x%08X\r\n", value);
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CP0_config2_analyze(value);
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rt_kprintf("\r\n");
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if(value & (1UL << 31))
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{
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value = read_c0_config3();
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rt_kprintf("(16,3) CONFIG3 : 0x%08X\r\n", value);
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CP0_config3_analyze(value);
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rt_kprintf("\r\n");
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}
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}
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}
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rt_kprintf("(17,0) LLADDR : 0x%08X\r\n", __read_32bit_c0_register($17, 0));
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rt_kprintf("(18,0) WATCHLO : 0x%08X\r\n", __read_32bit_c0_register($18, 0));
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rt_kprintf("(19,0) WATCHHI : 0x%08X\r\n", __read_32bit_c0_register($19, 0));
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rt_kprintf("(20,0) XCONTEXT : 0x%08X\r\n", __read_32bit_c0_register($20, 0));
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rt_kprintf("(21,0) FRAMEMASK : 0x%08X\r\n", __read_32bit_c0_register($21, 0));
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rt_kprintf("(22,0) DIAGNOSTIC: 0x%08X\r\n", __read_32bit_c0_register($22, 0));
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rt_kprintf("(23,0) DEBUG : 0x%08X\r\n", __read_32bit_c0_register($23, 0));
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rt_kprintf("(24,0) DEPC : 0x%08X\r\n", __read_32bit_c0_register($24, 0));
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rt_kprintf("(25,0) PERFCTL0 : 0x%08X\r\n", __read_32bit_c0_register($25, 0));
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rt_kprintf("(26,0) ECC : 0x%08X\r\n", __read_32bit_c0_register($26, 0));
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rt_kprintf("(27,0) CACHEERR : 0x%08X\r\n", __read_32bit_c0_register($27, 0));
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rt_kprintf("(28,0) TAGLO : 0x%08X\r\n", __read_32bit_c0_register($28, 0));
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rt_kprintf("(29,0) TAGHI : 0x%08X\r\n", __read_32bit_c0_register($29, 0));
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/*
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rt_kprintf("(30,0) ERROREPC : 0x%08X\r\n", __read_32bit_c0_register($30, 0));
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rt_kprintf("(31,0) DESAVE : 0x%08X\r\n", __read_32bit_c0_register($31, 0));
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*/
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rt_kprintf("\r\n");
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}
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FINSH_FUNCTION_EXPORT(list_mips, list CPU info)
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#endif /* RT_USING_FINSH */
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