768 lines
25 KiB
C
768 lines
25 KiB
C
//*****************************************************************************
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//
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// onewire.c - Driver for OneWire master module.
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//
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// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup onewire_api
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//! @{
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//
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//*****************************************************************************
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include "inc/hw_ints.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_onewire.h"
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#include "inc/hw_sysctl.h"
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#include "inc/hw_types.h"
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#include "driverlib/debug.h"
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#include "driverlib/interrupt.h"
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#include "driverlib/onewire.h"
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#include "driverlib/sysctl.h"
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//*****************************************************************************
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//
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// A bit mask for all transaction related fields in the 1-Wire control
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// register.
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//
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//*****************************************************************************
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#define ONEWIRE_TXN_MASK (ONEWIRE_CS_OP_M | ONEWIRE_CS_SZ_M | \
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ONEWIRE_CS_BSIZE_M)
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//*****************************************************************************
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//
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// Left-shift value for the control register's transaction size.
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//
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//*****************************************************************************
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#define ONEWIRE_TXN_SIZE_LSHIFT 3
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//*****************************************************************************
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//
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// Left-shift value for the control register's last byte bit size.
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//
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//*****************************************************************************
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#define ONEWIRE_TXN_BSIZE_LSHIFT \
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16
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//*****************************************************************************
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//
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//! Initializes the 1-Wire module.
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//!
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//! \param ui32Base specifies the base address of the 1-Wire module.
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//! \param ui32InitFlags provides the initialization flags.
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//!
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//! This function configures and initializes the 1-Wire interface for use.
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//!
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//! The \e ui32InitFlags parameter is a combination of the following:
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//!
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//! - \b ONEWIRE_INIT_SPD_STD - standard speed bus timings
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//! - \b ONEWIRE_INIT_SPD_OD - overdrive speed bus timings
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//! - \b ONEWIRE_INIT_READ_STD - standard read sampling timing
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//! - \b ONEWIRE_INIT_READ_LATE - late read sampling timing
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//! - \b ONEWIRE_INIT_ATR - standard answer-to-reset presence detect
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//! - \b ONEWIRE_INIT_NO_ATR - no answer-to-reset presence detect
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//! - \b ONEWIRE_INIT_STD_POL - normal signal polarity
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//! - \b ONEWIRE_INIT_ALT_POL - alternate (reverse) signal polarity
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//! - \b ONEWIRE_INIT_1_WIRE_CFG - standard 1-Wire (1 data pin) setup
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//! - \b ONEWIRE_INIT_2_WIRE_CFG - alternate 2-Wire (2 data pin) setup
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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OneWireInit(uint32_t ui32Base, uint32_t ui32InitFlags)
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{
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//
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// Check the arguments.
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//
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ASSERT(ui32Base == ONEWIRE0_BASE);
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//
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// Initialize control register.
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//
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HWREG(ui32Base + ONEWIRE_O_CS) = ui32InitFlags;
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}
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//*****************************************************************************
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//
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//! Issues a reset on the 1-Wire bus.
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//!
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//! \param ui32Base specifies the base address of the 1-Wire module.
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//!
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//! This function causes the 1-Wire module to generate a reset signal on the
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//! 1-Wire bus.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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OneWireBusReset(uint32_t ui32Base)
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{
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//
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// Check the argument.
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//
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ASSERT(ui32Base == ONEWIRE0_BASE);
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//
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// Issue a bus reset.
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//
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HWREG(ui32Base + ONEWIRE_O_CS) |= ONEWIRE_CS_RST;
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}
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//*****************************************************************************
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//
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//! Retrieves the 1-Wire bus condition status.
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//!
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//! \param ui32Base specifies the base address of the 1-Wire module.
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//!
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//! This function returns the 1-Wire bus conditions reported by the 1-Wire
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//! module. These conditions could be a logical OR of any of the following:
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//!
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//! - \b ONEWIRE_BUS_STATUS_BUSY - A read, write, or reset is active.
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//! - \b ONEWIRE_BUS_STATUS_NO_SLAVE - No slave presence pulses detected.
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//! - \b ONEWIRE_BUS_STATUS_STUCK - The bus is being held low by non-master.
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//!
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//! \return Returns the 1-Wire bus conditions if detected else zero.
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//
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//*****************************************************************************
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uint32_t
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OneWireBusStatus(uint32_t ui32Base)
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{
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//
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// Check the argument.
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//
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ASSERT(ui32Base == ONEWIRE0_BASE);
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//
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// Return the status bits from control and status register.
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//
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return(HWREG(ui32Base + ONEWIRE_O_CS) & (ONEWIRE_CS_BUSY |
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ONEWIRE_CS_NOATR |
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ONEWIRE_CS_STUCK));
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}
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//*****************************************************************************
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//
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//! Retrieves data from the 1-Wire interface.
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//!
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//! \param ui32Base specifies the base address of the 1-Wire module.
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//! \param pui32Data is a pointer to storage to hold the read data.
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//!
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//! This function reads data from the 1-Wire module once all active bus
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//! operations are completed. By protocol definition, bit data defaults to
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//! a 1. Thus if a slave did not signal any 0-bit data, this read returns
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//! 0xffffffff.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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OneWireDataGet(uint32_t ui32Base, uint32_t *pui32Data)
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{
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//
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// Check the arguments.
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//
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ASSERT(ui32Base == ONEWIRE0_BASE);
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ASSERT(pui32Data);
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//
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// Wait for any active operations to complete.
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//
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while(HWREG(ui32Base + ONEWIRE_O_CS) & ONEWIRE_CS_BUSY)
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{
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}
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//
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// Copy the data into the provided storage.
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//
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*pui32Data = HWREG(ui32Base + ONEWIRE_O_DATR);
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}
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//*****************************************************************************
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//
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//! Retrieves data from the 1-Wire interface.
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//!
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//! \param ui32Base specifies the base address of the 1-Wire module.
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//! \param pui32Data is a pointer to storage to hold the read data.
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//!
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//! This function reads data from the 1-Wire module if there are no active
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//! operations on the bus. Otherwise it returns without reading the data from
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//! the module.
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//!
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//! By protocol definition, bit data defaults to a 1. Thus if a slave did
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//! not signal any 0-bit data, this read returns 0xffffffff.
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//!
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//! \return Returns \b true if a data read was performed, or \b false if the
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//! bus was not idle and no data was read.
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//
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//*****************************************************************************
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bool
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OneWireDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data)
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{
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//
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// Check the arguments.
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//
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ASSERT(ui32Base == ONEWIRE0_BASE);
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ASSERT(pui32Data);
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//
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// If the bus is busy, return without reading.
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//
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if(HWREG(ui32Base + ONEWIRE_O_CS) & ONEWIRE_CS_BUSY)
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{
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return(false);
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}
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//
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// Copy the data into the provided storage.
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//
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*pui32Data = HWREG(ui32Base + ONEWIRE_O_DATR);
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//
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// Notify the caller data was read from the read register.
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//
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return(true);
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}
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//*****************************************************************************
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//
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//! Clears the 1-Wire module interrupt sources.
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//!
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//! \param ui32Base specifies the base address of the 1-Wire module.
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//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
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//!
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//! This function clears the specified 1-Wire interrupt sources so that they no
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//! longer assert. This function must be called in the interrupt handler to
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//! keep the interrupts from being triggered again immediately upon exit. The
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//! \e ui32IntFlags parameter can be a logical OR of any of the following:
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//!
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//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed.
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//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. If a
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//! combined write and read operation was set up, the interrupt signals the
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//! read is done.
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//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave.
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//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master.
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//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed.
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//!
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//! \note Because there is a write buffer in the Cortex-M processor, it may
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//! take several clock cycles before the interrupt source is actually cleared.
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//! Therefore, it is recommended that the interrupt source be cleared early in
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//! the interrupt handler (as opposed to the very last action) to avoid
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//! returning from the interrupt handler before the interrupt source is
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//! actually cleared. Failure to do so may result in the interrupt handler
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//! being immediately reentered (because the interrupt controller still sees
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//! the interrupt source asserted).
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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OneWireIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
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{
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//
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// Check the argument.
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//
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ASSERT(ui32Base == ONEWIRE0_BASE);
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ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA |
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ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0);
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//
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// Clear the requested interrupts.
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//
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HWREG(ui32Base + ONEWIRE_O_ICR) = ui32IntFlags;
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}
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//*****************************************************************************
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//
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//! Disables individual 1-Wire module interrupt sources.
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//!
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//! \param ui32Base specifies the base address of the 1-Wire module.
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//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled.
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//!
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//! This function disables the indicated 1-Wire interrupt sources. The
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//! \e ui32IntFlags parameter can be a logical OR of any of the following:
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//!
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//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed.
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//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. If a
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//! combined write and read operation was set up, the interrupt signals the
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//! read is done.
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//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave.
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//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master.
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//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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OneWireIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
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{
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//
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// Check the arguments.
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//
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ASSERT(ui32Base == ONEWIRE0_BASE);
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ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA |
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ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0);
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//
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// Disable the requested interrupts.
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//
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HWREG(ui32Base + ONEWIRE_O_IM) &= ~ui32IntFlags;
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}
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//*****************************************************************************
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//
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//! Enables individual 1-Wire module interrupt sources.
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//!
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//! \param ui32Base specifies the base address of the 1-Wire module.
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//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled.
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//!
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//! This function enables the indicated 1-Wire interrupt sources. Only the
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//! sources that are enabled can be reflected to the processor interrupt;
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//! disabled sources have no effect on the processor. The \e ui32IntFlags
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//! parameter can be a logical OR of any of the following:
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//!
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//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed.
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//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. If a
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//! combined write and read operation was set up, the interrupt signals the
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//! read is done.
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//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave.
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//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master.
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//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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OneWireIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
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{
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//
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// Check the arguments.
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//
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ASSERT(ui32Base == ONEWIRE0_BASE);
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ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA |
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ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0);
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//
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// Enable the requested interrupts.
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//
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HWREG(ui32Base + ONEWIRE_O_IM) |= ui32IntFlags;
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}
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//*****************************************************************************
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//
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//! Gets the current 1-Wire interrupt status.
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//!
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//! \param ui32Base specifies the base address of the 1-Wire module.
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//! \param bMasked is \b false if the raw interrupt status is required or
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//! \b true if the masked interrupt status is required.
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//!
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//! This function returns the interrupt status for the 1-Wire module. Either
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//! the raw interrupt status or the status of interrupts that are allowed to
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//! reflect to the processor can be returned.
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//!
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//! \return Returns the masked or raw 1-Wire interrupt status, as a bit field
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//! of any of the following values:
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//!
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//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed.
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//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed.
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//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave.
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//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master.
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//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed
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//
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//*****************************************************************************
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uint32_t
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OneWireIntStatus(uint32_t ui32Base, bool bMasked)
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{
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//
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// Check the argument.
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//
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ASSERT(ui32Base == ONEWIRE0_BASE);
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//
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// Return either the interrupt status or the raw interrupt status as
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// requested.
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//
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if(bMasked)
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{
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return(HWREG(ui32Base + ONEWIRE_O_MIS));
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}
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else
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{
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return(HWREG(ui32Base + ONEWIRE_O_RIS));
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}
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}
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//*****************************************************************************
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//
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//! Returns the 1-Wire controller interrupt number.
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//!
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//! \param ui32Base specifies the 1-Wire module base address.
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//!
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//! This function returns the interrupt number for the 1-Wire module with the
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//! base address passed in the \e ui32Base parameter.
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//!
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//! \return Returns a 1-Wire interrupt number or 0 if the interrupt does not
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//! exist.
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//
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//*****************************************************************************
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static uint32_t
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_OneWireIntNumberGet(uint32_t ui32Base)
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{
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uint32_t ui32Int;
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ASSERT(ui32Base == ONEWIRE0_BASE);
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ui32Int = 0;
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//
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// Find the valid interrupt number for the 1-Wire module.
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//
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if(CLASS_IS_TM4C129)
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{
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ui32Int = INT_ONEWIRE0_TM4C129;
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}
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return(ui32Int);
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}
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//*****************************************************************************
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//
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//! Registers an interrupt handler for the 1-Wire module.
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//!
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//! \param ui32Base is the base address of the 1-Wire module.
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//! \param pfnHandler is a pointer to the function to be called when the
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//! 1-Wire interrupt occurs.
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//!
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//! This function sets the handler to be called when a 1-Wire interrupt occurs.
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//! This function enables the global interrupt in the interrupt controller;
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//! specific 1-Wire interrupts must be enabled via OneWireIntEnable(). If
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//! necessary, it is the interrupt handler's responsibility to clear the
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//! interrupt source via OneWireIntClear().
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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OneWireIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
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{
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uint32_t ui32Int;
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//
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// Check the argument.
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//
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ASSERT(ui32Base == ONEWIRE0_BASE);
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ASSERT(pfnHandler);
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//
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// Get the actual interrupt number for the 1-Wire module.
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//
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ui32Int = _OneWireIntNumberGet(ui32Base);
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ASSERT(ui32Int != 0);
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//
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// Register the interrupt handler.
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//
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IntRegister(ui32Int, pfnHandler);
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//
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// Enable the 1-Wire peripheral interrupt.
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//
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IntEnable(ui32Int);
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}
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//*****************************************************************************
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//
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//! Unregisters an interrupt handler for the 1-Wire module.
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//!
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//! \param ui32Base is the base address of the 1-Wire module.
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//!
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//! This function clears the handler to be called when an 1-Wire interrupt
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//! occurs. This function also masks off the interrupt in the interrupt
|
|
//! controller so that the interrupt handler no longer is called.
|
|
//!
|
|
//! \sa IntRegister() for important information about registering interrupt
|
|
//! handlers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
OneWireIntUnregister(uint32_t ui32Base)
|
|
{
|
|
uint32_t ui32Int;
|
|
|
|
//
|
|
// Check the argument.
|
|
//
|
|
ASSERT(ui32Base == ONEWIRE0_BASE);
|
|
|
|
//
|
|
// Get the actual interrupt number for the 1-Wire module.
|
|
//
|
|
ui32Int = _OneWireIntNumberGet(ui32Base);
|
|
ASSERT(ui32Int != 0);
|
|
|
|
//
|
|
// Disable the 1-Wire peripheral interrupt.
|
|
//
|
|
IntDisable(ui32Int);
|
|
|
|
//
|
|
// Unregister the interrupt handler.
|
|
//
|
|
IntUnregister(ui32Int);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables 1-Wire DMA operations.
|
|
//!
|
|
//! \param ui32Base is the base address of the 1-Wire module.
|
|
//! \param ui32DMAFlags is a bit mask of the DMA features to disable.
|
|
//!
|
|
//! This function is used to disable 1-Wire DMA features that were enabled
|
|
//! by OneWireDMAEnable(). The specified 1-Wire DMA features are disabled.
|
|
//! The \e ui32DMAFlags parameter is a combination of the following:
|
|
//!
|
|
//! - \b ONEWIRE_DMA_BUS_RESET - Issue a 1-Wire bus reset before starting
|
|
//! - \b ONEWIRE_DMA_OP_READ - Read after each module transaction
|
|
//! - \b ONEWIRE_DMA_OP_MULTI_WRITE - Write after each previous write
|
|
//! - \b ONEWIRE_DMA_OP_MULTI_READ - Read after each previous read
|
|
//! - \b ONEWIRE_DMA_MODE_SG - Start DMA on enable then repeat on each
|
|
//! completion
|
|
//! - \b ONEWIRE_DMA_OP_SZ_8 - Bus read/write of 8 bits
|
|
//! - \b ONEWIRE_DMA_OP_SZ_16 - Bus read/write of 16 bits
|
|
//! - \b ONEWIRE_DMA_OP_SZ_32 - Bus read/write of 32 bits
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
OneWireDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ui32Base == ONEWIRE0_BASE);
|
|
ASSERT(ui32DMAFlags > 0);
|
|
|
|
//
|
|
// Clear the transaction size bits
|
|
//
|
|
HWREG(ui32Base + ONEWIRE_O_CS) = (HWREG(ui32Base + ONEWIRE_O_CS) &
|
|
~(ONEWIRE_TXN_MASK));
|
|
|
|
//
|
|
// Disable the DMA features as requested.
|
|
//
|
|
HWREG(ui32Base + ONEWIRE_O_DMA) &= ~(ui32DMAFlags & 0xff);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables 1-Wire DMA operations.
|
|
//!
|
|
//! \param ui32Base is the base address of the 1-Wire module.
|
|
//! \param ui32DMAFlags is a bit mask of the DMA features to enable.
|
|
//!
|
|
//! This function enables the specified 1-Wire DMA features. The 1-Wire module
|
|
//! can be configured for write operations, read operations, small write and
|
|
//! read operations, and scatter-gather support of mixed operations.
|
|
//!
|
|
//! The \e ui32DMAFlags parameter is a combination of the following:
|
|
//!
|
|
//! - \b ONEWIRE_DMA_BUS_RESET - Issue a 1-Wire bus reset before starting
|
|
//! - \b ONEWIRE_DMA_OP_READ - Read after each module transaction
|
|
//! - \b ONEWIRE_DMA_OP_MULTI_WRITE - Write after each previous write
|
|
//! - \b ONEWIRE_DMA_OP_MULTI_READ - Read after each previous read
|
|
//! - \b ONEWIRE_DMA_MODE_SG - Start DMA on enable then repeat on each
|
|
//! completion
|
|
//! - \b ONEWIRE_DMA_OP_SZ_8 - Bus read/write of 8 bits
|
|
//! - \b ONEWIRE_DMA_OP_SZ_16 - Bus read/write of 16 bits
|
|
//! - \b ONEWIRE_DMA_OP_SZ_32 - Bus read/write of 32 bits
|
|
//!
|
|
//! \note The uDMA controller must be properly configured before DMA can be
|
|
//! used with the 1-Wire module.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
OneWireDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ui32Base == ONEWIRE0_BASE);
|
|
ASSERT(ui32DMAFlags > 0);
|
|
|
|
//
|
|
// set up the transaction size.
|
|
//
|
|
HWREG(ui32Base + ONEWIRE_O_CS) = ((HWREG(ui32Base + ONEWIRE_O_CS) &
|
|
~(ONEWIRE_TXN_MASK)) |
|
|
(ui32DMAFlags >> 8));
|
|
|
|
//
|
|
// Enable DMA with the parameters provided.
|
|
//
|
|
HWREG(ui32Base + ONEWIRE_O_DMA) = (ui32DMAFlags & 0xf);
|
|
|
|
//
|
|
// If a read transaction was requested, seed the write data register. This
|
|
// will trigger the DMA reads to start. This should not be done for
|
|
// scatter-gather operations.
|
|
//
|
|
if((ui32DMAFlags & (ONEWIRE_DMA_DMAOP_RDSNG | ONEWIRE_DMA_DMAOP_RDMUL)) &&
|
|
!(ui32DMAFlags & ONEWIRE_DMA_SG))
|
|
{
|
|
//
|
|
// Workaround for Snowflake DMA receive trigger errata.
|
|
//
|
|
if(CLASS_IS_TM4C129)
|
|
{
|
|
SysCtlDelay(9);
|
|
}
|
|
|
|
//
|
|
// Write DATW to trigger DMA receive start.
|
|
//
|
|
HWREG(ui32Base + ONEWIRE_O_DATW) = 0xffffffff;
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Performs a 1-Wire protocol transaction on the bus.
|
|
//!
|
|
//! \param ui32Base specifies the base address of the 1-Wire module.
|
|
//! \param ui32OpMode sets the transaction type.
|
|
//! \param ui32Data is the data for a write operation.
|
|
//! \param ui32BitCnt specifies the number of valid bits (1-32) for the
|
|
//! operation.
|
|
//!
|
|
//! This function performs a 1-Wire protocol transaction, read and/or write, on
|
|
//! the bus. The application should confirm the bus is idle before starting a
|
|
//! read or write transaction.
|
|
//!
|
|
//! The \e ui32OpMode defines the activity for the bus operations and is a
|
|
//! logical OR of the following:
|
|
//!
|
|
//! - \b ONEWIRE_OP_RESET - Indicates the operation should be started with
|
|
//! a bus reset.
|
|
//! - \b ONEWIRE_OP_WRITE - A write operation
|
|
//! - \b ONEWIRE_OP_READ - A read operation
|
|
//!
|
|
//! \note If both a read and write operation are requested, the write will be
|
|
//! performed prior to the read.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
OneWireTransaction(uint32_t ui32Base, uint32_t ui32OpMode, uint32_t ui32Data,
|
|
uint32_t ui32BitCnt)
|
|
{
|
|
uint32_t ui32Transaction;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ui32Base == ONEWIRE0_BASE);
|
|
ASSERT((ui32OpMode & (ONEWIRE_OP_RESET | ONEWIRE_OP_WRITE |
|
|
ONEWIRE_OP_READ)) > 0);
|
|
ASSERT((ui32BitCnt >= 1) && (ui32BitCnt <= 32));
|
|
|
|
//
|
|
// Read the control register and clear any transaction related
|
|
// bit fields.
|
|
//
|
|
ui32Transaction = HWREG(ui32Base + ONEWIRE_O_CS) & ~(ONEWIRE_TXN_MASK);
|
|
|
|
//
|
|
// Add the user specified operation flags.
|
|
//
|
|
ui32Transaction |= (ui32OpMode & (ONEWIRE_OP_RESET | ONEWIRE_OP_WRITE |
|
|
ONEWIRE_OP_READ));
|
|
|
|
//
|
|
// set up for a read or write transaction.
|
|
//
|
|
if(ui32Transaction & (ONEWIRE_CS_OP_WR | ONEWIRE_CS_OP_RD))
|
|
{
|
|
//
|
|
// Configure the 1-Wire module for the transaction size. This is
|
|
// specified as 1-4 bytes and the specific bit size for the last
|
|
// byte therein.
|
|
//
|
|
ui32Transaction |= ((((ui32BitCnt % 8) ? (ui32BitCnt / 8) + 1 :
|
|
(ui32BitCnt / 8)) - 1) <<
|
|
ONEWIRE_TXN_SIZE_LSHIFT);
|
|
ui32Transaction |= ((ui32BitCnt % 8) << ONEWIRE_TXN_BSIZE_LSHIFT);
|
|
|
|
//
|
|
// Write specific setup.
|
|
//
|
|
if(ui32Transaction & ONEWIRE_CS_OP_WR)
|
|
{
|
|
//
|
|
// Load the data into the write register.
|
|
//
|
|
HWREG(ui32Base + ONEWIRE_O_DATW) = ui32Data;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Start the transaction.
|
|
//
|
|
HWREG(ui32Base + ONEWIRE_O_CS) = ui32Transaction;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|