653 lines
26 KiB
ArmAsm
653 lines
26 KiB
ArmAsm
; /*
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; * File : start_rvds.s
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2009, RT-Thread Development Team
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; *
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; * The license and distribution terms for this file may be
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; * found in the file LICENSE in this distribution or at
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; * http://www.rt-thread.org/license/LICENSE
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2009-09-23 Bernard first implementation
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; * 2010-02-04 Magicoe Edit for LPC17xx Series
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; * 2011-08-06 Magicoe Edit for PK40X256VLQ100
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; */
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;/*****************************************************************************
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; * @file: startup_MK40N512MD100.s
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; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
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; * MK40N512MD100
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; * @version: 1.6
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; * @date: 2011-1-14
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; *
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; * Copyright: 1997 - 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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;*
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; *****************************************************************************/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00001000
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00001000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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IMPORT rt_hw_hard_fault
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IMPORT rt_hw_pend_sv
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IMPORT rt_hw_timer_handler
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD rt_hw_hard_fault ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD rt_hw_pend_sv ; PendSV Handler
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DCD rt_hw_timer_handler ; SysTick Handler
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; External Interrupts
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DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
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DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
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DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
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DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
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DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
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DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
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DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
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DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
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DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
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DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
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DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
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DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
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DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
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DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
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DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
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DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
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DCD DMA_Error_IRQHandler ; DMA Error Interrupt
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DCD MCM_IRQHandler ; Normal Interrupt
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DCD FTFL_IRQHandler ; FTFL Interrupt
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DCD Read_Collision_IRQHandler ; Read Collision Interrupt
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DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
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DCD LLW_IRQHandler ; Low Leakage Wakeup
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DCD Watchdog_IRQHandler ; WDOG Interrupt
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DCD Reserved39_IRQHandler ; Reserved interrupt 39
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DCD I2C0_IRQHandler ; I2C0 interrupt
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DCD I2C1_IRQHandler ; I2C1 interrupt
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DCD SPI0_IRQHandler ; SPI0 Interrupt
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DCD SPI1_IRQHandler ; SPI1 Interrupt
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DCD SPI2_IRQHandler ; SPI2 Interrupt
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DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd Message Buffers Interrupt
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DCD CAN0_Bus_Off_IRQHandler ; CAN0 Bus Off Interrupt
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DCD CAN0_Error_IRQHandler ; CAN0 Error Interrupt
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DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx Warning Interrupt
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DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx Warning Interrupt
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DCD CAN0_Wake_Up_IRQHandler ; CAN0 Wake Up Interrupt
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DCD Reserved51_IRQHandler ; Reserved interrupt 51
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DCD Reserved52_IRQHandler ; Reserved interrupt 52
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DCD CAN1_ORed_Message_buffer_IRQHandler ; CAN1 OR'd Message Buffers Interrupt
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DCD CAN1_Bus_Off_IRQHandler ; CAN1 Bus Off Interrupt
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DCD CAN1_Error_IRQHandler ; CAN1 Error Interrupt
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DCD CAN1_Tx_Warning_IRQHandler ; CAN1 Tx Warning Interrupt
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DCD CAN1_Rx_Warning_IRQHandler ; CAN1 Rx Warning Interrupt
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DCD CAN1_Wake_Up_IRQHandler ; CAN1 Wake Up Interrupt
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DCD Reserved59_IRQHandler ; Reserved interrupt 59
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DCD Reserved60_IRQHandler ; Reserved interrupt 60
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DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
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DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
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DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
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DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
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DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
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DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
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DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
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DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
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DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
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DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
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DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
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DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
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DCD ADC0_IRQHandler ; ADC0 interrupt
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DCD ADC1_IRQHandler ; ADC1 interrupt
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DCD CMP0_IRQHandler ; CMP0 interrupt
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DCD CMP1_IRQHandler ; CMP1 interrupt
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DCD CMP2_IRQHandler ; CMP2 interrupt
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DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
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DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
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DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
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DCD CMT_IRQHandler ; CMT interrupt
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DCD RTC_IRQHandler ; RTC interrupt
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DCD Reserved83_IRQHandler ; Reserved interrupt 83
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DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
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DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
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DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
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DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
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DCD PDB0_IRQHandler ; PDB0 Interrupt
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DCD USB0_IRQHandler ; USB0 interrupt
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DCD USBDCD_IRQHandler ; USBDCD Interrupt
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DCD Reserved91_IRQHandler ; Reserved interrupt 91
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DCD Reserved92_IRQHandler ; Reserved interrupt 92
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DCD Reserved93_IRQHandler ; Reserved interrupt 93
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DCD Reserved94_IRQHandler ; Reserved interrupt 94
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DCD I2S0_IRQHandler ; I2S0 Interrupt
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DCD SDHC_IRQHandler ; SDHC Interrupt
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DCD DAC0_IRQHandler ; DAC0 interrupt
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DCD DAC1_IRQHandler ; DAC1 interrupt
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DCD TSI0_IRQHandler ; TSI0 Interrupt
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DCD MCG_IRQHandler ; MCG Interrupt
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DCD LPTimer_IRQHandler ; LPTimer interrupt
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DCD LCD_IRQHandler ; Segment LCD Interrupt
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DCD PORTA_IRQHandler ; Port A interrupt
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DCD PORTB_IRQHandler ; Port B interrupt
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DCD PORTC_IRQHandler ; Port C interrupt
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DCD PORTD_IRQHandler ; Port D interrupt
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DCD PORTE_IRQHandler ; Port E interrupt
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DCD Reserved108_IRQHandler ; Reserved interrupt 108
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DCD Reserved109_IRQHandler ; Reserved interrupt 109
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DCD Reserved110_IRQHandler ; Reserved interrupt 110
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DCD Reserved111_IRQHandler ; Reserved interrupt 111
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DCD Reserved112_IRQHandler ; Reserved interrupt 112
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DCD Reserved113_IRQHandler ; Reserved interrupt 113
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DCD Reserved114_IRQHandler ; Reserved interrupt 114
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DCD Reserved115_IRQHandler ; Reserved interrupt 115
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DCD Reserved116_IRQHandler ; Reserved interrupt 116
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DCD Reserved117_IRQHandler ; Reserved interrupt 117
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DCD Reserved118_IRQHandler ; Reserved interrupt 118
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DCD Reserved119_IRQHandler ; Reserved interrupt 119
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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; <h> Flash Configuration
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; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
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; <i> and security information that allows the MCU to restrict acces to the FTFL module.
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; <h> Backdoor Comparison Key
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; <o0> Backdoor Key 0 <0x0-0xFF:2>
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; <o1> Backdoor Key 1 <0x0-0xFF:2>
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; <o2> Backdoor Key 2 <0x0-0xFF:2>
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; <o3> Backdoor Key 3 <0x0-0xFF:2>
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; <o4> Backdoor Key 4 <0x0-0xFF:2>
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; <o5> Backdoor Key 5 <0x0-0xFF:2>
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; <o6> Backdoor Key 6 <0x0-0xFF:2>
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; <o7> Backdoor Key 7 <0x0-0xFF:2>
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BackDoorK0 EQU 0xFF
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BackDoorK1 EQU 0xFF
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BackDoorK2 EQU 0xFF
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BackDoorK3 EQU 0xFF
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BackDoorK4 EQU 0xFF
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BackDoorK5 EQU 0xFF
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BackDoorK6 EQU 0xFF
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BackDoorK7 EQU 0xFF
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; </h>
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; <h> Program flash protection bytes (FPROT)
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; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
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; <i> Each bit protects a 1/32 region of the program flash memory.
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; <h> FPROT0
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; <i> Program flash protection bytes
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; <i> 1/32 - 8/32 region
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; <o.0> FPROT0.0
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; <o.1> FPROT0.1
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; <o.2> FPROT0.2
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; <o.3> FPROT0.3
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; <o.4> FPROT0.4
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; <o.5> FPROT0.5
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; <o.6> FPROT0.6
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; <o.7> FPROT0.7
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nFPROT0 EQU 0x00
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FPROT0 EQU nFPROT0:EOR:0xFF
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; </h>
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; <h> FPROT1
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; <i> Program Flash Region Protect Register 1
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; <i> 9/32 - 16/32 region
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; <o.0> FPROT1.0
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; <o.1> FPROT1.1
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; <o.2> FPROT1.2
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; <o.3> FPROT1.3
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; <o.4> FPROT1.4
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; <o.5> FPROT1.5
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; <o.6> FPROT1.6
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; <o.7> FPROT1.7
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nFPROT1 EQU 0x00
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FPROT1 EQU nFPROT1:EOR:0xFF
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; </h>
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; <h> FPROT2
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; <i> Program Flash Region Protect Register 2
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; <i> 17/32 - 24/32 region
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; <o.0> FPROT2.0
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; <o.1> FPROT2.1
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; <o.2> FPROT2.2
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; <o.3> FPROT2.3
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; <o.4> FPROT2.4
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; <o.5> FPROT2.5
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; <o.6> FPROT2.6
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; <o.7> FPROT2.7
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nFPROT2 EQU 0x00
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FPROT2 EQU nFPROT2:EOR:0xFF
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; </h>
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; <h> FPROT3
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; <i> Program Flash Region Protect Register 3
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; <i> 25/32 - 32/32 region
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; <o.0> FPROT3.0
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; <o.1> FPROT3.1
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; <o.2> FPROT3.2
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; <o.3> FPROT3.3
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; <o.4> FPROT3.4
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; <o.5> FPROT3.5
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; <o.6> FPROT3.6
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; <o.7> FPROT3.7
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nFPROT3 EQU 0x00
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FPROT3 EQU nFPROT3:EOR:0xFF
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; </h>
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; </h>
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; <h> Data flash protection byte (FDPROT)
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; <i> Each bit protects a 1/8 region of the data flash memory.
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; <i> (Program flash only devices: Reserved)
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; <o.0> FDPROT.0
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; <o.1> FDPROT.1
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; <o.2> FDPROT.2
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; <o.3> FDPROT.3
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; <o.4> FDPROT.4
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; <o.5> FDPROT.5
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; <o.6> FDPROT.6
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; <o.7> FDPROT.7
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nFDPROT EQU 0x00
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FDPROT EQU nFDPROT:EOR:0xFF
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; </h>
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; <h> EEPROM protection byte (FEPROT)
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; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
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; <i> (Program flash only devices: Reserved)
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; <o.0> FEPROT.0
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; <o.1> FEPROT.1
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; <o.2> FEPROT.2
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; <o.3> FEPROT.3
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; <o.4> FEPROT.4
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; <o.5> FEPROT.5
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; <o.6> FEPROT.6
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; <o.7> FEPROT.7
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nFEPROT EQU 0x00
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FEPROT EQU nFEPROT:EOR:0xFF
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; </h>
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; <h> Flash nonvolatile option byte (FOPT)
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; <i> Allows the user to customize the operation of the MCU at boot time.
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; <o.0> LPBOOT
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; <0=> Low-power boot
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; <1=> normal boot
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; <o.1> EZPORT_DIS
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; <0=> EzPort operation is enabled
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; <1=> EzPort operation is disabled
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FOPT EQU 0xFF
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; </h>
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; <h> Flash security byte (FSEC)
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; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
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; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
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; <o.0..1> SEC
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; <2=> MCU security status is unsecure
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; <3=> MCU security status is secure
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; <i> Flash Security
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; <i> This bits define the security state of the MCU.
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; <o.2..3> FSLACC
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; <2=> Freescale factory access denied
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; <3=> Freescale factory access granted
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; <i> Freescale Failure Analysis Access Code
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; <i> This bits define the security state of the MCU.
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; <o.4..5> MEEN
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; <2=> Mass erase is disabled
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; <3=> Mass erase is enabled
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; <i> Mass Erase Enable Bits
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; <i> Enables and disables mass erase capability of the FTFL module
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; <o.6..7> KEYEN
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; <2=> Backdoor key access enabled
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; <3=> Backdoor key access disabled
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; <i> Backdoor key Security Enable
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; <i> These bits enable and disable backdoor key access to the FTFL module.
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FSEC EQU 0xFE
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; </h>
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; </h>
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IF :LNOT::DEF:RAM_TARGET
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AREA |.ARM.__at_0x400|, CODE, READONLY
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DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
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DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
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DCB FPROT0, FPROT1, FPROT2, FPROT3
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DCB FSEC, FOPT, FEPROT, FDPROT
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT DMA0_IRQHandler [WEAK]
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EXPORT DMA1_IRQHandler [WEAK]
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EXPORT DMA2_IRQHandler [WEAK]
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EXPORT DMA3_IRQHandler [WEAK]
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EXPORT DMA4_IRQHandler [WEAK]
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EXPORT DMA5_IRQHandler [WEAK]
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EXPORT DMA6_IRQHandler [WEAK]
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EXPORT DMA7_IRQHandler [WEAK]
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EXPORT DMA8_IRQHandler [WEAK]
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EXPORT DMA9_IRQHandler [WEAK]
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EXPORT DMA10_IRQHandler [WEAK]
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EXPORT DMA11_IRQHandler [WEAK]
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EXPORT DMA12_IRQHandler [WEAK]
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EXPORT DMA13_IRQHandler [WEAK]
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EXPORT DMA14_IRQHandler [WEAK]
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EXPORT DMA15_IRQHandler [WEAK]
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EXPORT DMA_Error_IRQHandler [WEAK]
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EXPORT MCM_IRQHandler [WEAK]
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EXPORT FTFL_IRQHandler [WEAK]
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EXPORT Read_Collision_IRQHandler [WEAK]
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EXPORT LVD_LVW_IRQHandler [WEAK]
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EXPORT LLW_IRQHandler [WEAK]
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EXPORT Watchdog_IRQHandler [WEAK]
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EXPORT Reserved39_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
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EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
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EXPORT CAN0_Error_IRQHandler [WEAK]
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EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
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EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
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EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
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EXPORT Reserved51_IRQHandler [WEAK]
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EXPORT Reserved52_IRQHandler [WEAK]
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EXPORT CAN1_ORed_Message_buffer_IRQHandler [WEAK]
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EXPORT CAN1_Bus_Off_IRQHandler [WEAK]
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EXPORT CAN1_Error_IRQHandler [WEAK]
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EXPORT CAN1_Tx_Warning_IRQHandler [WEAK]
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EXPORT CAN1_Rx_Warning_IRQHandler [WEAK]
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EXPORT CAN1_Wake_Up_IRQHandler [WEAK]
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EXPORT Reserved59_IRQHandler [WEAK]
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EXPORT Reserved60_IRQHandler [WEAK]
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EXPORT UART0_RX_TX_IRQHandler [WEAK]
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EXPORT UART0_ERR_IRQHandler [WEAK]
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EXPORT UART1_RX_TX_IRQHandler [WEAK]
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EXPORT UART1_ERR_IRQHandler [WEAK]
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EXPORT UART2_RX_TX_IRQHandler [WEAK]
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EXPORT UART2_ERR_IRQHandler [WEAK]
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EXPORT UART3_RX_TX_IRQHandler [WEAK]
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EXPORT UART3_ERR_IRQHandler [WEAK]
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EXPORT UART4_RX_TX_IRQHandler [WEAK]
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EXPORT UART4_ERR_IRQHandler [WEAK]
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EXPORT UART5_RX_TX_IRQHandler [WEAK]
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EXPORT UART5_ERR_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
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EXPORT ADC1_IRQHandler [WEAK]
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EXPORT CMP0_IRQHandler [WEAK]
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EXPORT CMP1_IRQHandler [WEAK]
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EXPORT CMP2_IRQHandler [WEAK]
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EXPORT FTM0_IRQHandler [WEAK]
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EXPORT FTM1_IRQHandler [WEAK]
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EXPORT FTM2_IRQHandler [WEAK]
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EXPORT CMT_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT Reserved83_IRQHandler [WEAK]
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EXPORT PIT0_IRQHandler [WEAK]
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EXPORT PIT1_IRQHandler [WEAK]
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EXPORT PIT2_IRQHandler [WEAK]
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EXPORT PIT3_IRQHandler [WEAK]
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EXPORT PDB0_IRQHandler [WEAK]
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EXPORT USB0_IRQHandler [WEAK]
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EXPORT USBDCD_IRQHandler [WEAK]
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EXPORT Reserved91_IRQHandler [WEAK]
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EXPORT Reserved92_IRQHandler [WEAK]
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EXPORT Reserved93_IRQHandler [WEAK]
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EXPORT Reserved94_IRQHandler [WEAK]
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EXPORT I2S0_IRQHandler [WEAK]
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EXPORT SDHC_IRQHandler [WEAK]
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EXPORT DAC0_IRQHandler [WEAK]
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EXPORT DAC1_IRQHandler [WEAK]
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EXPORT TSI0_IRQHandler [WEAK]
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EXPORT MCG_IRQHandler [WEAK]
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EXPORT LPTimer_IRQHandler [WEAK]
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EXPORT LCD_IRQHandler [WEAK]
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EXPORT PORTA_IRQHandler [WEAK]
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EXPORT PORTB_IRQHandler [WEAK]
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EXPORT PORTC_IRQHandler [WEAK]
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EXPORT PORTD_IRQHandler [WEAK]
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EXPORT PORTE_IRQHandler [WEAK]
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EXPORT Reserved108_IRQHandler [WEAK]
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EXPORT Reserved109_IRQHandler [WEAK]
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EXPORT Reserved110_IRQHandler [WEAK]
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EXPORT Reserved111_IRQHandler [WEAK]
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EXPORT Reserved112_IRQHandler [WEAK]
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EXPORT Reserved113_IRQHandler [WEAK]
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EXPORT Reserved114_IRQHandler [WEAK]
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EXPORT Reserved115_IRQHandler [WEAK]
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EXPORT Reserved116_IRQHandler [WEAK]
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EXPORT Reserved117_IRQHandler [WEAK]
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EXPORT Reserved118_IRQHandler [WEAK]
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EXPORT Reserved119_IRQHandler [WEAK]
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DMA0_IRQHandler
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DMA1_IRQHandler
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DMA2_IRQHandler
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DMA3_IRQHandler
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DMA4_IRQHandler
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DMA5_IRQHandler
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DMA6_IRQHandler
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DMA7_IRQHandler
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DMA8_IRQHandler
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DMA9_IRQHandler
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DMA10_IRQHandler
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DMA11_IRQHandler
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DMA12_IRQHandler
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DMA13_IRQHandler
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DMA14_IRQHandler
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DMA15_IRQHandler
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DMA_Error_IRQHandler
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MCM_IRQHandler
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FTFL_IRQHandler
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Read_Collision_IRQHandler
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LVD_LVW_IRQHandler
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LLW_IRQHandler
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|
Watchdog_IRQHandler
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Reserved39_IRQHandler
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I2C0_IRQHandler
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I2C1_IRQHandler
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SPI0_IRQHandler
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SPI1_IRQHandler
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SPI2_IRQHandler
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CAN0_ORed_Message_buffer_IRQHandler
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CAN0_Bus_Off_IRQHandler
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CAN0_Error_IRQHandler
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CAN0_Tx_Warning_IRQHandler
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CAN0_Rx_Warning_IRQHandler
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CAN0_Wake_Up_IRQHandler
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Reserved51_IRQHandler
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Reserved52_IRQHandler
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CAN1_ORed_Message_buffer_IRQHandler
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CAN1_Bus_Off_IRQHandler
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CAN1_Error_IRQHandler
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CAN1_Tx_Warning_IRQHandler
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CAN1_Rx_Warning_IRQHandler
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CAN1_Wake_Up_IRQHandler
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Reserved59_IRQHandler
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Reserved60_IRQHandler
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UART0_RX_TX_IRQHandler
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UART0_ERR_IRQHandler
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|
UART1_RX_TX_IRQHandler
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UART1_ERR_IRQHandler
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|
UART2_RX_TX_IRQHandler
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|
UART2_ERR_IRQHandler
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|
UART3_RX_TX_IRQHandler
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|
UART3_ERR_IRQHandler
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|
UART4_RX_TX_IRQHandler
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|
UART4_ERR_IRQHandler
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|
UART5_RX_TX_IRQHandler
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|
UART5_ERR_IRQHandler
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|
ADC0_IRQHandler
|
|
ADC1_IRQHandler
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|
CMP0_IRQHandler
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|
CMP1_IRQHandler
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|
CMP2_IRQHandler
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|
FTM0_IRQHandler
|
|
FTM1_IRQHandler
|
|
FTM2_IRQHandler
|
|
CMT_IRQHandler
|
|
RTC_IRQHandler
|
|
Reserved83_IRQHandler
|
|
PIT0_IRQHandler
|
|
PIT1_IRQHandler
|
|
PIT2_IRQHandler
|
|
PIT3_IRQHandler
|
|
PDB0_IRQHandler
|
|
USB0_IRQHandler
|
|
USBDCD_IRQHandler
|
|
Reserved91_IRQHandler
|
|
Reserved92_IRQHandler
|
|
Reserved93_IRQHandler
|
|
Reserved94_IRQHandler
|
|
I2S0_IRQHandler
|
|
SDHC_IRQHandler
|
|
DAC0_IRQHandler
|
|
DAC1_IRQHandler
|
|
TSI0_IRQHandler
|
|
MCG_IRQHandler
|
|
LPTimer_IRQHandler
|
|
LCD_IRQHandler
|
|
PORTA_IRQHandler
|
|
PORTB_IRQHandler
|
|
PORTC_IRQHandler
|
|
PORTD_IRQHandler
|
|
PORTE_IRQHandler
|
|
Reserved108_IRQHandler
|
|
Reserved109_IRQHandler
|
|
Reserved110_IRQHandler
|
|
Reserved111_IRQHandler
|
|
Reserved112_IRQHandler
|
|
Reserved113_IRQHandler
|
|
Reserved114_IRQHandler
|
|
Reserved115_IRQHandler
|
|
Reserved116_IRQHandler
|
|
Reserved117_IRQHandler
|
|
Reserved118_IRQHandler
|
|
Reserved119_IRQHandler
|
|
B .
|
|
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ENDP
|
|
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|
|
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ALIGN
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|
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|
; User Initial Stack & Heap
|
|
|
|
IF :DEF:__MICROLIB
|
|
|
|
EXPORT __initial_sp
|
|
EXPORT __heap_base
|
|
EXPORT __heap_limit
|
|
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|
ELSE
|
|
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|
IMPORT __use_two_region_memory
|
|
EXPORT __user_initial_stackheap
|
|
__user_initial_stackheap
|
|
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|
LDR R0, = Heap_Mem
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|
LDR R1, =(Stack_Mem + Stack_Size)
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|
LDR R2, = (Heap_Mem + Heap_Size)
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|
LDR R3, = Stack_Mem
|
|
BX LR
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|
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ALIGN
|
|
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ENDIF
|
|
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END
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