179 lines
5.3 KiB
C
179 lines
5.3 KiB
C
/*""FILE COMMENT""*******************************************************
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* System Name : POE API for RX62Nxx
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* File Name : r_pdl_poe.h
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* Version : 1.02
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* Contents : POE API header
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* Customer :
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* Model :
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* Order :
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* CPU : RX
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* Compiler : RXC
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* OS : Nothing
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* Programmer :
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* Note :
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************************************************************************
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* Copyright, 2011. Renesas Electronics Corporation
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* and Renesas Solutions Corporation
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************************************************************************
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* History : 2011.04.08
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* : Ver 1.02
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* : CS-5 release.
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*""FILE COMMENT END""**************************************************/
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#ifndef R_PDL_POE_H
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#define R_PDL_POE_H
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#include "r_pdl_common_defs_RX62Nxx.h"
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/* Function prototypes */
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bool R_POE_Set(
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uint32_t,
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uint8_t,
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uint32_t
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);
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bool R_POE_Create(
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uint16_t,
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void *,
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void *,
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void *,
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void *,
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uint8_t
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);
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bool POE_Control(
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uint8_t,
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uint16_t,
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uint16_t
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);
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bool R_POE_GetStatus(
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uint16_t *
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);
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/* Pin selection */
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#define PDL_POE_PINS_0_TO_3 0x01u
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#define PDL_POE_PINS_4_TO_7 0x02u
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#define PDL_POE_PIN_8 0x04u
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#define PDL_POE_PIN_9 0x08u
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/* Input pin detection */
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#define PDL_POE_0_MODE_EDGE 0x00000001ul
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#define PDL_POE_0_MODE_LOW_8 0x00000002ul
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#define PDL_POE_0_MODE_LOW_16 0x00000004ul
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#define PDL_POE_0_MODE_LOW_128 0x00000008ul
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#define PDL_POE_1_MODE_EDGE 0x00000010ul
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#define PDL_POE_1_MODE_LOW_8 0x00000020ul
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#define PDL_POE_1_MODE_LOW_16 0x00000040ul
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#define PDL_POE_1_MODE_LOW_128 0x00000080ul
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#define PDL_POE_2_MODE_EDGE 0x00000100ul
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#define PDL_POE_2_MODE_LOW_8 0x00000200ul
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#define PDL_POE_2_MODE_LOW_16 0x00000400ul
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#define PDL_POE_2_MODE_LOW_128 0x00000800ul
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#define PDL_POE_3_MODE_EDGE 0x00001000ul
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#define PDL_POE_3_MODE_LOW_8 0x00002000ul
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#define PDL_POE_3_MODE_LOW_16 0x00004000ul
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#define PDL_POE_3_MODE_LOW_128 0x00008000ul
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#define PDL_POE_4_MODE_EDGE 0x00010000ul
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#define PDL_POE_4_MODE_LOW_8 0x00020000ul
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#define PDL_POE_4_MODE_LOW_16 0x00040000ul
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#define PDL_POE_4_MODE_LOW_128 0x00080000ul
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#define PDL_POE_5_MODE_EDGE 0x00100000ul
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#define PDL_POE_5_MODE_LOW_8 0x00200000ul
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#define PDL_POE_5_MODE_LOW_16 0x00400000ul
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#define PDL_POE_5_MODE_LOW_128 0x00800000ul
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#define PDL_POE_6_MODE_EDGE 0x01000000ul
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#define PDL_POE_6_MODE_LOW_8 0x02000000ul
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#define PDL_POE_6_MODE_LOW_16 0x04000000ul
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#define PDL_POE_6_MODE_LOW_128 0x08000000ul
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#define PDL_POE_7_MODE_EDGE 0x10000000ul
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#define PDL_POE_7_MODE_LOW_8 0x20000000ul
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#define PDL_POE_7_MODE_LOW_16 0x40000000ul
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#define PDL_POE_7_MODE_LOW_128 0x80000000ul
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#define PDL_POE_8_MODE_EDGE 0x01u
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#define PDL_POE_8_MODE_LOW_8 0x02u
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#define PDL_POE_8_MODE_LOW_16 0x04u
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#define PDL_POE_8_MODE_LOW_128 0x08u
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#define PDL_POE_9_MODE_EDGE 0x10u
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#define PDL_POE_9_MODE_LOW_8 0x20u
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#define PDL_POE_9_MODE_LOW_16 0x40u
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#define PDL_POE_9_MODE_LOW_128 0x80u
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/* Pin output control */
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/* High impedance request detection */
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#define PDL_POE_HI_Z_REQ_8_ENABLE 0x00000001ul
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#define PDL_POE_HI_Z_REQ_MTIOC0A 0x00000002ul
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#define PDL_POE_HI_Z_REQ_MTIOC0B 0x00000004ul
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#define PDL_POE_HI_Z_REQ_MTIOC0C 0x00000008ul
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#define PDL_POE_HI_Z_REQ_MTIOC0D 0x00000010ul
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#define PDL_POE_HI_Z_REQ_9_ENABLE 0x00000020ul
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#define PDL_POE_HI_Z_REQ_MTIOC6A 0x00000040ul
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#define PDL_POE_HI_Z_REQ_MTIOC6B 0x00000080ul
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#define PDL_POE_HI_Z_REQ_MTIOC6C 0x00000100ul
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#define PDL_POE_HI_Z_REQ_MTIOC6D 0x00000200ul
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/* Output short detection */
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#define PDL_POE_SHORT_3_4_HI_Z 0x00000400ul
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#define PDL_POE_SHORT_MTIOC4BD_B 0x00000800ul
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#define PDL_POE_SHORT_MTIOC4AC_B 0x00001000ul
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#define PDL_POE_SHORT_MTIOC3BD_B 0x00002000ul
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#define PDL_POE_SHORT_MTIOC4BD_A 0x00004000ul
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#define PDL_POE_SHORT_MTIOC4AC_A 0x00008000ul
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#define PDL_POE_SHORT_MTIOC3BD_A 0x00010000ul
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#define PDL_POE_SHORT_9_10_HI_Z 0x00020000ul
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#define PDL_POE_SHORT_MTIOC10BD 0x00040000ul
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#define PDL_POE_SHORT_MTIOC10AC 0x00080000ul
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#define PDL_POE_SHORT_MTIOC9BD 0x00100000ul
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/* High impedance request response */
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#define PDL_POE_IRQ_HI_Z_0_3_DISABLE 0x0001u
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#define PDL_POE_IRQ_HI_Z_0_3_ENABLE 0x0002u
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#define PDL_POE_IRQ_HI_Z_4_7_DISABLE 0x0004u
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#define PDL_POE_IRQ_HI_Z_4_7_ENABLE 0x0008u
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#define PDL_POE_IRQ_HI_Z_8_DISABLE 0x0010u
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#define PDL_POE_IRQ_HI_Z_8_ENABLE 0x0020u
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#define PDL_POE_IRQ_HI_Z_9_DISABLE 0x0040u
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#define PDL_POE_IRQ_HI_Z_9_ENABLE 0x0080u
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/* Output short detection response */
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#define PDL_POE_IRQ_SHORT_3_4_ENABLE 0x0100u
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#define PDL_POE_IRQ_SHORT_3_4_DISABLE 0x0200u
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#define PDL_POE_IRQ_SHORT_9_10_ENABLE 0x0400u
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#define PDL_POE_IRQ_SHORT_9_10_DISABLE 0x0800u
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/* MTU channel high impedance control */
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#define PDL_POE_MTU3_MTU4_HI_Z_ON 0x01u
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#define PDL_POE_MTU3_MTU4_HI_Z_OFF 0x02u
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#define PDL_POE_MTU0_HI_Z_ON 0x04u
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#define PDL_POE_MTU0_HI_Z_OFF 0x08u
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#define PDL_POE_MTU9_MTU10_HI_Z_ON 0x10u
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#define PDL_POE_MTU9_MTU10_HI_Z_OFF 0x20u
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#define PDL_POE_MTU6_HI_Z_ON 0x40u
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#define PDL_POE_MTU6_HI_Z_OFF 0x80u
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/* Event flag control */
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#define PDL_POE_FLAG_POE0_CLEAR 0x0001u
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#define PDL_POE_FLAG_POE1_CLEAR 0x0002u
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#define PDL_POE_FLAG_POE2_CLEAR 0x0004u
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#define PDL_POE_FLAG_POE3_CLEAR 0x0008u
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#define PDL_POE_FLAG_POE4_CLEAR 0x0010u
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#define PDL_POE_FLAG_POE5_CLEAR 0x0020u
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#define PDL_POE_FLAG_POE6_CLEAR 0x0040u
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#define PDL_POE_FLAG_POE7_CLEAR 0x0080u
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#define PDL_POE_FLAG_POE8_CLEAR 0x0100u
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#define PDL_POE_FLAG_POE9_CLEAR 0x0200u
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#define PDL_POE_FLAG_SHORT_3_4_CLEAR 0x0400u
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#define PDL_POE_FLAG_SHORT_9_10_CLEAR 0x0800u
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#endif
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/* End of file */
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