1231 lines
37 KiB
C
1231 lines
37 KiB
C
/*
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* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_uart.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* UART transfer state. */
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enum _uart_tansfer_states
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{
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kUART_TxIdle, /* TX idle. */
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kUART_TxBusy, /* TX busy. */
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kUART_RxIdle, /* RX idle. */
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kUART_RxBusy, /* RX busy. */
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kUART_RxFramingError, /* Rx framing error */
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kUART_RxParityError /* Rx parity error */
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};
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/* Typedef for interrupt handler. */
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typedef void (*uart_isr_t)(UART_Type *base, uart_handle_t *handle);
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get the UART instance from peripheral base address.
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*
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* @param base UART peripheral base address.
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* @return UART instance.
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*/
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uint32_t UART_GetInstance(UART_Type *base);
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/*!
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* @brief Get the length of received data in RX ring buffer.
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*
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* @param handle UART handle pointer.
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* @return Length of received data in RX ring buffer.
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*/
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static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle);
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/*!
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* @brief Check whether the RX ring buffer is full.
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*
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* @param handle UART handle pointer.
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* @retval true RX ring buffer is full.
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* @retval false RX ring buffer is not full.
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*/
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static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle);
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/*!
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* @brief Read RX register using non-blocking method.
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*
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* This function reads data from the TX register directly, upper layer must make
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* sure the RX register is full or TX FIFO has data before calling this function.
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*
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* @param base UART peripheral base address.
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* @param data Start addresss of the buffer to store the received data.
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* @param length Size of the buffer.
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*/
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static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length);
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/*!
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* @brief Write to TX register using non-blocking method.
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*
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* This function writes data to the TX register directly, upper layer must make
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* sure the TX register is empty or TX FIFO has empty room before calling this function.
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*
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* @note This function does not check whether all the data has been sent out to bus,
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* so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is
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* finished.
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*
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* @param base UART peripheral base address.
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* @param data Start addresss of the data to write.
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* @param length Size of the buffer to be sent.
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*/
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static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* Array of UART handle. */
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#if (defined(UART5))
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#define UART_HANDLE_ARRAY_SIZE 6
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#else /* UART5 */
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#if (defined(UART4))
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#define UART_HANDLE_ARRAY_SIZE 5
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#else /* UART4 */
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#if (defined(UART3))
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#define UART_HANDLE_ARRAY_SIZE 4
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#else /* UART3 */
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#if (defined(UART2))
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#define UART_HANDLE_ARRAY_SIZE 3
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#else /* UART2 */
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#if (defined(UART1))
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#define UART_HANDLE_ARRAY_SIZE 2
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#else /* UART1 */
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#if (defined(UART0))
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#define UART_HANDLE_ARRAY_SIZE 1
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#else /* UART0 */
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#error No UART instance.
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#endif /* UART 0 */
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#endif /* UART 1 */
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#endif /* UART 2 */
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#endif /* UART 3 */
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#endif /* UART 4 */
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#endif /* UART 5 */
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static uart_handle_t *s_uartHandle[UART_HANDLE_ARRAY_SIZE];
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/* Array of UART peripheral base address. */
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static UART_Type *const s_uartBases[] = UART_BASE_PTRS;
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/* Array of UART IRQ number. */
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static const IRQn_Type s_uartIRQ[] = UART_RX_TX_IRQS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Array of UART clock name. */
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static const clock_ip_name_t s_uartClock[] = UART_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* UART ISR for transactional APIs. */
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static uart_isr_t s_uartIsr;
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/*******************************************************************************
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* Code
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******************************************************************************/
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uint32_t UART_GetInstance(UART_Type *base)
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{
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uint32_t instance;
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uint32_t uartArrayCount = (sizeof(s_uartBases) / sizeof(s_uartBases[0]));
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < uartArrayCount; instance++)
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{
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if (s_uartBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < uartArrayCount);
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return instance;
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}
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static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle)
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{
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assert(handle);
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size_t size;
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if (handle->rxRingBufferTail > handle->rxRingBufferHead)
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{
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size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
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}
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else
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{
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size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
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}
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return size;
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}
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static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle)
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{
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assert(handle);
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bool full;
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if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
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{
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full = true;
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}
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else
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{
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full = false;
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}
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return full;
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}
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status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz)
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{
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assert(config);
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assert(config->baudRate_Bps);
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#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
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assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->txFifoWatermark);
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assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
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#endif
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uint16_t sbr = 0;
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uint8_t temp = 0;
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uint32_t baudDiff = 0;
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/* Calculate the baud rate modulo divisor, sbr*/
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sbr = srcClock_Hz / (config->baudRate_Bps * 16);
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/* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */
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if (sbr == 0)
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{
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sbr = 1;
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}
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#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
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/* Determine if a fractional divider is needed to fine tune closer to the
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* desired baud, each value of brfa is in 1/32 increments,
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* hence the multiply-by-32. */
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uint32_t tempBaud = 0;
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uint16_t brfa = (2 * srcClock_Hz / (config->baudRate_Bps)) - 32 * sbr;
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/* Calculate the baud rate based on the temporary SBR values and BRFA */
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tempBaud = (srcClock_Hz * 2 / ((sbr * 32 + brfa)));
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baudDiff =
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(tempBaud > config->baudRate_Bps) ? (tempBaud - config->baudRate_Bps) : (config->baudRate_Bps - tempBaud);
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#else
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/* Calculate the baud rate based on the temporary SBR values */
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baudDiff = (srcClock_Hz / (sbr * 16)) - config->baudRate_Bps;
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/* Select the better value between sbr and (sbr + 1) */
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if (baudDiff > (config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)))))
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{
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baudDiff = config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)));
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sbr++;
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}
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#endif
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/* next, check to see if actual baud rate is within 3% of desired baud rate
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* based on the calculate SBR value */
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if (baudDiff > ((config->baudRate_Bps / 100) * 3))
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{
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/* Unacceptable baud rate difference of more than 3%*/
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return kStatus_UART_BaudrateNotSupport;
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}
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable uart clock */
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CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Disable UART TX RX before setting. */
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base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
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/* Write the sbr value to the BDH and BDL registers*/
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base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
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base->BDL = (uint8_t)sbr;
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#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
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/* Write the brfa value to the register*/
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base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK);
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#endif
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/* Set bit count and parity mode. */
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temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK);
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if (kUART_ParityDisabled != config->parityMode)
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{
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temp |= (UART_C1_M_MASK | (uint8_t)config->parityMode);
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}
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base->C1 = temp;
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#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
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/* Set stop bit per char */
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base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)config->stopBitCount);
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#endif
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#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
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/* Set tx/rx FIFO watermark */
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base->TWFIFO = config->txFifoWatermark;
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base->RWFIFO = config->rxFifoWatermark;
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/* Enable tx/rx FIFO */
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base->PFIFO |= (UART_PFIFO_TXFE_MASK | UART_PFIFO_RXFE_MASK);
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/* Flush FIFO */
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base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK);
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#endif
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/* Enable TX/RX base on configure structure. */
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temp = base->C2;
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if (config->enableTx)
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{
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temp |= UART_C2_TE_MASK;
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}
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if (config->enableRx)
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{
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temp |= UART_C2_RE_MASK;
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}
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base->C2 = temp;
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return kStatus_Success;
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}
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void UART_Deinit(UART_Type *base)
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{
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#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
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/* Wait tx FIFO send out*/
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while (0 != base->TCFIFO)
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{
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}
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#endif
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/* Wait last char shoft out */
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while (0 == (base->S1 & UART_S1_TC_MASK))
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{
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}
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/* Disable the module. */
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base->C2 = 0;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable uart clock */
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CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void UART_GetDefaultConfig(uart_config_t *config)
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{
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assert(config);
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config->baudRate_Bps = 115200U;
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config->parityMode = kUART_ParityDisabled;
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#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
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config->stopBitCount = kUART_OneStopBit;
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#endif
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#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
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config->txFifoWatermark = 0;
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config->rxFifoWatermark = 1;
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#endif
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config->enableTx = false;
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config->enableRx = false;
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}
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status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
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{
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assert(baudRate_Bps);
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uint16_t sbr = 0;
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uint32_t baudDiff = 0;
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uint8_t oldCtrl;
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/* Calculate the baud rate modulo divisor, sbr*/
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sbr = srcClock_Hz / (baudRate_Bps * 16);
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/* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */
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if (sbr == 0)
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{
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sbr = 1;
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}
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#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
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/* Determine if a fractional divider is needed to fine tune closer to the
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* desired baud, each value of brfa is in 1/32 increments,
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* hence the multiply-by-32. */
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uint32_t tempBaud = 0;
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uint16_t brfa = (2 * srcClock_Hz / (baudRate_Bps)) - 32 * sbr;
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/* Calculate the baud rate based on the temporary SBR values and BRFA */
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tempBaud = (srcClock_Hz * 2 / ((sbr * 32 + brfa)));
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baudDiff = (tempBaud > baudRate_Bps) ? (tempBaud - baudRate_Bps) : (baudRate_Bps - tempBaud);
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#else
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/* Calculate the baud rate based on the temporary SBR values */
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baudDiff = (srcClock_Hz / (sbr * 16)) - baudRate_Bps;
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/* Select the better value between sbr and (sbr + 1) */
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if (baudDiff > (baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)))))
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{
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baudDiff = baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)));
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sbr++;
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}
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#endif
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/* next, check to see if actual baud rate is within 3% of desired baud rate
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* based on the calculate SBR value */
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if (baudDiff < ((baudRate_Bps / 100) * 3))
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{
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/* Store C2 before disable Tx and Rx */
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oldCtrl = base->C2;
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/* Disable UART TX RX before setting. */
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base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
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/* Write the sbr value to the BDH and BDL registers*/
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base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
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base->BDL = (uint8_t)sbr;
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#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
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/* Write the brfa value to the register*/
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base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK);
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#endif
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/* Restore C2. */
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base->C2 = oldCtrl;
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return kStatus_Success;
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}
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else
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{
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/* Unacceptable baud rate difference of more than 3%*/
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return kStatus_UART_BaudrateNotSupport;
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}
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}
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void UART_EnableInterrupts(UART_Type *base, uint32_t mask)
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{
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mask &= kUART_AllInterruptsEnable;
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/* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH))
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*/
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base->BDH |= mask;
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base->C2 |= (mask >> 8);
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base->C3 |= (mask >> 16);
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#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
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base->CFIFO |= (mask >> 24);
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#endif
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}
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void UART_DisableInterrupts(UART_Type *base, uint32_t mask)
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{
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mask &= kUART_AllInterruptsEnable;
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/* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH))
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*/
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base->BDH &= ~mask;
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base->C2 &= ~(mask >> 8);
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base->C3 &= ~(mask >> 16);
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#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
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base->CFIFO &= ~(mask >> 24);
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#endif
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}
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uint32_t UART_GetEnabledInterrupts(UART_Type *base)
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{
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uint32_t temp;
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temp = base->BDH | ((uint32_t)(base->C2) << 8) | ((uint32_t)(base->C3) << 16);
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#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
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temp |= ((uint32_t)(base->CFIFO) << 24);
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#endif
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return temp & kUART_AllInterruptsEnable;
|
|
}
|
|
|
|
uint32_t UART_GetStatusFlags(UART_Type *base)
|
|
{
|
|
uint32_t status_flag;
|
|
|
|
status_flag = base->S1 | ((uint32_t)(base->S2) << 8);
|
|
|
|
#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
|
|
status_flag |= ((uint32_t)(base->ED) << 16);
|
|
#endif
|
|
|
|
#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
|
|
status_flag |= ((uint32_t)(base->SFIFO) << 24);
|
|
#endif
|
|
|
|
return status_flag;
|
|
}
|
|
|
|
status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask)
|
|
{
|
|
uint8_t reg = base->S2;
|
|
status_t status;
|
|
|
|
#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
|
|
reg &= ~(UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK);
|
|
#else
|
|
reg &= ~UART_S2_RXEDGIF_MASK;
|
|
#endif
|
|
|
|
base->S2 = reg | (uint8_t)(mask >> 8);
|
|
|
|
#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
|
|
base->SFIFO = (uint8_t)(mask >> 24);
|
|
#endif
|
|
|
|
if (mask & (kUART_IdleLineFlag | kUART_NoiseErrorFlag | kUART_FramingErrorFlag | kUART_ParityErrorFlag))
|
|
{
|
|
/* Read base->D to clear the flags. */
|
|
(void)base->S1;
|
|
(void)base->D;
|
|
}
|
|
|
|
if (mask & kUART_RxOverrunFlag)
|
|
{
|
|
/* Read base->D to clear the flags and Flush all data in FIFO. */
|
|
(void)base->S1;
|
|
(void)base->D;
|
|
#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
|
|
/* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
|
|
base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
|
|
#endif
|
|
}
|
|
|
|
/* If some flags still pending. */
|
|
if (mask & UART_GetStatusFlags(base))
|
|
{
|
|
/* Some flags can only clear or set by the hardware itself, these flags are: kUART_TxDataRegEmptyFlag,
|
|
kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag,
|
|
kUART_ParityErrorInRxDataRegFlag, kUART_TxFifoEmptyFlag, kUART_RxFifoEmptyFlag. */
|
|
status = kStatus_UART_FlagCannotClearManually;
|
|
}
|
|
else
|
|
{
|
|
status = kStatus_Success;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length)
|
|
{
|
|
/* This API can only ensure that the data is written into the data buffer but can't
|
|
ensure all data in the data buffer are sent into the transmit shift buffer. */
|
|
while (length--)
|
|
{
|
|
while (!(base->S1 & UART_S1_TDRE_MASK))
|
|
{
|
|
}
|
|
base->D = *(data++);
|
|
}
|
|
}
|
|
|
|
static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length)
|
|
{
|
|
assert(data);
|
|
|
|
size_t i;
|
|
|
|
/* The Non Blocking write data API assume user have ensured there is enough space in
|
|
peripheral to write. */
|
|
for (i = 0; i < length; i++)
|
|
{
|
|
base->D = data[i];
|
|
}
|
|
}
|
|
|
|
status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length)
|
|
{
|
|
assert(data);
|
|
|
|
uint32_t statusFlag;
|
|
|
|
while (length--)
|
|
{
|
|
#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
|
|
while (!base->RCFIFO)
|
|
#else
|
|
while (!(base->S1 & UART_S1_RDRF_MASK))
|
|
#endif
|
|
{
|
|
statusFlag = UART_GetStatusFlags(base);
|
|
|
|
if (statusFlag & kUART_RxOverrunFlag)
|
|
{
|
|
return kStatus_UART_RxHardwareOverrun;
|
|
}
|
|
|
|
if (statusFlag & kUART_NoiseErrorFlag)
|
|
{
|
|
return kStatus_UART_NoiseError;
|
|
}
|
|
|
|
if (statusFlag & kUART_FramingErrorFlag)
|
|
{
|
|
return kStatus_UART_FramingError;
|
|
}
|
|
|
|
if (statusFlag & kUART_ParityErrorFlag)
|
|
{
|
|
return kStatus_UART_ParityError;
|
|
}
|
|
}
|
|
*(data++) = base->D;
|
|
}
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length)
|
|
{
|
|
assert(data);
|
|
|
|
size_t i;
|
|
|
|
/* The Non Blocking read data API assume user have ensured there is enough space in
|
|
peripheral to write. */
|
|
for (i = 0; i < length; i++)
|
|
{
|
|
data[i] = base->D;
|
|
}
|
|
}
|
|
|
|
void UART_TransferCreateHandle(UART_Type *base,
|
|
uart_handle_t *handle,
|
|
uart_transfer_callback_t callback,
|
|
void *userData)
|
|
{
|
|
assert(handle);
|
|
|
|
uint32_t instance;
|
|
|
|
/* Zero the handle. */
|
|
memset(handle, 0, sizeof(*handle));
|
|
|
|
/* Set the TX/RX state. */
|
|
handle->rxState = kUART_RxIdle;
|
|
handle->txState = kUART_TxIdle;
|
|
|
|
/* Set the callback and user data. */
|
|
handle->callback = callback;
|
|
handle->userData = userData;
|
|
|
|
#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
|
|
/* Note:
|
|
Take care of the RX FIFO, RX interrupt request only assert when received bytes
|
|
equal or more than RX water mark, there is potential issue if RX water
|
|
mark larger than 1.
|
|
For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
|
|
5 bytes are received. the last byte will be saved in FIFO but not trigger
|
|
RX interrupt because the water mark is 2.
|
|
*/
|
|
base->RWFIFO = 1U;
|
|
#endif
|
|
|
|
/* Get instance from peripheral base address. */
|
|
instance = UART_GetInstance(base);
|
|
|
|
/* Save the handle in global variables to support the double weak mechanism. */
|
|
s_uartHandle[instance] = handle;
|
|
|
|
s_uartIsr = UART_TransferHandleIRQ;
|
|
/* Enable interrupt in NVIC. */
|
|
EnableIRQ(s_uartIRQ[instance]);
|
|
}
|
|
|
|
void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
|
|
{
|
|
assert(handle);
|
|
assert(ringBuffer);
|
|
|
|
/* Setup the ringbuffer address */
|
|
handle->rxRingBuffer = ringBuffer;
|
|
handle->rxRingBufferSize = ringBufferSize;
|
|
handle->rxRingBufferHead = 0U;
|
|
handle->rxRingBufferTail = 0U;
|
|
|
|
/* Enable the interrupt to accept the data when user need the ring buffer. */
|
|
UART_EnableInterrupts(
|
|
base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | kUART_FramingErrorInterruptEnable);
|
|
/* Enable parity error interrupt when parity mode is enable*/
|
|
if (UART_C1_PE_MASK & base->C1)
|
|
{
|
|
UART_EnableInterrupts(base, kUART_ParityErrorInterruptEnable);
|
|
}
|
|
}
|
|
|
|
void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
if (handle->rxState == kUART_RxIdle)
|
|
{
|
|
UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
|
|
kUART_FramingErrorInterruptEnable);
|
|
/* Disable parity error interrupt when parity mode is enable*/
|
|
if (UART_C1_PE_MASK & base->C1)
|
|
{
|
|
UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
|
|
}
|
|
}
|
|
|
|
handle->rxRingBuffer = NULL;
|
|
handle->rxRingBufferSize = 0U;
|
|
handle->rxRingBufferHead = 0U;
|
|
handle->rxRingBufferTail = 0U;
|
|
}
|
|
|
|
status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer)
|
|
{
|
|
assert(handle);
|
|
assert(xfer);
|
|
assert(xfer->dataSize);
|
|
assert(xfer->data);
|
|
|
|
status_t status;
|
|
|
|
/* Return error if current TX busy. */
|
|
if (kUART_TxBusy == handle->txState)
|
|
{
|
|
status = kStatus_UART_TxBusy;
|
|
}
|
|
else
|
|
{
|
|
handle->txData = xfer->data;
|
|
handle->txDataSize = xfer->dataSize;
|
|
handle->txDataSizeAll = xfer->dataSize;
|
|
handle->txState = kUART_TxBusy;
|
|
|
|
/* Enable transmiter interrupt. */
|
|
UART_EnableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable);
|
|
|
|
status = kStatus_Success;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
UART_DisableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable | kUART_TransmissionCompleteInterruptEnable);
|
|
|
|
handle->txDataSize = 0;
|
|
handle->txState = kUART_TxIdle;
|
|
}
|
|
|
|
status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
|
|
{
|
|
assert(handle);
|
|
assert(count);
|
|
|
|
if (kUART_TxIdle == handle->txState)
|
|
{
|
|
return kStatus_NoTransferInProgress;
|
|
}
|
|
|
|
*count = handle->txDataSizeAll - handle->txDataSize;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
status_t UART_TransferReceiveNonBlocking(UART_Type *base,
|
|
uart_handle_t *handle,
|
|
uart_transfer_t *xfer,
|
|
size_t *receivedBytes)
|
|
{
|
|
assert(handle);
|
|
assert(xfer);
|
|
assert(xfer->data);
|
|
assert(xfer->dataSize);
|
|
|
|
uint32_t i;
|
|
status_t status;
|
|
/* How many bytes to copy from ring buffer to user memory. */
|
|
size_t bytesToCopy = 0U;
|
|
/* How many bytes to receive. */
|
|
size_t bytesToReceive;
|
|
/* How many bytes currently have received. */
|
|
size_t bytesCurrentReceived;
|
|
|
|
/* How to get data:
|
|
1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
|
|
to uart handle, enable interrupt to store received data to xfer->data. When
|
|
all data received, trigger callback.
|
|
2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
|
|
If there are enough data in ring buffer, copy them to xfer->data and return.
|
|
If there are not enough data in ring buffer, copy all of them to xfer->data,
|
|
save the xfer->data remained empty space to uart handle, receive data
|
|
to this empty space and trigger callback when finished. */
|
|
|
|
if (kUART_RxBusy == handle->rxState)
|
|
{
|
|
status = kStatus_UART_RxBusy;
|
|
}
|
|
else
|
|
{
|
|
bytesToReceive = xfer->dataSize;
|
|
bytesCurrentReceived = 0U;
|
|
|
|
/* If RX ring buffer is used. */
|
|
if (handle->rxRingBuffer)
|
|
{
|
|
/* Disable UART RX IRQ, protect ring buffer. */
|
|
UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable);
|
|
|
|
/* How many bytes in RX ring buffer currently. */
|
|
bytesToCopy = UART_TransferGetRxRingBufferLength(handle);
|
|
|
|
if (bytesToCopy)
|
|
{
|
|
bytesToCopy = MIN(bytesToReceive, bytesToCopy);
|
|
|
|
bytesToReceive -= bytesToCopy;
|
|
|
|
/* Copy data from ring buffer to user memory. */
|
|
for (i = 0U; i < bytesToCopy; i++)
|
|
{
|
|
xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
|
|
|
|
/* Wrap to 0. Not use modulo (%) because it might be large and slow. */
|
|
if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
|
|
{
|
|
handle->rxRingBufferTail = 0U;
|
|
}
|
|
else
|
|
{
|
|
handle->rxRingBufferTail++;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* If ring buffer does not have enough data, still need to read more data. */
|
|
if (bytesToReceive)
|
|
{
|
|
/* No data in ring buffer, save the request to UART handle. */
|
|
handle->rxData = xfer->data + bytesCurrentReceived;
|
|
handle->rxDataSize = bytesToReceive;
|
|
handle->rxDataSizeAll = bytesToReceive;
|
|
handle->rxState = kUART_RxBusy;
|
|
}
|
|
|
|
/* Enable UART RX IRQ if previously enabled. */
|
|
UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable);
|
|
|
|
/* Call user callback since all data are received. */
|
|
if (0 == bytesToReceive)
|
|
{
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData);
|
|
}
|
|
}
|
|
}
|
|
/* Ring buffer not used. */
|
|
else
|
|
{
|
|
handle->rxData = xfer->data + bytesCurrentReceived;
|
|
handle->rxDataSize = bytesToReceive;
|
|
handle->rxDataSizeAll = bytesToReceive;
|
|
handle->rxState = kUART_RxBusy;
|
|
|
|
/* Enable RX/Rx overrun/framing error interrupt. */
|
|
UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
|
|
kUART_FramingErrorInterruptEnable);
|
|
/* Enable parity error interrupt when parity mode is enable*/
|
|
if (UART_C1_PE_MASK & base->C1)
|
|
{
|
|
UART_EnableInterrupts(base, kUART_ParityErrorInterruptEnable);
|
|
}
|
|
}
|
|
|
|
/* Return the how many bytes have read. */
|
|
if (receivedBytes)
|
|
{
|
|
*receivedBytes = bytesCurrentReceived;
|
|
}
|
|
|
|
status = kStatus_Success;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
/* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
|
|
if (!handle->rxRingBuffer)
|
|
{
|
|
/* Disable RX interrupt. */
|
|
UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
|
|
kUART_FramingErrorInterruptEnable);
|
|
/* Disable parity error interrupt when parity mode is enable*/
|
|
if (UART_C1_PE_MASK & base->C1)
|
|
{
|
|
UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
|
|
}
|
|
}
|
|
|
|
handle->rxDataSize = 0U;
|
|
handle->rxState = kUART_RxIdle;
|
|
}
|
|
|
|
status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
|
|
{
|
|
assert(handle);
|
|
assert(count);
|
|
|
|
if (kUART_RxIdle == handle->rxState)
|
|
{
|
|
return kStatus_NoTransferInProgress;
|
|
}
|
|
|
|
if (!count)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
*count = handle->rxDataSizeAll - handle->rxDataSize;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
uint8_t count;
|
|
uint8_t tempCount;
|
|
|
|
/* If RX framing error */
|
|
if (UART_S1_FE_MASK & base->S1)
|
|
{
|
|
/* Read base->D to clear framing error flag, otherwise the RX does not work. */
|
|
while (base->S1 & UART_S1_RDRF_MASK)
|
|
{
|
|
(void)base->D;
|
|
}
|
|
#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
|
|
/* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
|
|
base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
|
|
#endif
|
|
|
|
handle->rxState = kUART_RxFramingError;
|
|
handle->rxDataSize = 0U;
|
|
/* Trigger callback. */
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_UART_FramingError, handle->userData);
|
|
}
|
|
}
|
|
|
|
/* If RX parity error */
|
|
if (UART_S1_PF_MASK & base->S1)
|
|
{
|
|
/* Read base->D to clear parity error flag, otherwise the RX does not work. */
|
|
while (base->S1 & UART_S1_RDRF_MASK)
|
|
{
|
|
(void)base->D;
|
|
}
|
|
#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
|
|
/* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
|
|
base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
|
|
#endif
|
|
|
|
handle->rxState = kUART_RxParityError;
|
|
handle->rxDataSize = 0U;
|
|
/* Trigger callback. */
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_UART_ParityError, handle->userData);
|
|
}
|
|
}
|
|
|
|
/* If RX overrun. */
|
|
if (UART_S1_OR_MASK & base->S1)
|
|
{
|
|
/* Read base->D to clear overrun flag, otherwise the RX does not work. */
|
|
while (base->S1 & UART_S1_RDRF_MASK)
|
|
{
|
|
(void)base->D;
|
|
}
|
|
#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
|
|
/* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
|
|
base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
|
|
#endif
|
|
/* Trigger callback. */
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData);
|
|
}
|
|
}
|
|
|
|
/* Receive data register full */
|
|
if ((UART_S1_RDRF_MASK & base->S1) && (UART_C2_RIE_MASK & base->C2))
|
|
{
|
|
/* Get the size that can be stored into buffer for this interrupt. */
|
|
#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
|
|
count = base->RCFIFO;
|
|
#else
|
|
count = 1;
|
|
#endif
|
|
|
|
/* If handle->rxDataSize is not 0, first save data to handle->rxData. */
|
|
while ((count) && (handle->rxDataSize))
|
|
{
|
|
#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
|
|
tempCount = MIN(handle->rxDataSize, count);
|
|
#else
|
|
tempCount = 1;
|
|
#endif
|
|
|
|
/* Using non block API to read the data from the registers. */
|
|
UART_ReadNonBlocking(base, handle->rxData, tempCount);
|
|
handle->rxData += tempCount;
|
|
handle->rxDataSize -= tempCount;
|
|
count -= tempCount;
|
|
|
|
/* If all the data required for upper layer is ready, trigger callback. */
|
|
if (!handle->rxDataSize)
|
|
{
|
|
handle->rxState = kUART_RxIdle;
|
|
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* If use RX ring buffer, receive data to ring buffer. */
|
|
if (handle->rxRingBuffer)
|
|
{
|
|
while (count--)
|
|
{
|
|
/* If RX ring buffer is full, trigger callback to notify over run. */
|
|
if (UART_TransferIsRxRingBufferFull(handle))
|
|
{
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData);
|
|
}
|
|
}
|
|
|
|
/* If ring buffer is still full after callback function, the oldest data is overrided. */
|
|
if (UART_TransferIsRxRingBufferFull(handle))
|
|
{
|
|
/* Increase handle->rxRingBufferTail to make room for new data. */
|
|
if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
|
|
{
|
|
handle->rxRingBufferTail = 0U;
|
|
}
|
|
else
|
|
{
|
|
handle->rxRingBufferTail++;
|
|
}
|
|
}
|
|
|
|
/* Read data. */
|
|
handle->rxRingBuffer[handle->rxRingBufferHead] = base->D;
|
|
|
|
/* Increase handle->rxRingBufferHead. */
|
|
if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
|
|
{
|
|
handle->rxRingBufferHead = 0U;
|
|
}
|
|
else
|
|
{
|
|
handle->rxRingBufferHead++;
|
|
}
|
|
}
|
|
}
|
|
|
|
else if (!handle->rxDataSize)
|
|
{
|
|
/* Disable RX interrupt/overrun interrupt/fram error interrupt */
|
|
UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
|
|
kUART_FramingErrorInterruptEnable);
|
|
|
|
/* Disable parity error interrupt when parity mode is enable*/
|
|
if (UART_C1_PE_MASK & base->C1)
|
|
{
|
|
UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
}
|
|
}
|
|
|
|
/* If framing error or parity error happened, stop the RX interrupt when ues no ring buffer */
|
|
if (((handle->rxState == kUART_RxFramingError) || (handle->rxState == kUART_RxParityError)) &&
|
|
(!handle->rxRingBuffer))
|
|
{
|
|
UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
|
|
kUART_FramingErrorInterruptEnable);
|
|
|
|
/* Disable parity error interrupt when parity mode is enable*/
|
|
if (UART_C1_PE_MASK & base->C1)
|
|
{
|
|
UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
|
|
}
|
|
}
|
|
|
|
/* Send data register empty and the interrupt is enabled. */
|
|
if ((base->S1 & UART_S1_TDRE_MASK) && (base->C2 & UART_C2_TIE_MASK))
|
|
{
|
|
/* Get the bytes that available at this moment. */
|
|
#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
|
|
count = FSL_FEATURE_UART_FIFO_SIZEn(base) - base->TCFIFO;
|
|
#else
|
|
count = 1;
|
|
#endif
|
|
|
|
while ((count) && (handle->txDataSize))
|
|
{
|
|
#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
|
|
tempCount = MIN(handle->txDataSize, count);
|
|
#else
|
|
tempCount = 1;
|
|
#endif
|
|
|
|
/* Using non block API to write the data to the registers. */
|
|
UART_WriteNonBlocking(base, handle->txData, tempCount);
|
|
handle->txData += tempCount;
|
|
handle->txDataSize -= tempCount;
|
|
count -= tempCount;
|
|
|
|
/* If all the data are written to data register, TX finished. */
|
|
if (!handle->txDataSize)
|
|
{
|
|
handle->txState = kUART_TxIdle;
|
|
|
|
/* Disable TX register empty interrupt. */
|
|
base->C2 = (base->C2 & ~UART_C2_TIE_MASK);
|
|
|
|
/* Trigger callback. */
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle)
|
|
{
|
|
/* To be implemented by User. */
|
|
}
|
|
|
|
#if defined(UART0)
|
|
#if ((!(defined(FSL_FEATURE_SOC_LPSCI_COUNT))) || \
|
|
((defined(FSL_FEATURE_SOC_LPSCI_COUNT)) && (FSL_FEATURE_SOC_LPSCI_COUNT == 0)))
|
|
void UART0_DriverIRQHandler(void)
|
|
{
|
|
s_uartIsr(UART0, s_uartHandle[0]);
|
|
}
|
|
|
|
void UART0_RX_TX_DriverIRQHandler(void)
|
|
{
|
|
UART0_DriverIRQHandler();
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(UART1)
|
|
void UART1_DriverIRQHandler(void)
|
|
{
|
|
s_uartIsr(UART1, s_uartHandle[1]);
|
|
}
|
|
|
|
void UART1_RX_TX_DriverIRQHandler(void)
|
|
{
|
|
UART1_DriverIRQHandler();
|
|
}
|
|
#endif
|
|
|
|
#if defined(UART2)
|
|
void UART2_DriverIRQHandler(void)
|
|
{
|
|
s_uartIsr(UART2, s_uartHandle[2]);
|
|
}
|
|
|
|
void UART2_RX_TX_DriverIRQHandler(void)
|
|
{
|
|
UART2_DriverIRQHandler();
|
|
}
|
|
#endif
|
|
|
|
#if defined(UART3)
|
|
void UART3_DriverIRQHandler(void)
|
|
{
|
|
s_uartIsr(UART3, s_uartHandle[3]);
|
|
}
|
|
|
|
void UART3_RX_TX_DriverIRQHandler(void)
|
|
{
|
|
UART3_DriverIRQHandler();
|
|
}
|
|
#endif
|
|
|
|
#if defined(UART4)
|
|
void UART4_DriverIRQHandler(void)
|
|
{
|
|
s_uartIsr(UART4, s_uartHandle[4]);
|
|
}
|
|
|
|
void UART4_RX_TX_DriverIRQHandler(void)
|
|
{
|
|
UART4_DriverIRQHandler();
|
|
}
|
|
#endif
|
|
|
|
#if defined(UART5)
|
|
void UART5_DriverIRQHandler(void)
|
|
{
|
|
s_uartIsr(UART5, s_uartHandle[5]);
|
|
}
|
|
|
|
void UART5_RX_TX_DriverIRQHandler(void)
|
|
{
|
|
UART5_DriverIRQHandler();
|
|
}
|
|
#endif
|