1758 lines
51 KiB
C
1758 lines
51 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_i2c.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief i2c transfer state. */
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enum _i2c_transfer_states
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{
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kIdleState = 0x0U, /*!< I2C bus idle. */
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kCheckAddressState = 0x1U, /*!< 7-bit address check state. */
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kSendCommandState = 0x2U, /*!< Send command byte phase. */
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kSendDataState = 0x3U, /*!< Send data transfer phase. */
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kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */
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kReceiveDataState = 0x5U, /*!< Receive data transfer phase. */
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};
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/*! @brief Common sets of flags used by the driver. */
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enum _i2c_flag_constants
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{
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/*! All flags which are cleared by the driver upon starting a transfer. */
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#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
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kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StartDetectFlag | kI2C_StopDetectFlag,
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kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StartStopDetectInterruptEnable,
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#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
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kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StopDetectFlag,
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kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StopDetectInterruptEnable,
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#else
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kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag,
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kIrqFlags = kI2C_GlobalInterruptEnable,
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#endif
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};
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/*! @brief Typedef for interrupt handler. */
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typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle);
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get instance number for I2C module.
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*
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* @param base I2C peripheral base address.
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*/
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uint32_t I2C_GetInstance(I2C_Type *base);
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/*!
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* @brief Set SCL/SDA hold time, this API receives SCL stop hold time, calculate the
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* closest SCL divider and MULT value for the SDA hold time, SCL start and SCL stop
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* hold time. To reduce the ROM size, SDA/SCL hold value mapping table is not provided,
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* assume SCL divider = SCL stop hold value *2 to get the closest SCL divider value and MULT
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* value, then the related SDA hold time, SCL start and SCL stop hold time is used.
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*
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* @param base I2C peripheral base address.
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* @param sourceClock_Hz I2C functional clock frequency in Hertz.
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* @param sclStopHoldTime_ns SCL stop hold time in ns.
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*/
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static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz);
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/*!
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* @brief Set up master transfer, send slave address and decide the initial
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* transfer state.
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*
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* @param base I2C peripheral base address.
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* @param handle pointer to i2c_master_handle_t structure which stores the transfer state.
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* @param xfer pointer to i2c_master_transfer_t structure.
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*/
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static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
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/*!
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* @brief Check and clear status operation.
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*
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* @param base I2C peripheral base address.
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* @param status current i2c hardware status.
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* @retval kStatus_Success No error found.
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* @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
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* @retval kStatus_I2C_Nak Received Nak error.
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*/
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static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status);
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/*!
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* @brief Master run transfer state machine to perform a byte of transfer.
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*
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* @param base I2C peripheral base address.
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* @param handle pointer to i2c_master_handle_t structure which stores the transfer state
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* @param isDone input param to get whether the thing is done, true is done
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* @retval kStatus_Success No error found.
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* @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
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* @retval kStatus_I2C_Nak Received Nak error.
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* @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
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*/
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static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone);
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/*!
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* @brief I2C common interrupt handler.
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*
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* @param base I2C peripheral base address.
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* @param handle pointer to i2c_master_handle_t structure which stores the transfer state
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*/
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static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to i2c handles for each instance. */
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static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT] = {NULL};
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/*! @brief SCL clock divider used to calculate baudrate. */
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static const uint16_t s_i2cDividerTable[] = {
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20, 22, 24, 26, 28, 30, 34, 40, 28, 32, 36, 40, 44, 48, 56, 68,
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48, 56, 64, 72, 80, 88, 104, 128, 80, 96, 112, 128, 144, 160, 192, 240,
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160, 192, 224, 256, 288, 320, 384, 480, 320, 384, 448, 512, 576, 640, 768, 960,
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640, 768, 896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840};
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/*! @brief Pointers to i2c bases for each instance. */
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static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS;
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/*! @brief Pointers to i2c IRQ number for each instance. */
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static const IRQn_Type s_i2cIrqs[] = I2C_IRQS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to i2c clocks for each instance. */
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static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*! @brief Pointer to master IRQ handler for each instance. */
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static i2c_isr_t s_i2cMasterIsr;
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/*! @brief Pointer to slave IRQ handler for each instance. */
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static i2c_isr_t s_i2cSlaveIsr;
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/*******************************************************************************
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* Codes
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******************************************************************************/
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uint32_t I2C_GetInstance(I2C_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_i2cBases); instance++)
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{
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if (s_i2cBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_i2cBases));
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return instance;
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}
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static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz)
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{
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uint32_t multiplier;
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uint32_t computedSclHoldTime;
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uint32_t absError;
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uint32_t bestError = UINT32_MAX;
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uint32_t bestMult = 0u;
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uint32_t bestIcr = 0u;
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uint8_t mult;
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uint8_t i;
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/* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register,
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* and ranges from 0-2. It selects the multiplier factor for the divider. */
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/* SDA hold time = bus period (s) * mul * SDA hold value. */
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/* SCL start hold time = bus period (s) * mul * SCL start hold value. */
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/* SCL stop hold time = bus period (s) * mul * SCL stop hold value. */
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for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult)
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{
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multiplier = 1u << mult;
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/* Scan table to find best match. */
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for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(s_i2cDividerTable[0]); ++i)
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{
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/* Assume SCL hold(stop) value = s_i2cDividerTable[i]/2. */
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computedSclHoldTime = ((multiplier * s_i2cDividerTable[i]) * 500000000U) / sourceClock_Hz;
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absError = sclStopHoldTime_ns > computedSclHoldTime ? (sclStopHoldTime_ns - computedSclHoldTime) :
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(computedSclHoldTime - sclStopHoldTime_ns);
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if (absError < bestError)
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{
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bestMult = mult;
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bestIcr = i;
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bestError = absError;
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/* If the error is 0, then we can stop searching because we won't find a better match. */
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if (absError == 0)
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{
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break;
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}
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}
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}
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}
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/* Set frequency register based on best settings. */
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base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr);
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}
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static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
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{
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status_t result = kStatus_Success;
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i2c_direction_t direction = xfer->direction;
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/* Initialize the handle transfer information. */
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handle->transfer = *xfer;
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/* Save total transfer size. */
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handle->transferSize = xfer->dataSize;
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/* Initial transfer state. */
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if (handle->transfer.subaddressSize > 0)
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{
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if (xfer->direction == kI2C_Read)
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{
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direction = kI2C_Write;
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}
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}
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handle->state = kCheckAddressState;
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/* Clear all status before transfer. */
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I2C_MasterClearStatusFlags(base, kClearFlags);
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/* If repeated start is requested, send repeated start. */
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if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag)
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{
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result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction);
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}
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else /* For normal transfer, send start. */
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{
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result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction);
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}
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return result;
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}
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static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status)
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{
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status_t result = kStatus_Success;
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/* Check arbitration lost. */
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if (status & kI2C_ArbitrationLostFlag)
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{
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/* Clear arbitration lost flag. */
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base->S = kI2C_ArbitrationLostFlag;
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result = kStatus_I2C_ArbitrationLost;
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}
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/* Check NAK */
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else if (status & kI2C_ReceiveNakFlag)
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{
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result = kStatus_I2C_Nak;
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}
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else
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{
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}
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return result;
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}
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static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone)
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{
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status_t result = kStatus_Success;
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uint32_t statusFlags = base->S;
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*isDone = false;
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volatile uint8_t dummy = 0;
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bool ignoreNak = ((handle->state == kSendDataState) && (handle->transfer.dataSize == 0U)) ||
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((handle->state == kReceiveDataState) && (handle->transfer.dataSize == 1U));
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/* Add this to avoid build warning. */
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dummy++;
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/* Check & clear error flags. */
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result = I2C_CheckAndClearError(base, statusFlags);
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/* Ignore Nak when it's appeared for last byte. */
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if ((result == kStatus_I2C_Nak) && ignoreNak)
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{
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result = kStatus_Success;
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}
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/* Handle Check address state to check the slave address is Acked in slave
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probe application. */
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if (handle->state == kCheckAddressState)
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{
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if (statusFlags & kI2C_ReceiveNakFlag)
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{
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result = kStatus_I2C_Addr_Nak;
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}
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else
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{
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if (handle->transfer.subaddressSize > 0)
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{
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handle->state = kSendCommandState;
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}
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else
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{
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if (handle->transfer.direction == kI2C_Write)
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{
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/* Next state, send data. */
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handle->state = kSendDataState;
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}
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else
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{
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/* Next state, receive data begin. */
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handle->state = kReceiveDataBeginState;
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}
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}
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}
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}
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if (result)
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{
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return result;
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}
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/* Run state machine. */
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switch (handle->state)
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{
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/* Send I2C command. */
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case kSendCommandState:
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if (handle->transfer.subaddressSize)
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{
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handle->transfer.subaddressSize--;
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base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize));
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}
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else
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{
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if (handle->transfer.direction == kI2C_Write)
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{
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/* Next state, send data. */
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handle->state = kSendDataState;
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/* Send first byte of data. */
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if (handle->transfer.dataSize > 0)
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{
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base->D = *handle->transfer.data;
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handle->transfer.data++;
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handle->transfer.dataSize--;
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}
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}
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else
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{
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/* Send repeated start and slave address. */
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result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read);
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/* Next state, receive data begin. */
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handle->state = kReceiveDataBeginState;
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}
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}
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break;
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/* Send I2C data. */
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case kSendDataState:
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/* Send one byte of data. */
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if (handle->transfer.dataSize > 0)
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{
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base->D = *handle->transfer.data;
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handle->transfer.data++;
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handle->transfer.dataSize--;
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}
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else
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{
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*isDone = true;
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}
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break;
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/* Start I2C data receive. */
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case kReceiveDataBeginState:
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base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
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/* Send nak at the last receive byte. */
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if (handle->transfer.dataSize == 1)
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{
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base->C1 |= I2C_C1_TXAK_MASK;
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}
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/* Read dummy to release the bus. */
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dummy = base->D;
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/* Next state, receive data. */
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handle->state = kReceiveDataState;
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break;
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/* Receive I2C data. */
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case kReceiveDataState:
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/* Receive one byte of data. */
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if (handle->transfer.dataSize--)
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{
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if (handle->transfer.dataSize == 0)
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{
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*isDone = true;
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/* Send stop if kI2C_TransferNoStop is not asserted. */
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if (!(handle->transfer.flags & kI2C_TransferNoStopFlag))
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{
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result = I2C_MasterStop(base);
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}
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else
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{
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base->C1 |= I2C_C1_TX_MASK;
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}
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}
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/* Send NAK at the last receive byte. */
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if (handle->transfer.dataSize == 1)
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{
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base->C1 |= I2C_C1_TXAK_MASK;
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}
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/* Read the data byte into the transfer buffer. */
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*handle->transfer.data = base->D;
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handle->transfer.data++;
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}
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break;
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default:
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break;
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}
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return result;
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}
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static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle)
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{
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/* Check if master interrupt. */
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if ((base->S & kI2C_ArbitrationLostFlag) || (base->C1 & I2C_C1_MST_MASK))
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{
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s_i2cMasterIsr(base, handle);
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}
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else
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{
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s_i2cSlaveIsr(base, handle);
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}
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__DSB();
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}
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void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
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{
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assert(masterConfig && srcClock_Hz);
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/* Temporary register for filter read. */
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uint8_t fltReg;
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#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
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uint8_t s2Reg;
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#endif
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable I2C clock. */
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CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Reset the module. */
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base->A1 = 0;
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base->F = 0;
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base->C1 = 0;
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base->S = 0xFFU;
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base->C2 = 0;
|
|
#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
|
|
base->FLT = 0x50U;
|
|
#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
|
|
base->FLT = 0x40U;
|
|
#endif
|
|
base->RA = 0;
|
|
|
|
/* Disable I2C prior to configuring it. */
|
|
base->C1 &= ~(I2C_C1_IICEN_MASK);
|
|
|
|
/* Clear all flags. */
|
|
I2C_MasterClearStatusFlags(base, kClearFlags);
|
|
|
|
/* Configure baud rate. */
|
|
I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz);
|
|
|
|
/* Read out the FLT register. */
|
|
fltReg = base->FLT;
|
|
|
|
#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
|
|
/* Configure the stop / hold enable. */
|
|
fltReg &= ~(I2C_FLT_SHEN_MASK);
|
|
fltReg |= I2C_FLT_SHEN(masterConfig->enableStopHold);
|
|
#endif
|
|
|
|
/* Configure the glitch filter value. */
|
|
fltReg &= ~(I2C_FLT_FLT_MASK);
|
|
fltReg |= I2C_FLT_FLT(masterConfig->glitchFilterWidth);
|
|
|
|
/* Write the register value back to the filter register. */
|
|
base->FLT = fltReg;
|
|
|
|
/* Enable/Disable double buffering. */
|
|
#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
|
|
s2Reg = base->S2 & (~I2C_S2_DFEN_MASK);
|
|
base->S2 = s2Reg | I2C_S2_DFEN(masterConfig->enableDoubleBuffering);
|
|
#endif
|
|
|
|
/* Enable the I2C peripheral based on the configuration. */
|
|
base->C1 = I2C_C1_IICEN(masterConfig->enableMaster);
|
|
}
|
|
|
|
void I2C_MasterDeinit(I2C_Type *base)
|
|
{
|
|
/* Disable I2C module. */
|
|
I2C_Enable(base, false);
|
|
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
/* Disable I2C clock. */
|
|
CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
}
|
|
|
|
void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)
|
|
{
|
|
assert(masterConfig);
|
|
|
|
/* Default baud rate at 100kbps. */
|
|
masterConfig->baudRate_Bps = 100000U;
|
|
|
|
/* Default stop hold enable is disabled. */
|
|
#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
|
|
masterConfig->enableStopHold = false;
|
|
#endif
|
|
|
|
/* Default glitch filter value is no filter. */
|
|
masterConfig->glitchFilterWidth = 0U;
|
|
|
|
/* Default enable double buffering. */
|
|
#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
|
|
masterConfig->enableDoubleBuffering = true;
|
|
#endif
|
|
|
|
/* Enable the I2C peripheral. */
|
|
masterConfig->enableMaster = true;
|
|
}
|
|
|
|
void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask)
|
|
{
|
|
#ifdef I2C_HAS_STOP_DETECT
|
|
uint8_t fltReg;
|
|
#endif
|
|
|
|
if (mask & kI2C_GlobalInterruptEnable)
|
|
{
|
|
base->C1 |= I2C_C1_IICIE_MASK;
|
|
}
|
|
|
|
#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
|
|
if (mask & kI2C_StopDetectInterruptEnable)
|
|
{
|
|
fltReg = base->FLT;
|
|
|
|
/* Keep STOPF flag. */
|
|
fltReg &= ~I2C_FLT_STOPF_MASK;
|
|
|
|
/* Stop detect enable. */
|
|
fltReg |= I2C_FLT_STOPIE_MASK;
|
|
base->FLT = fltReg;
|
|
}
|
|
#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
|
|
|
|
#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
|
|
if (mask & kI2C_StartStopDetectInterruptEnable)
|
|
{
|
|
fltReg = base->FLT;
|
|
|
|
/* Keep STARTF and STOPF flags. */
|
|
fltReg &= ~(I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK);
|
|
|
|
/* Start and stop detect enable. */
|
|
fltReg |= I2C_FLT_SSIE_MASK;
|
|
base->FLT = fltReg;
|
|
}
|
|
#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
|
|
}
|
|
|
|
void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask)
|
|
{
|
|
if (mask & kI2C_GlobalInterruptEnable)
|
|
{
|
|
base->C1 &= ~I2C_C1_IICIE_MASK;
|
|
}
|
|
|
|
#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
|
|
if (mask & kI2C_StopDetectInterruptEnable)
|
|
{
|
|
base->FLT &= ~(I2C_FLT_STOPIE_MASK | I2C_FLT_STOPF_MASK);
|
|
}
|
|
#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
|
|
|
|
#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
|
|
if (mask & kI2C_StartStopDetectInterruptEnable)
|
|
{
|
|
base->FLT &= ~(I2C_FLT_SSIE_MASK | I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK);
|
|
}
|
|
#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
|
|
}
|
|
|
|
void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
|
|
{
|
|
uint32_t multiplier;
|
|
uint32_t computedRate;
|
|
uint32_t absError;
|
|
uint32_t bestError = UINT32_MAX;
|
|
uint32_t bestMult = 0u;
|
|
uint32_t bestIcr = 0u;
|
|
uint8_t mult;
|
|
uint8_t i;
|
|
|
|
/* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register,
|
|
* and ranges from 0-2. It selects the multiplier factor for the divider. */
|
|
for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult)
|
|
{
|
|
multiplier = 1u << mult;
|
|
|
|
/* Scan table to find best match. */
|
|
for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(uint16_t); ++i)
|
|
{
|
|
computedRate = srcClock_Hz / (multiplier * s_i2cDividerTable[i]);
|
|
absError = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps);
|
|
|
|
if (absError < bestError)
|
|
{
|
|
bestMult = mult;
|
|
bestIcr = i;
|
|
bestError = absError;
|
|
|
|
/* If the error is 0, then we can stop searching because we won't find a better match. */
|
|
if (absError == 0)
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set frequency register based on best settings. */
|
|
base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr);
|
|
}
|
|
|
|
status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
|
|
{
|
|
status_t result = kStatus_Success;
|
|
uint32_t statusFlags = I2C_MasterGetStatusFlags(base);
|
|
|
|
/* Return an error if the bus is already in use. */
|
|
if (statusFlags & kI2C_BusBusyFlag)
|
|
{
|
|
result = kStatus_I2C_Busy;
|
|
}
|
|
else
|
|
{
|
|
/* Send the START signal. */
|
|
base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK;
|
|
|
|
#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING
|
|
while (!(base->S2 & I2C_S2_EMPTY_MASK))
|
|
{
|
|
}
|
|
#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */
|
|
|
|
base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U));
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
|
|
{
|
|
status_t result = kStatus_Success;
|
|
uint8_t savedMult;
|
|
uint32_t statusFlags = I2C_MasterGetStatusFlags(base);
|
|
uint8_t timeDelay = 6;
|
|
|
|
/* Return an error if the bus is already in use, but not by us. */
|
|
if ((statusFlags & kI2C_BusBusyFlag) && ((base->C1 & I2C_C1_MST_MASK) == 0))
|
|
{
|
|
result = kStatus_I2C_Busy;
|
|
}
|
|
else
|
|
{
|
|
savedMult = base->F;
|
|
base->F = savedMult & (~I2C_F_MULT_MASK);
|
|
|
|
/* We are already in a transfer, so send a repeated start. */
|
|
base->C1 |= I2C_C1_RSTA_MASK | I2C_C1_TX_MASK;
|
|
|
|
/* Restore the multiplier factor. */
|
|
base->F = savedMult;
|
|
|
|
/* Add some delay to wait the Re-Start signal. */
|
|
while (timeDelay--)
|
|
{
|
|
__NOP();
|
|
}
|
|
|
|
#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING
|
|
while (!(base->S2 & I2C_S2_EMPTY_MASK))
|
|
{
|
|
}
|
|
#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */
|
|
|
|
base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U));
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
status_t I2C_MasterStop(I2C_Type *base)
|
|
{
|
|
status_t result = kStatus_Success;
|
|
uint16_t timeout = UINT16_MAX;
|
|
|
|
/* Issue the STOP command on the bus. */
|
|
base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
|
|
|
|
/* Wait until data transfer complete. */
|
|
while ((base->S & kI2C_BusBusyFlag) && (--timeout))
|
|
{
|
|
}
|
|
|
|
if (timeout == 0)
|
|
{
|
|
result = kStatus_I2C_Timeout;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
uint32_t I2C_MasterGetStatusFlags(I2C_Type *base)
|
|
{
|
|
uint32_t statusFlags = base->S;
|
|
|
|
#ifdef I2C_HAS_STOP_DETECT
|
|
/* Look up the STOPF bit from the filter register. */
|
|
if (base->FLT & I2C_FLT_STOPF_MASK)
|
|
{
|
|
statusFlags |= kI2C_StopDetectFlag;
|
|
}
|
|
#endif
|
|
|
|
#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
|
|
/* Look up the STARTF bit from the filter register. */
|
|
if (base->FLT & I2C_FLT_STARTF_MASK)
|
|
{
|
|
statusFlags |= kI2C_StartDetectFlag;
|
|
}
|
|
#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
|
|
|
|
return statusFlags;
|
|
}
|
|
|
|
status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags)
|
|
{
|
|
status_t result = kStatus_Success;
|
|
uint8_t statusFlags = 0;
|
|
|
|
/* Wait until the data register is ready for transmit. */
|
|
while (!(base->S & kI2C_TransferCompleteFlag))
|
|
{
|
|
}
|
|
|
|
/* Clear the IICIF flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
/* Setup the I2C peripheral to transmit data. */
|
|
base->C1 |= I2C_C1_TX_MASK;
|
|
|
|
while (txSize--)
|
|
{
|
|
/* Send a byte of data. */
|
|
base->D = *txBuff++;
|
|
|
|
/* Wait until data transfer complete. */
|
|
while (!(base->S & kI2C_IntPendingFlag))
|
|
{
|
|
}
|
|
|
|
statusFlags = base->S;
|
|
|
|
/* Clear the IICIF flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
/* Check if arbitration lost or no acknowledgement (NAK), return failure status. */
|
|
if (statusFlags & kI2C_ArbitrationLostFlag)
|
|
{
|
|
base->S = kI2C_ArbitrationLostFlag;
|
|
result = kStatus_I2C_ArbitrationLost;
|
|
}
|
|
|
|
if ((statusFlags & kI2C_ReceiveNakFlag) && txSize)
|
|
{
|
|
base->S = kI2C_ReceiveNakFlag;
|
|
result = kStatus_I2C_Nak;
|
|
}
|
|
|
|
if (result != kStatus_Success)
|
|
{
|
|
/* Breaking out of the send loop. */
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (((result == kStatus_Success) && (!(flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak))
|
|
{
|
|
/* Clear the IICIF flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
/* Send stop. */
|
|
result = I2C_MasterStop(base);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags)
|
|
{
|
|
status_t result = kStatus_Success;
|
|
volatile uint8_t dummy = 0;
|
|
|
|
/* Add this to avoid build warning. */
|
|
dummy++;
|
|
|
|
/* Wait until the data register is ready for transmit. */
|
|
while (!(base->S & kI2C_TransferCompleteFlag))
|
|
{
|
|
}
|
|
|
|
/* Clear the IICIF flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
/* Setup the I2C peripheral to receive data. */
|
|
base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
|
|
|
|
/* If rxSize equals 1, configure to send NAK. */
|
|
if (rxSize == 1)
|
|
{
|
|
/* Issue NACK on read. */
|
|
base->C1 |= I2C_C1_TXAK_MASK;
|
|
}
|
|
|
|
/* Do dummy read. */
|
|
dummy = base->D;
|
|
|
|
while ((rxSize--))
|
|
{
|
|
/* Wait until data transfer complete. */
|
|
while (!(base->S & kI2C_IntPendingFlag))
|
|
{
|
|
}
|
|
|
|
/* Clear the IICIF flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
/* Single byte use case. */
|
|
if (rxSize == 0)
|
|
{
|
|
if (!(flags & kI2C_TransferNoStopFlag))
|
|
{
|
|
/* Issue STOP command before reading last byte. */
|
|
result = I2C_MasterStop(base);
|
|
}
|
|
else
|
|
{
|
|
/* Change direction to Tx to avoid extra clocks. */
|
|
base->C1 |= I2C_C1_TX_MASK;
|
|
}
|
|
}
|
|
|
|
if (rxSize == 1)
|
|
{
|
|
/* Issue NACK on read. */
|
|
base->C1 |= I2C_C1_TXAK_MASK;
|
|
}
|
|
|
|
/* Read from the data register. */
|
|
*rxBuff++ = base->D;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer)
|
|
{
|
|
assert(xfer);
|
|
|
|
i2c_direction_t direction = xfer->direction;
|
|
status_t result = kStatus_Success;
|
|
|
|
/* Clear all status before transfer. */
|
|
I2C_MasterClearStatusFlags(base, kClearFlags);
|
|
|
|
/* Wait until ready to complete. */
|
|
while (!(base->S & kI2C_TransferCompleteFlag))
|
|
{
|
|
}
|
|
|
|
/* Change to send write address when it's a read operation with command. */
|
|
if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read))
|
|
{
|
|
direction = kI2C_Write;
|
|
}
|
|
|
|
/* If repeated start is requested, send repeated start. */
|
|
if (xfer->flags & kI2C_TransferRepeatedStartFlag)
|
|
{
|
|
result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction);
|
|
}
|
|
else /* For normal transfer, send start. */
|
|
{
|
|
result = I2C_MasterStart(base, xfer->slaveAddress, direction);
|
|
}
|
|
|
|
/* Return if error. */
|
|
if (result)
|
|
{
|
|
return result;
|
|
}
|
|
|
|
while (!(base->S & kI2C_IntPendingFlag))
|
|
{
|
|
}
|
|
|
|
/* Check if there's transfer error. */
|
|
result = I2C_CheckAndClearError(base, base->S);
|
|
|
|
/* Return if error. */
|
|
if (result)
|
|
{
|
|
if (result == kStatus_I2C_Nak)
|
|
{
|
|
result = kStatus_I2C_Addr_Nak;
|
|
|
|
I2C_MasterStop(base);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
/* Send subaddress. */
|
|
if (xfer->subaddressSize)
|
|
{
|
|
do
|
|
{
|
|
/* Clear interrupt pending flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
xfer->subaddressSize--;
|
|
base->D = ((xfer->subaddress) >> (8 * xfer->subaddressSize));
|
|
|
|
/* Wait until data transfer complete. */
|
|
while (!(base->S & kI2C_IntPendingFlag))
|
|
{
|
|
}
|
|
|
|
/* Check if there's transfer error. */
|
|
result = I2C_CheckAndClearError(base, base->S);
|
|
|
|
if (result)
|
|
{
|
|
if (result == kStatus_I2C_Nak)
|
|
{
|
|
I2C_MasterStop(base);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
} while ((xfer->subaddressSize > 0) && (result == kStatus_Success));
|
|
|
|
if (xfer->direction == kI2C_Read)
|
|
{
|
|
/* Clear pending flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
/* Send repeated start and slave address. */
|
|
result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read);
|
|
|
|
/* Return if error. */
|
|
if (result)
|
|
{
|
|
return result;
|
|
}
|
|
|
|
/* Wait until data transfer complete. */
|
|
while (!(base->S & kI2C_IntPendingFlag))
|
|
{
|
|
}
|
|
|
|
/* Check if there's transfer error. */
|
|
result = I2C_CheckAndClearError(base, base->S);
|
|
|
|
if (result)
|
|
{
|
|
if (result == kStatus_I2C_Nak)
|
|
{
|
|
result = kStatus_I2C_Addr_Nak;
|
|
|
|
I2C_MasterStop(base);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Transmit data. */
|
|
if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0))
|
|
{
|
|
/* Send Data. */
|
|
result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
|
|
}
|
|
|
|
/* Receive Data. */
|
|
if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0))
|
|
{
|
|
result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
void I2C_MasterTransferCreateHandle(I2C_Type *base,
|
|
i2c_master_handle_t *handle,
|
|
i2c_master_transfer_callback_t callback,
|
|
void *userData)
|
|
{
|
|
assert(handle);
|
|
|
|
uint32_t instance = I2C_GetInstance(base);
|
|
|
|
/* Zero handle. */
|
|
memset(handle, 0, sizeof(*handle));
|
|
|
|
/* Set callback and userData. */
|
|
handle->completionCallback = callback;
|
|
handle->userData = userData;
|
|
|
|
/* Save the context in global variables to support the double weak mechanism. */
|
|
s_i2cHandle[instance] = handle;
|
|
|
|
/* Save master interrupt handler. */
|
|
s_i2cMasterIsr = I2C_MasterTransferHandleIRQ;
|
|
|
|
/* Enable NVIC interrupt. */
|
|
EnableIRQ(s_i2cIrqs[instance]);
|
|
}
|
|
|
|
status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
|
|
{
|
|
assert(handle);
|
|
assert(xfer);
|
|
|
|
status_t result = kStatus_Success;
|
|
|
|
/* Check if the I2C bus is idle - if not return busy status. */
|
|
if (handle->state != kIdleState)
|
|
{
|
|
result = kStatus_I2C_Busy;
|
|
}
|
|
else
|
|
{
|
|
/* Start up the master transfer state machine. */
|
|
result = I2C_InitTransferStateMachine(base, handle, xfer);
|
|
|
|
if (result == kStatus_Success)
|
|
{
|
|
/* Enable the I2C interrupts. */
|
|
I2C_EnableInterrupts(base, kI2C_GlobalInterruptEnable);
|
|
}
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
volatile uint8_t dummy = 0;
|
|
|
|
/* Add this to avoid build warning. */
|
|
dummy++;
|
|
|
|
/* Disable interrupt. */
|
|
I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable);
|
|
|
|
/* Reset the state to idle. */
|
|
handle->state = kIdleState;
|
|
|
|
/* Send STOP signal. */
|
|
if (handle->transfer.direction == kI2C_Read)
|
|
{
|
|
base->C1 |= I2C_C1_TXAK_MASK;
|
|
while (!(base->S & kI2C_IntPendingFlag))
|
|
{
|
|
}
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
|
|
dummy = base->D;
|
|
}
|
|
else
|
|
{
|
|
while (!(base->S & kI2C_IntPendingFlag))
|
|
{
|
|
}
|
|
base->S = kI2C_IntPendingFlag;
|
|
base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
|
|
}
|
|
}
|
|
|
|
status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count)
|
|
{
|
|
assert(handle);
|
|
|
|
if (!count)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
*count = handle->transferSize - handle->transfer.dataSize;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
|
|
{
|
|
assert(i2cHandle);
|
|
|
|
i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle;
|
|
status_t result = kStatus_Success;
|
|
bool isDone;
|
|
|
|
/* Clear the interrupt flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
/* Check transfer complete flag. */
|
|
result = I2C_MasterTransferRunStateMachine(base, handle, &isDone);
|
|
|
|
if (isDone || result)
|
|
{
|
|
/* Send stop command if transfer done or received Nak. */
|
|
if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak) ||
|
|
(result == kStatus_I2C_Addr_Nak))
|
|
{
|
|
/* Ensure stop command is a need. */
|
|
if ((base->C1 & I2C_C1_MST_MASK))
|
|
{
|
|
if (I2C_MasterStop(base) != kStatus_Success)
|
|
{
|
|
result = kStatus_I2C_Timeout;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore handle to idle state. */
|
|
handle->state = kIdleState;
|
|
|
|
/* Disable interrupt. */
|
|
I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable);
|
|
|
|
/* Call the callback function after the function has completed. */
|
|
if (handle->completionCallback)
|
|
{
|
|
handle->completionCallback(base, handle, result, handle->userData);
|
|
}
|
|
}
|
|
}
|
|
|
|
void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz)
|
|
{
|
|
assert(slaveConfig);
|
|
|
|
uint8_t tmpReg;
|
|
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
|
|
/* Reset the module. */
|
|
base->A1 = 0;
|
|
base->F = 0;
|
|
base->C1 = 0;
|
|
base->S = 0xFFU;
|
|
base->C2 = 0;
|
|
#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
|
|
base->FLT = 0x50U;
|
|
#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
|
|
base->FLT = 0x40U;
|
|
#endif
|
|
base->RA = 0;
|
|
|
|
/* Configure addressing mode. */
|
|
switch (slaveConfig->addressingMode)
|
|
{
|
|
case kI2C_Address7bit:
|
|
base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U;
|
|
break;
|
|
|
|
case kI2C_RangeMatch:
|
|
assert(slaveConfig->slaveAddress < slaveConfig->upperAddress);
|
|
base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U;
|
|
base->RA = ((uint32_t)(slaveConfig->upperAddress)) << 1U;
|
|
base->C2 |= I2C_C2_RMEN_MASK;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Configure low power wake up feature. */
|
|
tmpReg = base->C1;
|
|
tmpReg &= ~I2C_C1_WUEN_MASK;
|
|
base->C1 = tmpReg | I2C_C1_WUEN(slaveConfig->enableWakeUp) | I2C_C1_IICEN(slaveConfig->enableSlave);
|
|
|
|
/* Configure general call & baud rate control. */
|
|
tmpReg = base->C2;
|
|
tmpReg &= ~(I2C_C2_SBRC_MASK | I2C_C2_GCAEN_MASK);
|
|
tmpReg |= I2C_C2_SBRC(slaveConfig->enableBaudRateCtl) | I2C_C2_GCAEN(slaveConfig->enableGeneralCall);
|
|
base->C2 = tmpReg;
|
|
|
|
/* Enable/Disable double buffering. */
|
|
#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
|
|
tmpReg = base->S2 & (~I2C_S2_DFEN_MASK);
|
|
base->S2 = tmpReg | I2C_S2_DFEN(slaveConfig->enableDoubleBuffering);
|
|
#endif
|
|
|
|
/* Set hold time. */
|
|
I2C_SetHoldTime(base, slaveConfig->sclStopHoldTime_ns, srcClock_Hz);
|
|
}
|
|
|
|
void I2C_SlaveDeinit(I2C_Type *base)
|
|
{
|
|
/* Disable I2C module. */
|
|
I2C_Enable(base, false);
|
|
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
/* Disable I2C clock. */
|
|
CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
}
|
|
|
|
void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)
|
|
{
|
|
assert(slaveConfig);
|
|
|
|
/* By default slave is addressed with 7-bit address. */
|
|
slaveConfig->addressingMode = kI2C_Address7bit;
|
|
|
|
/* General call mode is disabled by default. */
|
|
slaveConfig->enableGeneralCall = false;
|
|
|
|
/* Slave address match waking up MCU from low power mode is disabled. */
|
|
slaveConfig->enableWakeUp = false;
|
|
|
|
/* Independent slave mode baud rate at maximum frequency is disabled. */
|
|
slaveConfig->enableBaudRateCtl = false;
|
|
|
|
/* Default enable double buffering. */
|
|
#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
|
|
slaveConfig->enableDoubleBuffering = true;
|
|
#endif
|
|
|
|
/* Set default SCL stop hold time to 4us which is minimum requirement in I2C spec. */
|
|
slaveConfig->sclStopHoldTime_ns = 4000;
|
|
|
|
/* Enable the I2C peripheral. */
|
|
slaveConfig->enableSlave = true;
|
|
}
|
|
|
|
status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)
|
|
{
|
|
status_t result = kStatus_Success;
|
|
volatile uint8_t dummy = 0;
|
|
|
|
/* Add this to avoid build warning. */
|
|
dummy++;
|
|
|
|
#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
|
|
/* Check start flag. */
|
|
while (!(base->FLT & I2C_FLT_STARTF_MASK))
|
|
{
|
|
}
|
|
/* Clear STARTF flag. */
|
|
base->FLT |= I2C_FLT_STARTF_MASK;
|
|
/* Clear the IICIF flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
|
|
|
|
/* Wait for address match flag. */
|
|
while (!(base->S & kI2C_AddressMatchFlag))
|
|
{
|
|
}
|
|
|
|
/* Read dummy to release bus. */
|
|
dummy = base->D;
|
|
|
|
result = I2C_MasterWriteBlocking(base, txBuff, txSize, kI2C_TransferDefaultFlag);
|
|
|
|
/* Switch to receive mode. */
|
|
base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
|
|
|
|
/* Read dummy to release bus. */
|
|
dummy = base->D;
|
|
|
|
return result;
|
|
}
|
|
|
|
void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
|
|
{
|
|
volatile uint8_t dummy = 0;
|
|
|
|
/* Add this to avoid build warning. */
|
|
dummy++;
|
|
|
|
/* Wait until address match. */
|
|
#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
|
|
/* Check start flag. */
|
|
while (!(base->FLT & I2C_FLT_STARTF_MASK))
|
|
{
|
|
}
|
|
/* Clear STARTF flag. */
|
|
base->FLT |= I2C_FLT_STARTF_MASK;
|
|
/* Clear the IICIF flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
|
|
|
|
/* Wait for address match and int pending flag. */
|
|
while (!(base->S & kI2C_AddressMatchFlag))
|
|
{
|
|
}
|
|
while (!(base->S & kI2C_IntPendingFlag))
|
|
{
|
|
}
|
|
|
|
/* Read dummy to release bus. */
|
|
dummy = base->D;
|
|
|
|
/* Clear the IICIF flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
/* Setup the I2C peripheral to receive data. */
|
|
base->C1 &= ~(I2C_C1_TX_MASK);
|
|
|
|
while (rxSize--)
|
|
{
|
|
/* Wait until data transfer complete. */
|
|
while (!(base->S & kI2C_IntPendingFlag))
|
|
{
|
|
}
|
|
/* Clear the IICIF flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
/* Read from the data register. */
|
|
*rxBuff++ = base->D;
|
|
}
|
|
}
|
|
|
|
void I2C_SlaveTransferCreateHandle(I2C_Type *base,
|
|
i2c_slave_handle_t *handle,
|
|
i2c_slave_transfer_callback_t callback,
|
|
void *userData)
|
|
{
|
|
assert(handle);
|
|
|
|
uint32_t instance = I2C_GetInstance(base);
|
|
|
|
/* Zero handle. */
|
|
memset(handle, 0, sizeof(*handle));
|
|
|
|
/* Set callback and userData. */
|
|
handle->callback = callback;
|
|
handle->userData = userData;
|
|
|
|
/* Save the context in global variables to support the double weak mechanism. */
|
|
s_i2cHandle[instance] = handle;
|
|
|
|
/* Save slave interrupt handler. */
|
|
s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ;
|
|
|
|
/* Enable NVIC interrupt. */
|
|
EnableIRQ(s_i2cIrqs[instance]);
|
|
}
|
|
|
|
status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask)
|
|
{
|
|
assert(handle);
|
|
|
|
/* Check if the I2C bus is idle - if not return busy status. */
|
|
if (handle->isBusy)
|
|
{
|
|
return kStatus_I2C_Busy;
|
|
}
|
|
else
|
|
{
|
|
/* Disable LPI2C IRQ sources while we configure stuff. */
|
|
I2C_DisableInterrupts(base, kIrqFlags);
|
|
|
|
/* Clear transfer in handle. */
|
|
memset(&handle->transfer, 0, sizeof(handle->transfer));
|
|
|
|
/* Record that we're busy. */
|
|
handle->isBusy = true;
|
|
|
|
/* Set up event mask. tx and rx are always enabled. */
|
|
handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | kI2C_SlaveGenaralcallEvent;
|
|
|
|
/* Clear all flags. */
|
|
I2C_SlaveClearStatusFlags(base, kClearFlags);
|
|
|
|
/* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */
|
|
I2C_EnableInterrupts(base, kIrqFlags);
|
|
}
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
if (handle->isBusy)
|
|
{
|
|
/* Disable interrupts. */
|
|
I2C_DisableInterrupts(base, kIrqFlags);
|
|
|
|
/* Reset transfer info. */
|
|
memset(&handle->transfer, 0, sizeof(handle->transfer));
|
|
|
|
/* Reset the state to idle. */
|
|
handle->isBusy = false;
|
|
}
|
|
}
|
|
|
|
status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count)
|
|
{
|
|
assert(handle);
|
|
|
|
if (!count)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Catch when there is not an active transfer. */
|
|
if (!handle->isBusy)
|
|
{
|
|
*count = 0;
|
|
return kStatus_NoTransferInProgress;
|
|
}
|
|
|
|
/* For an active transfer, just return the count from the handle. */
|
|
*count = handle->transfer.transferredCount;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
|
|
{
|
|
assert(i2cHandle);
|
|
|
|
uint16_t status;
|
|
bool doTransmit = false;
|
|
i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle;
|
|
i2c_slave_transfer_t *xfer;
|
|
volatile uint8_t dummy = 0;
|
|
|
|
/* Add this to avoid build warning. */
|
|
dummy++;
|
|
|
|
status = I2C_SlaveGetStatusFlags(base);
|
|
xfer = &(handle->transfer);
|
|
|
|
#ifdef I2C_HAS_STOP_DETECT
|
|
/* Check stop flag. */
|
|
if (status & kI2C_StopDetectFlag)
|
|
{
|
|
I2C_MasterClearStatusFlags(base, kI2C_StopDetectFlag);
|
|
|
|
/* Clear the interrupt flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
/* Call slave callback if this is the STOP of the transfer. */
|
|
if (handle->isBusy)
|
|
{
|
|
xfer->event = kI2C_SlaveCompletionEvent;
|
|
xfer->completionStatus = kStatus_Success;
|
|
handle->isBusy = false;
|
|
|
|
if ((handle->eventMask & xfer->event) && (handle->callback))
|
|
{
|
|
handle->callback(base, xfer, handle->userData);
|
|
}
|
|
}
|
|
|
|
if (!(status & kI2C_AddressMatchFlag))
|
|
{
|
|
return;
|
|
}
|
|
}
|
|
#endif /* I2C_HAS_STOP_DETECT */
|
|
|
|
#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
|
|
/* Check start flag. */
|
|
if (status & kI2C_StartDetectFlag)
|
|
{
|
|
I2C_MasterClearStatusFlags(base, kI2C_StartDetectFlag);
|
|
|
|
/* Clear the interrupt flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
xfer->event = kI2C_SlaveStartEvent;
|
|
|
|
if ((handle->eventMask & xfer->event) && (handle->callback))
|
|
{
|
|
handle->callback(base, xfer, handle->userData);
|
|
}
|
|
|
|
if (!(status & kI2C_AddressMatchFlag))
|
|
{
|
|
return;
|
|
}
|
|
}
|
|
#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
|
|
|
|
/* Clear the interrupt flag. */
|
|
base->S = kI2C_IntPendingFlag;
|
|
|
|
/* Check NAK */
|
|
if (status & kI2C_ReceiveNakFlag)
|
|
{
|
|
/* Set receive mode. */
|
|
base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
|
|
|
|
/* Read dummy. */
|
|
dummy = base->D;
|
|
|
|
if (handle->transfer.dataSize != 0)
|
|
{
|
|
xfer->event = kI2C_SlaveCompletionEvent;
|
|
xfer->completionStatus = kStatus_I2C_Nak;
|
|
handle->isBusy = false;
|
|
|
|
if ((handle->eventMask & xfer->event) && (handle->callback))
|
|
{
|
|
handle->callback(base, xfer, handle->userData);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
#ifndef I2C_HAS_STOP_DETECT
|
|
xfer->event = kI2C_SlaveCompletionEvent;
|
|
xfer->completionStatus = kStatus_Success;
|
|
handle->isBusy = false;
|
|
|
|
if ((handle->eventMask & xfer->event) && (handle->callback))
|
|
{
|
|
handle->callback(base, xfer, handle->userData);
|
|
}
|
|
#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */
|
|
}
|
|
}
|
|
/* Check address match. */
|
|
else if (status & kI2C_AddressMatchFlag)
|
|
{
|
|
handle->isBusy = true;
|
|
xfer->event = kI2C_SlaveAddressMatchEvent;
|
|
|
|
/* Slave transmit, master reading from slave. */
|
|
if (status & kI2C_TransferDirectionFlag)
|
|
{
|
|
/* Change direction to send data. */
|
|
base->C1 |= I2C_C1_TX_MASK;
|
|
|
|
doTransmit = true;
|
|
}
|
|
else
|
|
{
|
|
/* Slave receive, master writing to slave. */
|
|
base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
|
|
|
|
/* Read dummy to release the bus. */
|
|
dummy = base->D;
|
|
|
|
if (dummy == 0)
|
|
{
|
|
xfer->event = kI2C_SlaveGenaralcallEvent;
|
|
}
|
|
}
|
|
|
|
if ((handle->eventMask & xfer->event) && (handle->callback))
|
|
{
|
|
handle->callback(base, xfer, handle->userData);
|
|
}
|
|
}
|
|
/* Check transfer complete flag. */
|
|
else if (status & kI2C_TransferCompleteFlag)
|
|
{
|
|
/* Slave transmit, master reading from slave. */
|
|
if (status & kI2C_TransferDirectionFlag)
|
|
{
|
|
doTransmit = true;
|
|
}
|
|
else
|
|
{
|
|
/* If we're out of data, invoke callback to get more. */
|
|
if ((!xfer->data) || (!xfer->dataSize))
|
|
{
|
|
xfer->event = kI2C_SlaveReceiveEvent;
|
|
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, xfer, handle->userData);
|
|
}
|
|
|
|
/* Clear the transferred count now that we have a new buffer. */
|
|
xfer->transferredCount = 0;
|
|
}
|
|
|
|
/* Slave receive, master writing to slave. */
|
|
uint8_t data = base->D;
|
|
|
|
if (handle->transfer.dataSize)
|
|
{
|
|
/* Receive data. */
|
|
*handle->transfer.data++ = data;
|
|
handle->transfer.dataSize--;
|
|
xfer->transferredCount++;
|
|
if (!handle->transfer.dataSize)
|
|
{
|
|
#ifndef I2C_HAS_STOP_DETECT
|
|
xfer->event = kI2C_SlaveCompletionEvent;
|
|
xfer->completionStatus = kStatus_Success;
|
|
handle->isBusy = false;
|
|
|
|
/* Proceed receive complete event. */
|
|
if ((handle->eventMask & xfer->event) && (handle->callback))
|
|
{
|
|
handle->callback(base, xfer, handle->userData);
|
|
}
|
|
#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Read dummy to release bus. */
|
|
dummy = base->D;
|
|
}
|
|
|
|
/* Send data if there is the need. */
|
|
if (doTransmit)
|
|
{
|
|
/* If we're out of data, invoke callback to get more. */
|
|
if ((!xfer->data) || (!xfer->dataSize))
|
|
{
|
|
xfer->event = kI2C_SlaveTransmitEvent;
|
|
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, xfer, handle->userData);
|
|
}
|
|
|
|
/* Clear the transferred count now that we have a new buffer. */
|
|
xfer->transferredCount = 0;
|
|
}
|
|
|
|
if (handle->transfer.dataSize)
|
|
{
|
|
/* Send data. */
|
|
base->D = *handle->transfer.data++;
|
|
handle->transfer.dataSize--;
|
|
xfer->transferredCount++;
|
|
}
|
|
else
|
|
{
|
|
/* Switch to receive mode. */
|
|
base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
|
|
|
|
/* Read dummy to release bus. */
|
|
dummy = base->D;
|
|
|
|
#ifndef I2C_HAS_STOP_DETECT
|
|
xfer->event = kI2C_SlaveCompletionEvent;
|
|
xfer->completionStatus = kStatus_Success;
|
|
handle->isBusy = false;
|
|
|
|
/* Proceed txdone event. */
|
|
if ((handle->eventMask & xfer->event) && (handle->callback))
|
|
{
|
|
handle->callback(base, xfer, handle->userData);
|
|
}
|
|
#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */
|
|
}
|
|
}
|
|
}
|
|
|
|
#if defined(I2C0)
|
|
void I2C0_DriverIRQHandler(void)
|
|
{
|
|
I2C_TransferCommonIRQHandler(I2C0, s_i2cHandle[0]);
|
|
}
|
|
#endif
|
|
|
|
#if defined(I2C1)
|
|
void I2C1_DriverIRQHandler(void)
|
|
{
|
|
I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]);
|
|
}
|
|
#endif
|
|
|
|
#if defined(I2C2)
|
|
void I2C2_DriverIRQHandler(void)
|
|
{
|
|
I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]);
|
|
}
|
|
#endif
|
|
|
|
#if defined(I2C3)
|
|
void I2C3_DriverIRQHandler(void)
|
|
{
|
|
I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]);
|
|
}
|
|
#endif
|