821 lines
30 KiB
C
821 lines
30 KiB
C
/*!
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\file gd32f4xx_dma.c
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\brief DMA driver
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*/
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/*
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Copyright (C) 2016 GigaDevice
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2016-08-15, V1.0.0, firmware for GD32F4xx
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*/
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#include "gd32f4xx_dma.h"
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/* DMA register bit offset */
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#define CHXCTL_PERIEN_OFFSET ((uint32_t)25U)
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/*!
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\brief deinitialize DMA a channel registers
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel is deinitialized
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\arg DMA_CHx(x=0..7)
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\param[out] none
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\retval none
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*/
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void dma_deinit(uint32_t dma_periph,dma_channel_enum channelx)
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{
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/* disable DMA a channel */
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DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN;
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/* reset DMA channel registers */
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DMA_CHCTL(dma_periph,channelx) = DMA_CHCTL_RESET_VALUE;
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DMA_CHCNT(dma_periph,channelx) = DMA_CHCNT_RESET_VALUE;
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DMA_CHPADDR(dma_periph,channelx) = DMA_CHPADDR_RESET_VALUE;
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DMA_CHM0ADDR(dma_periph,channelx) = DMA_CHMADDR_RESET_VALUE;
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DMA_CHM1ADDR(dma_periph,channelx) = DMA_CHMADDR_RESET_VALUE;
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DMA_CHFCTL(dma_periph,channelx) = DMA_CHFCTL_RESET_VALUE;
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if(channelx < DMA_CH4){
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DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx);
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}else{
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DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx);
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}
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}
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/*!
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\brief initialize DMA single data mode
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel is initialized
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\arg DMA_CHx(x=0..7)
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\param[in] init_struct: the data needed to initialize DMA single data mode
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periph_addr: peripheral base address
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periph_memory_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT
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periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX
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memory0_addr: memory base address
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memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE
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direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY
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number: the number of remaining data to be transferred by the DMA
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priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH
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circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE
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\param[out] none
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\retval none
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*/
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void dma_single_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_single_data_parameter_struct init_struct)
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{
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uint32_t ctl;
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/* select single data mode */
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DMA_CHFCTL(dma_periph,channelx) &= ~DMA_CHXFCTL_MDMEN;
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/* configure peripheral base address */
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DMA_CHPADDR(dma_periph,channelx) = init_struct.periph_addr;
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/* configure memory base address */
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DMA_CHM0ADDR(dma_periph,channelx) = init_struct.memory0_addr;
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/* configure the number of remaining data to be transferred */
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DMA_CHCNT(dma_periph,channelx) = init_struct.number;
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/* configure peripheral and memory transfer width,channel priotity,transfer mode */
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ctl = DMA_CHCTL(dma_periph,channelx);
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ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM);
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ctl |= (init_struct.periph_memory_width | (init_struct.periph_memory_width << 2) | init_struct.priority | init_struct.direction);
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DMA_CHCTL(dma_periph,channelx) = ctl;
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/* configure peripheral increasing mode */
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if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
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DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA;
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}else if(DMA_PERIPH_INCREASE_DISABLE == init_struct.periph_inc){
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DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA;
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}else{
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DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF;
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}
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/* configure memory increasing mode */
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if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
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DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA;
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}else{
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DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA;
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}
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/* configure DMA circular mode */
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if(DMA_CIRCULAR_MODE_ENABLE == init_struct.circular_mode){
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DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN;
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}else{
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DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN;
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}
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}
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/*!
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\brief initialize DMA multi data mode
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel is initialized
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\arg DMA_CHx(x=0..7)
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\param[in] dma_multi_data_parameter_struct: the data needed to initialize DMA multi data mode
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periph_addr: peripheral base address
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periph_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT
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periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX
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memory0_addr: memory0 base address
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memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT
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memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE
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direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY
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number: the number of remaining data to be transferred by the DMA
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priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH
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circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE
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memory_burst_width: DMA_MEMORY_BURST_SINGLE,DMA_MEMORY_BURST_4_BEAT,DMA_MEMORY_BURST_8_BEAT,DMA_MEMORY_BURST_16_BEAT
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periph_burst_width: DMA_PERIPH_BURST_SINGLE,DMA_PERIPH_BURST_4_BEAT,DMA_PERIPH_BURST_8_BEAT,DMA_PERIPH_BURST_16_BEAT
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critical_value: DMA_FIFO_1_WORD,DMA_FIFO_2_WORD,DMA_FIFO_3_WORD,DMA_FIFO_4_WORD
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\param[out] none
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\retval none
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*/
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void dma_multi_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_multi_data_parameter_struct init_struct)
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{
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uint32_t ctl;
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/* select multi data mode and configure FIFO critical value */
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DMA_CHFCTL(dma_periph,channelx) |= (DMA_CHXFCTL_MDMEN | init_struct.critical_value);
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/* configure peripheral base address */
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DMA_CHPADDR(dma_periph,channelx) = init_struct.periph_addr;
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/* configure memory base address */
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DMA_CHM0ADDR(dma_periph,channelx) = init_struct.memory0_addr;
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/* configure the number of remaining data to be transferred */
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DMA_CHCNT(dma_periph,channelx) = init_struct.number;
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/* configure peripheral and memory transfer width,channel priotity,transfer mode,peripheral and memory burst transfer width */
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ctl = DMA_CHCTL(dma_periph,channelx);
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ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM | DMA_CHXCTL_PBURST | DMA_CHXCTL_MBURST);
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ctl |= (init_struct.periph_width | (init_struct.memory_width ) | init_struct.priority | init_struct.direction | init_struct.memory_burst_width | init_struct.periph_burst_width);
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DMA_CHCTL(dma_periph,channelx) = ctl;
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/* configure peripheral increasing mode */
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if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
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DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA;
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}else if(DMA_PERIPH_INCREASE_DISABLE == init_struct.periph_inc){
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DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA;
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}else{
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DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF;
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}
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/* configure memory increasing mode */
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if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
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DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA;
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}else{
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DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA;
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}
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/* configure DMA circular mode */
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if(DMA_CIRCULAR_MODE_ENABLE == init_struct.circular_mode){
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DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN;
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}else{
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DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN;
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}
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}
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/*!
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\brief get DMA flag is set or not
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel to get flag
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\arg DMA_CHx(x=0..7)
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\param[in] flag: specify get which flag
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\arg DMA_INTF_FEEIF: FIFO error and exception flag
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\arg DMA_INTF_SDEIF: single data mode exception flag
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\arg DMA_INTF_TAEIF: transfer access error flag
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\arg DMA_INTF_HTFIF: half transfer finish flag
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\arg DMA_INTF_FTFIF: full transger finish flag
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\param[out] none
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\retval FlagStatus: SET or RESET
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*/
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FlagStatus dma_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag)
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{
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if(channelx < DMA_CH4){
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if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag,channelx)){
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return SET;
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}else{
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return RESET;
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}
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}else{
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channelx -= (dma_channel_enum)4;
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if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag,channelx)){
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return SET;
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}else{
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return RESET;
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}
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}
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}
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/*!
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\brief clear DMA a channel flag
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel to get flag
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\arg DMA_CHx(x=0..7)
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\param[in] flag: specify get which flag
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\arg DMA_INTF_FEEIF: FIFO error and exception flag
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\arg DMA_INTF_SDEIF: single data mode exception flag
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\arg DMA_INTF_TAEIF: transfer access error flag
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\arg DMA_INTF_HTFIF: half transfer finish flag
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\arg DMA_INTF_FTFIF: full transger finish flag
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\param[out] none
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\retval none
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*/
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void dma_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag)
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{
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if(channelx < DMA_CH4){
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DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag,channelx);
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}else{
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channelx -= (dma_channel_enum)4;
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DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(flag,channelx);
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}
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}
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/*!
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\brief get DMA interrupt flag is set or not
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel to get interrupt flag
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\arg DMA_CHx(x=0..7)
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\param[in] interrupt: specify get which flag
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\arg DMA_INTF_FEEIF: FIFO error and exception flag
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\arg DMA_INTF_SDEIF: single data mode exception flag
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\arg DMA_INTF_TAEIF: transfer access error flag
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\arg DMA_INTF_HTFIF: half transfer finish flag
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\arg DMA_INTF_FTFIF: full transger finish flag
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\param[out] none
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\retval FlagStatus: SET or RESET
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*/
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FlagStatus dma_interrupt_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt)
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{
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uint32_t interrupt_enable = 0U,interrupt_flag = 0U;
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dma_channel_enum channel_flag_offset = channelx;
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if(channelx < DMA_CH4){
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switch(interrupt){
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case DMA_INTF_FEEIF:
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interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx);
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interrupt_enable = DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FEEIE;
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break;
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case DMA_INTF_SDEIF:
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interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx);
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interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_SDEIE;
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break;
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case DMA_INTF_TAEIF:
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interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx);
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interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_TAEIE;
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break;
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case DMA_INTF_HTFIF:
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interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx);
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interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_HTFIE;
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break;
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case DMA_INTF_FTFIF:
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interrupt_flag = (DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx));
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interrupt_enable = (DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_FTFIE);
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break;
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default:
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break;
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}
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}else{
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channel_flag_offset -= (dma_channel_enum)4;
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switch(interrupt){
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case DMA_INTF_FEEIF:
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interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset);
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interrupt_enable = DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FEEIE;
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break;
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case DMA_INTF_SDEIF:
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interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset);
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interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_SDEIE;
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break;
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case DMA_INTF_TAEIF:
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interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset);
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interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_TAEIE;
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break;
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case DMA_INTF_HTFIF:
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interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset);
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interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_HTFIE;
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break;
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case DMA_INTF_FTFIF:
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interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset);
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interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_FTFIE;
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break;
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default:
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break;
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}
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}
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if(interrupt_flag && interrupt_enable){
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return SET;
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}else{
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return RESET;
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}
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}
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/*!
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\brief clear DMA a channel interrupt flag
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel to clear interrupt flag
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\arg DMA_CHx(x=0..7)
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\param[in] interrupt: specify get which flag
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\arg DMA_INTC_FEEIFC: clear FIFO error and exception flag
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\arg DMA_INTC_SDEIFC: clear single data mode exception flag
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\arg DMA_INTC_TAEIFC: clear transfer access error flag
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\arg DMA_INTC_HTFIFC: clear half transfer finish flag
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\arg DMA_INTC_FTFIFC: clear full transger finish flag
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\param[out] none
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\retval none
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*/
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void dma_interrupt_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt)
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{
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if(channelx < DMA_CH4){
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DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(interrupt,channelx);
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}else{
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channelx -= (dma_channel_enum)4;
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DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(interrupt,channelx);
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}
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}
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/*!
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\brief enable DMA interrupt
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel
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\arg DMA_CHx(x=0..7)
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\param[in] source: specify which interrupt to enbale
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\arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable
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\arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable
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\arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable
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\arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable
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\arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable
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\param[out] none
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\retval none
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*/
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void dma_interrupt_enable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source)
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{
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if(DMA_CHXFCTL_FEEIE != source){
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DMA_CHCTL(dma_periph,channelx) |= source;
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}else{
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DMA_CHFCTL(dma_periph,channelx) |= source;
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}
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}
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/*!
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\brief disable DMA interrupt
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel
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\arg DMA_CHx(x=0..7)
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\param[in] source: specify which interrupt to disbale
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\arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable
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\arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable
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\arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable
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\arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable
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\arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable
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\param[out] none
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\retval none
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*/
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void dma_interrupt_disable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source)
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{
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if(DMA_CHXFCTL_FEEIE != source){
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DMA_CHCTL(dma_periph,channelx) &= ~source;
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}else{
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DMA_CHFCTL(dma_periph,channelx) &= ~source;
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}
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}
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/*!
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\brief set DMA peripheral base address
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel to set peripheral base address
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\arg DMA_CHx(x=0..7)
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\param[in] address: peripheral base address
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\param[out] none
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\retval none
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*/
|
|
void dma_periph_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t address)
|
|
{
|
|
DMA_CHPADDR(dma_periph,channelx) = address;
|
|
}
|
|
|
|
/*!
|
|
\brief set DMA Memory0 base address
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel to set Memory base address
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] memory_flag: DMA_MEMORY_x(x=0,1)
|
|
\param[in] address: Memory base address
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_memory_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t memory_flag,uint32_t address)
|
|
{
|
|
if(memory_flag){
|
|
DMA_CHM1ADDR(dma_periph,channelx) = address;
|
|
}else{
|
|
DMA_CHM0ADDR(dma_periph,channelx) = address;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief set the number of remaining data to be transferred by the DMA
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel to set number
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] number: the number of remaining data to be transferred by the DMA
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t number)
|
|
{
|
|
DMA_CHCNT(dma_periph,channelx) = number;
|
|
}
|
|
|
|
/*!
|
|
\brief get the number of remaining data to be transferred by the DMA
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel to set number
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[out] none
|
|
\retval uint32_t: the number of remaining data to be transferred by the DMA
|
|
*/
|
|
uint32_t dma_transfer_number_get(uint32_t dma_periph,dma_channel_enum channelx)
|
|
{
|
|
return (uint32_t)DMA_CHCNT(dma_periph,channelx);
|
|
}
|
|
|
|
/*!
|
|
\brief configure priority level of DMA channel
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] priority: priority Level of this channel
|
|
\arg DMA_PRIORITY_LOW: low priority
|
|
\arg DMA_PRIORITY_MEDIUM: medium priority
|
|
\arg DMA_PRIORITY_HIGH: high priority
|
|
\arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_priority_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t priority)
|
|
{
|
|
uint32_t ctl;
|
|
/* acquire DMA_CHxCTL register */
|
|
ctl = DMA_CHCTL(dma_periph,channelx);
|
|
/* assign regiser */
|
|
ctl &= ~DMA_CHXCTL_PRIO;
|
|
ctl |= priority;
|
|
DMA_CHCTL(dma_periph,channelx) = ctl;
|
|
}
|
|
|
|
/*!
|
|
\brief configure transfer burst beats of memory
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] mbeat: transfer burst beats
|
|
\arg DMA_MEMORY_BURST_SINGLE: memory transfer single burst
|
|
\arg DMA_MEMORY_BURST_4_BEAT: memory transfer 4-beat burst
|
|
\arg DMA_MEMORY_BURST_8_BEAT: memory transfer 8-beat burst
|
|
\arg DMA_MEMORY_BURST_16_BEAT: memory transfer 16-beat burst
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_memory_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t mbeat)
|
|
{
|
|
uint32_t ctl;
|
|
/* acquire DMA_CHxCTL register */
|
|
ctl = DMA_CHCTL(dma_periph,channelx);
|
|
/* assign regiser */
|
|
ctl &= ~DMA_CHXCTL_MBURST;
|
|
ctl |= mbeat;
|
|
DMA_CHCTL(dma_periph,channelx) = ctl;
|
|
}
|
|
|
|
/*!
|
|
\brief configure transfer burst beats of peripheral
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] pbeat: transfer burst beats
|
|
\arg DMA_PERIPH_BURST_SINGLE: peripheral transfer single burst
|
|
\arg DMA_PERIPH_BURST_4_BEAT: peripheral transfer 4-beat burst
|
|
\arg DMA_PERIPH_BURST_8_BEAT: peripheral transfer 8-beat burst
|
|
\arg DMA_PERIPH_BURST_16_BEAT: peripheral transfer 16-beat burst
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_periph_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t pbeat)
|
|
{
|
|
uint32_t ctl;
|
|
/* acquire DMA_CHxCTL register */
|
|
ctl = DMA_CHCTL(dma_periph,channelx);
|
|
/* assign regiser */
|
|
ctl &= ~DMA_CHXCTL_PBURST;
|
|
ctl |= pbeat;
|
|
DMA_CHCTL(dma_periph,channelx) = ctl;
|
|
}
|
|
|
|
/*!
|
|
\brief configure transfer data size of memory
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] msize: transfer data size of memory
|
|
\arg DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit
|
|
\arg DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit
|
|
\arg DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_memory_width_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t msize)
|
|
{
|
|
uint32_t ctl;
|
|
/* acquire DMA_CHxCTL register */
|
|
ctl = DMA_CHCTL(dma_periph,channelx);
|
|
/* assign regiser */
|
|
ctl &= ~DMA_CHXCTL_MWIDTH;
|
|
ctl |= msize;
|
|
DMA_CHCTL(dma_periph,channelx) = ctl;
|
|
}
|
|
|
|
/*!
|
|
\brief configure transfer data size of peripheral
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] msize: transfer data size of peripheral
|
|
\arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit
|
|
\arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit
|
|
\arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_periph_width_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t psize)
|
|
{
|
|
uint32_t ctl;
|
|
/* acquire DMA_CHxCTL register */
|
|
ctl = DMA_CHCTL(dma_periph,channelx);
|
|
/* assign regiser */
|
|
ctl &= ~DMA_CHXCTL_PWIDTH;
|
|
ctl |= psize;
|
|
DMA_CHCTL(dma_periph,channelx) = ctl;
|
|
}
|
|
|
|
/*!
|
|
\brief configure memory address generation generation_algorithm
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] generation_algorithm: the address generation algorithm
|
|
\arg DMA_MEMORY_INCREASE_ENABLE: next address of memory is increasing address mode
|
|
\arg DMA_MEMORY_INCREASE_DISABLE: next address of memory is fixed address mode
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_memory_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm)
|
|
{
|
|
if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm){
|
|
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA;
|
|
}else{
|
|
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief configure peripheral address generation generation_algorithm
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] generation_algorithm: the address generation algorithm
|
|
\arg DMA_PERIPH_INCREASE_ENABLE: next address of peripheral is increasing address mode
|
|
\arg DMA_PERIPH_INCREASE_DISABLE: next address of peripheral is fixed address mode
|
|
\arg DMA_PERIPH_INCREASE_FIX: increasing steps of peripheral address is fixed
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_peripheral_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm)
|
|
{
|
|
if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm){
|
|
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA;
|
|
}else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm){
|
|
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA;
|
|
}else{
|
|
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA;
|
|
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief enable DMA circulation mode
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_circulation_enable(uint32_t dma_periph,dma_channel_enum channelx)
|
|
{
|
|
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN;
|
|
}
|
|
|
|
/*!
|
|
\brief disable DMA circulation mode
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_circulation_disable(uint32_t dma_periph,dma_channel_enum channelx)
|
|
{
|
|
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN;
|
|
}
|
|
|
|
/*!
|
|
\brief configure the direction of data transfer on the channel
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] direction: specify the direction of data transfer
|
|
\arg DMA_PERIPH_TO_MEMORY: read from peripheral and write to memory
|
|
\arg DMA_MEMORY_TO_PERIPH: read from memory and write to peripheral
|
|
\arg DMA_MEMORY_TO_MEMORY: read from memory and write to memory
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_transfer_direction_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t direction)
|
|
{
|
|
uint32_t ctl;
|
|
/* acquire DMA_CHxCTL register */
|
|
ctl = DMA_CHCTL(dma_periph,channelx);
|
|
/* assign regiser */
|
|
ctl &= ~DMA_CHXCTL_TM;
|
|
ctl |= direction;
|
|
|
|
DMA_CHCTL(dma_periph,channelx) = ctl;
|
|
}
|
|
|
|
/*!
|
|
\brief enable DMA channel
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_channel_enable(uint32_t dma_periph,dma_channel_enum channelx)
|
|
{
|
|
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CHEN;
|
|
}
|
|
|
|
/*!
|
|
\brief disable DMA channel
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_channel_disable(uint32_t dma_periph,dma_channel_enum channelx)
|
|
{
|
|
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN;
|
|
}
|
|
|
|
/*!
|
|
\brief DMA channel peripheral select
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] sub_periph: specify DMA channel peripheral
|
|
\arg DMA_SUBPERIx(x=0..7)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_channel_subperipheral_select(uint32_t dma_periph,dma_channel_enum channelx,dma_subperipheral_enum sub_periph)
|
|
{
|
|
uint32_t ctl;
|
|
/* acquire DMA_CHxCTL register */
|
|
ctl = DMA_CHCTL(dma_periph,channelx);
|
|
/* assign regiser */
|
|
ctl &= ~DMA_CHXCTL_PERIEN;
|
|
ctl |= ((uint32_t)sub_periph << CHXCTL_PERIEN_OFFSET);
|
|
|
|
DMA_CHCTL(dma_periph,channelx) = ctl;
|
|
}
|
|
|
|
/*!
|
|
\brief DMA switch buffer mode config
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] memory1_addr: memory1 base address
|
|
\param[in] memory_select: DMA_MEMORY_0 or DMA_MEMORY_1
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_switch_buffer_mode_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t memory1_addr,uint32_t memory_select)
|
|
{
|
|
/* configure memory1 base address */
|
|
DMA_CHM1ADDR(dma_periph,channelx) = memory1_addr;
|
|
|
|
if(DMA_MEMORY_0 == memory_select){
|
|
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MBS;
|
|
}else{
|
|
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MBS;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief DMA switch buffer mode enable
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] newvalue: ENABLE or DISABLE
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_switch_buffer_mode_enable(uint32_t dma_periph,dma_channel_enum channelx,ControlStatus newvalue)
|
|
{
|
|
if(ENABLE == newvalue){
|
|
/* switch buffer mode enable */
|
|
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_SBMEN;
|
|
}else{
|
|
/* switch buffer mode disable */
|
|
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_SBMEN;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief DMA using memory get
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[out] none
|
|
\retval the using memory
|
|
*/
|
|
uint32_t dma_using_memory_get(uint32_t dma_periph,dma_channel_enum channelx)
|
|
{
|
|
if((DMA_CHCTL(dma_periph,channelx)) & DMA_CHXCTL_MBS){
|
|
return DMA_MEMORY_1;
|
|
}else{
|
|
return DMA_MEMORY_0;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief DMA flow controller configure
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[in] controller: specify DMA flow controler
|
|
\arg DMA_FLOW_CONTROLLER_DMA: DMA is the flow controller
|
|
\arg DMA_FLOW_CONTROLLER_PERI: peripheral is the flow controller
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dma_flow_controller_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t controller)
|
|
{
|
|
if(DMA_FLOW_CONTROLLER_DMA == controller){
|
|
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_TFCS;
|
|
}else{
|
|
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_TFCS;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief DMA FIFO status get
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
|
\arg DMAx(x=0,1)
|
|
\param[in] channelx: specify which DMA channel
|
|
\arg DMA_CHx(x=0..7)
|
|
\param[out] none
|
|
\retval the using memory
|
|
*/
|
|
uint32_t dma_fifo_status_get(uint32_t dma_periph,dma_channel_enum channelx)
|
|
{
|
|
return (DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FCNT);
|
|
}
|