591 lines
19 KiB
C
591 lines
19 KiB
C
/*
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* Copyright (c) 2014, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#ifndef __HW_RNG_REGISTERS_H__
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#define __HW_RNG_REGISTERS_H__
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#include "regs.h"
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/*
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* MK64F12 RNG
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*
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* Random Number Generator Accelerator
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*
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* Registers defined in this header file:
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* - HW_RNG_CR - RNGA Control Register
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* - HW_RNG_SR - RNGA Status Register
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* - HW_RNG_ER - RNGA Entropy Register
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* - HW_RNG_OR - RNGA Output Register
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*
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* - hw_rng_t - Struct containing all module registers.
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*/
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//! @name Module base addresses
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//@{
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#ifndef REGS_RNG_BASE
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#define HW_RNG_INSTANCE_COUNT (1U) //!< Number of instances of the RNG module.
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#define REGS_RNG_BASE (0x40029000U) //!< Base address for RNG.
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_RNG_CR - RNGA Control Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_RNG_CR - RNGA Control Register (RW)
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*
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* Reset value: 0x00000000U
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*
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* Controls the operation of RNGA.
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*/
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typedef union _hw_rng_cr
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{
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uint32_t U;
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struct _hw_rng_cr_bitfields
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{
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uint32_t GO : 1; //!< [0] Go
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uint32_t HA : 1; //!< [1] High Assurance
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uint32_t INTM : 1; //!< [2] Interrupt Mask
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uint32_t CLRI : 1; //!< [3] Clear Interrupt
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uint32_t SLP : 1; //!< [4] Sleep
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uint32_t RESERVED0 : 27; //!< [31:5]
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} B;
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} hw_rng_cr_t;
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#endif
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/*!
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* @name Constants and macros for entire RNG_CR register
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*/
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//@{
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#define HW_RNG_CR_ADDR (REGS_RNG_BASE + 0x0U)
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#ifndef __LANGUAGE_ASM__
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#define HW_RNG_CR (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR)
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#define HW_RNG_CR_RD() (HW_RNG_CR.U)
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#define HW_RNG_CR_WR(v) (HW_RNG_CR.U = (v))
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#define HW_RNG_CR_SET(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() | (v)))
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#define HW_RNG_CR_CLR(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() & ~(v)))
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#define HW_RNG_CR_TOG(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual RNG_CR bitfields
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*/
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/*!
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* @name Register RNG_CR, field GO[0] (RW)
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*
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* Specifies whether random-data generation and loading (into OR[RANDOUT]) is
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* enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
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* OR[RANDOUT] with data.
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*
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* Values:
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* - 0 - Disabled
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* - 1 - Enabled
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*/
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//@{
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#define BP_RNG_CR_GO (0U) //!< Bit position for RNG_CR_GO.
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#define BM_RNG_CR_GO (0x00000001U) //!< Bit mask for RNG_CR_GO.
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#define BS_RNG_CR_GO (1U) //!< Bit field size in bits for RNG_CR_GO.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RNG_CR_GO field.
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#define BR_RNG_CR_GO (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO))
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#endif
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//! @brief Format value for bitfield RNG_CR_GO.
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#define BF_RNG_CR_GO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_GO), uint32_t) & BM_RNG_CR_GO)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the GO field to a new value.
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#define BW_RNG_CR_GO(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO) = (v))
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#endif
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//@}
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/*!
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* @name Register RNG_CR, field HA[1] (RW)
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*
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* Enables notification of security violations (via SR[SECV]). A security
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* violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
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* After enabling notification of security violations, you must reset RNGA to
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* disable them again.
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*
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* Values:
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* - 0 - Disabled
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* - 1 - Enabled
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*/
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//@{
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#define BP_RNG_CR_HA (1U) //!< Bit position for RNG_CR_HA.
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#define BM_RNG_CR_HA (0x00000002U) //!< Bit mask for RNG_CR_HA.
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#define BS_RNG_CR_HA (1U) //!< Bit field size in bits for RNG_CR_HA.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RNG_CR_HA field.
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#define BR_RNG_CR_HA (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA))
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#endif
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//! @brief Format value for bitfield RNG_CR_HA.
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#define BF_RNG_CR_HA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_HA), uint32_t) & BM_RNG_CR_HA)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the HA field to a new value.
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#define BW_RNG_CR_HA(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA) = (v))
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#endif
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//@}
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/*!
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* @name Register RNG_CR, field INTM[2] (RW)
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*
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* Masks the triggering of an error interrupt to the interrupt controller when
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* an OR underflow condition occurs. An OR underflow condition occurs when you
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* read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
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*
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* Values:
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* - 0 - Not masked
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* - 1 - Masked
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*/
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//@{
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#define BP_RNG_CR_INTM (2U) //!< Bit position for RNG_CR_INTM.
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#define BM_RNG_CR_INTM (0x00000004U) //!< Bit mask for RNG_CR_INTM.
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#define BS_RNG_CR_INTM (1U) //!< Bit field size in bits for RNG_CR_INTM.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RNG_CR_INTM field.
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#define BR_RNG_CR_INTM (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM))
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#endif
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//! @brief Format value for bitfield RNG_CR_INTM.
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#define BF_RNG_CR_INTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_INTM), uint32_t) & BM_RNG_CR_INTM)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the INTM field to a new value.
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#define BW_RNG_CR_INTM(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM) = (v))
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#endif
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//@}
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/*!
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* @name Register RNG_CR, field CLRI[3] (WORZ)
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*
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* Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
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*
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* Values:
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* - 0 - Do not clear the interrupt.
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* - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
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* the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
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*/
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//@{
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#define BP_RNG_CR_CLRI (3U) //!< Bit position for RNG_CR_CLRI.
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#define BM_RNG_CR_CLRI (0x00000008U) //!< Bit mask for RNG_CR_CLRI.
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#define BS_RNG_CR_CLRI (1U) //!< Bit field size in bits for RNG_CR_CLRI.
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//! @brief Format value for bitfield RNG_CR_CLRI.
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#define BF_RNG_CR_CLRI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_CLRI), uint32_t) & BM_RNG_CR_CLRI)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CLRI field to a new value.
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#define BW_RNG_CR_CLRI(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_CLRI) = (v))
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#endif
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//@}
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/*!
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* @name Register RNG_CR, field SLP[4] (RW)
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*
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* Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
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* mode by asserting the DOZE signal.
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*
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* Values:
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* - 0 - Normal mode
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* - 1 - Sleep (low-power) mode
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*/
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//@{
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#define BP_RNG_CR_SLP (4U) //!< Bit position for RNG_CR_SLP.
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#define BM_RNG_CR_SLP (0x00000010U) //!< Bit mask for RNG_CR_SLP.
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#define BS_RNG_CR_SLP (1U) //!< Bit field size in bits for RNG_CR_SLP.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RNG_CR_SLP field.
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#define BR_RNG_CR_SLP (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP))
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#endif
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//! @brief Format value for bitfield RNG_CR_SLP.
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#define BF_RNG_CR_SLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_SLP), uint32_t) & BM_RNG_CR_SLP)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the SLP field to a new value.
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#define BW_RNG_CR_SLP(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP) = (v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_RNG_SR - RNGA Status Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_RNG_SR - RNGA Status Register (RO)
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*
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* Reset value: 0x00010000U
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*
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* Indicates the status of RNGA. This register is read-only.
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*/
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typedef union _hw_rng_sr
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{
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uint32_t U;
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struct _hw_rng_sr_bitfields
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{
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uint32_t SECV : 1; //!< [0] Security Violation
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uint32_t LRS : 1; //!< [1] Last Read Status
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uint32_t ORU : 1; //!< [2] Output Register Underflow
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uint32_t ERRI : 1; //!< [3] Error Interrupt
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uint32_t SLP : 1; //!< [4] Sleep
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uint32_t RESERVED0 : 3; //!< [7:5]
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uint32_t OREG_LVL : 8; //!< [15:8] Output Register Level
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uint32_t OREG_SIZE : 8; //!< [23:16] Output Register Size
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uint32_t RESERVED1 : 8; //!< [31:24]
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} B;
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} hw_rng_sr_t;
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#endif
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/*!
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* @name Constants and macros for entire RNG_SR register
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*/
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//@{
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#define HW_RNG_SR_ADDR (REGS_RNG_BASE + 0x4U)
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#ifndef __LANGUAGE_ASM__
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#define HW_RNG_SR (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR)
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#define HW_RNG_SR_RD() (HW_RNG_SR.U)
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#endif
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//@}
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/*
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* Constants & macros for individual RNG_SR bitfields
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*/
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/*!
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* @name Register RNG_SR, field SECV[0] (RO)
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*
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* Used only when high assurance is enabled (CR[HA]). Indicates that a security
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* violation has occurred.This field is sticky. To clear SR[SECV], you must reset
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* RNGA.
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*
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* Values:
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* - 0 - No security violation
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* - 1 - Security violation
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*/
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//@{
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#define BP_RNG_SR_SECV (0U) //!< Bit position for RNG_SR_SECV.
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#define BM_RNG_SR_SECV (0x00000001U) //!< Bit mask for RNG_SR_SECV.
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#define BS_RNG_SR_SECV (1U) //!< Bit field size in bits for RNG_SR_SECV.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RNG_SR_SECV field.
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#define BR_RNG_SR_SECV (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SECV))
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#endif
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//@}
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/*!
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* @name Register RNG_SR, field LRS[1] (RO)
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*
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* Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
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* condition, regardless of whether the error interrupt is masked (CR[INTM]). An
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* OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
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* After you read this register, RNGA writes 0 to this field.
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*
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* Values:
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* - 0 - No underflow
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* - 1 - Underflow
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*/
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//@{
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#define BP_RNG_SR_LRS (1U) //!< Bit position for RNG_SR_LRS.
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#define BM_RNG_SR_LRS (0x00000002U) //!< Bit mask for RNG_SR_LRS.
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#define BS_RNG_SR_LRS (1U) //!< Bit field size in bits for RNG_SR_LRS.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RNG_SR_LRS field.
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#define BR_RNG_SR_LRS (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_LRS))
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#endif
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//@}
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/*!
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* @name Register RNG_SR, field ORU[2] (RO)
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*
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* Indicates whether an OR underflow condition has occurred since you last read
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* this register (SR) or RNGA was reset, regardless of whether the error
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* interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
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* OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
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* field.
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*
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* Values:
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* - 0 - No underflow
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* - 1 - Underflow
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*/
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//@{
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#define BP_RNG_SR_ORU (2U) //!< Bit position for RNG_SR_ORU.
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#define BM_RNG_SR_ORU (0x00000004U) //!< Bit mask for RNG_SR_ORU.
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#define BS_RNG_SR_ORU (1U) //!< Bit field size in bits for RNG_SR_ORU.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RNG_SR_ORU field.
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#define BR_RNG_SR_ORU (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ORU))
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#endif
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//@}
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/*!
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* @name Register RNG_SR, field ERRI[3] (RO)
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*
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* Indicates whether an OR underflow condition has occurred since you last
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* cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
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* error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
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* you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
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* indicator (via CR[CLRI]), RNGA writes 0 to this field.
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*
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* Values:
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* - 0 - No underflow
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* - 1 - Underflow
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*/
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//@{
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#define BP_RNG_SR_ERRI (3U) //!< Bit position for RNG_SR_ERRI.
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#define BM_RNG_SR_ERRI (0x00000008U) //!< Bit mask for RNG_SR_ERRI.
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#define BS_RNG_SR_ERRI (1U) //!< Bit field size in bits for RNG_SR_ERRI.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RNG_SR_ERRI field.
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#define BR_RNG_SR_ERRI (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ERRI))
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#endif
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//@}
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/*!
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* @name Register RNG_SR, field SLP[4] (RO)
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*
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* Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
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* mode by asserting the DOZE signal.
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*
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* Values:
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* - 0 - Normal mode
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* - 1 - Sleep (low-power) mode
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*/
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//@{
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#define BP_RNG_SR_SLP (4U) //!< Bit position for RNG_SR_SLP.
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#define BM_RNG_SR_SLP (0x00000010U) //!< Bit mask for RNG_SR_SLP.
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#define BS_RNG_SR_SLP (1U) //!< Bit field size in bits for RNG_SR_SLP.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RNG_SR_SLP field.
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#define BR_RNG_SR_SLP (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SLP))
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#endif
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//@}
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/*!
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* @name Register RNG_SR, field OREG_LVL[15:8] (RO)
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*
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* Indicates the number of random-data words that are in OR[RANDOUT], which
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* indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
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* is not 0, then the contents of a random number contained in OR[RANDOUT] are
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* returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
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*
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* Values:
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* - 0 - No words (empty)
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* - 1 - One word (valid)
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*/
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//@{
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#define BP_RNG_SR_OREG_LVL (8U) //!< Bit position for RNG_SR_OREG_LVL.
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#define BM_RNG_SR_OREG_LVL (0x0000FF00U) //!< Bit mask for RNG_SR_OREG_LVL.
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#define BS_RNG_SR_OREG_LVL (8U) //!< Bit field size in bits for RNG_SR_OREG_LVL.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RNG_SR_OREG_LVL field.
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#define BR_RNG_SR_OREG_LVL (HW_RNG_SR.B.OREG_LVL)
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#endif
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//@}
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/*!
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* @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
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*
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* Indicates the size of the Output (OR) register in terms of the number of
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* 32-bit random-data words it can hold.
|
|
*
|
|
* Values:
|
|
* - 1 - One word (this value is fixed)
|
|
*/
|
|
//@{
|
|
#define BP_RNG_SR_OREG_SIZE (16U) //!< Bit position for RNG_SR_OREG_SIZE.
|
|
#define BM_RNG_SR_OREG_SIZE (0x00FF0000U) //!< Bit mask for RNG_SR_OREG_SIZE.
|
|
#define BS_RNG_SR_OREG_SIZE (8U) //!< Bit field size in bits for RNG_SR_OREG_SIZE.
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Read current value of the RNG_SR_OREG_SIZE field.
|
|
#define BR_RNG_SR_OREG_SIZE (HW_RNG_SR.B.OREG_SIZE)
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_RNG_ER - RNGA Entropy Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
|
|
*
|
|
* Reset value: 0x00000000U
|
|
*
|
|
* Specifies an entropy value that RNGA uses in addition to its ring oscillators
|
|
* to seed its pseudorandom algorithm. This is a write-only register; reads
|
|
* return all zeros.
|
|
*/
|
|
typedef union _hw_rng_er
|
|
{
|
|
uint32_t U;
|
|
struct _hw_rng_er_bitfields
|
|
{
|
|
uint32_t EXT_ENT : 32; //!< [31:0] External Entropy
|
|
} B;
|
|
} hw_rng_er_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire RNG_ER register
|
|
*/
|
|
//@{
|
|
#define HW_RNG_ER_ADDR (REGS_RNG_BASE + 0x8U)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_RNG_ER (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR)
|
|
#define HW_RNG_ER_RD() (HW_RNG_ER.U)
|
|
#define HW_RNG_ER_WR(v) (HW_RNG_ER.U = (v))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* Constants & macros for individual RNG_ER bitfields
|
|
*/
|
|
|
|
/*!
|
|
* @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
|
|
*
|
|
* Specifies an entropy value that RNGA uses in addition to its ring oscillators
|
|
* to seed its pseudorandom algorithm.Specifying a value for this field is
|
|
* optional but recommended. You can write to this field at any time during operation.
|
|
*/
|
|
//@{
|
|
#define BP_RNG_ER_EXT_ENT (0U) //!< Bit position for RNG_ER_EXT_ENT.
|
|
#define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) //!< Bit mask for RNG_ER_EXT_ENT.
|
|
#define BS_RNG_ER_EXT_ENT (32U) //!< Bit field size in bits for RNG_ER_EXT_ENT.
|
|
|
|
//! @brief Format value for bitfield RNG_ER_EXT_ENT.
|
|
#define BF_RNG_ER_EXT_ENT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_ER_EXT_ENT), uint32_t) & BM_RNG_ER_EXT_ENT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the EXT_ENT field to a new value.
|
|
#define BW_RNG_ER_EXT_ENT(v) (HW_RNG_ER_WR(v))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_RNG_OR - RNGA Output Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_RNG_OR - RNGA Output Register (RO)
|
|
*
|
|
* Reset value: 0x00000000U
|
|
*
|
|
* Stores a random-data word generated by RNGA.
|
|
*/
|
|
typedef union _hw_rng_or
|
|
{
|
|
uint32_t U;
|
|
struct _hw_rng_or_bitfields
|
|
{
|
|
uint32_t RANDOUT : 32; //!< [31:0] Random Output
|
|
} B;
|
|
} hw_rng_or_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire RNG_OR register
|
|
*/
|
|
//@{
|
|
#define HW_RNG_OR_ADDR (REGS_RNG_BASE + 0xCU)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_RNG_OR (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR)
|
|
#define HW_RNG_OR_RD() (HW_RNG_OR.U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* Constants & macros for individual RNG_OR bitfields
|
|
*/
|
|
|
|
/*!
|
|
* @name Register RNG_OR, field RANDOUT[31:0] (RO)
|
|
*
|
|
* Stores a random-data word generated by RNGA. This is a read-only field.Before
|
|
* reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
|
|
*
|
|
* Values:
|
|
* - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
|
|
* 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
|
|
* interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
|
|
* request to the interrupt controller).
|
|
*/
|
|
//@{
|
|
#define BP_RNG_OR_RANDOUT (0U) //!< Bit position for RNG_OR_RANDOUT.
|
|
#define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) //!< Bit mask for RNG_OR_RANDOUT.
|
|
#define BS_RNG_OR_RANDOUT (32U) //!< Bit field size in bits for RNG_OR_RANDOUT.
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Read current value of the RNG_OR_RANDOUT field.
|
|
#define BR_RNG_OR_RANDOUT (HW_RNG_OR.U)
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// hw_rng_t - module struct
|
|
//-------------------------------------------------------------------------------------------
|
|
/*!
|
|
* @brief All RNG module registers.
|
|
*/
|
|
#ifndef __LANGUAGE_ASM__
|
|
#pragma pack(1)
|
|
typedef struct _hw_rng
|
|
{
|
|
__IO hw_rng_cr_t CR; //!< [0x0] RNGA Control Register
|
|
__I hw_rng_sr_t SR; //!< [0x4] RNGA Status Register
|
|
__O hw_rng_er_t ER; //!< [0x8] RNGA Entropy Register
|
|
__I hw_rng_or_t OR; //!< [0xC] RNGA Output Register
|
|
} hw_rng_t;
|
|
#pragma pack()
|
|
|
|
//! @brief Macro to access all RNG registers.
|
|
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
|
//! use the '&' operator, like <code>&HW_RNG</code>.
|
|
#define HW_RNG (*(hw_rng_t *) REGS_RNG_BASE)
|
|
#endif
|
|
|
|
#endif // __HW_RNG_REGISTERS_H__
|
|
// v22/130726/0.9
|
|
// EOF
|