zhangjun b80f83f360 modified: ../../libcpu/risc-v/e310/context_gcc.S ...

fix open timer intrrupt

2017-07-26 16:27:54 +08:00

..

applications

remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable();

2017-07-26 16:07:01 +08:00

drivers

modified: ../../libcpu/risc-v/e310/context_gcc.S

2017-07-26 16:27:54 +08:00

platform

remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable();

2017-07-26 16:07:01 +08:00

Makefile

remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable();

2017-07-26 16:07:01 +08:00

openocd.cfg

new bsp for risc-v

2017-07-16 20:37:03 +08:00

rtconfig.h

add context_gcc.s

2017-07-17 15:44:00 +08:00

rtconfig.py

remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable();

2017-07-26 16:07:01 +08:00

SConscript

new bsp for risc-v

2017-07-16 20:37:03 +08:00

SConstruct

new bsp for risc-v

2017-07-16 20:37:03 +08:00

sdram.ld

new bsp for risc-v

2017-07-16 20:37:03 +08:00

wrap_exit.c

new bsp for risc-v

2017-07-16 20:37:03 +08:00