285 lines
6.9 KiB
C
285 lines
6.9 KiB
C
/*
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* File : drv_uart.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2013-05-18 Bernard The first version for LPC40xx
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "board.h"
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#include "lpc_uart.h"
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#include "lpc_pinsel.h"
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struct lpc_uart
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{
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UART_ID_Type UART;
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IRQn_Type UART_IRQn;
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};
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static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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struct lpc_uart *uart;
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UART_CFG_Type UARTConfigStruct;
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UART_FIFO_CFG_Type UARTFIFOConfigStruct;
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RT_ASSERT(serial != RT_NULL);
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uart = (struct lpc_uart *)serial->parent.user_data;
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/* Initialize UART Configuration parameter structure to default state:
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* Baudrate = 115200 bps
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* 8 data bit
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* 1 Stop bit
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* None parity
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*/
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UART_ConfigStructInit(&UARTConfigStruct);
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UARTConfigStruct.Baud_rate = 115200;
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// Initialize UART0 peripheral with given to corresponding parameter
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UART_Init(uart->UART, &UARTConfigStruct);
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/* Initialize FIFOConfigStruct to default state:
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* - FIFO_DMAMode = DISABLE
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* - FIFO_Level = UART_FIFO_TRGLEV0
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* - FIFO_ResetRxBuf = ENABLE
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* - FIFO_ResetTxBuf = ENABLE
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* - FIFO_State = ENABLE
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*/
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UART_FIFOConfigStructInit(&UARTFIFOConfigStruct);
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// Initialize FIFO for UART0 peripheral
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UART_FIFOConfig(uart->UART, &UARTFIFOConfigStruct);
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UART_TxCmd(uart->UART, ENABLE);
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return RT_EOK;
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}
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static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg)
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{
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struct lpc_uart *uart;
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RT_ASSERT(serial != RT_NULL);
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uart = (struct lpc_uart *)serial->parent.user_data;
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switch (cmd)
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{
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case RT_DEVICE_CTRL_CLR_INT:
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/* disable rx irq */
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UART_IntConfig(uart->UART, UART_INTCFG_RBR, DISABLE);
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break;
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case RT_DEVICE_CTRL_SET_INT:
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/* enable rx irq */
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UART_IntConfig(uart->UART, UART_INTCFG_RBR, ENABLE);
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break;
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}
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return RT_EOK;
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}
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static int lpc_putc(struct rt_serial_device *serial, char c)
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{
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struct lpc_uart *uart;
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uart = (struct lpc_uart *)serial->parent.user_data;
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UART_Send(uart->UART, (uint8_t *)&c, 1, BLOCKING);
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return 1;
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}
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static int lpc_getc(struct rt_serial_device *serial)
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{
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uint8_t ch;
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struct lpc_uart *uart;
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uart = (struct lpc_uart *)serial->parent.user_data;
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if (UART_Receive(uart->UART, &ch, 1, NONE_BLOCKING) == 1)
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return (int) ch;
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return -1;
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}
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static const struct rt_uart_ops lpc_uart_ops =
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{
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lpc_configure,
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lpc_control,
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lpc_putc,
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lpc_getc,
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};
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#if defined(RT_USING_UART0)
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/* UART0 device driver structure */
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struct lpc_uart uart0 =
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{
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UART_0,
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UART0_IRQn,
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};
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struct rt_serial_device serial0;
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void UART0_IRQHandler(void)
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{
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struct lpc_uart *uart;
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uint32_t intsrc, tmp, tmp1;
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uart = &uart0;
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/* enter interrupt */
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rt_interrupt_enter();
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/* Determine the interrupt source */
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intsrc = UART_GetIntId(uart->UART);
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tmp = intsrc & UART_IIR_INTID_MASK;
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// Receive Line Status
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if (tmp == UART_IIR_INTID_RLS)
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{
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// Check line status
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tmp1 = UART_GetLineStatus(uart->UART);
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// Mask out the Receive Ready and Transmit Holding empty status
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tmp1 &= (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE \
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| UART_LSR_BI | UART_LSR_RXFE);
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// If any error exist
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if (tmp1)
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{
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//
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}
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}
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// Receive Data Available or Character time-out
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if ((tmp == UART_IIR_INTID_RDA) || (tmp == UART_IIR_INTID_CTI))
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{
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rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#if defined(RT_USING_UART2)
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/* UART2 device driver structure */
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struct lpc_uart uart2 =
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{
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UART_2,
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UART2_IRQn,
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};
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struct rt_serial_device serial2;
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void UART2_IRQHandler(void)
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{
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struct lpc_uart *uart;
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uint32_t intsrc, tmp, tmp1;
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uart = &uart2;
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/* enter interrupt */
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rt_interrupt_enter();
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/* Determine the interrupt source */
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intsrc = UART_GetIntId(uart->UART);
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tmp = intsrc & UART_IIR_INTID_MASK;
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// Receive Line Status
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if (tmp == UART_IIR_INTID_RLS)
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{
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// Check line status
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tmp1 = UART_GetLineStatus(uart->UART);
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// Mask out the Receive Ready and Transmit Holding empty status
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tmp1 &= (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE \
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| UART_LSR_BI | UART_LSR_RXFE);
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// If any error exist
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if (tmp1)
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{
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//
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}
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}
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// Receive Data Available or Character time-out
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if ((tmp == UART_IIR_INTID_RDA) || (tmp == UART_IIR_INTID_CTI))
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{
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rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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void rt_hw_uart_init(void)
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{
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struct lpc_uart *uart;
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struct serial_configure config;
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#ifdef RT_USING_UART0
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uart = &uart0;
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config.baud_rate = BAUD_RATE_115200;
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config.bit_order = BIT_ORDER_LSB;
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config.data_bits = DATA_BITS_8;
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config.parity = PARITY_NONE;
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config.stop_bits = STOP_BITS_1;
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config.invert = NRZ_NORMAL;
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config.bufsz = RT_SERIAL_RB_BUFSZ;
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serial0.ops = &lpc_uart_ops;
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serial0.config = config;
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/*
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* Initialize UART0 pin connect
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* P0.2: U0_TXD
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* P0.3: U0_RXD
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*/
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PINSEL_ConfigPin(0, 2, 1);
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PINSEL_ConfigPin(0, 3, 1);
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/* preemption = 1, sub-priority = 1 */
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NVIC_SetPriority(uart->UART_IRQn, ((0x01 << 3) | 0x01));
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/* Enable Interrupt for UART channel */
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NVIC_EnableIRQ(uart->UART_IRQn);
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/* register UART1 device */
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rt_hw_serial_register(&serial0, "uart0",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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uart);
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#endif
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#ifdef RT_USING_UART2
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uart = &uart2;
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config.baud_rate = BAUD_RATE_115200;
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config.bit_order = BIT_ORDER_LSB;
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config.data_bits = DATA_BITS_8;
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config.parity = PARITY_NONE;
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config.stop_bits = STOP_BITS_1;
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config.invert = NRZ_NORMAL;
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config.bufsz = RT_SERIAL_RB_BUFSZ;
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serial2.ops = &lpc_uart_ops;
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serial2.config = config;
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/*
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* Initialize UART2 pin connect
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* P2.8: U2_TXD
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* P0.11: U2_RXD
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*/
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PINSEL_ConfigPin(2, 8, 2);
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PINSEL_ConfigPin(0, 11, 1);
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/* preemption = 1, sub-priority = 1 */
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NVIC_SetPriority(uart->UART_IRQn, ((0x01 << 3) | 0x01));
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/* Enable Interrupt for UART channel */
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NVIC_EnableIRQ(uart->UART_IRQn);
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/* register UART1 device */
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rt_hw_serial_register(&serial2, "uart2",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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uart);
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#endif
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}
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