203 lines
8.0 KiB
C
203 lines
8.0 KiB
C
/************************************************************************/
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/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
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/* */
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/* The following software deliverable is intended for and must only be */
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/* used for reference and in an evaluation laboratory environment. */
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/* It is provided on an as-is basis without charge and is subject to */
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/* alterations. */
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/* It is the user's obligation to fully test the software in its */
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/* environment and to ensure proper functionality, qualification and */
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/* compliance with component specifications. */
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/* */
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/* In the event the software deliverable includes the use of open */
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/* source components, the provisions of the governing open source */
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/* license agreement shall apply with respect to such software */
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/* deliverable. */
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/* FSEU does not warrant that the deliverables do not infringe any */
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/* third party intellectual property right (IPR). In the event that */
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/* the deliverables infringe a third party IPR it is the sole */
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/* responsibility of the customer to obtain necessary licenses to */
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/* continue the usage of the deliverable. */
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/* */
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/* To the maximum extent permitted by applicable law FSEU disclaims all */
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/* warranties, whether express or implied, in particular, but not */
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/* limited to, warranties of merchantability and fitness for a */
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/* particular purpose for which the deliverable is not designated. */
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/* */
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/* To the maximum extent permitted by applicable law, FSEU's liability */
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/* is restricted to intentional misconduct and gross negligence. */
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/* FSEU is not liable for consequential damages. */
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/* */
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/* (V1.5) */
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/************************************************************************/
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#include "mcu.h"
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/** \file system_mb9bf50x.c
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**
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** FM3 system initialization functions
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** All adjustments can be done in belonging header file.
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**
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** History:
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** 2011-05-16 V1.0 MWi original version
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******************************************************************************/
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/**
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******************************************************************************
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** System Clock Frequency (Core Clock) Variable according CMSIS
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******************************************************************************/
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uint32_t SystemCoreClock = __HCLK;
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/**
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******************************************************************************
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** \brief Update the System Core Clock with current core Clock retrieved from
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** cpu registers.
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** \param none
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** \return none
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******************************************************************************/
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void SystemCoreClockUpdate (void) {
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uint32_t masterClk;
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uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance
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switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) {
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case 0: /* internal High-speed Cr osc. */
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masterClk = __CLKHC;
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break;
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case 1: /* external main osc. */
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masterClk = __CLKMO;
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break;
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case 2: /* PLL clock */
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// Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
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// violation:
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// "Unordered accesses to a volatile location"
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u32RegisterRead = (__CLKMO * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1));
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masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1));
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break;
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case 4: /* internal Low-speed CR osc. */
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masterClk = __CLKLC;
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break;
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case 5: /* external Sub osc. */
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masterClk = __CLKSO;
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break;
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default:
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masterClk = 0Ul;
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break;
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}
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switch (FM3_CRG->BSC_PSR & 0x07) {
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case 0:
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SystemCoreClock = masterClk;
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break;
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case 1:
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SystemCoreClock = masterClk / 2;
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break;
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case 2:
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SystemCoreClock = masterClk / 3;
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break;
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case 3:
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SystemCoreClock = masterClk / 4;
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break;
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case 4:
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SystemCoreClock = masterClk / 6;
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break;
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case 5:
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SystemCoreClock = masterClk /8;
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break;
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case 6:
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SystemCoreClock = masterClk /16;
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break;
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default:
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SystemCoreClock = 0Ul;
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break;
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}
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}
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/**
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******************************************************************************
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** \brief Setup the microcontroller system. Initialize the System and update
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** the SystemCoreClock variable.
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**
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** \param none
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** \return none
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******************************************************************************/
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void SystemInit (void) {
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static uint32_t u32IoRegisterRead; // Workaround variable for MISRA C rule conformance
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#if (HWWD_DISABLE) /* HW Watchdog Disable */
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FM3_HWWDT->WDG_LCK = 0x1ACCE551; /* HW Watchdog Unlock */
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FM3_HWWDT->WDG_LCK = 0xE5331AAE;
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FM3_HWWDT->WDG_CTL = 0; /* HW Watchdog stop */
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#endif
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#if (CLOCK_SETUP) /* Clock Setup */
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FM3_CRG->BSC_PSR = BSC_PSR_Val; /* set System Clock presacaler */
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FM3_CRG->APBC0_PSR = APBC0_PSR_Val; /* set APB0 presacaler */
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FM3_CRG->APBC1_PSR = APBC1_PSR_Val; /* set APB1 presacaler */
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FM3_CRG->APBC2_PSR = APBC2_PSR_Val; /* set APB2 presacaler */
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FM3_CRG->SWC_PSR = SWC_PSR_Val | (1UL << 7); /* set SW Watchdog presacaler */
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FM3_CRG->TTC_PSR = TTC_PSR_Val; /* set Trace Clock presacaler */
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FM3_CRG->CSW_TMR = CSW_TMR_Val; /* set oscillation stabilization wait time */
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if (SCM_CTL_Val & (1UL << 1)) { /* Main clock oscillator enabled ? */
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FM3_CRG->SCM_CTL |= (1UL << 1); /* enable main oscillator */
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while (!(FM3_CRG->SCM_STR & (1UL << 1))); /* wait for Main clock oscillation stable */
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}
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if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */
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FM3_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */
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while (!(FM3_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */
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}
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FM3_CRG->PSW_TMR = PSW_TMR_Val; /* set PLL stabilization wait time */
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FM3_CRG->PLL_CTL1 = PLL_CTL1_Val; /* set PLLM and PLLK */
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FM3_CRG->PLL_CTL2 = PLL_CTL2_Val; /* set PLLN */
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if (SCM_CTL_Val & (1UL << 4)) { /* PLL enabled ? */
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FM3_CRG->SCM_CTL |= (1UL << 4); /* enable PLL */
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while (!(FM3_CRG->SCM_STR & (1UL << 4))); /* wait for PLL stable */
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}
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FM3_CRG->SCM_CTL |= (SCM_CTL_Val & 0xE0); /* Set Master Clock switch */
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// Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
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// violations:
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// "Unordered reads and writes to or from same location" and
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// "Unordered accesses to a volatile location"
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do
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{
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u32IoRegisterRead = (FM3_CRG->SCM_CTL & 0xE0);
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}while ((FM3_CRG->SCM_STR & 0xE0) != u32IoRegisterRead);
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#endif // (CLOCK_SETUP)
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#if (CR_TRIM_SETUP)
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/* CR Trimming Data */
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if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) )
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{
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/* UnLock (MCR_FTRM) */
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FM3_CRTRIM->MCR_RLR = 0x1ACCE554;
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/* Set MCR_FTRM */
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FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM;
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/* Lock (MCR_FTRM) */
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FM3_CRTRIM->MCR_RLR = 0x00000000;
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}
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#endif // (CR_TRIM_SETUP)
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}
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