565 lines
17 KiB
C
565 lines
17 KiB
C
/*
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* File : syscall_write.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2017-10-10 Tanek first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include <drivers/mmcsd_core.h>
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#include <board.h>
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#include <fsl_usdhc.h>
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#include <fsl_gpio.h>
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#include <finsh.h>
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#define RT_USING_SDIO1
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#define RT_USING_SDIO2
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//#define DEBUG
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#ifdef DEBUG
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static int enable_log = 1;
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#define MMCSD_DGB(fmt, ...) \
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do \
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{ \
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if (enable_log) \
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{ \
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rt_kprintf(fmt, ##__VA_ARGS__); \
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} \
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} while (0)
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#else
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#define MMCSD_DGB(fmt, ...)
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#endif
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#define CACHE_LINESIZE (32)
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#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */
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#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */
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#define IMXRT_MAX_FREQ (25UL * 1000UL * 1000UL)
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#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */
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#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */
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#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */
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#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */
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#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */
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/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */
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#define USDHC_READ_WATERMARK_LEVEL (0x80U)
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#define USDHC_WRITE_WATERMARK_LEVEL (0x80U)
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/* DMA mode */
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#define USDHC_DMA_MODE kUSDHC_DmaModeAdma2
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/* Endian mode. */
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#define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle
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ALIGN(USDHC_ADMA2_ADDR_ALIGN) uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS] SECTION("NonCacheable");
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struct imxrt_mmcsd
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{
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struct rt_mmcsd_host *host;
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struct rt_mmcsd_req *req;
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struct rt_mmcsd_cmd *cmd;
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struct rt_timer timer;
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rt_uint32_t *buf;
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//USDHC_Type *base;
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usdhc_host_t usdhc_host;
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clock_div_t usdhc_div;
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clock_ip_name_t ip_clock;
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uint32_t *usdhc_adma2_table;
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};
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static void _mmcsd_gpio_init(struct imxrt_mmcsd *mmcsd)
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{
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gpio_pin_config_t sw_config;
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CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
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#ifdef RT_USING_SDIO1
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if (mmcsd->usdhc_host.base == USDHC1)
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{
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0);
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/* voltage select PIN */
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0);
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/* card detect PIN */
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_12_GPIO2_IO28, 0);
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/* power reset pin */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(1) | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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/*voltage select pin*/
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_12_GPIO2_IO28, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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sw_config.direction = kGPIO_DigitalOutput;
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sw_config.outputLogic = 0;
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sw_config.interruptMode = kGPIO_NoIntmode;
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GPIO_PinInit(GPIO1, 5U, &sw_config);
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GPIO_PinWrite(GPIO1, 5U, true);
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}
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else
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#endif
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#ifdef RT_USING_SDIO2
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if (mmcsd->usdhc_host.base == USDHC2)
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{
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// todo
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}
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#endif
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}
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static void SDMMCHOST_ErrorRecovery(USDHC_Type *base)
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{
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uint32_t status = 0U;
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/* get host present status */
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status = USDHC_GetPresentStatusFlags(base);
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/* check command inhibit status flag */
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if ((status & kUSDHC_CommandInhibitFlag) != 0U)
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{
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/* reset command line */
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USDHC_Reset(base, kUSDHC_ResetCommand, 1000U);
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}
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/* check data inhibit status flag */
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if ((status & kUSDHC_DataInhibitFlag) != 0U)
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{
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/* reset data line */
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USDHC_Reset(base, kUSDHC_ResetData, 1000U);
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}
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}
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static void _mmcsd_host_init(struct imxrt_mmcsd *mmcsd)
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{
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usdhc_host_t *usdhc_host = &mmcsd->usdhc_host;
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/* Initializes SDHC. */
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usdhc_host->config.dataTimeout = USDHC_DATA_TIMEOUT;
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usdhc_host->config.endianMode = USDHC_ENDIAN_MODE;
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usdhc_host->config.readWatermarkLevel = USDHC_READ_WATERMARK_LEVEL;
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usdhc_host->config.writeWatermarkLevel = USDHC_WRITE_WATERMARK_LEVEL;
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usdhc_host->config.readBurstLen = USDHC_READ_BURST_LEN;
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usdhc_host->config.writeBurstLen = USDHC_WRITE_BURST_LEN;
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USDHC_Init(usdhc_host->base, &(usdhc_host->config));
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}
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static void _mmcsd_clk_init(struct imxrt_mmcsd *mmcsd)
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{
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CLOCK_EnableClock(mmcsd->ip_clock);
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CLOCK_SetDiv(mmcsd->usdhc_div, 5U);
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}
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static void _mmcsd_isr_init(struct imxrt_mmcsd *mmcsd)
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{
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//NVIC_SetPriority(USDHC1_IRQn, 5U);
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}
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static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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{
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struct imxrt_mmcsd *mmcsd;
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struct rt_mmcsd_cmd *cmd;
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struct rt_mmcsd_data *data;
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status_t error;
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usdhc_adma_config_t dmaConfig;
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usdhc_transfer_t fsl_content = {0};
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usdhc_command_t fsl_command = {0};
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usdhc_data_t fsl_data = {0};
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rt_uint32_t *buf = NULL;
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RT_ASSERT(host != RT_NULL);
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RT_ASSERT(req != RT_NULL);
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mmcsd = (struct imxrt_mmcsd *)host->private_data;
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RT_ASSERT(mmcsd != RT_NULL);
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cmd = req->cmd;
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RT_ASSERT(cmd != RT_NULL);
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MMCSD_DGB("\tcmd->cmd_code: %02d, cmd->arg: %08x, cmd->flags: %08x --> ", cmd->cmd_code, cmd->arg, cmd->flags);
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data = cmd->data;
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memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t));
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/* config adma */
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dmaConfig.dmaMode = USDHC_DMA_MODE;
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dmaConfig.burstLen = kUSDHC_EnBurstLenForINCR;
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dmaConfig.admaTable = mmcsd->usdhc_adma2_table;
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dmaConfig.admaTableWords = USDHC_ADMA_TABLE_WORDS;
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fsl_command.index = cmd->cmd_code;
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fsl_command.argument = cmd->arg;
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if (cmd->cmd_code == STOP_TRANSMISSION)
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fsl_command.type = kCARD_CommandTypeAbort;
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else
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fsl_command.type = kCARD_CommandTypeNormal;
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switch (cmd->flags & RESP_MASK)
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{
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case RESP_NONE:
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fsl_command.responseType = kCARD_ResponseTypeNone;
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break;
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case RESP_R1:
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fsl_command.responseType = kCARD_ResponseTypeR1;
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break;
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case RESP_R1B:
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fsl_command.responseType = kCARD_ResponseTypeR1b;
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break;
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case RESP_R2:
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fsl_command.responseType = kCARD_ResponseTypeR2;
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break;
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case RESP_R3:
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fsl_command.responseType = kCARD_ResponseTypeR3;
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break;
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case RESP_R4:
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fsl_command.responseType = kCARD_ResponseTypeR4;
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break;
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case RESP_R6:
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fsl_command.responseType = kCARD_ResponseTypeR6;
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break;
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case RESP_R7:
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fsl_command.responseType = kCARD_ResponseTypeR7;
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break;
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case RESP_R5:
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fsl_command.responseType = kCARD_ResponseTypeR5;
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break;
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/*
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case RESP_R5B:
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fsl_command.responseType = kCARD_ResponseTypeR5b;
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break;
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*/
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default:
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RT_ASSERT(NULL);
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}
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// command type
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/*
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switch (cmd->flags & CMD_MASK)
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{
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case CMD_AC:
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break;
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case CMD_ADTC:
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break;
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case CMD_BC:
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break;
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case CMD_BCR:
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break;
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}
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*/
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fsl_command.flags = 0;
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//fsl_command.response
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//fsl_command.responseErrorFlags
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fsl_content.command = &fsl_command;
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if (data)
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{
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if (req->stop != NULL)
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fsl_data.enableAutoCommand12 = true;
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else
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fsl_data.enableAutoCommand12 = false;
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fsl_data.enableAutoCommand23 = false;
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fsl_data.enableIgnoreError = false;
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fsl_data.dataType = kUSDHC_TransferDataNormal; //todo : update data type
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fsl_data.blockSize = data->blksize;
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fsl_data.blockCount = data->blks;
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MMCSD_DGB(" blksize:%d, blks:%d ", fsl_data.blockSize, fsl_data.blockCount);
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if (((rt_uint32_t)data->buf & (CACHE_LINESIZE - 1)) || // align cache(32byte)
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((rt_uint32_t)data->buf > 0x00000000 && (rt_uint32_t)data->buf < 0x00080000) /*|| // ITCM
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((rt_uint32_t)data->buf >= 0x20000000 && (rt_uint32_t)data->buf < 0x20080000)*/) // DTCM
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{
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buf = rt_malloc_align(fsl_data.blockSize * fsl_data.blockCount, CACHE_LINESIZE);
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RT_ASSERT(buf != RT_NULL);
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MMCSD_DGB(" malloc buf: %p, data->buf:%p, %d ", buf, data->buf, fsl_data.blockSize * fsl_data.blockCount);
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}
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if ((cmd->cmd_code == WRITE_BLOCK) || (cmd->cmd_code == WRITE_MULTIPLE_BLOCK))
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{
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if (buf)
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{
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MMCSD_DGB(" write(data->buf to buf) ");
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rt_memcpy(buf, data->buf, fsl_data.blockSize * fsl_data.blockCount);
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fsl_data.txData = (uint32_t const *)buf;
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}
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else
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{
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fsl_data.txData = (uint32_t const *)data->buf;
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}
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fsl_data.rxData = NULL;
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}
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else
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{
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if (buf)
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{
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fsl_data.rxData = (uint32_t *)buf;
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}
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else
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{
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fsl_data.rxData = (uint32_t *)data->buf;
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}
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fsl_data.txData = NULL;
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}
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fsl_content.data = &fsl_data;
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}
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else
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{
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fsl_content.data = NULL;
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}
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error = USDHC_TransferBlocking(mmcsd->usdhc_host.base, &dmaConfig, &fsl_content);
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if (error == kStatus_Fail)
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{
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SDMMCHOST_ErrorRecovery(mmcsd->usdhc_host.base);
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MMCSD_DGB(" ***USDHC_TransferBlocking error: %d*** --> \n", error);
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cmd->err = -RT_ERROR;
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}
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if (buf)
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{
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if (fsl_data.rxData)
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{
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MMCSD_DGB("read copy buf to data->buf ");
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rt_memcpy(data->buf, buf, fsl_data.blockSize * fsl_data.blockCount);
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}
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rt_free_align(buf);
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}
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if ((cmd->flags & RESP_MASK) == RESP_R2)
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{
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cmd->resp[3] = fsl_command.response[0];
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cmd->resp[2] = fsl_command.response[1];
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cmd->resp[1] = fsl_command.response[2];
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cmd->resp[0] = fsl_command.response[3];
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MMCSD_DGB(" resp 0x%08X 0x%08X 0x%08X 0x%08X\n",
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cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
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}
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else
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{
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cmd->resp[0] = fsl_command.response[0];
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MMCSD_DGB(" resp 0x%08X\n", cmd->resp[0]);
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}
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mmcsd_req_complete(host);
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return;
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}
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static void _mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
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{
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struct imxrt_mmcsd *mmcsd;
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unsigned int usdhc_clk;
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unsigned int bus_width;
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uint32_t src_clk;
|
|
|
|
RT_ASSERT(host != RT_NULL);
|
|
RT_ASSERT(host->private_data != RT_NULL);
|
|
RT_ASSERT(io_cfg != RT_NULL);
|
|
|
|
mmcsd = (struct imxrt_mmcsd *)host->private_data;
|
|
usdhc_clk = io_cfg->clock;
|
|
bus_width = io_cfg->bus_width;
|
|
|
|
if (usdhc_clk > IMXRT_MAX_FREQ)
|
|
usdhc_clk = IMXRT_MAX_FREQ;
|
|
src_clk = (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(mmcsd->usdhc_div) + 1U));
|
|
|
|
MMCSD_DGB("\tsrc_clk: %d, usdhc_clk: %d, bus_width: %d\n", src_clk, usdhc_clk, bus_width);
|
|
|
|
if (usdhc_clk)
|
|
{
|
|
USDHC_SetSdClock(mmcsd->usdhc_host.base, src_clk, usdhc_clk);
|
|
//CLOCK_EnableClock(mmcsd->ip_clock);
|
|
|
|
/* Change bus width */
|
|
if (bus_width == MMCSD_BUS_WIDTH_8)
|
|
USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth8Bit);
|
|
else if (bus_width == MMCSD_BUS_WIDTH_4)
|
|
USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth4Bit);
|
|
else if (bus_width == MMCSD_BUS_WIDTH_1)
|
|
USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth1Bit);
|
|
else
|
|
RT_ASSERT(RT_NULL);
|
|
}
|
|
else
|
|
{
|
|
//CLOCK_DisableClock(mmcsd->ip_clock);
|
|
}
|
|
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
static void log_toggle(int en)
|
|
{
|
|
enable_log = en;
|
|
}
|
|
FINSH_FUNCTION_EXPORT(log_toggle, toglle log dumple);
|
|
#endif
|
|
|
|
//static rt_int32_t _mmc_get_card_status(struct rt_mmcsd_host *host)
|
|
//{
|
|
// MMCSD_DGB("%s, start\n", __func__);
|
|
// MMCSD_DGB("%s, end\n", __func__);
|
|
//
|
|
// return 0;
|
|
//}
|
|
//
|
|
//static void _mmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable)
|
|
//{
|
|
//
|
|
//}
|
|
|
|
static const struct rt_mmcsd_host_ops ops =
|
|
{
|
|
_mmc_request,
|
|
_mmc_set_iocfg,
|
|
RT_NULL,//_mmc_get_card_status,
|
|
RT_NULL,//_mmc_enable_sdio_irq,
|
|
};
|
|
|
|
rt_int32_t _imxrt_mci_init(void)
|
|
{
|
|
struct rt_mmcsd_host *host;
|
|
struct imxrt_mmcsd *mmcsd;
|
|
|
|
host = mmcsd_alloc_host();
|
|
if (!host)
|
|
{
|
|
return -RT_ERROR;
|
|
}
|
|
|
|
mmcsd = rt_malloc(sizeof(struct imxrt_mmcsd));
|
|
if (!mmcsd)
|
|
{
|
|
rt_kprintf("alloc mci failed\n");
|
|
goto err;
|
|
}
|
|
|
|
rt_memset(mmcsd, 0, sizeof(struct imxrt_mmcsd));
|
|
mmcsd->usdhc_host.base = USDHC1;
|
|
mmcsd->usdhc_div = kCLOCK_Usdhc1Div;
|
|
mmcsd->usdhc_adma2_table = g_usdhcAdma2Table;
|
|
|
|
host->ops = &ops;
|
|
host->freq_min = 375000;
|
|
host->freq_max = 25000000;
|
|
host->valid_ocr = VDD_32_33 | VDD_33_34;
|
|
host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \
|
|
MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
|
|
host->max_seg_size = 65535;
|
|
host->max_dma_segs = 2;
|
|
host->max_blk_size = 512;
|
|
host->max_blk_count = 4096;
|
|
|
|
mmcsd->host = host;
|
|
|
|
_mmcsd_clk_init(mmcsd);
|
|
_mmcsd_isr_init(mmcsd);
|
|
_mmcsd_gpio_init(mmcsd);
|
|
_mmcsd_host_init(mmcsd);
|
|
|
|
host->private_data = mmcsd;
|
|
|
|
mmcsd_change(host);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
mmcsd_free_host(host);
|
|
|
|
return -RT_ENOMEM;
|
|
}
|
|
|
|
int imxrt_mci_init(void)
|
|
{
|
|
/* initilize sd card */
|
|
_imxrt_mci_init();
|
|
|
|
return 0;
|
|
}
|
|
INIT_DEVICE_EXPORT(imxrt_mci_init);
|