1713 lines
57 KiB
C
1713 lines
57 KiB
C
/*
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* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_lpuart.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* LPUART transfer state. */
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enum _lpuart_transfer_states
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{
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kLPUART_TxIdle, /*!< TX idle. */
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kLPUART_TxBusy, /*!< TX busy. */
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kLPUART_RxIdle, /*!< RX idle. */
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kLPUART_RxBusy /*!< RX busy. */
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};
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/* Typedef for interrupt handler. */
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typedef void (*lpuart_isr_t)(LPUART_Type *base, lpuart_handle_t *handle);
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get the LPUART instance from peripheral base address.
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*
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* @param base LPUART peripheral base address.
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* @return LPUART instance.
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*/
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uint32_t LPUART_GetInstance(LPUART_Type *base);
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/*!
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* @brief Check whether the RX ring buffer is full.
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*
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* @userData handle LPUART handle pointer.
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* @retval true RX ring buffer is full.
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* @retval false RX ring buffer is not full.
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*/
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static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle);
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/*!
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* @brief Write to TX register using non-blocking method.
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*
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* This function writes data to the TX register directly, upper layer must make
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* sure the TX register is empty or TX FIFO has empty room before calling this function.
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*
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* @note This function does not check whether all the data has been sent out to bus,
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* so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is
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* finished.
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*
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* @param base LPUART peripheral base address.
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* @param data Start addresss of the data to write.
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* @param length Size of the buffer to be sent.
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*/
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static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
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/*!
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* @brief Read RX register using non-blocking method.
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*
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* This function reads data from the TX register directly, upper layer must make
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* sure the RX register is full or TX FIFO has data before calling this function.
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*
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* @param base LPUART peripheral base address.
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* @param data Start addresss of the buffer to store the received data.
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* @param length Size of the buffer.
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*/
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static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* Array of LPUART peripheral base address. */
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static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS;
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/* Array of LPUART handle. */
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static lpuart_handle_t *s_lpuartHandle[ARRAY_SIZE(s_lpuartBases)];
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/* Array of LPUART IRQ number. */
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#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
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static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS;
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static const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS;
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#else
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static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS;
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#endif
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Array of LPUART clock name. */
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static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS;
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#if defined(LPUART_PERIPH_CLOCKS)
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/* Array of LPUART functional clock name. */
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static const clock_ip_name_t s_lpuartPeriphClocks[] = LPUART_PERIPH_CLOCKS;
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#endif
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* LPUART ISR for transactional APIs. */
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static lpuart_isr_t s_lpuartIsr;
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/*******************************************************************************
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* Code
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******************************************************************************/
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uint32_t LPUART_GetInstance(LPUART_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_lpuartBases); instance++)
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{
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if (s_lpuartBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_lpuartBases));
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return instance;
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}
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size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
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{
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assert(handle);
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size_t size;
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if (handle->rxRingBufferTail > handle->rxRingBufferHead)
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{
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size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
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}
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else
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{
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size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
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}
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return size;
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}
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static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle)
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{
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assert(handle);
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bool full;
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if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U))
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{
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full = true;
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}
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else
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{
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full = false;
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}
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return full;
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}
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static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
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{
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assert(data);
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size_t i;
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/* The Non Blocking write data API assume user have ensured there is enough space in
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peripheral to write. */
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for (i = 0; i < length; i++)
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{
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base->DATA = data[i];
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}
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}
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static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
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{
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assert(data);
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size_t i;
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#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
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uint32_t ctrl = base->CTRL;
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bool isSevenDataBits =
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((ctrl & LPUART_CTRL_M7_MASK) ||
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((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
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#endif
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/* The Non Blocking read data API assume user have ensured there is enough space in
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peripheral to write. */
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for (i = 0; i < length; i++)
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{
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#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
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if (isSevenDataBits)
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{
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data[i] = (base->DATA & 0x7F);
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}
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else
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{
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data[i] = base->DATA;
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}
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#else
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data[i] = base->DATA;
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#endif
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}
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}
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status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
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{
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assert(config);
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assert(config->baudRate_Bps);
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#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
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assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark);
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assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
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#endif
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uint32_t temp;
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uint16_t sbr, sbrTemp;
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uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
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/* This LPUART instantiation uses a slightly different baud rate calculation
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* The idea is to use the best OSR (over-sampling rate) possible
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* Note, OSR is typically hard-set to 16 in other LPUART instantiations
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* loop to find the best OSR value possible, one that generates minimum baudDiff
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* iterate through the rest of the supported values of OSR */
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baudDiff = config->baudRate_Bps;
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osr = 0;
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sbr = 0;
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for (osrTemp = 4; osrTemp <= 32; osrTemp++)
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{
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/* calculate the temporary sbr value */
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sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp));
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/*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
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if (sbrTemp == 0)
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{
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sbrTemp = 1;
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}
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/* Calculate the baud rate based on the temporary OSR and SBR values */
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calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
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tempDiff = calculatedBaud - config->baudRate_Bps;
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/* Select the better value between srb and (sbr + 1) */
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if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
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{
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tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
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sbrTemp++;
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}
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if (tempDiff <= baudDiff)
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{
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baudDiff = tempDiff;
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osr = osrTemp; /* update and store the best OSR value calculated */
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sbr = sbrTemp; /* update store the best SBR value calculated */
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}
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}
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/* Check to see if actual baud rate is within 3% of desired baud rate
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* based on the best calculate OSR value */
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if (baudDiff > ((config->baudRate_Bps / 100) * 3))
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{
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/* Unacceptable baud rate difference of more than 3%*/
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return kStatus_LPUART_BaudrateNotSupport;
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}
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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uint32_t instance = LPUART_GetInstance(base);
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/* Enable lpuart clock */
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CLOCK_EnableClock(s_lpuartClock[instance]);
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#if defined(LPUART_PERIPH_CLOCKS)
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CLOCK_EnableClock(s_lpuartPeriphClocks[instance]);
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#endif
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
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/*Reset all internal logic and registers, except the Global Register */
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LPUART_SoftwareReset(base);
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#else
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/* Disable LPUART TX RX before setting. */
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base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
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#endif
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temp = base->BAUD;
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/* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
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* If so, then "BOTHEDGE" sampling must be turned on */
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if ((osr > 3) && (osr < 8))
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{
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temp |= LPUART_BAUD_BOTHEDGE_MASK;
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}
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/* program the osr value (bit value is one less than actual value) */
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temp &= ~LPUART_BAUD_OSR_MASK;
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temp |= LPUART_BAUD_OSR(osr - 1);
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/* write the sbr value to the BAUD registers */
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temp &= ~LPUART_BAUD_SBR_MASK;
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base->BAUD = temp | LPUART_BAUD_SBR(sbr);
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/* Set bit count and parity mode. */
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base->BAUD &= ~LPUART_BAUD_M10_MASK;
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temp = base->CTRL &
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~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
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LPUART_CTRL_IDLECFG_MASK);
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temp |=
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(uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | LPUART_CTRL_ILT(config->rxIdleType);
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#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
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if (kLPUART_SevenDataBits == config->dataBitsCount)
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{
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if (kLPUART_ParityDisabled != config->parityMode)
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{
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temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */
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}
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else
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{
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temp |= LPUART_CTRL_M7_MASK;
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}
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}
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else
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#endif
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{
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if (kLPUART_ParityDisabled != config->parityMode)
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{
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temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */
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}
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}
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base->CTRL = temp;
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#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
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/* set stop bit per char */
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temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK;
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base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount);
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#endif
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#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
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/* Set tx/rx WATER watermark
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Note:
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Take care of the RX FIFO, RX interrupt request only assert when received bytes
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equal or more than RX water mark, there is potential issue if RX water
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mark larger than 1.
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For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
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5 bytes are received. the last byte will be saved in FIFO but not trigger
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RX interrupt because the water mark is 2.
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*/
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base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark);
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/* Enable tx/rx FIFO */
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base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK);
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/* Flush FIFO */
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base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK);
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#endif
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/* Clear all status flags */
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temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
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LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
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#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
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temp |= LPUART_STAT_LBKDIF_MASK;
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#endif
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#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
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temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
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#endif
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#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
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/* Set the CTS configuration/TX CTS source. */
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base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource);
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if (config->enableRxRTS)
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{
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/* Enable the receiver RTS(request-to-send) function. */
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base->MODIR |= LPUART_MODIR_RXRTSE_MASK;
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}
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if (config->enableTxCTS)
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{
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/* Enable the CTS(clear-to-send) function. */
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base->MODIR |= LPUART_MODIR_TXCTSE_MASK;
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}
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#endif
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/* Set data bits order. */
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if (config->isMsb)
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{
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temp |= LPUART_STAT_MSBF_MASK;
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}
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else
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{
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temp &= ~LPUART_STAT_MSBF_MASK;
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}
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base->STAT |= temp;
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/* Enable TX/RX base on configure structure. */
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temp = base->CTRL;
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if (config->enableTx)
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{
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temp |= LPUART_CTRL_TE_MASK;
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}
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if (config->enableRx)
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{
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temp |= LPUART_CTRL_RE_MASK;
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}
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base->CTRL = temp;
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return kStatus_Success;
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}
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void LPUART_Deinit(LPUART_Type *base)
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{
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uint32_t temp;
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#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
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/* Wait tx FIFO send out*/
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while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT))
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{
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}
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#endif
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/* Wait last char shoft out */
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while (0 == (base->STAT & LPUART_STAT_TC_MASK))
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{
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}
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/* Clear all status flags */
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temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
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LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
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#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
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temp |= LPUART_STAT_LBKDIF_MASK;
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#endif
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#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
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temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
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#endif
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base->STAT |= temp;
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/* Disable the module. */
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base->CTRL = 0;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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uint32_t instance = LPUART_GetInstance(base);
|
|
|
|
/* Disable lpuart clock */
|
|
CLOCK_DisableClock(s_lpuartClock[instance]);
|
|
|
|
#if defined(LPUART_PERIPH_CLOCKS)
|
|
CLOCK_DisableClock(s_lpuartPeriphClocks[instance]);
|
|
#endif
|
|
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
}
|
|
|
|
void LPUART_GetDefaultConfig(lpuart_config_t *config)
|
|
{
|
|
assert(config);
|
|
|
|
config->baudRate_Bps = 115200U;
|
|
config->parityMode = kLPUART_ParityDisabled;
|
|
config->dataBitsCount = kLPUART_EightDataBits;
|
|
config->isMsb = false;
|
|
#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
|
|
config->stopBitCount = kLPUART_OneStopBit;
|
|
#endif
|
|
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
|
config->txFifoWatermark = 0;
|
|
config->rxFifoWatermark = 0;
|
|
#endif
|
|
#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
|
|
config->enableRxRTS = false;
|
|
config->enableTxCTS = false;
|
|
config->txCtsConfig = kLPUART_CtsSampleAtStart;
|
|
config->txCtsSource = kLPUART_CtsSourcePin;
|
|
#endif
|
|
config->rxIdleType = kLPUART_IdleTypeStartBit;
|
|
config->rxIdleConfig = kLPUART_IdleCharacter1;
|
|
config->enableTx = false;
|
|
config->enableRx = false;
|
|
}
|
|
|
|
status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
|
|
{
|
|
assert(baudRate_Bps);
|
|
|
|
uint32_t temp, oldCtrl;
|
|
uint16_t sbr, sbrTemp;
|
|
uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
|
|
|
|
/* This LPUART instantiation uses a slightly different baud rate calculation
|
|
* The idea is to use the best OSR (over-sampling rate) possible
|
|
* Note, OSR is typically hard-set to 16 in other LPUART instantiations
|
|
* loop to find the best OSR value possible, one that generates minimum baudDiff
|
|
* iterate through the rest of the supported values of OSR */
|
|
|
|
baudDiff = baudRate_Bps;
|
|
osr = 0;
|
|
sbr = 0;
|
|
for (osrTemp = 4; osrTemp <= 32; osrTemp++)
|
|
{
|
|
/* calculate the temporary sbr value */
|
|
sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp));
|
|
/*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
|
|
if (sbrTemp == 0)
|
|
{
|
|
sbrTemp = 1;
|
|
}
|
|
/* Calculate the baud rate based on the temporary OSR and SBR values */
|
|
calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
|
|
|
|
tempDiff = calculatedBaud - baudRate_Bps;
|
|
|
|
/* Select the better value between srb and (sbr + 1) */
|
|
if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
|
|
{
|
|
tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
|
|
sbrTemp++;
|
|
}
|
|
|
|
if (tempDiff <= baudDiff)
|
|
{
|
|
baudDiff = tempDiff;
|
|
osr = osrTemp; /* update and store the best OSR value calculated */
|
|
sbr = sbrTemp; /* update store the best SBR value calculated */
|
|
}
|
|
}
|
|
|
|
/* Check to see if actual baud rate is within 3% of desired baud rate
|
|
* based on the best calculate OSR value */
|
|
if (baudDiff < ((baudRate_Bps / 100) * 3))
|
|
{
|
|
/* Store CTRL before disable Tx and Rx */
|
|
oldCtrl = base->CTRL;
|
|
|
|
/* Disable LPUART TX RX before setting. */
|
|
base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
|
|
|
|
temp = base->BAUD;
|
|
|
|
/* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
|
|
* If so, then "BOTHEDGE" sampling must be turned on */
|
|
if ((osr > 3) && (osr < 8))
|
|
{
|
|
temp |= LPUART_BAUD_BOTHEDGE_MASK;
|
|
}
|
|
|
|
/* program the osr value (bit value is one less than actual value) */
|
|
temp &= ~LPUART_BAUD_OSR_MASK;
|
|
temp |= LPUART_BAUD_OSR(osr - 1);
|
|
|
|
/* write the sbr value to the BAUD registers */
|
|
temp &= ~LPUART_BAUD_SBR_MASK;
|
|
base->BAUD = temp | LPUART_BAUD_SBR(sbr);
|
|
|
|
/* Restore CTRL. */
|
|
base->CTRL = oldCtrl;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
else
|
|
{
|
|
/* Unacceptable baud rate difference of more than 3%*/
|
|
return kStatus_LPUART_BaudrateNotSupport;
|
|
}
|
|
}
|
|
|
|
void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
|
|
{
|
|
base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
|
|
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
|
base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
|
|
((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
|
|
#endif
|
|
mask &= 0xFFFFFF00U;
|
|
base->CTRL |= mask;
|
|
}
|
|
|
|
void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
|
|
{
|
|
base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
|
|
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
|
base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
|
|
~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
|
|
#endif
|
|
mask &= 0xFFFFFF00U;
|
|
base->CTRL &= ~mask;
|
|
}
|
|
|
|
uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)
|
|
{
|
|
uint32_t temp;
|
|
temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8;
|
|
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
|
temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8;
|
|
#endif
|
|
temp |= (base->CTRL & 0xFF0C000);
|
|
|
|
return temp;
|
|
}
|
|
|
|
uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
|
|
{
|
|
uint32_t temp;
|
|
temp = base->STAT;
|
|
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
|
temp |= (base->FIFO &
|
|
(LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >>
|
|
16;
|
|
#endif
|
|
return temp;
|
|
}
|
|
|
|
status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
|
|
{
|
|
uint32_t temp;
|
|
status_t status;
|
|
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
|
temp = (uint32_t)base->FIFO;
|
|
temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK));
|
|
temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
|
|
base->FIFO = temp;
|
|
#endif
|
|
temp = (uint32_t)base->STAT;
|
|
#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
|
|
temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK));
|
|
temp |= mask & LPUART_STAT_LBKDIF_MASK;
|
|
#endif
|
|
temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
|
|
LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK));
|
|
temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
|
|
LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
|
|
#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
|
|
temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK));
|
|
temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK);
|
|
#endif
|
|
base->STAT = temp;
|
|
/* If some flags still pending. */
|
|
if (mask & LPUART_GetStatusFlags(base))
|
|
{
|
|
/* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag,
|
|
kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag,
|
|
kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
|
|
kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */
|
|
status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */
|
|
}
|
|
else
|
|
{
|
|
status = kStatus_Success;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
|
|
{
|
|
assert(data);
|
|
|
|
/* This API can only ensure that the data is written into the data buffer but can't
|
|
ensure all data in the data buffer are sent into the transmit shift buffer. */
|
|
while (length--)
|
|
{
|
|
while (!(base->STAT & LPUART_STAT_TDRE_MASK))
|
|
{
|
|
}
|
|
base->DATA = *(data++);
|
|
}
|
|
}
|
|
|
|
status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
|
|
{
|
|
assert(data);
|
|
|
|
uint32_t statusFlag;
|
|
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
|
|
uint32_t ctrl = base->CTRL;
|
|
bool isSevenDataBits =
|
|
((ctrl & LPUART_CTRL_M7_MASK) ||
|
|
((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
|
|
#endif
|
|
|
|
while (length--)
|
|
{
|
|
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
|
while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
|
|
#else
|
|
while (!(base->STAT & LPUART_STAT_RDRF_MASK))
|
|
#endif
|
|
{
|
|
statusFlag = LPUART_GetStatusFlags(base);
|
|
|
|
if (statusFlag & kLPUART_RxOverrunFlag)
|
|
{
|
|
LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag);
|
|
return kStatus_LPUART_RxHardwareOverrun;
|
|
}
|
|
|
|
if (statusFlag & kLPUART_NoiseErrorFlag)
|
|
{
|
|
LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag);
|
|
return kStatus_LPUART_NoiseError;
|
|
}
|
|
|
|
if (statusFlag & kLPUART_FramingErrorFlag)
|
|
{
|
|
LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag);
|
|
return kStatus_LPUART_FramingError;
|
|
}
|
|
|
|
if (statusFlag & kLPUART_ParityErrorFlag)
|
|
{
|
|
LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag);
|
|
return kStatus_LPUART_ParityError;
|
|
}
|
|
}
|
|
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
|
|
if (isSevenDataBits)
|
|
{
|
|
*(data++) = (base->DATA & 0x7F);
|
|
}
|
|
else
|
|
{
|
|
*(data++) = base->DATA;
|
|
}
|
|
#else
|
|
*(data++) = base->DATA;
|
|
#endif
|
|
}
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void LPUART_TransferCreateHandle(LPUART_Type *base,
|
|
lpuart_handle_t *handle,
|
|
lpuart_transfer_callback_t callback,
|
|
void *userData)
|
|
{
|
|
assert(handle);
|
|
|
|
uint32_t instance;
|
|
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
|
|
uint32_t ctrl = base->CTRL;
|
|
bool isSevenDataBits =
|
|
((ctrl & LPUART_CTRL_M7_MASK) ||
|
|
((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
|
|
#endif
|
|
|
|
/* Zero the handle. */
|
|
memset(handle, 0, sizeof(lpuart_handle_t));
|
|
|
|
/* Set the TX/RX state. */
|
|
handle->rxState = kLPUART_RxIdle;
|
|
handle->txState = kLPUART_TxIdle;
|
|
|
|
/* Set the callback and user data. */
|
|
handle->callback = callback;
|
|
handle->userData = userData;
|
|
|
|
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
|
|
/* Initial seven data bits flag */
|
|
handle->isSevenDataBits = isSevenDataBits;
|
|
#endif
|
|
|
|
/* Get instance from peripheral base address. */
|
|
instance = LPUART_GetInstance(base);
|
|
|
|
/* Save the handle in global variables to support the double weak mechanism. */
|
|
s_lpuartHandle[instance] = handle;
|
|
|
|
s_lpuartIsr = LPUART_TransferHandleIRQ;
|
|
|
|
/* Enable interrupt in NVIC. */
|
|
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
|
|
EnableIRQ(s_lpuartRxIRQ[instance]);
|
|
EnableIRQ(s_lpuartTxIRQ[instance]);
|
|
#else
|
|
EnableIRQ(s_lpuartIRQ[instance]);
|
|
#endif
|
|
}
|
|
|
|
void LPUART_TransferStartRingBuffer(LPUART_Type *base,
|
|
lpuart_handle_t *handle,
|
|
uint8_t *ringBuffer,
|
|
size_t ringBufferSize)
|
|
{
|
|
assert(handle);
|
|
assert(ringBuffer);
|
|
|
|
/* Setup the ring buffer address */
|
|
handle->rxRingBuffer = ringBuffer;
|
|
handle->rxRingBufferSize = ringBufferSize;
|
|
handle->rxRingBufferHead = 0U;
|
|
handle->rxRingBufferTail = 0U;
|
|
|
|
/* Enable the interrupt to accept the data when user need the ring buffer. */
|
|
LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
|
|
}
|
|
|
|
void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
if (handle->rxState == kLPUART_RxIdle)
|
|
{
|
|
LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
|
|
}
|
|
|
|
handle->rxRingBuffer = NULL;
|
|
handle->rxRingBufferSize = 0U;
|
|
handle->rxRingBufferHead = 0U;
|
|
handle->rxRingBufferTail = 0U;
|
|
}
|
|
|
|
status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)
|
|
{
|
|
assert(handle);
|
|
assert(xfer);
|
|
assert(xfer->data);
|
|
assert(xfer->dataSize);
|
|
|
|
status_t status;
|
|
|
|
/* Return error if current TX busy. */
|
|
if (kLPUART_TxBusy == handle->txState)
|
|
{
|
|
status = kStatus_LPUART_TxBusy;
|
|
}
|
|
else
|
|
{
|
|
handle->txData = xfer->data;
|
|
handle->txDataSize = xfer->dataSize;
|
|
handle->txDataSizeAll = xfer->dataSize;
|
|
handle->txState = kLPUART_TxBusy;
|
|
|
|
/* Enable transmiter interrupt. */
|
|
LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable);
|
|
|
|
status = kStatus_Success;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable);
|
|
|
|
handle->txDataSize = 0;
|
|
handle->txState = kLPUART_TxIdle;
|
|
}
|
|
|
|
status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
|
|
{
|
|
assert(handle);
|
|
assert(count);
|
|
|
|
if (kLPUART_TxIdle == handle->txState)
|
|
{
|
|
return kStatus_NoTransferInProgress;
|
|
}
|
|
|
|
*count = handle->txDataSizeAll - handle->txDataSize;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
|
|
lpuart_handle_t *handle,
|
|
lpuart_transfer_t *xfer,
|
|
size_t *receivedBytes)
|
|
{
|
|
assert(handle);
|
|
assert(xfer);
|
|
assert(xfer->data);
|
|
assert(xfer->dataSize);
|
|
|
|
uint32_t i;
|
|
status_t status;
|
|
/* How many bytes to copy from ring buffer to user memory. */
|
|
size_t bytesToCopy = 0U;
|
|
/* How many bytes to receive. */
|
|
size_t bytesToReceive;
|
|
/* How many bytes currently have received. */
|
|
size_t bytesCurrentReceived;
|
|
|
|
/* How to get data:
|
|
1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
|
|
to lpuart handle, enable interrupt to store received data to xfer->data. When
|
|
all data received, trigger callback.
|
|
2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
|
|
If there are enough data in ring buffer, copy them to xfer->data and return.
|
|
If there are not enough data in ring buffer, copy all of them to xfer->data,
|
|
save the xfer->data remained empty space to lpuart handle, receive data
|
|
to this empty space and trigger callback when finished. */
|
|
|
|
if (kLPUART_RxBusy == handle->rxState)
|
|
{
|
|
status = kStatus_LPUART_RxBusy;
|
|
}
|
|
else
|
|
{
|
|
bytesToReceive = xfer->dataSize;
|
|
bytesCurrentReceived = 0;
|
|
|
|
/* If RX ring buffer is used. */
|
|
if (handle->rxRingBuffer)
|
|
{
|
|
/* Disable LPUART RX IRQ, protect ring buffer. */
|
|
LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
|
|
|
|
/* How many bytes in RX ring buffer currently. */
|
|
bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle);
|
|
|
|
if (bytesToCopy)
|
|
{
|
|
bytesToCopy = MIN(bytesToReceive, bytesToCopy);
|
|
|
|
bytesToReceive -= bytesToCopy;
|
|
|
|
/* Copy data from ring buffer to user memory. */
|
|
for (i = 0U; i < bytesToCopy; i++)
|
|
{
|
|
xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
|
|
|
|
/* Wrap to 0. Not use modulo (%) because it might be large and slow. */
|
|
if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
|
|
{
|
|
handle->rxRingBufferTail = 0U;
|
|
}
|
|
else
|
|
{
|
|
handle->rxRingBufferTail++;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* If ring buffer does not have enough data, still need to read more data. */
|
|
if (bytesToReceive)
|
|
{
|
|
/* No data in ring buffer, save the request to LPUART handle. */
|
|
handle->rxData = xfer->data + bytesCurrentReceived;
|
|
handle->rxDataSize = bytesToReceive;
|
|
handle->rxDataSizeAll = bytesToReceive;
|
|
handle->rxState = kLPUART_RxBusy;
|
|
}
|
|
/* Enable LPUART RX IRQ if previously enabled. */
|
|
LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
|
|
|
|
/* Call user callback since all data are received. */
|
|
if (0 == bytesToReceive)
|
|
{
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
|
|
}
|
|
}
|
|
}
|
|
/* Ring buffer not used. */
|
|
else
|
|
{
|
|
handle->rxData = xfer->data + bytesCurrentReceived;
|
|
handle->rxDataSize = bytesToReceive;
|
|
handle->rxDataSizeAll = bytesToReceive;
|
|
handle->rxState = kLPUART_RxBusy;
|
|
|
|
/* Enable RX interrupt. */
|
|
LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable |
|
|
kLPUART_IdleLineInterruptEnable);
|
|
}
|
|
|
|
/* Return the how many bytes have read. */
|
|
if (receivedBytes)
|
|
{
|
|
*receivedBytes = bytesCurrentReceived;
|
|
}
|
|
|
|
status = kStatus_Success;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
/* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
|
|
if (!handle->rxRingBuffer)
|
|
{
|
|
/* Disable RX interrupt. */
|
|
LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable |
|
|
kLPUART_IdleLineInterruptEnable);
|
|
}
|
|
|
|
handle->rxDataSize = 0U;
|
|
handle->rxState = kLPUART_RxIdle;
|
|
}
|
|
|
|
status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
|
|
{
|
|
assert(handle);
|
|
assert(count);
|
|
|
|
if (kLPUART_RxIdle == handle->rxState)
|
|
{
|
|
return kStatus_NoTransferInProgress;
|
|
}
|
|
|
|
*count = handle->rxDataSizeAll - handle->rxDataSize;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
uint8_t count;
|
|
uint8_t tempCount;
|
|
|
|
/* If RX overrun. */
|
|
if (LPUART_STAT_OR_MASK & base->STAT)
|
|
{
|
|
/* Clear overrun flag, otherwise the RX does not work. */
|
|
base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
|
|
|
|
/* Trigger callback. */
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData);
|
|
}
|
|
}
|
|
|
|
/* If IDLE flag is set and the IDLE interrupt is enabled. */
|
|
if ((LPUART_STAT_IDLE_MASK & base->STAT) && (LPUART_CTRL_ILIE_MASK & base->CTRL))
|
|
{
|
|
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
|
count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
|
|
|
|
while ((count) && (handle->rxDataSize))
|
|
{
|
|
tempCount = MIN(handle->rxDataSize, count);
|
|
|
|
/* Using non block API to read the data from the registers. */
|
|
LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
|
|
handle->rxData += tempCount;
|
|
handle->rxDataSize -= tempCount;
|
|
count -= tempCount;
|
|
|
|
/* If rxDataSize is 0, disable idle line interrupt.*/
|
|
if (!(handle->rxDataSize))
|
|
{
|
|
handle->rxState = kLPUART_RxIdle;
|
|
|
|
LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
/* Clear IDLE flag.*/
|
|
base->STAT |= LPUART_STAT_IDLE_MASK;
|
|
|
|
/* If rxDataSize is 0, disable idle line interrupt.*/
|
|
if (!(handle->rxDataSize))
|
|
{
|
|
LPUART_DisableInterrupts(base, kLPUART_IdleLineInterruptEnable);
|
|
}
|
|
/* If callback is not NULL and rxDataSize is not 0. */
|
|
if ((handle->callback) && (handle->rxDataSize))
|
|
{
|
|
handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData);
|
|
}
|
|
}
|
|
/* Receive data register full */
|
|
if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL))
|
|
{
|
|
/* Get the size that can be stored into buffer for this interrupt. */
|
|
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
|
count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
|
|
#else
|
|
count = 1;
|
|
#endif
|
|
|
|
/* If handle->rxDataSize is not 0, first save data to handle->rxData. */
|
|
while ((count) && (handle->rxDataSize))
|
|
{
|
|
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
|
tempCount = MIN(handle->rxDataSize, count);
|
|
#else
|
|
tempCount = 1;
|
|
#endif
|
|
|
|
/* Using non block API to read the data from the registers. */
|
|
LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
|
|
handle->rxData += tempCount;
|
|
handle->rxDataSize -= tempCount;
|
|
count -= tempCount;
|
|
|
|
/* If all the data required for upper layer is ready, trigger callback. */
|
|
if (!handle->rxDataSize)
|
|
{
|
|
handle->rxState = kLPUART_RxIdle;
|
|
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* If use RX ring buffer, receive data to ring buffer. */
|
|
if (handle->rxRingBuffer)
|
|
{
|
|
while (count--)
|
|
{
|
|
/* If RX ring buffer is full, trigger callback to notify over run. */
|
|
if (LPUART_TransferIsRxRingBufferFull(base, handle))
|
|
{
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData);
|
|
}
|
|
}
|
|
|
|
/* If ring buffer is still full after callback function, the oldest data is overrided. */
|
|
if (LPUART_TransferIsRxRingBufferFull(base, handle))
|
|
{
|
|
/* Increase handle->rxRingBufferTail to make room for new data. */
|
|
if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
|
|
{
|
|
handle->rxRingBufferTail = 0U;
|
|
}
|
|
else
|
|
{
|
|
handle->rxRingBufferTail++;
|
|
}
|
|
}
|
|
|
|
/* Read data. */
|
|
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
|
|
if (handle->isSevenDataBits)
|
|
{
|
|
handle->rxRingBuffer[handle->rxRingBufferHead] = (base->DATA & 0x7F);
|
|
}
|
|
else
|
|
{
|
|
handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
|
|
}
|
|
#else
|
|
handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
|
|
#endif
|
|
|
|
/* Increase handle->rxRingBufferHead. */
|
|
if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
|
|
{
|
|
handle->rxRingBufferHead = 0U;
|
|
}
|
|
else
|
|
{
|
|
handle->rxRingBufferHead++;
|
|
}
|
|
}
|
|
}
|
|
/* If no receive requst pending, stop RX interrupt. */
|
|
else if (!handle->rxDataSize)
|
|
{
|
|
LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
|
|
}
|
|
else
|
|
{
|
|
}
|
|
}
|
|
|
|
/* Send data register empty and the interrupt is enabled. */
|
|
if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK))
|
|
{
|
|
/* Get the bytes that available at this moment. */
|
|
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
|
count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) -
|
|
((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
|
|
#else
|
|
count = 1;
|
|
#endif
|
|
|
|
while ((count) && (handle->txDataSize))
|
|
{
|
|
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
|
tempCount = MIN(handle->txDataSize, count);
|
|
#else
|
|
tempCount = 1;
|
|
#endif
|
|
|
|
/* Using non block API to write the data to the registers. */
|
|
LPUART_WriteNonBlocking(base, handle->txData, tempCount);
|
|
handle->txData += tempCount;
|
|
handle->txDataSize -= tempCount;
|
|
count -= tempCount;
|
|
|
|
/* If all the data are written to data register, notify user with the callback, then TX finished. */
|
|
if (!handle->txDataSize)
|
|
{
|
|
handle->txState = kLPUART_TxIdle;
|
|
|
|
/* Disable TX register empty interrupt. */
|
|
base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK);
|
|
|
|
/* Trigger callback. */
|
|
if (handle->callback)
|
|
{
|
|
handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle)
|
|
{
|
|
/* To be implemented by User. */
|
|
}
|
|
#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1
|
|
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
|
|
void LPUART0_LPUART1_RX_DriverIRQHandler(void)
|
|
{
|
|
if (CLOCK_isEnabledClock(s_lpuartClock[0]))
|
|
{
|
|
if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
|
|
((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)))
|
|
{
|
|
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
|
|
}
|
|
}
|
|
if (CLOCK_isEnabledClock(s_lpuartClock[1]))
|
|
{
|
|
if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
|
|
((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)))
|
|
{
|
|
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
|
|
}
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
void LPUART0_LPUART1_TX_DriverIRQHandler(void)
|
|
{
|
|
if (CLOCK_isEnabledClock(s_lpuartClock[0]))
|
|
{
|
|
if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
|
|
((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK)))
|
|
{
|
|
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
|
|
}
|
|
}
|
|
if (CLOCK_isEnabledClock(s_lpuartClock[1]))
|
|
{
|
|
if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
|
|
((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK)))
|
|
{
|
|
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
|
|
}
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#else
|
|
void LPUART0_LPUART1_DriverIRQHandler(void)
|
|
{
|
|
if (CLOCK_isEnabledClock(s_lpuartClock[0]))
|
|
{
|
|
if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
|
|
((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)) ||
|
|
((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK)))
|
|
{
|
|
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
|
|
}
|
|
}
|
|
if (CLOCK_isEnabledClock(s_lpuartClock[1]))
|
|
{
|
|
if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
|
|
((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)) ||
|
|
((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK)))
|
|
{
|
|
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
|
|
}
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(LPUART0)
|
|
#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
|
|
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
|
|
void LPUART0_TX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
void LPUART0_RX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#else
|
|
void LPUART0_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(LPUART1)
|
|
#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
|
|
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
|
|
void LPUART1_TX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
void LPUART1_RX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#else
|
|
void LPUART1_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(LPUART2)
|
|
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
|
|
void LPUART2_TX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
void LPUART2_RX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#else
|
|
void LPUART2_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(LPUART3)
|
|
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
|
|
void LPUART3_TX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
void LPUART3_RX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#else
|
|
void LPUART3_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(LPUART4)
|
|
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
|
|
void LPUART4_TX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
void LPUART4_RX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#else
|
|
void LPUART4_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(LPUART5)
|
|
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
|
|
void LPUART5_TX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
void LPUART5_RX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#else
|
|
void LPUART5_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(LPUART6)
|
|
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
|
|
void LPUART6_TX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART6, s_lpuartHandle[6]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
void LPUART6_RX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART6, s_lpuartHandle[6]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#else
|
|
void LPUART6_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART6, s_lpuartHandle[6]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(LPUART7)
|
|
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
|
|
void LPUART7_TX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART7, s_lpuartHandle[7]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
void LPUART7_RX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART7, s_lpuartHandle[7]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#else
|
|
void LPUART7_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART7, s_lpuartHandle[7]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(LPUART8)
|
|
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
|
|
void LPUART8_TX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART8, s_lpuartHandle[8]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
void LPUART8_RX_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART8, s_lpuartHandle[8]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#else
|
|
void LPUART8_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(LPUART8, s_lpuartHandle[8]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CM4_0__LPUART)
|
|
void M4_0_LPUART_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(CM4_0__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0__LPUART)]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if defined(CM4_1__LPUART)
|
|
void M4_1_LPUART_DriverIRQHandler(void)
|
|
{
|
|
s_lpuartIsr(CM4_1__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1__LPUART)]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if defined(DMA__LPUART0)
|
|
void DMA_UART0_INT_IRQHandler(void)
|
|
{
|
|
s_lpuartIsr(DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if defined(DMA__LPUART1)
|
|
void DMA_UART1_INT_IRQHandler(void)
|
|
{
|
|
s_lpuartIsr(DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if defined(DMA__LPUART2)
|
|
void DMA_UART2_INT_IRQHandler(void)
|
|
{
|
|
s_lpuartIsr(DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if defined(DMA__LPUART3)
|
|
void DMA_UART3_INT_IRQHandler(void)
|
|
{
|
|
s_lpuartIsr(DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if defined(DMA__LPUART4)
|
|
void DMA_UART4_INT_IRQHandler(void)
|
|
{
|
|
s_lpuartIsr(DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|